/* Generated by Yosys 0.9+4008 (git sha1 049e3abf, ccache clang 9.0.1-12 -O0 -O3 -DNDEBUG -fPIC) */

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:5.1-335.10" *)
module ALU_dec19(ALU_dec19_function_unit, ALU_dec19_internal_op, ALU_dec19_in1_sel, ALU_dec19_in2_sel, ALU_dec19_cr_in, ALU_dec19_cr_out, ALU_dec19_ldst_len, ALU_dec19_rc_sel, ALU_dec19_cry_in, ALU_dec19_inv_a, ALU_dec19_inv_out, ALU_dec19_cry_out, ALU_dec19_is_32b, ALU_dec19_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:284.3-293.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:294.3-303.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:324.3-333.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:224.3-233.6" *)
  reg _03_;
  (* src = "libresoc.v:194.3-203.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:264.3-273.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:274.3-283.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:254.3-263.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:204.3-213.6" *)
  reg _08_;
  (* src = "libresoc.v:214.3-223.6" *)
  reg _09_;
  (* src = "libresoc.v:234.3-243.6" *)
  reg _10_;
  (* src = "libresoc.v:304.3-313.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:314.3-323.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:244.3-253.6" *)
  reg _13_;
  (* src = "libresoc.v:6.7-6.20" *)
  reg _14_;
  (* src = "libresoc.v:284.3-293.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:294.3-303.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:324.3-333.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:224.3-233.6" *)
  reg _18_;
  (* src = "libresoc.v:194.3-203.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:264.3-273.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:274.3-283.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:254.3-263.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:204.3-213.6" *)
  reg _23_;
  (* src = "libresoc.v:214.3-223.6" *)
  reg _24_;
  (* src = "libresoc.v:234.3-243.6" *)
  reg _25_;
  (* src = "libresoc.v:304.3-313.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:314.3-323.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:244.3-253.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec19_cr_in;
  reg [2:0] ALU_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec19_cr_out;
  reg [2:0] ALU_dec19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec19_cry_in;
  reg [1:0] ALU_dec19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec19_cry_out;
  reg ALU_dec19_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec19_function_unit;
  reg [13:0] ALU_dec19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec19_in1_sel;
  reg [2:0] ALU_dec19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec19_in2_sel;
  reg [3:0] ALU_dec19_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec19_internal_op;
  reg [6:0] ALU_dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec19_inv_a;
  reg ALU_dec19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec19_inv_out;
  reg ALU_dec19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec19_is_32b;
  reg ALU_dec19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec19_ldst_len;
  reg [3:0] ALU_dec19_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec19_rc_sel;
  reg [1:0] ALU_dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec19_sgn;
  reg ALU_dec19_sgn;
  (* src = "libresoc.v:6.7-6.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:195.5-195.29" *)
    casez (\initial )
      /* src = "libresoc.v:195.9-195.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec19_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:205.5-205.29" *)
    casez (\initial )
      /* src = "libresoc.v:205.9-205.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec19_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:215.5-215.29" *)
    casez (\initial )
      /* src = "libresoc.v:215.9-215.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec19_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:225.5-225.29" *)
    casez (\initial )
      /* src = "libresoc.v:225.9-225.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec19_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:235.5-235.29" *)
    casez (\initial )
      /* src = "libresoc.v:235.9-235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec19_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:245.5-245.29" *)
    casez (\initial )
      /* src = "libresoc.v:245.9-245.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec19_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:255.5-255.29" *)
    casez (\initial )
      /* src = "libresoc.v:255.9-255.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _22_ = 7'h24;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec19_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:265.5-265.29" *)
    casez (\initial )
      /* src = "libresoc.v:265.9-265.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _20_ = 3'h0;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec19_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:275.5-275.29" *)
    casez (\initial )
      /* src = "libresoc.v:275.9-275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec19_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:285.5-285.29" *)
    casez (\initial )
      /* src = "libresoc.v:285.9-285.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec19_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:295.5-295.29" *)
    casez (\initial )
      /* src = "libresoc.v:295.9-295.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec19_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:305.5-305.29" *)
    casez (\initial )
      /* src = "libresoc.v:305.9-305.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec19_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:315.5-315.29" *)
    casez (\initial )
      /* src = "libresoc.v:315.9-315.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec19_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:325.5-325.29" *)
    casez (\initial )
      /* src = "libresoc.v:325.9-325.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec19_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:339.1-1785.10" *)
module ALU_dec31(ALU_dec31_function_unit, ALU_dec31_internal_op, ALU_dec31_in1_sel, ALU_dec31_in2_sel, ALU_dec31_cr_in, ALU_dec31_cr_out, ALU_dec31_ldst_len, ALU_dec31_rc_sel, ALU_dec31_cry_in, ALU_dec31_inv_a, ALU_dec31_inv_out, ALU_dec31_cry_out, ALU_dec31_is_32b, ALU_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:1492.3-1513.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:1514.3-1535.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:1580.3-1601.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:1646.3-1667.6" *)
  reg _03_;
  (* src = "libresoc.v:1712.3-1733.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:1756.3-1777.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:1470.3-1491.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:1734.3-1755.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:1602.3-1623.6" *)
  reg _08_;
  (* src = "libresoc.v:1624.3-1645.6" *)
  reg _09_;
  (* src = "libresoc.v:1668.3-1689.6" *)
  reg _10_;
  (* src = "libresoc.v:1536.3-1557.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:1558.3-1579.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:1690.3-1711.6" *)
  reg _13_;
  (* src = "libresoc.v:340.7-340.20" *)
  reg _14_;
  (* src = "libresoc.v:1492.3-1513.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:1514.3-1535.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:1580.3-1601.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:1646.3-1667.6" *)
  reg _18_;
  (* src = "libresoc.v:1712.3-1733.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:1756.3-1777.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:1470.3-1491.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:1734.3-1755.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:1602.3-1623.6" *)
  reg _23_;
  (* src = "libresoc.v:1624.3-1645.6" *)
  reg _24_;
  (* src = "libresoc.v:1668.3-1689.6" *)
  reg _25_;
  (* src = "libresoc.v:1536.3-1557.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:1558.3-1579.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:1690.3-1711.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_cr_in;
  reg [2:0] ALU_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_cr_out;
  reg [2:0] ALU_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_cry_in;
  reg [1:0] ALU_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_cry_out;
  reg ALU_dec31_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_dec_sub0_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_dec_sub10_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_dec_sub22_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_dec_sub26_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_dec_sub8_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_function_unit;
  reg [13:0] ALU_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_in1_sel;
  reg [2:0] ALU_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_in2_sel;
  reg [3:0] ALU_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_internal_op;
  reg [6:0] ALU_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_inv_a;
  reg ALU_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_inv_out;
  reg ALU_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_is_32b;
  reg ALU_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_ldst_len;
  reg [3:0] ALU_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_rc_sel;
  reg [1:0] ALU_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_sgn;
  reg ALU_dec31_sgn;
  (* src = "libresoc.v:340.7-340.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:1385.22-1401.4" *)
  ALU_dec31_dec_sub0 ALU_dec31_dec_sub0 (
    .ALU_dec31_dec_sub0_cr_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in),
    .ALU_dec31_dec_sub0_cr_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out),
    .ALU_dec31_dec_sub0_cry_in(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in),
    .ALU_dec31_dec_sub0_cry_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out),
    .ALU_dec31_dec_sub0_function_unit(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit),
    .ALU_dec31_dec_sub0_in1_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel),
    .ALU_dec31_dec_sub0_in2_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel),
    .ALU_dec31_dec_sub0_internal_op(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op),
    .ALU_dec31_dec_sub0_inv_a(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a),
    .ALU_dec31_dec_sub0_inv_out(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out),
    .ALU_dec31_dec_sub0_is_32b(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b),
    .ALU_dec31_dec_sub0_ldst_len(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len),
    .ALU_dec31_dec_sub0_rc_sel(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel),
    .ALU_dec31_dec_sub0_sgn(ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn),
    .opcode_in(ALU_dec31_dec_sub0_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:1402.23-1418.4" *)
  ALU_dec31_dec_sub10 ALU_dec31_dec_sub10 (
    .ALU_dec31_dec_sub10_cr_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in),
    .ALU_dec31_dec_sub10_cr_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out),
    .ALU_dec31_dec_sub10_cry_in(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in),
    .ALU_dec31_dec_sub10_cry_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out),
    .ALU_dec31_dec_sub10_function_unit(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit),
    .ALU_dec31_dec_sub10_in1_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel),
    .ALU_dec31_dec_sub10_in2_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel),
    .ALU_dec31_dec_sub10_internal_op(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op),
    .ALU_dec31_dec_sub10_inv_a(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a),
    .ALU_dec31_dec_sub10_inv_out(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out),
    .ALU_dec31_dec_sub10_is_32b(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b),
    .ALU_dec31_dec_sub10_ldst_len(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len),
    .ALU_dec31_dec_sub10_rc_sel(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel),
    .ALU_dec31_dec_sub10_sgn(ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn),
    .opcode_in(ALU_dec31_dec_sub10_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:1419.23-1435.4" *)
  ALU_dec31_dec_sub22 ALU_dec31_dec_sub22 (
    .ALU_dec31_dec_sub22_cr_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in),
    .ALU_dec31_dec_sub22_cr_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out),
    .ALU_dec31_dec_sub22_cry_in(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in),
    .ALU_dec31_dec_sub22_cry_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out),
    .ALU_dec31_dec_sub22_function_unit(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit),
    .ALU_dec31_dec_sub22_in1_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel),
    .ALU_dec31_dec_sub22_in2_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel),
    .ALU_dec31_dec_sub22_internal_op(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op),
    .ALU_dec31_dec_sub22_inv_a(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a),
    .ALU_dec31_dec_sub22_inv_out(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out),
    .ALU_dec31_dec_sub22_is_32b(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b),
    .ALU_dec31_dec_sub22_ldst_len(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len),
    .ALU_dec31_dec_sub22_rc_sel(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel),
    .ALU_dec31_dec_sub22_sgn(ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn),
    .opcode_in(ALU_dec31_dec_sub22_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:1436.23-1452.4" *)
  ALU_dec31_dec_sub26 ALU_dec31_dec_sub26 (
    .ALU_dec31_dec_sub26_cr_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in),
    .ALU_dec31_dec_sub26_cr_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out),
    .ALU_dec31_dec_sub26_cry_in(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in),
    .ALU_dec31_dec_sub26_cry_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out),
    .ALU_dec31_dec_sub26_function_unit(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit),
    .ALU_dec31_dec_sub26_in1_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel),
    .ALU_dec31_dec_sub26_in2_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel),
    .ALU_dec31_dec_sub26_internal_op(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op),
    .ALU_dec31_dec_sub26_inv_a(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a),
    .ALU_dec31_dec_sub26_inv_out(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out),
    .ALU_dec31_dec_sub26_is_32b(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b),
    .ALU_dec31_dec_sub26_ldst_len(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len),
    .ALU_dec31_dec_sub26_rc_sel(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel),
    .ALU_dec31_dec_sub26_sgn(ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn),
    .opcode_in(ALU_dec31_dec_sub26_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:1453.22-1469.4" *)
  ALU_dec31_dec_sub8 ALU_dec31_dec_sub8 (
    .ALU_dec31_dec_sub8_cr_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in),
    .ALU_dec31_dec_sub8_cr_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out),
    .ALU_dec31_dec_sub8_cry_in(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in),
    .ALU_dec31_dec_sub8_cry_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out),
    .ALU_dec31_dec_sub8_function_unit(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit),
    .ALU_dec31_dec_sub8_in1_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel),
    .ALU_dec31_dec_sub8_in2_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel),
    .ALU_dec31_dec_sub8_internal_op(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op),
    .ALU_dec31_dec_sub8_inv_a(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a),
    .ALU_dec31_dec_sub8_inv_out(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out),
    .ALU_dec31_dec_sub8_is_32b(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b),
    .ALU_dec31_dec_sub8_ldst_len(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len),
    .ALU_dec31_dec_sub8_rc_sel(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel),
    .ALU_dec31_dec_sub8_sgn(ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn),
    .opcode_in(ALU_dec31_dec_sub8_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:1471.5-1471.29" *)
    casez (\initial )
      /* src = "libresoc.v:1471.9-1471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _21_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _21_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _21_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:1493.5-1493.29" *)
    casez (\initial )
      /* src = "libresoc.v:1493.9-1493.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _15_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _15_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _15_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:1515.5-1515.29" *)
    casez (\initial )
      /* src = "libresoc.v:1515.9-1515.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _16_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _16_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _16_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:1537.5-1537.29" *)
    casez (\initial )
      /* src = "libresoc.v:1537.9-1537.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _26_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _26_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _26_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:1559.5-1559.29" *)
    casez (\initial )
      /* src = "libresoc.v:1559.9-1559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _27_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _27_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _27_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:1581.5-1581.29" *)
    casez (\initial )
      /* src = "libresoc.v:1581.9-1581.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _17_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _17_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _17_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:1603.5-1603.29" *)
    casez (\initial )
      /* src = "libresoc.v:1603.9-1603.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _23_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _23_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _23_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:1625.5-1625.29" *)
    casez (\initial )
      /* src = "libresoc.v:1625.9-1625.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _24_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _24_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _24_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:1647.5-1647.29" *)
    casez (\initial )
      /* src = "libresoc.v:1647.9-1647.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _18_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _18_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _18_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:1669.5-1669.29" *)
    casez (\initial )
      /* src = "libresoc.v:1669.9-1669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _25_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _25_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _25_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:1691.5-1691.29" *)
    casez (\initial )
      /* src = "libresoc.v:1691.9-1691.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _28_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _28_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _28_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:1713.5-1713.29" *)
    casez (\initial )
      /* src = "libresoc.v:1713.9-1713.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _19_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _19_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _19_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:1735.5-1735.29" *)
    casez (\initial )
      /* src = "libresoc.v:1735.9-1735.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _22_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _22_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _22_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:1757.5-1757.29" *)
    casez (\initial )
      /* src = "libresoc.v:1757.9-1757.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _20_ = ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _20_ = ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _20_ = ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  assign ALU_dec31_dec_sub8_opcode_in = opcode_in;
  assign ALU_dec31_dec_sub22_opcode_in = opcode_in;
  assign ALU_dec31_dec_sub26_opcode_in = opcode_in;
  assign ALU_dec31_dec_sub0_opcode_in = opcode_in;
  assign ALU_dec31_dec_sub10_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:1789.1-2203.10" *)
module ALU_dec31_dec_sub0(ALU_dec31_dec_sub0_function_unit, ALU_dec31_dec_sub0_internal_op, ALU_dec31_dec_sub0_in1_sel, ALU_dec31_dec_sub0_in2_sel, ALU_dec31_dec_sub0_cr_in, ALU_dec31_dec_sub0_cr_out, ALU_dec31_dec_sub0_ldst_len, ALU_dec31_dec_sub0_rc_sel, ALU_dec31_dec_sub0_cry_in, ALU_dec31_dec_sub0_inv_a, ALU_dec31_dec_sub0_inv_out, ALU_dec31_dec_sub0_cry_out, ALU_dec31_dec_sub0_is_32b, ALU_dec31_dec_sub0_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:2122.3-2137.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:2138.3-2153.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:2186.3-2201.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:2026.3-2041.6" *)
  reg _03_;
  (* src = "libresoc.v:1978.3-1993.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:2090.3-2105.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:2106.3-2121.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:2074.3-2089.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:1994.3-2009.6" *)
  reg _08_;
  (* src = "libresoc.v:2010.3-2025.6" *)
  reg _09_;
  (* src = "libresoc.v:2042.3-2057.6" *)
  reg _10_;
  (* src = "libresoc.v:2154.3-2169.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:2170.3-2185.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:2058.3-2073.6" *)
  reg _13_;
  (* src = "libresoc.v:1790.7-1790.20" *)
  reg _14_;
  (* src = "libresoc.v:2122.3-2137.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:2138.3-2153.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:2186.3-2201.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:2026.3-2041.6" *)
  reg _18_;
  (* src = "libresoc.v:1978.3-1993.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:2090.3-2105.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:2106.3-2121.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:2074.3-2089.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:1994.3-2009.6" *)
  reg _23_;
  (* src = "libresoc.v:2010.3-2025.6" *)
  reg _24_;
  (* src = "libresoc.v:2042.3-2057.6" *)
  reg _25_;
  (* src = "libresoc.v:2154.3-2169.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:2170.3-2185.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:2058.3-2073.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub0_cr_in;
  reg [2:0] ALU_dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub0_cr_out;
  reg [2:0] ALU_dec31_dec_sub0_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub0_cry_in;
  reg [1:0] ALU_dec31_dec_sub0_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub0_cry_out;
  reg ALU_dec31_dec_sub0_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_dec_sub0_function_unit;
  reg [13:0] ALU_dec31_dec_sub0_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub0_in1_sel;
  reg [2:0] ALU_dec31_dec_sub0_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub0_in2_sel;
  reg [3:0] ALU_dec31_dec_sub0_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_dec_sub0_internal_op;
  reg [6:0] ALU_dec31_dec_sub0_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub0_inv_a;
  reg ALU_dec31_dec_sub0_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub0_inv_out;
  reg ALU_dec31_dec_sub0_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub0_is_32b;
  reg ALU_dec31_dec_sub0_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub0_ldst_len;
  reg [3:0] ALU_dec31_dec_sub0_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub0_rc_sel;
  reg [1:0] ALU_dec31_dec_sub0_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub0_sgn;
  reg ALU_dec31_dec_sub0_sgn;
  (* src = "libresoc.v:1790.7-1790.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:1979.5-1979.29" *)
    casez (\initial )
      /* src = "libresoc.v:1979.9-1979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:1995.5-1995.29" *)
    casez (\initial )
      /* src = "libresoc.v:1995.9-1995.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 1'h1;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:2011.5-2011.29" *)
    casez (\initial )
      /* src = "libresoc.v:2011.9-2011.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:2027.5-2027.29" *)
    casez (\initial )
      /* src = "libresoc.v:2027.9-2027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:2043.5-2043.29" *)
    casez (\initial )
      /* src = "libresoc.v:2043.9-2043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:2059.5-2059.29" *)
    casez (\initial )
      /* src = "libresoc.v:2059.9-2059.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:2075.5-2075.29" *)
    casez (\initial )
      /* src = "libresoc.v:2075.9-2075.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 7'h0c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 7'h0a;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:2091.5-2091.29" *)
    casez (\initial )
      /* src = "libresoc.v:2091.9-2091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:2107.5-2107.29" *)
    casez (\initial )
      /* src = "libresoc.v:2107.9-2107.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 4'h1;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:2123.5-2123.29" *)
    casez (\initial )
      /* src = "libresoc.v:2123.9-2123.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:2139.5-2139.29" *)
    casez (\initial )
      /* src = "libresoc.v:2139.9-2139.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h2;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:2155.5-2155.29" *)
    casez (\initial )
      /* src = "libresoc.v:2155.9-2155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:2171.5-2171.29" *)
    casez (\initial )
      /* src = "libresoc.v:2171.9-2171.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:2187.5-2187.29" *)
    casez (\initial )
      /* src = "libresoc.v:2187.9-2187.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 2'h1;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub0_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:2207.1-2915.10" *)
module ALU_dec31_dec_sub10(ALU_dec31_dec_sub10_function_unit, ALU_dec31_dec_sub10_internal_op, ALU_dec31_dec_sub10_in1_sel, ALU_dec31_dec_sub10_in2_sel, ALU_dec31_dec_sub10_cr_in, ALU_dec31_dec_sub10_cr_out, ALU_dec31_dec_sub10_ldst_len, ALU_dec31_dec_sub10_rc_sel, ALU_dec31_dec_sub10_cry_in, ALU_dec31_dec_sub10_inv_a, ALU_dec31_dec_sub10_inv_out, ALU_dec31_dec_sub10_cry_out, ALU_dec31_dec_sub10_is_32b, ALU_dec31_dec_sub10_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:2729.3-2765.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:2766.3-2802.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:2877.3-2913.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:2507.3-2543.6" *)
  reg _03_;
  (* src = "libresoc.v:2396.3-2432.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:2655.3-2691.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:2692.3-2728.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:2618.3-2654.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:2433.3-2469.6" *)
  reg _08_;
  (* src = "libresoc.v:2470.3-2506.6" *)
  reg _09_;
  (* src = "libresoc.v:2544.3-2580.6" *)
  reg _10_;
  (* src = "libresoc.v:2803.3-2839.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:2840.3-2876.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:2581.3-2617.6" *)
  reg _13_;
  (* src = "libresoc.v:2208.7-2208.20" *)
  reg _14_;
  (* src = "libresoc.v:2729.3-2765.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:2766.3-2802.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:2877.3-2913.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:2507.3-2543.6" *)
  reg _18_;
  (* src = "libresoc.v:2396.3-2432.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:2655.3-2691.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:2692.3-2728.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:2618.3-2654.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:2433.3-2469.6" *)
  reg _23_;
  (* src = "libresoc.v:2470.3-2506.6" *)
  reg _24_;
  (* src = "libresoc.v:2544.3-2580.6" *)
  reg _25_;
  (* src = "libresoc.v:2803.3-2839.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:2840.3-2876.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:2581.3-2617.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub10_cr_in;
  reg [2:0] ALU_dec31_dec_sub10_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub10_cr_out;
  reg [2:0] ALU_dec31_dec_sub10_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub10_cry_in;
  reg [1:0] ALU_dec31_dec_sub10_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub10_cry_out;
  reg ALU_dec31_dec_sub10_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_dec_sub10_function_unit;
  reg [13:0] ALU_dec31_dec_sub10_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub10_in1_sel;
  reg [2:0] ALU_dec31_dec_sub10_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub10_in2_sel;
  reg [3:0] ALU_dec31_dec_sub10_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_dec_sub10_internal_op;
  reg [6:0] ALU_dec31_dec_sub10_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub10_inv_a;
  reg ALU_dec31_dec_sub10_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub10_inv_out;
  reg ALU_dec31_dec_sub10_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub10_is_32b;
  reg ALU_dec31_dec_sub10_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub10_ldst_len;
  reg [3:0] ALU_dec31_dec_sub10_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub10_rc_sel;
  reg [1:0] ALU_dec31_dec_sub10_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub10_sgn;
  reg ALU_dec31_dec_sub10_sgn;
  (* src = "libresoc.v:2208.7-2208.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:2397.5-2397.29" *)
    casez (\initial )
      /* src = "libresoc.v:2397.9-2397.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:2434.5-2434.29" *)
    casez (\initial )
      /* src = "libresoc.v:2434.9-2434.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:2471.5-2471.29" *)
    casez (\initial )
      /* src = "libresoc.v:2471.9-2471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:2508.5-2508.29" *)
    casez (\initial )
      /* src = "libresoc.v:2508.9-2508.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _18_ = 1'h1;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:2545.5-2545.29" *)
    casez (\initial )
      /* src = "libresoc.v:2545.9-2545.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:2582.5-2582.29" *)
    casez (\initial )
      /* src = "libresoc.v:2582.9-2582.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:2619.5-2619.29" *)
    casez (\initial )
      /* src = "libresoc.v:2619.9-2619.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _22_ = 7'h02;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:2656.5-2656.29" *)
    casez (\initial )
      /* src = "libresoc.v:2656.9-2656.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:2693.5-2693.29" *)
    casez (\initial )
      /* src = "libresoc.v:2693.9-2693.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _21_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:2730.5-2730.29" *)
    casez (\initial )
      /* src = "libresoc.v:2730.9-2730.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:2767.5-2767.29" *)
    casez (\initial )
      /* src = "libresoc.v:2767.9-2767.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _16_ = 3'h1;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:2804.5-2804.29" *)
    casez (\initial )
      /* src = "libresoc.v:2804.9-2804.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:2841.5-2841.29" *)
    casez (\initial )
      /* src = "libresoc.v:2841.9-2841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _27_ = 2'h2;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:2878.5-2878.29" *)
    casez (\initial )
      /* src = "libresoc.v:2878.9-2878.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _17_ = 2'h2;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub10_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:2919.1-3501.10" *)
module ALU_dec31_dec_sub22(ALU_dec31_dec_sub22_function_unit, ALU_dec31_dec_sub22_internal_op, ALU_dec31_dec_sub22_in1_sel, ALU_dec31_dec_sub22_in2_sel, ALU_dec31_dec_sub22_cr_in, ALU_dec31_dec_sub22_cr_out, ALU_dec31_dec_sub22_ldst_len, ALU_dec31_dec_sub22_rc_sel, ALU_dec31_dec_sub22_cry_in, ALU_dec31_dec_sub22_inv_a, ALU_dec31_dec_sub22_inv_out, ALU_dec31_dec_sub22_cry_out, ALU_dec31_dec_sub22_is_32b, ALU_dec31_dec_sub22_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:3360.3-3387.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:3388.3-3415.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:3472.3-3499.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:3192.3-3219.6" *)
  reg _03_;
  (* src = "libresoc.v:3108.3-3135.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:3304.3-3331.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:3332.3-3359.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:3276.3-3303.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:3136.3-3163.6" *)
  reg _08_;
  (* src = "libresoc.v:3164.3-3191.6" *)
  reg _09_;
  (* src = "libresoc.v:3220.3-3247.6" *)
  reg _10_;
  (* src = "libresoc.v:3416.3-3443.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:3444.3-3471.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:3248.3-3275.6" *)
  reg _13_;
  (* src = "libresoc.v:2920.7-2920.20" *)
  reg _14_;
  (* src = "libresoc.v:3360.3-3387.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:3388.3-3415.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:3472.3-3499.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:3192.3-3219.6" *)
  reg _18_;
  (* src = "libresoc.v:3108.3-3135.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:3304.3-3331.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:3332.3-3359.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:3276.3-3303.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:3136.3-3163.6" *)
  reg _23_;
  (* src = "libresoc.v:3164.3-3191.6" *)
  reg _24_;
  (* src = "libresoc.v:3220.3-3247.6" *)
  reg _25_;
  (* src = "libresoc.v:3416.3-3443.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:3444.3-3471.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:3248.3-3275.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub22_cr_in;
  reg [2:0] ALU_dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub22_cr_out;
  reg [2:0] ALU_dec31_dec_sub22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub22_cry_in;
  reg [1:0] ALU_dec31_dec_sub22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub22_cry_out;
  reg ALU_dec31_dec_sub22_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_dec_sub22_function_unit;
  reg [13:0] ALU_dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub22_in1_sel;
  reg [2:0] ALU_dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub22_in2_sel;
  reg [3:0] ALU_dec31_dec_sub22_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_dec_sub22_internal_op;
  reg [6:0] ALU_dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub22_inv_a;
  reg ALU_dec31_dec_sub22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub22_inv_out;
  reg ALU_dec31_dec_sub22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub22_is_32b;
  reg ALU_dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub22_ldst_len;
  reg [3:0] ALU_dec31_dec_sub22_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub22_rc_sel;
  reg [1:0] ALU_dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub22_sgn;
  reg ALU_dec31_dec_sub22_sgn;
  (* src = "libresoc.v:2920.7-2920.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:3109.5-3109.29" *)
    casez (\initial )
      /* src = "libresoc.v:3109.9-3109.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:3137.5-3137.29" *)
    casez (\initial )
      /* src = "libresoc.v:3137.9-3137.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:3165.5-3165.29" *)
    casez (\initial )
      /* src = "libresoc.v:3165.9-3165.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:3193.5-3193.29" *)
    casez (\initial )
      /* src = "libresoc.v:3193.9-3193.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:3221.5-3221.29" *)
    casez (\initial )
      /* src = "libresoc.v:3221.9-3221.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:3249.5-3249.29" *)
    casez (\initial )
      /* src = "libresoc.v:3249.9-3249.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:3277.5-3277.29" *)
    casez (\initial )
      /* src = "libresoc.v:3277.9-3277.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _22_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _22_ = 7'h21;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _22_ = 7'h01;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:3305.5-3305.29" *)
    casez (\initial )
      /* src = "libresoc.v:3305.9-3305.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _20_ = 3'h0;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:3333.5-3333.29" *)
    casez (\initial )
      /* src = "libresoc.v:3333.9-3333.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:3361.5-3361.29" *)
    casez (\initial )
      /* src = "libresoc.v:3361.9-3361.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:3389.5-3389.29" *)
    casez (\initial )
      /* src = "libresoc.v:3389.9-3389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:3417.5-3417.29" *)
    casez (\initial )
      /* src = "libresoc.v:3417.9-3417.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:3445.5-3445.29" *)
    casez (\initial )
      /* src = "libresoc.v:3445.9-3445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:3473.5-3473.29" *)
    casez (\initial )
      /* src = "libresoc.v:3473.9-3473.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub22_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:3505.1-3919.10" *)
module ALU_dec31_dec_sub26(ALU_dec31_dec_sub26_function_unit, ALU_dec31_dec_sub26_internal_op, ALU_dec31_dec_sub26_in1_sel, ALU_dec31_dec_sub26_in2_sel, ALU_dec31_dec_sub26_cr_in, ALU_dec31_dec_sub26_cr_out, ALU_dec31_dec_sub26_ldst_len, ALU_dec31_dec_sub26_rc_sel, ALU_dec31_dec_sub26_cry_in, ALU_dec31_dec_sub26_inv_a, ALU_dec31_dec_sub26_inv_out, ALU_dec31_dec_sub26_cry_out, ALU_dec31_dec_sub26_is_32b, ALU_dec31_dec_sub26_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:3838.3-3853.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:3854.3-3869.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:3902.3-3917.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:3742.3-3757.6" *)
  reg _03_;
  (* src = "libresoc.v:3694.3-3709.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:3806.3-3821.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:3822.3-3837.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:3790.3-3805.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:3710.3-3725.6" *)
  reg _08_;
  (* src = "libresoc.v:3726.3-3741.6" *)
  reg _09_;
  (* src = "libresoc.v:3758.3-3773.6" *)
  reg _10_;
  (* src = "libresoc.v:3870.3-3885.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:3886.3-3901.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:3774.3-3789.6" *)
  reg _13_;
  (* src = "libresoc.v:3506.7-3506.20" *)
  reg _14_;
  (* src = "libresoc.v:3838.3-3853.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:3854.3-3869.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:3902.3-3917.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:3742.3-3757.6" *)
  reg _18_;
  (* src = "libresoc.v:3694.3-3709.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:3806.3-3821.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:3822.3-3837.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:3790.3-3805.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:3710.3-3725.6" *)
  reg _23_;
  (* src = "libresoc.v:3726.3-3741.6" *)
  reg _24_;
  (* src = "libresoc.v:3758.3-3773.6" *)
  reg _25_;
  (* src = "libresoc.v:3870.3-3885.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:3886.3-3901.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:3774.3-3789.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub26_cr_in;
  reg [2:0] ALU_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub26_cr_out;
  reg [2:0] ALU_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub26_cry_in;
  reg [1:0] ALU_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub26_cry_out;
  reg ALU_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_dec_sub26_function_unit;
  reg [13:0] ALU_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub26_in1_sel;
  reg [2:0] ALU_dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub26_in2_sel;
  reg [3:0] ALU_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_dec_sub26_internal_op;
  reg [6:0] ALU_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub26_inv_a;
  reg ALU_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub26_inv_out;
  reg ALU_dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub26_is_32b;
  reg ALU_dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub26_ldst_len;
  reg [3:0] ALU_dec31_dec_sub26_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub26_rc_sel;
  reg [1:0] ALU_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub26_sgn;
  reg ALU_dec31_dec_sub26_sgn;
  (* src = "libresoc.v:3506.7-3506.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:3695.5-3695.29" *)
    casez (\initial )
      /* src = "libresoc.v:3695.9-3695.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:3711.5-3711.29" *)
    casez (\initial )
      /* src = "libresoc.v:3711.9-3711.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:3727.5-3727.29" *)
    casez (\initial )
      /* src = "libresoc.v:3727.9-3727.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:3743.5-3743.29" *)
    casez (\initial )
      /* src = "libresoc.v:3743.9-3743.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:3759.5-3759.29" *)
    casez (\initial )
      /* src = "libresoc.v:3759.9-3759.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:3775.5-3775.29" *)
    casez (\initial )
      /* src = "libresoc.v:3775.9-3775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:3791.5-3791.29" *)
    casez (\initial )
      /* src = "libresoc.v:3791.9-3791.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _22_ = 7'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = 7'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _22_ = 7'h1f;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:3807.5-3807.29" *)
    casez (\initial )
      /* src = "libresoc.v:3807.9-3807.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _20_ = 3'h4;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:3823.5-3823.29" *)
    casez (\initial )
      /* src = "libresoc.v:3823.9-3823.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:3839.5-3839.29" *)
    casez (\initial )
      /* src = "libresoc.v:3839.9-3839.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:3855.5-3855.29" *)
    casez (\initial )
      /* src = "libresoc.v:3855.9-3855.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _16_ = 3'h1;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:3871.5-3871.29" *)
    casez (\initial )
      /* src = "libresoc.v:3871.9-3871.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _26_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _26_ = 4'h4;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:3887.5-3887.29" *)
    casez (\initial )
      /* src = "libresoc.v:3887.9-3887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _27_ = 2'h2;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:3903.5-3903.29" *)
    casez (\initial )
      /* src = "libresoc.v:3903.9-3903.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub26_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:3923.1-4715.10" *)
module ALU_dec31_dec_sub8(ALU_dec31_dec_sub8_function_unit, ALU_dec31_dec_sub8_internal_op, ALU_dec31_dec_sub8_in1_sel, ALU_dec31_dec_sub8_in2_sel, ALU_dec31_dec_sub8_cr_in, ALU_dec31_dec_sub8_cr_out, ALU_dec31_dec_sub8_ldst_len, ALU_dec31_dec_sub8_rc_sel, ALU_dec31_dec_sub8_cry_in, ALU_dec31_dec_sub8_inv_a, ALU_dec31_dec_sub8_inv_out, ALU_dec31_dec_sub8_cry_out, ALU_dec31_dec_sub8_is_32b, ALU_dec31_dec_sub8_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:4499.3-4541.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:4542.3-4584.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:4671.3-4713.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:4241.3-4283.6" *)
  reg _03_;
  (* src = "libresoc.v:4112.3-4154.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:4413.3-4455.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:4456.3-4498.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:4370.3-4412.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:4155.3-4197.6" *)
  reg _08_;
  (* src = "libresoc.v:4198.3-4240.6" *)
  reg _09_;
  (* src = "libresoc.v:4284.3-4326.6" *)
  reg _10_;
  (* src = "libresoc.v:4585.3-4627.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:4628.3-4670.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:4327.3-4369.6" *)
  reg _13_;
  (* src = "libresoc.v:3924.7-3924.20" *)
  reg _14_;
  (* src = "libresoc.v:4499.3-4541.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:4542.3-4584.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:4671.3-4713.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:4241.3-4283.6" *)
  reg _18_;
  (* src = "libresoc.v:4112.3-4154.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:4413.3-4455.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:4456.3-4498.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:4370.3-4412.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:4155.3-4197.6" *)
  reg _23_;
  (* src = "libresoc.v:4198.3-4240.6" *)
  reg _24_;
  (* src = "libresoc.v:4284.3-4326.6" *)
  reg _25_;
  (* src = "libresoc.v:4585.3-4627.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:4628.3-4670.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:4327.3-4369.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub8_cr_in;
  reg [2:0] ALU_dec31_dec_sub8_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub8_cr_out;
  reg [2:0] ALU_dec31_dec_sub8_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub8_cry_in;
  reg [1:0] ALU_dec31_dec_sub8_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub8_cry_out;
  reg ALU_dec31_dec_sub8_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_dec31_dec_sub8_function_unit;
  reg [13:0] ALU_dec31_dec_sub8_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_dec31_dec_sub8_in1_sel;
  reg [2:0] ALU_dec31_dec_sub8_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub8_in2_sel;
  reg [3:0] ALU_dec31_dec_sub8_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_dec31_dec_sub8_internal_op;
  reg [6:0] ALU_dec31_dec_sub8_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub8_inv_a;
  reg ALU_dec31_dec_sub8_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub8_inv_out;
  reg ALU_dec31_dec_sub8_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub8_is_32b;
  reg ALU_dec31_dec_sub8_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_dec31_dec_sub8_ldst_len;
  reg [3:0] ALU_dec31_dec_sub8_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_dec31_dec_sub8_rc_sel;
  reg [1:0] ALU_dec31_dec_sub8_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_dec31_dec_sub8_sgn;
  reg ALU_dec31_dec_sub8_sgn;
  (* src = "libresoc.v:3924.7-3924.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:4113.5-4113.29" *)
    casez (\initial )
      /* src = "libresoc.v:4113.9-4113.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:4156.5-4156.29" *)
    casez (\initial )
      /* src = "libresoc.v:4156.9-4156.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _23_ = 1'h1;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:4199.5-4199.29" *)
    casez (\initial )
      /* src = "libresoc.v:4199.9-4199.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:4242.5-4242.29" *)
    casez (\initial )
      /* src = "libresoc.v:4242.9-4242.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _18_ = 1'h1;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:4285.5-4285.29" *)
    casez (\initial )
      /* src = "libresoc.v:4285.9-4285.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:4328.5-4328.29" *)
    casez (\initial )
      /* src = "libresoc.v:4328.9-4328.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:4371.5-4371.29" *)
    casez (\initial )
      /* src = "libresoc.v:4371.9-4371.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _22_ = 7'h02;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:4414.5-4414.29" *)
    casez (\initial )
      /* src = "libresoc.v:4414.9-4414.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:4457.5-4457.29" *)
    casez (\initial )
      /* src = "libresoc.v:4457.9-4457.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _21_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:4500.5-4500.29" *)
    casez (\initial )
      /* src = "libresoc.v:4500.9-4500.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:4543.5-4543.29" *)
    casez (\initial )
      /* src = "libresoc.v:4543.9-4543.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _16_ = 3'h1;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:4586.5-4586.29" *)
    casez (\initial )
      /* src = "libresoc.v:4586.9-4586.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:4629.5-4629.29" *)
    casez (\initial )
      /* src = "libresoc.v:4629.9-4629.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _27_ = 2'h2;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:4672.5-4672.29" *)
    casez (\initial )
      /* src = "libresoc.v:4672.9-4672.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _17_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _17_ = 2'h2;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_dec31_dec_sub8_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH.dec.BRANCH_dec19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:4719.1-5003.10" *)
module BRANCH_dec19(BRANCH_dec19_function_unit, BRANCH_dec19_internal_op, BRANCH_dec19_in2_sel, BRANCH_dec19_cr_in, BRANCH_dec19_cr_out, BRANCH_dec19_rc_sel, BRANCH_dec19_is_32b, BRANCH_dec19_lk, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:4922.3-4937.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:4938.3-4953.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:4874.3-4889.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:4906.3-4921.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:4890.3-4905.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:4970.3-4985.6" *)
  reg _05_;
  (* src = "libresoc.v:4986.3-5001.6" *)
  reg _06_;
  (* src = "libresoc.v:4954.3-4969.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:4720.7-4720.20" *)
  reg _08_;
  (* src = "libresoc.v:4922.3-4937.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:4938.3-4953.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:4874.3-4889.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:4906.3-4921.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:4890.3-4905.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:4970.3-4985.6" *)
  reg _14_;
  (* src = "libresoc.v:4986.3-5001.6" *)
  reg _15_;
  (* src = "libresoc.v:4954.3-4969.6" *)
  reg [1:0] _16_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] BRANCH_dec19_cr_in;
  reg [2:0] BRANCH_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] BRANCH_dec19_cr_out;
  reg [2:0] BRANCH_dec19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] BRANCH_dec19_function_unit;
  reg [13:0] BRANCH_dec19_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] BRANCH_dec19_in2_sel;
  reg [3:0] BRANCH_dec19_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] BRANCH_dec19_internal_op;
  reg [6:0] BRANCH_dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output BRANCH_dec19_is_32b;
  reg BRANCH_dec19_is_32b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output BRANCH_dec19_lk;
  reg BRANCH_dec19_lk;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] BRANCH_dec19_rc_sel;
  reg [1:0] BRANCH_dec19_rc_sel;
  (* src = "libresoc.v:4720.7-4720.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:4875.5-4875.29" *)
    casez (\initial )
      /* src = "libresoc.v:4875.9-4875.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _11_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _11_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _11_ = 14'h0020;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      BRANCH_dec19_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:4891.5-4891.29" *)
    casez (\initial )
      /* src = "libresoc.v:4891.9-4891.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _13_ = 7'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _13_ = 7'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _13_ = 7'h08;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      BRANCH_dec19_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:4907.5-4907.29" *)
    casez (\initial )
      /* src = "libresoc.v:4907.9-4907.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _12_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _12_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _12_ = 4'hc;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:4923.5-4923.29" *)
    casez (\initial )
      /* src = "libresoc.v:4923.9-4923.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _09_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _09_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _09_ = 3'h2;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:4939.5-4939.29" *)
    casez (\initial )
      /* src = "libresoc.v:4939.9-4939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _10_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _10_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _10_ = 3'h0;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:4955.5-4955.29" *)
    casez (\initial )
      /* src = "libresoc.v:4955.9-4955.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _16_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _16_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _16_ = 2'h0;
        end
      default:
          _16_ = 2'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_rc_sel <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:4971.5-4971.29" *)
    casez (\initial )
      /* src = "libresoc.v:4971.9-4971.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:4987.5-4987.29" *)
    casez (\initial )
      /* src = "libresoc.v:4987.9-4987.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _15_ = 1'h1;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      BRANCH_dec19_lk <= _06_;
  end
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:5007.1-5309.10" *)
module CR_dec19(CR_dec19_function_unit, CR_dec19_internal_op, CR_dec19_cr_in, CR_dec19_cr_out, CR_dec19_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:5206.3-5239.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:5240.3-5273.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:5138.3-5171.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:5172.3-5205.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:5274.3-5307.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:5008.7-5008.20" *)
  reg _05_;
  (* src = "libresoc.v:5206.3-5239.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:5240.3-5273.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:5138.3-5171.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:5172.3-5205.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:5274.3-5307.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec19_cr_in;
  reg [2:0] CR_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec19_cr_out;
  reg [2:0] CR_dec19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec19_function_unit;
  reg [13:0] CR_dec19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec19_internal_op;
  reg [6:0] CR_dec19_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec19_rc_sel;
  reg [1:0] CR_dec19_rc_sel;
  (* src = "libresoc.v:5008.7-5008.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:5139.5-5139.29" *)
    casez (\initial )
      /* src = "libresoc.v:5139.9-5139.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _08_ = 14'h0040;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec19_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:5173.5-5173.29" *)
    casez (\initial )
      /* src = "libresoc.v:5173.9-5173.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _09_ = 7'h2a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _09_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _09_ = 7'h45;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec19_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:5207.5-5207.29" *)
    casez (\initial )
      /* src = "libresoc.v:5207.9-5207.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _06_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _06_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _06_ = 3'h4;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec19_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:5241.5-5241.29" *)
    casez (\initial )
      /* src = "libresoc.v:5241.9-5241.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _07_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _07_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _07_ = 3'h3;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec19_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:5275.5-5275.29" *)
    casez (\initial )
      /* src = "libresoc.v:5275.9-5275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _10_ = 2'h0;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec19_rc_sel <= _04_;
  end
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:5313.1-6067.10" *)
module CR_dec31(CR_dec31_function_unit, CR_dec31_internal_op, CR_dec31_cr_in, CR_dec31_cr_out, CR_dec31_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:6023.3-6041.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:6042.3-6060.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:5985.3-6003.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:6004.3-6022.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:5966.3-5984.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:5314.7-5314.20" *)
  reg _05_;
  (* src = "libresoc.v:6023.3-6041.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:6042.3-6060.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:5985.3-6003.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:6004.3-6022.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:5966.3-5984.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_cr_in;
  reg [2:0] CR_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_cr_out;
  reg [2:0] CR_dec31_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec31_dec_sub0_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec31_dec_sub15_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec31_dec_sub16_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec31_dec_sub19_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec31_function_unit;
  reg [13:0] CR_dec31_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec31_internal_op;
  reg [6:0] CR_dec31_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec31_rc_sel;
  reg [1:0] CR_dec31_rc_sel;
  (* src = "libresoc.v:5314.7-5314.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:5934.21-5941.4" *)
  CR_dec31_dec_sub0 CR_dec31_dec_sub0 (
    .CR_dec31_dec_sub0_cr_in(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in),
    .CR_dec31_dec_sub0_cr_out(CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out),
    .CR_dec31_dec_sub0_function_unit(CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit),
    .CR_dec31_dec_sub0_internal_op(CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op),
    .CR_dec31_dec_sub0_rc_sel(CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel),
    .opcode_in(CR_dec31_dec_sub0_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:5942.22-5949.4" *)
  CR_dec31_dec_sub15 CR_dec31_dec_sub15 (
    .CR_dec31_dec_sub15_cr_in(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in),
    .CR_dec31_dec_sub15_cr_out(CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out),
    .CR_dec31_dec_sub15_function_unit(CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit),
    .CR_dec31_dec_sub15_internal_op(CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op),
    .CR_dec31_dec_sub15_rc_sel(CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel),
    .opcode_in(CR_dec31_dec_sub15_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:5950.22-5957.4" *)
  CR_dec31_dec_sub16 CR_dec31_dec_sub16 (
    .CR_dec31_dec_sub16_cr_in(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in),
    .CR_dec31_dec_sub16_cr_out(CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out),
    .CR_dec31_dec_sub16_function_unit(CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit),
    .CR_dec31_dec_sub16_internal_op(CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op),
    .CR_dec31_dec_sub16_rc_sel(CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel),
    .opcode_in(CR_dec31_dec_sub16_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:5958.22-5965.4" *)
  CR_dec31_dec_sub19 CR_dec31_dec_sub19 (
    .CR_dec31_dec_sub19_cr_in(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in),
    .CR_dec31_dec_sub19_cr_out(CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out),
    .CR_dec31_dec_sub19_function_unit(CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit),
    .CR_dec31_dec_sub19_internal_op(CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op),
    .CR_dec31_dec_sub19_rc_sel(CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel),
    .opcode_in(CR_dec31_dec_sub19_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:5967.5-5967.29" *)
    casez (\initial )
      /* src = "libresoc.v:5967.9-5967.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _10_ = CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _10_ = CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _10_ = CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _10_ = CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec31_rc_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:5986.5-5986.29" *)
    casez (\initial )
      /* src = "libresoc.v:5986.9-5986.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _08_ = CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _08_ = CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _08_ = CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _08_ = CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec31_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:6005.5-6005.29" *)
    casez (\initial )
      /* src = "libresoc.v:6005.9-6005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _09_ = CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _09_ = CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _09_ = CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _09_ = CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec31_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:6024.5-6024.29" *)
    casez (\initial )
      /* src = "libresoc.v:6024.9-6024.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _06_ = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _06_ = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _06_ = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _06_ = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:6043.5-6043.29" *)
    casez (\initial )
      /* src = "libresoc.v:6043.9-6043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _07_ = CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _07_ = CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _07_ = CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _07_ = CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_cr_out <= _01_;
  end
  assign CR_dec31_dec_sub16_opcode_in = opcode_in;
  assign CR_dec31_dec_sub15_opcode_in = opcode_in;
  assign CR_dec31_dec_sub19_opcode_in = opcode_in;
  assign CR_dec31_dec_sub0_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:6071.1-6253.10" *)
module CR_dec31_dec_sub0(CR_dec31_dec_sub0_function_unit, CR_dec31_dec_sub0_internal_op, CR_dec31_dec_sub0_cr_in, CR_dec31_dec_sub0_cr_out, CR_dec31_dec_sub0_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:6222.3-6231.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:6232.3-6241.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:6202.3-6211.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:6212.3-6221.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:6242.3-6251.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:6072.7-6072.20" *)
  reg _05_;
  (* src = "libresoc.v:6222.3-6231.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:6232.3-6241.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:6202.3-6211.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:6212.3-6221.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:6242.3-6251.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub0_cr_in;
  reg [2:0] CR_dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub0_cr_out;
  reg [2:0] CR_dec31_dec_sub0_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec31_dec_sub0_function_unit;
  reg [13:0] CR_dec31_dec_sub0_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec31_dec_sub0_internal_op;
  reg [6:0] CR_dec31_dec_sub0_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec31_dec_sub0_rc_sel;
  reg [1:0] CR_dec31_dec_sub0_rc_sel;
  (* src = "libresoc.v:6072.7-6072.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:6203.5-6203.29" *)
    casez (\initial )
      /* src = "libresoc.v:6203.9-6203.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _08_ = 14'h0040;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub0_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:6213.5-6213.29" *)
    casez (\initial )
      /* src = "libresoc.v:6213.9-6213.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _09_ = 7'h3b;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub0_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:6223.5-6223.29" *)
    casez (\initial )
      /* src = "libresoc.v:6223.9-6223.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _06_ = 3'h3;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub0_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:6233.5-6233.29" *)
    casez (\initial )
      /* src = "libresoc.v:6233.9-6233.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _07_ = 3'h0;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub0_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:6243.5-6243.29" *)
    casez (\initial )
      /* src = "libresoc.v:6243.9-6243.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _10_ = 2'h0;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub0_rc_sel <= _04_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:6257.1-6904.10" *)
module CR_dec31_dec_sub15(CR_dec31_dec_sub15_function_unit, CR_dec31_dec_sub15_internal_op, CR_dec31_dec_sub15_cr_in, CR_dec31_dec_sub15_cr_out, CR_dec31_dec_sub15_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:6594.3-6696.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:6697.3-6799.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:6388.3-6490.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:6491.3-6593.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:6800.3-6902.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:6258.7-6258.20" *)
  reg _05_;
  (* src = "libresoc.v:6594.3-6696.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:6697.3-6799.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:6388.3-6490.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:6491.3-6593.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:6800.3-6902.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub15_cr_in;
  reg [2:0] CR_dec31_dec_sub15_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub15_cr_out;
  reg [2:0] CR_dec31_dec_sub15_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec31_dec_sub15_function_unit;
  reg [13:0] CR_dec31_dec_sub15_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec31_dec_sub15_internal_op;
  reg [6:0] CR_dec31_dec_sub15_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec31_dec_sub15_rc_sel;
  reg [1:0] CR_dec31_dec_sub15_rc_sel;
  (* src = "libresoc.v:6258.7-6258.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:6389.5-6389.29" *)
    casez (\initial )
      /* src = "libresoc.v:6389.9-6389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _08_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _08_ = 14'h0040;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub15_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:6492.5-6492.29" *)
    casez (\initial )
      /* src = "libresoc.v:6492.9-6492.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _09_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _09_ = 7'h23;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub15_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:6595.5-6595.29" *)
    casez (\initial )
      /* src = "libresoc.v:6595.9-6595.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _06_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _06_ = 3'h5;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub15_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:6698.5-6698.29" *)
    casez (\initial )
      /* src = "libresoc.v:6698.9-6698.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _07_ = 3'h0;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub15_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:6801.5-6801.29" *)
    casez (\initial )
      /* src = "libresoc.v:6801.9-6801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _10_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _10_ = 2'h0;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub15_rc_sel <= _04_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:6908.1-7090.10" *)
module CR_dec31_dec_sub16(CR_dec31_dec_sub16_function_unit, CR_dec31_dec_sub16_internal_op, CR_dec31_dec_sub16_cr_in, CR_dec31_dec_sub16_cr_out, CR_dec31_dec_sub16_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:7059.3-7068.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:7069.3-7078.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:7039.3-7048.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:7049.3-7058.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:7079.3-7088.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:6909.7-6909.20" *)
  reg _05_;
  (* src = "libresoc.v:7059.3-7068.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:7069.3-7078.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:7039.3-7048.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:7049.3-7058.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:7079.3-7088.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub16_cr_in;
  reg [2:0] CR_dec31_dec_sub16_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub16_cr_out;
  reg [2:0] CR_dec31_dec_sub16_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec31_dec_sub16_function_unit;
  reg [13:0] CR_dec31_dec_sub16_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec31_dec_sub16_internal_op;
  reg [6:0] CR_dec31_dec_sub16_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec31_dec_sub16_rc_sel;
  reg [1:0] CR_dec31_dec_sub16_rc_sel;
  (* src = "libresoc.v:6909.7-6909.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:7040.5-7040.29" *)
    casez (\initial )
      /* src = "libresoc.v:7040.9-7040.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _08_ = 14'h0040;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub16_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:7050.5-7050.29" *)
    casez (\initial )
      /* src = "libresoc.v:7050.9-7050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _09_ = 7'h30;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub16_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:7060.5-7060.29" *)
    casez (\initial )
      /* src = "libresoc.v:7060.9-7060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _06_ = 3'h6;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub16_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:7070.5-7070.29" *)
    casez (\initial )
      /* src = "libresoc.v:7070.9-7070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _07_ = 3'h4;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub16_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:7080.5-7080.29" *)
    casez (\initial )
      /* src = "libresoc.v:7080.9-7080.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _10_ = 2'h0;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub16_rc_sel <= _04_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:7094.1-7276.10" *)
module CR_dec31_dec_sub19(CR_dec31_dec_sub19_function_unit, CR_dec31_dec_sub19_internal_op, CR_dec31_dec_sub19_cr_in, CR_dec31_dec_sub19_cr_out, CR_dec31_dec_sub19_rc_sel, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:7245.3-7254.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:7255.3-7264.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:7225.3-7234.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:7235.3-7244.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:7265.3-7274.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:7095.7-7095.20" *)
  reg _05_;
  (* src = "libresoc.v:7245.3-7254.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:7255.3-7264.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:7225.3-7234.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:7235.3-7244.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:7265.3-7274.6" *)
  reg [1:0] _10_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub19_cr_in;
  reg [2:0] CR_dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_dec31_dec_sub19_cr_out;
  reg [2:0] CR_dec31_dec_sub19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_dec31_dec_sub19_function_unit;
  reg [13:0] CR_dec31_dec_sub19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_dec31_dec_sub19_internal_op;
  reg [6:0] CR_dec31_dec_sub19_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_dec31_dec_sub19_rc_sel;
  reg [1:0] CR_dec31_dec_sub19_rc_sel;
  (* src = "libresoc.v:7095.7-7095.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:7226.5-7226.29" *)
    casez (\initial )
      /* src = "libresoc.v:7226.9-7226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _08_ = 14'h0040;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub19_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:7236.5-7236.29" *)
    casez (\initial )
      /* src = "libresoc.v:7236.9-7236.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _09_ = 7'h2d;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub19_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:7246.5-7246.29" *)
    casez (\initial )
      /* src = "libresoc.v:7246.9-7246.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _06_ = 3'h6;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub19_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:7256.5-7256.29" *)
    casez (\initial )
      /* src = "libresoc.v:7256.9-7256.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _07_ = 3'h0;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub19_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:7266.5-7266.29" *)
    casez (\initial )
      /* src = "libresoc.v:7266.9-7266.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _10_ = 2'h0;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_dec31_dec_sub19_rc_sel <= _04_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:7280.1-8033.10" *)
module DIV_dec31(DIV_dec31_function_unit, DIV_dec31_internal_op, DIV_dec31_in1_sel, DIV_dec31_in2_sel, DIV_dec31_cr_in, DIV_dec31_cr_out, DIV_dec31_ldst_len, DIV_dec31_rc_sel, DIV_dec31_cry_in, DIV_dec31_inv_a, DIV_dec31_inv_out, DIV_dec31_cry_out, DIV_dec31_is_32b, DIV_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:8003.3-8015.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:8016.3-8028.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:7873.3-7885.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:7912.3-7924.6" *)
  reg _03_;
  (* src = "libresoc.v:7951.3-7963.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:7977.3-7989.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:7990.3-8002.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:7964.3-7976.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:7886.3-7898.6" *)
  reg _08_;
  (* src = "libresoc.v:7899.3-7911.6" *)
  reg _09_;
  (* src = "libresoc.v:7925.3-7937.6" *)
  reg _10_;
  (* src = "libresoc.v:7847.3-7859.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:7860.3-7872.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:7938.3-7950.6" *)
  reg _13_;
  (* src = "libresoc.v:7281.7-7281.20" *)
  reg _14_;
  (* src = "libresoc.v:8003.3-8015.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:8016.3-8028.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:7873.3-7885.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:7912.3-7924.6" *)
  reg _18_;
  (* src = "libresoc.v:7951.3-7963.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:7977.3-7989.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:7990.3-8002.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:7964.3-7976.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:7886.3-7898.6" *)
  reg _23_;
  (* src = "libresoc.v:7899.3-7911.6" *)
  reg _24_;
  (* src = "libresoc.v:7925.3-7937.6" *)
  reg _25_;
  (* src = "libresoc.v:7847.3-7859.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:7860.3-7872.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:7938.3-7950.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_cr_in;
  reg [2:0] DIV_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_cr_out;
  reg [2:0] DIV_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_cry_in;
  reg [1:0] DIV_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_cry_out;
  reg DIV_dec31_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] DIV_dec31_dec_sub11_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] DIV_dec31_dec_sub9_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] DIV_dec31_function_unit;
  reg [13:0] DIV_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_in1_sel;
  reg [2:0] DIV_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_in2_sel;
  reg [3:0] DIV_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] DIV_dec31_internal_op;
  reg [6:0] DIV_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_inv_a;
  reg DIV_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_inv_out;
  reg DIV_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_is_32b;
  reg DIV_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_ldst_len;
  reg [3:0] DIV_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_rc_sel;
  reg [1:0] DIV_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_sgn;
  reg DIV_dec31_sgn;
  (* src = "libresoc.v:7281.7-7281.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:7813.23-7829.4" *)
  DIV_dec31_dec_sub11 DIV_dec31_dec_sub11 (
    .DIV_dec31_dec_sub11_cr_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in),
    .DIV_dec31_dec_sub11_cr_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out),
    .DIV_dec31_dec_sub11_cry_in(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in),
    .DIV_dec31_dec_sub11_cry_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out),
    .DIV_dec31_dec_sub11_function_unit(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit),
    .DIV_dec31_dec_sub11_in1_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel),
    .DIV_dec31_dec_sub11_in2_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel),
    .DIV_dec31_dec_sub11_internal_op(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op),
    .DIV_dec31_dec_sub11_inv_a(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a),
    .DIV_dec31_dec_sub11_inv_out(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out),
    .DIV_dec31_dec_sub11_is_32b(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b),
    .DIV_dec31_dec_sub11_ldst_len(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len),
    .DIV_dec31_dec_sub11_rc_sel(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel),
    .DIV_dec31_dec_sub11_sgn(DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn),
    .opcode_in(DIV_dec31_dec_sub11_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:7830.22-7846.4" *)
  DIV_dec31_dec_sub9 DIV_dec31_dec_sub9 (
    .DIV_dec31_dec_sub9_cr_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in),
    .DIV_dec31_dec_sub9_cr_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out),
    .DIV_dec31_dec_sub9_cry_in(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in),
    .DIV_dec31_dec_sub9_cry_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out),
    .DIV_dec31_dec_sub9_function_unit(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit),
    .DIV_dec31_dec_sub9_in1_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel),
    .DIV_dec31_dec_sub9_in2_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel),
    .DIV_dec31_dec_sub9_internal_op(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op),
    .DIV_dec31_dec_sub9_inv_a(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a),
    .DIV_dec31_dec_sub9_inv_out(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out),
    .DIV_dec31_dec_sub9_is_32b(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b),
    .DIV_dec31_dec_sub9_ldst_len(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len),
    .DIV_dec31_dec_sub9_rc_sel(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel),
    .DIV_dec31_dec_sub9_sgn(DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn),
    .opcode_in(DIV_dec31_dec_sub9_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:7848.5-7848.29" *)
    casez (\initial )
      /* src = "libresoc.v:7848.9-7848.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _26_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _26_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:7861.5-7861.29" *)
    casez (\initial )
      /* src = "libresoc.v:7861.9-7861.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _27_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _27_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:7874.5-7874.29" *)
    casez (\initial )
      /* src = "libresoc.v:7874.9-7874.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _17_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _17_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:7887.5-7887.29" *)
    casez (\initial )
      /* src = "libresoc.v:7887.9-7887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _23_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _23_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:7900.5-7900.29" *)
    casez (\initial )
      /* src = "libresoc.v:7900.9-7900.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _24_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _24_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:7913.5-7913.29" *)
    casez (\initial )
      /* src = "libresoc.v:7913.9-7913.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _18_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _18_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:7926.5-7926.29" *)
    casez (\initial )
      /* src = "libresoc.v:7926.9-7926.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _25_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _25_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:7939.5-7939.29" *)
    casez (\initial )
      /* src = "libresoc.v:7939.9-7939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _28_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _28_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:7952.5-7952.29" *)
    casez (\initial )
      /* src = "libresoc.v:7952.9-7952.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _19_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _19_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      DIV_dec31_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:7965.5-7965.29" *)
    casez (\initial )
      /* src = "libresoc.v:7965.9-7965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _22_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _22_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      DIV_dec31_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:7978.5-7978.29" *)
    casez (\initial )
      /* src = "libresoc.v:7978.9-7978.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _20_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _20_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:7991.5-7991.29" *)
    casez (\initial )
      /* src = "libresoc.v:7991.9-7991.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _21_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _21_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:8004.5-8004.29" *)
    casez (\initial )
      /* src = "libresoc.v:8004.9-8004.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _15_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _15_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:8017.5-8017.29" *)
    casez (\initial )
      /* src = "libresoc.v:8017.9-8017.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _16_ = DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _16_ = DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_cr_out <= _01_;
  end
  assign DIV_dec31_dec_sub11_opcode_in = opcode_in;
  assign DIV_dec31_dec_sub9_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:8037.1-8745.10" *)
module DIV_dec31_dec_sub11(DIV_dec31_dec_sub11_function_unit, DIV_dec31_dec_sub11_internal_op, DIV_dec31_dec_sub11_in1_sel, DIV_dec31_dec_sub11_in2_sel, DIV_dec31_dec_sub11_cr_in, DIV_dec31_dec_sub11_cr_out, DIV_dec31_dec_sub11_ldst_len, DIV_dec31_dec_sub11_rc_sel, DIV_dec31_dec_sub11_cry_in, DIV_dec31_dec_sub11_inv_a, DIV_dec31_dec_sub11_inv_out, DIV_dec31_dec_sub11_cry_out, DIV_dec31_dec_sub11_is_32b, DIV_dec31_dec_sub11_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:8559.3-8595.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:8596.3-8632.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:8707.3-8743.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:8337.3-8373.6" *)
  reg _03_;
  (* src = "libresoc.v:8226.3-8262.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:8485.3-8521.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:8522.3-8558.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:8448.3-8484.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:8263.3-8299.6" *)
  reg _08_;
  (* src = "libresoc.v:8300.3-8336.6" *)
  reg _09_;
  (* src = "libresoc.v:8374.3-8410.6" *)
  reg _10_;
  (* src = "libresoc.v:8633.3-8669.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:8670.3-8706.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:8411.3-8447.6" *)
  reg _13_;
  (* src = "libresoc.v:8038.7-8038.20" *)
  reg _14_;
  (* src = "libresoc.v:8559.3-8595.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:8596.3-8632.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:8707.3-8743.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:8337.3-8373.6" *)
  reg _18_;
  (* src = "libresoc.v:8226.3-8262.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:8485.3-8521.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:8522.3-8558.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:8448.3-8484.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:8263.3-8299.6" *)
  reg _23_;
  (* src = "libresoc.v:8300.3-8336.6" *)
  reg _24_;
  (* src = "libresoc.v:8374.3-8410.6" *)
  reg _25_;
  (* src = "libresoc.v:8633.3-8669.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:8670.3-8706.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:8411.3-8447.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub11_cr_in;
  reg [2:0] DIV_dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub11_cr_out;
  reg [2:0] DIV_dec31_dec_sub11_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_dec_sub11_cry_in;
  reg [1:0] DIV_dec31_dec_sub11_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub11_cry_out;
  reg DIV_dec31_dec_sub11_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] DIV_dec31_dec_sub11_function_unit;
  reg [13:0] DIV_dec31_dec_sub11_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub11_in1_sel;
  reg [2:0] DIV_dec31_dec_sub11_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_dec_sub11_in2_sel;
  reg [3:0] DIV_dec31_dec_sub11_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] DIV_dec31_dec_sub11_internal_op;
  reg [6:0] DIV_dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub11_inv_a;
  reg DIV_dec31_dec_sub11_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub11_inv_out;
  reg DIV_dec31_dec_sub11_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub11_is_32b;
  reg DIV_dec31_dec_sub11_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_dec_sub11_ldst_len;
  reg [3:0] DIV_dec31_dec_sub11_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_dec_sub11_rc_sel;
  reg [1:0] DIV_dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub11_sgn;
  reg DIV_dec31_dec_sub11_sgn;
  (* src = "libresoc.v:8038.7-8038.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:8227.5-8227.29" *)
    casez (\initial )
      /* src = "libresoc.v:8227.9-8227.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 14'h0200;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:8264.5-8264.29" *)
    casez (\initial )
      /* src = "libresoc.v:8264.9-8264.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:8301.5-8301.29" *)
    casez (\initial )
      /* src = "libresoc.v:8301.9-8301.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:8338.5-8338.29" *)
    casez (\initial )
      /* src = "libresoc.v:8338.9-8338.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:8375.5-8375.29" *)
    casez (\initial )
      /* src = "libresoc.v:8375.9-8375.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _25_ = 1'h1;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:8412.5-8412.29" *)
    casez (\initial )
      /* src = "libresoc.v:8412.9-8412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _28_ = 1'h1;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:8449.5-8449.29" *)
    casez (\initial )
      /* src = "libresoc.v:8449.9-8449.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 7'h2f;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:8486.5-8486.29" *)
    casez (\initial )
      /* src = "libresoc.v:8486.9-8486.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:8523.5-8523.29" *)
    casez (\initial )
      /* src = "libresoc.v:8523.9-8523.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 4'h1;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:8560.5-8560.29" *)
    casez (\initial )
      /* src = "libresoc.v:8560.9-8560.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:8597.5-8597.29" *)
    casez (\initial )
      /* src = "libresoc.v:8597.9-8597.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:8634.5-8634.29" *)
    casez (\initial )
      /* src = "libresoc.v:8634.9-8634.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:8671.5-8671.29" *)
    casez (\initial )
      /* src = "libresoc.v:8671.9-8671.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:8708.5-8708.29" *)
    casez (\initial )
      /* src = "libresoc.v:8708.9-8708.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub11_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:8749.1-9457.10" *)
module DIV_dec31_dec_sub9(DIV_dec31_dec_sub9_function_unit, DIV_dec31_dec_sub9_internal_op, DIV_dec31_dec_sub9_in1_sel, DIV_dec31_dec_sub9_in2_sel, DIV_dec31_dec_sub9_cr_in, DIV_dec31_dec_sub9_cr_out, DIV_dec31_dec_sub9_ldst_len, DIV_dec31_dec_sub9_rc_sel, DIV_dec31_dec_sub9_cry_in, DIV_dec31_dec_sub9_inv_a, DIV_dec31_dec_sub9_inv_out, DIV_dec31_dec_sub9_cry_out, DIV_dec31_dec_sub9_is_32b, DIV_dec31_dec_sub9_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:9271.3-9307.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:9308.3-9344.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:9419.3-9455.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:9049.3-9085.6" *)
  reg _03_;
  (* src = "libresoc.v:8938.3-8974.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:9197.3-9233.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:9234.3-9270.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:9160.3-9196.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:8975.3-9011.6" *)
  reg _08_;
  (* src = "libresoc.v:9012.3-9048.6" *)
  reg _09_;
  (* src = "libresoc.v:9086.3-9122.6" *)
  reg _10_;
  (* src = "libresoc.v:9345.3-9381.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:9382.3-9418.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:9123.3-9159.6" *)
  reg _13_;
  (* src = "libresoc.v:8750.7-8750.20" *)
  reg _14_;
  (* src = "libresoc.v:9271.3-9307.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:9308.3-9344.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:9419.3-9455.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:9049.3-9085.6" *)
  reg _18_;
  (* src = "libresoc.v:8938.3-8974.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:9197.3-9233.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:9234.3-9270.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:9160.3-9196.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:8975.3-9011.6" *)
  reg _23_;
  (* src = "libresoc.v:9012.3-9048.6" *)
  reg _24_;
  (* src = "libresoc.v:9086.3-9122.6" *)
  reg _25_;
  (* src = "libresoc.v:9345.3-9381.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:9382.3-9418.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:9123.3-9159.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub9_cr_in;
  reg [2:0] DIV_dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub9_cr_out;
  reg [2:0] DIV_dec31_dec_sub9_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_dec_sub9_cry_in;
  reg [1:0] DIV_dec31_dec_sub9_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub9_cry_out;
  reg DIV_dec31_dec_sub9_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] DIV_dec31_dec_sub9_function_unit;
  reg [13:0] DIV_dec31_dec_sub9_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_dec31_dec_sub9_in1_sel;
  reg [2:0] DIV_dec31_dec_sub9_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_dec_sub9_in2_sel;
  reg [3:0] DIV_dec31_dec_sub9_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] DIV_dec31_dec_sub9_internal_op;
  reg [6:0] DIV_dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub9_inv_a;
  reg DIV_dec31_dec_sub9_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub9_inv_out;
  reg DIV_dec31_dec_sub9_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub9_is_32b;
  reg DIV_dec31_dec_sub9_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_dec31_dec_sub9_ldst_len;
  reg [3:0] DIV_dec31_dec_sub9_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_dec31_dec_sub9_rc_sel;
  reg [1:0] DIV_dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_dec31_dec_sub9_sgn;
  reg DIV_dec31_dec_sub9_sgn;
  (* src = "libresoc.v:8750.7-8750.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:8939.5-8939.29" *)
    casez (\initial )
      /* src = "libresoc.v:8939.9-8939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 14'h0200;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:8976.5-8976.29" *)
    casez (\initial )
      /* src = "libresoc.v:8976.9-8976.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:9013.5-9013.29" *)
    casez (\initial )
      /* src = "libresoc.v:9013.9-9013.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:9050.5-9050.29" *)
    casez (\initial )
      /* src = "libresoc.v:9050.9-9050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:9087.5-9087.29" *)
    casez (\initial )
      /* src = "libresoc.v:9087.9-9087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:9124.5-9124.29" *)
    casez (\initial )
      /* src = "libresoc.v:9124.9-9124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _28_ = 1'h1;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:9161.5-9161.29" *)
    casez (\initial )
      /* src = "libresoc.v:9161.9-9161.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _22_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _22_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 7'h2f;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:9198.5-9198.29" *)
    casez (\initial )
      /* src = "libresoc.v:9198.9-9198.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:9235.5-9235.29" *)
    casez (\initial )
      /* src = "libresoc.v:9235.9-9235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 4'h1;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:9272.5-9272.29" *)
    casez (\initial )
      /* src = "libresoc.v:9272.9-9272.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:9309.5-9309.29" *)
    casez (\initial )
      /* src = "libresoc.v:9309.9-9309.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:9346.5-9346.29" *)
    casez (\initial )
      /* src = "libresoc.v:9346.9-9346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:9383.5-9383.29" *)
    casez (\initial )
      /* src = "libresoc.v:9383.9-9383.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:9420.5-9420.29" *)
    casez (\initial )
      /* src = "libresoc.v:9420.9-9420.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_dec31_dec_sub9_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:9461.1-10647.10" *)
module LDST_dec31(LDST_dec31_function_unit, LDST_dec31_internal_op, LDST_dec31_in1_sel, LDST_dec31_in2_sel, LDST_dec31_cr_in, LDST_dec31_cr_out, LDST_dec31_ldst_len, LDST_dec31_upd, LDST_dec31_rc_sel, LDST_dec31_br, LDST_dec31_sgn_ext, LDST_dec31_is_32b, LDST_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:10489.3-10507.6" *)
  reg _00_;
  (* src = "libresoc.v:10394.3-10412.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:10413.3-10431.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:10565.3-10583.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:10603.3-10621.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:10622.3-10640.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:10584.3-10602.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:10527.3-10545.6" *)
  reg _07_;
  (* src = "libresoc.v:10432.3-10450.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:10470.3-10488.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:10546.3-10564.6" *)
  reg _10_;
  (* src = "libresoc.v:10508.3-10526.6" *)
  reg _11_;
  (* src = "libresoc.v:10451.3-10469.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:9462.7-9462.20" *)
  reg _13_;
  (* src = "libresoc.v:10489.3-10507.6" *)
  reg _14_;
  (* src = "libresoc.v:10394.3-10412.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:10413.3-10431.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:10565.3-10583.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:10603.3-10621.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:10622.3-10640.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:10584.3-10602.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:10527.3-10545.6" *)
  reg _21_;
  (* src = "libresoc.v:10432.3-10450.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:10470.3-10488.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:10546.3-10564.6" *)
  reg _24_;
  (* src = "libresoc.v:10508.3-10526.6" *)
  reg _25_;
  (* src = "libresoc.v:10451.3-10469.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_br;
  reg LDST_dec31_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_cr_in;
  reg [2:0] LDST_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_cr_out;
  reg [2:0] LDST_dec31_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec31_dec_sub20_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec31_dec_sub21_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec31_dec_sub22_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec31_dec_sub23_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec31_function_unit;
  reg [13:0] LDST_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_in1_sel;
  reg [2:0] LDST_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_in2_sel;
  reg [3:0] LDST_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec31_internal_op;
  reg [6:0] LDST_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_is_32b;
  reg LDST_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_ldst_len;
  reg [3:0] LDST_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_rc_sel;
  reg [1:0] LDST_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_sgn;
  reg LDST_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_sgn_ext;
  reg LDST_dec31_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_upd;
  reg [1:0] LDST_dec31_upd;
  (* src = "libresoc.v:9462.7-9462.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:10330.24-10345.4" *)
  LDST_dec31_dec_sub20 LDST_dec31_dec_sub20 (
    .LDST_dec31_dec_sub20_br(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br),
    .LDST_dec31_dec_sub20_cr_in(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in),
    .LDST_dec31_dec_sub20_cr_out(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out),
    .LDST_dec31_dec_sub20_function_unit(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit),
    .LDST_dec31_dec_sub20_in1_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel),
    .LDST_dec31_dec_sub20_in2_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel),
    .LDST_dec31_dec_sub20_internal_op(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op),
    .LDST_dec31_dec_sub20_is_32b(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b),
    .LDST_dec31_dec_sub20_ldst_len(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len),
    .LDST_dec31_dec_sub20_rc_sel(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel),
    .LDST_dec31_dec_sub20_sgn(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn),
    .LDST_dec31_dec_sub20_sgn_ext(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext),
    .LDST_dec31_dec_sub20_upd(LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd),
    .opcode_in(LDST_dec31_dec_sub20_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:10346.24-10361.4" *)
  LDST_dec31_dec_sub21 LDST_dec31_dec_sub21 (
    .LDST_dec31_dec_sub21_br(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br),
    .LDST_dec31_dec_sub21_cr_in(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in),
    .LDST_dec31_dec_sub21_cr_out(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out),
    .LDST_dec31_dec_sub21_function_unit(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit),
    .LDST_dec31_dec_sub21_in1_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel),
    .LDST_dec31_dec_sub21_in2_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel),
    .LDST_dec31_dec_sub21_internal_op(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op),
    .LDST_dec31_dec_sub21_is_32b(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b),
    .LDST_dec31_dec_sub21_ldst_len(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len),
    .LDST_dec31_dec_sub21_rc_sel(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel),
    .LDST_dec31_dec_sub21_sgn(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn),
    .LDST_dec31_dec_sub21_sgn_ext(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext),
    .LDST_dec31_dec_sub21_upd(LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd),
    .opcode_in(LDST_dec31_dec_sub21_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:10362.24-10377.4" *)
  LDST_dec31_dec_sub22 LDST_dec31_dec_sub22 (
    .LDST_dec31_dec_sub22_br(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br),
    .LDST_dec31_dec_sub22_cr_in(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in),
    .LDST_dec31_dec_sub22_cr_out(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out),
    .LDST_dec31_dec_sub22_function_unit(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit),
    .LDST_dec31_dec_sub22_in1_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel),
    .LDST_dec31_dec_sub22_in2_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel),
    .LDST_dec31_dec_sub22_internal_op(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op),
    .LDST_dec31_dec_sub22_is_32b(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b),
    .LDST_dec31_dec_sub22_ldst_len(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len),
    .LDST_dec31_dec_sub22_rc_sel(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel),
    .LDST_dec31_dec_sub22_sgn(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn),
    .LDST_dec31_dec_sub22_sgn_ext(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext),
    .LDST_dec31_dec_sub22_upd(LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd),
    .opcode_in(LDST_dec31_dec_sub22_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:10378.24-10393.4" *)
  LDST_dec31_dec_sub23 LDST_dec31_dec_sub23 (
    .LDST_dec31_dec_sub23_br(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br),
    .LDST_dec31_dec_sub23_cr_in(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in),
    .LDST_dec31_dec_sub23_cr_out(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out),
    .LDST_dec31_dec_sub23_function_unit(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit),
    .LDST_dec31_dec_sub23_in1_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel),
    .LDST_dec31_dec_sub23_in2_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel),
    .LDST_dec31_dec_sub23_internal_op(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op),
    .LDST_dec31_dec_sub23_is_32b(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b),
    .LDST_dec31_dec_sub23_ldst_len(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len),
    .LDST_dec31_dec_sub23_rc_sel(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel),
    .LDST_dec31_dec_sub23_sgn(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn),
    .LDST_dec31_dec_sub23_sgn_ext(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext),
    .LDST_dec31_dec_sub23_upd(LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd),
    .opcode_in(LDST_dec31_dec_sub23_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:10395.5-10395.29" *)
    casez (\initial )
      /* src = "libresoc.v:10395.9-10395.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _15_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _15_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _15_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _15_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:10414.5-10414.29" *)
    casez (\initial )
      /* src = "libresoc.v:10414.9-10414.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _16_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _16_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _16_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _16_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:10433.5-10433.29" *)
    casez (\initial )
      /* src = "libresoc.v:10433.9-10433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _22_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _22_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _22_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _22_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:10452.5-10452.29" *)
    casez (\initial )
      /* src = "libresoc.v:10452.9-10452.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _26_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _26_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _26_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _26_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:10471.5-10471.29" *)
    casez (\initial )
      /* src = "libresoc.v:10471.9-10471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _23_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _23_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _23_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _23_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:10490.5-10490.29" *)
    casez (\initial )
      /* src = "libresoc.v:10490.9-10490.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _14_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _14_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _14_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _14_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:10509.5-10509.29" *)
    casez (\initial )
      /* src = "libresoc.v:10509.9-10509.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _25_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _25_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _25_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _25_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:10528.5-10528.29" *)
    casez (\initial )
      /* src = "libresoc.v:10528.9-10528.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _21_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _21_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _21_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _21_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:10547.5-10547.29" *)
    casez (\initial )
      /* src = "libresoc.v:10547.9-10547.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _24_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _24_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _24_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _24_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:10566.5-10566.29" *)
    casez (\initial )
      /* src = "libresoc.v:10566.9-10566.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _17_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _17_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _17_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _17_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec31_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:10585.5-10585.29" *)
    casez (\initial )
      /* src = "libresoc.v:10585.9-10585.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _20_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _20_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _20_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _20_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec31_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:10604.5-10604.29" *)
    casez (\initial )
      /* src = "libresoc.v:10604.9-10604.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _18_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _18_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _18_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _18_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:10623.5-10623.29" *)
    casez (\initial )
      /* src = "libresoc.v:10623.9-10623.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _19_ = LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _19_ = LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _19_ = LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _19_ = LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  assign LDST_dec31_dec_sub23_opcode_in = opcode_in;
  assign LDST_dec31_dec_sub21_opcode_in = opcode_in;
  assign LDST_dec31_dec_sub20_opcode_in = opcode_in;
  assign LDST_dec31_dec_sub22_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:10651.1-11164.10" *)
module LDST_dec31_dec_sub20(LDST_dec31_dec_sub20_function_unit, LDST_dec31_dec_sub20_internal_op, LDST_dec31_dec_sub20_in1_sel, LDST_dec31_dec_sub20_in2_sel, LDST_dec31_dec_sub20_cr_in, LDST_dec31_dec_sub20_cr_out, LDST_dec31_dec_sub20_ldst_len, LDST_dec31_dec_sub20_upd, LDST_dec31_dec_sub20_rc_sel, LDST_dec31_dec_sub20_br, LDST_dec31_dec_sub20_sgn_ext, LDST_dec31_dec_sub20_is_32b, LDST_dec31_dec_sub20_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:10863.3-10887.6" *)
  reg _00_;
  (* src = "libresoc.v:11038.3-11062.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:11063.3-11087.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:10838.3-10862.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:10988.3-11012.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:11013.3-11037.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:10963.3-10987.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:10913.3-10937.6" *)
  reg _07_;
  (* src = "libresoc.v:11088.3-11112.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:11138.3-11162.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:10938.3-10962.6" *)
  reg _10_;
  (* src = "libresoc.v:10888.3-10912.6" *)
  reg _11_;
  (* src = "libresoc.v:11113.3-11137.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:10652.7-10652.20" *)
  reg _13_;
  (* src = "libresoc.v:10863.3-10887.6" *)
  reg _14_;
  (* src = "libresoc.v:11038.3-11062.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:11063.3-11087.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:10838.3-10862.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:10988.3-11012.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:11013.3-11037.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:10963.3-10987.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:10913.3-10937.6" *)
  reg _21_;
  (* src = "libresoc.v:11088.3-11112.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:11138.3-11162.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:10938.3-10962.6" *)
  reg _24_;
  (* src = "libresoc.v:10888.3-10912.6" *)
  reg _25_;
  (* src = "libresoc.v:11113.3-11137.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub20_br;
  reg LDST_dec31_dec_sub20_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub20_cr_in;
  reg [2:0] LDST_dec31_dec_sub20_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub20_cr_out;
  reg [2:0] LDST_dec31_dec_sub20_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec31_dec_sub20_function_unit;
  reg [13:0] LDST_dec31_dec_sub20_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub20_in1_sel;
  reg [2:0] LDST_dec31_dec_sub20_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub20_in2_sel;
  reg [3:0] LDST_dec31_dec_sub20_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec31_dec_sub20_internal_op;
  reg [6:0] LDST_dec31_dec_sub20_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub20_is_32b;
  reg LDST_dec31_dec_sub20_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub20_ldst_len;
  reg [3:0] LDST_dec31_dec_sub20_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub20_rc_sel;
  reg [1:0] LDST_dec31_dec_sub20_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub20_sgn;
  reg LDST_dec31_dec_sub20_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub20_sgn_ext;
  reg LDST_dec31_dec_sub20_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub20_upd;
  reg [1:0] LDST_dec31_dec_sub20_upd;
  (* src = "libresoc.v:10652.7-10652.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:10839.5-10839.29" *)
    casez (\initial )
      /* src = "libresoc.v:10839.9-10839.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:10864.5-10864.29" *)
    casez (\initial )
      /* src = "libresoc.v:10864.9-10864.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _14_ = 1'h1;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:10889.5-10889.29" *)
    casez (\initial )
      /* src = "libresoc.v:10889.9-10889.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:10914.5-10914.29" *)
    casez (\initial )
      /* src = "libresoc.v:10914.9-10914.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:10939.5-10939.29" *)
    casez (\initial )
      /* src = "libresoc.v:10939.9-10939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:10964.5-10964.29" *)
    casez (\initial )
      /* src = "libresoc.v:10964.9-10964.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:10989.5-10989.29" *)
    casez (\initial )
      /* src = "libresoc.v:10989.9-10989.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:11014.5-11014.29" *)
    casez (\initial )
      /* src = "libresoc.v:11014.9-11014.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _19_ = 4'h1;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:11039.5-11039.29" *)
    casez (\initial )
      /* src = "libresoc.v:11039.9-11039.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:11064.5-11064.29" *)
    casez (\initial )
      /* src = "libresoc.v:11064.9-11064.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:11089.5-11089.29" *)
    casez (\initial )
      /* src = "libresoc.v:11089.9-11089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _22_ = 4'h8;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:11114.5-11114.29" *)
    casez (\initial )
      /* src = "libresoc.v:11114.9-11114.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _26_ = 2'h0;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:11139.5-11139.29" *)
    casez (\initial )
      /* src = "libresoc.v:11139.9-11139.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub20_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:11168.1-11993.10" *)
module LDST_dec31_dec_sub21(LDST_dec31_dec_sub21_function_unit, LDST_dec31_dec_sub21_internal_op, LDST_dec31_dec_sub21_in1_sel, LDST_dec31_dec_sub21_in2_sel, LDST_dec31_dec_sub21_cr_in, LDST_dec31_dec_sub21_cr_out, LDST_dec31_dec_sub21_ldst_len, LDST_dec31_dec_sub21_upd, LDST_dec31_dec_sub21_rc_sel, LDST_dec31_dec_sub21_br, LDST_dec31_dec_sub21_sgn_ext, LDST_dec31_dec_sub21_is_32b, LDST_dec31_dec_sub21_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:11404.3-11452.6" *)
  reg _00_;
  (* src = "libresoc.v:11747.3-11795.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:11796.3-11844.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:11355.3-11403.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:11649.3-11697.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:11698.3-11746.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:11600.3-11648.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:11502.3-11550.6" *)
  reg _07_;
  (* src = "libresoc.v:11845.3-11893.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:11943.3-11991.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:11551.3-11599.6" *)
  reg _10_;
  (* src = "libresoc.v:11453.3-11501.6" *)
  reg _11_;
  (* src = "libresoc.v:11894.3-11942.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:11169.7-11169.20" *)
  reg _13_;
  (* src = "libresoc.v:11404.3-11452.6" *)
  reg _14_;
  (* src = "libresoc.v:11747.3-11795.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:11796.3-11844.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:11355.3-11403.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:11649.3-11697.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:11698.3-11746.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:11600.3-11648.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:11502.3-11550.6" *)
  reg _21_;
  (* src = "libresoc.v:11845.3-11893.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:11943.3-11991.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:11551.3-11599.6" *)
  reg _24_;
  (* src = "libresoc.v:11453.3-11501.6" *)
  reg _25_;
  (* src = "libresoc.v:11894.3-11942.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub21_br;
  reg LDST_dec31_dec_sub21_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub21_cr_in;
  reg [2:0] LDST_dec31_dec_sub21_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub21_cr_out;
  reg [2:0] LDST_dec31_dec_sub21_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec31_dec_sub21_function_unit;
  reg [13:0] LDST_dec31_dec_sub21_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub21_in1_sel;
  reg [2:0] LDST_dec31_dec_sub21_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub21_in2_sel;
  reg [3:0] LDST_dec31_dec_sub21_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec31_dec_sub21_internal_op;
  reg [6:0] LDST_dec31_dec_sub21_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub21_is_32b;
  reg LDST_dec31_dec_sub21_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub21_ldst_len;
  reg [3:0] LDST_dec31_dec_sub21_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub21_rc_sel;
  reg [1:0] LDST_dec31_dec_sub21_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub21_sgn;
  reg LDST_dec31_dec_sub21_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub21_sgn_ext;
  reg LDST_dec31_dec_sub21_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub21_upd;
  reg [1:0] LDST_dec31_dec_sub21_upd;
  (* src = "libresoc.v:11169.7-11169.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:11356.5-11356.29" *)
    casez (\initial )
      /* src = "libresoc.v:11356.9-11356.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:11405.5-11405.29" *)
    casez (\initial )
      /* src = "libresoc.v:11405.9-11405.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:11454.5-11454.29" *)
    casez (\initial )
      /* src = "libresoc.v:11454.9-11454.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:11503.5-11503.29" *)
    casez (\initial )
      /* src = "libresoc.v:11503.9-11503.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:11552.5-11552.29" *)
    casez (\initial )
      /* src = "libresoc.v:11552.9-11552.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:11601.5-11601.29" *)
    casez (\initial )
      /* src = "libresoc.v:11601.9-11601.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:11650.5-11650.29" *)
    casez (\initial )
      /* src = "libresoc.v:11650.9-11650.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:11699.5-11699.29" *)
    casez (\initial )
      /* src = "libresoc.v:11699.9-11699.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = 4'h1;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:11748.5-11748.29" *)
    casez (\initial )
      /* src = "libresoc.v:11748.9-11748.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:11797.5-11797.29" *)
    casez (\initial )
      /* src = "libresoc.v:11797.9-11797.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:11846.5-11846.29" *)
    casez (\initial )
      /* src = "libresoc.v:11846.9-11846.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = 4'h4;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:11895.5-11895.29" *)
    casez (\initial )
      /* src = "libresoc.v:11895.9-11895.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _26_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = 2'h2;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:11944.5-11944.29" *)
    casez (\initial )
      /* src = "libresoc.v:11944.9-11944.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub21_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:11997.1-12588.10" *)
module LDST_dec31_dec_sub22(LDST_dec31_dec_sub22_function_unit, LDST_dec31_dec_sub22_internal_op, LDST_dec31_dec_sub22_in1_sel, LDST_dec31_dec_sub22_in2_sel, LDST_dec31_dec_sub22_cr_in, LDST_dec31_dec_sub22_cr_out, LDST_dec31_dec_sub22_ldst_len, LDST_dec31_dec_sub22_upd, LDST_dec31_dec_sub22_rc_sel, LDST_dec31_dec_sub22_br, LDST_dec31_dec_sub22_sgn_ext, LDST_dec31_dec_sub22_is_32b, LDST_dec31_dec_sub22_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:12215.3-12245.6" *)
  reg _00_;
  (* src = "libresoc.v:12432.3-12462.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:12463.3-12493.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:12184.3-12214.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:12370.3-12400.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:12401.3-12431.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:12339.3-12369.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:12277.3-12307.6" *)
  reg _07_;
  (* src = "libresoc.v:12494.3-12524.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:12556.3-12586.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:12308.3-12338.6" *)
  reg _10_;
  (* src = "libresoc.v:12246.3-12276.6" *)
  reg _11_;
  (* src = "libresoc.v:12525.3-12555.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:11998.7-11998.20" *)
  reg _13_;
  (* src = "libresoc.v:12215.3-12245.6" *)
  reg _14_;
  (* src = "libresoc.v:12432.3-12462.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:12463.3-12493.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:12184.3-12214.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:12370.3-12400.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:12401.3-12431.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:12339.3-12369.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:12277.3-12307.6" *)
  reg _21_;
  (* src = "libresoc.v:12494.3-12524.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:12556.3-12586.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:12308.3-12338.6" *)
  reg _24_;
  (* src = "libresoc.v:12246.3-12276.6" *)
  reg _25_;
  (* src = "libresoc.v:12525.3-12555.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub22_br;
  reg LDST_dec31_dec_sub22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub22_cr_in;
  reg [2:0] LDST_dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub22_cr_out;
  reg [2:0] LDST_dec31_dec_sub22_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec31_dec_sub22_function_unit;
  reg [13:0] LDST_dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub22_in1_sel;
  reg [2:0] LDST_dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub22_in2_sel;
  reg [3:0] LDST_dec31_dec_sub22_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec31_dec_sub22_internal_op;
  reg [6:0] LDST_dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub22_is_32b;
  reg LDST_dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub22_ldst_len;
  reg [3:0] LDST_dec31_dec_sub22_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub22_rc_sel;
  reg [1:0] LDST_dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub22_sgn;
  reg LDST_dec31_dec_sub22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub22_sgn_ext;
  reg LDST_dec31_dec_sub22_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub22_upd;
  reg [1:0] LDST_dec31_dec_sub22_upd;
  (* src = "libresoc.v:11998.7-11998.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:12185.5-12185.29" *)
    casez (\initial )
      /* src = "libresoc.v:12185.9-12185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:12216.5-12216.29" *)
    casez (\initial )
      /* src = "libresoc.v:12216.9-12216.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:12247.5-12247.29" *)
    casez (\initial )
      /* src = "libresoc.v:12247.9-12247.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:12278.5-12278.29" *)
    casez (\initial )
      /* src = "libresoc.v:12278.9-12278.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:12309.5-12309.29" *)
    casez (\initial )
      /* src = "libresoc.v:12309.9-12309.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:12340.5-12340.29" *)
    casez (\initial )
      /* src = "libresoc.v:12340.9-12340.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:12371.5-12371.29" *)
    casez (\initial )
      /* src = "libresoc.v:12371.9-12371.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:12402.5-12402.29" *)
    casez (\initial )
      /* src = "libresoc.v:12402.9-12402.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 4'h1;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:12433.5-12433.29" *)
    casez (\initial )
      /* src = "libresoc.v:12433.9-12433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:12464.5-12464.29" *)
    casez (\initial )
      /* src = "libresoc.v:12464.9-12464.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h1;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:12495.5-12495.29" *)
    casez (\initial )
      /* src = "libresoc.v:12495.9-12495.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 4'h4;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:12526.5-12526.29" *)
    casez (\initial )
      /* src = "libresoc.v:12526.9-12526.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 2'h0;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:12557.5-12557.29" *)
    casez (\initial )
      /* src = "libresoc.v:12557.9-12557.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _23_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _23_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _23_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 2'h1;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub22_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:12592.1-13417.10" *)
module LDST_dec31_dec_sub23(LDST_dec31_dec_sub23_function_unit, LDST_dec31_dec_sub23_internal_op, LDST_dec31_dec_sub23_in1_sel, LDST_dec31_dec_sub23_in2_sel, LDST_dec31_dec_sub23_cr_in, LDST_dec31_dec_sub23_cr_out, LDST_dec31_dec_sub23_ldst_len, LDST_dec31_dec_sub23_upd, LDST_dec31_dec_sub23_rc_sel, LDST_dec31_dec_sub23_br, LDST_dec31_dec_sub23_sgn_ext, LDST_dec31_dec_sub23_is_32b, LDST_dec31_dec_sub23_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:12828.3-12876.6" *)
  reg _00_;
  (* src = "libresoc.v:13171.3-13219.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:13220.3-13268.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:12779.3-12827.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:13073.3-13121.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:13122.3-13170.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:13024.3-13072.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:12926.3-12974.6" *)
  reg _07_;
  (* src = "libresoc.v:13269.3-13317.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:13367.3-13415.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:12975.3-13023.6" *)
  reg _10_;
  (* src = "libresoc.v:12877.3-12925.6" *)
  reg _11_;
  (* src = "libresoc.v:13318.3-13366.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:12593.7-12593.20" *)
  reg _13_;
  (* src = "libresoc.v:12828.3-12876.6" *)
  reg _14_;
  (* src = "libresoc.v:13171.3-13219.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:13220.3-13268.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:12779.3-12827.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:13073.3-13121.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:13122.3-13170.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:13024.3-13072.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:12926.3-12974.6" *)
  reg _21_;
  (* src = "libresoc.v:13269.3-13317.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:13367.3-13415.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:12975.3-13023.6" *)
  reg _24_;
  (* src = "libresoc.v:12877.3-12925.6" *)
  reg _25_;
  (* src = "libresoc.v:13318.3-13366.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub23_br;
  reg LDST_dec31_dec_sub23_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub23_cr_in;
  reg [2:0] LDST_dec31_dec_sub23_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub23_cr_out;
  reg [2:0] LDST_dec31_dec_sub23_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec31_dec_sub23_function_unit;
  reg [13:0] LDST_dec31_dec_sub23_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec31_dec_sub23_in1_sel;
  reg [2:0] LDST_dec31_dec_sub23_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub23_in2_sel;
  reg [3:0] LDST_dec31_dec_sub23_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec31_dec_sub23_internal_op;
  reg [6:0] LDST_dec31_dec_sub23_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub23_is_32b;
  reg LDST_dec31_dec_sub23_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec31_dec_sub23_ldst_len;
  reg [3:0] LDST_dec31_dec_sub23_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub23_rc_sel;
  reg [1:0] LDST_dec31_dec_sub23_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub23_sgn;
  reg LDST_dec31_dec_sub23_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec31_dec_sub23_sgn_ext;
  reg LDST_dec31_dec_sub23_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec31_dec_sub23_upd;
  reg [1:0] LDST_dec31_dec_sub23_upd;
  (* src = "libresoc.v:12593.7-12593.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:12780.5-12780.29" *)
    casez (\initial )
      /* src = "libresoc.v:12780.9-12780.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:12829.5-12829.29" *)
    casez (\initial )
      /* src = "libresoc.v:12829.9-12829.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:12878.5-12878.29" *)
    casez (\initial )
      /* src = "libresoc.v:12878.9-12878.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:12927.5-12927.29" *)
    casez (\initial )
      /* src = "libresoc.v:12927.9-12927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:12976.5-12976.29" *)
    casez (\initial )
      /* src = "libresoc.v:12976.9-12976.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:13025.5-13025.29" *)
    casez (\initial )
      /* src = "libresoc.v:13025.9-13025.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:13074.5-13074.29" *)
    casez (\initial )
      /* src = "libresoc.v:13074.9-13074.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:13123.5-13123.29" *)
    casez (\initial )
      /* src = "libresoc.v:13123.9-13123.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _19_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 4'h1;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:13172.5-13172.29" *)
    casez (\initial )
      /* src = "libresoc.v:13172.9-13172.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:13221.5-13221.29" *)
    casez (\initial )
      /* src = "libresoc.v:13221.9-13221.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:13270.5-13270.29" *)
    casez (\initial )
      /* src = "libresoc.v:13270.9-13270.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 4'h4;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:13319.5-13319.29" *)
    casez (\initial )
      /* src = "libresoc.v:13319.9-13319.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 2'h0;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:13368.5-13368.29" *)
    casez (\initial )
      /* src = "libresoc.v:13368.9-13368.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec31_dec_sub23_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec58" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:13421.1-13817.10" *)
module LDST_dec58(LDST_dec58_function_unit, LDST_dec58_internal_op, LDST_dec58_in1_sel, LDST_dec58_in2_sel, LDST_dec58_cr_in, LDST_dec58_cr_out, LDST_dec58_ldst_len, LDST_dec58_upd, LDST_dec58_rc_sel, LDST_dec58_br, LDST_dec58_sgn_ext, LDST_dec58_is_32b, LDST_dec58_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:13624.3-13639.6" *)
  reg _00_;
  (* src = "libresoc.v:13736.3-13751.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:13752.3-13767.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:13608.3-13623.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:13704.3-13719.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:13720.3-13735.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:13688.3-13703.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:13656.3-13671.6" *)
  reg _07_;
  (* src = "libresoc.v:13768.3-13783.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:13800.3-13815.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:13672.3-13687.6" *)
  reg _10_;
  (* src = "libresoc.v:13640.3-13655.6" *)
  reg _11_;
  (* src = "libresoc.v:13784.3-13799.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:13422.7-13422.20" *)
  reg _13_;
  (* src = "libresoc.v:13624.3-13639.6" *)
  reg _14_;
  (* src = "libresoc.v:13736.3-13751.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:13752.3-13767.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:13608.3-13623.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:13704.3-13719.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:13720.3-13735.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:13688.3-13703.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:13656.3-13671.6" *)
  reg _21_;
  (* src = "libresoc.v:13768.3-13783.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:13800.3-13815.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:13672.3-13687.6" *)
  reg _24_;
  (* src = "libresoc.v:13640.3-13655.6" *)
  reg _25_;
  (* src = "libresoc.v:13784.3-13799.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec58_br;
  reg LDST_dec58_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec58_cr_in;
  reg [2:0] LDST_dec58_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec58_cr_out;
  reg [2:0] LDST_dec58_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec58_function_unit;
  reg [13:0] LDST_dec58_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec58_in1_sel;
  reg [2:0] LDST_dec58_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec58_in2_sel;
  reg [3:0] LDST_dec58_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec58_internal_op;
  reg [6:0] LDST_dec58_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec58_is_32b;
  reg LDST_dec58_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec58_ldst_len;
  reg [3:0] LDST_dec58_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec58_rc_sel;
  reg [1:0] LDST_dec58_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec58_sgn;
  reg LDST_dec58_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec58_sgn_ext;
  reg LDST_dec58_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec58_upd;
  reg [1:0] LDST_dec58_upd;
  (* src = "libresoc.v:13422.7-13422.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [1:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:13609.5-13609.29" *)
    casez (\initial )
      /* src = "libresoc.v:13609.9-13609.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec58_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:13625.5-13625.29" *)
    casez (\initial )
      /* src = "libresoc.v:13625.9-13625.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec58_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:13641.5-13641.29" *)
    casez (\initial )
      /* src = "libresoc.v:13641.9-13641.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _25_ = 1'h1;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec58_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:13657.5-13657.29" *)
    casez (\initial )
      /* src = "libresoc.v:13657.9-13657.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec58_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:13673.5-13673.29" *)
    casez (\initial )
      /* src = "libresoc.v:13673.9-13673.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec58_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:13689.5-13689.29" *)
    casez (\initial )
      /* src = "libresoc.v:13689.9-13689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _20_ = 7'h25;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec58_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:13705.5-13705.29" *)
    casez (\initial )
      /* src = "libresoc.v:13705.9-13705.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec58_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:13721.5-13721.29" *)
    casez (\initial )
      /* src = "libresoc.v:13721.9-13721.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _19_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _19_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _19_ = 4'h8;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec58_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:13737.5-13737.29" *)
    casez (\initial )
      /* src = "libresoc.v:13737.9-13737.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec58_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:13753.5-13753.29" *)
    casez (\initial )
      /* src = "libresoc.v:13753.9-13753.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec58_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:13769.5-13769.29" *)
    casez (\initial )
      /* src = "libresoc.v:13769.9-13769.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _22_ = 4'h4;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec58_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:13785.5-13785.29" *)
    casez (\initial )
      /* src = "libresoc.v:13785.9-13785.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _26_ = 2'h0;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec58_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:13801.5-13801.29" *)
    casez (\initial )
      /* src = "libresoc.v:13801.9-13801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec58_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec.LDST_dec62" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:13821.1-14178.10" *)
module LDST_dec62(LDST_dec62_function_unit, LDST_dec62_internal_op, LDST_dec62_in1_sel, LDST_dec62_in2_sel, LDST_dec62_cr_in, LDST_dec62_cr_out, LDST_dec62_ldst_len, LDST_dec62_upd, LDST_dec62_rc_sel, LDST_dec62_br, LDST_dec62_sgn_ext, LDST_dec62_is_32b, LDST_dec62_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:14021.3-14033.6" *)
  reg _00_;
  (* src = "libresoc.v:14112.3-14124.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:14125.3-14137.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:14008.3-14020.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:14086.3-14098.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:14099.3-14111.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:14073.3-14085.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:14047.3-14059.6" *)
  reg _07_;
  (* src = "libresoc.v:14138.3-14150.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:14164.3-14176.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:14060.3-14072.6" *)
  reg _10_;
  (* src = "libresoc.v:14034.3-14046.6" *)
  reg _11_;
  (* src = "libresoc.v:14151.3-14163.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:13822.7-13822.20" *)
  reg _13_;
  (* src = "libresoc.v:14021.3-14033.6" *)
  reg _14_;
  (* src = "libresoc.v:14112.3-14124.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:14125.3-14137.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:14008.3-14020.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:14086.3-14098.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:14099.3-14111.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:14073.3-14085.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:14047.3-14059.6" *)
  reg _21_;
  (* src = "libresoc.v:14138.3-14150.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:14164.3-14176.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:14060.3-14072.6" *)
  reg _24_;
  (* src = "libresoc.v:14034.3-14046.6" *)
  reg _25_;
  (* src = "libresoc.v:14151.3-14163.6" *)
  reg [1:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec62_br;
  reg LDST_dec62_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec62_cr_in;
  reg [2:0] LDST_dec62_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec62_cr_out;
  reg [2:0] LDST_dec62_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_dec62_function_unit;
  reg [13:0] LDST_dec62_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_dec62_in1_sel;
  reg [2:0] LDST_dec62_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec62_in2_sel;
  reg [3:0] LDST_dec62_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_dec62_internal_op;
  reg [6:0] LDST_dec62_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec62_is_32b;
  reg LDST_dec62_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_dec62_ldst_len;
  reg [3:0] LDST_dec62_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec62_rc_sel;
  reg [1:0] LDST_dec62_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec62_sgn;
  reg LDST_dec62_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_dec62_sgn_ext;
  reg LDST_dec62_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_dec62_upd;
  reg [1:0] LDST_dec62_upd;
  (* src = "libresoc.v:13822.7-13822.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [1:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:14009.5-14009.29" *)
    casez (\initial )
      /* src = "libresoc.v:14009.9-14009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_dec62_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:14022.5-14022.29" *)
    casez (\initial )
      /* src = "libresoc.v:14022.9-14022.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec62_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:14035.5-14035.29" *)
    casez (\initial )
      /* src = "libresoc.v:14035.9-14035.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec62_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:14048.5-14048.29" *)
    casez (\initial )
      /* src = "libresoc.v:14048.9-14048.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec62_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:14061.5-14061.29" *)
    casez (\initial )
      /* src = "libresoc.v:14061.9-14061.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_dec62_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:14074.5-14074.29" *)
    casez (\initial )
      /* src = "libresoc.v:14074.9-14074.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_dec62_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:14087.5-14087.29" *)
    casez (\initial )
      /* src = "libresoc.v:14087.9-14087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec62_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:14100.5-14100.29" *)
    casez (\initial )
      /* src = "libresoc.v:14100.9-14100.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _19_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _19_ = 4'h8;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec62_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:14113.5-14113.29" *)
    casez (\initial )
      /* src = "libresoc.v:14113.9-14113.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec62_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:14126.5-14126.29" *)
    casez (\initial )
      /* src = "libresoc.v:14126.9-14126.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_dec62_cr_out <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:14139.5-14139.29" *)
    casez (\initial )
      /* src = "libresoc.v:14139.9-14139.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _22_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _22_ = 4'h8;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_dec62_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:14152.5-14152.29" *)
    casez (\initial )
      /* src = "libresoc.v:14152.9-14152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _26_ = 2'h1;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec62_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:14165.5-14165.29" *)
    casez (\initial )
      /* src = "libresoc.v:14165.9-14165.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_dec62_rc_sel <= _09_;
  end
  assign opcode_switch = opcode_in[1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:14182.1-14935.10" *)
module LOGICAL_dec31(LOGICAL_dec31_function_unit, LOGICAL_dec31_internal_op, LOGICAL_dec31_in1_sel, LOGICAL_dec31_in2_sel, LOGICAL_dec31_cr_in, LOGICAL_dec31_cr_out, LOGICAL_dec31_ldst_len, LOGICAL_dec31_rc_sel, LOGICAL_dec31_cry_in, LOGICAL_dec31_inv_a, LOGICAL_dec31_inv_out, LOGICAL_dec31_cry_out, LOGICAL_dec31_is_32b, LOGICAL_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:14905.3-14917.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:14918.3-14930.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:14775.3-14787.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:14814.3-14826.6" *)
  reg _03_;
  (* src = "libresoc.v:14853.3-14865.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:14879.3-14891.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:14892.3-14904.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:14866.3-14878.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:14788.3-14800.6" *)
  reg _08_;
  (* src = "libresoc.v:14801.3-14813.6" *)
  reg _09_;
  (* src = "libresoc.v:14827.3-14839.6" *)
  reg _10_;
  (* src = "libresoc.v:14749.3-14761.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:14762.3-14774.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:14840.3-14852.6" *)
  reg _13_;
  (* src = "libresoc.v:14183.7-14183.20" *)
  reg _14_;
  (* src = "libresoc.v:14905.3-14917.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:14918.3-14930.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:14775.3-14787.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:14814.3-14826.6" *)
  reg _18_;
  (* src = "libresoc.v:14853.3-14865.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:14879.3-14891.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:14892.3-14904.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:14866.3-14878.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:14788.3-14800.6" *)
  reg _23_;
  (* src = "libresoc.v:14801.3-14813.6" *)
  reg _24_;
  (* src = "libresoc.v:14827.3-14839.6" *)
  reg _25_;
  (* src = "libresoc.v:14749.3-14761.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:14762.3-14774.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:14840.3-14852.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_cr_in;
  reg [2:0] LOGICAL_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_cr_out;
  reg [2:0] LOGICAL_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_cry_in;
  reg [1:0] LOGICAL_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_cry_out;
  reg LOGICAL_dec31_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LOGICAL_dec31_dec_sub26_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LOGICAL_dec31_dec_sub28_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LOGICAL_dec31_function_unit;
  reg [13:0] LOGICAL_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_in1_sel;
  reg [2:0] LOGICAL_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_in2_sel;
  reg [3:0] LOGICAL_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LOGICAL_dec31_internal_op;
  reg [6:0] LOGICAL_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_inv_a;
  reg LOGICAL_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_inv_out;
  reg LOGICAL_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_is_32b;
  reg LOGICAL_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_ldst_len;
  reg [3:0] LOGICAL_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_rc_sel;
  reg [1:0] LOGICAL_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_sgn;
  reg LOGICAL_dec31_sgn;
  (* src = "libresoc.v:14183.7-14183.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:14715.27-14731.4" *)
  LOGICAL_dec31_dec_sub26 LOGICAL_dec31_dec_sub26 (
    .LOGICAL_dec31_dec_sub26_cr_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in),
    .LOGICAL_dec31_dec_sub26_cr_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out),
    .LOGICAL_dec31_dec_sub26_cry_in(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in),
    .LOGICAL_dec31_dec_sub26_cry_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out),
    .LOGICAL_dec31_dec_sub26_function_unit(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit),
    .LOGICAL_dec31_dec_sub26_in1_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel),
    .LOGICAL_dec31_dec_sub26_in2_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel),
    .LOGICAL_dec31_dec_sub26_internal_op(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op),
    .LOGICAL_dec31_dec_sub26_inv_a(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a),
    .LOGICAL_dec31_dec_sub26_inv_out(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out),
    .LOGICAL_dec31_dec_sub26_is_32b(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b),
    .LOGICAL_dec31_dec_sub26_ldst_len(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len),
    .LOGICAL_dec31_dec_sub26_rc_sel(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel),
    .LOGICAL_dec31_dec_sub26_sgn(LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn),
    .opcode_in(LOGICAL_dec31_dec_sub26_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:14732.27-14748.4" *)
  LOGICAL_dec31_dec_sub28 LOGICAL_dec31_dec_sub28 (
    .LOGICAL_dec31_dec_sub28_cr_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in),
    .LOGICAL_dec31_dec_sub28_cr_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out),
    .LOGICAL_dec31_dec_sub28_cry_in(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in),
    .LOGICAL_dec31_dec_sub28_cry_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out),
    .LOGICAL_dec31_dec_sub28_function_unit(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit),
    .LOGICAL_dec31_dec_sub28_in1_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel),
    .LOGICAL_dec31_dec_sub28_in2_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel),
    .LOGICAL_dec31_dec_sub28_internal_op(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op),
    .LOGICAL_dec31_dec_sub28_inv_a(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a),
    .LOGICAL_dec31_dec_sub28_inv_out(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out),
    .LOGICAL_dec31_dec_sub28_is_32b(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b),
    .LOGICAL_dec31_dec_sub28_ldst_len(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len),
    .LOGICAL_dec31_dec_sub28_rc_sel(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel),
    .LOGICAL_dec31_dec_sub28_sgn(LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn),
    .opcode_in(LOGICAL_dec31_dec_sub28_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:14750.5-14750.29" *)
    casez (\initial )
      /* src = "libresoc.v:14750.9-14750.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _26_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _26_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:14763.5-14763.29" *)
    casez (\initial )
      /* src = "libresoc.v:14763.9-14763.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _27_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _27_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:14776.5-14776.29" *)
    casez (\initial )
      /* src = "libresoc.v:14776.9-14776.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _17_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _17_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:14789.5-14789.29" *)
    casez (\initial )
      /* src = "libresoc.v:14789.9-14789.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _23_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _23_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:14802.5-14802.29" *)
    casez (\initial )
      /* src = "libresoc.v:14802.9-14802.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _24_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _24_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:14815.5-14815.29" *)
    casez (\initial )
      /* src = "libresoc.v:14815.9-14815.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _18_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _18_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:14828.5-14828.29" *)
    casez (\initial )
      /* src = "libresoc.v:14828.9-14828.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _25_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _25_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:14841.5-14841.29" *)
    casez (\initial )
      /* src = "libresoc.v:14841.9-14841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _28_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _28_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:14854.5-14854.29" *)
    casez (\initial )
      /* src = "libresoc.v:14854.9-14854.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _19_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _19_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      LOGICAL_dec31_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:14867.5-14867.29" *)
    casez (\initial )
      /* src = "libresoc.v:14867.9-14867.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _22_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _22_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      LOGICAL_dec31_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:14880.5-14880.29" *)
    casez (\initial )
      /* src = "libresoc.v:14880.9-14880.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _20_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _20_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:14893.5-14893.29" *)
    casez (\initial )
      /* src = "libresoc.v:14893.9-14893.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _21_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _21_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:14906.5-14906.29" *)
    casez (\initial )
      /* src = "libresoc.v:14906.9-14906.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _15_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _15_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:14919.5-14919.29" *)
    casez (\initial )
      /* src = "libresoc.v:14919.9-14919.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _16_ = LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _16_ = LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_cr_out <= _01_;
  end
  assign LOGICAL_dec31_dec_sub26_opcode_in = opcode_in;
  assign LOGICAL_dec31_dec_sub28_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:14939.1-15605.10" *)
module LOGICAL_dec31_dec_sub26(LOGICAL_dec31_dec_sub26_function_unit, LOGICAL_dec31_dec_sub26_internal_op, LOGICAL_dec31_dec_sub26_in1_sel, LOGICAL_dec31_dec_sub26_in2_sel, LOGICAL_dec31_dec_sub26_cr_in, LOGICAL_dec31_dec_sub26_cr_out, LOGICAL_dec31_dec_sub26_ldst_len, LOGICAL_dec31_dec_sub26_rc_sel, LOGICAL_dec31_dec_sub26_cry_in, LOGICAL_dec31_dec_sub26_inv_a, LOGICAL_dec31_dec_sub26_inv_out, LOGICAL_dec31_dec_sub26_cry_out, LOGICAL_dec31_dec_sub26_is_32b, LOGICAL_dec31_dec_sub26_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:15434.3-15467.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:15468.3-15501.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:15570.3-15603.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:15230.3-15263.6" *)
  reg _03_;
  (* src = "libresoc.v:15128.3-15161.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:15366.3-15399.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:15400.3-15433.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:15332.3-15365.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:15162.3-15195.6" *)
  reg _08_;
  (* src = "libresoc.v:15196.3-15229.6" *)
  reg _09_;
  (* src = "libresoc.v:15264.3-15297.6" *)
  reg _10_;
  (* src = "libresoc.v:15502.3-15535.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:15536.3-15569.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:15298.3-15331.6" *)
  reg _13_;
  (* src = "libresoc.v:14940.7-14940.20" *)
  reg _14_;
  (* src = "libresoc.v:15434.3-15467.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:15468.3-15501.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:15570.3-15603.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:15230.3-15263.6" *)
  reg _18_;
  (* src = "libresoc.v:15128.3-15161.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:15366.3-15399.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:15400.3-15433.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:15332.3-15365.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:15162.3-15195.6" *)
  reg _23_;
  (* src = "libresoc.v:15196.3-15229.6" *)
  reg _24_;
  (* src = "libresoc.v:15264.3-15297.6" *)
  reg _25_;
  (* src = "libresoc.v:15502.3-15535.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:15536.3-15569.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:15298.3-15331.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub26_cr_in;
  reg [2:0] LOGICAL_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub26_cr_out;
  reg [2:0] LOGICAL_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_dec_sub26_cry_in;
  reg [1:0] LOGICAL_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub26_cry_out;
  reg LOGICAL_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LOGICAL_dec31_dec_sub26_function_unit;
  reg [13:0] LOGICAL_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub26_in1_sel;
  reg [2:0] LOGICAL_dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_dec_sub26_in2_sel;
  reg [3:0] LOGICAL_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LOGICAL_dec31_dec_sub26_internal_op;
  reg [6:0] LOGICAL_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub26_inv_a;
  reg LOGICAL_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub26_inv_out;
  reg LOGICAL_dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub26_is_32b;
  reg LOGICAL_dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_dec_sub26_ldst_len;
  reg [3:0] LOGICAL_dec31_dec_sub26_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_dec_sub26_rc_sel;
  reg [1:0] LOGICAL_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub26_sgn;
  reg LOGICAL_dec31_dec_sub26_sgn;
  (* src = "libresoc.v:14940.7-14940.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:15129.5-15129.29" *)
    casez (\initial )
      /* src = "libresoc.v:15129.9-15129.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _19_ = 14'h0010;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:15163.5-15163.29" *)
    casez (\initial )
      /* src = "libresoc.v:15163.9-15163.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:15197.5-15197.29" *)
    casez (\initial )
      /* src = "libresoc.v:15197.9-15197.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:15231.5-15231.29" *)
    casez (\initial )
      /* src = "libresoc.v:15231.9-15231.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:15265.5-15265.29" *)
    casez (\initial )
      /* src = "libresoc.v:15265.9-15265.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:15299.5-15299.29" *)
    casez (\initial )
      /* src = "libresoc.v:15299.9-15299.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:15333.5-15333.29" *)
    casez (\initial )
      /* src = "libresoc.v:15333.9-15333.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _22_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _22_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _22_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _22_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _22_ = 7'h37;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _22_ = 7'h37;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:15367.5-15367.29" *)
    casez (\initial )
      /* src = "libresoc.v:15367.9-15367.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _20_ = 3'h4;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:15401.5-15401.29" *)
    casez (\initial )
      /* src = "libresoc.v:15401.9-15401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _21_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _21_ = 4'h0;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:15435.5-15435.29" *)
    casez (\initial )
      /* src = "libresoc.v:15435.9-15435.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:15469.5-15469.29" *)
    casez (\initial )
      /* src = "libresoc.v:15469.9-15469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:15503.5-15503.29" *)
    casez (\initial )
      /* src = "libresoc.v:15503.9-15503.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _26_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _26_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _26_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _26_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _26_ = 4'h4;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:15537.5-15537.29" *)
    casez (\initial )
      /* src = "libresoc.v:15537.9-15537.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:15571.5-15571.29" *)
    casez (\initial )
      /* src = "libresoc.v:15571.9-15571.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub26_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:15609.1-16317.10" *)
module LOGICAL_dec31_dec_sub28(LOGICAL_dec31_dec_sub28_function_unit, LOGICAL_dec31_dec_sub28_internal_op, LOGICAL_dec31_dec_sub28_in1_sel, LOGICAL_dec31_dec_sub28_in2_sel, LOGICAL_dec31_dec_sub28_cr_in, LOGICAL_dec31_dec_sub28_cr_out, LOGICAL_dec31_dec_sub28_ldst_len, LOGICAL_dec31_dec_sub28_rc_sel, LOGICAL_dec31_dec_sub28_cry_in, LOGICAL_dec31_dec_sub28_inv_a, LOGICAL_dec31_dec_sub28_inv_out, LOGICAL_dec31_dec_sub28_cry_out, LOGICAL_dec31_dec_sub28_is_32b, LOGICAL_dec31_dec_sub28_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:16131.3-16167.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:16168.3-16204.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:16279.3-16315.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:15909.3-15945.6" *)
  reg _03_;
  (* src = "libresoc.v:15798.3-15834.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:16057.3-16093.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:16094.3-16130.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:16020.3-16056.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:15835.3-15871.6" *)
  reg _08_;
  (* src = "libresoc.v:15872.3-15908.6" *)
  reg _09_;
  (* src = "libresoc.v:15946.3-15982.6" *)
  reg _10_;
  (* src = "libresoc.v:16205.3-16241.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:16242.3-16278.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:15983.3-16019.6" *)
  reg _13_;
  (* src = "libresoc.v:15610.7-15610.20" *)
  reg _14_;
  (* src = "libresoc.v:16131.3-16167.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:16168.3-16204.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:16279.3-16315.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:15909.3-15945.6" *)
  reg _18_;
  (* src = "libresoc.v:15798.3-15834.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:16057.3-16093.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:16094.3-16130.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:16020.3-16056.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:15835.3-15871.6" *)
  reg _23_;
  (* src = "libresoc.v:15872.3-15908.6" *)
  reg _24_;
  (* src = "libresoc.v:15946.3-15982.6" *)
  reg _25_;
  (* src = "libresoc.v:16205.3-16241.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:16242.3-16278.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:15983.3-16019.6" *)
  reg _28_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub28_cr_in;
  reg [2:0] LOGICAL_dec31_dec_sub28_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub28_cr_out;
  reg [2:0] LOGICAL_dec31_dec_sub28_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_dec_sub28_cry_in;
  reg [1:0] LOGICAL_dec31_dec_sub28_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub28_cry_out;
  reg LOGICAL_dec31_dec_sub28_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LOGICAL_dec31_dec_sub28_function_unit;
  reg [13:0] LOGICAL_dec31_dec_sub28_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_dec31_dec_sub28_in1_sel;
  reg [2:0] LOGICAL_dec31_dec_sub28_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_dec_sub28_in2_sel;
  reg [3:0] LOGICAL_dec31_dec_sub28_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LOGICAL_dec31_dec_sub28_internal_op;
  reg [6:0] LOGICAL_dec31_dec_sub28_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub28_inv_a;
  reg LOGICAL_dec31_dec_sub28_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub28_inv_out;
  reg LOGICAL_dec31_dec_sub28_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub28_is_32b;
  reg LOGICAL_dec31_dec_sub28_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_dec31_dec_sub28_ldst_len;
  reg [3:0] LOGICAL_dec31_dec_sub28_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_dec31_dec_sub28_rc_sel;
  reg [1:0] LOGICAL_dec31_dec_sub28_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_dec31_dec_sub28_sgn;
  reg LOGICAL_dec31_dec_sub28_sgn;
  (* src = "libresoc.v:15610.7-15610.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:15799.5-15799.29" *)
    casez (\initial )
      /* src = "libresoc.v:15799.9-15799.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _19_ = 14'h0010;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:15836.5-15836.29" *)
    casez (\initial )
      /* src = "libresoc.v:15836.9-15836.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:15873.5-15873.29" *)
    casez (\initial )
      /* src = "libresoc.v:15873.9-15873.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _24_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _24_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _24_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:15910.5-15910.29" *)
    casez (\initial )
      /* src = "libresoc.v:15910.9-15910.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:15947.5-15947.29" *)
    casez (\initial )
      /* src = "libresoc.v:15947.9-15947.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:15984.5-15984.29" *)
    casez (\initial )
      /* src = "libresoc.v:15984.9-15984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:16021.5-16021.29" *)
    casez (\initial )
      /* src = "libresoc.v:16021.9-16021.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _22_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _22_ = 7'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _22_ = 7'h0b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _22_ = 7'h43;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _22_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _22_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _22_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _22_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _22_ = 7'h43;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:16058.5-16058.29" *)
    casez (\initial )
      /* src = "libresoc.v:16058.9-16058.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _20_ = 3'h4;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:16095.5-16095.29" *)
    casez (\initial )
      /* src = "libresoc.v:16095.9-16095.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _21_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _21_ = 4'h1;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:16132.5-16132.29" *)
    casez (\initial )
      /* src = "libresoc.v:16132.9-16132.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:16169.5-16169.29" *)
    casez (\initial )
      /* src = "libresoc.v:16169.9-16169.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _16_ = 3'h1;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:16206.5-16206.29" *)
    casez (\initial )
      /* src = "libresoc.v:16206.9-16206.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:16243.5-16243.29" *)
    casez (\initial )
      /* src = "libresoc.v:16243.9-16243.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _27_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _27_ = 2'h2;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:16280.5-16280.29" *)
    casez (\initial )
      /* src = "libresoc.v:16280.9-16280.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_dec31_dec_sub28_cry_in <= _02_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:16321.1-16894.10" *)
module MUL_dec31(MUL_dec31_function_unit, MUL_dec31_internal_op, MUL_dec31_in2_sel, MUL_dec31_cr_in, MUL_dec31_cr_out, MUL_dec31_rc_sel, MUL_dec31_is_32b, MUL_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:16851.3-16863.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:16864.3-16876.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:16812.3-16824.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:16838.3-16850.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:16825.3-16837.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:16786.3-16798.6" *)
  reg _05_;
  (* src = "libresoc.v:16877.3-16889.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:16799.3-16811.6" *)
  reg _07_;
  (* src = "libresoc.v:16322.7-16322.20" *)
  reg _08_;
  (* src = "libresoc.v:16851.3-16863.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:16864.3-16876.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:16812.3-16824.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:16838.3-16850.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:16825.3-16837.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:16786.3-16798.6" *)
  reg _14_;
  (* src = "libresoc.v:16877.3-16889.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:16799.3-16811.6" *)
  reg _16_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_cr_in;
  reg [2:0] MUL_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_cr_out;
  reg [2:0] MUL_dec31_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] MUL_dec31_dec_sub11_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] MUL_dec31_dec_sub9_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] MUL_dec31_function_unit;
  reg [13:0] MUL_dec31_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] MUL_dec31_in2_sel;
  reg [3:0] MUL_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] MUL_dec31_internal_op;
  reg [6:0] MUL_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_is_32b;
  reg MUL_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] MUL_dec31_rc_sel;
  reg [1:0] MUL_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_sgn;
  reg MUL_dec31_sgn;
  (* src = "libresoc.v:16322.7-16322.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:16764.23-16774.4" *)
  MUL_dec31_dec_sub11 MUL_dec31_dec_sub11 (
    .MUL_dec31_dec_sub11_cr_in(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in),
    .MUL_dec31_dec_sub11_cr_out(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out),
    .MUL_dec31_dec_sub11_function_unit(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit),
    .MUL_dec31_dec_sub11_in2_sel(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel),
    .MUL_dec31_dec_sub11_internal_op(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op),
    .MUL_dec31_dec_sub11_is_32b(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b),
    .MUL_dec31_dec_sub11_rc_sel(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel),
    .MUL_dec31_dec_sub11_sgn(MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn),
    .opcode_in(MUL_dec31_dec_sub11_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:16775.22-16785.4" *)
  MUL_dec31_dec_sub9 MUL_dec31_dec_sub9 (
    .MUL_dec31_dec_sub9_cr_in(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in),
    .MUL_dec31_dec_sub9_cr_out(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out),
    .MUL_dec31_dec_sub9_function_unit(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit),
    .MUL_dec31_dec_sub9_in2_sel(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel),
    .MUL_dec31_dec_sub9_internal_op(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op),
    .MUL_dec31_dec_sub9_is_32b(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b),
    .MUL_dec31_dec_sub9_rc_sel(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel),
    .MUL_dec31_dec_sub9_sgn(MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn),
    .opcode_in(MUL_dec31_dec_sub9_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:16787.5-16787.29" *)
    casez (\initial )
      /* src = "libresoc.v:16787.9-16787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _14_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _14_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:16800.5-16800.29" *)
    casez (\initial )
      /* src = "libresoc.v:16800.9-16800.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _16_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _16_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn;
        end
      default:
          _16_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_sgn <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:16813.5-16813.29" *)
    casez (\initial )
      /* src = "libresoc.v:16813.9-16813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _11_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _11_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      MUL_dec31_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:16826.5-16826.29" *)
    casez (\initial )
      /* src = "libresoc.v:16826.9-16826.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _13_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _13_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      MUL_dec31_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:16839.5-16839.29" *)
    casez (\initial )
      /* src = "libresoc.v:16839.9-16839.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _12_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _12_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      MUL_dec31_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:16852.5-16852.29" *)
    casez (\initial )
      /* src = "libresoc.v:16852.9-16852.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _09_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _09_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:16865.5-16865.29" *)
    casez (\initial )
      /* src = "libresoc.v:16865.9-16865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _10_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _10_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:16878.5-16878.29" *)
    casez (\initial )
      /* src = "libresoc.v:16878.9-16878.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _15_ = MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _15_ = MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel;
        end
      default:
          _15_ = 2'h0;
    endcase
  end
  always @* begin
      MUL_dec31_rc_sel <= _06_;
  end
  assign MUL_dec31_dec_sub11_opcode_in = opcode_in;
  assign MUL_dec31_dec_sub9_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:16898.1-17254.10" *)
module MUL_dec31_dec_sub11(MUL_dec31_dec_sub11_function_unit, MUL_dec31_dec_sub11_internal_op, MUL_dec31_dec_sub11_in2_sel, MUL_dec31_dec_sub11_cr_in, MUL_dec31_dec_sub11_cr_out, MUL_dec31_dec_sub11_rc_sel, MUL_dec31_dec_sub11_is_32b, MUL_dec31_dec_sub11_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:17128.3-17152.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:17153.3-17177.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:17053.3-17077.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:17103.3-17127.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:17078.3-17102.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:17203.3-17227.6" *)
  reg _05_;
  (* src = "libresoc.v:17178.3-17202.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:17228.3-17252.6" *)
  reg _07_;
  (* src = "libresoc.v:16899.7-16899.20" *)
  reg _08_;
  (* src = "libresoc.v:17128.3-17152.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:17153.3-17177.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:17053.3-17077.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:17103.3-17127.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:17078.3-17102.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:17203.3-17227.6" *)
  reg _14_;
  (* src = "libresoc.v:17178.3-17202.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:17228.3-17252.6" *)
  reg _16_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_dec_sub11_cr_in;
  reg [2:0] MUL_dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_dec_sub11_cr_out;
  reg [2:0] MUL_dec31_dec_sub11_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] MUL_dec31_dec_sub11_function_unit;
  reg [13:0] MUL_dec31_dec_sub11_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] MUL_dec31_dec_sub11_in2_sel;
  reg [3:0] MUL_dec31_dec_sub11_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] MUL_dec31_dec_sub11_internal_op;
  reg [6:0] MUL_dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_dec_sub11_is_32b;
  reg MUL_dec31_dec_sub11_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] MUL_dec31_dec_sub11_rc_sel;
  reg [1:0] MUL_dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_dec_sub11_sgn;
  reg MUL_dec31_dec_sub11_sgn;
  (* src = "libresoc.v:16899.7-16899.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:17054.5-17054.29" *)
    casez (\initial )
      /* src = "libresoc.v:17054.9-17054.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _11_ = 14'h0100;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:17079.5-17079.29" *)
    casez (\initial )
      /* src = "libresoc.v:17079.9-17079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _13_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _13_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _13_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _13_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _13_ = 7'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _13_ = 7'h32;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:17104.5-17104.29" *)
    casez (\initial )
      /* src = "libresoc.v:17104.9-17104.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _12_ = 4'h1;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:17129.5-17129.29" *)
    casez (\initial )
      /* src = "libresoc.v:17129.9-17129.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _09_ = 3'h0;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:17154.5-17154.29" *)
    casez (\initial )
      /* src = "libresoc.v:17154.9-17154.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _10_ = 3'h1;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:17179.5-17179.29" *)
    casez (\initial )
      /* src = "libresoc.v:17179.9-17179.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _15_ = 2'h2;
        end
      default:
          _15_ = 2'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_rc_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:17204.5-17204.29" *)
    casez (\initial )
      /* src = "libresoc.v:17204.9-17204.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _14_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _14_ = 1'h1;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:17229.5-17229.29" *)
    casez (\initial )
      /* src = "libresoc.v:17229.9-17229.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _16_ = 1'h1;
        end
      default:
          _16_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub11_sgn <= _07_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:17258.1-17614.10" *)
module MUL_dec31_dec_sub9(MUL_dec31_dec_sub9_function_unit, MUL_dec31_dec_sub9_internal_op, MUL_dec31_dec_sub9_in2_sel, MUL_dec31_dec_sub9_cr_in, MUL_dec31_dec_sub9_cr_out, MUL_dec31_dec_sub9_rc_sel, MUL_dec31_dec_sub9_is_32b, MUL_dec31_dec_sub9_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:17488.3-17512.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:17513.3-17537.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:17413.3-17437.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:17463.3-17487.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:17438.3-17462.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:17563.3-17587.6" *)
  reg _05_;
  (* src = "libresoc.v:17538.3-17562.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:17588.3-17612.6" *)
  reg _07_;
  (* src = "libresoc.v:17259.7-17259.20" *)
  reg _08_;
  (* src = "libresoc.v:17488.3-17512.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:17513.3-17537.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:17413.3-17437.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:17463.3-17487.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:17438.3-17462.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:17563.3-17587.6" *)
  reg _14_;
  (* src = "libresoc.v:17538.3-17562.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:17588.3-17612.6" *)
  reg _16_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_dec_sub9_cr_in;
  reg [2:0] MUL_dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_dec31_dec_sub9_cr_out;
  reg [2:0] MUL_dec31_dec_sub9_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] MUL_dec31_dec_sub9_function_unit;
  reg [13:0] MUL_dec31_dec_sub9_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] MUL_dec31_dec_sub9_in2_sel;
  reg [3:0] MUL_dec31_dec_sub9_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] MUL_dec31_dec_sub9_internal_op;
  reg [6:0] MUL_dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_dec_sub9_is_32b;
  reg MUL_dec31_dec_sub9_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] MUL_dec31_dec_sub9_rc_sel;
  reg [1:0] MUL_dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_dec31_dec_sub9_sgn;
  reg MUL_dec31_dec_sub9_sgn;
  (* src = "libresoc.v:17259.7-17259.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:17414.5-17414.29" *)
    casez (\initial )
      /* src = "libresoc.v:17414.9-17414.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _11_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _11_ = 14'h0100;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:17439.5-17439.29" *)
    casez (\initial )
      /* src = "libresoc.v:17439.9-17439.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _13_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _13_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _13_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _13_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _13_ = 7'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _13_ = 7'h32;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:17464.5-17464.29" *)
    casez (\initial )
      /* src = "libresoc.v:17464.9-17464.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _12_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _12_ = 4'h1;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:17489.5-17489.29" *)
    casez (\initial )
      /* src = "libresoc.v:17489.9-17489.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _09_ = 3'h0;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:17514.5-17514.29" *)
    casez (\initial )
      /* src = "libresoc.v:17514.9-17514.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _10_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _10_ = 3'h1;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:17539.5-17539.29" *)
    casez (\initial )
      /* src = "libresoc.v:17539.9-17539.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _15_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _15_ = 2'h2;
        end
      default:
          _15_ = 2'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_rc_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:17564.5-17564.29" *)
    casez (\initial )
      /* src = "libresoc.v:17564.9-17564.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:17589.5-17589.29" *)
    casez (\initial )
      /* src = "libresoc.v:17589.9-17589.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _16_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _16_ = 1'h1;
        end
      default:
          _16_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_dec31_dec_sub9_sgn <= _07_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:17618.1-18194.10" *)
module SHIFT_ROT_dec30(SHIFT_ROT_dec30_function_unit, SHIFT_ROT_dec30_internal_op, SHIFT_ROT_dec30_in2_sel, SHIFT_ROT_dec30_cr_in, SHIFT_ROT_dec30_cr_out, SHIFT_ROT_dec30_rc_sel, SHIFT_ROT_dec30_cry_in, SHIFT_ROT_dec30_inv_a, SHIFT_ROT_dec30_cry_out, SHIFT_ROT_dec30_is_32b, SHIFT_ROT_dec30_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:17971.3-18007.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:18008.3-18044.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:18082.3-18118.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:18156.3-18192.6" *)
  reg _03_;
  (* src = "libresoc.v:17786.3-17822.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:17934.3-17970.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:17897.3-17933.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:18119.3-18155.6" *)
  reg _07_;
  (* src = "libresoc.v:17823.3-17859.6" *)
  reg _08_;
  (* src = "libresoc.v:18045.3-18081.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:17860.3-17896.6" *)
  reg _10_;
  (* src = "libresoc.v:17619.7-17619.20" *)
  reg _11_;
  (* src = "libresoc.v:17971.3-18007.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:18008.3-18044.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:18082.3-18118.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:18156.3-18192.6" *)
  reg _15_;
  (* src = "libresoc.v:17786.3-17822.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:17934.3-17970.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:17897.3-17933.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:18119.3-18155.6" *)
  reg _19_;
  (* src = "libresoc.v:17823.3-17859.6" *)
  reg _20_;
  (* src = "libresoc.v:18045.3-18081.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:17860.3-17896.6" *)
  reg _22_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec30_cr_in;
  reg [2:0] SHIFT_ROT_dec30_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec30_cr_out;
  reg [2:0] SHIFT_ROT_dec30_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec30_cry_in;
  reg [1:0] SHIFT_ROT_dec30_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec30_cry_out;
  reg SHIFT_ROT_dec30_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_dec30_function_unit;
  reg [13:0] SHIFT_ROT_dec30_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_dec30_in2_sel;
  reg [3:0] SHIFT_ROT_dec30_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_dec30_internal_op;
  reg [6:0] SHIFT_ROT_dec30_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec30_inv_a;
  reg SHIFT_ROT_dec30_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec30_is_32b;
  reg SHIFT_ROT_dec30_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec30_rc_sel;
  reg [1:0] SHIFT_ROT_dec30_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec30_sgn;
  reg SHIFT_ROT_dec30_sgn;
  (* src = "libresoc.v:17619.7-17619.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [3:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:17787.5-17787.29" *)
    casez (\initial )
      /* src = "libresoc.v:17787.9-17787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _16_ = 14'h0008;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:17824.5-17824.29" *)
    casez (\initial )
      /* src = "libresoc.v:17824.9-17824.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _20_ = 1'h0;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:17861.5-17861.29" *)
    casez (\initial )
      /* src = "libresoc.v:17861.9-17861.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _22_ = 1'h0;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:17898.5-17898.29" *)
    casez (\initial )
      /* src = "libresoc.v:17898.9-17898.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _18_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _18_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _18_ = 7'h3a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _18_ = 7'h3a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _18_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _18_ = 7'h3a;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:17935.5-17935.29" *)
    casez (\initial )
      /* src = "libresoc.v:17935.9-17935.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _17_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _17_ = 4'h1;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:17972.5-17972.29" *)
    casez (\initial )
      /* src = "libresoc.v:17972.9-17972.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:18009.5-18009.29" *)
    casez (\initial )
      /* src = "libresoc.v:18009.9-18009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _13_ = 3'h1;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:18046.5-18046.29" *)
    casez (\initial )
      /* src = "libresoc.v:18046.9-18046.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _21_ = 2'h2;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:18083.5-18083.29" *)
    casez (\initial )
      /* src = "libresoc.v:18083.9-18083.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _14_ = 2'h0;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:18120.5-18120.29" *)
    casez (\initial )
      /* src = "libresoc.v:18120.9-18120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:18157.5-18157.29" *)
    casez (\initial )
      /* src = "libresoc.v:18157.9-18157.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _15_ = 1'h0;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec30_cry_out <= _03_;
  end
  assign opcode_switch = opcode_in[4:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:18198.1-19050.10" *)
module SHIFT_ROT_dec31(SHIFT_ROT_dec31_function_unit, SHIFT_ROT_dec31_internal_op, SHIFT_ROT_dec31_in2_sel, SHIFT_ROT_dec31_cr_in, SHIFT_ROT_dec31_cr_out, SHIFT_ROT_dec31_rc_sel, SHIFT_ROT_dec31_cry_in, SHIFT_ROT_dec31_inv_a, SHIFT_ROT_dec31_cry_out, SHIFT_ROT_dec31_is_32b, SHIFT_ROT_dec31_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:19013.3-19028.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:19029.3-19044.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:18885.3-18900.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:18917.3-18932.6" *)
  reg _03_;
  (* src = "libresoc.v:18965.3-18980.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:18997.3-19012.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:18981.3-18996.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:18901.3-18916.6" *)
  reg _07_;
  (* src = "libresoc.v:18933.3-18948.6" *)
  reg _08_;
  (* src = "libresoc.v:18869.3-18884.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:18949.3-18964.6" *)
  reg _10_;
  (* src = "libresoc.v:18199.7-18199.20" *)
  reg _11_;
  (* src = "libresoc.v:19013.3-19028.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:19029.3-19044.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:18885.3-18900.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:18917.3-18932.6" *)
  reg _15_;
  (* src = "libresoc.v:18965.3-18980.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:18997.3-19012.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:18981.3-18996.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:18901.3-18916.6" *)
  reg _19_;
  (* src = "libresoc.v:18933.3-18948.6" *)
  reg _20_;
  (* src = "libresoc.v:18869.3-18884.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:18949.3-18964.6" *)
  reg _22_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_cr_in;
  reg [2:0] SHIFT_ROT_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_cr_out;
  reg [2:0] SHIFT_ROT_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_cry_in;
  reg [1:0] SHIFT_ROT_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_cry_out;
  reg SHIFT_ROT_dec31_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SHIFT_ROT_dec31_dec_sub24_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SHIFT_ROT_dec31_dec_sub26_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SHIFT_ROT_dec31_dec_sub27_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_dec31_function_unit;
  reg [13:0] SHIFT_ROT_dec31_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_dec31_in2_sel;
  reg [3:0] SHIFT_ROT_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_dec31_internal_op;
  reg [6:0] SHIFT_ROT_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_inv_a;
  reg SHIFT_ROT_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_is_32b;
  reg SHIFT_ROT_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_rc_sel;
  reg [1:0] SHIFT_ROT_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_sgn;
  reg SHIFT_ROT_dec31_sgn;
  (* src = "libresoc.v:18199.7-18199.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:18827.29-18840.4" *)
  SHIFT_ROT_dec31_dec_sub24 SHIFT_ROT_dec31_dec_sub24 (
    .SHIFT_ROT_dec31_dec_sub24_cr_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in),
    .SHIFT_ROT_dec31_dec_sub24_cr_out(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out),
    .SHIFT_ROT_dec31_dec_sub24_cry_in(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in),
    .SHIFT_ROT_dec31_dec_sub24_cry_out(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out),
    .SHIFT_ROT_dec31_dec_sub24_function_unit(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit),
    .SHIFT_ROT_dec31_dec_sub24_in2_sel(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel),
    .SHIFT_ROT_dec31_dec_sub24_internal_op(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op),
    .SHIFT_ROT_dec31_dec_sub24_inv_a(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a),
    .SHIFT_ROT_dec31_dec_sub24_is_32b(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b),
    .SHIFT_ROT_dec31_dec_sub24_rc_sel(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel),
    .SHIFT_ROT_dec31_dec_sub24_sgn(SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn),
    .opcode_in(SHIFT_ROT_dec31_dec_sub24_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:18841.29-18854.4" *)
  SHIFT_ROT_dec31_dec_sub26 SHIFT_ROT_dec31_dec_sub26 (
    .SHIFT_ROT_dec31_dec_sub26_cr_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in),
    .SHIFT_ROT_dec31_dec_sub26_cr_out(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out),
    .SHIFT_ROT_dec31_dec_sub26_cry_in(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in),
    .SHIFT_ROT_dec31_dec_sub26_cry_out(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out),
    .SHIFT_ROT_dec31_dec_sub26_function_unit(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit),
    .SHIFT_ROT_dec31_dec_sub26_in2_sel(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel),
    .SHIFT_ROT_dec31_dec_sub26_internal_op(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op),
    .SHIFT_ROT_dec31_dec_sub26_inv_a(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a),
    .SHIFT_ROT_dec31_dec_sub26_is_32b(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b),
    .SHIFT_ROT_dec31_dec_sub26_rc_sel(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel),
    .SHIFT_ROT_dec31_dec_sub26_sgn(SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn),
    .opcode_in(SHIFT_ROT_dec31_dec_sub26_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:18855.29-18868.4" *)
  SHIFT_ROT_dec31_dec_sub27 SHIFT_ROT_dec31_dec_sub27 (
    .SHIFT_ROT_dec31_dec_sub27_cr_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in),
    .SHIFT_ROT_dec31_dec_sub27_cr_out(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out),
    .SHIFT_ROT_dec31_dec_sub27_cry_in(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in),
    .SHIFT_ROT_dec31_dec_sub27_cry_out(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out),
    .SHIFT_ROT_dec31_dec_sub27_function_unit(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit),
    .SHIFT_ROT_dec31_dec_sub27_in2_sel(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel),
    .SHIFT_ROT_dec31_dec_sub27_internal_op(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op),
    .SHIFT_ROT_dec31_dec_sub27_inv_a(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a),
    .SHIFT_ROT_dec31_dec_sub27_is_32b(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b),
    .SHIFT_ROT_dec31_dec_sub27_rc_sel(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel),
    .SHIFT_ROT_dec31_dec_sub27_sgn(SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn),
    .opcode_in(SHIFT_ROT_dec31_dec_sub27_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:18870.5-18870.29" *)
    casez (\initial )
      /* src = "libresoc.v:18870.9-18870.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _21_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _21_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:18886.5-18886.29" *)
    casez (\initial )
      /* src = "libresoc.v:18886.9-18886.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _14_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _14_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _14_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:18902.5-18902.29" *)
    casez (\initial )
      /* src = "libresoc.v:18902.9-18902.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _19_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _19_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_inv_a;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:18918.5-18918.29" *)
    casez (\initial )
      /* src = "libresoc.v:18918.9-18918.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _15_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _15_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:18934.5-18934.29" *)
    casez (\initial )
      /* src = "libresoc.v:18934.9-18934.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _20_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _20_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:18950.5-18950.29" *)
    casez (\initial )
      /* src = "libresoc.v:18950.9-18950.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _22_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _22_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:18966.5-18966.29" *)
    casez (\initial )
      /* src = "libresoc.v:18966.9-18966.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _16_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _16_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:18982.5-18982.29" *)
    casez (\initial )
      /* src = "libresoc.v:18982.9-18982.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _18_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _18_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:18998.5-18998.29" *)
    casez (\initial )
      /* src = "libresoc.v:18998.9-18998.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _17_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _17_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:19014.5-19014.29" *)
    casez (\initial )
      /* src = "libresoc.v:19014.9-19014.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _12_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _12_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _12_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:19030.5-19030.29" *)
    casez (\initial )
      /* src = "libresoc.v:19030.9-19030.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _13_ = SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _13_ = SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _13_ = SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_cr_out <= _01_;
  end
  assign SHIFT_ROT_dec31_dec_sub24_opcode_in = opcode_in;
  assign SHIFT_ROT_dec31_dec_sub27_opcode_in = opcode_in;
  assign SHIFT_ROT_dec31_dec_sub26_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:19054.1-19432.10" *)
module SHIFT_ROT_dec31_dec_sub24(SHIFT_ROT_dec31_dec_sub24_function_unit, SHIFT_ROT_dec31_dec_sub24_internal_op, SHIFT_ROT_dec31_dec_sub24_in2_sel, SHIFT_ROT_dec31_dec_sub24_cr_in, SHIFT_ROT_dec31_dec_sub24_cr_out, SHIFT_ROT_dec31_dec_sub24_rc_sel, SHIFT_ROT_dec31_dec_sub24_cry_in, SHIFT_ROT_dec31_dec_sub24_inv_a, SHIFT_ROT_dec31_dec_sub24_cry_out, SHIFT_ROT_dec31_dec_sub24_is_32b, SHIFT_ROT_dec31_dec_sub24_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:19317.3-19335.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:19336.3-19354.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:19374.3-19392.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:19412.3-19430.6" *)
  reg _03_;
  (* src = "libresoc.v:19222.3-19240.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:19298.3-19316.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:19279.3-19297.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:19393.3-19411.6" *)
  reg _07_;
  (* src = "libresoc.v:19241.3-19259.6" *)
  reg _08_;
  (* src = "libresoc.v:19355.3-19373.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:19260.3-19278.6" *)
  reg _10_;
  (* src = "libresoc.v:19055.7-19055.20" *)
  reg _11_;
  (* src = "libresoc.v:19317.3-19335.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:19336.3-19354.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:19374.3-19392.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:19412.3-19430.6" *)
  reg _15_;
  (* src = "libresoc.v:19222.3-19240.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:19298.3-19316.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:19279.3-19297.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:19393.3-19411.6" *)
  reg _19_;
  (* src = "libresoc.v:19241.3-19259.6" *)
  reg _20_;
  (* src = "libresoc.v:19355.3-19373.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:19260.3-19278.6" *)
  reg _22_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in;
  reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out;
  reg [2:0] SHIFT_ROT_dec31_dec_sub24_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in;
  reg [1:0] SHIFT_ROT_dec31_dec_sub24_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub24_cry_out;
  reg SHIFT_ROT_dec31_dec_sub24_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit;
  reg [13:0] SHIFT_ROT_dec31_dec_sub24_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel;
  reg [3:0] SHIFT_ROT_dec31_dec_sub24_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op;
  reg [6:0] SHIFT_ROT_dec31_dec_sub24_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub24_inv_a;
  reg SHIFT_ROT_dec31_dec_sub24_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub24_is_32b;
  reg SHIFT_ROT_dec31_dec_sub24_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel;
  reg [1:0] SHIFT_ROT_dec31_dec_sub24_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub24_sgn;
  reg SHIFT_ROT_dec31_dec_sub24_sgn;
  (* src = "libresoc.v:19055.7-19055.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:19223.5-19223.29" *)
    casez (\initial )
      /* src = "libresoc.v:19223.9-19223.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 14'h0008;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:19242.5-19242.29" *)
    casez (\initial )
      /* src = "libresoc.v:19242.9-19242.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _20_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 1'h1;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:19261.5-19261.29" *)
    casez (\initial )
      /* src = "libresoc.v:19261.9-19261.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _22_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 1'h0;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:19280.5-19280.29" *)
    casez (\initial )
      /* src = "libresoc.v:19280.9-19280.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 7'h3c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _18_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 7'h3d;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:19299.5-19299.29" *)
    casez (\initial )
      /* src = "libresoc.v:19299.9-19299.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _17_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 4'h1;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:19318.5-19318.29" *)
    casez (\initial )
      /* src = "libresoc.v:19318.9-19318.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:19337.5-19337.29" *)
    casez (\initial )
      /* src = "libresoc.v:19337.9-19337.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _13_ = 3'h1;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:19356.5-19356.29" *)
    casez (\initial )
      /* src = "libresoc.v:19356.9-19356.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 2'h2;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:19375.5-19375.29" *)
    casez (\initial )
      /* src = "libresoc.v:19375.9-19375.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 2'h0;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:19394.5-19394.29" *)
    casez (\initial )
      /* src = "libresoc.v:19394.9-19394.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:19413.5-19413.29" *)
    casez (\initial )
      /* src = "libresoc.v:19413.9-19413.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 1'h0;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub24_cry_out <= _03_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:19436.1-19781.10" *)
module SHIFT_ROT_dec31_dec_sub26(SHIFT_ROT_dec31_dec_sub26_function_unit, SHIFT_ROT_dec31_dec_sub26_internal_op, SHIFT_ROT_dec31_dec_sub26_in2_sel, SHIFT_ROT_dec31_dec_sub26_cr_in, SHIFT_ROT_dec31_dec_sub26_cr_out, SHIFT_ROT_dec31_dec_sub26_rc_sel, SHIFT_ROT_dec31_dec_sub26_cry_in, SHIFT_ROT_dec31_dec_sub26_inv_a, SHIFT_ROT_dec31_dec_sub26_cry_out, SHIFT_ROT_dec31_dec_sub26_is_32b, SHIFT_ROT_dec31_dec_sub26_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:19684.3-19699.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:19700.3-19715.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:19732.3-19747.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:19764.3-19779.6" *)
  reg _03_;
  (* src = "libresoc.v:19604.3-19619.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:19668.3-19683.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:19652.3-19667.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:19748.3-19763.6" *)
  reg _07_;
  (* src = "libresoc.v:19620.3-19635.6" *)
  reg _08_;
  (* src = "libresoc.v:19716.3-19731.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:19636.3-19651.6" *)
  reg _10_;
  (* src = "libresoc.v:19437.7-19437.20" *)
  reg _11_;
  (* src = "libresoc.v:19684.3-19699.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:19700.3-19715.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:19732.3-19747.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:19764.3-19779.6" *)
  reg _15_;
  (* src = "libresoc.v:19604.3-19619.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:19668.3-19683.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:19652.3-19667.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:19748.3-19763.6" *)
  reg _19_;
  (* src = "libresoc.v:19620.3-19635.6" *)
  reg _20_;
  (* src = "libresoc.v:19716.3-19731.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:19636.3-19651.6" *)
  reg _22_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in;
  reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out;
  reg [2:0] SHIFT_ROT_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in;
  reg [1:0] SHIFT_ROT_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub26_cry_out;
  reg SHIFT_ROT_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit;
  reg [13:0] SHIFT_ROT_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel;
  reg [3:0] SHIFT_ROT_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op;
  reg [6:0] SHIFT_ROT_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub26_inv_a;
  reg SHIFT_ROT_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub26_is_32b;
  reg SHIFT_ROT_dec31_dec_sub26_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel;
  reg [1:0] SHIFT_ROT_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub26_sgn;
  reg SHIFT_ROT_dec31_dec_sub26_sgn;
  (* src = "libresoc.v:19437.7-19437.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:19605.5-19605.29" *)
    casez (\initial )
      /* src = "libresoc.v:19605.9-19605.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _16_ = 14'h0008;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:19621.5-19621.29" *)
    casez (\initial )
      /* src = "libresoc.v:19621.9-19621.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _20_ = 1'h0;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:19637.5-19637.29" *)
    casez (\initial )
      /* src = "libresoc.v:19637.9-19637.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _22_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _22_ = 1'h1;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:19653.5-19653.29" *)
    casez (\initial )
      /* src = "libresoc.v:19653.9-19653.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _18_ = 7'h20;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _18_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _18_ = 7'h3d;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:19669.5-19669.29" *)
    casez (\initial )
      /* src = "libresoc.v:19669.9-19669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _17_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _17_ = 4'ha;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:19685.5-19685.29" *)
    casez (\initial )
      /* src = "libresoc.v:19685.9-19685.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:19701.5-19701.29" *)
    casez (\initial )
      /* src = "libresoc.v:19701.9-19701.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _13_ = 3'h1;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:19717.5-19717.29" *)
    casez (\initial )
      /* src = "libresoc.v:19717.9-19717.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _21_ = 2'h2;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:19733.5-19733.29" *)
    casez (\initial )
      /* src = "libresoc.v:19733.9-19733.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _14_ = 2'h0;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:19749.5-19749.29" *)
    casez (\initial )
      /* src = "libresoc.v:19749.9-19749.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:19765.5-19765.29" *)
    casez (\initial )
      /* src = "libresoc.v:19765.9-19765.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _15_ = 1'h1;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub26_cry_out <= _03_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:19785.1-20163.10" *)
module SHIFT_ROT_dec31_dec_sub27(SHIFT_ROT_dec31_dec_sub27_function_unit, SHIFT_ROT_dec31_dec_sub27_internal_op, SHIFT_ROT_dec31_dec_sub27_in2_sel, SHIFT_ROT_dec31_dec_sub27_cr_in, SHIFT_ROT_dec31_dec_sub27_cr_out, SHIFT_ROT_dec31_dec_sub27_rc_sel, SHIFT_ROT_dec31_dec_sub27_cry_in, SHIFT_ROT_dec31_dec_sub27_inv_a, SHIFT_ROT_dec31_dec_sub27_cry_out, SHIFT_ROT_dec31_dec_sub27_is_32b, SHIFT_ROT_dec31_dec_sub27_sgn, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:20048.3-20066.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:20067.3-20085.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:20105.3-20123.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:20143.3-20161.6" *)
  reg _03_;
  (* src = "libresoc.v:19953.3-19971.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:20029.3-20047.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:20010.3-20028.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:20124.3-20142.6" *)
  reg _07_;
  (* src = "libresoc.v:19972.3-19990.6" *)
  reg _08_;
  (* src = "libresoc.v:20086.3-20104.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:19991.3-20009.6" *)
  reg _10_;
  (* src = "libresoc.v:19786.7-19786.20" *)
  reg _11_;
  (* src = "libresoc.v:20048.3-20066.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:20067.3-20085.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:20105.3-20123.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:20143.3-20161.6" *)
  reg _15_;
  (* src = "libresoc.v:19953.3-19971.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:20029.3-20047.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:20010.3-20028.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:20124.3-20142.6" *)
  reg _19_;
  (* src = "libresoc.v:19972.3-19990.6" *)
  reg _20_;
  (* src = "libresoc.v:20086.3-20104.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:19991.3-20009.6" *)
  reg _22_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in;
  reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out;
  reg [2:0] SHIFT_ROT_dec31_dec_sub27_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in;
  reg [1:0] SHIFT_ROT_dec31_dec_sub27_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub27_cry_out;
  reg SHIFT_ROT_dec31_dec_sub27_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit;
  reg [13:0] SHIFT_ROT_dec31_dec_sub27_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel;
  reg [3:0] SHIFT_ROT_dec31_dec_sub27_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op;
  reg [6:0] SHIFT_ROT_dec31_dec_sub27_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub27_inv_a;
  reg SHIFT_ROT_dec31_dec_sub27_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub27_is_32b;
  reg SHIFT_ROT_dec31_dec_sub27_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel;
  reg [1:0] SHIFT_ROT_dec31_dec_sub27_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_dec31_dec_sub27_sgn;
  reg SHIFT_ROT_dec31_dec_sub27_sgn;
  (* src = "libresoc.v:19786.7-19786.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:19954.5-19954.29" *)
    casez (\initial )
      /* src = "libresoc.v:19954.9-19954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _16_ = 14'h0008;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:19973.5-19973.29" *)
    casez (\initial )
      /* src = "libresoc.v:19973.9-19973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _20_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _20_ = 1'h0;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:19992.5-19992.29" *)
    casez (\initial )
      /* src = "libresoc.v:19992.9-19992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _22_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _22_ = 1'h0;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:20011.5-20011.29" *)
    casez (\initial )
      /* src = "libresoc.v:20011.9-20011.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _18_ = 7'h20;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _18_ = 7'h3c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _18_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _18_ = 7'h3d;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:20030.5-20030.29" *)
    casez (\initial )
      /* src = "libresoc.v:20030.9-20030.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _17_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _17_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _17_ = 4'h1;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:20049.5-20049.29" *)
    casez (\initial )
      /* src = "libresoc.v:20049.9-20049.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:20068.5-20068.29" *)
    casez (\initial )
      /* src = "libresoc.v:20068.9-20068.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _13_ = 3'h1;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:20087.5-20087.29" *)
    casez (\initial )
      /* src = "libresoc.v:20087.9-20087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _21_ = 2'h2;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:20106.5-20106.29" *)
    casez (\initial )
      /* src = "libresoc.v:20106.9-20106.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _14_ = 2'h0;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:20125.5-20125.29" *)
    casez (\initial )
      /* src = "libresoc.v:20125.9-20125.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:20144.5-20144.29" *)
    casez (\initial )
      /* src = "libresoc.v:20144.9-20144.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _15_ = 1'h0;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_dec31_dec_sub27_cry_out <= _03_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:20167.1-20499.10" *)
module SPR_dec31(SPR_dec31_function_unit, SPR_dec31_internal_op, SPR_dec31_cr_in, SPR_dec31_cr_out, SPR_dec31_rc_sel, SPR_dec31_is_32b, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:20456.3-20465.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:20466.3-20475.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:20436.3-20445.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:20446.3-20455.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:20486.3-20495.6" *)
  reg _04_;
  (* src = "libresoc.v:20476.3-20485.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:20168.7-20168.20" *)
  reg _06_;
  (* src = "libresoc.v:20456.3-20465.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:20466.3-20475.6" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:20436.3-20445.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:20446.3-20455.6" *)
  reg [6:0] _10_;
  (* src = "libresoc.v:20486.3-20495.6" *)
  reg _11_;
  (* src = "libresoc.v:20476.3-20485.6" *)
  reg [1:0] _12_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SPR_dec31_cr_in;
  reg [2:0] SPR_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SPR_dec31_cr_out;
  reg [2:0] SPR_dec31_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SPR_dec31_dec_sub19_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SPR_dec31_function_unit;
  reg [13:0] SPR_dec31_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SPR_dec31_internal_op;
  reg [6:0] SPR_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SPR_dec31_is_32b;
  reg SPR_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SPR_dec31_rc_sel;
  reg [1:0] SPR_dec31_rc_sel;
  (* src = "libresoc.v:20168.7-20168.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:20427.23-20435.4" *)
  SPR_dec31_dec_sub19 SPR_dec31_dec_sub19 (
    .SPR_dec31_dec_sub19_cr_in(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in),
    .SPR_dec31_dec_sub19_cr_out(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out),
    .SPR_dec31_dec_sub19_function_unit(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit),
    .SPR_dec31_dec_sub19_internal_op(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op),
    .SPR_dec31_dec_sub19_is_32b(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b),
    .SPR_dec31_dec_sub19_rc_sel(SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel),
    .opcode_in(SPR_dec31_dec_sub19_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _06_ = 1'h0;
  end
  always @* begin
      \initial  <= _06_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _09_;
    (* src = "libresoc.v:20437.5-20437.29" *)
    casez (\initial )
      /* src = "libresoc.v:20437.9-20437.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _09_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit;
        end
      default:
          _09_ = 14'h0000;
    endcase
  end
  always @* begin
      SPR_dec31_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _10_;
    (* src = "libresoc.v:20447.5-20447.29" *)
    casez (\initial )
      /* src = "libresoc.v:20447.9-20447.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _10_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op;
        end
      default:
          _10_ = 7'h00;
    endcase
  end
  always @* begin
      SPR_dec31_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _07_;
    (* src = "libresoc.v:20457.5-20457.29" *)
    casez (\initial )
      /* src = "libresoc.v:20457.9-20457.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _07_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_dec31_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _08_;
    (* src = "libresoc.v:20467.5-20467.29" *)
    casez (\initial )
      /* src = "libresoc.v:20467.9-20467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _08_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out;
        end
      default:
          _08_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_dec31_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:20477.5-20477.29" *)
    casez (\initial )
      /* src = "libresoc.v:20477.9-20477.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _12_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel;
        end
      default:
          _12_ = 2'h0;
    endcase
  end
  always @* begin
      SPR_dec31_rc_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _11_;
    (* src = "libresoc.v:20487.5-20487.29" *)
    casez (\initial )
      /* src = "libresoc.v:20487.9-20487.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _11_ = SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b;
        end
      default:
          _11_ = 1'h0;
    endcase
  end
  always @* begin
      SPR_dec31_is_32b <= _04_;
  end
  assign SPR_dec31_dec_sub19_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:20503.1-20716.10" *)
module SPR_dec31_dec_sub19(SPR_dec31_dec_sub19_function_unit, SPR_dec31_dec_sub19_internal_op, SPR_dec31_dec_sub19_cr_in, SPR_dec31_dec_sub19_cr_out, SPR_dec31_dec_sub19_rc_sel, SPR_dec31_dec_sub19_is_32b, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:20663.3-20675.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:20676.3-20688.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:20637.3-20649.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:20650.3-20662.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:20702.3-20714.6" *)
  reg _04_;
  (* src = "libresoc.v:20689.3-20701.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:20504.7-20504.20" *)
  reg _06_;
  (* src = "libresoc.v:20663.3-20675.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:20676.3-20688.6" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:20637.3-20649.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:20650.3-20662.6" *)
  reg [6:0] _10_;
  (* src = "libresoc.v:20702.3-20714.6" *)
  reg _11_;
  (* src = "libresoc.v:20689.3-20701.6" *)
  reg [1:0] _12_;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SPR_dec31_dec_sub19_cr_in;
  reg [2:0] SPR_dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SPR_dec31_dec_sub19_cr_out;
  reg [2:0] SPR_dec31_dec_sub19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SPR_dec31_dec_sub19_function_unit;
  reg [13:0] SPR_dec31_dec_sub19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SPR_dec31_dec_sub19_internal_op;
  reg [6:0] SPR_dec31_dec_sub19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SPR_dec31_dec_sub19_is_32b;
  reg SPR_dec31_dec_sub19_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SPR_dec31_dec_sub19_rc_sel;
  reg [1:0] SPR_dec31_dec_sub19_rc_sel;
  (* src = "libresoc.v:20504.7-20504.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _06_ = 1'h0;
  end
  always @* begin
      \initial  <= _06_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _09_;
    (* src = "libresoc.v:20638.5-20638.29" *)
    casez (\initial )
      /* src = "libresoc.v:20638.9-20638.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _09_ = 14'h0400;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _09_ = 14'h0400;
        end
      default:
          _09_ = 14'h0000;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _10_;
    (* src = "libresoc.v:20651.5-20651.29" *)
    casez (\initial )
      /* src = "libresoc.v:20651.9-20651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _10_ = 7'h2e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _10_ = 7'h31;
        end
      default:
          _10_ = 7'h00;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _07_;
    (* src = "libresoc.v:20664.5-20664.29" *)
    casez (\initial )
      /* src = "libresoc.v:20664.9-20664.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _07_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _07_ = 3'h0;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _08_;
    (* src = "libresoc.v:20677.5-20677.29" *)
    casez (\initial )
      /* src = "libresoc.v:20677.9-20677.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _08_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _08_ = 3'h0;
        end
      default:
          _08_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:20690.5-20690.29" *)
    casez (\initial )
      /* src = "libresoc.v:20690.9-20690.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _12_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _12_ = 2'h0;
        end
      default:
          _12_ = 2'h0;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_rc_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _11_;
    (* src = "libresoc.v:20703.5-20703.29" *)
    casez (\initial )
      /* src = "libresoc.v:20703.9-20703.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _11_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _11_ = 1'h0;
        end
      default:
          _11_ = 1'h0;
    endcase
  end
  always @* begin
      SPR_dec31_dec_sub19_is_32b <= _04_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.jtag._fsm" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:20720.1-21040.10" *)
module _fsm(capture, shift, update, isir, posjtag_rst, negjtag_rst, posjtag_clk, negjtag_clk, TAP_bus__tck, TAP_bus__tms, isdr);
  reg \initial  = 0;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:20806.3-20807.35" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:20721.7-20721.20" *)
  reg _02_;
  (* src = "libresoc.v:20812.3-20863.6" *)
  reg _03_;
  (* src = "libresoc.v:20808.3-20809.25" *)
  reg _04_;
  (* src = "libresoc.v:20979.3-21030.6" *)
  reg _05_;
  (* src = "libresoc.v:20810.3-20811.25" *)
  reg _06_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:20761.13-20761.29" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:20812.3-20863.6" *)
  reg _11_;
  (* src = "libresoc.v:20766.7-20766.18" *)
  reg _12_;
  (* src = "libresoc.v:20979.3-21030.6" *)
  reg _13_;
  (* src = "libresoc.v:20771.7-20771.18" *)
  reg _14_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _15_;
  (* src = "libresoc.v:20812.3-20863.6" *)
  reg _16_;
  (* src = "libresoc.v:20979.3-21030.6" *)
  reg _17_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:20864.3-20978.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:20790.17-20790.110" *)
  wire _25_;
  (* src = "libresoc.v:20791.18-20791.111" *)
  wire _26_;
  (* src = "libresoc.v:20792.18-20792.111" *)
  wire _27_;
  (* src = "libresoc.v:20793.18-20793.111" *)
  wire _28_;
  (* src = "libresoc.v:20794.18-20794.111" *)
  wire _29_;
  (* src = "libresoc.v:20795.17-20795.108" *)
  wire _30_;
  (* src = "libresoc.v:20796.18-20796.111" *)
  wire _31_;
  (* src = "libresoc.v:20797.18-20797.111" *)
  wire _32_;
  (* src = "libresoc.v:20798.18-20798.111" *)
  wire _33_;
  (* src = "libresoc.v:20799.18-20799.111" *)
  wire _34_;
  (* src = "libresoc.v:20800.18-20800.111" *)
  wire _35_;
  (* src = "libresoc.v:20801.18-20801.111" *)
  wire _36_;
  (* src = "libresoc.v:20802.18-20802.112" *)
  wire _37_;
  (* src = "libresoc.v:20803.17-20803.108" *)
  wire _38_;
  (* src = "libresoc.v:20804.17-20804.108" *)
  wire _39_;
  (* src = "libresoc.v:20805.17-20805.108" *)
  wire _40_;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tck;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tms;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
  output capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *)
  reg [3:0] fsm_state;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *)
  reg [3:0] \fsm_state$next ;
  (* src = "libresoc.v:20721.7-20721.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *)
  output isdr;
  reg isdr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *)
  reg \isdr$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *)
  output isir;
  reg isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *)
  reg \isir$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:49" *)
  wire local_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
  output negjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
  output negjtag_rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  output posjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  output posjtag_rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:36" *)
  wire rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *)
  output shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *)
  output update;
  assign _25_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0;
  assign _26_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0;
  assign _27_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *) 1'h0;
  assign _28_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *) 1'h1;
  assign _29_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *) 1'h0;
  assign _30_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:113" *) 1'h0;
  assign _31_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *) 1'h0;
  assign _32_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *) 1'h0;
  assign _33_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *) 1'h1;
  assign _34_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *) 1'h0;
  assign _35_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *) 1'h1;
  assign _36_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *) 1'h0;
  assign _37_ = TAP_bus__tms == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *) 1'h0;
  assign _38_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:114" *) 2'h3;
  assign _39_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:115" *) 3'h5;
  assign _40_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:116" *) 4'h8;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _10_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      fsm_state <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      isdr <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      isir <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \fsm_state$next ;
  end
  always @(posedge local_clk) begin
      fsm_state <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \isdr$next ;
  end
  always @(posedge local_clk) begin
      isdr <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \isir$next ;
  end
  always @(posedge local_clk) begin
      isir <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _11_;
    (* src = "libresoc.v:20813.5-20813.29" *)
    casez (\initial )
      /* src = "libresoc.v:20813.9-20813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _11_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _11_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = _16_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *)
          casez (\$11 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _16_ = 1'h1;
              end
            default:
                _16_ = isdr;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
          _11_ = isdr;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = 1'h0;
        end
      default:
          _11_ = isdr;
    endcase
  end
  always @* begin
      \isdr$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:20865.5-20865.29" *)
    casez (\initial )
      /* src = "libresoc.v:20865.9-20865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _09_ = _15_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:59" *)
          casez (\$13 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _15_ = 4'h1;
              end
            default:
                _15_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _09_ = _18_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:67" *)
          casez (\$15 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _18_ = 4'h2;
              end
            default:
                _18_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _09_ = _19_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:70" *)
          casez (\$17 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _19_ = 4'h3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _19_ = 4'h4;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _09_ = _20_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *)
          casez (\$19 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _20_ = 4'h3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _20_ = 4'h0;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _09_ = _21_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:82" *)
          casez (\$21 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _21_ = 4'h5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _21_ = 4'h6;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _09_ = _22_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:87" *)
          casez (\$23 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _22_ = 4'h6;
              end
            default:
                _22_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _09_ = _23_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:90" *)
          casez (\$25 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _23_ = 4'h7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _23_ = 4'h8;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = _24_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:95" *)
          casez (\$27 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = 4'h9;
              end
            default:
                _24_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _09_ = _07_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:98" *)
          casez (\$29 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _07_ = 4'h5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _07_ = 4'h8;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _09_ = _08_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:107" *)
          casez (\$31 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _08_ = 4'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _08_ = 4'h2;
              end
          endcase
        end
      default:
          _09_ = fsm_state;
    endcase
  end
  always @* begin
      \fsm_state$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:20980.5-20980.29" *)
    casez (\initial )
      /* src = "libresoc.v:20980.9-20980.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:52" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _13_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _13_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _13_ = _17_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:76" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _17_ = 1'h1;
              end
            default:
                _17_ = isir;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
          _13_ = isir;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _13_ = 1'h0;
        end
      default:
          _13_ = isir;
    endcase
  end
  always @* begin
      \isir$next  <= _05_;
  end
  assign \$9  = _25_;
  assign \$11  = _26_;
  assign \$13  = _27_;
  assign \$15  = _28_;
  assign \$17  = _29_;
  assign \$1  = _30_;
  assign \$19  = _31_;
  assign \$21  = _32_;
  assign \$23  = _33_;
  assign \$25  = _34_;
  assign \$27  = _35_;
  assign \$29  = _36_;
  assign \$31  = _37_;
  assign \$3  = _38_;
  assign \$5  = _39_;
  assign \$7  = _40_;
  assign update = \$7 ;
  assign shift = \$5 ;
  assign capture = \$3 ;
  assign rst = \$1 ;
  assign local_clk = TAP_bus__tck;
  assign negjtag_rst = rst;
  assign negjtag_clk = TAP_bus__tck;
  assign posjtag_rst = rst;
  assign posjtag_clk = TAP_bus__tck;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.jtag._idblock" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:21044.1-21116.10" *)
module _idblock(id_bypass, capture, shift, update, TAP_bus__tdi, TAP_id_tdo, posjtag_rst, posjtag_clk, select_id);
  reg \initial  = 0;
  (* src = "libresoc.v:21089.3-21109.6" *)
  reg [31:0] _00_;
  (* src = "libresoc.v:21087.3-21088.35" *)
  reg [31:0] _01_;
  (* src = "libresoc.v:21045.7-21045.20" *)
  reg _02_;
  (* src = "libresoc.v:21089.3-21109.6" *)
  reg [31:0] _03_;
  (* src = "libresoc.v:21055.14-21055.31" *)
  reg [31:0] _04_;
  (* src = "libresoc.v:21089.3-21109.6" *)
  reg [31:0] _05_;
  (* src = "libresoc.v:21084.17-21084.110" *)
  wire _06_;
  (* src = "libresoc.v:21085.17-21085.108" *)
  wire _07_;
  (* src = "libresoc.v:21086.17-21086.109" *)
  wire _08_;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tdi;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *)
  reg [31:0] TAP_id_sr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:236" *)
  reg [31:0] \TAP_id_sr$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *)
  output TAP_id_tdo;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:243" *)
  wire _bypass;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:240" *)
  wire _capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:241" *)
  wire _shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:239" *)
  wire _tdi;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:242" *)
  wire _update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
  input capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *)
  input id_bypass;
  (* src = "libresoc.v:21045.7-21045.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  input posjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  input posjtag_rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *)
  input select_id;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *)
  input shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *)
  input update;
  assign _06_ = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" *) capture;
  assign _07_ = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" *) shift;
  assign _08_ = select_id & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" *) update;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      TAP_id_sr <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \TAP_id_sr$next ;
  end
  always @(posedge posjtag_clk) begin
      TAP_id_sr <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _03_;
    (* src = "libresoc.v:21090.5-21090.29" *)
    casez (\initial )
      /* src = "libresoc.v:21090.9-21090.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:254" *)
    casez ({ _shift, _capture })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _03_ = 32'd6399;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _03_ = _05_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:257" *)
          casez (_bypass)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _05_[31:1] = TAP_id_sr[31:1];
                _05_[0] = _tdi;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _05_ = { _tdi, TAP_id_sr[31:1] };
              end
          endcase
        end
      default:
          _03_ = TAP_id_sr;
    endcase
  end
  always @* begin
      \TAP_id_sr$next  <= _00_;
  end
  assign \$1  = _06_;
  assign \$3  = _07_;
  assign \$5  = _08_;
  assign TAP_id_tdo = TAP_id_sr[0];
  assign _bypass = id_bypass;
  assign _update = \$5 ;
  assign _shift = \$3 ;
  assign _capture = \$1 ;
  assign _tdi = TAP_bus__tdi;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.jtag._irblock" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:21120.1-21204.10" *)
module _irblock(capture, shift, update, TAP_bus__tdi, isir, tdo, posjtag_rst, posjtag_clk, ir);
  reg \initial  = 0;
  (* src = "libresoc.v:21121.7-21121.20" *)
  reg _00_;
  (* src = "libresoc.v:21182.3-21202.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:21165.3-21166.21" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:21169.3-21181.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:21167.3-21168.33" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:21182.3-21202.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:21140.13-21140.22" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:21169.3-21181.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:21152.13-21152.28" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:21182.3-21202.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:21159.17-21159.103" *)
  wire _10_;
  (* src = "libresoc.v:21160.18-21160.105" *)
  wire _11_;
  (* src = "libresoc.v:21161.17-21161.105" *)
  wire _12_;
  (* src = "libresoc.v:21162.17-21162.103" *)
  wire _13_;
  (* src = "libresoc.v:21163.17-21163.104" *)
  wire _14_;
  (* src = "libresoc.v:21164.17-21164.105" *)
  wire _15_;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tdi;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
  input capture;
  (* src = "libresoc.v:21121.7-21121.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *)
  output [3:0] ir;
  reg [3:0] ir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *)
  reg [3:0] \ir$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *)
  input isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  input posjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  input posjtag_rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *)
  input shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *)
  reg [3:0] shift_ir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:138" *)
  reg [3:0] \shift_ir$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *)
  output tdo;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *)
  input update;
  assign _10_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift;
  assign _11_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update;
  assign _12_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture;
  assign _13_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" *) shift;
  assign _14_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" *) update;
  assign _15_ = isir & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" *) capture;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _06_ = 4'h1;
  end
  always @* begin
  end
  initial begin
      ir <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      shift_ir <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \ir$next ;
  end
  always @(posedge posjtag_clk) begin
      ir <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \shift_ir$next ;
  end
  always @(posedge posjtag_clk) begin
      shift_ir <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _07_;
    (* src = "libresoc.v:21170.5-21170.29" *)
    casez (\initial )
      /* src = "libresoc.v:21170.9-21170.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *)
    casez ({ \$5 , \$3 , \$1  })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _07_ = ir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
        begin
          _07_ = { TAP_bus__tdi, shift_ir[3:1] };
        end
      default:
          _07_ = shift_ir;
    endcase
  end
  always @* begin
      \shift_ir$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _09_;
    (* src = "libresoc.v:21183.5-21183.29" *)
    casez (\initial )
      /* src = "libresoc.v:21183.9-21183.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:141" *)
    casez ({ \$11 , \$9 , \$7  })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
          _05_ = ir;
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
          _05_ = ir;
      /* src = "libresoc.v:0.0-0.0" */
      3'b1??:
        begin
          _05_ = shift_ir;
        end
      default:
          _05_ = ir;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _09_ = 4'h1;
        end
      default:
          _09_ = _05_;
    endcase
  end
  always @* begin
      \ir$next  <= _01_;
  end
  assign \$9  = _10_;
  assign \$11  = _11_;
  assign \$1  = _12_;
  assign \$3  = _13_;
  assign \$5  = _14_;
  assign \$7  = _15_;
  assign tdo = ir[0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.adr_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:21208.1-21266.10" *)
module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:21209.7-21209.20" *)
  reg _00_;
  (* src = "libresoc.v:21254.3-21262.6" *)
  reg _01_;
  (* src = "libresoc.v:21252.3-21253.27" *)
  reg _02_;
  (* src = "libresoc.v:21254.3-21262.6" *)
  reg _03_;
  (* src = "libresoc.v:21233.7-21233.19" *)
  reg _04_;
  (* src = "libresoc.v:21244.17-21244.96" *)
  wire _05_;
  (* src = "libresoc.v:21249.17-21249.96" *)
  wire _06_;
  (* src = "libresoc.v:21246.18-21246.93" *)
  wire _07_;
  (* src = "libresoc.v:21248.17-21248.92" *)
  wire _08_;
  (* src = "libresoc.v:21251.17-21251.92" *)
  wire _09_;
  (* src = "libresoc.v:21245.18-21245.98" *)
  wire _10_;
  (* src = "libresoc.v:21247.18-21247.99" *)
  wire _11_;
  (* src = "libresoc.v:21250.17-21250.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:21209.7-21209.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_adr;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_adr;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_adr;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_adr;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_adr;
  assign _11_ = q_adr | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_adr;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:21255.5-21255.29" *)
    casez (\initial )
      /* src = "libresoc.v:21255.9-21255.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_adr = \$15 ;
  assign qn_adr = \$13 ;
  assign q_adr = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.adrok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:21270.1-21328.10" *)
module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_acked, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:21271.7-21271.20" *)
  reg _00_;
  (* src = "libresoc.v:21316.3-21324.6" *)
  reg _01_;
  (* src = "libresoc.v:21314.3-21315.27" *)
  reg _02_;
  (* src = "libresoc.v:21316.3-21324.6" *)
  reg _03_;
  (* src = "libresoc.v:21295.7-21295.19" *)
  reg _04_;
  (* src = "libresoc.v:21306.17-21306.96" *)
  wire _05_;
  (* src = "libresoc.v:21311.17-21311.96" *)
  wire _06_;
  (* src = "libresoc.v:21308.18-21308.100" *)
  wire _07_;
  (* src = "libresoc.v:21310.17-21310.99" *)
  wire _08_;
  (* src = "libresoc.v:21313.17-21313.99" *)
  wire _09_;
  (* src = "libresoc.v:21307.18-21307.105" *)
  wire _10_;
  (* src = "libresoc.v:21309.18-21309.106" *)
  wire _11_;
  (* src = "libresoc.v:21312.17-21312.104" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:21271.7-21271.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  output qn_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_addr_acked;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_addr_acked;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_addr_acked;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_addr_acked;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_addr_acked;
  assign _11_ = q_addr_acked | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_addr_acked;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:21317.5-21317.29" *)
    casez (\initial )
      /* src = "libresoc.v:21317.9-21317.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_addr_acked = \$15 ;
  assign qn_addr_acked = \$13 ;
  assign q_addr_acked = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:21332.1-22663.10" *)
module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, xer_ov_ok, dest4_o, xer_so_ok, dest5_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:22174.3-22175.25" *)
  reg _000_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:22146.3-22147.67" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [13:0] _003_;
  (* src = "libresoc.v:22116.3-22117.65" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:22118.3-22119.79" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _007_;
  (* src = "libresoc.v:22120.3-22121.75" *)
  reg _008_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:22138.3-22139.73" *)
  reg [1:0] _010_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [31:0] _011_;
  (* src = "libresoc.v:22148.3-22149.59" *)
  reg [31:0] _012_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [6:0] _013_;
  (* src = "libresoc.v:22114.3-22115.69" *)
  reg [6:0] _014_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _015_;
  (* src = "libresoc.v:22130.3-22131.69" *)
  reg _016_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _017_;
  (* src = "libresoc.v:22134.3-22135.71" *)
  reg _018_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _019_;
  (* src = "libresoc.v:22142.3-22143.67" *)
  reg _020_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _021_;
  (* src = "libresoc.v:22144.3-22145.69" *)
  reg _022_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _023_;
  (* src = "libresoc.v:22126.3-22127.63" *)
  reg _024_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _025_;
  (* src = "libresoc.v:22128.3-22129.63" *)
  reg _026_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _027_;
  (* src = "libresoc.v:22140.3-22141.75" *)
  reg _028_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _029_;
  (* src = "libresoc.v:22124.3-22125.63" *)
  reg _030_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _031_;
  (* src = "libresoc.v:22122.3-22123.63" *)
  reg _032_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _033_;
  (* src = "libresoc.v:22136.3-22137.69" *)
  reg _034_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _035_;
  (* src = "libresoc.v:22132.3-22133.63" *)
  reg _036_;
  (* src = "libresoc.v:22172.3-22173.40" *)
  reg _037_;
  (* src = "libresoc.v:22562.3-22570.6" *)
  reg _038_;
  (* src = "libresoc.v:22082.3-22083.39" *)
  reg _039_;
  (* src = "libresoc.v:22553.3-22561.6" *)
  reg _040_;
  (* src = "libresoc.v:22084.3-22085.43" *)
  reg _041_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg [63:0] _042_;
  (* src = "libresoc.v:22110.3-22111.37" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg _044_;
  (* src = "libresoc.v:22112.3-22113.43" *)
  reg _045_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg [3:0] _046_;
  (* src = "libresoc.v:22106.3-22107.43" *)
  reg [3:0] _047_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg _048_;
  (* src = "libresoc.v:22108.3-22109.49" *)
  reg _049_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg [1:0] _050_;
  (* src = "libresoc.v:22102.3-22103.47" *)
  reg [1:0] _051_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg _052_;
  (* src = "libresoc.v:22104.3-22105.53" *)
  reg _053_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg [1:0] _054_;
  (* src = "libresoc.v:22098.3-22099.47" *)
  reg [1:0] _055_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg _056_;
  (* src = "libresoc.v:22100.3-22101.53" *)
  reg _057_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _058_;
  (* src = "libresoc.v:22094.3-22095.47" *)
  reg _059_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _060_;
  (* src = "libresoc.v:22096.3-22097.53" *)
  reg _061_;
  (* src = "libresoc.v:22571.3-22580.6" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:22581.3-22590.6" *)
  reg [3:0] _063_;
  (* src = "libresoc.v:22591.3-22600.6" *)
  reg [1:0] _064_;
  (* src = "libresoc.v:22601.3-22610.6" *)
  reg [1:0] _065_;
  (* src = "libresoc.v:22611.3-22620.6" *)
  reg _066_;
  (* src = "libresoc.v:21333.7-21333.20" *)
  reg _067_;
  (* src = "libresoc.v:22319.3-22327.6" *)
  reg _068_;
  (* src = "libresoc.v:22158.3-22159.39" *)
  reg _069_;
  (* src = "libresoc.v:22310.3-22318.6" *)
  reg _070_;
  (* src = "libresoc.v:22160.3-22161.39" *)
  reg _071_;
  (* src = "libresoc.v:22621.3-22629.6" *)
  reg [4:0] _072_;
  (* src = "libresoc.v:22170.3-22171.37" *)
  reg [4:0] _073_;
  (* src = "libresoc.v:22264.3-22273.6" *)
  reg _074_;
  (* src = "libresoc.v:22355.3-22363.6" *)
  reg [4:0] _075_;
  (* src = "libresoc.v:22150.3-22151.39" *)
  reg [4:0] _076_;
  (* src = "libresoc.v:22346.3-22354.6" *)
  reg [4:0] _077_;
  (* src = "libresoc.v:22152.3-22153.39" *)
  reg [4:0] _078_;
  (* src = "libresoc.v:22283.3-22291.6" *)
  reg _079_;
  (* src = "libresoc.v:22166.3-22167.41" *)
  reg _080_;
  (* src = "libresoc.v:22274.3-22282.6" *)
  reg _081_;
  (* src = "libresoc.v:22168.3-22169.41" *)
  reg _082_;
  (* src = "libresoc.v:22301.3-22309.6" *)
  reg _083_;
  (* src = "libresoc.v:22162.3-22163.39" *)
  reg _084_;
  (* src = "libresoc.v:22292.3-22300.6" *)
  reg _085_;
  (* src = "libresoc.v:22164.3-22165.39" *)
  reg _086_;
  (* src = "libresoc.v:22337.3-22345.6" *)
  reg [3:0] _087_;
  (* src = "libresoc.v:22154.3-22155.39" *)
  reg [3:0] _088_;
  (* src = "libresoc.v:22328.3-22336.6" *)
  reg [3:0] _089_;
  (* src = "libresoc.v:22156.3-22157.39" *)
  reg [3:0] _090_;
  (* src = "libresoc.v:22513.3-22522.6" *)
  reg [63:0] _091_;
  (* src = "libresoc.v:22092.3-22093.29" *)
  reg [63:0] _092_;
  (* src = "libresoc.v:22523.3-22532.6" *)
  reg [63:0] _093_;
  (* src = "libresoc.v:22090.3-22091.29" *)
  reg [63:0] _094_;
  (* src = "libresoc.v:22533.3-22542.6" *)
  reg _095_;
  (* src = "libresoc.v:22088.3-22089.29" *)
  reg _096_;
  (* src = "libresoc.v:22543.3-22552.6" *)
  reg [1:0] _097_;
  (* src = "libresoc.v:22086.3-22087.29" *)
  reg [1:0] _098_;
  (* src = "libresoc.v:21471.7-21471.24" *)
  reg _099_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [3:0] _100_;
  (* src = "libresoc.v:21479.13-21479.45" *)
  reg [3:0] _101_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [13:0] _102_;
  (* src = "libresoc.v:21498.14-21498.49" *)
  reg [13:0] _103_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [63:0] _104_;
  (* src = "libresoc.v:21502.14-21502.68" *)
  reg [63:0] _105_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _106_;
  (* src = "libresoc.v:21506.7-21506.43" *)
  reg _107_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [1:0] _108_;
  (* src = "libresoc.v:21514.13-21514.48" *)
  reg [1:0] _109_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [31:0] _110_;
  (* src = "libresoc.v:21518.14-21518.43" *)
  reg [31:0] _111_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [6:0] _112_;
  (* src = "libresoc.v:21597.13-21597.47" *)
  reg [6:0] _113_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _114_;
  (* src = "libresoc.v:21601.7-21601.40" *)
  reg _115_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _116_;
  (* src = "libresoc.v:21605.7-21605.41" *)
  reg _117_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _118_;
  (* src = "libresoc.v:21609.7-21609.39" *)
  reg _119_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _120_;
  (* src = "libresoc.v:21613.7-21613.40" *)
  reg _121_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _122_;
  (* src = "libresoc.v:21617.7-21617.37" *)
  reg _123_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _124_;
  (* src = "libresoc.v:21621.7-21621.37" *)
  reg _125_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _126_;
  (* src = "libresoc.v:21625.7-21625.43" *)
  reg _127_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _128_;
  (* src = "libresoc.v:21629.7-21629.37" *)
  reg _129_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _130_;
  (* src = "libresoc.v:21633.7-21633.37" *)
  reg _131_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _132_;
  (* src = "libresoc.v:21637.7-21637.40" *)
  reg _133_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _134_;
  (* src = "libresoc.v:21641.7-21641.37" *)
  reg _135_;
  (* src = "libresoc.v:21673.7-21673.26" *)
  reg _136_;
  (* src = "libresoc.v:22562.3-22570.6" *)
  reg _137_;
  (* src = "libresoc.v:21681.7-21681.25" *)
  reg _138_;
  (* src = "libresoc.v:22553.3-22561.6" *)
  reg _139_;
  (* src = "libresoc.v:21693.7-21693.27" *)
  reg _140_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg [63:0] _141_;
  (* src = "libresoc.v:21727.14-21727.47" *)
  reg [63:0] _142_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg _143_;
  (* src = "libresoc.v:21731.7-21731.27" *)
  reg _144_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg [3:0] _145_;
  (* src = "libresoc.v:21735.13-21735.33" *)
  reg [3:0] _146_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg _147_;
  (* src = "libresoc.v:21739.7-21739.30" *)
  reg _148_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg [1:0] _149_;
  (* src = "libresoc.v:21743.13-21743.35" *)
  reg [1:0] _150_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg _151_;
  (* src = "libresoc.v:21747.7-21747.32" *)
  reg _152_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg [1:0] _153_;
  (* src = "libresoc.v:21751.13-21751.35" *)
  reg [1:0] _154_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg _155_;
  (* src = "libresoc.v:21755.7-21755.32" *)
  reg _156_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _157_;
  (* src = "libresoc.v:21759.7-21759.29" *)
  reg _158_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _159_;
  (* src = "libresoc.v:21763.7-21763.32" *)
  reg _160_;
  (* src = "libresoc.v:22571.3-22580.6" *)
  reg [63:0] _161_;
  (* src = "libresoc.v:22581.3-22590.6" *)
  reg [3:0] _162_;
  (* src = "libresoc.v:22591.3-22600.6" *)
  reg [1:0] _163_;
  (* src = "libresoc.v:22601.3-22610.6" *)
  reg [1:0] _164_;
  (* src = "libresoc.v:22611.3-22620.6" *)
  reg _165_;
  (* src = "libresoc.v:22319.3-22327.6" *)
  reg _166_;
  (* src = "libresoc.v:21786.7-21786.25" *)
  reg _167_;
  (* src = "libresoc.v:22310.3-22318.6" *)
  reg _168_;
  (* src = "libresoc.v:21790.7-21790.25" *)
  reg _169_;
  (* src = "libresoc.v:22621.3-22629.6" *)
  reg [4:0] _170_;
  (* src = "libresoc.v:21924.13-21924.31" *)
  reg [4:0] _171_;
  (* src = "libresoc.v:22264.3-22273.6" *)
  reg _172_;
  (* src = "libresoc.v:22355.3-22363.6" *)
  reg [4:0] _173_;
  (* src = "libresoc.v:21932.13-21932.32" *)
  reg [4:0] _174_;
  (* src = "libresoc.v:22346.3-22354.6" *)
  reg [4:0] _175_;
  (* src = "libresoc.v:21936.13-21936.32" *)
  reg [4:0] _176_;
  (* src = "libresoc.v:22283.3-22291.6" *)
  reg _177_;
  (* src = "libresoc.v:21948.7-21948.26" *)
  reg _178_;
  (* src = "libresoc.v:22274.3-22282.6" *)
  reg _179_;
  (* src = "libresoc.v:21952.7-21952.26" *)
  reg _180_;
  (* src = "libresoc.v:22301.3-22309.6" *)
  reg _181_;
  (* src = "libresoc.v:21956.7-21956.25" *)
  reg _182_;
  (* src = "libresoc.v:22292.3-22300.6" *)
  reg _183_;
  (* src = "libresoc.v:21960.7-21960.25" *)
  reg _184_;
  (* src = "libresoc.v:22337.3-22345.6" *)
  reg [3:0] _185_;
  (* src = "libresoc.v:21976.13-21976.31" *)
  reg [3:0] _186_;
  (* src = "libresoc.v:22328.3-22336.6" *)
  reg [3:0] _187_;
  (* src = "libresoc.v:21980.13-21980.31" *)
  reg [3:0] _188_;
  (* src = "libresoc.v:22513.3-22522.6" *)
  reg [63:0] _189_;
  (* src = "libresoc.v:21988.14-21988.43" *)
  reg [63:0] _190_;
  (* src = "libresoc.v:22523.3-22532.6" *)
  reg [63:0] _191_;
  (* src = "libresoc.v:21992.14-21992.43" *)
  reg [63:0] _192_;
  (* src = "libresoc.v:22533.3-22542.6" *)
  reg _193_;
  (* src = "libresoc.v:21996.7-21996.20" *)
  reg _194_;
  (* src = "libresoc.v:22543.3-22552.6" *)
  reg [1:0] _195_;
  (* src = "libresoc.v:22000.13-22000.26" *)
  reg [1:0] _196_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg [63:0] _197_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _198_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _199_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _200_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _201_;
  (* src = "libresoc.v:22364.3-22402.6" *)
  reg _202_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg [63:0] _203_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg _204_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg [3:0] _205_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg _206_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg [1:0] _207_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg _208_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg [1:0] _209_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg _210_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _211_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _212_;
  (* src = "libresoc.v:22403.3-22424.6" *)
  reg _213_;
  (* src = "libresoc.v:22425.3-22446.6" *)
  reg _214_;
  (* src = "libresoc.v:22447.3-22468.6" *)
  reg _215_;
  (* src = "libresoc.v:22469.3-22490.6" *)
  reg _216_;
  (* src = "libresoc.v:22491.3-22512.6" *)
  reg _217_;
  (* src = "libresoc.v:22016.18-22016.134" *)
  wire _218_;
  (* src = "libresoc.v:22017.19-22017.133" *)
  wire _219_;
  (* src = "libresoc.v:22018.19-22018.161" *)
  wire [3:0] _220_;
  (* src = "libresoc.v:22021.19-22021.134" *)
  wire [3:0] _221_;
  (* src = "libresoc.v:22023.19-22023.115" *)
  wire [3:0] _222_;
  (* src = "libresoc.v:22024.19-22024.125" *)
  wire _223_;
  (* src = "libresoc.v:22025.19-22025.125" *)
  wire _224_;
  (* src = "libresoc.v:22026.18-22026.110" *)
  wire _225_;
  (* src = "libresoc.v:22027.19-22027.125" *)
  wire _226_;
  (* src = "libresoc.v:22028.19-22028.125" *)
  wire _227_;
  (* src = "libresoc.v:22029.19-22029.125" *)
  wire _228_;
  (* src = "libresoc.v:22030.19-22030.157" *)
  wire [4:0] _229_;
  (* src = "libresoc.v:22031.19-22031.121" *)
  wire [4:0] _230_;
  (* src = "libresoc.v:22032.19-22032.127" *)
  wire _231_;
  (* src = "libresoc.v:22033.19-22033.127" *)
  wire _232_;
  (* src = "libresoc.v:22034.19-22034.127" *)
  wire _233_;
  (* src = "libresoc.v:22035.19-22035.127" *)
  wire _234_;
  (* src = "libresoc.v:22036.19-22036.127" *)
  wire _235_;
  (* src = "libresoc.v:22038.18-22038.98" *)
  wire _236_;
  (* src = "libresoc.v:22040.18-22040.100" *)
  wire _237_;
  (* src = "libresoc.v:22041.18-22041.171" *)
  wire [4:0] _238_;
  (* src = "libresoc.v:22043.18-22043.119" *)
  wire [4:0] _239_;
  (* src = "libresoc.v:22046.18-22046.116" *)
  wire _240_;
  (* src = "libresoc.v:22050.17-22050.123" *)
  wire _241_;
  (* src = "libresoc.v:22052.18-22052.113" *)
  wire _242_;
  (* src = "libresoc.v:22053.18-22053.125" *)
  wire [4:0] _243_;
  (* src = "libresoc.v:22055.18-22055.112" *)
  wire _244_;
  (* src = "libresoc.v:22057.18-22057.126" *)
  wire _245_;
  (* src = "libresoc.v:22058.18-22058.126" *)
  wire _246_;
  (* src = "libresoc.v:22059.18-22059.117" *)
  wire _247_;
  (* src = "libresoc.v:22064.18-22064.130" *)
  wire _248_;
  (* src = "libresoc.v:22065.18-22065.124" *)
  wire [4:0] _249_;
  (* src = "libresoc.v:22068.18-22068.116" *)
  wire _250_;
  (* src = "libresoc.v:22069.18-22069.119" *)
  wire _251_;
  (* src = "libresoc.v:22070.18-22070.121" *)
  wire _252_;
  (* src = "libresoc.v:22071.18-22071.121" *)
  wire _253_;
  (* src = "libresoc.v:22072.18-22072.121" *)
  wire _254_;
  (* src = "libresoc.v:22054.18-22054.113" *)
  wire _255_;
  (* src = "libresoc.v:22056.18-22056.119" *)
  wire _256_;
  (* src = "libresoc.v:22019.19-22019.126" *)
  wire _257_;
  (* src = "libresoc.v:22020.19-22020.132" *)
  wire _258_;
  (* src = "libresoc.v:22022.19-22022.115" *)
  wire [3:0] _259_;
  (* src = "libresoc.v:22037.18-22037.97" *)
  wire _260_;
  (* src = "libresoc.v:22039.18-22039.99" *)
  wire _261_;
  (* src = "libresoc.v:22042.18-22042.113" *)
  wire [4:0] _262_;
  (* src = "libresoc.v:22045.18-22045.106" *)
  wire _263_;
  (* src = "libresoc.v:22051.18-22051.120" *)
  wire _264_;
  (* src = "libresoc.v:22066.17-22066.113" *)
  wire [3:0] _265_;
  (* src = "libresoc.v:22049.18-22049.112" *)
  wire _266_;
  (* src = "libresoc.v:22060.18-22060.122" *)
  wire _267_;
  (* src = "libresoc.v:22061.18-22061.124" *)
  wire _268_;
  (* src = "libresoc.v:22062.18-22062.181" *)
  wire [4:0] _269_;
  (* src = "libresoc.v:22063.18-22063.168" *)
  wire [3:0] _270_;
  (* src = "libresoc.v:22067.18-22067.120" *)
  wire [4:0] _271_;
  (* src = "libresoc.v:22076.17-22076.117" *)
  wire [3:0] _272_;
  (* src = "libresoc.v:22015.17-22015.104" *)
  wire _273_;
  (* src = "libresoc.v:22044.18-22044.106" *)
  wire _274_;
  (* src = "libresoc.v:22047.18-22047.113" *)
  wire _275_;
  (* src = "libresoc.v:22048.18-22048.112" *)
  wire _276_;
  (* src = "libresoc.v:22073.18-22073.154" *)
  wire _277_;
  (* src = "libresoc.v:22074.18-22074.155" *)
  wire [63:0] _278_;
  (* src = "libresoc.v:22075.18-22075.160" *)
  wire _279_;
  (* src = "libresoc.v:22077.18-22077.172" *)
  wire [63:0] _280_;
  (* src = "libresoc.v:22078.18-22078.115" *)
  wire [63:0] _281_;
  (* src = "libresoc.v:22079.18-22079.125" *)
  wire [63:0] _282_;
  (* src = "libresoc.v:22080.18-22080.118" *)
  wire _283_;
  (* src = "libresoc.v:22081.18-22081.118" *)
  wire [1:0] _284_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [4:0] \$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [4:0] \$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$137 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [4:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [4:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [4:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [4:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [3:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [4:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [3:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [4:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [4:0] \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [3:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$89 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$91 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$93 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [1:0] \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] alu_alu0_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \alu_alu0_alu_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_alu0_alu_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_alu0_alu_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_alu0_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_alu0_alu_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] alu_alu0_alu_op__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_alu0_alu_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_alu0_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_alu0_alu_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_alu0_alu_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_alu0_alu_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_alu0_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_alu0_alu_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_alu0_cr_a;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_alu0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_alu0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_alu0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_alu0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_alu0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_alu0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_alu0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_alu0_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \alu_alu0_xer_ca$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_alu0_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire alu_alu0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \alu_alu0_xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [4:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [3:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [4:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r1__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r1__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r2__xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r2__xer_ca$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r3__xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r3__xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r4__xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r4__xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r4__xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r4__xer_so_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest2_o;
  reg [3:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest3_o;
  reg [1:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest4_o;
  reg [1:0] dest4_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output dest5_o;
  reg dest5_o;
  (* src = "libresoc.v:21333.7-21333.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_alu0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_alu0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_alu0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_alu0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_alu0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_alu0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [4:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [4:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [4:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [3:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [4:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src4_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [3:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] \src_or_imm$88 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] src_r3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] \src_r3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire \src_sel$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  assign _218_ = alu_alu0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _219_ = alu_alu0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _220_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _221_ = \$103  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 2'h3, \$107 , \$105  };
  assign _222_ = \$109  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$111 ;
  assign _223_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _224_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _225_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ;
  assign _226_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _227_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _228_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _229_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$115 , \$117 , \$119 , \$121 , \$123  };
  assign _230_ = \$125  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _231_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _232_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _233_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _234_ = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _235_ = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _236_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ;
  assign _237_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ;
  assign _238_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _239_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ;
  assign _240_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _241_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _242_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ;
  assign _243_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _244_ = \$41  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ;
  assign _245_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_alu0_n_ready_i;
  assign _246_ = \$51  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_alu0_n_valid_o;
  assign _247_ = \$53  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _248_ = alu_alu0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _249_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _250_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _251_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _252_ = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _253_ = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _254_ = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _255_ = \$43  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _256_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _257_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_alu0_alu_op__zero_a;
  assign _258_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_alu0_alu_op__imm_data__ok;
  assign _259_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _260_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _261_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _262_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _263_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _264_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_alu0_n_ready_i;
  assign _265_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _266_ = \$33  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ;
  assign _267_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _268_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _269_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _270_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _271_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _272_ = \$6  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _273_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ;
  assign _274_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ;
  assign _275_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _276_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _277_ = alu_alu0_alu_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0];
  assign _278_ = alu_alu0_alu_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i;
  assign _279_ = alu_alu0_alu_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _280_ = alu_alu0_alu_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_alu0_alu_op__imm_data__data : src2_i;
  assign _281_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0;
  assign _282_ = \src_sel$85  ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$88  : src_r1;
  assign _283_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  assign _284_ = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22176.12-22215.4" *)
  alu_alu0 alu_alu0 (
    .alu_op__data_len(alu_alu0_alu_op__data_len),
    .alu_op__fn_unit(alu_alu0_alu_op__fn_unit),
    .alu_op__imm_data__data(alu_alu0_alu_op__imm_data__data),
    .alu_op__imm_data__ok(alu_alu0_alu_op__imm_data__ok),
    .alu_op__input_carry(alu_alu0_alu_op__input_carry),
    .alu_op__insn(alu_alu0_alu_op__insn),
    .alu_op__insn_type(alu_alu0_alu_op__insn_type),
    .alu_op__invert_in(alu_alu0_alu_op__invert_in),
    .alu_op__invert_out(alu_alu0_alu_op__invert_out),
    .alu_op__is_32bit(alu_alu0_alu_op__is_32bit),
    .alu_op__is_signed(alu_alu0_alu_op__is_signed),
    .alu_op__oe__oe(alu_alu0_alu_op__oe__oe),
    .alu_op__oe__ok(alu_alu0_alu_op__oe__ok),
    .alu_op__output_carry(alu_alu0_alu_op__output_carry),
    .alu_op__rc__ok(alu_alu0_alu_op__rc__ok),
    .alu_op__rc__rc(alu_alu0_alu_op__rc__rc),
    .alu_op__write_cr0(alu_alu0_alu_op__write_cr0),
    .alu_op__zero_a(alu_alu0_alu_op__zero_a),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_alu0_cr_a),
    .cr_a_ok(cr_a_ok),
    .n_ready_i(alu_alu0_n_ready_i),
    .n_valid_o(alu_alu0_n_valid_o),
    .o(alu_alu0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_alu0_p_ready_o),
    .p_valid_i(alu_alu0_p_valid_i),
    .ra(alu_alu0_ra),
    .rb(alu_alu0_rb),
    .xer_ca(alu_alu0_xer_ca),
    .\xer_ca$2 (\alu_alu0_xer_ca$2 ),
    .xer_ca_ok(xer_ca_ok),
    .xer_ov(alu_alu0_xer_ov),
    .xer_ov_ok(xer_ov_ok),
    .xer_so(alu_alu0_xer_so),
    .\xer_so$1 (\alu_alu0_xer_so$1 ),
    .xer_so_ok(xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22216.9-22222.4" *)
  alu_l alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22223.10-22229.4" *)
  alui_l alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22230.9-22236.4" *)
  opc_l opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22237.9-22243.4" *)
  req_l req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22244.9-22250.4" *)
  rok_l rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22251.9-22256.4" *)
  rst_l rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:22257.9-22263.4" *)
  src_l src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _067_ = 1'h0;
  end
  always @* begin
      \initial  <= _067_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _099_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__data_len <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__fn_unit <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__imm_data__data <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__imm_data__ok <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__input_carry <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__insn <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__insn_type <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__invert_in <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__invert_out <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__is_32bit <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__is_signed <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__oe__oe <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__oe__ok <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__output_carry <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__rc__ok <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__rc__rc <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__write_cr0 <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_alu0_alu_op__zero_a <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _136_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _136_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a_ok <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ca <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ca_ok <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_ov <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_ov_ok <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r4__xer_so <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _160_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r4__xer_so_ok <= _160_;
  end
  always @* begin
    if (\initial ) begin end
    _167_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _167_;
  end
  always @* begin
    if (\initial ) begin end
    _169_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _169_;
  end
  always @* begin
    if (\initial ) begin end
    _171_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _171_;
  end
  always @* begin
    if (\initial ) begin end
    _174_ = 5'h1f;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _174_;
  end
  always @* begin
    if (\initial ) begin end
    _176_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _176_;
  end
  always @* begin
    if (\initial ) begin end
    _178_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _178_;
  end
  always @* begin
    if (\initial ) begin end
    _180_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _180_;
  end
  always @* begin
    if (\initial ) begin end
    _182_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _182_;
  end
  always @* begin
    if (\initial ) begin end
    _184_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _184_;
  end
  always @* begin
    if (\initial ) begin end
    _186_ = 4'hf;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _186_;
  end
  always @* begin
    if (\initial ) begin end
    _188_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _188_;
  end
  always @* begin
    if (\initial ) begin end
    _190_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _190_;
  end
  always @* begin
    if (\initial ) begin end
    _192_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _192_;
  end
  always @* begin
    if (\initial ) begin end
    _194_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _194_;
  end
  always @* begin
    if (\initial ) begin end
    _196_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src_r3 <= _196_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = \src_r3$next ;
  end
  always @(posedge coresync_clk) begin
      src_r3 <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \data_r4__xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__xer_so <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \data_r4__xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__xer_so_ok <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \data_r3__xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_ov <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \data_r3__xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_ov_ok <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \data_r2__xer_ca$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ca <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \data_r2__xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ca_ok <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \data_r1__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \data_r1__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a_ok <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \alu_alu0_alu_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__insn_type <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \alu_alu0_alu_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__fn_unit <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \alu_alu0_alu_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__imm_data__data <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \alu_alu0_alu_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__imm_data__ok <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \alu_alu0_alu_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__rc__rc <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \alu_alu0_alu_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__rc__ok <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \alu_alu0_alu_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__oe__oe <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \alu_alu0_alu_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__oe__ok <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \alu_alu0_alu_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__invert_in <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \alu_alu0_alu_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__zero_a <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \alu_alu0_alu_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__invert_out <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \alu_alu0_alu_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__write_cr0 <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \alu_alu0_alu_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__input_carry <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \alu_alu0_alu_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__output_carry <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \alu_alu0_alu_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__is_32bit <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \alu_alu0_alu_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__is_signed <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \alu_alu0_alu_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__data_len <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \alu_alu0_alu_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_alu0_alu_op__insn <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = alu_alu0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$11 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = _172_;
    (* src = "libresoc.v:22265.5-22265.29" *)
    casez (\initial )
      /* src = "libresoc.v:22265.9-22265.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _172_ = 1'h1;
        end
      default:
          _172_ = \$47 ;
    endcase
  end
  always @* begin
      req_done <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = _179_;
    (* src = "libresoc.v:22275.5-22275.29" *)
    casez (\initial )
      /* src = "libresoc.v:22275.9-22275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _179_ = 1'h0;
        end
      default:
          _179_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = _177_;
    (* src = "libresoc.v:22284.5-22284.29" *)
    casez (\initial )
      /* src = "libresoc.v:22284.9-22284.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _177_ = 1'h1;
        end
      default:
          _177_ = \$65 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = _183_;
    (* src = "libresoc.v:22293.5-22293.29" *)
    casez (\initial )
      /* src = "libresoc.v:22293.9-22293.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _183_ = 1'h0;
        end
      default:
          _183_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = _181_;
    (* src = "libresoc.v:22302.5-22302.29" *)
    casez (\initial )
      /* src = "libresoc.v:22302.9-22302.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _181_ = 1'h1;
        end
      default:
          _181_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _168_;
    (* src = "libresoc.v:22311.5-22311.29" *)
    casez (\initial )
      /* src = "libresoc.v:22311.9-22311.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _168_ = 1'h0;
        end
      default:
          _168_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = _166_;
    (* src = "libresoc.v:22320.5-22320.29" *)
    casez (\initial )
      /* src = "libresoc.v:22320.9-22320.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _166_ = 1'h1;
        end
      default:
          _166_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = _187_;
    (* src = "libresoc.v:22329.5-22329.29" *)
    casez (\initial )
      /* src = "libresoc.v:22329.9-22329.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _187_ = 4'h0;
        end
      default:
          _187_ = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = _185_;
    (* src = "libresoc.v:22338.5-22338.29" *)
    casez (\initial )
      /* src = "libresoc.v:22338.9-22338.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _185_ = 4'hf;
        end
      default:
          _185_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = _175_;
    (* src = "libresoc.v:22347.5-22347.29" *)
    casez (\initial )
      /* src = "libresoc.v:22347.9-22347.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 5'h00;
        end
      default:
          _175_ = \$67 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = _173_;
    (* src = "libresoc.v:22356.5-22356.29" *)
    casez (\initial )
      /* src = "libresoc.v:22356.9-22356.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 5'h1f;
        end
      default:
          _173_ = \$69 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _100_;
    _003_ = _102_;
    _009_ = _108_;
    _011_ = _110_;
    _013_ = _112_;
    _015_ = _114_;
    _017_ = _116_;
    _019_ = _118_;
    _021_ = _120_;
    _027_ = _126_;
    _033_ = _132_;
    _035_ = _134_;
    _005_ = _197_;
    _007_ = _198_;
    _023_ = _199_;
    _025_ = _200_;
    _029_ = _201_;
    _031_ = _202_;
    (* src = "libresoc.v:22365.5-22365.29" *)
    casez (\initial )
      /* src = "libresoc.v:22365.9-22365.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _110_, _100_, _120_, _118_, _126_, _108_, _132_, _116_, _134_, _114_, _124_, _122_, _128_, _130_, _106_, _104_, _102_, _112_ } = { oper_i_alu_alu0__insn, oper_i_alu_alu0__data_len, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__insn_type };
        end
      default:
        begin
          _100_ = alu_alu0_alu_op__data_len;
          _102_ = alu_alu0_alu_op__fn_unit;
          _104_ = alu_alu0_alu_op__imm_data__data;
          _106_ = alu_alu0_alu_op__imm_data__ok;
          _108_ = alu_alu0_alu_op__input_carry;
          _110_ = alu_alu0_alu_op__insn;
          _112_ = alu_alu0_alu_op__insn_type;
          _114_ = alu_alu0_alu_op__invert_in;
          _116_ = alu_alu0_alu_op__invert_out;
          _118_ = alu_alu0_alu_op__is_32bit;
          _120_ = alu_alu0_alu_op__is_signed;
          _122_ = alu_alu0_alu_op__oe__oe;
          _124_ = alu_alu0_alu_op__oe__ok;
          _126_ = alu_alu0_alu_op__output_carry;
          _128_ = alu_alu0_alu_op__rc__ok;
          _130_ = alu_alu0_alu_op__rc__rc;
          _132_ = alu_alu0_alu_op__write_cr0;
          _134_ = alu_alu0_alu_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _197_ = 64'h0000000000000000;
          _198_ = 1'h0;
          _202_ = 1'h0;
          _201_ = 1'h0;
          _199_ = 1'h0;
          _200_ = 1'h0;
        end
      default:
        begin
          _197_ = _104_;
          _198_ = _106_;
          _199_ = _122_;
          _200_ = _124_;
          _201_ = _128_;
          _202_ = _130_;
        end
    endcase
  end
  always @* begin
      \alu_alu0_alu_op__data_len$next  <= _001_;
      \alu_alu0_alu_op__fn_unit$next  <= _003_;
      \alu_alu0_alu_op__imm_data__data$next  <= _005_;
      \alu_alu0_alu_op__imm_data__ok$next  <= _007_;
      \alu_alu0_alu_op__input_carry$next  <= _009_;
      \alu_alu0_alu_op__insn$next  <= _011_;
      \alu_alu0_alu_op__insn_type$next  <= _013_;
      \alu_alu0_alu_op__invert_in$next  <= _015_;
      \alu_alu0_alu_op__invert_out$next  <= _017_;
      \alu_alu0_alu_op__is_32bit$next  <= _019_;
      \alu_alu0_alu_op__is_signed$next  <= _021_;
      \alu_alu0_alu_op__oe__oe$next  <= _023_;
      \alu_alu0_alu_op__oe__ok$next  <= _025_;
      \alu_alu0_alu_op__output_carry$next  <= _027_;
      \alu_alu0_alu_op__rc__ok$next  <= _029_;
      \alu_alu0_alu_op__rc__rc$next  <= _031_;
      \alu_alu0_alu_op__write_cr0$next  <= _033_;
      \alu_alu0_alu_op__zero_a$next  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _203_;
    _044_ = _213_;
    (* src = "libresoc.v:22404.5-22404.29" *)
    casez (\initial )
      /* src = "libresoc.v:22404.9-22404.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _143_, _141_ } = { o_ok, alu_alu0_o };
        end
      default:
        begin
          _141_ = data_r0__o;
          _143_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _204_, _203_ } = 65'h00000000000000000;
        end
      default:
        begin
          _203_ = _141_;
          _204_ = _143_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _213_ = 1'h0;
        end
      default:
          _213_ = _204_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _042_;
      \data_r0__o_ok$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _205_;
    _048_ = _214_;
    (* src = "libresoc.v:22426.5-22426.29" *)
    casez (\initial )
      /* src = "libresoc.v:22426.9-22426.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _147_, _145_ } = { cr_a_ok, alu_alu0_cr_a };
        end
      default:
        begin
          _145_ = data_r1__cr_a;
          _147_ = data_r1__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _206_, _205_ } = 5'h00;
        end
      default:
        begin
          _205_ = _145_;
          _206_ = _147_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _214_ = 1'h0;
        end
      default:
          _214_ = _206_;
    endcase
  end
  always @* begin
      \data_r1__cr_a$next  <= _046_;
      \data_r1__cr_a_ok$next  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _207_;
    _052_ = _215_;
    (* src = "libresoc.v:22448.5-22448.29" *)
    casez (\initial )
      /* src = "libresoc.v:22448.9-22448.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _151_, _149_ } = { xer_ca_ok, alu_alu0_xer_ca };
        end
      default:
        begin
          _149_ = data_r2__xer_ca;
          _151_ = data_r2__xer_ca_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _208_, _207_ } = 3'h0;
        end
      default:
        begin
          _207_ = _149_;
          _208_ = _151_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _215_ = 1'h0;
        end
      default:
          _215_ = _208_;
    endcase
  end
  always @* begin
      \data_r2__xer_ca$next  <= _050_;
      \data_r2__xer_ca_ok$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _209_;
    _056_ = _216_;
    (* src = "libresoc.v:22470.5-22470.29" *)
    casez (\initial )
      /* src = "libresoc.v:22470.9-22470.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _155_, _153_ } = { xer_ov_ok, alu_alu0_xer_ov };
        end
      default:
        begin
          _153_ = data_r3__xer_ov;
          _155_ = data_r3__xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _210_, _209_ } = 3'h0;
        end
      default:
        begin
          _209_ = _153_;
          _210_ = _155_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _216_ = 1'h0;
        end
      default:
          _216_ = _210_;
    endcase
  end
  always @* begin
      \data_r3__xer_ov$next  <= _054_;
      \data_r3__xer_ov_ok$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _211_;
    _060_ = _217_;
    (* src = "libresoc.v:22492.5-22492.29" *)
    casez (\initial )
      /* src = "libresoc.v:22492.9-22492.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _159_, _157_ } = { xer_so_ok, alu_alu0_xer_so };
        end
      default:
        begin
          _157_ = data_r4__xer_so;
          _159_ = data_r4__xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _212_, _211_ } = 2'h0;
        end
      default:
        begin
          _211_ = _157_;
          _212_ = _159_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _217_ = 1'h0;
        end
      default:
          _217_ = _212_;
    endcase
  end
  always @* begin
      \data_r4__xer_so$next  <= _058_;
      \data_r4__xer_so_ok$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = _189_;
    (* src = "libresoc.v:22514.5-22514.29" *)
    casez (\initial )
      /* src = "libresoc.v:22514.9-22514.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _189_ = src_or_imm;
        end
      default:
          _189_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = _191_;
    (* src = "libresoc.v:22524.5-22524.29" *)
    casez (\initial )
      /* src = "libresoc.v:22524.9-22524.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (\src_sel$85 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _191_ = \src_or_imm$88 ;
        end
      default:
          _191_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = _193_;
    (* src = "libresoc.v:22534.5-22534.29" *)
    casez (\initial )
      /* src = "libresoc.v:22534.9-22534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _193_ = src3_i;
        end
      default:
          _193_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = _195_;
    (* src = "libresoc.v:22544.5-22544.29" *)
    casez (\initial )
      /* src = "libresoc.v:22544.9-22544.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[3])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _195_ = src4_i;
        end
      default:
          _195_ = src_r3;
    endcase
  end
  always @* begin
      \src_r3$next  <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _139_;
    (* src = "libresoc.v:22554.5-22554.29" *)
    casez (\initial )
      /* src = "libresoc.v:22554.9-22554.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _139_ = 1'h1;
        end
      default:
          _139_ = \$99 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _137_;
    (* src = "libresoc.v:22563.5-22563.29" *)
    casez (\initial )
      /* src = "libresoc.v:22563.9-22563.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _137_ = 1'h1;
        end
      default:
          _137_ = \$101 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _161_;
    (* src = "libresoc.v:22572.5-22572.29" *)
    casez (\initial )
      /* src = "libresoc.v:22572.9-22572.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$129 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _161_ = data_r0__o;
        end
      default:
          _161_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = _162_;
    (* src = "libresoc.v:22582.5-22582.29" *)
    casez (\initial )
      /* src = "libresoc.v:22582.9-22582.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$131 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _162_ = data_r1__cr_a;
        end
      default:
          _162_ = 4'h0;
    endcase
  end
  always @* begin
      dest2_o <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _163_;
    (* src = "libresoc.v:22592.5-22592.29" *)
    casez (\initial )
      /* src = "libresoc.v:22592.9-22592.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$133 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _163_ = data_r2__xer_ca;
        end
      default:
          _163_ = 2'h0;
    endcase
  end
  always @* begin
      dest3_o <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _164_;
    (* src = "libresoc.v:22602.5-22602.29" *)
    casez (\initial )
      /* src = "libresoc.v:22602.9-22602.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$135 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _164_ = data_r3__xer_ov;
        end
      default:
          _164_ = 2'h0;
    endcase
  end
  always @* begin
      dest4_o <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _165_;
    (* src = "libresoc.v:22612.5-22612.29" *)
    casez (\initial )
      /* src = "libresoc.v:22612.9-22612.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$137 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _165_ = data_r4__xer_so;
        end
      default:
          _165_ = 1'h0;
    endcase
  end
  always @* begin
      dest5_o <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _170_;
    (* src = "libresoc.v:22622.5-22622.29" *)
    casez (\initial )
      /* src = "libresoc.v:22622.9-22622.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _170_ = 5'h00;
        end
      default:
          _170_ = \$21 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _072_;
  end
  assign \$5  = _273_;
  assign \$99  = _218_;
  assign \$101  = _219_;
  assign \$103  = _220_;
  assign \$105  = _257_;
  assign \$107  = _258_;
  assign \$109  = _221_;
  assign \$111  = _259_;
  assign \$113  = _222_;
  assign \$115  = _223_;
  assign \$117  = _224_;
  assign \$11  = _225_;
  assign \$119  = _226_;
  assign \$121  = _227_;
  assign \$123  = _228_;
  assign \$125  = _229_;
  assign \$127  = _230_;
  assign \$129  = _231_;
  assign \$131  = _232_;
  assign \$133  = _233_;
  assign \$135  = _234_;
  assign \$137  = _235_;
  assign \$13  = _260_;
  assign \$15  = _236_;
  assign \$17  = _261_;
  assign \$19  = _237_;
  assign \$21  = _238_;
  assign \$25  = _262_;
  assign \$27  = _239_;
  assign \$24  = _274_;
  assign \$23  = _263_;
  assign \$31  = _240_;
  assign \$33  = _275_;
  assign \$35  = _276_;
  assign \$37  = _266_;
  assign \$3  = _241_;
  assign \$39  = _264_;
  assign \$41  = _242_;
  assign \$43  = _243_;
  assign \$45  = _255_;
  assign \$47  = _244_;
  assign \$49  = _256_;
  assign \$51  = _245_;
  assign \$53  = _246_;
  assign \$55  = _247_;
  assign \$57  = _267_;
  assign \$59  = _268_;
  assign \$61  = _269_;
  assign \$63  = _270_;
  assign \$65  = _248_;
  assign \$67  = _249_;
  assign \$6  = _265_;
  assign \$69  = _271_;
  assign \$71  = _250_;
  assign \$73  = _251_;
  assign \$75  = _252_;
  assign \$77  = _253_;
  assign \$79  = _254_;
  assign \$81  = _277_;
  assign \$83  = _278_;
  assign \$86  = _279_;
  assign \$8  = _272_;
  assign \$89  = _280_;
  assign \$91  = _281_;
  assign \$93  = _282_;
  assign \$95  = _283_;
  assign \$97  = _284_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$127 ;
  assign cu_rd__rel_o = \$113 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_alu0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_alu0_p_valid_i = alui_l_q_alui;
  assign \alu_alu0_xer_ca$2  = \$97 ;
  assign \alu_alu0_xer_so$1  = \$95 ;
  assign alu_alu0_rb = \$93 ;
  assign alu_alu0_ra = \$91 ;
  assign \src_or_imm$88  = \$89 ;
  assign \src_sel$85  = \$86 ;
  assign src_or_imm = \$83 ;
  assign src_sel = \$81 ;
  assign cu_wrmask_o = { \$79 , \$77 , \$75 , \$73 , \$71  };
  assign reset_r = \$63 ;
  assign reset_w = \$61 ;
  assign rst_r = \$59 ;
  assign reset = \$57 ;
  assign wr_any = \$37 ;
  assign cu_done_o = \$31 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$19 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_alu0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$15 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:22667.1-23745.10" *)
module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, cr_a, xer_ca, xer_ov, xer_so, ra, rb, \xer_so$1 , \xer_ca$2 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \alu_op__data_len$70 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \alu_op__fn_unit$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \alu_op__imm_data__data$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__imm_data__ok$57 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \alu_op__input_carry$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \alu_op__insn$71 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \alu_op__insn_type$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_in$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_out$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_32bit$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_signed$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__oe$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__ok$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__output_carry$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__ok$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__rc$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__write_cr0$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__zero_a$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] pipe1_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \pipe1_alu_op__data_len$20 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe1_alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe1_alu_op__fn_unit$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe1_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe1_alu_op__imm_data__data$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__imm_data__ok$7 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe1_alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe1_alu_op__input_carry$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe1_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe1_alu_op__insn$21 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe1_alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe1_alu_op__insn_type$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__invert_in$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__invert_out$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__is_32bit$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__is_signed$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__oe__oe$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__oe__ok$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__output_carry$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__rc__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__rc__rc$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__write_cr0$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_alu_op__zero_a$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] pipe1_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe1_muxid$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe1_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe1_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe1_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe1_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe1_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \pipe1_xer_ca$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe1_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \pipe1_xer_so$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] pipe2_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \pipe2_alu_op__data_len$41 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe2_alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe2_alu_op__fn_unit$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe2_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe2_alu_op__imm_data__data$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__imm_data__ok$28 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe2_alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe2_alu_op__input_carry$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe2_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe2_alu_op__insn$42 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe2_alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe2_alu_op__insn_type$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__invert_in$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__invert_out$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__is_32bit$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__is_signed$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__oe__oe$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__oe__ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__output_carry$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__rc__ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__rc__rc$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__write_cr0$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_alu_op__zero_a$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] pipe2_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \pipe2_cr_a$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_cr_a_ok$46 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe2_muxid$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe2_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe2_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe2_o$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_o_ok$44 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe2_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe2_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe2_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \pipe2_xer_ca$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_xer_ca_ok$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe2_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \pipe2_xer_ov$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_xer_ov_ok$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_xer_so$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_xer_so_ok$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ca$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:23584.5-23587.4" *)
  n n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:23588.5-23591.4" *)
  p p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:23592.9-23651.4" *)
  pipe1 pipe1 (
    .alu_op__data_len(pipe1_alu_op__data_len),
    .\alu_op__data_len$18 (\pipe1_alu_op__data_len$20 ),
    .alu_op__fn_unit(pipe1_alu_op__fn_unit),
    .\alu_op__fn_unit$3 (\pipe1_alu_op__fn_unit$5 ),
    .alu_op__imm_data__data(pipe1_alu_op__imm_data__data),
    .\alu_op__imm_data__data$4 (\pipe1_alu_op__imm_data__data$6 ),
    .alu_op__imm_data__ok(pipe1_alu_op__imm_data__ok),
    .\alu_op__imm_data__ok$5 (\pipe1_alu_op__imm_data__ok$7 ),
    .alu_op__input_carry(pipe1_alu_op__input_carry),
    .\alu_op__input_carry$14 (\pipe1_alu_op__input_carry$16 ),
    .alu_op__insn(pipe1_alu_op__insn),
    .\alu_op__insn$19 (\pipe1_alu_op__insn$21 ),
    .alu_op__insn_type(pipe1_alu_op__insn_type),
    .\alu_op__insn_type$2 (\pipe1_alu_op__insn_type$4 ),
    .alu_op__invert_in(pipe1_alu_op__invert_in),
    .\alu_op__invert_in$10 (\pipe1_alu_op__invert_in$12 ),
    .alu_op__invert_out(pipe1_alu_op__invert_out),
    .\alu_op__invert_out$12 (\pipe1_alu_op__invert_out$14 ),
    .alu_op__is_32bit(pipe1_alu_op__is_32bit),
    .\alu_op__is_32bit$16 (\pipe1_alu_op__is_32bit$18 ),
    .alu_op__is_signed(pipe1_alu_op__is_signed),
    .\alu_op__is_signed$17 (\pipe1_alu_op__is_signed$19 ),
    .alu_op__oe__oe(pipe1_alu_op__oe__oe),
    .\alu_op__oe__oe$8 (\pipe1_alu_op__oe__oe$10 ),
    .alu_op__oe__ok(pipe1_alu_op__oe__ok),
    .\alu_op__oe__ok$9 (\pipe1_alu_op__oe__ok$11 ),
    .alu_op__output_carry(pipe1_alu_op__output_carry),
    .\alu_op__output_carry$15 (\pipe1_alu_op__output_carry$17 ),
    .alu_op__rc__ok(pipe1_alu_op__rc__ok),
    .\alu_op__rc__ok$7 (\pipe1_alu_op__rc__ok$9 ),
    .alu_op__rc__rc(pipe1_alu_op__rc__rc),
    .\alu_op__rc__rc$6 (\pipe1_alu_op__rc__rc$8 ),
    .alu_op__write_cr0(pipe1_alu_op__write_cr0),
    .\alu_op__write_cr0$13 (\pipe1_alu_op__write_cr0$15 ),
    .alu_op__zero_a(pipe1_alu_op__zero_a),
    .\alu_op__zero_a$11 (\pipe1_alu_op__zero_a$13 ),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe1_cr_a),
    .cr_a_ok(pipe1_cr_a_ok),
    .muxid(pipe1_muxid),
    .\muxid$1 (\pipe1_muxid$3 ),
    .n_ready_i(pipe1_n_ready_i),
    .n_valid_o(pipe1_n_valid_o),
    .o(pipe1_o),
    .o_ok(pipe1_o_ok),
    .p_ready_o(pipe1_p_ready_o),
    .p_valid_i(pipe1_p_valid_i),
    .ra(pipe1_ra),
    .rb(pipe1_rb),
    .xer_ca(pipe1_xer_ca),
    .\xer_ca$21 (\pipe1_xer_ca$23 ),
    .xer_ca_ok(pipe1_xer_ca_ok),
    .xer_ov(pipe1_xer_ov),
    .xer_ov_ok(pipe1_xer_ov_ok),
    .xer_so(pipe1_xer_so),
    .\xer_so$20 (\pipe1_xer_so$22 ),
    .xer_so_ok(pipe1_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:23652.9-23717.4" *)
  pipe2 pipe2 (
    .alu_op__data_len(pipe2_alu_op__data_len),
    .\alu_op__data_len$18 (\pipe2_alu_op__data_len$41 ),
    .alu_op__fn_unit(pipe2_alu_op__fn_unit),
    .\alu_op__fn_unit$3 (\pipe2_alu_op__fn_unit$26 ),
    .alu_op__imm_data__data(pipe2_alu_op__imm_data__data),
    .\alu_op__imm_data__data$4 (\pipe2_alu_op__imm_data__data$27 ),
    .alu_op__imm_data__ok(pipe2_alu_op__imm_data__ok),
    .\alu_op__imm_data__ok$5 (\pipe2_alu_op__imm_data__ok$28 ),
    .alu_op__input_carry(pipe2_alu_op__input_carry),
    .\alu_op__input_carry$14 (\pipe2_alu_op__input_carry$37 ),
    .alu_op__insn(pipe2_alu_op__insn),
    .\alu_op__insn$19 (\pipe2_alu_op__insn$42 ),
    .alu_op__insn_type(pipe2_alu_op__insn_type),
    .\alu_op__insn_type$2 (\pipe2_alu_op__insn_type$25 ),
    .alu_op__invert_in(pipe2_alu_op__invert_in),
    .\alu_op__invert_in$10 (\pipe2_alu_op__invert_in$33 ),
    .alu_op__invert_out(pipe2_alu_op__invert_out),
    .\alu_op__invert_out$12 (\pipe2_alu_op__invert_out$35 ),
    .alu_op__is_32bit(pipe2_alu_op__is_32bit),
    .\alu_op__is_32bit$16 (\pipe2_alu_op__is_32bit$39 ),
    .alu_op__is_signed(pipe2_alu_op__is_signed),
    .\alu_op__is_signed$17 (\pipe2_alu_op__is_signed$40 ),
    .alu_op__oe__oe(pipe2_alu_op__oe__oe),
    .\alu_op__oe__oe$8 (\pipe2_alu_op__oe__oe$31 ),
    .alu_op__oe__ok(pipe2_alu_op__oe__ok),
    .\alu_op__oe__ok$9 (\pipe2_alu_op__oe__ok$32 ),
    .alu_op__output_carry(pipe2_alu_op__output_carry),
    .\alu_op__output_carry$15 (\pipe2_alu_op__output_carry$38 ),
    .alu_op__rc__ok(pipe2_alu_op__rc__ok),
    .\alu_op__rc__ok$7 (\pipe2_alu_op__rc__ok$30 ),
    .alu_op__rc__rc(pipe2_alu_op__rc__rc),
    .\alu_op__rc__rc$6 (\pipe2_alu_op__rc__rc$29 ),
    .alu_op__write_cr0(pipe2_alu_op__write_cr0),
    .\alu_op__write_cr0$13 (\pipe2_alu_op__write_cr0$36 ),
    .alu_op__zero_a(pipe2_alu_op__zero_a),
    .\alu_op__zero_a$11 (\pipe2_alu_op__zero_a$34 ),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe2_cr_a),
    .\cr_a$22 (\pipe2_cr_a$45 ),
    .cr_a_ok(pipe2_cr_a_ok),
    .\cr_a_ok$23 (\pipe2_cr_a_ok$46 ),
    .muxid(pipe2_muxid),
    .\muxid$1 (\pipe2_muxid$24 ),
    .n_ready_i(pipe2_n_ready_i),
    .n_valid_o(pipe2_n_valid_o),
    .o(pipe2_o),
    .\o$20 (\pipe2_o$43 ),
    .o_ok(pipe2_o_ok),
    .\o_ok$21 (\pipe2_o_ok$44 ),
    .p_ready_o(pipe2_p_ready_o),
    .p_valid_i(pipe2_p_valid_i),
    .xer_ca(pipe2_xer_ca),
    .\xer_ca$24 (\pipe2_xer_ca$47 ),
    .xer_ca_ok(pipe2_xer_ca_ok),
    .\xer_ca_ok$25 (\pipe2_xer_ca_ok$48 ),
    .xer_ov(pipe2_xer_ov),
    .\xer_ov$26 (\pipe2_xer_ov$49 ),
    .xer_ov_ok(pipe2_xer_ov_ok),
    .\xer_ov_ok$27 (\pipe2_xer_ov_ok$50 ),
    .xer_so(pipe2_xer_so),
    .\xer_so$28 (\pipe2_xer_so$51 ),
    .xer_so_ok(pipe2_xer_so_ok),
    .\xer_so_ok$29 (\pipe2_xer_so_ok$52 )
  );
  assign muxid = 2'h0;
  assign { xer_so_ok, xer_so } = { \pipe2_xer_so_ok$52 , \pipe2_xer_so$51  };
  assign { xer_ov_ok, xer_ov } = { \pipe2_xer_ov_ok$50 , \pipe2_xer_ov$49  };
  assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$48 , \pipe2_xer_ca$47  };
  assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$46 , \pipe2_cr_a$45  };
  assign { o_ok, o } = { \pipe2_o_ok$44 , \pipe2_o$43  };
  assign { \alu_op__insn$71 , \alu_op__data_len$70 , \alu_op__is_signed$69 , \alu_op__is_32bit$68 , \alu_op__output_carry$67 , \alu_op__input_carry$66 , \alu_op__write_cr0$65 , \alu_op__invert_out$64 , \alu_op__zero_a$63 , \alu_op__invert_in$62 , \alu_op__oe__ok$61 , \alu_op__oe__oe$60 , \alu_op__rc__ok$59 , \alu_op__rc__rc$58 , \alu_op__imm_data__ok$57 , \alu_op__imm_data__data$56 , \alu_op__fn_unit$55 , \alu_op__insn_type$54  } = { \pipe2_alu_op__insn$42 , \pipe2_alu_op__data_len$41 , \pipe2_alu_op__is_signed$40 , \pipe2_alu_op__is_32bit$39 , \pipe2_alu_op__output_carry$38 , \pipe2_alu_op__input_carry$37 , \pipe2_alu_op__write_cr0$36 , \pipe2_alu_op__invert_out$35 , \pipe2_alu_op__zero_a$34 , \pipe2_alu_op__invert_in$33 , \pipe2_alu_op__oe__ok$32 , \pipe2_alu_op__oe__oe$31 , \pipe2_alu_op__rc__ok$30 , \pipe2_alu_op__rc__rc$29 , \pipe2_alu_op__imm_data__ok$28 , \pipe2_alu_op__imm_data__data$27 , \pipe2_alu_op__fn_unit$26 , \pipe2_alu_op__insn_type$25  };
  assign \muxid$53  = \pipe2_muxid$24 ;
  assign pipe2_n_ready_i = n_ready_i;
  assign n_valid_o = pipe2_n_valid_o;
  assign \pipe1_xer_ca$23  = \xer_ca$2 ;
  assign \pipe1_xer_so$22  = \xer_so$1 ;
  assign pipe1_rb = rb;
  assign pipe1_ra = ra;
  assign { \pipe1_alu_op__insn$21 , \pipe1_alu_op__data_len$20 , \pipe1_alu_op__is_signed$19 , \pipe1_alu_op__is_32bit$18 , \pipe1_alu_op__output_carry$17 , \pipe1_alu_op__input_carry$16 , \pipe1_alu_op__write_cr0$15 , \pipe1_alu_op__invert_out$14 , \pipe1_alu_op__zero_a$13 , \pipe1_alu_op__invert_in$12 , \pipe1_alu_op__oe__ok$11 , \pipe1_alu_op__oe__oe$10 , \pipe1_alu_op__rc__ok$9 , \pipe1_alu_op__rc__rc$8 , \pipe1_alu_op__imm_data__ok$7 , \pipe1_alu_op__imm_data__data$6 , \pipe1_alu_op__fn_unit$5 , \pipe1_alu_op__insn_type$4  } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
  assign \pipe1_muxid$3  = 2'h0;
  assign p_ready_o = pipe1_p_ready_o;
  assign pipe1_p_valid_i = p_valid_i;
  assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so };
  assign { pipe2_xer_ov_ok, pipe2_xer_ov } = { pipe1_xer_ov_ok, pipe1_xer_ov };
  assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca };
  assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a };
  assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o };
  assign { pipe2_alu_op__insn, pipe2_alu_op__data_len, pipe2_alu_op__is_signed, pipe2_alu_op__is_32bit, pipe2_alu_op__output_carry, pipe2_alu_op__input_carry, pipe2_alu_op__write_cr0, pipe2_alu_op__invert_out, pipe2_alu_op__zero_a, pipe2_alu_op__invert_in, pipe2_alu_op__oe__ok, pipe2_alu_op__oe__oe, pipe2_alu_op__rc__ok, pipe2_alu_op__rc__rc, pipe2_alu_op__imm_data__ok, pipe2_alu_op__imm_data__data, pipe2_alu_op__fn_unit, pipe2_alu_op__insn_type } = { pipe1_alu_op__insn, pipe1_alu_op__data_len, pipe1_alu_op__is_signed, pipe1_alu_op__is_32bit, pipe1_alu_op__output_carry, pipe1_alu_op__input_carry, pipe1_alu_op__write_cr0, pipe1_alu_op__invert_out, pipe1_alu_op__zero_a, pipe1_alu_op__invert_in, pipe1_alu_op__oe__ok, pipe1_alu_op__oe__oe, pipe1_alu_op__rc__ok, pipe1_alu_op__rc__rc, pipe1_alu_op__imm_data__ok, pipe1_alu_op__imm_data__data, pipe1_alu_op__fn_unit, pipe1_alu_op__insn_type };
  assign pipe2_muxid = pipe1_muxid;
  assign pipe1_n_ready_i = pipe2_p_ready_o;
  assign pipe2_p_valid_i = pipe1_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:23749.1-24296.10" *)
module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_i, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, nia, \fast1$1 , \fast2$2 , cr_a, p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \br_op__cia$15 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] br_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \br_op__fn_unit$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \br_op__imm_data__data$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__imm_data__ok$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \br_op__insn$18 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] br_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \br_op__insn_type$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__is_32bit$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__lk$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast1$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast2$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe_br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe_br_op__cia$4 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_br_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_br_op__fn_unit$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe_br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe_br_op__imm_data__data$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_br_op__imm_data__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_br_op__insn$7 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_br_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_br_op__insn_type$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_br_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_br_op__lk$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] pipe_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe_fast1$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe_fast2$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_muxid$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe_nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_nia_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_p_valid_i;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24238.10-24241.4" *)
  \n$18  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24242.10-24245.4" *)
  \p$17  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24246.13-24280.4" *)
  \pipe$19  pipe (
    .br_op__cia(pipe_br_op__cia),
    .\br_op__cia$2 (\pipe_br_op__cia$4 ),
    .br_op__fn_unit(pipe_br_op__fn_unit),
    .\br_op__fn_unit$4 (\pipe_br_op__fn_unit$6 ),
    .br_op__imm_data__data(pipe_br_op__imm_data__data),
    .\br_op__imm_data__data$6 (\pipe_br_op__imm_data__data$8 ),
    .br_op__imm_data__ok(pipe_br_op__imm_data__ok),
    .\br_op__imm_data__ok$7 (\pipe_br_op__imm_data__ok$9 ),
    .br_op__insn(pipe_br_op__insn),
    .\br_op__insn$5 (\pipe_br_op__insn$7 ),
    .br_op__insn_type(pipe_br_op__insn_type),
    .\br_op__insn_type$3 (\pipe_br_op__insn_type$5 ),
    .br_op__is_32bit(pipe_br_op__is_32bit),
    .\br_op__is_32bit$9 (\pipe_br_op__is_32bit$11 ),
    .br_op__lk(pipe_br_op__lk),
    .\br_op__lk$8 (\pipe_br_op__lk$10 ),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe_cr_a),
    .fast1(pipe_fast1),
    .\fast1$10 (\pipe_fast1$12 ),
    .fast1_ok(pipe_fast1_ok),
    .fast2(pipe_fast2),
    .\fast2$11 (\pipe_fast2$13 ),
    .fast2_ok(pipe_fast2_ok),
    .muxid(pipe_muxid),
    .\muxid$1 (\pipe_muxid$3 ),
    .n_ready_i(pipe_n_ready_i),
    .n_valid_o(pipe_n_valid_o),
    .nia(pipe_nia),
    .nia_ok(pipe_nia_ok),
    .p_ready_o(pipe_p_ready_o),
    .p_valid_i(pipe_p_valid_i)
  );
  assign muxid = 2'h0;
  assign { nia_ok, nia } = { pipe_nia_ok, pipe_nia };
  assign { fast2_ok, fast2 } = { pipe_fast2_ok, \pipe_fast2$13  };
  assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12  };
  assign { \br_op__is_32bit$22 , \br_op__lk$21 , \br_op__imm_data__ok$20 , \br_op__imm_data__data$19 , \br_op__insn$18 , \br_op__fn_unit$17 , \br_op__insn_type$16 , \br_op__cia$15  } = { \pipe_br_op__is_32bit$11 , \pipe_br_op__lk$10 , \pipe_br_op__imm_data__ok$9 , \pipe_br_op__imm_data__data$8 , \pipe_br_op__insn$7 , \pipe_br_op__fn_unit$6 , \pipe_br_op__insn_type$5 , \pipe_br_op__cia$4  };
  assign \muxid$14  = \pipe_muxid$3 ;
  assign pipe_n_ready_i = n_ready_i;
  assign n_valid_o = pipe_n_valid_o;
  assign pipe_cr_a = cr_a;
  assign pipe_fast2 = \fast2$2 ;
  assign pipe_fast1 = \fast1$1 ;
  assign { pipe_br_op__is_32bit, pipe_br_op__lk, pipe_br_op__imm_data__ok, pipe_br_op__imm_data__data, pipe_br_op__insn, pipe_br_op__fn_unit, pipe_br_op__insn_type, pipe_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
  assign pipe_muxid = 2'h0;
  assign p_ready_o = pipe_p_ready_o;
  assign pipe_p_valid_i = p_valid_i;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:24300.1-24815.10" *)
module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] \cr_a$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] cr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \cr_op__fn_unit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \cr_op__insn$12 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] cr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \cr_op__insn_type$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [31:0] full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [31:0] \full_cr$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] pipe_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \pipe_cr_a$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] pipe_cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] pipe_cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_cr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_cr_op__fn_unit$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_cr_op__insn$6 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_cr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_cr_op__insn_type$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [31:0] pipe_full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [31:0] \pipe_full_cr$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_muxid$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24761.9-24764.4" *)
  \n$6  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24765.9-24768.4" *)
  \p$5  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:24769.8-24796.4" *)
  pipe pipe (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe_cr_a),
    .\cr_a$6 (\pipe_cr_a$8 ),
    .cr_a_ok(pipe_cr_a_ok),
    .cr_b(pipe_cr_b),
    .cr_c(pipe_cr_c),
    .cr_op__fn_unit(pipe_cr_op__fn_unit),
    .\cr_op__fn_unit$3 (\pipe_cr_op__fn_unit$5 ),
    .cr_op__insn(pipe_cr_op__insn),
    .\cr_op__insn$4 (\pipe_cr_op__insn$6 ),
    .cr_op__insn_type(pipe_cr_op__insn_type),
    .\cr_op__insn_type$2 (\pipe_cr_op__insn_type$4 ),
    .full_cr(pipe_full_cr),
    .\full_cr$5 (\pipe_full_cr$7 ),
    .full_cr_ok(pipe_full_cr_ok),
    .muxid(pipe_muxid),
    .\muxid$1 (\pipe_muxid$3 ),
    .n_ready_i(pipe_n_ready_i),
    .n_valid_o(pipe_n_valid_o),
    .o(pipe_o),
    .o_ok(pipe_o_ok),
    .p_ready_o(pipe_p_ready_o),
    .p_valid_i(pipe_p_valid_i),
    .ra(pipe_ra),
    .rb(pipe_rb)
  );
  assign muxid = 2'h0;
  assign { cr_a_ok, cr_a } = { pipe_cr_a_ok, \pipe_cr_a$8  };
  assign { full_cr_ok, full_cr } = { pipe_full_cr_ok, \pipe_full_cr$7  };
  assign { o_ok, o } = { pipe_o_ok, pipe_o };
  assign { \cr_op__insn$12 , \cr_op__fn_unit$11 , \cr_op__insn_type$10  } = { \pipe_cr_op__insn$6 , \pipe_cr_op__fn_unit$5 , \pipe_cr_op__insn_type$4  };
  assign \muxid$9  = \pipe_muxid$3 ;
  assign pipe_n_ready_i = n_ready_i;
  assign n_valid_o = pipe_n_valid_o;
  assign pipe_cr_c = cr_c;
  assign pipe_cr_b = cr_b;
  assign pipe_cr_a = \cr_a$2 ;
  assign pipe_full_cr = \full_cr$1 ;
  assign pipe_rb = rb;
  assign pipe_ra = ra;
  assign { pipe_cr_op__insn, pipe_cr_op__fn_unit, pipe_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
  assign pipe_muxid = 2'h0;
  assign p_ready_o = pipe_p_ready_o;
  assign pipe_p_valid_i = p_valid_i;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:24819.1-26284.10" *)
module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$88 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$75 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$89 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$71 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] pipe_end_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_end_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire pipe_end_div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire pipe_end_dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire pipe_end_dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire pipe_end_dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire pipe_end_divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] pipe_end_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \pipe_end_logical_op__data_len$68 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_end_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_end_logical_op__fn_unit$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe_end_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe_end_logical_op__imm_data__data$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__imm_data__ok$55 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe_end_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe_end_logical_op__input_carry$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_end_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_end_logical_op__insn$69 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_end_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_end_logical_op__insn_type$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__invert_in$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__invert_out$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__is_32bit$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__is_signed$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__oe__oe$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__oe__ok$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__output_carry$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__rc__ok$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__rc__rc$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__write_cr0$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_end_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_end_logical_op__zero_a$61 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_end_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_end_muxid$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_end_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_end_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe_end_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_end_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_end_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_end_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  wire [63:0] pipe_end_quotient_root;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_end_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_end_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  wire [191:0] pipe_end_remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe_end_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_end_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire pipe_end_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe_end_xer_so$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_end_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire pipe_middle_0_div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire \pipe_middle_0_div_by_zero$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire pipe_middle_0_dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire \pipe_middle_0_dive_abs_ov32$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire pipe_middle_0_dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire \pipe_middle_0_dive_abs_ov64$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  wire [127:0] pipe_middle_0_dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire pipe_middle_0_dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire \pipe_middle_0_dividend_neg$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire pipe_middle_0_divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire \pipe_middle_0_divisor_neg$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  wire [63:0] pipe_middle_0_divisor_radicand;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] pipe_middle_0_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \pipe_middle_0_logical_op__data_len$41 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_middle_0_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_middle_0_logical_op__fn_unit$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe_middle_0_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe_middle_0_logical_op__imm_data__data$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__imm_data__ok$28 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe_middle_0_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe_middle_0_logical_op__input_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_middle_0_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_middle_0_logical_op__insn$42 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_middle_0_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_middle_0_logical_op__insn_type$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__invert_in$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__invert_out$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__is_32bit$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__is_signed$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__oe__oe$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__oe__ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__output_carry$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__rc__ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__rc__rc$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__write_cr0$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_middle_0_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_middle_0_logical_op__zero_a$34 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_middle_0_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_middle_0_muxid$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_middle_0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_middle_0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  wire [1:0] pipe_middle_0_operation;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_middle_0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_middle_0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  wire [63:0] pipe_middle_0_quotient_root;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_middle_0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe_middle_0_ra$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_middle_0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe_middle_0_rb$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  wire [191:0] pipe_middle_0_remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire pipe_middle_0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \pipe_middle_0_xer_so$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire pipe_start_div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire pipe_start_dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire pipe_start_dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  wire [127:0] pipe_start_dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire pipe_start_dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire pipe_start_divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  wire [63:0] pipe_start_divisor_radicand;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] pipe_start_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \pipe_start_logical_op__data_len$19 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_start_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_start_logical_op__fn_unit$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe_start_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe_start_logical_op__imm_data__data$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__imm_data__ok$6 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe_start_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe_start_logical_op__input_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_start_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_start_logical_op__insn$20 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_start_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_start_logical_op__insn_type$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__invert_out$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__is_32bit$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__is_signed$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__oe__oe$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__oe__ok$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__output_carry$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__rc__ok$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__rc__rc$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__write_cr0$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_start_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_start_logical_op__zero_a$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_start_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_start_muxid$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_start_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_start_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  wire [1:0] pipe_start_operation;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_start_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_start_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_start_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe_start_ra$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_start_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe_start_rb$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire pipe_start_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \pipe_start_xer_so$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:26040.10-26043.4" *)
  \n$75  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:26044.10-26047.4" *)
  \p$74  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:26048.12-26111.4" *)
  pipe_end pipe_end (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe_end_cr_a),
    .cr_a_ok(pipe_end_cr_a_ok),
    .div_by_zero(pipe_end_div_by_zero),
    .dive_abs_ov32(pipe_end_dive_abs_ov32),
    .dive_abs_ov64(pipe_end_dive_abs_ov64),
    .dividend_neg(pipe_end_dividend_neg),
    .divisor_neg(pipe_end_divisor_neg),
    .logical_op__data_len(pipe_end_logical_op__data_len),
    .\logical_op__data_len$18 (\pipe_end_logical_op__data_len$68 ),
    .logical_op__fn_unit(pipe_end_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\pipe_end_logical_op__fn_unit$53 ),
    .logical_op__imm_data__data(pipe_end_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\pipe_end_logical_op__imm_data__data$54 ),
    .logical_op__imm_data__ok(pipe_end_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\pipe_end_logical_op__imm_data__ok$55 ),
    .logical_op__input_carry(pipe_end_logical_op__input_carry),
    .\logical_op__input_carry$12 (\pipe_end_logical_op__input_carry$62 ),
    .logical_op__insn(pipe_end_logical_op__insn),
    .\logical_op__insn$19 (\pipe_end_logical_op__insn$69 ),
    .logical_op__insn_type(pipe_end_logical_op__insn_type),
    .\logical_op__insn_type$2 (\pipe_end_logical_op__insn_type$52 ),
    .logical_op__invert_in(pipe_end_logical_op__invert_in),
    .\logical_op__invert_in$10 (\pipe_end_logical_op__invert_in$60 ),
    .logical_op__invert_out(pipe_end_logical_op__invert_out),
    .\logical_op__invert_out$13 (\pipe_end_logical_op__invert_out$63 ),
    .logical_op__is_32bit(pipe_end_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\pipe_end_logical_op__is_32bit$66 ),
    .logical_op__is_signed(pipe_end_logical_op__is_signed),
    .\logical_op__is_signed$17 (\pipe_end_logical_op__is_signed$67 ),
    .logical_op__oe__oe(pipe_end_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\pipe_end_logical_op__oe__oe$58 ),
    .logical_op__oe__ok(pipe_end_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\pipe_end_logical_op__oe__ok$59 ),
    .logical_op__output_carry(pipe_end_logical_op__output_carry),
    .\logical_op__output_carry$15 (\pipe_end_logical_op__output_carry$65 ),
    .logical_op__rc__ok(pipe_end_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\pipe_end_logical_op__rc__ok$57 ),
    .logical_op__rc__rc(pipe_end_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\pipe_end_logical_op__rc__rc$56 ),
    .logical_op__write_cr0(pipe_end_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\pipe_end_logical_op__write_cr0$64 ),
    .logical_op__zero_a(pipe_end_logical_op__zero_a),
    .\logical_op__zero_a$11 (\pipe_end_logical_op__zero_a$61 ),
    .muxid(pipe_end_muxid),
    .\muxid$1 (\pipe_end_muxid$51 ),
    .n_ready_i(pipe_end_n_ready_i),
    .n_valid_o(pipe_end_n_valid_o),
    .o(pipe_end_o),
    .o_ok(pipe_end_o_ok),
    .p_ready_o(pipe_end_p_ready_o),
    .p_valid_i(pipe_end_p_valid_i),
    .quotient_root(pipe_end_quotient_root),
    .ra(pipe_end_ra),
    .rb(pipe_end_rb),
    .remainder(pipe_end_remainder),
    .xer_ov(pipe_end_xer_ov),
    .xer_ov_ok(pipe_end_xer_ov_ok),
    .xer_so(pipe_end_xer_so),
    .\xer_so$20 (\pipe_end_xer_so$70 ),
    .xer_so_ok(pipe_end_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:26112.17-26178.4" *)
  pipe_middle_0 pipe_middle_0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .div_by_zero(pipe_middle_0_div_by_zero),
    .\div_by_zero$27 (\pipe_middle_0_div_by_zero$50 ),
    .dive_abs_ov32(pipe_middle_0_dive_abs_ov32),
    .\dive_abs_ov32$25 (\pipe_middle_0_dive_abs_ov32$48 ),
    .dive_abs_ov64(pipe_middle_0_dive_abs_ov64),
    .\dive_abs_ov64$26 (\pipe_middle_0_dive_abs_ov64$49 ),
    .dividend(pipe_middle_0_dividend),
    .dividend_neg(pipe_middle_0_dividend_neg),
    .\dividend_neg$24 (\pipe_middle_0_dividend_neg$47 ),
    .divisor_neg(pipe_middle_0_divisor_neg),
    .\divisor_neg$23 (\pipe_middle_0_divisor_neg$46 ),
    .divisor_radicand(pipe_middle_0_divisor_radicand),
    .logical_op__data_len(pipe_middle_0_logical_op__data_len),
    .\logical_op__data_len$18 (\pipe_middle_0_logical_op__data_len$41 ),
    .logical_op__fn_unit(pipe_middle_0_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\pipe_middle_0_logical_op__fn_unit$26 ),
    .logical_op__imm_data__data(pipe_middle_0_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\pipe_middle_0_logical_op__imm_data__data$27 ),
    .logical_op__imm_data__ok(pipe_middle_0_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\pipe_middle_0_logical_op__imm_data__ok$28 ),
    .logical_op__input_carry(pipe_middle_0_logical_op__input_carry),
    .\logical_op__input_carry$12 (\pipe_middle_0_logical_op__input_carry$35 ),
    .logical_op__insn(pipe_middle_0_logical_op__insn),
    .\logical_op__insn$19 (\pipe_middle_0_logical_op__insn$42 ),
    .logical_op__insn_type(pipe_middle_0_logical_op__insn_type),
    .\logical_op__insn_type$2 (\pipe_middle_0_logical_op__insn_type$25 ),
    .logical_op__invert_in(pipe_middle_0_logical_op__invert_in),
    .\logical_op__invert_in$10 (\pipe_middle_0_logical_op__invert_in$33 ),
    .logical_op__invert_out(pipe_middle_0_logical_op__invert_out),
    .\logical_op__invert_out$13 (\pipe_middle_0_logical_op__invert_out$36 ),
    .logical_op__is_32bit(pipe_middle_0_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\pipe_middle_0_logical_op__is_32bit$39 ),
    .logical_op__is_signed(pipe_middle_0_logical_op__is_signed),
    .\logical_op__is_signed$17 (\pipe_middle_0_logical_op__is_signed$40 ),
    .logical_op__oe__oe(pipe_middle_0_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\pipe_middle_0_logical_op__oe__oe$31 ),
    .logical_op__oe__ok(pipe_middle_0_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\pipe_middle_0_logical_op__oe__ok$32 ),
    .logical_op__output_carry(pipe_middle_0_logical_op__output_carry),
    .\logical_op__output_carry$15 (\pipe_middle_0_logical_op__output_carry$38 ),
    .logical_op__rc__ok(pipe_middle_0_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\pipe_middle_0_logical_op__rc__ok$30 ),
    .logical_op__rc__rc(pipe_middle_0_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\pipe_middle_0_logical_op__rc__rc$29 ),
    .logical_op__write_cr0(pipe_middle_0_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\pipe_middle_0_logical_op__write_cr0$37 ),
    .logical_op__zero_a(pipe_middle_0_logical_op__zero_a),
    .\logical_op__zero_a$11 (\pipe_middle_0_logical_op__zero_a$34 ),
    .muxid(pipe_middle_0_muxid),
    .\muxid$1 (\pipe_middle_0_muxid$24 ),
    .n_ready_i(pipe_middle_0_n_ready_i),
    .n_valid_o(pipe_middle_0_n_valid_o),
    .operation(pipe_middle_0_operation),
    .p_ready_o(pipe_middle_0_p_ready_o),
    .p_valid_i(pipe_middle_0_p_valid_i),
    .quotient_root(pipe_middle_0_quotient_root),
    .ra(pipe_middle_0_ra),
    .\ra$20 (\pipe_middle_0_ra$43 ),
    .rb(pipe_middle_0_rb),
    .\rb$21 (\pipe_middle_0_rb$44 ),
    .remainder(pipe_middle_0_remainder),
    .xer_so(pipe_middle_0_xer_so),
    .\xer_so$22 (\pipe_middle_0_xer_so$45 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:26179.14-26238.4" *)
  pipe_start pipe_start (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .div_by_zero(pipe_start_div_by_zero),
    .dive_abs_ov32(pipe_start_dive_abs_ov32),
    .dive_abs_ov64(pipe_start_dive_abs_ov64),
    .dividend(pipe_start_dividend),
    .dividend_neg(pipe_start_dividend_neg),
    .divisor_neg(pipe_start_divisor_neg),
    .divisor_radicand(pipe_start_divisor_radicand),
    .logical_op__data_len(pipe_start_logical_op__data_len),
    .\logical_op__data_len$18 (\pipe_start_logical_op__data_len$19 ),
    .logical_op__fn_unit(pipe_start_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\pipe_start_logical_op__fn_unit$4 ),
    .logical_op__imm_data__data(pipe_start_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\pipe_start_logical_op__imm_data__data$5 ),
    .logical_op__imm_data__ok(pipe_start_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\pipe_start_logical_op__imm_data__ok$6 ),
    .logical_op__input_carry(pipe_start_logical_op__input_carry),
    .\logical_op__input_carry$12 (\pipe_start_logical_op__input_carry$13 ),
    .logical_op__insn(pipe_start_logical_op__insn),
    .\logical_op__insn$19 (\pipe_start_logical_op__insn$20 ),
    .logical_op__insn_type(pipe_start_logical_op__insn_type),
    .\logical_op__insn_type$2 (\pipe_start_logical_op__insn_type$3 ),
    .logical_op__invert_in(pipe_start_logical_op__invert_in),
    .\logical_op__invert_in$10 (\pipe_start_logical_op__invert_in$11 ),
    .logical_op__invert_out(pipe_start_logical_op__invert_out),
    .\logical_op__invert_out$13 (\pipe_start_logical_op__invert_out$14 ),
    .logical_op__is_32bit(pipe_start_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\pipe_start_logical_op__is_32bit$17 ),
    .logical_op__is_signed(pipe_start_logical_op__is_signed),
    .\logical_op__is_signed$17 (\pipe_start_logical_op__is_signed$18 ),
    .logical_op__oe__oe(pipe_start_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\pipe_start_logical_op__oe__oe$9 ),
    .logical_op__oe__ok(pipe_start_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\pipe_start_logical_op__oe__ok$10 ),
    .logical_op__output_carry(pipe_start_logical_op__output_carry),
    .\logical_op__output_carry$15 (\pipe_start_logical_op__output_carry$16 ),
    .logical_op__rc__ok(pipe_start_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\pipe_start_logical_op__rc__ok$8 ),
    .logical_op__rc__rc(pipe_start_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\pipe_start_logical_op__rc__rc$7 ),
    .logical_op__write_cr0(pipe_start_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\pipe_start_logical_op__write_cr0$15 ),
    .logical_op__zero_a(pipe_start_logical_op__zero_a),
    .\logical_op__zero_a$11 (\pipe_start_logical_op__zero_a$12 ),
    .muxid(pipe_start_muxid),
    .\muxid$1 (\pipe_start_muxid$2 ),
    .n_ready_i(pipe_start_n_ready_i),
    .n_valid_o(pipe_start_n_valid_o),
    .operation(pipe_start_operation),
    .p_ready_o(pipe_start_p_ready_o),
    .p_valid_i(pipe_start_p_valid_i),
    .ra(pipe_start_ra),
    .\ra$20 (\pipe_start_ra$21 ),
    .rb(pipe_start_rb),
    .\rb$21 (\pipe_start_rb$22 ),
    .xer_so(pipe_start_xer_so),
    .\xer_so$22 (\pipe_start_xer_so$23 )
  );
  assign muxid = 2'h0;
  assign { xer_so_ok, xer_so } = { pipe_end_xer_so_ok, \pipe_end_xer_so$70  };
  assign { xer_ov_ok, xer_ov } = { pipe_end_xer_ov_ok, pipe_end_xer_ov };
  assign { cr_a_ok, cr_a } = { pipe_end_cr_a_ok, pipe_end_cr_a };
  assign { o_ok, o } = { pipe_end_o_ok, pipe_end_o };
  assign { \logical_op__insn$89 , \logical_op__data_len$88 , \logical_op__is_signed$87 , \logical_op__is_32bit$86 , \logical_op__output_carry$85 , \logical_op__write_cr0$84 , \logical_op__invert_out$83 , \logical_op__input_carry$82 , \logical_op__zero_a$81 , \logical_op__invert_in$80 , \logical_op__oe__ok$79 , \logical_op__oe__oe$78 , \logical_op__rc__ok$77 , \logical_op__rc__rc$76 , \logical_op__imm_data__ok$75 , \logical_op__imm_data__data$74 , \logical_op__fn_unit$73 , \logical_op__insn_type$72  } = { \pipe_end_logical_op__insn$69 , \pipe_end_logical_op__data_len$68 , \pipe_end_logical_op__is_signed$67 , \pipe_end_logical_op__is_32bit$66 , \pipe_end_logical_op__output_carry$65 , \pipe_end_logical_op__write_cr0$64 , \pipe_end_logical_op__invert_out$63 , \pipe_end_logical_op__input_carry$62 , \pipe_end_logical_op__zero_a$61 , \pipe_end_logical_op__invert_in$60 , \pipe_end_logical_op__oe__ok$59 , \pipe_end_logical_op__oe__oe$58 , \pipe_end_logical_op__rc__ok$57 , \pipe_end_logical_op__rc__rc$56 , \pipe_end_logical_op__imm_data__ok$55 , \pipe_end_logical_op__imm_data__data$54 , \pipe_end_logical_op__fn_unit$53 , \pipe_end_logical_op__insn_type$52  };
  assign \muxid$71  = \pipe_end_muxid$51 ;
  assign pipe_end_n_ready_i = n_ready_i;
  assign n_valid_o = pipe_end_n_valid_o;
  assign \pipe_start_xer_so$23  = \xer_so$1 ;
  assign \pipe_start_rb$22  = rb;
  assign \pipe_start_ra$21  = ra;
  assign { \pipe_start_logical_op__insn$20 , \pipe_start_logical_op__data_len$19 , \pipe_start_logical_op__is_signed$18 , \pipe_start_logical_op__is_32bit$17 , \pipe_start_logical_op__output_carry$16 , \pipe_start_logical_op__write_cr0$15 , \pipe_start_logical_op__invert_out$14 , \pipe_start_logical_op__input_carry$13 , \pipe_start_logical_op__zero_a$12 , \pipe_start_logical_op__invert_in$11 , \pipe_start_logical_op__oe__ok$10 , \pipe_start_logical_op__oe__oe$9 , \pipe_start_logical_op__rc__ok$8 , \pipe_start_logical_op__rc__rc$7 , \pipe_start_logical_op__imm_data__ok$6 , \pipe_start_logical_op__imm_data__data$5 , \pipe_start_logical_op__fn_unit$4 , \pipe_start_logical_op__insn_type$3  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \pipe_start_muxid$2  = 2'h0;
  assign p_ready_o = pipe_start_p_ready_o;
  assign pipe_start_p_valid_i = p_valid_i;
  assign pipe_end_remainder = pipe_middle_0_remainder;
  assign pipe_end_quotient_root = pipe_middle_0_quotient_root;
  assign pipe_end_div_by_zero = \pipe_middle_0_div_by_zero$50 ;
  assign pipe_end_dive_abs_ov64 = \pipe_middle_0_dive_abs_ov64$49 ;
  assign pipe_end_dive_abs_ov32 = \pipe_middle_0_dive_abs_ov32$48 ;
  assign pipe_end_dividend_neg = \pipe_middle_0_dividend_neg$47 ;
  assign pipe_end_divisor_neg = \pipe_middle_0_divisor_neg$46 ;
  assign pipe_end_xer_so = \pipe_middle_0_xer_so$45 ;
  assign pipe_end_rb = \pipe_middle_0_rb$44 ;
  assign pipe_end_ra = \pipe_middle_0_ra$43 ;
  assign { pipe_end_logical_op__insn, pipe_end_logical_op__data_len, pipe_end_logical_op__is_signed, pipe_end_logical_op__is_32bit, pipe_end_logical_op__output_carry, pipe_end_logical_op__write_cr0, pipe_end_logical_op__invert_out, pipe_end_logical_op__input_carry, pipe_end_logical_op__zero_a, pipe_end_logical_op__invert_in, pipe_end_logical_op__oe__ok, pipe_end_logical_op__oe__oe, pipe_end_logical_op__rc__ok, pipe_end_logical_op__rc__rc, pipe_end_logical_op__imm_data__ok, pipe_end_logical_op__imm_data__data, pipe_end_logical_op__fn_unit, pipe_end_logical_op__insn_type } = { \pipe_middle_0_logical_op__insn$42 , \pipe_middle_0_logical_op__data_len$41 , \pipe_middle_0_logical_op__is_signed$40 , \pipe_middle_0_logical_op__is_32bit$39 , \pipe_middle_0_logical_op__output_carry$38 , \pipe_middle_0_logical_op__write_cr0$37 , \pipe_middle_0_logical_op__invert_out$36 , \pipe_middle_0_logical_op__input_carry$35 , \pipe_middle_0_logical_op__zero_a$34 , \pipe_middle_0_logical_op__invert_in$33 , \pipe_middle_0_logical_op__oe__ok$32 , \pipe_middle_0_logical_op__oe__oe$31 , \pipe_middle_0_logical_op__rc__ok$30 , \pipe_middle_0_logical_op__rc__rc$29 , \pipe_middle_0_logical_op__imm_data__ok$28 , \pipe_middle_0_logical_op__imm_data__data$27 , \pipe_middle_0_logical_op__fn_unit$26 , \pipe_middle_0_logical_op__insn_type$25  };
  assign pipe_end_muxid = \pipe_middle_0_muxid$24 ;
  assign pipe_middle_0_n_ready_i = pipe_end_p_ready_o;
  assign pipe_end_p_valid_i = pipe_middle_0_n_valid_o;
  assign pipe_middle_0_operation = pipe_start_operation;
  assign pipe_middle_0_divisor_radicand = pipe_start_divisor_radicand;
  assign pipe_middle_0_dividend = pipe_start_dividend;
  assign pipe_middle_0_div_by_zero = pipe_start_div_by_zero;
  assign pipe_middle_0_dive_abs_ov64 = pipe_start_dive_abs_ov64;
  assign pipe_middle_0_dive_abs_ov32 = pipe_start_dive_abs_ov32;
  assign pipe_middle_0_dividend_neg = pipe_start_dividend_neg;
  assign pipe_middle_0_divisor_neg = pipe_start_divisor_neg;
  assign pipe_middle_0_xer_so = pipe_start_xer_so;
  assign pipe_middle_0_rb = pipe_start_rb;
  assign pipe_middle_0_ra = pipe_start_ra;
  assign { pipe_middle_0_logical_op__insn, pipe_middle_0_logical_op__data_len, pipe_middle_0_logical_op__is_signed, pipe_middle_0_logical_op__is_32bit, pipe_middle_0_logical_op__output_carry, pipe_middle_0_logical_op__write_cr0, pipe_middle_0_logical_op__invert_out, pipe_middle_0_logical_op__input_carry, pipe_middle_0_logical_op__zero_a, pipe_middle_0_logical_op__invert_in, pipe_middle_0_logical_op__oe__ok, pipe_middle_0_logical_op__oe__oe, pipe_middle_0_logical_op__rc__ok, pipe_middle_0_logical_op__rc__rc, pipe_middle_0_logical_op__imm_data__ok, pipe_middle_0_logical_op__imm_data__data, pipe_middle_0_logical_op__fn_unit, pipe_middle_0_logical_op__insn_type } = { pipe_start_logical_op__insn, pipe_start_logical_op__data_len, pipe_start_logical_op__is_signed, pipe_start_logical_op__is_32bit, pipe_start_logical_op__output_carry, pipe_start_logical_op__write_cr0, pipe_start_logical_op__invert_out, pipe_start_logical_op__input_carry, pipe_start_logical_op__zero_a, pipe_start_logical_op__invert_in, pipe_start_logical_op__oe__ok, pipe_start_logical_op__oe__oe, pipe_start_logical_op__rc__ok, pipe_start_logical_op__rc__rc, pipe_start_logical_op__imm_data__ok, pipe_start_logical_op__imm_data__data, pipe_start_logical_op__fn_unit, pipe_start_logical_op__insn_type };
  assign pipe_middle_0_muxid = pipe_start_muxid;
  assign pipe_start_n_ready_i = pipe_middle_0_p_ready_o;
  assign pipe_middle_0_p_valid_i = pipe_start_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26288.1-26346.10" *)
module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26289.7-26289.20" *)
  reg _00_;
  (* src = "libresoc.v:26334.3-26342.6" *)
  reg _01_;
  (* src = "libresoc.v:26332.3-26333.27" *)
  reg _02_;
  (* src = "libresoc.v:26334.3-26342.6" *)
  reg _03_;
  (* src = "libresoc.v:26313.7-26313.19" *)
  reg _04_;
  (* src = "libresoc.v:26324.17-26324.96" *)
  wire _05_;
  (* src = "libresoc.v:26329.17-26329.96" *)
  wire _06_;
  (* src = "libresoc.v:26326.18-26326.93" *)
  wire _07_;
  (* src = "libresoc.v:26328.17-26328.92" *)
  wire _08_;
  (* src = "libresoc.v:26331.17-26331.92" *)
  wire _09_;
  (* src = "libresoc.v:26325.18-26325.98" *)
  wire _10_;
  (* src = "libresoc.v:26327.18-26327.99" *)
  wire _11_;
  (* src = "libresoc.v:26330.17-26330.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26289.7-26289.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26335.5-26335.29" *)
    casez (\initial )
      /* src = "libresoc.v:26335.9-26335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26350.1-26408.10" *)
module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26351.7-26351.20" *)
  reg _00_;
  (* src = "libresoc.v:26396.3-26404.6" *)
  reg _01_;
  (* src = "libresoc.v:26394.3-26395.27" *)
  reg _02_;
  (* src = "libresoc.v:26396.3-26404.6" *)
  reg _03_;
  (* src = "libresoc.v:26375.7-26375.19" *)
  reg _04_;
  (* src = "libresoc.v:26386.17-26386.96" *)
  wire _05_;
  (* src = "libresoc.v:26391.17-26391.96" *)
  wire _06_;
  (* src = "libresoc.v:26388.18-26388.93" *)
  wire _07_;
  (* src = "libresoc.v:26390.17-26390.92" *)
  wire _08_;
  (* src = "libresoc.v:26393.17-26393.92" *)
  wire _09_;
  (* src = "libresoc.v:26387.18-26387.98" *)
  wire _10_;
  (* src = "libresoc.v:26389.18-26389.99" *)
  wire _11_;
  (* src = "libresoc.v:26392.17-26392.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26351.7-26351.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26397.5-26397.29" *)
    casez (\initial )
      /* src = "libresoc.v:26397.9-26397.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26412.1-26470.10" *)
module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26413.7-26413.20" *)
  reg _00_;
  (* src = "libresoc.v:26458.3-26466.6" *)
  reg _01_;
  (* src = "libresoc.v:26456.3-26457.27" *)
  reg _02_;
  (* src = "libresoc.v:26458.3-26466.6" *)
  reg _03_;
  (* src = "libresoc.v:26437.7-26437.19" *)
  reg _04_;
  (* src = "libresoc.v:26448.17-26448.96" *)
  wire _05_;
  (* src = "libresoc.v:26453.17-26453.96" *)
  wire _06_;
  (* src = "libresoc.v:26450.18-26450.93" *)
  wire _07_;
  (* src = "libresoc.v:26452.17-26452.92" *)
  wire _08_;
  (* src = "libresoc.v:26455.17-26455.92" *)
  wire _09_;
  (* src = "libresoc.v:26449.18-26449.98" *)
  wire _10_;
  (* src = "libresoc.v:26451.18-26451.99" *)
  wire _11_;
  (* src = "libresoc.v:26454.17-26454.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26413.7-26413.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26459.5-26459.29" *)
    casez (\initial )
      /* src = "libresoc.v:26459.9-26459.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26474.1-26532.10" *)
module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26475.7-26475.20" *)
  reg _00_;
  (* src = "libresoc.v:26520.3-26528.6" *)
  reg _01_;
  (* src = "libresoc.v:26518.3-26519.27" *)
  reg _02_;
  (* src = "libresoc.v:26520.3-26528.6" *)
  reg _03_;
  (* src = "libresoc.v:26499.7-26499.19" *)
  reg _04_;
  (* src = "libresoc.v:26510.17-26510.96" *)
  wire _05_;
  (* src = "libresoc.v:26515.17-26515.96" *)
  wire _06_;
  (* src = "libresoc.v:26512.18-26512.93" *)
  wire _07_;
  (* src = "libresoc.v:26514.17-26514.92" *)
  wire _08_;
  (* src = "libresoc.v:26517.17-26517.92" *)
  wire _09_;
  (* src = "libresoc.v:26511.18-26511.98" *)
  wire _10_;
  (* src = "libresoc.v:26513.18-26513.99" *)
  wire _11_;
  (* src = "libresoc.v:26516.17-26516.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26475.7-26475.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26521.5-26521.29" *)
    casez (\initial )
      /* src = "libresoc.v:26521.9-26521.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26536.1-26594.10" *)
module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26537.7-26537.20" *)
  reg _00_;
  (* src = "libresoc.v:26582.3-26590.6" *)
  reg _01_;
  (* src = "libresoc.v:26580.3-26581.27" *)
  reg _02_;
  (* src = "libresoc.v:26582.3-26590.6" *)
  reg _03_;
  (* src = "libresoc.v:26561.7-26561.19" *)
  reg _04_;
  (* src = "libresoc.v:26572.17-26572.96" *)
  wire _05_;
  (* src = "libresoc.v:26577.17-26577.96" *)
  wire _06_;
  (* src = "libresoc.v:26574.18-26574.93" *)
  wire _07_;
  (* src = "libresoc.v:26576.17-26576.92" *)
  wire _08_;
  (* src = "libresoc.v:26579.17-26579.92" *)
  wire _09_;
  (* src = "libresoc.v:26573.18-26573.98" *)
  wire _10_;
  (* src = "libresoc.v:26575.18-26575.99" *)
  wire _11_;
  (* src = "libresoc.v:26578.17-26578.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26537.7-26537.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26583.5-26583.29" *)
    casez (\initial )
      /* src = "libresoc.v:26583.9-26583.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26598.1-26656.10" *)
module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26599.7-26599.20" *)
  reg _00_;
  (* src = "libresoc.v:26644.3-26652.6" *)
  reg _01_;
  (* src = "libresoc.v:26642.3-26643.27" *)
  reg _02_;
  (* src = "libresoc.v:26644.3-26652.6" *)
  reg _03_;
  (* src = "libresoc.v:26623.7-26623.19" *)
  reg _04_;
  (* src = "libresoc.v:26634.17-26634.96" *)
  wire _05_;
  (* src = "libresoc.v:26639.17-26639.96" *)
  wire _06_;
  (* src = "libresoc.v:26636.18-26636.93" *)
  wire _07_;
  (* src = "libresoc.v:26638.17-26638.92" *)
  wire _08_;
  (* src = "libresoc.v:26641.17-26641.92" *)
  wire _09_;
  (* src = "libresoc.v:26635.18-26635.98" *)
  wire _10_;
  (* src = "libresoc.v:26637.18-26637.99" *)
  wire _11_;
  (* src = "libresoc.v:26640.17-26640.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26599.7-26599.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26645.5-26645.29" *)
    casez (\initial )
      /* src = "libresoc.v:26645.9-26645.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26660.1-26718.10" *)
module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26661.7-26661.20" *)
  reg _00_;
  (* src = "libresoc.v:26706.3-26714.6" *)
  reg _01_;
  (* src = "libresoc.v:26704.3-26705.27" *)
  reg _02_;
  (* src = "libresoc.v:26706.3-26714.6" *)
  reg _03_;
  (* src = "libresoc.v:26685.7-26685.19" *)
  reg _04_;
  (* src = "libresoc.v:26696.17-26696.96" *)
  wire _05_;
  (* src = "libresoc.v:26701.17-26701.96" *)
  wire _06_;
  (* src = "libresoc.v:26698.18-26698.93" *)
  wire _07_;
  (* src = "libresoc.v:26700.17-26700.92" *)
  wire _08_;
  (* src = "libresoc.v:26703.17-26703.92" *)
  wire _09_;
  (* src = "libresoc.v:26697.18-26697.98" *)
  wire _10_;
  (* src = "libresoc.v:26699.18-26699.99" *)
  wire _11_;
  (* src = "libresoc.v:26702.17-26702.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26661.7-26661.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26707.5-26707.29" *)
    casez (\initial )
      /* src = "libresoc.v:26707.9-26707.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26722.1-26780.10" *)
module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26723.7-26723.20" *)
  reg _00_;
  (* src = "libresoc.v:26768.3-26776.6" *)
  reg _01_;
  (* src = "libresoc.v:26766.3-26767.27" *)
  reg _02_;
  (* src = "libresoc.v:26768.3-26776.6" *)
  reg _03_;
  (* src = "libresoc.v:26747.7-26747.19" *)
  reg _04_;
  (* src = "libresoc.v:26758.17-26758.96" *)
  wire _05_;
  (* src = "libresoc.v:26763.17-26763.96" *)
  wire _06_;
  (* src = "libresoc.v:26760.18-26760.93" *)
  wire _07_;
  (* src = "libresoc.v:26762.17-26762.92" *)
  wire _08_;
  (* src = "libresoc.v:26765.17-26765.92" *)
  wire _09_;
  (* src = "libresoc.v:26759.18-26759.98" *)
  wire _10_;
  (* src = "libresoc.v:26761.18-26761.99" *)
  wire _11_;
  (* src = "libresoc.v:26764.17-26764.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26723.7-26723.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26769.5-26769.29" *)
    casez (\initial )
      /* src = "libresoc.v:26769.9-26769.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26784.1-26842.10" *)
module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26785.7-26785.20" *)
  reg _00_;
  (* src = "libresoc.v:26830.3-26838.6" *)
  reg _01_;
  (* src = "libresoc.v:26828.3-26829.27" *)
  reg _02_;
  (* src = "libresoc.v:26830.3-26838.6" *)
  reg _03_;
  (* src = "libresoc.v:26809.7-26809.19" *)
  reg _04_;
  (* src = "libresoc.v:26820.17-26820.96" *)
  wire _05_;
  (* src = "libresoc.v:26825.17-26825.96" *)
  wire _06_;
  (* src = "libresoc.v:26822.18-26822.93" *)
  wire _07_;
  (* src = "libresoc.v:26824.17-26824.92" *)
  wire _08_;
  (* src = "libresoc.v:26827.17-26827.92" *)
  wire _09_;
  (* src = "libresoc.v:26821.18-26821.98" *)
  wire _10_;
  (* src = "libresoc.v:26823.18-26823.99" *)
  wire _11_;
  (* src = "libresoc.v:26826.17-26826.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26785.7-26785.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26831.5-26831.29" *)
    casez (\initial )
      /* src = "libresoc.v:26831.9-26831.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26846.1-26904.10" *)
module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:26847.7-26847.20" *)
  reg _00_;
  (* src = "libresoc.v:26892.3-26900.6" *)
  reg _01_;
  (* src = "libresoc.v:26890.3-26891.27" *)
  reg _02_;
  (* src = "libresoc.v:26892.3-26900.6" *)
  reg _03_;
  (* src = "libresoc.v:26871.7-26871.19" *)
  reg _04_;
  (* src = "libresoc.v:26882.17-26882.96" *)
  wire _05_;
  (* src = "libresoc.v:26887.17-26887.96" *)
  wire _06_;
  (* src = "libresoc.v:26884.18-26884.93" *)
  wire _07_;
  (* src = "libresoc.v:26886.17-26886.92" *)
  wire _08_;
  (* src = "libresoc.v:26889.17-26889.92" *)
  wire _09_;
  (* src = "libresoc.v:26883.18-26883.98" *)
  wire _10_;
  (* src = "libresoc.v:26885.18-26885.99" *)
  wire _11_;
  (* src = "libresoc.v:26888.17-26888.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:26847.7-26847.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alu;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alu;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alu;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alu;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alu;
  assign _11_ = q_alu | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alu;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:26893.5-26893.29" *)
    casez (\initial )
      /* src = "libresoc.v:26893.9-26893.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alu = \$15 ;
  assign qn_alu = \$13 ;
  assign q_alu = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:26908.1-27921.10" *)
module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$61 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$48 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$62 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] logical_pipe1_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe1_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] logical_pipe1_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_pipe1_logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] logical_pipe1_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_pipe1_logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] logical_pipe1_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_pipe1_logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] logical_pipe1_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_pipe1_logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] logical_pipe1_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_pipe1_logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] logical_pipe1_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_pipe1_logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe1_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe1_logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] logical_pipe1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \logical_pipe1_muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire logical_pipe1_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire logical_pipe1_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] logical_pipe1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe1_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire logical_pipe1_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire logical_pipe1_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] logical_pipe1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] logical_pipe1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe1_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \logical_pipe1_xer_so$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe1_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] logical_pipe2_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \logical_pipe2_cr_a$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe2_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \logical_pipe2_cr_a_ok$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] logical_pipe2_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_pipe2_logical_op__data_len$38 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] logical_pipe2_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_pipe2_logical_op__fn_unit$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] logical_pipe2_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_pipe2_logical_op__imm_data__data$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__imm_data__ok$25 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] logical_pipe2_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_pipe2_logical_op__input_carry$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] logical_pipe2_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_pipe2_logical_op__insn$39 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] logical_pipe2_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_pipe2_logical_op__insn_type$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__invert_in$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__invert_out$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__is_32bit$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__is_signed$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__oe__oe$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__oe__ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__output_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__rc__ok$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__rc__rc$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__write_cr0$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire logical_pipe2_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_pipe2_logical_op__zero_a$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] logical_pipe2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \logical_pipe2_muxid$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire logical_pipe2_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire logical_pipe2_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] logical_pipe2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \logical_pipe2_o$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe2_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \logical_pipe2_o_ok$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire logical_pipe2_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire logical_pipe2_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe2_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire logical_pipe2_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$44 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:27781.17-27835.4" *)
  logical_pipe1 logical_pipe1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(logical_pipe1_cr_a),
    .cr_a_ok(logical_pipe1_cr_a_ok),
    .logical_op__data_len(logical_pipe1_logical_op__data_len),
    .\logical_op__data_len$18 (\logical_pipe1_logical_op__data_len$18 ),
    .logical_op__fn_unit(logical_pipe1_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\logical_pipe1_logical_op__fn_unit$3 ),
    .logical_op__imm_data__data(logical_pipe1_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\logical_pipe1_logical_op__imm_data__data$4 ),
    .logical_op__imm_data__ok(logical_pipe1_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\logical_pipe1_logical_op__imm_data__ok$5 ),
    .logical_op__input_carry(logical_pipe1_logical_op__input_carry),
    .\logical_op__input_carry$12 (\logical_pipe1_logical_op__input_carry$12 ),
    .logical_op__insn(logical_pipe1_logical_op__insn),
    .\logical_op__insn$19 (\logical_pipe1_logical_op__insn$19 ),
    .logical_op__insn_type(logical_pipe1_logical_op__insn_type),
    .\logical_op__insn_type$2 (\logical_pipe1_logical_op__insn_type$2 ),
    .logical_op__invert_in(logical_pipe1_logical_op__invert_in),
    .\logical_op__invert_in$10 (\logical_pipe1_logical_op__invert_in$10 ),
    .logical_op__invert_out(logical_pipe1_logical_op__invert_out),
    .\logical_op__invert_out$13 (\logical_pipe1_logical_op__invert_out$13 ),
    .logical_op__is_32bit(logical_pipe1_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\logical_pipe1_logical_op__is_32bit$16 ),
    .logical_op__is_signed(logical_pipe1_logical_op__is_signed),
    .\logical_op__is_signed$17 (\logical_pipe1_logical_op__is_signed$17 ),
    .logical_op__oe__oe(logical_pipe1_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\logical_pipe1_logical_op__oe__oe$8 ),
    .logical_op__oe__ok(logical_pipe1_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\logical_pipe1_logical_op__oe__ok$9 ),
    .logical_op__output_carry(logical_pipe1_logical_op__output_carry),
    .\logical_op__output_carry$15 (\logical_pipe1_logical_op__output_carry$15 ),
    .logical_op__rc__ok(logical_pipe1_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\logical_pipe1_logical_op__rc__ok$7 ),
    .logical_op__rc__rc(logical_pipe1_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\logical_pipe1_logical_op__rc__rc$6 ),
    .logical_op__write_cr0(logical_pipe1_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\logical_pipe1_logical_op__write_cr0$14 ),
    .logical_op__zero_a(logical_pipe1_logical_op__zero_a),
    .\logical_op__zero_a$11 (\logical_pipe1_logical_op__zero_a$11 ),
    .muxid(logical_pipe1_muxid),
    .\muxid$1 (\logical_pipe1_muxid$1 ),
    .n_ready_i(logical_pipe1_n_ready_i),
    .n_valid_o(logical_pipe1_n_valid_o),
    .o(logical_pipe1_o),
    .o_ok(logical_pipe1_o_ok),
    .p_ready_o(logical_pipe1_p_ready_o),
    .p_valid_i(logical_pipe1_p_valid_i),
    .ra(logical_pipe1_ra),
    .rb(logical_pipe1_rb),
    .xer_so(logical_pipe1_xer_so),
    .\xer_so$20 (\logical_pipe1_xer_so$20 ),
    .xer_so_ok(logical_pipe1_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:27836.17-27891.4" *)
  logical_pipe2 logical_pipe2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(logical_pipe2_cr_a),
    .\cr_a$22 (\logical_pipe2_cr_a$42 ),
    .cr_a_ok(logical_pipe2_cr_a_ok),
    .\cr_a_ok$23 (\logical_pipe2_cr_a_ok$43 ),
    .logical_op__data_len(logical_pipe2_logical_op__data_len),
    .\logical_op__data_len$18 (\logical_pipe2_logical_op__data_len$38 ),
    .logical_op__fn_unit(logical_pipe2_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\logical_pipe2_logical_op__fn_unit$23 ),
    .logical_op__imm_data__data(logical_pipe2_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\logical_pipe2_logical_op__imm_data__data$24 ),
    .logical_op__imm_data__ok(logical_pipe2_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\logical_pipe2_logical_op__imm_data__ok$25 ),
    .logical_op__input_carry(logical_pipe2_logical_op__input_carry),
    .\logical_op__input_carry$12 (\logical_pipe2_logical_op__input_carry$32 ),
    .logical_op__insn(logical_pipe2_logical_op__insn),
    .\logical_op__insn$19 (\logical_pipe2_logical_op__insn$39 ),
    .logical_op__insn_type(logical_pipe2_logical_op__insn_type),
    .\logical_op__insn_type$2 (\logical_pipe2_logical_op__insn_type$22 ),
    .logical_op__invert_in(logical_pipe2_logical_op__invert_in),
    .\logical_op__invert_in$10 (\logical_pipe2_logical_op__invert_in$30 ),
    .logical_op__invert_out(logical_pipe2_logical_op__invert_out),
    .\logical_op__invert_out$13 (\logical_pipe2_logical_op__invert_out$33 ),
    .logical_op__is_32bit(logical_pipe2_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\logical_pipe2_logical_op__is_32bit$36 ),
    .logical_op__is_signed(logical_pipe2_logical_op__is_signed),
    .\logical_op__is_signed$17 (\logical_pipe2_logical_op__is_signed$37 ),
    .logical_op__oe__oe(logical_pipe2_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\logical_pipe2_logical_op__oe__oe$28 ),
    .logical_op__oe__ok(logical_pipe2_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\logical_pipe2_logical_op__oe__ok$29 ),
    .logical_op__output_carry(logical_pipe2_logical_op__output_carry),
    .\logical_op__output_carry$15 (\logical_pipe2_logical_op__output_carry$35 ),
    .logical_op__rc__ok(logical_pipe2_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\logical_pipe2_logical_op__rc__ok$27 ),
    .logical_op__rc__rc(logical_pipe2_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\logical_pipe2_logical_op__rc__rc$26 ),
    .logical_op__write_cr0(logical_pipe2_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\logical_pipe2_logical_op__write_cr0$34 ),
    .logical_op__zero_a(logical_pipe2_logical_op__zero_a),
    .\logical_op__zero_a$11 (\logical_pipe2_logical_op__zero_a$31 ),
    .muxid(logical_pipe2_muxid),
    .\muxid$1 (\logical_pipe2_muxid$21 ),
    .n_ready_i(logical_pipe2_n_ready_i),
    .n_valid_o(logical_pipe2_n_valid_o),
    .o(logical_pipe2_o),
    .\o$20 (\logical_pipe2_o$40 ),
    .o_ok(logical_pipe2_o_ok),
    .\o_ok$21 (\logical_pipe2_o_ok$41 ),
    .p_ready_o(logical_pipe2_p_ready_o),
    .p_valid_i(logical_pipe2_p_valid_i),
    .xer_so(logical_pipe2_xer_so),
    .xer_so_ok(logical_pipe2_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:27892.10-27895.4" *)
  \n$47  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:27896.10-27899.4" *)
  \p$46  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  assign muxid = 2'h0;
  assign { cr_a_ok, cr_a } = { \logical_pipe2_cr_a_ok$43 , \logical_pipe2_cr_a$42  };
  assign { o_ok, o } = { \logical_pipe2_o_ok$41 , \logical_pipe2_o$40  };
  assign { \logical_op__insn$62 , \logical_op__data_len$61 , \logical_op__is_signed$60 , \logical_op__is_32bit$59 , \logical_op__output_carry$58 , \logical_op__write_cr0$57 , \logical_op__invert_out$56 , \logical_op__input_carry$55 , \logical_op__zero_a$54 , \logical_op__invert_in$53 , \logical_op__oe__ok$52 , \logical_op__oe__oe$51 , \logical_op__rc__ok$50 , \logical_op__rc__rc$49 , \logical_op__imm_data__ok$48 , \logical_op__imm_data__data$47 , \logical_op__fn_unit$46 , \logical_op__insn_type$45  } = { \logical_pipe2_logical_op__insn$39 , \logical_pipe2_logical_op__data_len$38 , \logical_pipe2_logical_op__is_signed$37 , \logical_pipe2_logical_op__is_32bit$36 , \logical_pipe2_logical_op__output_carry$35 , \logical_pipe2_logical_op__write_cr0$34 , \logical_pipe2_logical_op__invert_out$33 , \logical_pipe2_logical_op__input_carry$32 , \logical_pipe2_logical_op__zero_a$31 , \logical_pipe2_logical_op__invert_in$30 , \logical_pipe2_logical_op__oe__ok$29 , \logical_pipe2_logical_op__oe__oe$28 , \logical_pipe2_logical_op__rc__ok$27 , \logical_pipe2_logical_op__rc__rc$26 , \logical_pipe2_logical_op__imm_data__ok$25 , \logical_pipe2_logical_op__imm_data__data$24 , \logical_pipe2_logical_op__fn_unit$23 , \logical_pipe2_logical_op__insn_type$22  };
  assign \muxid$44  = \logical_pipe2_muxid$21 ;
  assign logical_pipe2_n_ready_i = n_ready_i;
  assign n_valid_o = logical_pipe2_n_valid_o;
  assign \logical_pipe1_xer_so$20  = xer_so;
  assign logical_pipe1_rb = rb;
  assign logical_pipe1_ra = ra;
  assign { \logical_pipe1_logical_op__insn$19 , \logical_pipe1_logical_op__data_len$18 , \logical_pipe1_logical_op__is_signed$17 , \logical_pipe1_logical_op__is_32bit$16 , \logical_pipe1_logical_op__output_carry$15 , \logical_pipe1_logical_op__write_cr0$14 , \logical_pipe1_logical_op__invert_out$13 , \logical_pipe1_logical_op__input_carry$12 , \logical_pipe1_logical_op__zero_a$11 , \logical_pipe1_logical_op__invert_in$10 , \logical_pipe1_logical_op__oe__ok$9 , \logical_pipe1_logical_op__oe__oe$8 , \logical_pipe1_logical_op__rc__ok$7 , \logical_pipe1_logical_op__rc__rc$6 , \logical_pipe1_logical_op__imm_data__ok$5 , \logical_pipe1_logical_op__imm_data__data$4 , \logical_pipe1_logical_op__fn_unit$3 , \logical_pipe1_logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \logical_pipe1_muxid$1  = 2'h0;
  assign p_ready_o = logical_pipe1_p_ready_o;
  assign logical_pipe1_p_valid_i = p_valid_i;
  assign { logical_pipe2_xer_so_ok, logical_pipe2_xer_so } = { logical_pipe1_xer_so_ok, logical_pipe1_xer_so };
  assign { logical_pipe2_cr_a_ok, logical_pipe2_cr_a } = { logical_pipe1_cr_a_ok, logical_pipe1_cr_a };
  assign { logical_pipe2_o_ok, logical_pipe2_o } = { logical_pipe1_o_ok, logical_pipe1_o };
  assign { logical_pipe2_logical_op__insn, logical_pipe2_logical_op__data_len, logical_pipe2_logical_op__is_signed, logical_pipe2_logical_op__is_32bit, logical_pipe2_logical_op__output_carry, logical_pipe2_logical_op__write_cr0, logical_pipe2_logical_op__invert_out, logical_pipe2_logical_op__input_carry, logical_pipe2_logical_op__zero_a, logical_pipe2_logical_op__invert_in, logical_pipe2_logical_op__oe__ok, logical_pipe2_logical_op__oe__oe, logical_pipe2_logical_op__rc__ok, logical_pipe2_logical_op__rc__rc, logical_pipe2_logical_op__imm_data__ok, logical_pipe2_logical_op__imm_data__data, logical_pipe2_logical_op__fn_unit, logical_pipe2_logical_op__insn_type } = { logical_pipe1_logical_op__insn, logical_pipe1_logical_op__data_len, logical_pipe1_logical_op__is_signed, logical_pipe1_logical_op__is_32bit, logical_pipe1_logical_op__output_carry, logical_pipe1_logical_op__write_cr0, logical_pipe1_logical_op__invert_out, logical_pipe1_logical_op__input_carry, logical_pipe1_logical_op__zero_a, logical_pipe1_logical_op__invert_in, logical_pipe1_logical_op__oe__ok, logical_pipe1_logical_op__oe__oe, logical_pipe1_logical_op__rc__ok, logical_pipe1_logical_op__rc__rc, logical_pipe1_logical_op__imm_data__ok, logical_pipe1_logical_op__imm_data__data, logical_pipe1_logical_op__fn_unit, logical_pipe1_logical_op__insn_type };
  assign logical_pipe2_muxid = logical_pipe1_muxid;
  assign logical_pipe1_n_ready_i = logical_pipe2_p_ready_o;
  assign logical_pipe2_p_valid_i = logical_pipe1_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:27925.1-29142.10" *)
module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_op__fn_unit$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_op__imm_data__data$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__imm_data__ok$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_op__insn$61 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_op__insn_type$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_32bit$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_signed$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__oe$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__ok$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__ok$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__rc$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__write_cr0$58 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul_pipe1_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_pipe1_mul_op__fn_unit$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul_pipe1_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_pipe1_mul_op__imm_data__data$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__imm_data__ok$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul_pipe1_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_pipe1_mul_op__insn$14 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul_pipe1_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_pipe1_mul_op__insn_type$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__is_32bit$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__is_signed$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__oe__oe$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__oe__ok$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__rc__ok$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__rc__rc$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe1_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe1_mul_op__write_cr0$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul_pipe1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul_pipe1_muxid$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire mul_pipe1_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire mul_pipe1_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  wire mul_pipe1_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  wire mul_pipe1_neg_res32;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire mul_pipe1_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire mul_pipe1_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul_pipe1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \mul_pipe1_ra$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul_pipe1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \mul_pipe1_rb$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul_pipe1_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \mul_pipe1_xer_so$17 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul_pipe2_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_pipe2_mul_op__fn_unit$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul_pipe2_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_pipe2_mul_op__imm_data__data$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__imm_data__ok$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul_pipe2_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_pipe2_mul_op__insn$30 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul_pipe2_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_pipe2_mul_op__insn_type$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__is_32bit$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__is_signed$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__oe__oe$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__oe__ok$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__rc__ok$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__rc__rc$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe2_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe2_mul_op__write_cr0$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul_pipe2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul_pipe2_muxid$18 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire mul_pipe2_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire mul_pipe2_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  wire mul_pipe2_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  wire \mul_pipe2_neg_res$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  wire mul_pipe2_neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  wire \mul_pipe2_neg_res32$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [128:0] mul_pipe2_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire mul_pipe2_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire mul_pipe2_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul_pipe2_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul_pipe2_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul_pipe2_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \mul_pipe2_xer_so$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] mul_pipe3_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul_pipe3_cr_a_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul_pipe3_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_pipe3_mul_op__fn_unit$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul_pipe3_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_pipe3_mul_op__imm_data__data$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__imm_data__ok$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul_pipe3_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_pipe3_mul_op__insn$46 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul_pipe3_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_pipe3_mul_op__insn_type$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__is_32bit$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__is_signed$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__oe__oe$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__oe__ok$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__rc__ok$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__rc__rc$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul_pipe3_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_pipe3_mul_op__write_cr0$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul_pipe3_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul_pipe3_muxid$34 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire mul_pipe3_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire mul_pipe3_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  wire mul_pipe3_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  wire mul_pipe3_neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [128:0] mul_pipe3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \mul_pipe3_o$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul_pipe3_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire mul_pipe3_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire mul_pipe3_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] mul_pipe3_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul_pipe3_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul_pipe3_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \mul_pipe3_xer_so$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul_pipe3_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:28970.13-29011.4" *)
  mul_pipe1 mul_pipe1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .mul_op__fn_unit(mul_pipe1_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul_pipe1_mul_op__fn_unit$4 ),
    .mul_op__imm_data__data(mul_pipe1_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul_pipe1_mul_op__imm_data__data$5 ),
    .mul_op__imm_data__ok(mul_pipe1_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul_pipe1_mul_op__imm_data__ok$6 ),
    .mul_op__insn(mul_pipe1_mul_op__insn),
    .\mul_op__insn$13 (\mul_pipe1_mul_op__insn$14 ),
    .mul_op__insn_type(mul_pipe1_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul_pipe1_mul_op__insn_type$3 ),
    .mul_op__is_32bit(mul_pipe1_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul_pipe1_mul_op__is_32bit$12 ),
    .mul_op__is_signed(mul_pipe1_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul_pipe1_mul_op__is_signed$13 ),
    .mul_op__oe__oe(mul_pipe1_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul_pipe1_mul_op__oe__oe$9 ),
    .mul_op__oe__ok(mul_pipe1_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul_pipe1_mul_op__oe__ok$10 ),
    .mul_op__rc__ok(mul_pipe1_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul_pipe1_mul_op__rc__ok$8 ),
    .mul_op__rc__rc(mul_pipe1_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul_pipe1_mul_op__rc__rc$7 ),
    .mul_op__write_cr0(mul_pipe1_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul_pipe1_mul_op__write_cr0$11 ),
    .muxid(mul_pipe1_muxid),
    .\muxid$1 (\mul_pipe1_muxid$2 ),
    .n_ready_i(mul_pipe1_n_ready_i),
    .n_valid_o(mul_pipe1_n_valid_o),
    .neg_res(mul_pipe1_neg_res),
    .neg_res32(mul_pipe1_neg_res32),
    .p_ready_o(mul_pipe1_p_ready_o),
    .p_valid_i(mul_pipe1_p_valid_i),
    .ra(mul_pipe1_ra),
    .\ra$14 (\mul_pipe1_ra$15 ),
    .rb(mul_pipe1_rb),
    .\rb$15 (\mul_pipe1_rb$16 ),
    .xer_so(mul_pipe1_xer_so),
    .\xer_so$16 (\mul_pipe1_xer_so$17 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:29012.13-29054.4" *)
  mul_pipe2 mul_pipe2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .mul_op__fn_unit(mul_pipe2_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul_pipe2_mul_op__fn_unit$20 ),
    .mul_op__imm_data__data(mul_pipe2_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul_pipe2_mul_op__imm_data__data$21 ),
    .mul_op__imm_data__ok(mul_pipe2_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul_pipe2_mul_op__imm_data__ok$22 ),
    .mul_op__insn(mul_pipe2_mul_op__insn),
    .\mul_op__insn$13 (\mul_pipe2_mul_op__insn$30 ),
    .mul_op__insn_type(mul_pipe2_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul_pipe2_mul_op__insn_type$19 ),
    .mul_op__is_32bit(mul_pipe2_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul_pipe2_mul_op__is_32bit$28 ),
    .mul_op__is_signed(mul_pipe2_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul_pipe2_mul_op__is_signed$29 ),
    .mul_op__oe__oe(mul_pipe2_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul_pipe2_mul_op__oe__oe$25 ),
    .mul_op__oe__ok(mul_pipe2_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul_pipe2_mul_op__oe__ok$26 ),
    .mul_op__rc__ok(mul_pipe2_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul_pipe2_mul_op__rc__ok$24 ),
    .mul_op__rc__rc(mul_pipe2_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul_pipe2_mul_op__rc__rc$23 ),
    .mul_op__write_cr0(mul_pipe2_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul_pipe2_mul_op__write_cr0$27 ),
    .muxid(mul_pipe2_muxid),
    .\muxid$1 (\mul_pipe2_muxid$18 ),
    .n_ready_i(mul_pipe2_n_ready_i),
    .n_valid_o(mul_pipe2_n_valid_o),
    .neg_res(mul_pipe2_neg_res),
    .\neg_res$15 (\mul_pipe2_neg_res$32 ),
    .neg_res32(mul_pipe2_neg_res32),
    .\neg_res32$16 (\mul_pipe2_neg_res32$33 ),
    .o(mul_pipe2_o),
    .p_ready_o(mul_pipe2_p_ready_o),
    .p_valid_i(mul_pipe2_p_valid_i),
    .ra(mul_pipe2_ra),
    .rb(mul_pipe2_rb),
    .xer_so(mul_pipe2_xer_so),
    .\xer_so$14 (\mul_pipe2_xer_so$31 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:29055.13-29100.4" *)
  mul_pipe3 mul_pipe3 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(mul_pipe3_cr_a),
    .cr_a_ok(mul_pipe3_cr_a_ok),
    .mul_op__fn_unit(mul_pipe3_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul_pipe3_mul_op__fn_unit$36 ),
    .mul_op__imm_data__data(mul_pipe3_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul_pipe3_mul_op__imm_data__data$37 ),
    .mul_op__imm_data__ok(mul_pipe3_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul_pipe3_mul_op__imm_data__ok$38 ),
    .mul_op__insn(mul_pipe3_mul_op__insn),
    .\mul_op__insn$13 (\mul_pipe3_mul_op__insn$46 ),
    .mul_op__insn_type(mul_pipe3_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul_pipe3_mul_op__insn_type$35 ),
    .mul_op__is_32bit(mul_pipe3_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul_pipe3_mul_op__is_32bit$44 ),
    .mul_op__is_signed(mul_pipe3_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul_pipe3_mul_op__is_signed$45 ),
    .mul_op__oe__oe(mul_pipe3_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul_pipe3_mul_op__oe__oe$41 ),
    .mul_op__oe__ok(mul_pipe3_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul_pipe3_mul_op__oe__ok$42 ),
    .mul_op__rc__ok(mul_pipe3_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul_pipe3_mul_op__rc__ok$40 ),
    .mul_op__rc__rc(mul_pipe3_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul_pipe3_mul_op__rc__rc$39 ),
    .mul_op__write_cr0(mul_pipe3_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul_pipe3_mul_op__write_cr0$43 ),
    .muxid(mul_pipe3_muxid),
    .\muxid$1 (\mul_pipe3_muxid$34 ),
    .n_ready_i(mul_pipe3_n_ready_i),
    .n_valid_o(mul_pipe3_n_valid_o),
    .neg_res(mul_pipe3_neg_res),
    .neg_res32(mul_pipe3_neg_res32),
    .o(mul_pipe3_o),
    .\o$14 (\mul_pipe3_o$47 ),
    .o_ok(mul_pipe3_o_ok),
    .p_ready_o(mul_pipe3_p_ready_o),
    .p_valid_i(mul_pipe3_p_valid_i),
    .xer_ov(mul_pipe3_xer_ov),
    .xer_ov_ok(mul_pipe3_xer_ov_ok),
    .xer_so(mul_pipe3_xer_so),
    .\xer_so$15 (\mul_pipe3_xer_so$48 ),
    .xer_so_ok(mul_pipe3_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:29101.10-29104.4" *)
  \n$92  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:29105.10-29108.4" *)
  \p$91  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  assign muxid = 2'h0;
  assign { xer_so_ok, xer_so } = { mul_pipe3_xer_so_ok, \mul_pipe3_xer_so$48  };
  assign { xer_ov_ok, xer_ov } = { mul_pipe3_xer_ov_ok, mul_pipe3_xer_ov };
  assign { cr_a_ok, cr_a } = { mul_pipe3_cr_a_ok, mul_pipe3_cr_a };
  assign { o_ok, o } = { mul_pipe3_o_ok, \mul_pipe3_o$47  };
  assign { \mul_op__insn$61 , \mul_op__is_signed$60 , \mul_op__is_32bit$59 , \mul_op__write_cr0$58 , \mul_op__oe__ok$57 , \mul_op__oe__oe$56 , \mul_op__rc__ok$55 , \mul_op__rc__rc$54 , \mul_op__imm_data__ok$53 , \mul_op__imm_data__data$52 , \mul_op__fn_unit$51 , \mul_op__insn_type$50  } = { \mul_pipe3_mul_op__insn$46 , \mul_pipe3_mul_op__is_signed$45 , \mul_pipe3_mul_op__is_32bit$44 , \mul_pipe3_mul_op__write_cr0$43 , \mul_pipe3_mul_op__oe__ok$42 , \mul_pipe3_mul_op__oe__oe$41 , \mul_pipe3_mul_op__rc__ok$40 , \mul_pipe3_mul_op__rc__rc$39 , \mul_pipe3_mul_op__imm_data__ok$38 , \mul_pipe3_mul_op__imm_data__data$37 , \mul_pipe3_mul_op__fn_unit$36 , \mul_pipe3_mul_op__insn_type$35  };
  assign \muxid$49  = \mul_pipe3_muxid$34 ;
  assign mul_pipe3_n_ready_i = n_ready_i;
  assign n_valid_o = mul_pipe3_n_valid_o;
  assign \mul_pipe1_xer_so$17  = \xer_so$1 ;
  assign \mul_pipe1_rb$16  = rb;
  assign \mul_pipe1_ra$15  = ra;
  assign { \mul_pipe1_mul_op__insn$14 , \mul_pipe1_mul_op__is_signed$13 , \mul_pipe1_mul_op__is_32bit$12 , \mul_pipe1_mul_op__write_cr0$11 , \mul_pipe1_mul_op__oe__ok$10 , \mul_pipe1_mul_op__oe__oe$9 , \mul_pipe1_mul_op__rc__ok$8 , \mul_pipe1_mul_op__rc__rc$7 , \mul_pipe1_mul_op__imm_data__ok$6 , \mul_pipe1_mul_op__imm_data__data$5 , \mul_pipe1_mul_op__fn_unit$4 , \mul_pipe1_mul_op__insn_type$3  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \mul_pipe1_muxid$2  = 2'h0;
  assign p_ready_o = mul_pipe1_p_ready_o;
  assign mul_pipe1_p_valid_i = p_valid_i;
  assign mul_pipe3_neg_res32 = \mul_pipe2_neg_res32$33 ;
  assign mul_pipe3_neg_res = \mul_pipe2_neg_res$32 ;
  assign mul_pipe3_xer_so = \mul_pipe2_xer_so$31 ;
  assign mul_pipe3_o = mul_pipe2_o;
  assign { mul_pipe3_mul_op__insn, mul_pipe3_mul_op__is_signed, mul_pipe3_mul_op__is_32bit, mul_pipe3_mul_op__write_cr0, mul_pipe3_mul_op__oe__ok, mul_pipe3_mul_op__oe__oe, mul_pipe3_mul_op__rc__ok, mul_pipe3_mul_op__rc__rc, mul_pipe3_mul_op__imm_data__ok, mul_pipe3_mul_op__imm_data__data, mul_pipe3_mul_op__fn_unit, mul_pipe3_mul_op__insn_type } = { \mul_pipe2_mul_op__insn$30 , \mul_pipe2_mul_op__is_signed$29 , \mul_pipe2_mul_op__is_32bit$28 , \mul_pipe2_mul_op__write_cr0$27 , \mul_pipe2_mul_op__oe__ok$26 , \mul_pipe2_mul_op__oe__oe$25 , \mul_pipe2_mul_op__rc__ok$24 , \mul_pipe2_mul_op__rc__rc$23 , \mul_pipe2_mul_op__imm_data__ok$22 , \mul_pipe2_mul_op__imm_data__data$21 , \mul_pipe2_mul_op__fn_unit$20 , \mul_pipe2_mul_op__insn_type$19  };
  assign mul_pipe3_muxid = \mul_pipe2_muxid$18 ;
  assign mul_pipe2_n_ready_i = mul_pipe3_p_ready_o;
  assign mul_pipe3_p_valid_i = mul_pipe2_n_valid_o;
  assign mul_pipe2_neg_res32 = mul_pipe1_neg_res32;
  assign mul_pipe2_neg_res = mul_pipe1_neg_res;
  assign mul_pipe2_xer_so = mul_pipe1_xer_so;
  assign mul_pipe2_rb = mul_pipe1_rb;
  assign mul_pipe2_ra = mul_pipe1_ra;
  assign { mul_pipe2_mul_op__insn, mul_pipe2_mul_op__is_signed, mul_pipe2_mul_op__is_32bit, mul_pipe2_mul_op__write_cr0, mul_pipe2_mul_op__oe__ok, mul_pipe2_mul_op__oe__oe, mul_pipe2_mul_op__rc__ok, mul_pipe2_mul_op__rc__rc, mul_pipe2_mul_op__imm_data__ok, mul_pipe2_mul_op__imm_data__data, mul_pipe2_mul_op__fn_unit, mul_pipe2_mul_op__insn_type } = { mul_pipe1_mul_op__insn, mul_pipe1_mul_op__is_signed, mul_pipe1_mul_op__is_32bit, mul_pipe1_mul_op__write_cr0, mul_pipe1_mul_op__oe__ok, mul_pipe1_mul_op__oe__oe, mul_pipe1_mul_op__rc__ok, mul_pipe1_mul_op__rc__rc, mul_pipe1_mul_op__imm_data__ok, mul_pipe1_mul_op__imm_data__data, mul_pipe1_mul_op__fn_unit, mul_pipe1_mul_op__insn_type };
  assign mul_pipe2_muxid = mul_pipe1_muxid;
  assign mul_pipe1_n_ready_i = mul_pipe2_p_ready_o;
  assign mul_pipe2_p_valid_i = mul_pipe1_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:29146.1-30179.10" *)
module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$46 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] pipe1_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe1_muxid$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe1_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe1_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe1_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe1_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_rc;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe1_sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe1_sr_op__fn_unit$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe1_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe1_sr_op__imm_data__data$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__imm_data__ok$6 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe1_sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe1_sr_op__input_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__input_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe1_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe1_sr_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe1_sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe1_sr_op__insn_type$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__invert_in$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__is_32bit$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__is_signed$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__oe__oe$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__oe__ok$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__output_carry$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__output_cr$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__rc__ok$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__rc__rc$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_sr_op__write_cr0$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe1_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \pipe1_xer_ca$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \pipe1_xer_so$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe1_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] pipe2_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \pipe2_cr_a$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_cr_a_ok$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe2_muxid$22 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe2_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe2_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe2_o$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_o_ok$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe2_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe2_p_valid_i;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe2_sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe2_sr_op__fn_unit$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe2_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe2_sr_op__imm_data__data$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__imm_data__ok$26 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] pipe2_sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \pipe2_sr_op__input_carry$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__input_cr$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe2_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe2_sr_op__insn$39 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe2_sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe2_sr_op__insn_type$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__invert_in$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__is_32bit$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__is_signed$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__oe__oe$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__oe__ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__output_carry$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__output_cr$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__rc__ok$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__rc__rc$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_sr_op__write_cr0$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] pipe2_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \pipe2_xer_ca$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe2_xer_ca_ok$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rc;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \sr_op__fn_unit$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \sr_op__imm_data__data$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__imm_data__ok$50 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \sr_op__input_carry$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__input_cr$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \sr_op__insn$63 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \sr_op__insn_type$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__invert_in$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_32bit$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_signed$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__oe$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__ok$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_carry$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_cr$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__ok$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__rc$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__write_cr0$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ca$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30031.11-30034.4" *)
  \n$109  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30035.11-30038.4" *)
  \p$108  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30039.15-30095.4" *)
  \pipe1$110  pipe1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe1_cr_a),
    .cr_a_ok(pipe1_cr_a_ok),
    .muxid(pipe1_muxid),
    .\muxid$1 (\pipe1_muxid$2 ),
    .n_ready_i(pipe1_n_ready_i),
    .n_valid_o(pipe1_n_valid_o),
    .o(pipe1_o),
    .o_ok(pipe1_o_ok),
    .p_ready_o(pipe1_p_ready_o),
    .p_valid_i(pipe1_p_valid_i),
    .ra(pipe1_ra),
    .rb(pipe1_rb),
    .rc(pipe1_rc),
    .sr_op__fn_unit(pipe1_sr_op__fn_unit),
    .\sr_op__fn_unit$3 (\pipe1_sr_op__fn_unit$4 ),
    .sr_op__imm_data__data(pipe1_sr_op__imm_data__data),
    .\sr_op__imm_data__data$4 (\pipe1_sr_op__imm_data__data$5 ),
    .sr_op__imm_data__ok(pipe1_sr_op__imm_data__ok),
    .\sr_op__imm_data__ok$5 (\pipe1_sr_op__imm_data__ok$6 ),
    .sr_op__input_carry(pipe1_sr_op__input_carry),
    .\sr_op__input_carry$12 (\pipe1_sr_op__input_carry$13 ),
    .sr_op__input_cr(pipe1_sr_op__input_cr),
    .\sr_op__input_cr$14 (\pipe1_sr_op__input_cr$15 ),
    .sr_op__insn(pipe1_sr_op__insn),
    .\sr_op__insn$18 (\pipe1_sr_op__insn$19 ),
    .sr_op__insn_type(pipe1_sr_op__insn_type),
    .\sr_op__insn_type$2 (\pipe1_sr_op__insn_type$3 ),
    .sr_op__invert_in(pipe1_sr_op__invert_in),
    .\sr_op__invert_in$11 (\pipe1_sr_op__invert_in$12 ),
    .sr_op__is_32bit(pipe1_sr_op__is_32bit),
    .\sr_op__is_32bit$16 (\pipe1_sr_op__is_32bit$17 ),
    .sr_op__is_signed(pipe1_sr_op__is_signed),
    .\sr_op__is_signed$17 (\pipe1_sr_op__is_signed$18 ),
    .sr_op__oe__oe(pipe1_sr_op__oe__oe),
    .\sr_op__oe__oe$8 (\pipe1_sr_op__oe__oe$9 ),
    .sr_op__oe__ok(pipe1_sr_op__oe__ok),
    .\sr_op__oe__ok$9 (\pipe1_sr_op__oe__ok$10 ),
    .sr_op__output_carry(pipe1_sr_op__output_carry),
    .\sr_op__output_carry$13 (\pipe1_sr_op__output_carry$14 ),
    .sr_op__output_cr(pipe1_sr_op__output_cr),
    .\sr_op__output_cr$15 (\pipe1_sr_op__output_cr$16 ),
    .sr_op__rc__ok(pipe1_sr_op__rc__ok),
    .\sr_op__rc__ok$7 (\pipe1_sr_op__rc__ok$8 ),
    .sr_op__rc__rc(pipe1_sr_op__rc__rc),
    .\sr_op__rc__rc$6 (\pipe1_sr_op__rc__rc$7 ),
    .sr_op__write_cr0(pipe1_sr_op__write_cr0),
    .\sr_op__write_cr0$10 (\pipe1_sr_op__write_cr0$11 ),
    .xer_ca(pipe1_xer_ca),
    .\xer_ca$20 (\pipe1_xer_ca$21 ),
    .xer_ca_ok(pipe1_xer_ca_ok),
    .xer_so(pipe1_xer_so),
    .\xer_so$19 (\pipe1_xer_so$20 ),
    .xer_so_ok(pipe1_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30096.15-30153.4" *)
  \pipe2$115  pipe2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(pipe2_cr_a),
    .\cr_a$21 (\pipe2_cr_a$42 ),
    .cr_a_ok(pipe2_cr_a_ok),
    .\cr_a_ok$22 (\pipe2_cr_a_ok$43 ),
    .muxid(pipe2_muxid),
    .\muxid$1 (\pipe2_muxid$22 ),
    .n_ready_i(pipe2_n_ready_i),
    .n_valid_o(pipe2_n_valid_o),
    .o(pipe2_o),
    .\o$19 (\pipe2_o$40 ),
    .o_ok(pipe2_o_ok),
    .\o_ok$20 (\pipe2_o_ok$41 ),
    .p_ready_o(pipe2_p_ready_o),
    .p_valid_i(pipe2_p_valid_i),
    .sr_op__fn_unit(pipe2_sr_op__fn_unit),
    .\sr_op__fn_unit$3 (\pipe2_sr_op__fn_unit$24 ),
    .sr_op__imm_data__data(pipe2_sr_op__imm_data__data),
    .\sr_op__imm_data__data$4 (\pipe2_sr_op__imm_data__data$25 ),
    .sr_op__imm_data__ok(pipe2_sr_op__imm_data__ok),
    .\sr_op__imm_data__ok$5 (\pipe2_sr_op__imm_data__ok$26 ),
    .sr_op__input_carry(pipe2_sr_op__input_carry),
    .\sr_op__input_carry$12 (\pipe2_sr_op__input_carry$33 ),
    .sr_op__input_cr(pipe2_sr_op__input_cr),
    .\sr_op__input_cr$14 (\pipe2_sr_op__input_cr$35 ),
    .sr_op__insn(pipe2_sr_op__insn),
    .\sr_op__insn$18 (\pipe2_sr_op__insn$39 ),
    .sr_op__insn_type(pipe2_sr_op__insn_type),
    .\sr_op__insn_type$2 (\pipe2_sr_op__insn_type$23 ),
    .sr_op__invert_in(pipe2_sr_op__invert_in),
    .\sr_op__invert_in$11 (\pipe2_sr_op__invert_in$32 ),
    .sr_op__is_32bit(pipe2_sr_op__is_32bit),
    .\sr_op__is_32bit$16 (\pipe2_sr_op__is_32bit$37 ),
    .sr_op__is_signed(pipe2_sr_op__is_signed),
    .\sr_op__is_signed$17 (\pipe2_sr_op__is_signed$38 ),
    .sr_op__oe__oe(pipe2_sr_op__oe__oe),
    .\sr_op__oe__oe$8 (\pipe2_sr_op__oe__oe$29 ),
    .sr_op__oe__ok(pipe2_sr_op__oe__ok),
    .\sr_op__oe__ok$9 (\pipe2_sr_op__oe__ok$30 ),
    .sr_op__output_carry(pipe2_sr_op__output_carry),
    .\sr_op__output_carry$13 (\pipe2_sr_op__output_carry$34 ),
    .sr_op__output_cr(pipe2_sr_op__output_cr),
    .\sr_op__output_cr$15 (\pipe2_sr_op__output_cr$36 ),
    .sr_op__rc__ok(pipe2_sr_op__rc__ok),
    .\sr_op__rc__ok$7 (\pipe2_sr_op__rc__ok$28 ),
    .sr_op__rc__rc(pipe2_sr_op__rc__rc),
    .\sr_op__rc__rc$6 (\pipe2_sr_op__rc__rc$27 ),
    .sr_op__write_cr0(pipe2_sr_op__write_cr0),
    .\sr_op__write_cr0$10 (\pipe2_sr_op__write_cr0$31 ),
    .xer_ca(pipe2_xer_ca),
    .\xer_ca$23 (\pipe2_xer_ca$44 ),
    .xer_ca_ok(pipe2_xer_ca_ok),
    .\xer_ca_ok$24 (\pipe2_xer_ca_ok$45 ),
    .xer_so(pipe2_xer_so),
    .xer_so_ok(pipe2_xer_so_ok)
  );
  assign muxid = 2'h0;
  assign { xer_ca_ok, xer_ca } = { \pipe2_xer_ca_ok$45 , \pipe2_xer_ca$44  };
  assign { cr_a_ok, cr_a } = { \pipe2_cr_a_ok$43 , \pipe2_cr_a$42  };
  assign { o_ok, o } = { \pipe2_o_ok$41 , \pipe2_o$40  };
  assign { \sr_op__insn$63 , \sr_op__is_signed$62 , \sr_op__is_32bit$61 , \sr_op__output_cr$60 , \sr_op__input_cr$59 , \sr_op__output_carry$58 , \sr_op__input_carry$57 , \sr_op__invert_in$56 , \sr_op__write_cr0$55 , \sr_op__oe__ok$54 , \sr_op__oe__oe$53 , \sr_op__rc__ok$52 , \sr_op__rc__rc$51 , \sr_op__imm_data__ok$50 , \sr_op__imm_data__data$49 , \sr_op__fn_unit$48 , \sr_op__insn_type$47  } = { \pipe2_sr_op__insn$39 , \pipe2_sr_op__is_signed$38 , \pipe2_sr_op__is_32bit$37 , \pipe2_sr_op__output_cr$36 , \pipe2_sr_op__input_cr$35 , \pipe2_sr_op__output_carry$34 , \pipe2_sr_op__input_carry$33 , \pipe2_sr_op__invert_in$32 , \pipe2_sr_op__write_cr0$31 , \pipe2_sr_op__oe__ok$30 , \pipe2_sr_op__oe__oe$29 , \pipe2_sr_op__rc__ok$28 , \pipe2_sr_op__rc__rc$27 , \pipe2_sr_op__imm_data__ok$26 , \pipe2_sr_op__imm_data__data$25 , \pipe2_sr_op__fn_unit$24 , \pipe2_sr_op__insn_type$23  };
  assign \muxid$46  = \pipe2_muxid$22 ;
  assign pipe2_n_ready_i = n_ready_i;
  assign n_valid_o = pipe2_n_valid_o;
  assign \pipe1_xer_ca$21  = \xer_ca$1 ;
  assign \pipe1_xer_so$20  = xer_so;
  assign pipe1_rc = rc;
  assign pipe1_rb = rb;
  assign pipe1_ra = ra;
  assign { \pipe1_sr_op__insn$19 , \pipe1_sr_op__is_signed$18 , \pipe1_sr_op__is_32bit$17 , \pipe1_sr_op__output_cr$16 , \pipe1_sr_op__input_cr$15 , \pipe1_sr_op__output_carry$14 , \pipe1_sr_op__input_carry$13 , \pipe1_sr_op__invert_in$12 , \pipe1_sr_op__write_cr0$11 , \pipe1_sr_op__oe__ok$10 , \pipe1_sr_op__oe__oe$9 , \pipe1_sr_op__rc__ok$8 , \pipe1_sr_op__rc__rc$7 , \pipe1_sr_op__imm_data__ok$6 , \pipe1_sr_op__imm_data__data$5 , \pipe1_sr_op__fn_unit$4 , \pipe1_sr_op__insn_type$3  } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
  assign \pipe1_muxid$2  = 2'h0;
  assign p_ready_o = pipe1_p_ready_o;
  assign pipe1_p_valid_i = p_valid_i;
  assign { pipe2_xer_ca_ok, pipe2_xer_ca } = { pipe1_xer_ca_ok, pipe1_xer_ca };
  assign { pipe2_xer_so_ok, pipe2_xer_so } = { pipe1_xer_so_ok, pipe1_xer_so };
  assign { pipe2_cr_a_ok, pipe2_cr_a } = { pipe1_cr_a_ok, pipe1_cr_a };
  assign { pipe2_o_ok, pipe2_o } = { pipe1_o_ok, pipe1_o };
  assign { pipe2_sr_op__insn, pipe2_sr_op__is_signed, pipe2_sr_op__is_32bit, pipe2_sr_op__output_cr, pipe2_sr_op__input_cr, pipe2_sr_op__output_carry, pipe2_sr_op__input_carry, pipe2_sr_op__invert_in, pipe2_sr_op__write_cr0, pipe2_sr_op__oe__ok, pipe2_sr_op__oe__oe, pipe2_sr_op__rc__ok, pipe2_sr_op__rc__rc, pipe2_sr_op__imm_data__ok, pipe2_sr_op__imm_data__data, pipe2_sr_op__fn_unit, pipe2_sr_op__insn_type } = { pipe1_sr_op__insn, pipe1_sr_op__is_signed, pipe1_sr_op__is_32bit, pipe1_sr_op__output_cr, pipe1_sr_op__input_cr, pipe1_sr_op__output_carry, pipe1_sr_op__input_carry, pipe1_sr_op__invert_in, pipe1_sr_op__write_cr0, pipe1_sr_op__oe__ok, pipe1_sr_op__oe__oe, pipe1_sr_op__rc__ok, pipe1_sr_op__rc__rc, pipe1_sr_op__imm_data__ok, pipe1_sr_op__imm_data__data, pipe1_sr_op__fn_unit, pipe1_sr_op__insn_type };
  assign pipe2_muxid = pipe1_muxid;
  assign pipe1_n_ready_i = pipe2_p_ready_o;
  assign pipe2_p_valid_i = pipe1_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:30183.1-30741.10" *)
module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast1$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe_fast1$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe_muxid$6 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe_spr1$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_spr1_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe_spr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe_spr_op__fn_unit$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe_spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe_spr_op__insn$9 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe_spr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe_spr_op__insn_type$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe_spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe_spr_op__is_32bit$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] pipe_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \pipe_xer_ca$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] pipe_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \pipe_xer_ov$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire pipe_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \pipe_xer_so$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \spr1$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] spr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \spr_op__fn_unit$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \spr_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] spr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \spr_op__insn_type$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \spr_op__is_32bit$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ca$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ov$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30676.10-30679.4" *)
  \n$63  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30680.10-30683.4" *)
  \p$62  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:30684.13-30719.4" *)
  \pipe$64  pipe (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .fast1(pipe_fast1),
    .\fast1$7 (\pipe_fast1$12 ),
    .fast1_ok(pipe_fast1_ok),
    .muxid(pipe_muxid),
    .\muxid$1 (\pipe_muxid$6 ),
    .n_ready_i(pipe_n_ready_i),
    .n_valid_o(pipe_n_valid_o),
    .o(pipe_o),
    .o_ok(pipe_o_ok),
    .p_ready_o(pipe_p_ready_o),
    .p_valid_i(pipe_p_valid_i),
    .ra(pipe_ra),
    .spr1(pipe_spr1),
    .\spr1$6 (\pipe_spr1$11 ),
    .spr1_ok(pipe_spr1_ok),
    .spr_op__fn_unit(pipe_spr_op__fn_unit),
    .\spr_op__fn_unit$3 (\pipe_spr_op__fn_unit$8 ),
    .spr_op__insn(pipe_spr_op__insn),
    .\spr_op__insn$4 (\pipe_spr_op__insn$9 ),
    .spr_op__insn_type(pipe_spr_op__insn_type),
    .\spr_op__insn_type$2 (\pipe_spr_op__insn_type$7 ),
    .spr_op__is_32bit(pipe_spr_op__is_32bit),
    .\spr_op__is_32bit$5 (\pipe_spr_op__is_32bit$10 ),
    .xer_ca(pipe_xer_ca),
    .\xer_ca$10 (\pipe_xer_ca$15 ),
    .xer_ca_ok(pipe_xer_ca_ok),
    .xer_ov(pipe_xer_ov),
    .\xer_ov$9 (\pipe_xer_ov$14 ),
    .xer_ov_ok(pipe_xer_ov_ok),
    .xer_so(pipe_xer_so),
    .\xer_so$8 (\pipe_xer_so$13 ),
    .xer_so_ok(pipe_xer_so_ok)
  );
  assign muxid = 2'h0;
  assign { xer_ca_ok, xer_ca } = { pipe_xer_ca_ok, \pipe_xer_ca$15  };
  assign { xer_ov_ok, xer_ov } = { pipe_xer_ov_ok, \pipe_xer_ov$14  };
  assign { xer_so_ok, xer_so } = { pipe_xer_so_ok, \pipe_xer_so$13  };
  assign { fast1_ok, fast1 } = { pipe_fast1_ok, \pipe_fast1$12  };
  assign { spr1_ok, spr1 } = { pipe_spr1_ok, \pipe_spr1$11  };
  assign { o_ok, o } = { pipe_o_ok, pipe_o };
  assign { \spr_op__is_32bit$20 , \spr_op__insn$19 , \spr_op__fn_unit$18 , \spr_op__insn_type$17  } = { \pipe_spr_op__is_32bit$10 , \pipe_spr_op__insn$9 , \pipe_spr_op__fn_unit$8 , \pipe_spr_op__insn_type$7  };
  assign \muxid$16  = \pipe_muxid$6 ;
  assign pipe_n_ready_i = n_ready_i;
  assign n_valid_o = pipe_n_valid_o;
  assign pipe_xer_ca = \xer_ca$5 ;
  assign pipe_xer_ov = \xer_ov$4 ;
  assign pipe_xer_so = \xer_so$3 ;
  assign pipe_fast1 = \fast1$2 ;
  assign pipe_spr1 = \spr1$1 ;
  assign pipe_ra = ra;
  assign { pipe_spr_op__is_32bit, pipe_spr_op__insn, pipe_spr_op__fn_unit, pipe_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
  assign pipe_muxid = 2'h0;
  assign p_ready_o = pipe_p_ready_o;
  assign pipe_p_valid_i = p_valid_i;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:30745.1-31618.10" *)
module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, nia_ok, msr_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, o, fast1, fast2, nia, msr, ra, rb, \fast1$1 , \fast2$2 , p_valid_i, p_ready_o, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast1$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast2$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output msr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe1_fast1$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe1_fast2$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe1_muxid$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe1_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe1_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe1_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe1_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe1_ra$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \pipe1_rb$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe1_trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe1_trap_op__cia$8 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe1_trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe1_trap_op__fn_unit$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe1_trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe1_trap_op__insn$6 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe1_trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe1_trap_op__insn_type$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe1_trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe1_trap_op__is_32bit$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] pipe1_trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \pipe1_trap_op__ldst_exc$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe1_trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe1_trap_op__msr$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] pipe1_trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \pipe1_trap_op__trapaddr$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] pipe1_trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \pipe1_trap_op__traptype$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe2_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe2_fast1$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe2_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \pipe2_fast2$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe2_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_msr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] pipe2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \pipe2_muxid$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire pipe2_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire pipe2_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe2_nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pipe2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pipe2_o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire pipe2_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire pipe2_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe2_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] pipe2_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe2_trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe2_trap_op__cia$22 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] pipe2_trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \pipe2_trap_op__fn_unit$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] pipe2_trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \pipe2_trap_op__insn$20 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] pipe2_trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \pipe2_trap_op__insn_type$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire pipe2_trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \pipe2_trap_op__is_32bit$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] pipe2_trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \pipe2_trap_op__ldst_exc$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] pipe2_trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \pipe2_trap_op__msr$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] pipe2_trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \pipe2_trap_op__trapaddr$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] pipe2_trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \pipe2_trap_op__traptype$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__cia$34 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \trap_op__fn_unit$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \trap_op__insn$32 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \trap_op__insn_type$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \trap_op__is_32bit$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__ldst_exc$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__msr$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \trap_op__trapaddr$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__traptype$36 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:31506.10-31509.4" *)
  \n$31  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:31510.10-31513.4" *)
  \p$30  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:31514.14-31549.4" *)
  \pipe1$32  pipe1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .fast1(pipe1_fast1),
    .\fast1$13 (\pipe1_fast1$15 ),
    .fast2(pipe1_fast2),
    .\fast2$14 (\pipe1_fast2$16 ),
    .muxid(pipe1_muxid),
    .\muxid$1 (\pipe1_muxid$3 ),
    .n_ready_i(pipe1_n_ready_i),
    .n_valid_o(pipe1_n_valid_o),
    .p_ready_o(pipe1_p_ready_o),
    .p_valid_i(pipe1_p_valid_i),
    .ra(pipe1_ra),
    .\ra$11 (\pipe1_ra$13 ),
    .rb(pipe1_rb),
    .\rb$12 (\pipe1_rb$14 ),
    .trap_op__cia(pipe1_trap_op__cia),
    .\trap_op__cia$6 (\pipe1_trap_op__cia$8 ),
    .trap_op__fn_unit(pipe1_trap_op__fn_unit),
    .\trap_op__fn_unit$3 (\pipe1_trap_op__fn_unit$5 ),
    .trap_op__insn(pipe1_trap_op__insn),
    .\trap_op__insn$4 (\pipe1_trap_op__insn$6 ),
    .trap_op__insn_type(pipe1_trap_op__insn_type),
    .\trap_op__insn_type$2 (\pipe1_trap_op__insn_type$4 ),
    .trap_op__is_32bit(pipe1_trap_op__is_32bit),
    .\trap_op__is_32bit$7 (\pipe1_trap_op__is_32bit$9 ),
    .trap_op__ldst_exc(pipe1_trap_op__ldst_exc),
    .\trap_op__ldst_exc$10 (\pipe1_trap_op__ldst_exc$12 ),
    .trap_op__msr(pipe1_trap_op__msr),
    .\trap_op__msr$5 (\pipe1_trap_op__msr$7 ),
    .trap_op__trapaddr(pipe1_trap_op__trapaddr),
    .\trap_op__trapaddr$9 (\pipe1_trap_op__trapaddr$11 ),
    .trap_op__traptype(pipe1_trap_op__traptype),
    .\trap_op__traptype$8 (\pipe1_trap_op__traptype$10 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:31550.14-31591.4" *)
  \pipe2$35  pipe2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .fast1(pipe2_fast1),
    .\fast1$11 (\pipe2_fast1$27 ),
    .fast1_ok(pipe2_fast1_ok),
    .fast2(pipe2_fast2),
    .\fast2$12 (\pipe2_fast2$28 ),
    .fast2_ok(pipe2_fast2_ok),
    .msr(pipe2_msr),
    .msr_ok(pipe2_msr_ok),
    .muxid(pipe2_muxid),
    .\muxid$1 (\pipe2_muxid$17 ),
    .n_ready_i(pipe2_n_ready_i),
    .n_valid_o(pipe2_n_valid_o),
    .nia(pipe2_nia),
    .nia_ok(pipe2_nia_ok),
    .o(pipe2_o),
    .o_ok(pipe2_o_ok),
    .p_ready_o(pipe2_p_ready_o),
    .p_valid_i(pipe2_p_valid_i),
    .ra(pipe2_ra),
    .rb(pipe2_rb),
    .trap_op__cia(pipe2_trap_op__cia),
    .\trap_op__cia$6 (\pipe2_trap_op__cia$22 ),
    .trap_op__fn_unit(pipe2_trap_op__fn_unit),
    .\trap_op__fn_unit$3 (\pipe2_trap_op__fn_unit$19 ),
    .trap_op__insn(pipe2_trap_op__insn),
    .\trap_op__insn$4 (\pipe2_trap_op__insn$20 ),
    .trap_op__insn_type(pipe2_trap_op__insn_type),
    .\trap_op__insn_type$2 (\pipe2_trap_op__insn_type$18 ),
    .trap_op__is_32bit(pipe2_trap_op__is_32bit),
    .\trap_op__is_32bit$7 (\pipe2_trap_op__is_32bit$23 ),
    .trap_op__ldst_exc(pipe2_trap_op__ldst_exc),
    .\trap_op__ldst_exc$10 (\pipe2_trap_op__ldst_exc$26 ),
    .trap_op__msr(pipe2_trap_op__msr),
    .\trap_op__msr$5 (\pipe2_trap_op__msr$21 ),
    .trap_op__trapaddr(pipe2_trap_op__trapaddr),
    .\trap_op__trapaddr$9 (\pipe2_trap_op__trapaddr$25 ),
    .trap_op__traptype(pipe2_trap_op__traptype),
    .\trap_op__traptype$8 (\pipe2_trap_op__traptype$24 )
  );
  assign muxid = 2'h0;
  assign { msr_ok, msr } = { pipe2_msr_ok, pipe2_msr };
  assign { nia_ok, nia } = { pipe2_nia_ok, pipe2_nia };
  assign { fast2_ok, fast2 } = { pipe2_fast2_ok, \pipe2_fast2$28  };
  assign { fast1_ok, fast1 } = { pipe2_fast1_ok, \pipe2_fast1$27  };
  assign { o_ok, o } = { pipe2_o_ok, pipe2_o };
  assign { \trap_op__ldst_exc$38 , \trap_op__trapaddr$37 , \trap_op__traptype$36 , \trap_op__is_32bit$35 , \trap_op__cia$34 , \trap_op__msr$33 , \trap_op__insn$32 , \trap_op__fn_unit$31 , \trap_op__insn_type$30  } = { \pipe2_trap_op__ldst_exc$26 , \pipe2_trap_op__trapaddr$25 , \pipe2_trap_op__traptype$24 , \pipe2_trap_op__is_32bit$23 , \pipe2_trap_op__cia$22 , \pipe2_trap_op__msr$21 , \pipe2_trap_op__insn$20 , \pipe2_trap_op__fn_unit$19 , \pipe2_trap_op__insn_type$18  };
  assign \muxid$29  = \pipe2_muxid$17 ;
  assign pipe2_n_ready_i = n_ready_i;
  assign n_valid_o = pipe2_n_valid_o;
  assign \pipe1_fast2$16  = \fast2$2 ;
  assign \pipe1_fast1$15  = \fast1$1 ;
  assign \pipe1_rb$14  = rb;
  assign \pipe1_ra$13  = ra;
  assign { \pipe1_trap_op__ldst_exc$12 , \pipe1_trap_op__trapaddr$11 , \pipe1_trap_op__traptype$10 , \pipe1_trap_op__is_32bit$9 , \pipe1_trap_op__cia$8 , \pipe1_trap_op__msr$7 , \pipe1_trap_op__insn$6 , \pipe1_trap_op__fn_unit$5 , \pipe1_trap_op__insn_type$4  } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
  assign \pipe1_muxid$3  = 2'h0;
  assign p_ready_o = pipe1_p_ready_o;
  assign pipe1_p_valid_i = p_valid_i;
  assign pipe2_fast2 = pipe1_fast2;
  assign pipe2_fast1 = pipe1_fast1;
  assign pipe2_rb = pipe1_rb;
  assign pipe2_ra = pipe1_ra;
  assign { pipe2_trap_op__ldst_exc, pipe2_trap_op__trapaddr, pipe2_trap_op__traptype, pipe2_trap_op__is_32bit, pipe2_trap_op__cia, pipe2_trap_op__msr, pipe2_trap_op__insn, pipe2_trap_op__fn_unit, pipe2_trap_op__insn_type } = { pipe1_trap_op__ldst_exc, pipe1_trap_op__trapaddr, pipe1_trap_op__traptype, pipe1_trap_op__is_32bit, pipe1_trap_op__cia, pipe1_trap_op__msr, pipe1_trap_op__insn, pipe1_trap_op__fn_unit, pipe1_trap_op__insn_type };
  assign pipe2_muxid = pipe1_muxid;
  assign pipe1_n_ready_i = pipe2_p_ready_o;
  assign pipe2_p_valid_i = pipe1_n_valid_o;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31622.1-31680.10" *)
module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31623.7-31623.20" *)
  reg _00_;
  (* src = "libresoc.v:31668.3-31676.6" *)
  reg _01_;
  (* src = "libresoc.v:31666.3-31667.27" *)
  reg _02_;
  (* src = "libresoc.v:31668.3-31676.6" *)
  reg _03_;
  (* src = "libresoc.v:31647.7-31647.19" *)
  reg _04_;
  (* src = "libresoc.v:31658.17-31658.96" *)
  wire _05_;
  (* src = "libresoc.v:31663.17-31663.96" *)
  wire _06_;
  (* src = "libresoc.v:31660.18-31660.94" *)
  wire _07_;
  (* src = "libresoc.v:31662.17-31662.93" *)
  wire _08_;
  (* src = "libresoc.v:31665.17-31665.93" *)
  wire _09_;
  (* src = "libresoc.v:31659.18-31659.99" *)
  wire _10_;
  (* src = "libresoc.v:31661.18-31661.100" *)
  wire _11_;
  (* src = "libresoc.v:31664.17-31664.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31623.7-31623.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31669.5-31669.29" *)
    casez (\initial )
      /* src = "libresoc.v:31669.9-31669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31684.1-31742.10" *)
module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31685.7-31685.20" *)
  reg _00_;
  (* src = "libresoc.v:31730.3-31738.6" *)
  reg _01_;
  (* src = "libresoc.v:31728.3-31729.27" *)
  reg _02_;
  (* src = "libresoc.v:31730.3-31738.6" *)
  reg _03_;
  (* src = "libresoc.v:31709.7-31709.19" *)
  reg _04_;
  (* src = "libresoc.v:31720.17-31720.96" *)
  wire _05_;
  (* src = "libresoc.v:31725.17-31725.96" *)
  wire _06_;
  (* src = "libresoc.v:31722.18-31722.94" *)
  wire _07_;
  (* src = "libresoc.v:31724.17-31724.93" *)
  wire _08_;
  (* src = "libresoc.v:31727.17-31727.93" *)
  wire _09_;
  (* src = "libresoc.v:31721.18-31721.99" *)
  wire _10_;
  (* src = "libresoc.v:31723.18-31723.100" *)
  wire _11_;
  (* src = "libresoc.v:31726.17-31726.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31685.7-31685.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31731.5-31731.29" *)
    casez (\initial )
      /* src = "libresoc.v:31731.9-31731.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31746.1-31804.10" *)
module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31747.7-31747.20" *)
  reg _00_;
  (* src = "libresoc.v:31792.3-31800.6" *)
  reg _01_;
  (* src = "libresoc.v:31790.3-31791.27" *)
  reg _02_;
  (* src = "libresoc.v:31792.3-31800.6" *)
  reg _03_;
  (* src = "libresoc.v:31771.7-31771.19" *)
  reg _04_;
  (* src = "libresoc.v:31782.17-31782.96" *)
  wire _05_;
  (* src = "libresoc.v:31787.17-31787.96" *)
  wire _06_;
  (* src = "libresoc.v:31784.18-31784.94" *)
  wire _07_;
  (* src = "libresoc.v:31786.17-31786.93" *)
  wire _08_;
  (* src = "libresoc.v:31789.17-31789.93" *)
  wire _09_;
  (* src = "libresoc.v:31783.18-31783.99" *)
  wire _10_;
  (* src = "libresoc.v:31785.18-31785.100" *)
  wire _11_;
  (* src = "libresoc.v:31788.17-31788.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31747.7-31747.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31793.5-31793.29" *)
    casez (\initial )
      /* src = "libresoc.v:31793.9-31793.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31808.1-31866.10" *)
module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31809.7-31809.20" *)
  reg _00_;
  (* src = "libresoc.v:31854.3-31862.6" *)
  reg _01_;
  (* src = "libresoc.v:31852.3-31853.27" *)
  reg _02_;
  (* src = "libresoc.v:31854.3-31862.6" *)
  reg _03_;
  (* src = "libresoc.v:31833.7-31833.19" *)
  reg _04_;
  (* src = "libresoc.v:31844.17-31844.96" *)
  wire _05_;
  (* src = "libresoc.v:31849.17-31849.96" *)
  wire _06_;
  (* src = "libresoc.v:31846.18-31846.94" *)
  wire _07_;
  (* src = "libresoc.v:31848.17-31848.93" *)
  wire _08_;
  (* src = "libresoc.v:31851.17-31851.93" *)
  wire _09_;
  (* src = "libresoc.v:31845.18-31845.99" *)
  wire _10_;
  (* src = "libresoc.v:31847.18-31847.100" *)
  wire _11_;
  (* src = "libresoc.v:31850.17-31850.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31809.7-31809.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31855.5-31855.29" *)
    casez (\initial )
      /* src = "libresoc.v:31855.9-31855.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31870.1-31928.10" *)
module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31871.7-31871.20" *)
  reg _00_;
  (* src = "libresoc.v:31916.3-31924.6" *)
  reg _01_;
  (* src = "libresoc.v:31914.3-31915.27" *)
  reg _02_;
  (* src = "libresoc.v:31916.3-31924.6" *)
  reg _03_;
  (* src = "libresoc.v:31895.7-31895.19" *)
  reg _04_;
  (* src = "libresoc.v:31906.17-31906.96" *)
  wire _05_;
  (* src = "libresoc.v:31911.17-31911.96" *)
  wire _06_;
  (* src = "libresoc.v:31908.18-31908.94" *)
  wire _07_;
  (* src = "libresoc.v:31910.17-31910.93" *)
  wire _08_;
  (* src = "libresoc.v:31913.17-31913.93" *)
  wire _09_;
  (* src = "libresoc.v:31907.18-31907.99" *)
  wire _10_;
  (* src = "libresoc.v:31909.18-31909.100" *)
  wire _11_;
  (* src = "libresoc.v:31912.17-31912.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31871.7-31871.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31917.5-31917.29" *)
    casez (\initial )
      /* src = "libresoc.v:31917.9-31917.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31932.1-31990.10" *)
module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31933.7-31933.20" *)
  reg _00_;
  (* src = "libresoc.v:31978.3-31986.6" *)
  reg _01_;
  (* src = "libresoc.v:31976.3-31977.27" *)
  reg _02_;
  (* src = "libresoc.v:31978.3-31986.6" *)
  reg _03_;
  (* src = "libresoc.v:31957.7-31957.19" *)
  reg _04_;
  (* src = "libresoc.v:31968.17-31968.96" *)
  wire _05_;
  (* src = "libresoc.v:31973.17-31973.96" *)
  wire _06_;
  (* src = "libresoc.v:31970.18-31970.94" *)
  wire _07_;
  (* src = "libresoc.v:31972.17-31972.93" *)
  wire _08_;
  (* src = "libresoc.v:31975.17-31975.93" *)
  wire _09_;
  (* src = "libresoc.v:31969.18-31969.99" *)
  wire _10_;
  (* src = "libresoc.v:31971.18-31971.100" *)
  wire _11_;
  (* src = "libresoc.v:31974.17-31974.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31933.7-31933.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:31979.5-31979.29" *)
    casez (\initial )
      /* src = "libresoc.v:31979.9-31979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:31994.1-32052.10" *)
module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:31995.7-31995.20" *)
  reg _00_;
  (* src = "libresoc.v:32040.3-32048.6" *)
  reg _01_;
  (* src = "libresoc.v:32038.3-32039.27" *)
  reg _02_;
  (* src = "libresoc.v:32040.3-32048.6" *)
  reg _03_;
  (* src = "libresoc.v:32019.7-32019.19" *)
  reg _04_;
  (* src = "libresoc.v:32030.17-32030.96" *)
  wire _05_;
  (* src = "libresoc.v:32035.17-32035.96" *)
  wire _06_;
  (* src = "libresoc.v:32032.18-32032.94" *)
  wire _07_;
  (* src = "libresoc.v:32034.17-32034.93" *)
  wire _08_;
  (* src = "libresoc.v:32037.17-32037.93" *)
  wire _09_;
  (* src = "libresoc.v:32031.18-32031.99" *)
  wire _10_;
  (* src = "libresoc.v:32033.18-32033.100" *)
  wire _11_;
  (* src = "libresoc.v:32036.17-32036.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:31995.7-31995.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:32041.5-32041.29" *)
    casez (\initial )
      /* src = "libresoc.v:32041.9-32041.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:32056.1-32114.10" *)
module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:32057.7-32057.20" *)
  reg _00_;
  (* src = "libresoc.v:32102.3-32110.6" *)
  reg _01_;
  (* src = "libresoc.v:32100.3-32101.27" *)
  reg _02_;
  (* src = "libresoc.v:32102.3-32110.6" *)
  reg _03_;
  (* src = "libresoc.v:32081.7-32081.19" *)
  reg _04_;
  (* src = "libresoc.v:32092.17-32092.96" *)
  wire _05_;
  (* src = "libresoc.v:32097.17-32097.96" *)
  wire _06_;
  (* src = "libresoc.v:32094.18-32094.94" *)
  wire _07_;
  (* src = "libresoc.v:32096.17-32096.93" *)
  wire _08_;
  (* src = "libresoc.v:32099.17-32099.93" *)
  wire _09_;
  (* src = "libresoc.v:32093.18-32093.99" *)
  wire _10_;
  (* src = "libresoc.v:32095.18-32095.100" *)
  wire _11_;
  (* src = "libresoc.v:32098.17-32098.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:32057.7-32057.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:32103.5-32103.29" *)
    casez (\initial )
      /* src = "libresoc.v:32103.9-32103.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alui_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:32118.1-32176.10" *)
module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:32119.7-32119.20" *)
  reg _00_;
  (* src = "libresoc.v:32164.3-32172.6" *)
  reg _01_;
  (* src = "libresoc.v:32162.3-32163.27" *)
  reg _02_;
  (* src = "libresoc.v:32164.3-32172.6" *)
  reg _03_;
  (* src = "libresoc.v:32143.7-32143.19" *)
  reg _04_;
  (* src = "libresoc.v:32154.17-32154.96" *)
  wire _05_;
  (* src = "libresoc.v:32159.17-32159.96" *)
  wire _06_;
  (* src = "libresoc.v:32156.18-32156.94" *)
  wire _07_;
  (* src = "libresoc.v:32158.17-32158.93" *)
  wire _08_;
  (* src = "libresoc.v:32161.17-32161.93" *)
  wire _09_;
  (* src = "libresoc.v:32155.18-32155.99" *)
  wire _10_;
  (* src = "libresoc.v:32157.18-32157.100" *)
  wire _11_;
  (* src = "libresoc.v:32160.17-32160.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:32119.7-32119.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_alui;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_alui;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_alui;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_alui;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_alui;
  assign _11_ = q_alui | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_alui;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:32165.5-32165.29" *)
    casez (\initial )
      /* src = "libresoc.v:32165.9-32165.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_alui = \$15 ;
  assign qn_alui = \$13 ;
  assign q_alui = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:32180.1-33524.10" *)
module bpermd(rb, ra, rs);
  reg \initial  = 0;
  (* src = "libresoc.v:32181.7-32181.20" *)
  reg _00_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _02_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _03_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _04_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _05_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _06_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _07_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _08_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _09_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _10_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _11_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _12_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _13_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _14_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _15_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _16_;
  (* src = "libresoc.v:32358.3-33449.6" *)
  reg _17_;
  (* src = "libresoc.v:32350.17-32350.104" *)
  wire _18_;
  (* src = "libresoc.v:32351.18-32351.105" *)
  wire _19_;
  (* src = "libresoc.v:32352.18-32352.105" *)
  wire _20_;
  (* src = "libresoc.v:32353.18-32353.105" *)
  wire _21_;
  (* src = "libresoc.v:32354.17-32354.104" *)
  wire _22_;
  (* src = "libresoc.v:32355.17-32355.104" *)
  wire _23_;
  (* src = "libresoc.v:32356.17-32356.104" *)
  wire _24_;
  (* src = "libresoc.v:32357.17-32357.104" *)
  wire _25_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" *)
  wire [7:0] idx_7;
  (* src = "libresoc.v:32181.7-32181.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" *)
  reg [63:0] perm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" *)
  output [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_19;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_20;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_21;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_22;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_23;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_24;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_25;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_26;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_27;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_28;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_29;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_30;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_31;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_33;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_34;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_35;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_36;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_37;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_38;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_39;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_40;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_41;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_42;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_43;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_44;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_45;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_46;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_47;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_48;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_49;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_50;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_51;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_52;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_53;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_54;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_55;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_56;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_57;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_58;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_59;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_60;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_61;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_62;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_63;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" *)
  wire rb64_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" *)
  input [63:0] rs;
  assign _18_ = idx_4 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _19_ = idx_5 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _20_ = idx_6 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _21_ = idx_7 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _22_ = idx_0 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _23_ = idx_1 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _24_ = idx_2 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  assign _25_ = idx_3 < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *) 7'h40;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_[63:8] = 56'h00000000000000;
    _01_[0] = _09_;
    _01_[1] = _11_;
    _01_[2] = _13_;
    _01_[3] = _15_;
    _01_[4] = _17_;
    _01_[5] = _03_;
    _01_[6] = _05_;
    _01_[7] = _07_;
    (* src = "libresoc.v:32359.5-32359.29" *)
    casez (\initial )
      /* src = "libresoc.v:32359.9-32359.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _09_ = _10_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_0)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _10_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _10_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _10_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _10_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _10_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _10_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _10_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _10_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _10_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _10_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _10_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _10_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _10_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _10_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _10_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _10_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _10_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _10_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _10_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _10_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _10_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _10_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _10_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _10_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _10_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _10_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _10_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _10_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _10_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _10_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _10_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _10_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _10_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _10_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _10_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _10_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _10_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _10_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _10_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _10_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _10_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _10_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _10_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _10_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _10_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _10_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _10_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _10_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _10_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _10_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _10_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _10_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _10_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _10_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _10_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _10_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _10_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _10_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _10_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _10_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _10_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _10_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _10_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _10_ = rb64_63;
              end
            default:
                _10_ = 1'h0;
          endcase
        end
      default:
          _09_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$3 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _11_ = _12_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_1)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _12_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _12_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _12_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _12_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _12_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _12_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _12_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _12_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _12_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _12_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _12_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _12_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _12_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _12_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _12_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _12_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _12_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _12_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _12_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _12_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _12_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _12_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _12_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _12_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _12_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _12_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _12_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _12_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _12_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _12_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _12_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _12_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _12_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _12_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _12_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _12_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _12_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _12_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _12_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _12_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _12_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _12_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _12_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _12_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _12_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _12_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _12_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _12_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _12_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _12_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _12_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _12_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _12_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _12_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _12_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _12_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _12_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _12_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _12_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _12_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _12_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _12_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _12_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _12_ = rb64_63;
              end
            default:
                _12_ = 1'h0;
          endcase
        end
      default:
          _11_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$5 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = _14_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_2)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _14_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _14_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _14_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _14_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _14_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _14_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _14_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _14_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _14_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _14_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _14_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _14_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _14_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _14_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _14_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _14_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _14_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _14_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _14_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _14_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _14_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _14_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _14_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _14_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _14_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _14_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _14_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _14_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _14_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _14_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _14_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _14_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _14_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _14_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _14_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _14_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _14_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _14_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _14_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _14_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _14_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _14_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _14_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _14_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _14_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _14_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _14_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _14_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _14_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _14_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _14_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _14_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _14_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _14_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _14_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _14_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _14_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _14_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _14_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _14_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _14_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _14_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _14_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _14_ = rb64_63;
              end
            default:
                _14_ = 1'h0;
          endcase
        end
      default:
          _13_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$7 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = _16_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_3)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _16_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _16_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _16_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _16_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _16_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _16_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _16_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _16_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _16_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _16_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _16_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _16_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _16_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _16_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _16_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _16_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _16_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _16_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _16_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _16_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _16_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _16_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _16_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _16_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _16_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _16_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _16_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _16_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _16_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _16_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _16_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _16_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _16_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _16_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _16_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _16_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _16_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _16_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _16_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _16_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _16_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _16_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _16_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _16_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _16_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _16_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _16_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _16_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _16_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _16_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _16_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _16_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _16_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _16_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _16_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _16_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _16_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _16_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _16_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _16_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _16_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _16_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _16_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _16_ = rb64_63;
              end
            default:
                _16_ = 1'h0;
          endcase
        end
      default:
          _15_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = _02_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_4)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _02_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _02_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _02_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _02_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _02_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _02_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _02_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _02_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _02_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _02_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _02_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _02_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _02_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _02_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _02_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _02_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _02_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _02_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _02_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _02_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _02_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _02_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _02_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _02_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _02_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _02_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _02_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _02_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _02_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _02_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _02_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _02_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _02_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _02_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _02_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _02_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _02_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _02_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _02_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _02_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _02_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _02_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _02_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _02_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _02_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _02_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _02_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _02_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _02_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _02_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _02_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _02_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _02_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _02_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _02_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _02_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _02_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _02_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _02_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _02_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _02_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _02_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _02_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _02_ = rb64_63;
              end
            default:
                _02_ = 1'h0;
          endcase
        end
      default:
          _17_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$11 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = _04_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_5)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _04_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _04_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _04_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _04_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _04_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _04_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _04_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _04_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _04_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _04_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _04_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _04_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _04_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _04_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _04_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _04_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _04_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _04_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _04_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _04_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _04_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _04_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _04_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _04_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _04_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _04_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _04_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _04_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _04_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _04_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _04_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _04_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _04_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _04_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _04_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _04_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _04_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _04_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _04_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _04_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _04_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _04_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _04_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _04_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _04_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _04_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _04_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _04_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _04_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _04_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _04_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _04_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _04_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _04_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _04_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _04_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _04_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _04_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _04_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _04_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _04_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _04_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _04_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _04_ = rb64_63;
              end
            default:
                _04_ = 1'h0;
          endcase
        end
      default:
          _03_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _05_ = _06_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_6)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _06_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _06_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _06_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _06_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _06_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _06_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _06_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _06_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _06_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _06_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _06_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _06_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _06_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _06_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _06_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _06_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _06_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _06_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _06_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _06_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _06_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _06_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _06_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _06_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _06_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _06_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _06_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _06_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _06_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _06_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _06_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _06_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _06_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _06_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _06_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _06_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _06_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _06_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _06_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _06_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _06_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _06_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _06_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _06_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _06_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _06_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _06_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _06_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _06_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _06_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _06_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _06_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _06_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _06_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _06_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _06_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _06_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _06_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _06_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _06_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _06_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _06_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _06_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _06_ = rb64_63;
              end
            default:
                _06_ = 1'h0;
          endcase
        end
      default:
          _05_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" *)
    casez (\$15 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _07_ = _08_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" *)
          casez (idx_7)
            /* src = "libresoc.v:0.0-0.0" */
            8'h00:
              begin
                _08_ = rb64_0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h01:
              begin
                _08_ = rb64_1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h02:
              begin
                _08_ = rb64_2;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h03:
              begin
                _08_ = rb64_3;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h04:
              begin
                _08_ = rb64_4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h05:
              begin
                _08_ = rb64_5;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h06:
              begin
                _08_ = rb64_6;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h07:
              begin
                _08_ = rb64_7;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h08:
              begin
                _08_ = rb64_8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h09:
              begin
                _08_ = rb64_9;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0a:
              begin
                _08_ = rb64_10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0b:
              begin
                _08_ = rb64_11;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0c:
              begin
                _08_ = rb64_12;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0d:
              begin
                _08_ = rb64_13;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0e:
              begin
                _08_ = rb64_14;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h0f:
              begin
                _08_ = rb64_15;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h10:
              begin
                _08_ = rb64_16;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h11:
              begin
                _08_ = rb64_17;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h12:
              begin
                _08_ = rb64_18;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h13:
              begin
                _08_ = rb64_19;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h14:
              begin
                _08_ = rb64_20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h15:
              begin
                _08_ = rb64_21;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h16:
              begin
                _08_ = rb64_22;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h17:
              begin
                _08_ = rb64_23;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h18:
              begin
                _08_ = rb64_24;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h19:
              begin
                _08_ = rb64_25;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1a:
              begin
                _08_ = rb64_26;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1b:
              begin
                _08_ = rb64_27;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1c:
              begin
                _08_ = rb64_28;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1d:
              begin
                _08_ = rb64_29;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1e:
              begin
                _08_ = rb64_30;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h1f:
              begin
                _08_ = rb64_31;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h20:
              begin
                _08_ = rb64_32;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h21:
              begin
                _08_ = rb64_33;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h22:
              begin
                _08_ = rb64_34;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h23:
              begin
                _08_ = rb64_35;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h24:
              begin
                _08_ = rb64_36;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h25:
              begin
                _08_ = rb64_37;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h26:
              begin
                _08_ = rb64_38;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h27:
              begin
                _08_ = rb64_39;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h28:
              begin
                _08_ = rb64_40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h29:
              begin
                _08_ = rb64_41;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2a:
              begin
                _08_ = rb64_42;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2b:
              begin
                _08_ = rb64_43;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2c:
              begin
                _08_ = rb64_44;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2d:
              begin
                _08_ = rb64_45;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2e:
              begin
                _08_ = rb64_46;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h2f:
              begin
                _08_ = rb64_47;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h30:
              begin
                _08_ = rb64_48;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h31:
              begin
                _08_ = rb64_49;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h32:
              begin
                _08_ = rb64_50;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h33:
              begin
                _08_ = rb64_51;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h34:
              begin
                _08_ = rb64_52;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h35:
              begin
                _08_ = rb64_53;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h36:
              begin
                _08_ = rb64_54;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h37:
              begin
                _08_ = rb64_55;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h38:
              begin
                _08_ = rb64_56;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h39:
              begin
                _08_ = rb64_57;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3a:
              begin
                _08_ = rb64_58;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3b:
              begin
                _08_ = rb64_59;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3c:
              begin
                _08_ = rb64_60;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3d:
              begin
                _08_ = rb64_61;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h3e:
              begin
                _08_ = rb64_62;
              end
            /* src = "libresoc.v:0.0-0.0" */
            8'h??:
              begin
                _08_ = rb64_63;
              end
            default:
                _08_ = 1'h0;
          endcase
        end
      default:
          _07_ = 1'h0;
    endcase
  end
  always @* begin
      perm <= _01_;
  end
  assign \$9  = _18_;
  assign \$11  = _19_;
  assign \$13  = _20_;
  assign \$15  = _21_;
  assign \$1  = _22_;
  assign \$3  = _23_;
  assign \$5  = _24_;
  assign \$7  = _25_;
  assign ra[7:0] = perm[7:0];
  assign ra[63:8] = 56'h00000000000000;
  assign idx_7 = rs[63:56];
  assign idx_6 = rs[55:48];
  assign idx_5 = rs[47:40];
  assign idx_4 = rs[39:32];
  assign idx_3 = rs[31:24];
  assign idx_2 = rs[23:16];
  assign idx_1 = rs[15:8];
  assign idx_0 = rs[7:0];
  assign rb64_63 = rb[0];
  assign rb64_62 = rb[1];
  assign rb64_61 = rb[2];
  assign rb64_60 = rb[3];
  assign rb64_59 = rb[4];
  assign rb64_58 = rb[5];
  assign rb64_57 = rb[6];
  assign rb64_56 = rb[7];
  assign rb64_55 = rb[8];
  assign rb64_54 = rb[9];
  assign rb64_53 = rb[10];
  assign rb64_52 = rb[11];
  assign rb64_51 = rb[12];
  assign rb64_50 = rb[13];
  assign rb64_49 = rb[14];
  assign rb64_48 = rb[15];
  assign rb64_47 = rb[16];
  assign rb64_46 = rb[17];
  assign rb64_45 = rb[18];
  assign rb64_44 = rb[19];
  assign rb64_43 = rb[20];
  assign rb64_42 = rb[21];
  assign rb64_41 = rb[22];
  assign rb64_40 = rb[23];
  assign rb64_39 = rb[24];
  assign rb64_38 = rb[25];
  assign rb64_37 = rb[26];
  assign rb64_36 = rb[27];
  assign rb64_35 = rb[28];
  assign rb64_34 = rb[29];
  assign rb64_33 = rb[30];
  assign rb64_32 = rb[31];
  assign rb64_31 = rb[32];
  assign rb64_30 = rb[33];
  assign rb64_29 = rb[34];
  assign rb64_28 = rb[35];
  assign rb64_27 = rb[36];
  assign rb64_26 = rb[37];
  assign rb64_25 = rb[38];
  assign rb64_24 = rb[39];
  assign rb64_23 = rb[40];
  assign rb64_22 = rb[41];
  assign rb64_21 = rb[42];
  assign rb64_20 = rb[43];
  assign rb64_19 = rb[44];
  assign rb64_18 = rb[45];
  assign rb64_17 = rb[46];
  assign rb64_16 = rb[47];
  assign rb64_15 = rb[48];
  assign rb64_14 = rb[49];
  assign rb64_13 = rb[50];
  assign rb64_12 = rb[51];
  assign rb64_11 = rb[52];
  assign rb64_10 = rb[53];
  assign rb64_9 = rb[54];
  assign rb64_8 = rb[55];
  assign rb64_7 = rb[56];
  assign rb64_6 = rb[57];
  assign rb64_5 = rb[58];
  assign rb64_4 = rb[59];
  assign rb64_3 = rb[60];
  assign rb64_2 = rb[61];
  assign rb64_1 = rb[62];
  assign rb64_0 = rb[63];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:33528.1-34583.10" *)
module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src3_i, src1_i, src2_i, fast1_ok, cu_wr__rel_o, cu_wr__go_i, fast2_ok, dest1_o, dest2_o, nia_ok, dest3_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:34200.3-34201.25" *)
  reg _000_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:34160.3-34161.61" *)
  reg [63:0] _002_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [13:0] _003_;
  (* src = "libresoc.v:34164.3-34165.69" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:34168.3-34169.83" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _007_;
  (* src = "libresoc.v:34170.3-34171.79" *)
  reg _008_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [31:0] _009_;
  (* src = "libresoc.v:34166.3-34167.63" *)
  reg [31:0] _010_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [6:0] _011_;
  (* src = "libresoc.v:34162.3-34163.73" *)
  reg [6:0] _012_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _013_;
  (* src = "libresoc.v:34174.3-34175.71" *)
  reg _014_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _015_;
  (* src = "libresoc.v:34172.3-34173.59" *)
  reg _016_;
  (* src = "libresoc.v:34198.3-34199.43" *)
  reg _017_;
  (* src = "libresoc.v:34505.3-34513.6" *)
  reg _018_;
  (* src = "libresoc.v:34138.3-34139.39" *)
  reg _019_;
  (* src = "libresoc.v:34496.3-34504.6" *)
  reg _020_;
  (* src = "libresoc.v:34140.3-34141.43" *)
  reg _021_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg [63:0] _022_;
  (* src = "libresoc.v:34156.3-34157.45" *)
  reg [63:0] _023_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg _024_;
  (* src = "libresoc.v:34158.3-34159.51" *)
  reg _025_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg [63:0] _026_;
  (* src = "libresoc.v:34152.3-34153.45" *)
  reg [63:0] _027_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg _028_;
  (* src = "libresoc.v:34154.3-34155.51" *)
  reg _029_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg [63:0] _030_;
  (* src = "libresoc.v:34148.3-34149.41" *)
  reg [63:0] _031_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg _032_;
  (* src = "libresoc.v:34150.3-34151.47" *)
  reg _033_;
  (* src = "libresoc.v:34514.3-34523.6" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:34524.3-34533.6" *)
  reg [63:0] _035_;
  (* src = "libresoc.v:34534.3-34543.6" *)
  reg [63:0] _036_;
  (* src = "libresoc.v:33529.7-33529.20" *)
  reg _037_;
  (* src = "libresoc.v:34330.3-34338.6" *)
  reg _038_;
  (* src = "libresoc.v:34184.3-34185.39" *)
  reg _039_;
  (* src = "libresoc.v:34321.3-34329.6" *)
  reg _040_;
  (* src = "libresoc.v:34186.3-34187.39" *)
  reg _041_;
  (* src = "libresoc.v:34544.3-34552.6" *)
  reg [2:0] _042_;
  (* src = "libresoc.v:34196.3-34197.37" *)
  reg [2:0] _043_;
  (* src = "libresoc.v:34275.3-34284.6" *)
  reg _044_;
  (* src = "libresoc.v:34366.3-34374.6" *)
  reg [2:0] _045_;
  (* src = "libresoc.v:34176.3-34177.39" *)
  reg [2:0] _046_;
  (* src = "libresoc.v:34357.3-34365.6" *)
  reg [2:0] _047_;
  (* src = "libresoc.v:34178.3-34179.39" *)
  reg [2:0] _048_;
  (* src = "libresoc.v:34294.3-34302.6" *)
  reg _049_;
  (* src = "libresoc.v:34192.3-34193.41" *)
  reg _050_;
  (* src = "libresoc.v:34285.3-34293.6" *)
  reg _051_;
  (* src = "libresoc.v:34194.3-34195.41" *)
  reg _052_;
  (* src = "libresoc.v:34312.3-34320.6" *)
  reg _053_;
  (* src = "libresoc.v:34188.3-34189.39" *)
  reg _054_;
  (* src = "libresoc.v:34303.3-34311.6" *)
  reg _055_;
  (* src = "libresoc.v:34190.3-34191.39" *)
  reg _056_;
  (* src = "libresoc.v:34348.3-34356.6" *)
  reg [2:0] _057_;
  (* src = "libresoc.v:34180.3-34181.39" *)
  reg [2:0] _058_;
  (* src = "libresoc.v:34339.3-34347.6" *)
  reg [2:0] _059_;
  (* src = "libresoc.v:34182.3-34183.39" *)
  reg [2:0] _060_;
  (* src = "libresoc.v:34466.3-34475.6" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:34146.3-34147.29" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:34476.3-34485.6" *)
  reg [63:0] _063_;
  (* src = "libresoc.v:34144.3-34145.29" *)
  reg [63:0] _064_;
  (* src = "libresoc.v:34486.3-34495.6" *)
  reg [3:0] _065_;
  (* src = "libresoc.v:34142.3-34143.29" *)
  reg [3:0] _066_;
  (* src = "libresoc.v:33647.7-33647.24" *)
  reg _067_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [63:0] _068_;
  (* src = "libresoc.v:33655.14-33655.59" *)
  reg [63:0] _069_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [13:0] _070_;
  (* src = "libresoc.v:33674.14-33674.51" *)
  reg [13:0] _071_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [63:0] _072_;
  (* src = "libresoc.v:33678.14-33678.70" *)
  reg [63:0] _073_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _074_;
  (* src = "libresoc.v:33682.7-33682.45" *)
  reg _075_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [31:0] _076_;
  (* src = "libresoc.v:33686.14-33686.45" *)
  reg [31:0] _077_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [6:0] _078_;
  (* src = "libresoc.v:33765.13-33765.49" *)
  reg [6:0] _079_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _080_;
  (* src = "libresoc.v:33769.7-33769.41" *)
  reg _081_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _082_;
  (* src = "libresoc.v:33773.7-33773.35" *)
  reg _083_;
  (* src = "libresoc.v:33799.7-33799.26" *)
  reg _084_;
  (* src = "libresoc.v:34505.3-34513.6" *)
  reg _085_;
  (* src = "libresoc.v:33807.7-33807.25" *)
  reg _086_;
  (* src = "libresoc.v:34496.3-34504.6" *)
  reg _087_;
  (* src = "libresoc.v:33819.7-33819.27" *)
  reg _088_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg [63:0] _089_;
  (* src = "libresoc.v:33851.14-33851.51" *)
  reg [63:0] _090_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg _091_;
  (* src = "libresoc.v:33855.7-33855.31" *)
  reg _092_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg [63:0] _093_;
  (* src = "libresoc.v:33859.14-33859.51" *)
  reg [63:0] _094_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg _095_;
  (* src = "libresoc.v:33863.7-33863.31" *)
  reg _096_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg [63:0] _097_;
  (* src = "libresoc.v:33867.14-33867.49" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg _099_;
  (* src = "libresoc.v:33871.7-33871.29" *)
  reg _100_;
  (* src = "libresoc.v:34514.3-34523.6" *)
  reg [63:0] _101_;
  (* src = "libresoc.v:34524.3-34533.6" *)
  reg [63:0] _102_;
  (* src = "libresoc.v:34534.3-34543.6" *)
  reg [63:0] _103_;
  (* src = "libresoc.v:34330.3-34338.6" *)
  reg _104_;
  (* src = "libresoc.v:33892.7-33892.25" *)
  reg _105_;
  (* src = "libresoc.v:34321.3-34329.6" *)
  reg _106_;
  (* src = "libresoc.v:33896.7-33896.25" *)
  reg _107_;
  (* src = "libresoc.v:34544.3-34552.6" *)
  reg [2:0] _108_;
  (* src = "libresoc.v:34006.13-34006.30" *)
  reg [2:0] _109_;
  (* src = "libresoc.v:34275.3-34284.6" *)
  reg _110_;
  (* src = "libresoc.v:34366.3-34374.6" *)
  reg [2:0] _111_;
  (* src = "libresoc.v:34014.13-34014.31" *)
  reg [2:0] _112_;
  (* src = "libresoc.v:34357.3-34365.6" *)
  reg [2:0] _113_;
  (* src = "libresoc.v:34018.13-34018.31" *)
  reg [2:0] _114_;
  (* src = "libresoc.v:34294.3-34302.6" *)
  reg _115_;
  (* src = "libresoc.v:34030.7-34030.26" *)
  reg _116_;
  (* src = "libresoc.v:34285.3-34293.6" *)
  reg _117_;
  (* src = "libresoc.v:34034.7-34034.26" *)
  reg _118_;
  (* src = "libresoc.v:34312.3-34320.6" *)
  reg _119_;
  (* src = "libresoc.v:34038.7-34038.25" *)
  reg _120_;
  (* src = "libresoc.v:34303.3-34311.6" *)
  reg _121_;
  (* src = "libresoc.v:34042.7-34042.25" *)
  reg _122_;
  (* src = "libresoc.v:34348.3-34356.6" *)
  reg [2:0] _123_;
  (* src = "libresoc.v:34056.13-34056.31" *)
  reg [2:0] _124_;
  (* src = "libresoc.v:34339.3-34347.6" *)
  reg [2:0] _125_;
  (* src = "libresoc.v:34060.13-34060.31" *)
  reg [2:0] _126_;
  (* src = "libresoc.v:34466.3-34475.6" *)
  reg [63:0] _127_;
  (* src = "libresoc.v:34066.14-34066.43" *)
  reg [63:0] _128_;
  (* src = "libresoc.v:34476.3-34485.6" *)
  reg [63:0] _129_;
  (* src = "libresoc.v:34070.14-34070.43" *)
  reg [63:0] _130_;
  (* src = "libresoc.v:34486.3-34495.6" *)
  reg [3:0] _131_;
  (* src = "libresoc.v:34074.13-34074.26" *)
  reg [3:0] _132_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg [63:0] _133_;
  (* src = "libresoc.v:34375.3-34399.6" *)
  reg _134_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg [63:0] _135_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg _136_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg [63:0] _137_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg _138_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg [63:0] _139_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg _140_;
  (* src = "libresoc.v:34400.3-34421.6" *)
  reg _141_;
  (* src = "libresoc.v:34422.3-34443.6" *)
  reg _142_;
  (* src = "libresoc.v:34444.3-34465.6" *)
  reg _143_;
  (* src = "libresoc.v:34082.18-34082.112" *)
  wire [2:0] _144_;
  (* src = "libresoc.v:34083.19-34083.125" *)
  wire _145_;
  (* src = "libresoc.v:34084.19-34084.125" *)
  wire _146_;
  (* src = "libresoc.v:34085.19-34085.125" *)
  wire _147_;
  (* src = "libresoc.v:34086.19-34086.141" *)
  wire [2:0] _148_;
  (* src = "libresoc.v:34087.19-34087.121" *)
  wire [2:0] _149_;
  (* src = "libresoc.v:34088.19-34088.127" *)
  wire _150_;
  (* src = "libresoc.v:34089.19-34089.127" *)
  wire _151_;
  (* src = "libresoc.v:34090.19-34090.127" *)
  wire _152_;
  (* src = "libresoc.v:34091.18-34091.110" *)
  wire _153_;
  (* src = "libresoc.v:34093.18-34093.98" *)
  wire _154_;
  (* src = "libresoc.v:34095.18-34095.100" *)
  wire _155_;
  (* src = "libresoc.v:34096.18-34096.149" *)
  wire [2:0] _156_;
  (* src = "libresoc.v:34098.18-34098.119" *)
  wire [2:0] _157_;
  (* src = "libresoc.v:34101.18-34101.116" *)
  wire _158_;
  (* src = "libresoc.v:34105.17-34105.123" *)
  wire _159_;
  (* src = "libresoc.v:34107.18-34107.113" *)
  wire _160_;
  (* src = "libresoc.v:34108.18-34108.125" *)
  wire [2:0] _161_;
  (* src = "libresoc.v:34110.18-34110.112" *)
  wire _162_;
  (* src = "libresoc.v:34112.18-34112.129" *)
  wire _163_;
  (* src = "libresoc.v:34113.18-34113.129" *)
  wire _164_;
  (* src = "libresoc.v:34114.18-34114.117" *)
  wire _165_;
  (* src = "libresoc.v:34119.18-34119.133" *)
  wire _166_;
  (* src = "libresoc.v:34120.18-34120.124" *)
  wire [2:0] _167_;
  (* src = "libresoc.v:34123.18-34123.120" *)
  wire _168_;
  (* src = "libresoc.v:34124.18-34124.120" *)
  wire _169_;
  (* src = "libresoc.v:34125.18-34125.118" *)
  wire _170_;
  (* src = "libresoc.v:34131.18-34131.137" *)
  wire _171_;
  (* src = "libresoc.v:34133.18-34133.135" *)
  wire _172_;
  (* src = "libresoc.v:34134.18-34134.149" *)
  wire [2:0] _173_;
  (* src = "libresoc.v:34136.18-34136.129" *)
  wire [2:0] _174_;
  (* src = "libresoc.v:34109.18-34109.113" *)
  wire _175_;
  (* src = "libresoc.v:34111.18-34111.119" *)
  wire _176_;
  (* src = "libresoc.v:34092.18-34092.97" *)
  wire _177_;
  (* src = "libresoc.v:34094.18-34094.99" *)
  wire _178_;
  (* src = "libresoc.v:34097.18-34097.113" *)
  wire [2:0] _179_;
  (* src = "libresoc.v:34100.18-34100.106" *)
  wire _180_;
  (* src = "libresoc.v:34106.18-34106.123" *)
  wire _181_;
  (* src = "libresoc.v:34121.17-34121.113" *)
  wire [2:0] _182_;
  (* src = "libresoc.v:34135.18-34135.133" *)
  wire _183_;
  (* src = "libresoc.v:34137.18-34137.114" *)
  wire [2:0] _184_;
  (* src = "libresoc.v:34104.18-34104.112" *)
  wire _185_;
  (* src = "libresoc.v:34115.18-34115.122" *)
  wire _186_;
  (* src = "libresoc.v:34116.18-34116.124" *)
  wire _187_;
  (* src = "libresoc.v:34117.18-34117.155" *)
  wire [2:0] _188_;
  (* src = "libresoc.v:34118.18-34118.155" *)
  wire [2:0] _189_;
  (* src = "libresoc.v:34122.18-34122.120" *)
  wire [2:0] _190_;
  (* src = "libresoc.v:34132.17-34132.117" *)
  wire [2:0] _191_;
  (* src = "libresoc.v:34081.17-34081.104" *)
  wire _192_;
  (* src = "libresoc.v:34099.18-34099.106" *)
  wire _193_;
  (* src = "libresoc.v:34102.18-34102.113" *)
  wire _194_;
  (* src = "libresoc.v:34103.18-34103.112" *)
  wire _195_;
  (* src = "libresoc.v:34126.18-34126.162" *)
  wire _196_;
  (* src = "libresoc.v:34127.18-34127.176" *)
  wire [63:0] _197_;
  (* src = "libresoc.v:34128.18-34128.118" *)
  wire [63:0] _198_;
  (* src = "libresoc.v:34129.18-34129.115" *)
  wire [63:0] _199_;
  (* src = "libresoc.v:34130.18-34130.118" *)
  wire [3:0] _200_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [2:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [2:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [2:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [2:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [2:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [2:0] \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [3:0] \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_branch0_br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_branch0_br_op__cia$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_branch0_br_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_branch0_br_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_branch0_br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_branch0_br_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_branch0_br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_branch0_br_op__imm_data__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_branch0_br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_branch0_br_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_branch0_br_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_branch0_br_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_branch0_br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_branch0_br_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_branch0_br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_branch0_br_op__lk$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] alu_branch0_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_branch0_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_branch0_fast1$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_branch0_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_branch0_fast2$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_branch0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_branch0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_branch0_nia;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_branch0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_branch0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [2:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [2:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__fast1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r1__fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r1__fast2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__fast2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r2__nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r2__nia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__nia_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest2_o;
  reg [63:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest3_o;
  reg [63:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  (* src = "libresoc.v:33529.7-33529.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_branch0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_branch0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_branch0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_branch0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_branch0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [2:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [2:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  assign _144_ = \$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ;
  assign _145_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _146_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _147_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _148_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105  };
  assign _149_ = \$107  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _150_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _151_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _152_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _153_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ;
  assign _154_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ;
  assign _155_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ;
  assign _156_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _157_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ;
  assign _158_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _159_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _160_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ;
  assign _161_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _162_ = \$41  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ;
  assign _163_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_branch0_n_ready_i;
  assign _164_ = \$51  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_branch0_n_valid_o;
  assign _165_ = \$53  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _166_ = alu_branch0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _167_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _168_ = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _169_ = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _170_ = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _171_ = alu_branch0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _172_ = alu_branch0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _173_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _174_ = \$91  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$93 , 1'h1 };
  assign _175_ = \$43  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _176_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _177_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _178_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _179_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _180_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _181_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_branch0_n_ready_i;
  assign _182_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _183_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_branch0_br_op__imm_data__ok;
  assign _184_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _185_ = \$33  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ;
  assign _186_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _187_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _188_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _189_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _190_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _191_ = \$6  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _192_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ;
  assign _193_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ;
  assign _194_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _195_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _196_ = alu_branch0_br_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _197_ = alu_branch0_br_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_branch0_br_op__imm_data__data : src2_i;
  assign _198_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _199_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1;
  assign _200_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34202.15-34226.4" *)
  alu_branch0 alu_branch0 (
    .br_op__cia(alu_branch0_br_op__cia),
    .br_op__fn_unit(alu_branch0_br_op__fn_unit),
    .br_op__imm_data__data(alu_branch0_br_op__imm_data__data),
    .br_op__imm_data__ok(alu_branch0_br_op__imm_data__ok),
    .br_op__insn(alu_branch0_br_op__insn),
    .br_op__insn_type(alu_branch0_br_op__insn_type),
    .br_op__is_32bit(alu_branch0_br_op__is_32bit),
    .br_op__lk(alu_branch0_br_op__lk),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_branch0_cr_a),
    .fast1(alu_branch0_fast1),
    .\fast1$1 (\alu_branch0_fast1$1 ),
    .fast1_ok(fast1_ok),
    .fast2(alu_branch0_fast2),
    .\fast2$2 (\alu_branch0_fast2$2 ),
    .fast2_ok(fast2_ok),
    .n_ready_i(alu_branch0_n_ready_i),
    .n_valid_o(alu_branch0_n_valid_o),
    .nia(alu_branch0_nia),
    .nia_ok(nia_ok),
    .p_ready_o(alu_branch0_p_ready_o),
    .p_valid_i(alu_branch0_p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34227.14-34233.4" *)
  \alu_l$29  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34234.15-34240.4" *)
  \alui_l$28  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34241.14-34247.4" *)
  \opc_l$24  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34248.14-34254.4" *)
  \req_l$25  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34255.14-34261.4" *)
  \rok_l$27  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34262.14-34267.4" *)
  \rst_l$26  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:34268.14-34274.4" *)
  \src_l$23  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
      \initial  <= _037_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _067_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__cia <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__fn_unit <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__imm_data__data <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__imm_data__ok <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__insn <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__insn_type <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__is_32bit <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_branch0_br_op__lk <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__fast1 <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__fast1_ok <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r1__fast2 <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__fast2_ok <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r2__nia <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__nia_ok <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _126_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _126_;
  end
  always @* begin
    if (\initial ) begin end
    _128_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _128_;
  end
  always @* begin
    if (\initial ) begin end
    _130_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _130_;
  end
  always @* begin
    if (\initial ) begin end
    _132_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _132_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \data_r2__nia$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__nia <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \data_r2__nia_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__nia_ok <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \data_r1__fast2$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__fast2 <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \data_r1__fast2_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__fast2_ok <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \data_r0__fast1$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__fast1 <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \data_r0__fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__fast1_ok <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \alu_branch0_br_op__cia$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__cia <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \alu_branch0_br_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__insn_type <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \alu_branch0_br_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__fn_unit <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \alu_branch0_br_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__insn <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \alu_branch0_br_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__imm_data__data <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \alu_branch0_br_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__imm_data__ok <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \alu_branch0_br_op__lk$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__lk <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \alu_branch0_br_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_branch0_br_op__is_32bit <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = alu_branch0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$11 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _110_;
    (* src = "libresoc.v:34276.5-34276.29" *)
    casez (\initial )
      /* src = "libresoc.v:34276.9-34276.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _110_ = 1'h1;
        end
      default:
          _110_ = \$47 ;
    endcase
  end
  always @* begin
      req_done <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _117_;
    (* src = "libresoc.v:34286.5-34286.29" *)
    casez (\initial )
      /* src = "libresoc.v:34286.9-34286.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _117_ = 1'h0;
        end
      default:
          _117_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _115_;
    (* src = "libresoc.v:34295.5-34295.29" *)
    casez (\initial )
      /* src = "libresoc.v:34295.9-34295.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _115_ = 1'h1;
        end
      default:
          _115_ = \$65 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _121_;
    (* src = "libresoc.v:34304.5-34304.29" *)
    casez (\initial )
      /* src = "libresoc.v:34304.9-34304.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = 1'h0;
        end
      default:
          _121_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _119_;
    (* src = "libresoc.v:34313.5-34313.29" *)
    casez (\initial )
      /* src = "libresoc.v:34313.9-34313.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _119_ = 1'h1;
        end
      default:
          _119_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _106_;
    (* src = "libresoc.v:34322.5-34322.29" *)
    casez (\initial )
      /* src = "libresoc.v:34322.9-34322.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _106_ = 1'h0;
        end
      default:
          _106_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _104_;
    (* src = "libresoc.v:34331.5-34331.29" *)
    casez (\initial )
      /* src = "libresoc.v:34331.9-34331.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = 1'h1;
        end
      default:
          _104_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _125_;
    (* src = "libresoc.v:34340.5-34340.29" *)
    casez (\initial )
      /* src = "libresoc.v:34340.9-34340.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _125_ = 3'h0;
        end
      default:
          _125_ = { cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _123_;
    (* src = "libresoc.v:34349.5-34349.29" *)
    casez (\initial )
      /* src = "libresoc.v:34349.9-34349.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _123_ = 3'h7;
        end
      default:
          _123_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _113_;
    (* src = "libresoc.v:34358.5-34358.29" *)
    casez (\initial )
      /* src = "libresoc.v:34358.9-34358.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = 3'h0;
        end
      default:
          _113_ = \$67 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = _111_;
    (* src = "libresoc.v:34367.5-34367.29" *)
    casez (\initial )
      /* src = "libresoc.v:34367.9-34367.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _111_ = 3'h7;
        end
      default:
          _111_ = \$69 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _068_;
    _003_ = _070_;
    _009_ = _076_;
    _011_ = _078_;
    _013_ = _080_;
    _015_ = _082_;
    _005_ = _133_;
    _007_ = _134_;
    (* src = "libresoc.v:34376.5-34376.29" *)
    casez (\initial )
      /* src = "libresoc.v:34376.9-34376.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _080_, _082_, _074_, _072_, _076_, _070_, _078_, _068_ } = { oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__lk, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__insn, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__cia };
        end
      default:
        begin
          _068_ = alu_branch0_br_op__cia;
          _070_ = alu_branch0_br_op__fn_unit;
          _072_ = alu_branch0_br_op__imm_data__data;
          _074_ = alu_branch0_br_op__imm_data__ok;
          _076_ = alu_branch0_br_op__insn;
          _078_ = alu_branch0_br_op__insn_type;
          _080_ = alu_branch0_br_op__is_32bit;
          _082_ = alu_branch0_br_op__lk;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _133_ = 64'h0000000000000000;
          _134_ = 1'h0;
        end
      default:
        begin
          _133_ = _072_;
          _134_ = _074_;
        end
    endcase
  end
  always @* begin
      \alu_branch0_br_op__cia$next  <= _001_;
      \alu_branch0_br_op__fn_unit$next  <= _003_;
      \alu_branch0_br_op__imm_data__data$next  <= _005_;
      \alu_branch0_br_op__imm_data__ok$next  <= _007_;
      \alu_branch0_br_op__insn$next  <= _009_;
      \alu_branch0_br_op__insn_type$next  <= _011_;
      \alu_branch0_br_op__is_32bit$next  <= _013_;
      \alu_branch0_br_op__lk$next  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _135_;
    _024_ = _141_;
    (* src = "libresoc.v:34401.5-34401.29" *)
    casez (\initial )
      /* src = "libresoc.v:34401.9-34401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _091_, _089_ } = { fast1_ok, alu_branch0_fast1 };
        end
      default:
        begin
          _089_ = data_r0__fast1;
          _091_ = data_r0__fast1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _136_, _135_ } = 65'h00000000000000000;
        end
      default:
        begin
          _135_ = _089_;
          _136_ = _091_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 1'h0;
        end
      default:
          _141_ = _136_;
    endcase
  end
  always @* begin
      \data_r0__fast1$next  <= _022_;
      \data_r0__fast1_ok$next  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _137_;
    _028_ = _142_;
    (* src = "libresoc.v:34423.5-34423.29" *)
    casez (\initial )
      /* src = "libresoc.v:34423.9-34423.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _095_, _093_ } = { fast2_ok, alu_branch0_fast2 };
        end
      default:
        begin
          _093_ = data_r1__fast2;
          _095_ = data_r1__fast2_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _138_, _137_ } = 65'h00000000000000000;
        end
      default:
        begin
          _137_ = _093_;
          _138_ = _095_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _142_ = 1'h0;
        end
      default:
          _142_ = _138_;
    endcase
  end
  always @* begin
      \data_r1__fast2$next  <= _026_;
      \data_r1__fast2_ok$next  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _139_;
    _032_ = _143_;
    (* src = "libresoc.v:34445.5-34445.29" *)
    casez (\initial )
      /* src = "libresoc.v:34445.9-34445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _099_, _097_ } = { nia_ok, alu_branch0_nia };
        end
      default:
        begin
          _097_ = data_r2__nia;
          _099_ = data_r2__nia_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _140_, _139_ } = 65'h00000000000000000;
        end
      default:
        begin
          _139_ = _097_;
          _140_ = _099_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 1'h0;
        end
      default:
          _143_ = _140_;
    endcase
  end
  always @* begin
      \data_r2__nia$next  <= _030_;
      \data_r2__nia_ok$next  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _127_;
    (* src = "libresoc.v:34467.5-34467.29" *)
    casez (\initial )
      /* src = "libresoc.v:34467.9-34467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = src1_i;
        end
      default:
          _127_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = _129_;
    (* src = "libresoc.v:34477.5-34477.29" *)
    casez (\initial )
      /* src = "libresoc.v:34477.9-34477.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = src_or_imm;
        end
      default:
          _129_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _131_;
    (* src = "libresoc.v:34487.5-34487.29" *)
    casez (\initial )
      /* src = "libresoc.v:34487.9-34487.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = src3_i;
        end
      default:
          _131_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _087_;
    (* src = "libresoc.v:34497.5-34497.29" *)
    casez (\initial )
      /* src = "libresoc.v:34497.9-34497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = 1'h1;
        end
      default:
          _087_ = \$87 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _085_;
    (* src = "libresoc.v:34506.5-34506.29" *)
    casez (\initial )
      /* src = "libresoc.v:34506.9-34506.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _085_ = 1'h1;
        end
      default:
          _085_ = \$89 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _101_;
    (* src = "libresoc.v:34515.5-34515.29" *)
    casez (\initial )
      /* src = "libresoc.v:34515.9-34515.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$111 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = data_r0__fast1;
        end
      default:
          _101_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = _102_;
    (* src = "libresoc.v:34525.5-34525.29" *)
    casez (\initial )
      /* src = "libresoc.v:34525.9-34525.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _102_ = data_r1__fast2;
        end
      default:
          _102_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest2_o <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _103_;
    (* src = "libresoc.v:34535.5-34535.29" *)
    casez (\initial )
      /* src = "libresoc.v:34535.9-34535.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = data_r2__nia;
        end
      default:
          _103_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest3_o <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _108_;
    (* src = "libresoc.v:34545.5-34545.29" *)
    casez (\initial )
      /* src = "libresoc.v:34545.9-34545.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _108_ = 3'h0;
        end
      default:
          _108_ = \$21 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _042_;
  end
  assign \$5  = _192_;
  assign \$99  = _144_;
  assign \$101  = _145_;
  assign \$103  = _146_;
  assign \$105  = _147_;
  assign \$107  = _148_;
  assign \$109  = _149_;
  assign \$111  = _150_;
  assign \$113  = _151_;
  assign \$115  = _152_;
  assign \$11  = _153_;
  assign \$13  = _177_;
  assign \$15  = _154_;
  assign \$17  = _178_;
  assign \$19  = _155_;
  assign \$21  = _156_;
  assign \$25  = _179_;
  assign \$27  = _157_;
  assign \$24  = _193_;
  assign \$23  = _180_;
  assign \$31  = _158_;
  assign \$33  = _194_;
  assign \$35  = _195_;
  assign \$37  = _185_;
  assign \$3  = _159_;
  assign \$39  = _181_;
  assign \$41  = _160_;
  assign \$43  = _161_;
  assign \$45  = _175_;
  assign \$47  = _162_;
  assign \$49  = _176_;
  assign \$51  = _163_;
  assign \$53  = _164_;
  assign \$55  = _165_;
  assign \$57  = _186_;
  assign \$59  = _187_;
  assign \$61  = _188_;
  assign \$63  = _189_;
  assign \$65  = _166_;
  assign \$67  = _167_;
  assign \$6  = _182_;
  assign \$69  = _190_;
  assign \$71  = _168_;
  assign \$73  = _169_;
  assign \$75  = _170_;
  assign \$77  = _196_;
  assign \$79  = _197_;
  assign \$81  = _198_;
  assign \$83  = _199_;
  assign \$85  = _200_;
  assign \$87  = _171_;
  assign \$8  = _191_;
  assign \$89  = _172_;
  assign \$91  = _173_;
  assign \$93  = _183_;
  assign \$95  = _174_;
  assign \$97  = _184_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$109 ;
  assign cu_rd__rel_o = \$99 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_branch0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_branch0_p_valid_i = alui_l_q_alui;
  assign alu_branch0_cr_a = \$85 ;
  assign \alu_branch0_fast2$2  = \$83 ;
  assign \alu_branch0_fast1$1  = \$81 ;
  assign src_or_imm = \$79 ;
  assign src_sel = \$77 ;
  assign cu_wrmask_o = { \$75 , \$73 , \$71  };
  assign reset_r = \$63 ;
  assign reset_w = \$61 ;
  assign rst_r = \$59 ;
  assign reset = \$57 ;
  assign wr_any = \$37 ;
  assign cu_done_o = \$31 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$19 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_branch0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$15 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.busy_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:34587.1-34645.10" *)
module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:34588.7-34588.20" *)
  reg _00_;
  (* src = "libresoc.v:34633.3-34641.6" *)
  reg _01_;
  (* src = "libresoc.v:34631.3-34632.27" *)
  reg _02_;
  (* src = "libresoc.v:34633.3-34641.6" *)
  reg _03_;
  (* src = "libresoc.v:34612.7-34612.19" *)
  reg _04_;
  (* src = "libresoc.v:34623.17-34623.96" *)
  wire _05_;
  (* src = "libresoc.v:34628.17-34628.96" *)
  wire _06_;
  (* src = "libresoc.v:34625.18-34625.94" *)
  wire _07_;
  (* src = "libresoc.v:34627.17-34627.93" *)
  wire _08_;
  (* src = "libresoc.v:34630.17-34630.93" *)
  wire _09_;
  (* src = "libresoc.v:34624.18-34624.99" *)
  wire _10_;
  (* src = "libresoc.v:34626.18-34626.100" *)
  wire _11_;
  (* src = "libresoc.v:34629.17-34629.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:34588.7-34588.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_busy;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_busy;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_busy;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_busy;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_busy;
  assign _11_ = q_busy | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_busy;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:34634.5-34634.29" *)
    casez (\initial )
      /* src = "libresoc.v:34634.9-34634.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_busy = \$15 ;
  assign qn_busy = \$13 ;
  assign q_busy = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:34649.1-36257.10" *)
module clz(lz, sig_in);
  reg \initial  = 0;
  (* src = "libresoc.v:35124.3-35138.6" *)
  reg [1:0] _000_;
  (* src = "libresoc.v:35214.3-35228.6" *)
  reg [1:0] _001_;
  (* src = "libresoc.v:35229.3-35243.6" *)
  reg [1:0] _002_;
  (* src = "libresoc.v:35244.3-35258.6" *)
  reg [1:0] _003_;
  (* src = "libresoc.v:35259.3-35273.6" *)
  reg [1:0] _004_;
  (* src = "libresoc.v:35274.3-35288.6" *)
  reg [1:0] _005_;
  (* src = "libresoc.v:35304.3-35318.6" *)
  reg [1:0] _006_;
  (* src = "libresoc.v:35319.3-35333.6" *)
  reg [1:0] _007_;
  (* src = "libresoc.v:35334.3-35348.6" *)
  reg [1:0] _008_;
  (* src = "libresoc.v:35349.3-35363.6" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:35364.3-35378.6" *)
  reg [1:0] _010_;
  (* src = "libresoc.v:35289.3-35303.6" *)
  reg [1:0] _011_;
  (* src = "libresoc.v:35379.3-35393.6" *)
  reg [1:0] _012_;
  (* src = "libresoc.v:35394.3-35408.6" *)
  reg [1:0] _013_;
  (* src = "libresoc.v:35409.3-35423.6" *)
  reg [1:0] _014_;
  (* src = "libresoc.v:35424.3-35438.6" *)
  reg [1:0] _015_;
  (* src = "libresoc.v:35439.3-35453.6" *)
  reg [1:0] _016_;
  (* src = "libresoc.v:35469.3-35483.6" *)
  reg [1:0] _017_;
  (* src = "libresoc.v:35484.3-35498.6" *)
  reg [1:0] _018_;
  (* src = "libresoc.v:35499.3-35513.6" *)
  reg [1:0] _019_;
  (* src = "libresoc.v:35514.3-35528.6" *)
  reg [1:0] _020_;
  (* src = "libresoc.v:35529.3-35543.6" *)
  reg [1:0] _021_;
  (* src = "libresoc.v:35454.3-35468.6" *)
  reg [1:0] _022_;
  (* src = "libresoc.v:35544.3-35558.6" *)
  reg [1:0] _023_;
  (* src = "libresoc.v:35559.3-35573.6" *)
  reg [1:0] _024_;
  (* src = "libresoc.v:35694.3-35708.6" *)
  reg [1:0] _025_;
  (* src = "libresoc.v:36109.3-36123.6" *)
  reg [1:0] _026_;
  (* src = "libresoc.v:35139.3-35153.6" *)
  reg [1:0] _027_;
  (* src = "libresoc.v:35154.3-35168.6" *)
  reg [1:0] _028_;
  (* src = "libresoc.v:35169.3-35183.6" *)
  reg [1:0] _029_;
  (* src = "libresoc.v:35184.3-35198.6" *)
  reg [1:0] _030_;
  (* src = "libresoc.v:35199.3-35213.6" *)
  reg [1:0] _031_;
  (* src = "libresoc.v:35574.3-35593.6" *)
  reg [2:0] _032_;
  (* src = "libresoc.v:35674.3-35693.6" *)
  reg [2:0] _033_;
  (* src = "libresoc.v:35709.3-35728.6" *)
  reg [2:0] _034_;
  (* src = "libresoc.v:35729.3-35748.6" *)
  reg [2:0] _035_;
  (* src = "libresoc.v:35749.3-35768.6" *)
  reg [2:0] _036_;
  (* src = "libresoc.v:35769.3-35788.6" *)
  reg [2:0] _037_;
  (* src = "libresoc.v:35789.3-35808.6" *)
  reg [2:0] _038_;
  (* src = "libresoc.v:35809.3-35828.6" *)
  reg [2:0] _039_;
  (* src = "libresoc.v:35829.3-35848.6" *)
  reg [2:0] _040_;
  (* src = "libresoc.v:35849.3-35868.6" *)
  reg [2:0] _041_;
  (* src = "libresoc.v:35869.3-35888.6" *)
  reg [2:0] _042_;
  (* src = "libresoc.v:35594.3-35613.6" *)
  reg [2:0] _043_;
  (* src = "libresoc.v:35889.3-35908.6" *)
  reg [2:0] _044_;
  (* src = "libresoc.v:35614.3-35633.6" *)
  reg [2:0] _045_;
  (* src = "libresoc.v:35634.3-35653.6" *)
  reg [2:0] _046_;
  (* src = "libresoc.v:35654.3-35673.6" *)
  reg [2:0] _047_;
  (* src = "libresoc.v:35909.3-35928.6" *)
  reg [3:0] _048_;
  (* src = "libresoc.v:36009.3-36028.6" *)
  reg [3:0] _049_;
  (* src = "libresoc.v:36029.3-36048.6" *)
  reg [3:0] _050_;
  (* src = "libresoc.v:36049.3-36068.6" *)
  reg [3:0] _051_;
  (* src = "libresoc.v:35929.3-35948.6" *)
  reg [3:0] _052_;
  (* src = "libresoc.v:35949.3-35968.6" *)
  reg [3:0] _053_;
  (* src = "libresoc.v:35969.3-35988.6" *)
  reg [3:0] _054_;
  (* src = "libresoc.v:35989.3-36008.6" *)
  reg [3:0] _055_;
  (* src = "libresoc.v:36069.3-36088.6" *)
  reg [4:0] _056_;
  (* src = "libresoc.v:36089.3-36108.6" *)
  reg [4:0] _057_;
  (* src = "libresoc.v:36124.3-36143.6" *)
  reg [4:0] _058_;
  (* src = "libresoc.v:36144.3-36163.6" *)
  reg [4:0] _059_;
  (* src = "libresoc.v:36164.3-36183.6" *)
  reg [5:0] _060_;
  (* src = "libresoc.v:36184.3-36203.6" *)
  reg [5:0] _061_;
  (* src = "libresoc.v:36204.3-36223.6" *)
  reg [6:0] _062_;
  (* src = "libresoc.v:34650.7-34650.20" *)
  reg _063_;
  (* src = "libresoc.v:35124.3-35138.6" *)
  reg [1:0] _064_;
  (* src = "libresoc.v:35214.3-35228.6" *)
  reg [1:0] _065_;
  (* src = "libresoc.v:35229.3-35243.6" *)
  reg [1:0] _066_;
  (* src = "libresoc.v:35244.3-35258.6" *)
  reg [1:0] _067_;
  (* src = "libresoc.v:35259.3-35273.6" *)
  reg [1:0] _068_;
  (* src = "libresoc.v:35274.3-35288.6" *)
  reg [1:0] _069_;
  (* src = "libresoc.v:35304.3-35318.6" *)
  reg [1:0] _070_;
  (* src = "libresoc.v:35319.3-35333.6" *)
  reg [1:0] _071_;
  (* src = "libresoc.v:35334.3-35348.6" *)
  reg [1:0] _072_;
  (* src = "libresoc.v:35349.3-35363.6" *)
  reg [1:0] _073_;
  (* src = "libresoc.v:35364.3-35378.6" *)
  reg [1:0] _074_;
  (* src = "libresoc.v:35289.3-35303.6" *)
  reg [1:0] _075_;
  (* src = "libresoc.v:35379.3-35393.6" *)
  reg [1:0] _076_;
  (* src = "libresoc.v:35394.3-35408.6" *)
  reg [1:0] _077_;
  (* src = "libresoc.v:35409.3-35423.6" *)
  reg [1:0] _078_;
  (* src = "libresoc.v:35424.3-35438.6" *)
  reg [1:0] _079_;
  (* src = "libresoc.v:35439.3-35453.6" *)
  reg [1:0] _080_;
  (* src = "libresoc.v:35469.3-35483.6" *)
  reg [1:0] _081_;
  (* src = "libresoc.v:35484.3-35498.6" *)
  reg [1:0] _082_;
  (* src = "libresoc.v:35499.3-35513.6" *)
  reg [1:0] _083_;
  (* src = "libresoc.v:35514.3-35528.6" *)
  reg [1:0] _084_;
  (* src = "libresoc.v:35529.3-35543.6" *)
  reg [1:0] _085_;
  (* src = "libresoc.v:35454.3-35468.6" *)
  reg [1:0] _086_;
  (* src = "libresoc.v:35544.3-35558.6" *)
  reg [1:0] _087_;
  (* src = "libresoc.v:35559.3-35573.6" *)
  reg [1:0] _088_;
  (* src = "libresoc.v:35694.3-35708.6" *)
  reg [1:0] _089_;
  (* src = "libresoc.v:36109.3-36123.6" *)
  reg [1:0] _090_;
  (* src = "libresoc.v:35139.3-35153.6" *)
  reg [1:0] _091_;
  (* src = "libresoc.v:35154.3-35168.6" *)
  reg [1:0] _092_;
  (* src = "libresoc.v:35169.3-35183.6" *)
  reg [1:0] _093_;
  (* src = "libresoc.v:35184.3-35198.6" *)
  reg [1:0] _094_;
  (* src = "libresoc.v:35199.3-35213.6" *)
  reg [1:0] _095_;
  (* src = "libresoc.v:35574.3-35593.6" *)
  reg [2:0] _096_;
  (* src = "libresoc.v:35674.3-35693.6" *)
  reg [2:0] _097_;
  (* src = "libresoc.v:35709.3-35728.6" *)
  reg [2:0] _098_;
  (* src = "libresoc.v:35729.3-35748.6" *)
  reg [2:0] _099_;
  (* src = "libresoc.v:35749.3-35768.6" *)
  reg [2:0] _100_;
  (* src = "libresoc.v:35769.3-35788.6" *)
  reg [2:0] _101_;
  (* src = "libresoc.v:35789.3-35808.6" *)
  reg [2:0] _102_;
  (* src = "libresoc.v:35809.3-35828.6" *)
  reg [2:0] _103_;
  (* src = "libresoc.v:35829.3-35848.6" *)
  reg [2:0] _104_;
  (* src = "libresoc.v:35849.3-35868.6" *)
  reg [2:0] _105_;
  (* src = "libresoc.v:35869.3-35888.6" *)
  reg [2:0] _106_;
  (* src = "libresoc.v:35594.3-35613.6" *)
  reg [2:0] _107_;
  (* src = "libresoc.v:35889.3-35908.6" *)
  reg [2:0] _108_;
  (* src = "libresoc.v:35614.3-35633.6" *)
  reg [2:0] _109_;
  (* src = "libresoc.v:35634.3-35653.6" *)
  reg [2:0] _110_;
  (* src = "libresoc.v:35654.3-35673.6" *)
  reg [2:0] _111_;
  (* src = "libresoc.v:35909.3-35928.6" *)
  reg [3:0] _112_;
  (* src = "libresoc.v:36009.3-36028.6" *)
  reg [3:0] _113_;
  (* src = "libresoc.v:36029.3-36048.6" *)
  reg [3:0] _114_;
  (* src = "libresoc.v:36049.3-36068.6" *)
  reg [3:0] _115_;
  (* src = "libresoc.v:35929.3-35948.6" *)
  reg [3:0] _116_;
  (* src = "libresoc.v:35949.3-35968.6" *)
  reg [3:0] _117_;
  (* src = "libresoc.v:35969.3-35988.6" *)
  reg [3:0] _118_;
  (* src = "libresoc.v:35989.3-36008.6" *)
  reg [3:0] _119_;
  (* src = "libresoc.v:36069.3-36088.6" *)
  reg [4:0] _120_;
  (* src = "libresoc.v:36089.3-36108.6" *)
  reg [4:0] _121_;
  (* src = "libresoc.v:36124.3-36143.6" *)
  reg [4:0] _122_;
  (* src = "libresoc.v:36144.3-36163.6" *)
  reg [4:0] _123_;
  (* src = "libresoc.v:36164.3-36183.6" *)
  reg [5:0] _124_;
  (* src = "libresoc.v:36184.3-36203.6" *)
  reg [5:0] _125_;
  (* src = "libresoc.v:36204.3-36223.6" *)
  reg [6:0] _126_;
  (* src = "libresoc.v:35574.3-35593.6" *)
  reg [2:0] _127_;
  (* src = "libresoc.v:35674.3-35693.6" *)
  reg [2:0] _128_;
  (* src = "libresoc.v:35709.3-35728.6" *)
  reg [2:0] _129_;
  (* src = "libresoc.v:35729.3-35748.6" *)
  reg [2:0] _130_;
  (* src = "libresoc.v:35749.3-35768.6" *)
  reg [2:0] _131_;
  (* src = "libresoc.v:35769.3-35788.6" *)
  reg [2:0] _132_;
  (* src = "libresoc.v:35789.3-35808.6" *)
  reg [2:0] _133_;
  (* src = "libresoc.v:35809.3-35828.6" *)
  reg [2:0] _134_;
  (* src = "libresoc.v:35829.3-35848.6" *)
  reg [2:0] _135_;
  (* src = "libresoc.v:35849.3-35868.6" *)
  reg [2:0] _136_;
  (* src = "libresoc.v:35869.3-35888.6" *)
  reg [2:0] _137_;
  (* src = "libresoc.v:35594.3-35613.6" *)
  reg [2:0] _138_;
  (* src = "libresoc.v:35889.3-35908.6" *)
  reg [2:0] _139_;
  (* src = "libresoc.v:35614.3-35633.6" *)
  reg [2:0] _140_;
  (* src = "libresoc.v:35634.3-35653.6" *)
  reg [2:0] _141_;
  (* src = "libresoc.v:35654.3-35673.6" *)
  reg [2:0] _142_;
  (* src = "libresoc.v:35909.3-35928.6" *)
  reg [3:0] _143_;
  (* src = "libresoc.v:36009.3-36028.6" *)
  reg [3:0] _144_;
  (* src = "libresoc.v:36029.3-36048.6" *)
  reg [3:0] _145_;
  (* src = "libresoc.v:36049.3-36068.6" *)
  reg [3:0] _146_;
  (* src = "libresoc.v:35929.3-35948.6" *)
  reg [3:0] _147_;
  (* src = "libresoc.v:35949.3-35968.6" *)
  reg [3:0] _148_;
  (* src = "libresoc.v:35969.3-35988.6" *)
  reg [3:0] _149_;
  (* src = "libresoc.v:35989.3-36008.6" *)
  reg [3:0] _150_;
  (* src = "libresoc.v:36069.3-36088.6" *)
  reg [4:0] _151_;
  (* src = "libresoc.v:36089.3-36108.6" *)
  reg [4:0] _152_;
  (* src = "libresoc.v:36124.3-36143.6" *)
  reg [4:0] _153_;
  (* src = "libresoc.v:36144.3-36163.6" *)
  reg [4:0] _154_;
  (* src = "libresoc.v:36164.3-36183.6" *)
  reg [5:0] _155_;
  (* src = "libresoc.v:36184.3-36203.6" *)
  reg [5:0] _156_;
  (* src = "libresoc.v:36204.3-36223.6" *)
  reg [6:0] _157_;
  (* src = "libresoc.v:35031.17-35031.101" *)
  wire _158_;
  (* src = "libresoc.v:35032.18-35032.102" *)
  wire _159_;
  (* src = "libresoc.v:35034.19-35034.103" *)
  wire _160_;
  (* src = "libresoc.v:35035.19-35035.103" *)
  wire _161_;
  (* src = "libresoc.v:35037.19-35037.104" *)
  wire _162_;
  (* src = "libresoc.v:35038.19-35038.103" *)
  wire _163_;
  (* src = "libresoc.v:35040.19-35040.104" *)
  wire _164_;
  (* src = "libresoc.v:35041.19-35041.104" *)
  wire _165_;
  (* src = "libresoc.v:35044.19-35044.104" *)
  wire _166_;
  (* src = "libresoc.v:35045.19-35045.104" *)
  wire _167_;
  (* src = "libresoc.v:35047.19-35047.104" *)
  wire _168_;
  (* src = "libresoc.v:35048.19-35048.104" *)
  wire _169_;
  (* src = "libresoc.v:35050.19-35050.104" *)
  wire _170_;
  (* src = "libresoc.v:35051.19-35051.104" *)
  wire _171_;
  (* src = "libresoc.v:35053.18-35053.102" *)
  wire _172_;
  (* src = "libresoc.v:35054.19-35054.104" *)
  wire _173_;
  (* src = "libresoc.v:35055.19-35055.104" *)
  wire _174_;
  (* src = "libresoc.v:35057.19-35057.103" *)
  wire _175_;
  (* src = "libresoc.v:35058.19-35058.103" *)
  wire _176_;
  (* src = "libresoc.v:35060.19-35060.103" *)
  wire _177_;
  (* src = "libresoc.v:35061.19-35061.103" *)
  wire _178_;
  (* src = "libresoc.v:35063.19-35063.104" *)
  wire _179_;
  (* src = "libresoc.v:35064.18-35064.102" *)
  wire _180_;
  (* src = "libresoc.v:35065.19-35065.103" *)
  wire _181_;
  (* src = "libresoc.v:35067.19-35067.104" *)
  wire _182_;
  (* src = "libresoc.v:35068.19-35068.104" *)
  wire _183_;
  (* src = "libresoc.v:35070.19-35070.103" *)
  wire _184_;
  (* src = "libresoc.v:35071.19-35071.103" *)
  wire _185_;
  (* src = "libresoc.v:35073.19-35073.103" *)
  wire _186_;
  (* src = "libresoc.v:35074.19-35074.103" *)
  wire _187_;
  (* src = "libresoc.v:35077.19-35077.103" *)
  wire _188_;
  (* src = "libresoc.v:35078.19-35078.103" *)
  wire _189_;
  (* src = "libresoc.v:35080.17-35080.101" *)
  wire _190_;
  (* src = "libresoc.v:35081.18-35081.102" *)
  wire _191_;
  (* src = "libresoc.v:35082.18-35082.102" *)
  wire _192_;
  (* src = "libresoc.v:35084.18-35084.102" *)
  wire _193_;
  (* src = "libresoc.v:35085.18-35085.102" *)
  wire _194_;
  (* src = "libresoc.v:35087.18-35087.103" *)
  wire _195_;
  (* src = "libresoc.v:35088.18-35088.103" *)
  wire _196_;
  (* src = "libresoc.v:35090.18-35090.103" *)
  wire _197_;
  (* src = "libresoc.v:35091.17-35091.101" *)
  wire _198_;
  (* src = "libresoc.v:35092.18-35092.103" *)
  wire _199_;
  (* src = "libresoc.v:35094.18-35094.103" *)
  wire _200_;
  (* src = "libresoc.v:35095.18-35095.103" *)
  wire _201_;
  (* src = "libresoc.v:35097.18-35097.103" *)
  wire _202_;
  (* src = "libresoc.v:35098.18-35098.103" *)
  wire _203_;
  (* src = "libresoc.v:35100.18-35100.103" *)
  wire _204_;
  (* src = "libresoc.v:35101.18-35101.103" *)
  wire _205_;
  (* src = "libresoc.v:35104.18-35104.103" *)
  wire _206_;
  (* src = "libresoc.v:35105.18-35105.103" *)
  wire _207_;
  (* src = "libresoc.v:35107.18-35107.103" *)
  wire _208_;
  (* src = "libresoc.v:35108.18-35108.103" *)
  wire _209_;
  (* src = "libresoc.v:35110.18-35110.103" *)
  wire _210_;
  (* src = "libresoc.v:35111.18-35111.103" *)
  wire _211_;
  (* src = "libresoc.v:35113.17-35113.101" *)
  wire _212_;
  (* src = "libresoc.v:35114.18-35114.103" *)
  wire _213_;
  (* src = "libresoc.v:35115.18-35115.103" *)
  wire _214_;
  (* src = "libresoc.v:35117.18-35117.103" *)
  wire _215_;
  (* src = "libresoc.v:35118.18-35118.103" *)
  wire _216_;
  (* src = "libresoc.v:35120.18-35120.103" *)
  wire _217_;
  (* src = "libresoc.v:35121.18-35121.103" *)
  wire _218_;
  (* src = "libresoc.v:35123.18-35123.102" *)
  wire _219_;
  (* src = "libresoc.v:35033.19-35033.109" *)
  wire [3:0] _220_;
  (* src = "libresoc.v:35036.19-35036.109" *)
  wire [3:0] _221_;
  (* src = "libresoc.v:35039.19-35039.109" *)
  wire [3:0] _222_;
  (* src = "libresoc.v:35042.18-35042.106" *)
  wire [2:0] _223_;
  (* src = "libresoc.v:35043.19-35043.110" *)
  wire [3:0] _224_;
  (* src = "libresoc.v:35046.19-35046.110" *)
  wire [3:0] _225_;
  (* src = "libresoc.v:35049.19-35049.110" *)
  wire [3:0] _226_;
  (* src = "libresoc.v:35052.19-35052.110" *)
  wire [3:0] _227_;
  (* src = "libresoc.v:35056.19-35056.110" *)
  wire [3:0] _228_;
  (* src = "libresoc.v:35059.19-35059.109" *)
  wire [4:0] _229_;
  (* src = "libresoc.v:35062.19-35062.109" *)
  wire [4:0] _230_;
  (* src = "libresoc.v:35066.19-35066.109" *)
  wire [4:0] _231_;
  (* src = "libresoc.v:35069.19-35069.110" *)
  wire [4:0] _232_;
  (* src = "libresoc.v:35072.19-35072.109" *)
  wire [5:0] _233_;
  (* src = "libresoc.v:35075.18-35075.106" *)
  wire [2:0] _234_;
  (* src = "libresoc.v:35076.19-35076.109" *)
  wire [5:0] _235_;
  (* src = "libresoc.v:35079.19-35079.109" *)
  wire [6:0] _236_;
  (* src = "libresoc.v:35083.18-35083.106" *)
  wire [2:0] _237_;
  (* src = "libresoc.v:35086.18-35086.106" *)
  wire [2:0] _238_;
  (* src = "libresoc.v:35089.18-35089.107" *)
  wire [2:0] _239_;
  (* src = "libresoc.v:35093.18-35093.107" *)
  wire [2:0] _240_;
  (* src = "libresoc.v:35096.18-35096.107" *)
  wire [2:0] _241_;
  (* src = "libresoc.v:35099.18-35099.107" *)
  wire [2:0] _242_;
  (* src = "libresoc.v:35102.17-35102.105" *)
  wire [2:0] _243_;
  (* src = "libresoc.v:35103.18-35103.107" *)
  wire [2:0] _244_;
  (* src = "libresoc.v:35106.18-35106.107" *)
  wire [2:0] _245_;
  (* src = "libresoc.v:35109.18-35109.107" *)
  wire [2:0] _246_;
  (* src = "libresoc.v:35112.18-35112.107" *)
  wire [2:0] _247_;
  (* src = "libresoc.v:35116.18-35116.107" *)
  wire [2:0] _248_;
  (* src = "libresoc.v:35119.18-35119.107" *)
  wire [2:0] _249_;
  (* src = "libresoc.v:35122.18-35122.107" *)
  wire [2:0] _250_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$101 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$107 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$113 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$119 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$125 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$131 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$137 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$139 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$141 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [3:0] \$143 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$145 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$147 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [4:0] \$149 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$151 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$153 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [4:0] \$155 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$157 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$159 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [4:0] \$161 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$163 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$165 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [4:0] \$167 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$169 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$171 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [5:0] \$173 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$175 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$177 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [5:0] \$179 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$181 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$183 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [6:0] \$185 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$71 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$77 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$89 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *)
  wire [2:0] \$95 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_10;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_11;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_12;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_13;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_14;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_15;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_16;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_17;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_18;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_19;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_20;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_21;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_22;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_23;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_24;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_25;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_26;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_27;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_28;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_29;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_30;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_31;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_7;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:32" *)
  reg [1:0] cnt_1_9;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_10;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_12;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_14;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_16;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_18;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_20;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_22;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_24;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_26;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_28;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_30;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [2:0] cnt_2_8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_10;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_12;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_14;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [3:0] cnt_3_8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [4:0] cnt_4_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [4:0] cnt_4_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [4:0] cnt_4_4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [4:0] cnt_4_6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [5:0] cnt_5_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [5:0] cnt_5_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" *)
  reg [6:0] cnt_6_0;
  (* src = "libresoc.v:34650.7-34650.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *)
  output [6:0] lz;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair10;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair12;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair14;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair16;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair18;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair20;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair22;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair24;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair26;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair28;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair30;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair32;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair34;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair36;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair38;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair40;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair42;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair44;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair46;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair48;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair50;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair52;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair54;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair56;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair58;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair60;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair62;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" *)
  wire [1:0] pair8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" *)
  input [63:0] sig_in;
  assign _158_ = cnt_1_2[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _159_ = cnt_2_0[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _160_ = cnt_2_6[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _161_ = cnt_2_4[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _162_ = cnt_2_10[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _163_ = cnt_2_8[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _164_ = cnt_2_14[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _165_ = cnt_2_12[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _166_ = cnt_2_18[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _167_ = cnt_2_16[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _168_ = cnt_2_22[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _169_ = cnt_2_20[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _170_ = cnt_2_26[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _171_ = cnt_2_24[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _172_ = cnt_1_5[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _173_ = cnt_2_30[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _174_ = cnt_2_28[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _175_ = cnt_3_2[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _176_ = cnt_3_0[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _177_ = cnt_3_6[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _178_ = cnt_3_4[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _179_ = cnt_3_10[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _180_ = cnt_1_4[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _181_ = cnt_3_8[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _182_ = cnt_3_14[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _183_ = cnt_3_12[3] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _184_ = cnt_4_2[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _185_ = cnt_4_0[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _186_ = cnt_4_6[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _187_ = cnt_4_4[4] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _188_ = cnt_5_2[5] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _189_ = cnt_5_0[5] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _190_ = cnt_1_1[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _191_ = cnt_1_7[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _192_ = cnt_1_6[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _193_ = cnt_1_9[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _194_ = cnt_1_8[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _195_ = cnt_1_11[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _196_ = cnt_1_10[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _197_ = cnt_1_13[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _198_ = cnt_1_0[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _199_ = cnt_1_12[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _200_ = cnt_1_15[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _201_ = cnt_1_14[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _202_ = cnt_1_17[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _203_ = cnt_1_16[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _204_ = cnt_1_19[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _205_ = cnt_1_18[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _206_ = cnt_1_21[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _207_ = cnt_1_20[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _208_ = cnt_1_23[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _209_ = cnt_1_22[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _210_ = cnt_1_25[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _211_ = cnt_1_24[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _212_ = cnt_1_3[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _213_ = cnt_1_27[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _214_ = cnt_1_26[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _215_ = cnt_1_29[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _216_ = cnt_1_28[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _217_ = cnt_1_31[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _218_ = cnt_1_30[1] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *) 1'h1;
  assign _219_ = cnt_2_2[2] == (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *) 1'h1;
  assign _220_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_0[1:0] };
  assign _221_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_4[1:0] };
  assign _222_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_8[1:0] };
  assign _223_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_2[0] };
  assign _224_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_12[1:0] };
  assign _225_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_16[1:0] };
  assign _226_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_20[1:0] };
  assign _227_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_24[1:0] };
  assign _228_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_2_28[1:0] };
  assign _229_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_3_0[2:0] };
  assign _230_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_3_4[2:0] };
  assign _231_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_3_8[2:0] };
  assign _232_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_3_12[2:0] };
  assign _233_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_4_0[3:0] };
  assign _234_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_4[0] };
  assign _235_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_4_4[3:0] };
  assign _236_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_5_0[4:0] };
  assign _237_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_6[0] };
  assign _238_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_8[0] };
  assign _239_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_10[0] };
  assign _240_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_12[0] };
  assign _241_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_14[0] };
  assign _242_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_16[0] };
  assign _243_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_0[0] };
  assign _244_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_18[0] };
  assign _245_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_20[0] };
  assign _246_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_22[0] };
  assign _247_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_24[0] };
  assign _248_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_26[0] };
  assign _249_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_28[0] };
  assign _250_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" *) { 2'h1, cnt_1_30[0] };
  always @* begin
    if (\initial ) begin end
    _063_ = 1'h0;
  end
  always @* begin
      \initial  <= _063_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _064_;
    (* src = "libresoc.v:35125.5-35125.29" *)
    casez (\initial )
      /* src = "libresoc.v:35125.9-35125.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair0)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _064_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _064_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _064_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_0 <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _091_;
    (* src = "libresoc.v:35140.5-35140.29" *)
    casez (\initial )
      /* src = "libresoc.v:35140.9-35140.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair10)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _091_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _091_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _091_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_5 <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _092_;
    (* src = "libresoc.v:35155.5-35155.29" *)
    casez (\initial )
      /* src = "libresoc.v:35155.9-35155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair12)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _092_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _092_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _092_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_6 <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = _093_;
    (* src = "libresoc.v:35170.5-35170.29" *)
    casez (\initial )
      /* src = "libresoc.v:35170.9-35170.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair14)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _093_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _093_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _093_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_7 <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _094_;
    (* src = "libresoc.v:35185.5-35185.29" *)
    casez (\initial )
      /* src = "libresoc.v:35185.9-35185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair16)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _094_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _094_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _094_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_8 <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = _095_;
    (* src = "libresoc.v:35200.5-35200.29" *)
    casez (\initial )
      /* src = "libresoc.v:35200.9-35200.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair18)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _095_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _095_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _095_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_9 <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _065_;
    (* src = "libresoc.v:35215.5-35215.29" *)
    casez (\initial )
      /* src = "libresoc.v:35215.9-35215.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair20)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _065_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _065_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _065_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_10 <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _066_;
    (* src = "libresoc.v:35230.5-35230.29" *)
    casez (\initial )
      /* src = "libresoc.v:35230.9-35230.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair22)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _066_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _066_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_11 <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _067_;
    (* src = "libresoc.v:35245.5-35245.29" *)
    casez (\initial )
      /* src = "libresoc.v:35245.9-35245.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair24)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _067_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _067_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _067_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_12 <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _068_;
    (* src = "libresoc.v:35260.5-35260.29" *)
    casez (\initial )
      /* src = "libresoc.v:35260.9-35260.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair26)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _068_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _068_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _068_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_13 <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _069_;
    (* src = "libresoc.v:35275.5-35275.29" *)
    casez (\initial )
      /* src = "libresoc.v:35275.9-35275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair28)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _069_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _069_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _069_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_14 <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _075_;
    (* src = "libresoc.v:35290.5-35290.29" *)
    casez (\initial )
      /* src = "libresoc.v:35290.9-35290.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair2)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _075_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _075_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _075_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_1 <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _070_;
    (* src = "libresoc.v:35305.5-35305.29" *)
    casez (\initial )
      /* src = "libresoc.v:35305.9-35305.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair30)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _070_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _070_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _070_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_15 <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _071_;
    (* src = "libresoc.v:35320.5-35320.29" *)
    casez (\initial )
      /* src = "libresoc.v:35320.9-35320.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair32)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _071_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _071_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _071_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_16 <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _072_;
    (* src = "libresoc.v:35335.5-35335.29" *)
    casez (\initial )
      /* src = "libresoc.v:35335.9-35335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair34)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _072_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _072_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _072_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_17 <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _073_;
    (* src = "libresoc.v:35350.5-35350.29" *)
    casez (\initial )
      /* src = "libresoc.v:35350.9-35350.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair36)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _073_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _073_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _073_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_18 <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _074_;
    (* src = "libresoc.v:35365.5-35365.29" *)
    casez (\initial )
      /* src = "libresoc.v:35365.9-35365.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair38)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _074_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _074_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _074_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_19 <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _076_;
    (* src = "libresoc.v:35380.5-35380.29" *)
    casez (\initial )
      /* src = "libresoc.v:35380.9-35380.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair40)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _076_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _076_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _076_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_20 <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _077_;
    (* src = "libresoc.v:35395.5-35395.29" *)
    casez (\initial )
      /* src = "libresoc.v:35395.9-35395.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair42)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _077_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _077_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _077_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_21 <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _078_;
    (* src = "libresoc.v:35410.5-35410.29" *)
    casez (\initial )
      /* src = "libresoc.v:35410.9-35410.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair44)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _078_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _078_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _078_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_22 <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _079_;
    (* src = "libresoc.v:35425.5-35425.29" *)
    casez (\initial )
      /* src = "libresoc.v:35425.9-35425.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair46)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _079_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _079_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _079_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_23 <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _080_;
    (* src = "libresoc.v:35440.5-35440.29" *)
    casez (\initial )
      /* src = "libresoc.v:35440.9-35440.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair48)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _080_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _080_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _080_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_24 <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _086_;
    (* src = "libresoc.v:35455.5-35455.29" *)
    casez (\initial )
      /* src = "libresoc.v:35455.9-35455.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair4)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _086_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _086_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _086_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_2 <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _081_;
    (* src = "libresoc.v:35470.5-35470.29" *)
    casez (\initial )
      /* src = "libresoc.v:35470.9-35470.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair50)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _081_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _081_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _081_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_25 <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _082_;
    (* src = "libresoc.v:35485.5-35485.29" *)
    casez (\initial )
      /* src = "libresoc.v:35485.9-35485.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair52)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _082_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _082_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _082_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_26 <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _083_;
    (* src = "libresoc.v:35500.5-35500.29" *)
    casez (\initial )
      /* src = "libresoc.v:35500.9-35500.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair54)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _083_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _083_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _083_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_27 <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _084_;
    (* src = "libresoc.v:35515.5-35515.29" *)
    casez (\initial )
      /* src = "libresoc.v:35515.9-35515.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair56)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _084_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _084_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _084_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_28 <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _085_;
    (* src = "libresoc.v:35530.5-35530.29" *)
    casez (\initial )
      /* src = "libresoc.v:35530.9-35530.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair58)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _085_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _085_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _085_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_29 <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = _087_;
    (* src = "libresoc.v:35545.5-35545.29" *)
    casez (\initial )
      /* src = "libresoc.v:35545.9-35545.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair60)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _087_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _087_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _087_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_30 <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _088_;
    (* src = "libresoc.v:35560.5-35560.29" *)
    casez (\initial )
      /* src = "libresoc.v:35560.9-35560.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair62)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _088_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _088_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _088_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_31 <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _096_;
    (* src = "libresoc.v:35575.5-35575.29" *)
    casez (\initial )
      /* src = "libresoc.v:35575.9-35575.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _096_ = _127_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _127_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _127_ = \$5 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _096_ = { 1'h0, cnt_1_1 };
        end
    endcase
  end
  always @* begin
      cnt_2_0 <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _107_;
    (* src = "libresoc.v:35595.5-35595.29" *)
    casez (\initial )
      /* src = "libresoc.v:35595.9-35595.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$7 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _107_ = _138_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _138_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _138_ = \$11 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _107_ = { 1'h0, cnt_1_3 };
        end
    endcase
  end
  always @* begin
      cnt_2_2 <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = _109_;
    (* src = "libresoc.v:35615.5-35615.29" *)
    casez (\initial )
      /* src = "libresoc.v:35615.9-35615.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _109_ = _140_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$15 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _140_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _140_ = \$17 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _109_ = { 1'h0, cnt_1_5 };
        end
    endcase
  end
  always @* begin
      cnt_2_4 <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _110_;
    (* src = "libresoc.v:35635.5-35635.29" *)
    casez (\initial )
      /* src = "libresoc.v:35635.9-35635.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$19 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _110_ = _141_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$21 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _141_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _141_ = \$23 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _110_ = { 1'h0, cnt_1_7 };
        end
    endcase
  end
  always @* begin
      cnt_2_6 <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _111_;
    (* src = "libresoc.v:35655.5-35655.29" *)
    casez (\initial )
      /* src = "libresoc.v:35655.9-35655.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$25 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _111_ = _142_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$27 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _142_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _142_ = \$29 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _111_ = { 1'h0, cnt_1_9 };
        end
    endcase
  end
  always @* begin
      cnt_2_8 <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = _097_;
    (* src = "libresoc.v:35675.5-35675.29" *)
    casez (\initial )
      /* src = "libresoc.v:35675.9-35675.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$31 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = _128_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$33 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _128_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _128_ = \$35 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _097_ = { 1'h0, cnt_1_11 };
        end
    endcase
  end
  always @* begin
      cnt_2_10 <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _089_;
    (* src = "libresoc.v:35695.5-35695.29" *)
    casez (\initial )
      /* src = "libresoc.v:35695.9-35695.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair6)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _089_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _089_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _089_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_3 <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _098_;
    (* src = "libresoc.v:35710.5-35710.29" *)
    casez (\initial )
      /* src = "libresoc.v:35710.9-35710.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$37 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _098_ = _129_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$39 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _129_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _129_ = \$41 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _098_ = { 1'h0, cnt_1_13 };
        end
    endcase
  end
  always @* begin
      cnt_2_12 <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = _099_;
    (* src = "libresoc.v:35730.5-35730.29" *)
    casez (\initial )
      /* src = "libresoc.v:35730.9-35730.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$43 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _099_ = _130_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$45 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _130_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _130_ = \$47 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _099_ = { 1'h0, cnt_1_15 };
        end
    endcase
  end
  always @* begin
      cnt_2_14 <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _100_;
    (* src = "libresoc.v:35750.5-35750.29" *)
    casez (\initial )
      /* src = "libresoc.v:35750.9-35750.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _100_ = _131_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$51 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _131_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _131_ = \$53 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _100_ = { 1'h0, cnt_1_17 };
        end
    endcase
  end
  always @* begin
      cnt_2_16 <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = _101_;
    (* src = "libresoc.v:35770.5-35770.29" *)
    casez (\initial )
      /* src = "libresoc.v:35770.9-35770.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = _132_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$57 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _132_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _132_ = \$59 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _101_ = { 1'h0, cnt_1_19 };
        end
    endcase
  end
  always @* begin
      cnt_2_18 <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _102_;
    (* src = "libresoc.v:35790.5-35790.29" *)
    casez (\initial )
      /* src = "libresoc.v:35790.9-35790.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$61 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _102_ = _133_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$63 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _133_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _133_ = \$65 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _102_ = { 1'h0, cnt_1_21 };
        end
    endcase
  end
  always @* begin
      cnt_2_20 <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = _103_;
    (* src = "libresoc.v:35810.5-35810.29" *)
    casez (\initial )
      /* src = "libresoc.v:35810.9-35810.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$67 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = _134_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$69 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _134_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _134_ = \$71 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _103_ = { 1'h0, cnt_1_23 };
        end
    endcase
  end
  always @* begin
      cnt_2_22 <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _104_;
    (* src = "libresoc.v:35830.5-35830.29" *)
    casez (\initial )
      /* src = "libresoc.v:35830.9-35830.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$73 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = _135_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$75 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _135_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _135_ = \$77 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _104_ = { 1'h0, cnt_1_25 };
        end
    endcase
  end
  always @* begin
      cnt_2_24 <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _105_;
    (* src = "libresoc.v:35850.5-35850.29" *)
    casez (\initial )
      /* src = "libresoc.v:35850.9-35850.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$79 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = _136_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$81 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _136_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _136_ = \$83 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _105_ = { 1'h0, cnt_1_27 };
        end
    endcase
  end
  always @* begin
      cnt_2_26 <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _106_;
    (* src = "libresoc.v:35870.5-35870.29" *)
    casez (\initial )
      /* src = "libresoc.v:35870.9-35870.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$85 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _106_ = _137_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$87 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _137_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _137_ = \$89 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _106_ = { 1'h0, cnt_1_29 };
        end
    endcase
  end
  always @* begin
      cnt_2_28 <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _108_;
    (* src = "libresoc.v:35890.5-35890.29" *)
    casez (\initial )
      /* src = "libresoc.v:35890.9-35890.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$91 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _108_ = _139_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$93 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _139_ = 3'h4;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _139_ = \$95 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _108_ = { 1'h0, cnt_1_31 };
        end
    endcase
  end
  always @* begin
      cnt_2_30 <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = _112_;
    (* src = "libresoc.v:35910.5-35910.29" *)
    casez (\initial )
      /* src = "libresoc.v:35910.9-35910.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$97 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _112_ = _143_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$99 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _143_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _143_ = \$101 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _112_ = { 1'h0, cnt_2_2 };
        end
    endcase
  end
  always @* begin
      cnt_3_0 <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = _116_;
    (* src = "libresoc.v:35930.5-35930.29" *)
    casez (\initial )
      /* src = "libresoc.v:35930.9-35930.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$103 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _116_ = _147_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$105 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _147_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _147_ = \$107 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _116_ = { 1'h0, cnt_2_6 };
        end
    endcase
  end
  always @* begin
      cnt_3_2 <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _117_;
    (* src = "libresoc.v:35950.5-35950.29" *)
    casez (\initial )
      /* src = "libresoc.v:35950.9-35950.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$109 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _117_ = _148_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$111 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _148_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _148_ = \$113 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _117_ = { 1'h0, cnt_2_10 };
        end
    endcase
  end
  always @* begin
      cnt_3_4 <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _118_;
    (* src = "libresoc.v:35970.5-35970.29" *)
    casez (\initial )
      /* src = "libresoc.v:35970.9-35970.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _118_ = _149_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$117 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _149_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _149_ = \$119 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _118_ = { 1'h0, cnt_2_14 };
        end
    endcase
  end
  always @* begin
      cnt_3_6 <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _119_;
    (* src = "libresoc.v:35990.5-35990.29" *)
    casez (\initial )
      /* src = "libresoc.v:35990.9-35990.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$121 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _119_ = _150_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$123 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _150_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _150_ = \$125 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _119_ = { 1'h0, cnt_2_18 };
        end
    endcase
  end
  always @* begin
      cnt_3_8 <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _113_;
    (* src = "libresoc.v:36010.5-36010.29" *)
    casez (\initial )
      /* src = "libresoc.v:36010.9-36010.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$127 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = _144_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$129 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _144_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _144_ = \$131 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _113_ = { 1'h0, cnt_2_22 };
        end
    endcase
  end
  always @* begin
      cnt_3_10 <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _114_;
    (* src = "libresoc.v:36030.5-36030.29" *)
    casez (\initial )
      /* src = "libresoc.v:36030.9-36030.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$133 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _114_ = _145_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$135 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _145_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _145_ = \$137 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _114_ = { 1'h0, cnt_2_26 };
        end
    endcase
  end
  always @* begin
      cnt_3_12 <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _115_;
    (* src = "libresoc.v:36050.5-36050.29" *)
    casez (\initial )
      /* src = "libresoc.v:36050.9-36050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$139 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _115_ = _146_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$141 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _146_ = 4'h8;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _146_ = \$143 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _115_ = { 1'h0, cnt_2_30 };
        end
    endcase
  end
  always @* begin
      cnt_3_14 <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _120_;
    (* src = "libresoc.v:36070.5-36070.29" *)
    casez (\initial )
      /* src = "libresoc.v:36070.9-36070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$145 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _120_ = _151_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$147 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _151_ = 5'h10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _151_ = \$149 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _120_ = { 1'h0, cnt_3_2 };
        end
    endcase
  end
  always @* begin
      cnt_4_0 <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _121_;
    (* src = "libresoc.v:36090.5-36090.29" *)
    casez (\initial )
      /* src = "libresoc.v:36090.9-36090.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$151 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = _152_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$153 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _152_ = 5'h10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _152_ = \$155 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _121_ = { 1'h0, cnt_3_6 };
        end
    endcase
  end
  always @* begin
      cnt_4_2 <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _090_;
    (* src = "libresoc.v:36110.5-36110.29" *)
    casez (\initial )
      /* src = "libresoc.v:36110.9-36110.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" *)
    casez (pair8)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _090_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _090_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _090_ = 2'h0;
        end
    endcase
  end
  always @* begin
      cnt_1_4 <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _122_;
    (* src = "libresoc.v:36125.5-36125.29" *)
    casez (\initial )
      /* src = "libresoc.v:36125.9-36125.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$157 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _122_ = _153_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$159 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _153_ = 5'h10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _153_ = \$161 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _122_ = { 1'h0, cnt_3_10 };
        end
    endcase
  end
  always @* begin
      cnt_4_4 <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _123_;
    (* src = "libresoc.v:36145.5-36145.29" *)
    casez (\initial )
      /* src = "libresoc.v:36145.9-36145.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$163 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _123_ = _154_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$165 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _154_ = 5'h10;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _154_ = \$167 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _123_ = { 1'h0, cnt_3_14 };
        end
    endcase
  end
  always @* begin
      cnt_4_6 <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _124_;
    (* src = "libresoc.v:36165.5-36165.29" *)
    casez (\initial )
      /* src = "libresoc.v:36165.9-36165.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$169 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _124_ = _155_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$171 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _155_ = 6'h20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _155_ = \$173 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _124_ = { 1'h0, cnt_4_2 };
        end
    endcase
  end
  always @* begin
      cnt_5_0 <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _125_;
    (* src = "libresoc.v:36185.5-36185.29" *)
    casez (\initial )
      /* src = "libresoc.v:36185.9-36185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$175 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _125_ = _156_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$177 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _156_ = 6'h20;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _156_ = \$179 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _125_ = { 1'h0, cnt_4_6 };
        end
    endcase
  end
  always @* begin
      cnt_5_2 <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _126_;
    (* src = "libresoc.v:36205.5-36205.29" *)
    casez (\initial )
      /* src = "libresoc.v:36205.9-36205.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" *)
    casez (\$181 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = _157_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" *)
          casez (\$183 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _157_ = 7'h40;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _157_ = \$185 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _126_ = { 1'h0, cnt_5_2 };
        end
    endcase
  end
  always @* begin
      cnt_6_0 <= _062_;
  end
  assign \$9  = _158_;
  assign \$99  = _159_;
  assign \$101  = _220_;
  assign \$103  = _160_;
  assign \$105  = _161_;
  assign \$107  = _221_;
  assign \$109  = _162_;
  assign \$111  = _163_;
  assign \$113  = _222_;
  assign \$115  = _164_;
  assign \$117  = _165_;
  assign \$11  = _223_;
  assign \$119  = _224_;
  assign \$121  = _166_;
  assign \$123  = _167_;
  assign \$125  = _225_;
  assign \$127  = _168_;
  assign \$129  = _169_;
  assign \$131  = _226_;
  assign \$133  = _170_;
  assign \$135  = _171_;
  assign \$137  = _227_;
  assign \$13  = _172_;
  assign \$139  = _173_;
  assign \$141  = _174_;
  assign \$143  = _228_;
  assign \$145  = _175_;
  assign \$147  = _176_;
  assign \$149  = _229_;
  assign \$151  = _177_;
  assign \$153  = _178_;
  assign \$155  = _230_;
  assign \$157  = _179_;
  assign \$15  = _180_;
  assign \$159  = _181_;
  assign \$161  = _231_;
  assign \$163  = _182_;
  assign \$165  = _183_;
  assign \$167  = _232_;
  assign \$169  = _184_;
  assign \$171  = _185_;
  assign \$173  = _233_;
  assign \$175  = _186_;
  assign \$177  = _187_;
  assign \$17  = _234_;
  assign \$179  = _235_;
  assign \$181  = _188_;
  assign \$183  = _189_;
  assign \$185  = _236_;
  assign \$1  = _190_;
  assign \$19  = _191_;
  assign \$21  = _192_;
  assign \$23  = _237_;
  assign \$25  = _193_;
  assign \$27  = _194_;
  assign \$29  = _238_;
  assign \$31  = _195_;
  assign \$33  = _196_;
  assign \$35  = _239_;
  assign \$37  = _197_;
  assign \$3  = _198_;
  assign \$39  = _199_;
  assign \$41  = _240_;
  assign \$43  = _200_;
  assign \$45  = _201_;
  assign \$47  = _241_;
  assign \$49  = _202_;
  assign \$51  = _203_;
  assign \$53  = _242_;
  assign \$55  = _204_;
  assign \$57  = _205_;
  assign \$5  = _243_;
  assign \$59  = _244_;
  assign \$61  = _206_;
  assign \$63  = _207_;
  assign \$65  = _245_;
  assign \$67  = _208_;
  assign \$69  = _209_;
  assign \$71  = _246_;
  assign \$73  = _210_;
  assign \$75  = _211_;
  assign \$77  = _247_;
  assign \$7  = _212_;
  assign \$79  = _213_;
  assign \$81  = _214_;
  assign \$83  = _248_;
  assign \$85  = _215_;
  assign \$87  = _216_;
  assign \$89  = _249_;
  assign \$91  = _217_;
  assign \$93  = _218_;
  assign \$95  = _250_;
  assign \$97  = _219_;
  assign lz = cnt_6_0;
  assign pair62 = sig_in[63:62];
  assign pair60 = sig_in[61:60];
  assign pair58 = sig_in[59:58];
  assign pair56 = sig_in[57:56];
  assign pair54 = sig_in[55:54];
  assign pair52 = sig_in[53:52];
  assign pair50 = sig_in[51:50];
  assign pair48 = sig_in[49:48];
  assign pair46 = sig_in[47:46];
  assign pair44 = sig_in[45:44];
  assign pair42 = sig_in[43:42];
  assign pair40 = sig_in[41:40];
  assign pair38 = sig_in[39:38];
  assign pair36 = sig_in[37:36];
  assign pair34 = sig_in[35:34];
  assign pair32 = sig_in[33:32];
  assign pair30 = sig_in[31:30];
  assign pair28 = sig_in[29:28];
  assign pair26 = sig_in[27:26];
  assign pair24 = sig_in[25:24];
  assign pair22 = sig_in[23:22];
  assign pair20 = sig_in[21:20];
  assign pair18 = sig_in[19:18];
  assign pair16 = sig_in[17:16];
  assign pair14 = sig_in[15:14];
  assign pair12 = sig_in[13:12];
  assign pair10 = sig_in[11:10];
  assign pair8 = sig_in[9:8];
  assign pair6 = sig_in[7:6];
  assign pair4 = sig_in[5:4];
  assign pair2 = sig_in[3:2];
  assign pair0 = sig_in[1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:36261.1-48917.10" *)
module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, core_terminate_o, msr__data_o, core_rego, core_ea, core_reg1, core_reg1_ok, core_reg2, core_reg2_ok, core_reg3, core_reg3_ok, core_spro, core_spr1, core_spr1_ok, core_xer_in, core_fast1, core_fast1_ok, core_fast2, core_fast2_ok, core_fasto1, core_fasto2, core_cr_in1, core_cr_in1_ok, core_cr_in2, core_cr_in2_ok, \core_cr_in2$1 , \core_cr_in2_ok$2 , core_cr_out, core_core_msr, core_core_cia, core_core_insn, core_core_insn_type, core_core_fn_unit, core_core_rc, core_core_rc_ok, core_core_oe, core_core_oe_ok, core_core_input_carry, core_core_traptype, \core_core_exc_$signal , \core_core_exc_$signal$3 , \core_core_exc_$signal$4 , \core_core_exc_$signal$5 , \core_core_exc_$signal$6 , \core_core_exc_$signal$7 , \core_core_exc_$signal$8 , \core_core_exc_$signal$9 , core_core_trapaddr, core_core_cr_rd, core_core_cr_rd_ok, core_core_cr_wr, core_core_is_32bit, core_pc, raw_insn_i, bigendian_i, sv_a_nz, \wen$10 , \data_i$11 , ivalid_i, issue_i, state_nia_wen, dmi__addr, dmi__ren, dmi__data_o, full_rd2__ren, full_rd2__data_o, full_rd__ren, full_rd__data_o, issue__addr, issue__ren, issue__data_o, \issue__addr$12 , issue__wen, issue__data_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:46390.3-46410.6" *)
  reg _0000_;
  (* src = "libresoc.v:42786.3-42787.49" *)
  reg _0001_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0002_;
  (* src = "libresoc.v:46220.3-46250.6" *)
  reg [1:0] _0003_;
  (* src = "libresoc.v:42788.3-42789.31" *)
  reg [1:0] _0004_;
  (* src = "libresoc.v:46192.3-46200.6" *)
  reg _0005_;
  (* src = "libresoc.v:42722.3-42723.57" *)
  reg _0006_;
  (* src = "libresoc.v:46173.3-46181.6" *)
  reg _0007_;
  (* src = "libresoc.v:42724.3-42725.49" *)
  reg _0008_;
  (* src = "libresoc.v:46211.3-46219.6" *)
  reg _0009_;
  (* src = "libresoc.v:42720.3-42721.49" *)
  reg _0010_;
  (* src = "libresoc.v:46261.3-46269.6" *)
  reg _0011_;
  (* src = "libresoc.v:42718.3-42719.49" *)
  reg _0012_;
  (* src = "libresoc.v:46154.3-46162.6" *)
  reg _0013_;
  (* src = "libresoc.v:42726.3-42727.55" *)
  reg _0014_;
  (* src = "libresoc.v:46371.3-46379.6" *)
  reg _0015_;
  (* src = "libresoc.v:42716.3-42717.63" *)
  reg _0016_;
  (* src = "libresoc.v:46478.3-46486.6" *)
  reg _0017_;
  (* src = "libresoc.v:42710.3-42711.63" *)
  reg _0018_;
  (* src = "libresoc.v:46430.3-46438.6" *)
  reg _0019_;
  (* src = "libresoc.v:42712.3-42713.57" *)
  reg _0020_;
  (* src = "libresoc.v:46411.3-46419.6" *)
  reg _0021_;
  (* src = "libresoc.v:42714.3-42715.59" *)
  reg _0022_;
  (* src = "libresoc.v:46497.3-46505.6" *)
  reg _0023_;
  (* src = "libresoc.v:42708.3-42709.59" *)
  reg _0024_;
  (* src = "libresoc.v:45603.3-45611.6" *)
  reg _0025_;
  (* src = "libresoc.v:42784.3-42785.53" *)
  reg _0026_;
  (* src = "libresoc.v:45793.3-45801.6" *)
  reg _0027_;
  (* src = "libresoc.v:42764.3-42765.55" *)
  reg _0028_;
  (* src = "libresoc.v:45622.3-45630.6" *)
  reg _0029_;
  (* src = "libresoc.v:45812.3-45820.6" *)
  reg _0030_;
  (* src = "libresoc.v:42762.3-42763.53" *)
  reg _0031_;
  (* src = "libresoc.v:42782.3-42783.51" *)
  reg _0032_;
  (* src = "libresoc.v:45888.3-45896.6" *)
  reg _0033_;
  (* src = "libresoc.v:42754.3-42755.55" *)
  reg _0034_;
  (* src = "libresoc.v:45679.3-45687.6" *)
  reg _0035_;
  (* src = "libresoc.v:42776.3-42777.53" *)
  reg _0036_;
  (* src = "libresoc.v:45945.3-45953.6" *)
  reg _0037_;
  (* src = "libresoc.v:42748.3-42749.57" *)
  reg _0038_;
  (* src = "libresoc.v:45736.3-45744.6" *)
  reg _0039_;
  (* src = "libresoc.v:42770.3-42771.55" *)
  reg _0040_;
  (* src = "libresoc.v:45774.3-45782.6" *)
  reg _0041_;
  (* src = "libresoc.v:42766.3-42767.55" *)
  reg _0042_;
  (* src = "libresoc.v:45850.3-45858.6" *)
  reg _0043_;
  (* src = "libresoc.v:42758.3-42759.63" *)
  reg _0044_;
  (* src = "libresoc.v:45660.3-45668.6" *)
  reg _0045_;
  (* src = "libresoc.v:42778.3-42779.61" *)
  reg _0046_;
  (* src = "libresoc.v:45907.3-45915.6" *)
  reg _0047_;
  (* src = "libresoc.v:42752.3-42753.55" *)
  reg _0048_;
  (* src = "libresoc.v:45698.3-45706.6" *)
  reg _0049_;
  (* src = "libresoc.v:42774.3-42775.53" *)
  reg _0050_;
  (* src = "libresoc.v:45926.3-45934.6" *)
  reg _0051_;
  (* src = "libresoc.v:42750.3-42751.65" *)
  reg _0052_;
  (* src = "libresoc.v:45717.3-45725.6" *)
  reg _0053_;
  (* src = "libresoc.v:42772.3-42773.63" *)
  reg _0054_;
  (* src = "libresoc.v:45755.3-45763.6" *)
  reg _0055_;
  (* src = "libresoc.v:42768.3-42769.63" *)
  reg _0056_;
  (* src = "libresoc.v:45869.3-45877.6" *)
  reg _0057_;
  (* src = "libresoc.v:42756.3-42757.55" *)
  reg _0058_;
  (* src = "libresoc.v:45831.3-45839.6" *)
  reg _0059_;
  (* src = "libresoc.v:42760.3-42761.57" *)
  reg _0060_;
  (* src = "libresoc.v:45641.3-45649.6" *)
  reg _0061_;
  (* src = "libresoc.v:42780.3-42781.55" *)
  reg _0062_;
  (* src = "libresoc.v:46545.3-46553.6" *)
  reg _0063_;
  (* src = "libresoc.v:42706.3-42707.53" *)
  reg _0064_;
  (* src = "libresoc.v:46078.3-46086.6" *)
  reg _0065_;
  (* src = "libresoc.v:42734.3-42735.57" *)
  reg _0066_;
  (* src = "libresoc.v:46116.3-46124.6" *)
  reg _0067_;
  (* src = "libresoc.v:42730.3-42731.67" *)
  reg _0068_;
  (* src = "libresoc.v:46097.3-46105.6" *)
  reg _0069_;
  (* src = "libresoc.v:42732.3-42733.57" *)
  reg _0070_;
  (* src = "libresoc.v:46135.3-46143.6" *)
  reg _0071_;
  (* src = "libresoc.v:42728.3-42729.57" *)
  reg _0072_;
  (* src = "libresoc.v:45964.3-45972.6" *)
  reg _0073_;
  (* src = "libresoc.v:42746.3-42747.57" *)
  reg _0074_;
  (* src = "libresoc.v:46021.3-46029.6" *)
  reg _0075_;
  (* src = "libresoc.v:42740.3-42741.57" *)
  reg _0076_;
  (* src = "libresoc.v:45983.3-45991.6" *)
  reg _0077_;
  (* src = "libresoc.v:42744.3-42745.65" *)
  reg _0078_;
  (* src = "libresoc.v:46040.3-46048.6" *)
  reg _0079_;
  (* src = "libresoc.v:42738.3-42739.57" *)
  reg _0080_;
  (* src = "libresoc.v:46059.3-46067.6" *)
  reg _0081_;
  (* src = "libresoc.v:42736.3-42737.67" *)
  reg _0082_;
  (* src = "libresoc.v:46002.3-46010.6" *)
  reg _0083_;
  (* src = "libresoc.v:42742.3-42743.57" *)
  reg _0084_;
  (* src = "libresoc.v:47359.3-47387.6" *)
  reg _0085_;
  (* src = "libresoc.v:47684.3-47712.6" *)
  reg _0086_;
  (* src = "libresoc.v:48003.3-48031.6" *)
  reg _0087_;
  (* src = "libresoc.v:43648.3-43676.6" *)
  reg _0088_;
  (* src = "libresoc.v:43822.3-43850.6" *)
  reg _0089_;
  (* src = "libresoc.v:44318.3-44346.6" *)
  reg _0090_;
  (* src = "libresoc.v:44640.3-44668.6" *)
  reg _0091_;
  (* src = "libresoc.v:45107.3-45135.6" *)
  reg _0092_;
  (* src = "libresoc.v:45545.3-45573.6" *)
  reg _0093_;
  (* src = "libresoc.v:47151.3-47179.6" *)
  reg _0094_;
  (* src = "libresoc.v:47406.3-47434.6" *)
  reg [5:0] _0095_;
  (* src = "libresoc.v:47713.3-47741.6" *)
  reg [2:0] _0096_;
  (* src = "libresoc.v:48032.3-48060.6" *)
  reg [3:0] _0097_;
  (* src = "libresoc.v:43677.3-43705.6" *)
  reg [2:0] _0098_;
  (* src = "libresoc.v:43851.3-43879.6" *)
  reg [5:0] _0099_;
  (* src = "libresoc.v:44347.3-44375.6" *)
  reg [2:0] _0100_;
  (* src = "libresoc.v:44669.3-44697.6" *)
  reg [2:0] _0101_;
  (* src = "libresoc.v:45136.3-45164.6" *)
  reg [4:0] _0102_;
  (* src = "libresoc.v:45574.3-45602.6" *)
  reg [2:0] _0103_;
  (* src = "libresoc.v:47189.3-47217.6" *)
  reg [3:0] _0104_;
  (* src = "libresoc.v:47066.3-47094.6" *)
  reg [3:0] _0105_;
  (* src = "libresoc.v:46516.3-46544.6" *)
  reg [13:0] _0106_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg [63:0] _0107_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg _0108_;
  (* src = "libresoc.v:46896.3-46924.6" *)
  reg [1:0] _0109_;
  (* src = "libresoc.v:47104.3-47132.6" *)
  reg [31:0] _0110_;
  (* src = "libresoc.v:46449.3-46477.6" *)
  reg [6:0] _0111_;
  (* src = "libresoc.v:46735.3-46763.6" *)
  reg _0112_;
  (* src = "libresoc.v:46811.3-46839.6" *)
  reg _0113_;
  (* src = "libresoc.v:46981.3-47009.6" *)
  reg _0114_;
  (* src = "libresoc.v:47019.3-47047.6" *)
  reg _0115_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0116_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0117_;
  (* src = "libresoc.v:46943.3-46971.6" *)
  reg _0118_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0119_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0120_;
  (* src = "libresoc.v:46849.3-46877.6" *)
  reg _0121_;
  (* src = "libresoc.v:46773.3-46801.6" *)
  reg _0122_;
  (* src = "libresoc.v:47444.3-47472.6" *)
  reg [63:0] _0123_;
  (* src = "libresoc.v:47529.3-47557.6" *)
  reg [13:0] _0124_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg [63:0] _0125_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg _0126_;
  (* src = "libresoc.v:47567.3-47595.6" *)
  reg [31:0] _0127_;
  (* src = "libresoc.v:47482.3-47510.6" *)
  reg [6:0] _0128_;
  (* src = "libresoc.v:47655.3-47683.6" *)
  reg _0129_;
  (* src = "libresoc.v:47626.3-47654.6" *)
  reg _0130_;
  (* src = "libresoc.v:47274.3-47302.6" *)
  reg [13:0] _0131_;
  (* src = "libresoc.v:47321.3-47349.6" *)
  reg [31:0] _0132_;
  (* src = "libresoc.v:47236.3-47264.6" *)
  reg [6:0] _0133_;
  (* src = "libresoc.v:44260.3-44288.6" *)
  reg [3:0] _0134_;
  (* src = "libresoc.v:43909.3-43937.6" *)
  reg [13:0] _0135_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg [63:0] _0136_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg _0137_;
  (* src = "libresoc.v:44086.3-44114.6" *)
  reg [1:0] _0138_;
  (* src = "libresoc.v:44289.3-44317.6" *)
  reg [31:0] _0139_;
  (* src = "libresoc.v:43880.3-43908.6" *)
  reg [6:0] _0140_;
  (* src = "libresoc.v:44028.3-44056.6" *)
  reg _0141_;
  (* src = "libresoc.v:44115.3-44143.6" *)
  reg _0142_;
  (* src = "libresoc.v:44202.3-44230.6" *)
  reg _0143_;
  (* src = "libresoc.v:44231.3-44259.6" *)
  reg _0144_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0145_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0146_;
  (* src = "libresoc.v:44173.3-44201.6" *)
  reg _0147_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0148_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0149_;
  (* src = "libresoc.v:44144.3-44172.6" *)
  reg _0150_;
  (* src = "libresoc.v:44057.3-44085.6" *)
  reg _0151_;
  (* src = "libresoc.v:43590.3-43618.6" *)
  reg [3:0] _0152_;
  (* src = "libresoc.v:48090.3-48118.6" *)
  reg [13:0] _0153_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg [63:0] _0154_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg _0155_;
  (* src = "libresoc.v:48267.3-48295.6" *)
  reg [1:0] _0156_;
  (* src = "libresoc.v:43619.3-43647.6" *)
  reg [31:0] _0157_;
  (* src = "libresoc.v:48061.3-48089.6" *)
  reg [6:0] _0158_;
  (* src = "libresoc.v:48209.3-48237.6" *)
  reg _0159_;
  (* src = "libresoc.v:48296.3-48324.6" *)
  reg _0160_;
  (* src = "libresoc.v:43532.3-43560.6" *)
  reg _0161_;
  (* src = "libresoc.v:43561.3-43589.6" *)
  reg _0162_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0163_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0164_;
  (* src = "libresoc.v:43503.3-43531.6" *)
  reg _0165_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0166_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0167_;
  (* src = "libresoc.v:48325.3-48353.6" *)
  reg _0168_;
  (* src = "libresoc.v:48238.3-48266.6" *)
  reg _0169_;
  (* src = "libresoc.v:44405.3-44433.6" *)
  reg [13:0] _0170_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg [63:0] _0171_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg _0172_;
  (* src = "libresoc.v:44611.3-44639.6" *)
  reg [31:0] _0173_;
  (* src = "libresoc.v:44376.3-44404.6" *)
  reg [6:0] _0174_;
  (* src = "libresoc.v:44553.3-44581.6" *)
  reg _0175_;
  (* src = "libresoc.v:44582.3-44610.6" *)
  reg _0176_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0177_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0178_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0179_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0180_;
  (* src = "libresoc.v:44524.3-44552.6" *)
  reg _0181_;
  (* src = "libresoc.v:44727.3-44755.6" *)
  reg [13:0] _0182_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg [63:0] _0183_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg _0184_;
  (* src = "libresoc.v:44904.3-44932.6" *)
  reg [1:0] _0185_;
  (* src = "libresoc.v:44962.3-44990.6" *)
  reg _0186_;
  (* src = "libresoc.v:45078.3-45106.6" *)
  reg [31:0] _0187_;
  (* src = "libresoc.v:44698.3-44726.6" *)
  reg [6:0] _0188_;
  (* src = "libresoc.v:44875.3-44903.6" *)
  reg _0189_;
  (* src = "libresoc.v:45020.3-45048.6" *)
  reg _0190_;
  (* src = "libresoc.v:45049.3-45077.6" *)
  reg _0191_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0192_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0193_;
  (* src = "libresoc.v:44933.3-44961.6" *)
  reg _0194_;
  (* src = "libresoc.v:44991.3-45019.6" *)
  reg _0195_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0196_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0197_;
  (* src = "libresoc.v:44846.3-44874.6" *)
  reg _0198_;
  (* src = "libresoc.v:43735.3-43763.6" *)
  reg [13:0] _0199_;
  (* src = "libresoc.v:43764.3-43792.6" *)
  reg [31:0] _0200_;
  (* src = "libresoc.v:43706.3-43734.6" *)
  reg [6:0] _0201_;
  (* src = "libresoc.v:43793.3-43821.6" *)
  reg _0202_;
  (* src = "libresoc.v:47858.3-47886.6" *)
  reg [63:0] _0203_;
  (* src = "libresoc.v:47771.3-47799.6" *)
  reg [13:0] _0204_;
  (* src = "libresoc.v:47800.3-47828.6" *)
  reg [31:0] _0205_;
  (* src = "libresoc.v:47742.3-47770.6" *)
  reg [6:0] _0206_;
  (* src = "libresoc.v:47887.3-47915.6" *)
  reg _0207_;
  (* src = "libresoc.v:47974.3-48002.6" *)
  reg [7:0] _0208_;
  (* src = "libresoc.v:47829.3-47857.6" *)
  reg [63:0] _0209_;
  (* src = "libresoc.v:47945.3-47973.6" *)
  reg [12:0] _0210_;
  (* src = "libresoc.v:47916.3-47944.6" *)
  reg [7:0] _0211_;
  (* src = "libresoc.v:45429.3-45457.6" *)
  reg _0212_;
  (* src = "libresoc.v:45400.3-45428.6" *)
  reg [3:0] _0213_;
  (* src = "libresoc.v:45194.3-45222.6" *)
  reg [13:0] _0214_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg [63:0] _0215_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg _0216_;
  (* src = "libresoc.v:45516.3-45544.6" *)
  reg [31:0] _0217_;
  (* src = "libresoc.v:45165.3-45193.6" *)
  reg [6:0] _0218_;
  (* src = "libresoc.v:45342.3-45370.6" *)
  reg _0219_;
  (* src = "libresoc.v:45371.3-45399.6" *)
  reg _0220_;
  (* src = "libresoc.v:45487.3-45515.6" *)
  reg [1:0] _0221_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0222_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0223_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0224_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0225_;
  (* src = "libresoc.v:45458.3-45486.6" *)
  reg _0226_;
  (* src = "libresoc.v:45253.3-45281.6" *)
  reg _0227_;
  (* src = "libresoc.v:45821.3-45830.6" *)
  reg [63:0] _0228_;
  (* src = "libresoc.v:45840.3-45849.6" *)
  reg [63:0] _0229_;
  (* src = "libresoc.v:45859.3-45868.6" *)
  reg [63:0] _0230_;
  (* src = "libresoc.v:45878.3-45887.6" *)
  reg [63:0] _0231_;
  (* src = "libresoc.v:45897.3-45906.6" *)
  reg [63:0] _0232_;
  (* src = "libresoc.v:45916.3-45925.6" *)
  reg [63:0] _0233_;
  (* src = "libresoc.v:45935.3-45944.6" *)
  reg [63:0] _0234_;
  (* src = "libresoc.v:45954.3-45963.6" *)
  reg [63:0] _0235_;
  (* src = "libresoc.v:46380.3-46389.6" *)
  reg [63:0] _0236_;
  (* src = "libresoc.v:45802.3-45811.6" *)
  reg [63:0] _0237_;
  (* src = "libresoc.v:45631.3-45640.6" *)
  reg [63:0] _0238_;
  (* src = "libresoc.v:45650.3-45659.6" *)
  reg [63:0] _0239_;
  (* src = "libresoc.v:45669.3-45678.6" *)
  reg [63:0] _0240_;
  (* src = "libresoc.v:45688.3-45697.6" *)
  reg [63:0] _0241_;
  (* src = "libresoc.v:45707.3-45716.6" *)
  reg [63:0] _0242_;
  (* src = "libresoc.v:45726.3-45735.6" *)
  reg [63:0] _0243_;
  (* src = "libresoc.v:45745.3-45754.6" *)
  reg [63:0] _0244_;
  (* src = "libresoc.v:46487.3-46496.6" *)
  reg [63:0] _0245_;
  (* src = "libresoc.v:46554.3-46563.6" *)
  reg [63:0] _0246_;
  (* src = "libresoc.v:45612.3-45621.6" *)
  reg [63:0] _0247_;
  (* src = "libresoc.v:45783.3-45792.6" *)
  reg [63:0] _0248_;
  (* src = "libresoc.v:45973.3-45982.6" *)
  reg _0249_;
  (* src = "libresoc.v:45992.3-46001.6" *)
  reg _0250_;
  (* src = "libresoc.v:46030.3-46039.6" *)
  reg _0251_;
  (* src = "libresoc.v:46049.3-46058.6" *)
  reg _0252_;
  (* src = "libresoc.v:46163.3-46172.6" *)
  reg [31:0] _0253_;
  (* src = "libresoc.v:46201.3-46210.6" *)
  reg [3:0] _0254_;
  (* src = "libresoc.v:46420.3-46429.6" *)
  reg [63:0] _0255_;
  (* src = "libresoc.v:46439.3-46448.6" *)
  reg [63:0] _0256_;
  (* src = "libresoc.v:45764.3-45773.6" *)
  reg [63:0] _0257_;
  (* src = "libresoc.v:46068.3-46077.6" *)
  reg _0258_;
  (* src = "libresoc.v:46087.3-46096.6" *)
  reg [1:0] _0259_;
  (* src = "libresoc.v:46182.3-46191.6" *)
  reg [3:0] _0260_;
  (* src = "libresoc.v:46506.3-46515.6" *)
  reg [63:0] _0261_;
  (* src = "libresoc.v:46011.3-46020.6" *)
  reg _0262_;
  (* src = "libresoc.v:46144.3-46153.6" *)
  reg [1:0] _0263_;
  (* src = "libresoc.v:46251.3-46260.6" *)
  reg [3:0] _0264_;
  (* src = "libresoc.v:46125.3-46134.6" *)
  reg [1:0] _0265_;
  (* src = "libresoc.v:46270.3-46279.6" *)
  reg [3:0] _0266_;
  (* src = "libresoc.v:46106.3-46115.6" *)
  reg [1:0] _0267_;
  (* src = "libresoc.v:36262.7-36262.20" *)
  reg _0268_;
  (* src = "libresoc.v:46612.3-46620.6" *)
  reg _0269_;
  (* src = "libresoc.v:42700.3-42701.51" *)
  reg _0270_;
  (* src = "libresoc.v:41530.7-41530.32" *)
  reg _0271_;
  (* src = "libresoc.v:46651.3-46659.6" *)
  reg _0272_;
  (* src = "libresoc.v:42698.3-42699.51" *)
  reg _0273_;
  (* src = "libresoc.v:41534.7-41534.32" *)
  reg _0274_;
  (* src = "libresoc.v:46660.3-46668.6" *)
  reg _0275_;
  (* src = "libresoc.v:42696.3-42697.51" *)
  reg _0276_;
  (* src = "libresoc.v:41538.7-41538.32" *)
  reg _0277_;
  (* src = "libresoc.v:46669.3-46677.6" *)
  reg _0278_;
  (* src = "libresoc.v:42694.3-42695.51" *)
  reg _0279_;
  (* src = "libresoc.v:41542.7-41542.32" *)
  reg _0280_;
  (* src = "libresoc.v:46708.3-46716.6" *)
  reg _0281_;
  (* src = "libresoc.v:42692.3-42693.51" *)
  reg _0282_;
  (* src = "libresoc.v:41546.7-41546.32" *)
  reg _0283_;
  (* src = "libresoc.v:46717.3-46725.6" *)
  reg _0284_;
  (* src = "libresoc.v:42690.3-42691.51" *)
  reg _0285_;
  (* src = "libresoc.v:41550.7-41550.32" *)
  reg _0286_;
  (* src = "libresoc.v:46726.3-46734.6" *)
  reg _0287_;
  (* src = "libresoc.v:42688.3-42689.51" *)
  reg _0288_;
  (* src = "libresoc.v:41554.7-41554.32" *)
  reg _0289_;
  (* src = "libresoc.v:46764.3-46772.6" *)
  reg _0290_;
  (* src = "libresoc.v:42686.3-42687.51" *)
  reg _0291_;
  (* src = "libresoc.v:41558.7-41558.32" *)
  reg _0292_;
  (* src = "libresoc.v:46802.3-46810.6" *)
  reg _0293_;
  (* src = "libresoc.v:42684.3-42685.51" *)
  reg _0294_;
  (* src = "libresoc.v:41562.7-41562.32" *)
  reg _0295_;
  (* src = "libresoc.v:46840.3-46848.6" *)
  reg _0296_;
  (* src = "libresoc.v:42682.3-42683.51" *)
  reg _0297_;
  (* src = "libresoc.v:41566.7-41566.32" *)
  reg _0298_;
  (* src = "libresoc.v:46878.3-46886.6" *)
  reg _0299_;
  (* src = "libresoc.v:42680.3-42681.51" *)
  reg _0300_;
  (* src = "libresoc.v:41570.7-41570.32" *)
  reg _0301_;
  (* src = "libresoc.v:46887.3-46895.6" *)
  reg _0302_;
  (* src = "libresoc.v:42678.3-42679.51" *)
  reg _0303_;
  (* src = "libresoc.v:41574.7-41574.32" *)
  reg _0304_;
  (* src = "libresoc.v:46925.3-46933.6" *)
  reg _0305_;
  (* src = "libresoc.v:42676.3-42677.51" *)
  reg _0306_;
  (* src = "libresoc.v:41578.7-41578.32" *)
  reg _0307_;
  (* src = "libresoc.v:46934.3-46942.6" *)
  reg _0308_;
  (* src = "libresoc.v:42674.3-42675.51" *)
  reg _0309_;
  (* src = "libresoc.v:41582.7-41582.32" *)
  reg _0310_;
  (* src = "libresoc.v:46972.3-46980.6" *)
  reg _0311_;
  (* src = "libresoc.v:42672.3-42673.51" *)
  reg _0312_;
  (* src = "libresoc.v:41586.7-41586.32" *)
  reg _0313_;
  (* src = "libresoc.v:47010.3-47018.6" *)
  reg _0314_;
  (* src = "libresoc.v:42670.3-42671.51" *)
  reg _0315_;
  (* src = "libresoc.v:41590.7-41590.32" *)
  reg _0316_;
  (* src = "libresoc.v:47048.3-47056.6" *)
  reg _0317_;
  (* src = "libresoc.v:42668.3-42669.51" *)
  reg _0318_;
  (* src = "libresoc.v:41594.7-41594.32" *)
  reg _0319_;
  (* src = "libresoc.v:47057.3-47065.6" *)
  reg _0320_;
  (* src = "libresoc.v:42666.3-42667.51" *)
  reg _0321_;
  (* src = "libresoc.v:41598.7-41598.32" *)
  reg _0322_;
  (* src = "libresoc.v:47095.3-47103.6" *)
  reg _0323_;
  (* src = "libresoc.v:42664.3-42665.51" *)
  reg _0324_;
  (* src = "libresoc.v:41602.7-41602.32" *)
  reg _0325_;
  (* src = "libresoc.v:47133.3-47141.6" *)
  reg _0326_;
  (* src = "libresoc.v:42662.3-42663.51" *)
  reg _0327_;
  (* src = "libresoc.v:41606.7-41606.32" *)
  reg _0328_;
  (* src = "libresoc.v:47142.3-47150.6" *)
  reg _0329_;
  (* src = "libresoc.v:42660.3-42661.51" *)
  reg _0330_;
  (* src = "libresoc.v:41610.7-41610.32" *)
  reg _0331_;
  (* src = "libresoc.v:47180.3-47188.6" *)
  reg _0332_;
  (* src = "libresoc.v:42658.3-42659.51" *)
  reg _0333_;
  (* src = "libresoc.v:41614.7-41614.32" *)
  reg _0334_;
  (* src = "libresoc.v:47218.3-47226.6" *)
  reg _0335_;
  (* src = "libresoc.v:42656.3-42657.51" *)
  reg _0336_;
  (* src = "libresoc.v:41618.7-41618.32" *)
  reg _0337_;
  (* src = "libresoc.v:47227.3-47235.6" *)
  reg _0338_;
  (* src = "libresoc.v:42654.3-42655.51" *)
  reg _0339_;
  (* src = "libresoc.v:41622.7-41622.32" *)
  reg _0340_;
  (* src = "libresoc.v:47265.3-47273.6" *)
  reg _0341_;
  (* src = "libresoc.v:42652.3-42653.51" *)
  reg _0342_;
  (* src = "libresoc.v:41626.7-41626.32" *)
  reg _0343_;
  (* src = "libresoc.v:47303.3-47311.6" *)
  reg _0344_;
  (* src = "libresoc.v:42650.3-42651.51" *)
  reg _0345_;
  (* src = "libresoc.v:41630.7-41630.32" *)
  reg _0346_;
  (* src = "libresoc.v:47312.3-47320.6" *)
  reg _0347_;
  (* src = "libresoc.v:42648.3-42649.51" *)
  reg _0348_;
  (* src = "libresoc.v:41634.7-41634.32" *)
  reg _0349_;
  (* src = "libresoc.v:47350.3-47358.6" *)
  reg _0350_;
  (* src = "libresoc.v:42646.3-42647.51" *)
  reg _0351_;
  (* src = "libresoc.v:41638.7-41638.32" *)
  reg _0352_;
  (* src = "libresoc.v:47388.3-47396.6" *)
  reg _0353_;
  (* src = "libresoc.v:42644.3-42645.51" *)
  reg _0354_;
  (* src = "libresoc.v:41642.7-41642.32" *)
  reg _0355_;
  (* src = "libresoc.v:47397.3-47405.6" *)
  reg _0356_;
  (* src = "libresoc.v:42642.3-42643.51" *)
  reg _0357_;
  (* src = "libresoc.v:41646.7-41646.32" *)
  reg _0358_;
  (* src = "libresoc.v:47435.3-47443.6" *)
  reg _0359_;
  (* src = "libresoc.v:42640.3-42641.51" *)
  reg _0360_;
  (* src = "libresoc.v:41650.7-41650.32" *)
  reg _0361_;
  (* src = "libresoc.v:47473.3-47481.6" *)
  reg _0362_;
  (* src = "libresoc.v:42638.3-42639.51" *)
  reg _0363_;
  (* src = "libresoc.v:41654.7-41654.32" *)
  reg _0364_;
  (* src = "libresoc.v:47511.3-47519.6" *)
  reg _0365_;
  (* src = "libresoc.v:42636.3-42637.51" *)
  reg _0366_;
  (* src = "libresoc.v:41658.7-41658.32" *)
  reg _0367_;
  (* src = "libresoc.v:47520.3-47528.6" *)
  reg _0368_;
  (* src = "libresoc.v:42634.3-42635.51" *)
  reg _0369_;
  (* src = "libresoc.v:41662.7-41662.32" *)
  reg _0370_;
  (* src = "libresoc.v:47558.3-47566.6" *)
  reg _0371_;
  (* src = "libresoc.v:42632.3-42633.51" *)
  reg _0372_;
  (* src = "libresoc.v:41666.7-41666.32" *)
  reg _0373_;
  (* src = "libresoc.v:46603.3-46611.6" *)
  reg _0374_;
  (* src = "libresoc.v:42702.3-42703.49" *)
  reg _0375_;
  (* src = "libresoc.v:41670.7-41670.31" *)
  reg _0376_;
  (* src = "libresoc.v:46594.3-46602.6" *)
  reg _0377_;
  (* src = "libresoc.v:42704.3-42705.39" *)
  reg _0378_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0379_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0380_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0381_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0382_;
  (* src = "libresoc.v:46390.3-46410.6" *)
  reg _0383_;
  (* src = "libresoc.v:38103.7-38103.30" *)
  reg _0384_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0385_;
  (* src = "libresoc.v:46220.3-46250.6" *)
  reg [1:0] _0386_;
  (* src = "libresoc.v:38116.13-38116.27" *)
  reg [1:0] _0387_;
  (* src = "libresoc.v:46192.3-46200.6" *)
  reg _0388_;
  (* src = "libresoc.v:39283.7-39283.34" *)
  reg _0389_;
  (* src = "libresoc.v:46173.3-46181.6" *)
  reg _0390_;
  (* src = "libresoc.v:39287.7-39287.30" *)
  reg _0391_;
  (* src = "libresoc.v:46211.3-46219.6" *)
  reg _0392_;
  (* src = "libresoc.v:39291.7-39291.30" *)
  reg _0393_;
  (* src = "libresoc.v:46261.3-46269.6" *)
  reg _0394_;
  (* src = "libresoc.v:39295.7-39295.30" *)
  reg _0395_;
  (* src = "libresoc.v:46154.3-46162.6" *)
  reg _0396_;
  (* src = "libresoc.v:39299.7-39299.33" *)
  reg _0397_;
  (* src = "libresoc.v:46371.3-46379.6" *)
  reg _0398_;
  (* src = "libresoc.v:39303.7-39303.37" *)
  reg _0399_;
  (* src = "libresoc.v:46478.3-46486.6" *)
  reg _0400_;
  (* src = "libresoc.v:39307.7-39307.37" *)
  reg _0401_;
  (* src = "libresoc.v:46430.3-46438.6" *)
  reg _0402_;
  (* src = "libresoc.v:39311.7-39311.34" *)
  reg _0403_;
  (* src = "libresoc.v:46411.3-46419.6" *)
  reg _0404_;
  (* src = "libresoc.v:39315.7-39315.35" *)
  reg _0405_;
  (* src = "libresoc.v:46497.3-46505.6" *)
  reg _0406_;
  (* src = "libresoc.v:39319.7-39319.35" *)
  reg _0407_;
  (* src = "libresoc.v:45603.3-45611.6" *)
  reg _0408_;
  (* src = "libresoc.v:39323.7-39323.32" *)
  reg _0409_;
  (* src = "libresoc.v:45793.3-45801.6" *)
  reg _0410_;
  (* src = "libresoc.v:39327.7-39327.33" *)
  reg _0411_;
  (* src = "libresoc.v:45622.3-45630.6" *)
  reg _0412_;
  (* src = "libresoc.v:45812.3-45820.6" *)
  reg _0413_;
  (* src = "libresoc.v:39335.7-39335.32" *)
  reg _0414_;
  (* src = "libresoc.v:39331.7-39331.31" *)
  reg _0415_;
  (* src = "libresoc.v:45888.3-45896.6" *)
  reg _0416_;
  (* src = "libresoc.v:39339.7-39339.33" *)
  reg _0417_;
  (* src = "libresoc.v:45679.3-45687.6" *)
  reg _0418_;
  (* src = "libresoc.v:39343.7-39343.32" *)
  reg _0419_;
  (* src = "libresoc.v:45945.3-45953.6" *)
  reg _0420_;
  (* src = "libresoc.v:39347.7-39347.34" *)
  reg _0421_;
  (* src = "libresoc.v:45736.3-45744.6" *)
  reg _0422_;
  (* src = "libresoc.v:39351.7-39351.33" *)
  reg _0423_;
  (* src = "libresoc.v:45774.3-45782.6" *)
  reg _0424_;
  (* src = "libresoc.v:39355.7-39355.33" *)
  reg _0425_;
  (* src = "libresoc.v:45850.3-45858.6" *)
  reg _0426_;
  (* src = "libresoc.v:39359.7-39359.37" *)
  reg _0427_;
  (* src = "libresoc.v:45660.3-45668.6" *)
  reg _0428_;
  (* src = "libresoc.v:39363.7-39363.36" *)
  reg _0429_;
  (* src = "libresoc.v:45907.3-45915.6" *)
  reg _0430_;
  (* src = "libresoc.v:39367.7-39367.33" *)
  reg _0431_;
  (* src = "libresoc.v:45698.3-45706.6" *)
  reg _0432_;
  (* src = "libresoc.v:39371.7-39371.32" *)
  reg _0433_;
  (* src = "libresoc.v:45926.3-45934.6" *)
  reg _0434_;
  (* src = "libresoc.v:39375.7-39375.38" *)
  reg _0435_;
  (* src = "libresoc.v:45717.3-45725.6" *)
  reg _0436_;
  (* src = "libresoc.v:39379.7-39379.37" *)
  reg _0437_;
  (* src = "libresoc.v:45755.3-45763.6" *)
  reg _0438_;
  (* src = "libresoc.v:39383.7-39383.37" *)
  reg _0439_;
  (* src = "libresoc.v:45869.3-45877.6" *)
  reg _0440_;
  (* src = "libresoc.v:39387.7-39387.33" *)
  reg _0441_;
  (* src = "libresoc.v:45831.3-45839.6" *)
  reg _0442_;
  (* src = "libresoc.v:39391.7-39391.34" *)
  reg _0443_;
  (* src = "libresoc.v:45641.3-45649.6" *)
  reg _0444_;
  (* src = "libresoc.v:39395.7-39395.33" *)
  reg _0445_;
  (* src = "libresoc.v:46545.3-46553.6" *)
  reg _0446_;
  (* src = "libresoc.v:39399.7-39399.32" *)
  reg _0447_;
  (* src = "libresoc.v:46078.3-46086.6" *)
  reg _0448_;
  (* src = "libresoc.v:39403.7-39403.34" *)
  reg _0449_;
  (* src = "libresoc.v:46116.3-46124.6" *)
  reg _0450_;
  (* src = "libresoc.v:39407.7-39407.39" *)
  reg _0451_;
  (* src = "libresoc.v:46097.3-46105.6" *)
  reg _0452_;
  (* src = "libresoc.v:39411.7-39411.34" *)
  reg _0453_;
  (* src = "libresoc.v:46135.3-46143.6" *)
  reg _0454_;
  (* src = "libresoc.v:39415.7-39415.34" *)
  reg _0455_;
  (* src = "libresoc.v:45964.3-45972.6" *)
  reg _0456_;
  (* src = "libresoc.v:39419.7-39419.34" *)
  reg _0457_;
  (* src = "libresoc.v:46021.3-46029.6" *)
  reg _0458_;
  (* src = "libresoc.v:39423.7-39423.34" *)
  reg _0459_;
  (* src = "libresoc.v:45983.3-45991.6" *)
  reg _0460_;
  (* src = "libresoc.v:39427.7-39427.38" *)
  reg _0461_;
  (* src = "libresoc.v:46040.3-46048.6" *)
  reg _0462_;
  (* src = "libresoc.v:39431.7-39431.34" *)
  reg _0463_;
  (* src = "libresoc.v:46059.3-46067.6" *)
  reg _0464_;
  (* src = "libresoc.v:39435.7-39435.39" *)
  reg _0465_;
  (* src = "libresoc.v:46002.3-46010.6" *)
  reg _0466_;
  (* src = "libresoc.v:39439.7-39439.34" *)
  reg _0467_;
  (* src = "libresoc.v:47359.3-47387.6" *)
  reg _0468_;
  (* src = "libresoc.v:47684.3-47712.6" *)
  reg _0469_;
  (* src = "libresoc.v:48003.3-48031.6" *)
  reg _0470_;
  (* src = "libresoc.v:43648.3-43676.6" *)
  reg _0471_;
  (* src = "libresoc.v:43822.3-43850.6" *)
  reg _0472_;
  (* src = "libresoc.v:44318.3-44346.6" *)
  reg _0473_;
  (* src = "libresoc.v:44640.3-44668.6" *)
  reg _0474_;
  (* src = "libresoc.v:45107.3-45135.6" *)
  reg _0475_;
  (* src = "libresoc.v:45545.3-45573.6" *)
  reg _0476_;
  (* src = "libresoc.v:47151.3-47179.6" *)
  reg _0477_;
  (* src = "libresoc.v:47406.3-47434.6" *)
  reg [5:0] _0478_;
  (* src = "libresoc.v:47713.3-47741.6" *)
  reg [2:0] _0479_;
  (* src = "libresoc.v:48032.3-48060.6" *)
  reg [3:0] _0480_;
  (* src = "libresoc.v:43677.3-43705.6" *)
  reg [2:0] _0481_;
  (* src = "libresoc.v:43851.3-43879.6" *)
  reg [5:0] _0482_;
  (* src = "libresoc.v:44347.3-44375.6" *)
  reg [2:0] _0483_;
  (* src = "libresoc.v:44669.3-44697.6" *)
  reg [2:0] _0484_;
  (* src = "libresoc.v:45136.3-45164.6" *)
  reg [4:0] _0485_;
  (* src = "libresoc.v:45574.3-45602.6" *)
  reg [2:0] _0486_;
  (* src = "libresoc.v:47189.3-47217.6" *)
  reg [3:0] _0487_;
  (* src = "libresoc.v:47066.3-47094.6" *)
  reg [3:0] _0488_;
  (* src = "libresoc.v:46516.3-46544.6" *)
  reg [13:0] _0489_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg [63:0] _0490_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg _0491_;
  (* src = "libresoc.v:46896.3-46924.6" *)
  reg [1:0] _0492_;
  (* src = "libresoc.v:47104.3-47132.6" *)
  reg [31:0] _0493_;
  (* src = "libresoc.v:46449.3-46477.6" *)
  reg [6:0] _0494_;
  (* src = "libresoc.v:46735.3-46763.6" *)
  reg _0495_;
  (* src = "libresoc.v:46811.3-46839.6" *)
  reg _0496_;
  (* src = "libresoc.v:46981.3-47009.6" *)
  reg _0497_;
  (* src = "libresoc.v:47019.3-47047.6" *)
  reg _0498_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0499_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0500_;
  (* src = "libresoc.v:46943.3-46971.6" *)
  reg _0501_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0502_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0503_;
  (* src = "libresoc.v:46849.3-46877.6" *)
  reg _0504_;
  (* src = "libresoc.v:46773.3-46801.6" *)
  reg _0505_;
  (* src = "libresoc.v:47444.3-47472.6" *)
  reg [63:0] _0506_;
  (* src = "libresoc.v:47529.3-47557.6" *)
  reg [13:0] _0507_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg [63:0] _0508_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg _0509_;
  (* src = "libresoc.v:47567.3-47595.6" *)
  reg [31:0] _0510_;
  (* src = "libresoc.v:47482.3-47510.6" *)
  reg [6:0] _0511_;
  (* src = "libresoc.v:47655.3-47683.6" *)
  reg _0512_;
  (* src = "libresoc.v:47626.3-47654.6" *)
  reg _0513_;
  (* src = "libresoc.v:47274.3-47302.6" *)
  reg [13:0] _0514_;
  (* src = "libresoc.v:47321.3-47349.6" *)
  reg [31:0] _0515_;
  (* src = "libresoc.v:47236.3-47264.6" *)
  reg [6:0] _0516_;
  (* src = "libresoc.v:44260.3-44288.6" *)
  reg [3:0] _0517_;
  (* src = "libresoc.v:43909.3-43937.6" *)
  reg [13:0] _0518_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg [63:0] _0519_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg _0520_;
  (* src = "libresoc.v:44086.3-44114.6" *)
  reg [1:0] _0521_;
  (* src = "libresoc.v:44289.3-44317.6" *)
  reg [31:0] _0522_;
  (* src = "libresoc.v:43880.3-43908.6" *)
  reg [6:0] _0523_;
  (* src = "libresoc.v:44028.3-44056.6" *)
  reg _0524_;
  (* src = "libresoc.v:44115.3-44143.6" *)
  reg _0525_;
  (* src = "libresoc.v:44202.3-44230.6" *)
  reg _0526_;
  (* src = "libresoc.v:44231.3-44259.6" *)
  reg _0527_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0528_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0529_;
  (* src = "libresoc.v:44173.3-44201.6" *)
  reg _0530_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0531_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0532_;
  (* src = "libresoc.v:44144.3-44172.6" *)
  reg _0533_;
  (* src = "libresoc.v:44057.3-44085.6" *)
  reg _0534_;
  (* src = "libresoc.v:43590.3-43618.6" *)
  reg [3:0] _0535_;
  (* src = "libresoc.v:48090.3-48118.6" *)
  reg [13:0] _0536_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg [63:0] _0537_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg _0538_;
  (* src = "libresoc.v:48267.3-48295.6" *)
  reg [1:0] _0539_;
  (* src = "libresoc.v:43619.3-43647.6" *)
  reg [31:0] _0540_;
  (* src = "libresoc.v:48061.3-48089.6" *)
  reg [6:0] _0541_;
  (* src = "libresoc.v:48209.3-48237.6" *)
  reg _0542_;
  (* src = "libresoc.v:48296.3-48324.6" *)
  reg _0543_;
  (* src = "libresoc.v:43532.3-43560.6" *)
  reg _0544_;
  (* src = "libresoc.v:43561.3-43589.6" *)
  reg _0545_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0546_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0547_;
  (* src = "libresoc.v:43503.3-43531.6" *)
  reg _0548_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0549_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0550_;
  (* src = "libresoc.v:48325.3-48353.6" *)
  reg _0551_;
  (* src = "libresoc.v:48238.3-48266.6" *)
  reg _0552_;
  (* src = "libresoc.v:44405.3-44433.6" *)
  reg [13:0] _0553_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg [63:0] _0554_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg _0555_;
  (* src = "libresoc.v:44611.3-44639.6" *)
  reg [31:0] _0556_;
  (* src = "libresoc.v:44376.3-44404.6" *)
  reg [6:0] _0557_;
  (* src = "libresoc.v:44553.3-44581.6" *)
  reg _0558_;
  (* src = "libresoc.v:44582.3-44610.6" *)
  reg _0559_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0560_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0561_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0562_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0563_;
  (* src = "libresoc.v:44524.3-44552.6" *)
  reg _0564_;
  (* src = "libresoc.v:44727.3-44755.6" *)
  reg [13:0] _0565_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg [63:0] _0566_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg _0567_;
  (* src = "libresoc.v:44904.3-44932.6" *)
  reg [1:0] _0568_;
  (* src = "libresoc.v:44962.3-44990.6" *)
  reg _0569_;
  (* src = "libresoc.v:45078.3-45106.6" *)
  reg [31:0] _0570_;
  (* src = "libresoc.v:44698.3-44726.6" *)
  reg [6:0] _0571_;
  (* src = "libresoc.v:44875.3-44903.6" *)
  reg _0572_;
  (* src = "libresoc.v:45020.3-45048.6" *)
  reg _0573_;
  (* src = "libresoc.v:45049.3-45077.6" *)
  reg _0574_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0575_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0576_;
  (* src = "libresoc.v:44933.3-44961.6" *)
  reg _0577_;
  (* src = "libresoc.v:44991.3-45019.6" *)
  reg _0578_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0579_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0580_;
  (* src = "libresoc.v:44846.3-44874.6" *)
  reg _0581_;
  (* src = "libresoc.v:43735.3-43763.6" *)
  reg [13:0] _0582_;
  (* src = "libresoc.v:43764.3-43792.6" *)
  reg [31:0] _0583_;
  (* src = "libresoc.v:43706.3-43734.6" *)
  reg [6:0] _0584_;
  (* src = "libresoc.v:43793.3-43821.6" *)
  reg _0585_;
  (* src = "libresoc.v:47858.3-47886.6" *)
  reg [63:0] _0586_;
  (* src = "libresoc.v:47771.3-47799.6" *)
  reg [13:0] _0587_;
  (* src = "libresoc.v:47800.3-47828.6" *)
  reg [31:0] _0588_;
  (* src = "libresoc.v:47742.3-47770.6" *)
  reg [6:0] _0589_;
  (* src = "libresoc.v:47887.3-47915.6" *)
  reg _0590_;
  (* src = "libresoc.v:47974.3-48002.6" *)
  reg [7:0] _0591_;
  (* src = "libresoc.v:47829.3-47857.6" *)
  reg [63:0] _0592_;
  (* src = "libresoc.v:47945.3-47973.6" *)
  reg [12:0] _0593_;
  (* src = "libresoc.v:47916.3-47944.6" *)
  reg [7:0] _0594_;
  (* src = "libresoc.v:45429.3-45457.6" *)
  reg _0595_;
  (* src = "libresoc.v:45400.3-45428.6" *)
  reg [3:0] _0596_;
  (* src = "libresoc.v:45194.3-45222.6" *)
  reg [13:0] _0597_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg [63:0] _0598_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg _0599_;
  (* src = "libresoc.v:45516.3-45544.6" *)
  reg [31:0] _0600_;
  (* src = "libresoc.v:45165.3-45193.6" *)
  reg [6:0] _0601_;
  (* src = "libresoc.v:45342.3-45370.6" *)
  reg _0602_;
  (* src = "libresoc.v:45371.3-45399.6" *)
  reg _0603_;
  (* src = "libresoc.v:45487.3-45515.6" *)
  reg [1:0] _0604_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0605_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0606_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0607_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0608_;
  (* src = "libresoc.v:45458.3-45486.6" *)
  reg _0609_;
  (* src = "libresoc.v:45253.3-45281.6" *)
  reg _0610_;
  (* src = "libresoc.v:45821.3-45830.6" *)
  reg [63:0] _0611_;
  (* src = "libresoc.v:45840.3-45849.6" *)
  reg [63:0] _0612_;
  (* src = "libresoc.v:45859.3-45868.6" *)
  reg [63:0] _0613_;
  (* src = "libresoc.v:45878.3-45887.6" *)
  reg [63:0] _0614_;
  (* src = "libresoc.v:45897.3-45906.6" *)
  reg [63:0] _0615_;
  (* src = "libresoc.v:45916.3-45925.6" *)
  reg [63:0] _0616_;
  (* src = "libresoc.v:45935.3-45944.6" *)
  reg [63:0] _0617_;
  (* src = "libresoc.v:45954.3-45963.6" *)
  reg [63:0] _0618_;
  (* src = "libresoc.v:46380.3-46389.6" *)
  reg [63:0] _0619_;
  (* src = "libresoc.v:45802.3-45811.6" *)
  reg [63:0] _0620_;
  (* src = "libresoc.v:45631.3-45640.6" *)
  reg [63:0] _0621_;
  (* src = "libresoc.v:45650.3-45659.6" *)
  reg [63:0] _0622_;
  (* src = "libresoc.v:45669.3-45678.6" *)
  reg [63:0] _0623_;
  (* src = "libresoc.v:45688.3-45697.6" *)
  reg [63:0] _0624_;
  (* src = "libresoc.v:45707.3-45716.6" *)
  reg [63:0] _0625_;
  (* src = "libresoc.v:45726.3-45735.6" *)
  reg [63:0] _0626_;
  (* src = "libresoc.v:45745.3-45754.6" *)
  reg [63:0] _0627_;
  (* src = "libresoc.v:46487.3-46496.6" *)
  reg [63:0] _0628_;
  (* src = "libresoc.v:46554.3-46563.6" *)
  reg [63:0] _0629_;
  (* src = "libresoc.v:45612.3-45621.6" *)
  reg [63:0] _0630_;
  (* src = "libresoc.v:45783.3-45792.6" *)
  reg [63:0] _0631_;
  (* src = "libresoc.v:45973.3-45982.6" *)
  reg _0632_;
  (* src = "libresoc.v:45992.3-46001.6" *)
  reg _0633_;
  (* src = "libresoc.v:46030.3-46039.6" *)
  reg _0634_;
  (* src = "libresoc.v:46049.3-46058.6" *)
  reg _0635_;
  (* src = "libresoc.v:46163.3-46172.6" *)
  reg [31:0] _0636_;
  (* src = "libresoc.v:46201.3-46210.6" *)
  reg [3:0] _0637_;
  (* src = "libresoc.v:46420.3-46429.6" *)
  reg [63:0] _0638_;
  (* src = "libresoc.v:46439.3-46448.6" *)
  reg [63:0] _0639_;
  (* src = "libresoc.v:45764.3-45773.6" *)
  reg [63:0] _0640_;
  (* src = "libresoc.v:46068.3-46077.6" *)
  reg _0641_;
  (* src = "libresoc.v:46087.3-46096.6" *)
  reg [1:0] _0642_;
  (* src = "libresoc.v:46182.3-46191.6" *)
  reg [3:0] _0643_;
  (* src = "libresoc.v:46506.3-46515.6" *)
  reg [63:0] _0644_;
  (* src = "libresoc.v:46011.3-46020.6" *)
  reg _0645_;
  (* src = "libresoc.v:46144.3-46153.6" *)
  reg [1:0] _0646_;
  (* src = "libresoc.v:46251.3-46260.6" *)
  reg [3:0] _0647_;
  (* src = "libresoc.v:46125.3-46134.6" *)
  reg [1:0] _0648_;
  (* src = "libresoc.v:46270.3-46279.6" *)
  reg [3:0] _0649_;
  (* src = "libresoc.v:46106.3-46115.6" *)
  reg [1:0] _0650_;
  (* src = "libresoc.v:46612.3-46620.6" *)
  reg _0651_;
  (* src = "libresoc.v:46651.3-46659.6" *)
  reg _0652_;
  (* src = "libresoc.v:46660.3-46668.6" *)
  reg _0653_;
  (* src = "libresoc.v:46669.3-46677.6" *)
  reg _0654_;
  (* src = "libresoc.v:46708.3-46716.6" *)
  reg _0655_;
  (* src = "libresoc.v:46717.3-46725.6" *)
  reg _0656_;
  (* src = "libresoc.v:46726.3-46734.6" *)
  reg _0657_;
  (* src = "libresoc.v:46764.3-46772.6" *)
  reg _0658_;
  (* src = "libresoc.v:46802.3-46810.6" *)
  reg _0659_;
  (* src = "libresoc.v:46840.3-46848.6" *)
  reg _0660_;
  (* src = "libresoc.v:46878.3-46886.6" *)
  reg _0661_;
  (* src = "libresoc.v:46887.3-46895.6" *)
  reg _0662_;
  (* src = "libresoc.v:46925.3-46933.6" *)
  reg _0663_;
  (* src = "libresoc.v:46934.3-46942.6" *)
  reg _0664_;
  (* src = "libresoc.v:46972.3-46980.6" *)
  reg _0665_;
  (* src = "libresoc.v:47010.3-47018.6" *)
  reg _0666_;
  (* src = "libresoc.v:47048.3-47056.6" *)
  reg _0667_;
  (* src = "libresoc.v:47057.3-47065.6" *)
  reg _0668_;
  (* src = "libresoc.v:47095.3-47103.6" *)
  reg _0669_;
  (* src = "libresoc.v:47133.3-47141.6" *)
  reg _0670_;
  (* src = "libresoc.v:47142.3-47150.6" *)
  reg _0671_;
  (* src = "libresoc.v:47180.3-47188.6" *)
  reg _0672_;
  (* src = "libresoc.v:47218.3-47226.6" *)
  reg _0673_;
  (* src = "libresoc.v:47227.3-47235.6" *)
  reg _0674_;
  (* src = "libresoc.v:47265.3-47273.6" *)
  reg _0675_;
  (* src = "libresoc.v:47303.3-47311.6" *)
  reg _0676_;
  (* src = "libresoc.v:47312.3-47320.6" *)
  reg _0677_;
  (* src = "libresoc.v:47350.3-47358.6" *)
  reg _0678_;
  (* src = "libresoc.v:47388.3-47396.6" *)
  reg _0679_;
  (* src = "libresoc.v:47397.3-47405.6" *)
  reg _0680_;
  (* src = "libresoc.v:47435.3-47443.6" *)
  reg _0681_;
  (* src = "libresoc.v:47473.3-47481.6" *)
  reg _0682_;
  (* src = "libresoc.v:47511.3-47519.6" *)
  reg _0683_;
  (* src = "libresoc.v:47520.3-47528.6" *)
  reg _0684_;
  (* src = "libresoc.v:47558.3-47566.6" *)
  reg _0685_;
  (* src = "libresoc.v:46603.3-46611.6" *)
  reg _0686_;
  (* src = "libresoc.v:46594.3-46602.6" *)
  reg _0687_;
  (* src = "libresoc.v:41528.7-41528.25" *)
  reg _0688_;
  (* src = "libresoc.v:46390.3-46410.6" *)
  reg _0689_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0690_;
  (* src = "libresoc.v:46220.3-46250.6" *)
  reg [1:0] _0691_;
  (* src = "libresoc.v:47359.3-47387.6" *)
  reg _0692_;
  (* src = "libresoc.v:47684.3-47712.6" *)
  reg _0693_;
  (* src = "libresoc.v:48003.3-48031.6" *)
  reg _0694_;
  (* src = "libresoc.v:43648.3-43676.6" *)
  reg _0695_;
  (* src = "libresoc.v:43822.3-43850.6" *)
  reg _0696_;
  (* src = "libresoc.v:44318.3-44346.6" *)
  reg _0697_;
  (* src = "libresoc.v:44640.3-44668.6" *)
  reg _0698_;
  (* src = "libresoc.v:45107.3-45135.6" *)
  reg _0699_;
  (* src = "libresoc.v:45545.3-45573.6" *)
  reg _0700_;
  (* src = "libresoc.v:47151.3-47179.6" *)
  reg _0701_;
  (* src = "libresoc.v:47406.3-47434.6" *)
  reg [5:0] _0702_;
  (* src = "libresoc.v:47713.3-47741.6" *)
  reg [2:0] _0703_;
  (* src = "libresoc.v:48032.3-48060.6" *)
  reg [3:0] _0704_;
  (* src = "libresoc.v:43677.3-43705.6" *)
  reg [2:0] _0705_;
  (* src = "libresoc.v:43851.3-43879.6" *)
  reg [5:0] _0706_;
  (* src = "libresoc.v:44347.3-44375.6" *)
  reg [2:0] _0707_;
  (* src = "libresoc.v:44669.3-44697.6" *)
  reg [2:0] _0708_;
  (* src = "libresoc.v:45136.3-45164.6" *)
  reg [4:0] _0709_;
  (* src = "libresoc.v:45574.3-45602.6" *)
  reg [2:0] _0710_;
  (* src = "libresoc.v:47189.3-47217.6" *)
  reg [3:0] _0711_;
  (* src = "libresoc.v:47066.3-47094.6" *)
  reg [3:0] _0712_;
  (* src = "libresoc.v:46516.3-46544.6" *)
  reg [13:0] _0713_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg [63:0] _0714_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg _0715_;
  (* src = "libresoc.v:46896.3-46924.6" *)
  reg [1:0] _0716_;
  (* src = "libresoc.v:47104.3-47132.6" *)
  reg [31:0] _0717_;
  (* src = "libresoc.v:46449.3-46477.6" *)
  reg [6:0] _0718_;
  (* src = "libresoc.v:46735.3-46763.6" *)
  reg _0719_;
  (* src = "libresoc.v:46811.3-46839.6" *)
  reg _0720_;
  (* src = "libresoc.v:46981.3-47009.6" *)
  reg _0721_;
  (* src = "libresoc.v:47019.3-47047.6" *)
  reg _0722_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0723_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0724_;
  (* src = "libresoc.v:46943.3-46971.6" *)
  reg _0725_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0726_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0727_;
  (* src = "libresoc.v:46849.3-46877.6" *)
  reg _0728_;
  (* src = "libresoc.v:46773.3-46801.6" *)
  reg _0729_;
  (* src = "libresoc.v:47444.3-47472.6" *)
  reg [63:0] _0730_;
  (* src = "libresoc.v:47529.3-47557.6" *)
  reg [13:0] _0731_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg [63:0] _0732_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg _0733_;
  (* src = "libresoc.v:47567.3-47595.6" *)
  reg [31:0] _0734_;
  (* src = "libresoc.v:47482.3-47510.6" *)
  reg [6:0] _0735_;
  (* src = "libresoc.v:47655.3-47683.6" *)
  reg _0736_;
  (* src = "libresoc.v:47626.3-47654.6" *)
  reg _0737_;
  (* src = "libresoc.v:47274.3-47302.6" *)
  reg [13:0] _0738_;
  (* src = "libresoc.v:47321.3-47349.6" *)
  reg [31:0] _0739_;
  (* src = "libresoc.v:47236.3-47264.6" *)
  reg [6:0] _0740_;
  (* src = "libresoc.v:44260.3-44288.6" *)
  reg [3:0] _0741_;
  (* src = "libresoc.v:43909.3-43937.6" *)
  reg [13:0] _0742_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg [63:0] _0743_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg _0744_;
  (* src = "libresoc.v:44086.3-44114.6" *)
  reg [1:0] _0745_;
  (* src = "libresoc.v:44289.3-44317.6" *)
  reg [31:0] _0746_;
  (* src = "libresoc.v:43880.3-43908.6" *)
  reg [6:0] _0747_;
  (* src = "libresoc.v:44028.3-44056.6" *)
  reg _0748_;
  (* src = "libresoc.v:44115.3-44143.6" *)
  reg _0749_;
  (* src = "libresoc.v:44202.3-44230.6" *)
  reg _0750_;
  (* src = "libresoc.v:44231.3-44259.6" *)
  reg _0751_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0752_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0753_;
  (* src = "libresoc.v:44173.3-44201.6" *)
  reg _0754_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0755_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0756_;
  (* src = "libresoc.v:44144.3-44172.6" *)
  reg _0757_;
  (* src = "libresoc.v:44057.3-44085.6" *)
  reg _0758_;
  (* src = "libresoc.v:43590.3-43618.6" *)
  reg [3:0] _0759_;
  (* src = "libresoc.v:48090.3-48118.6" *)
  reg [13:0] _0760_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg [63:0] _0761_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg _0762_;
  (* src = "libresoc.v:48267.3-48295.6" *)
  reg [1:0] _0763_;
  (* src = "libresoc.v:43619.3-43647.6" *)
  reg [31:0] _0764_;
  (* src = "libresoc.v:48061.3-48089.6" *)
  reg [6:0] _0765_;
  (* src = "libresoc.v:48209.3-48237.6" *)
  reg _0766_;
  (* src = "libresoc.v:48296.3-48324.6" *)
  reg _0767_;
  (* src = "libresoc.v:43532.3-43560.6" *)
  reg _0768_;
  (* src = "libresoc.v:43561.3-43589.6" *)
  reg _0769_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0770_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0771_;
  (* src = "libresoc.v:43503.3-43531.6" *)
  reg _0772_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0773_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0774_;
  (* src = "libresoc.v:48325.3-48353.6" *)
  reg _0775_;
  (* src = "libresoc.v:48238.3-48266.6" *)
  reg _0776_;
  (* src = "libresoc.v:44405.3-44433.6" *)
  reg [13:0] _0777_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg [63:0] _0778_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg _0779_;
  (* src = "libresoc.v:44611.3-44639.6" *)
  reg [31:0] _0780_;
  (* src = "libresoc.v:44376.3-44404.6" *)
  reg [6:0] _0781_;
  (* src = "libresoc.v:44553.3-44581.6" *)
  reg _0782_;
  (* src = "libresoc.v:44582.3-44610.6" *)
  reg _0783_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0784_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0785_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0786_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0787_;
  (* src = "libresoc.v:44524.3-44552.6" *)
  reg _0788_;
  (* src = "libresoc.v:44727.3-44755.6" *)
  reg [13:0] _0789_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg [63:0] _0790_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg _0791_;
  (* src = "libresoc.v:44904.3-44932.6" *)
  reg [1:0] _0792_;
  (* src = "libresoc.v:44962.3-44990.6" *)
  reg _0793_;
  (* src = "libresoc.v:45078.3-45106.6" *)
  reg [31:0] _0794_;
  (* src = "libresoc.v:44698.3-44726.6" *)
  reg [6:0] _0795_;
  (* src = "libresoc.v:44875.3-44903.6" *)
  reg _0796_;
  (* src = "libresoc.v:45020.3-45048.6" *)
  reg _0797_;
  (* src = "libresoc.v:45049.3-45077.6" *)
  reg _0798_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0799_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0800_;
  (* src = "libresoc.v:44933.3-44961.6" *)
  reg _0801_;
  (* src = "libresoc.v:44991.3-45019.6" *)
  reg _0802_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0803_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0804_;
  (* src = "libresoc.v:44846.3-44874.6" *)
  reg _0805_;
  (* src = "libresoc.v:43735.3-43763.6" *)
  reg [13:0] _0806_;
  (* src = "libresoc.v:43764.3-43792.6" *)
  reg [31:0] _0807_;
  (* src = "libresoc.v:43706.3-43734.6" *)
  reg [6:0] _0808_;
  (* src = "libresoc.v:43793.3-43821.6" *)
  reg _0809_;
  (* src = "libresoc.v:47858.3-47886.6" *)
  reg [63:0] _0810_;
  (* src = "libresoc.v:47771.3-47799.6" *)
  reg [13:0] _0811_;
  (* src = "libresoc.v:47800.3-47828.6" *)
  reg [31:0] _0812_;
  (* src = "libresoc.v:47742.3-47770.6" *)
  reg [6:0] _0813_;
  (* src = "libresoc.v:47887.3-47915.6" *)
  reg _0814_;
  (* src = "libresoc.v:47974.3-48002.6" *)
  reg [7:0] _0815_;
  (* src = "libresoc.v:47829.3-47857.6" *)
  reg [63:0] _0816_;
  (* src = "libresoc.v:47945.3-47973.6" *)
  reg [12:0] _0817_;
  (* src = "libresoc.v:47916.3-47944.6" *)
  reg [7:0] _0818_;
  (* src = "libresoc.v:45429.3-45457.6" *)
  reg _0819_;
  (* src = "libresoc.v:45400.3-45428.6" *)
  reg [3:0] _0820_;
  (* src = "libresoc.v:45194.3-45222.6" *)
  reg [13:0] _0821_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg [63:0] _0822_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg _0823_;
  (* src = "libresoc.v:45516.3-45544.6" *)
  reg [31:0] _0824_;
  (* src = "libresoc.v:45165.3-45193.6" *)
  reg [6:0] _0825_;
  (* src = "libresoc.v:45342.3-45370.6" *)
  reg _0826_;
  (* src = "libresoc.v:45371.3-45399.6" *)
  reg _0827_;
  (* src = "libresoc.v:45487.3-45515.6" *)
  reg [1:0] _0828_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0829_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0830_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0831_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0832_;
  (* src = "libresoc.v:45458.3-45486.6" *)
  reg _0833_;
  (* src = "libresoc.v:45253.3-45281.6" *)
  reg _0834_;
  (* src = "libresoc.v:46390.3-46410.6" *)
  reg _0835_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0836_;
  (* src = "libresoc.v:46220.3-46250.6" *)
  reg [1:0] _0837_;
  (* src = "libresoc.v:47359.3-47387.6" *)
  reg _0838_;
  (* src = "libresoc.v:47684.3-47712.6" *)
  reg _0839_;
  (* src = "libresoc.v:48003.3-48031.6" *)
  reg _0840_;
  (* src = "libresoc.v:43648.3-43676.6" *)
  reg _0841_;
  (* src = "libresoc.v:43822.3-43850.6" *)
  reg _0842_;
  (* src = "libresoc.v:44318.3-44346.6" *)
  reg _0843_;
  (* src = "libresoc.v:44640.3-44668.6" *)
  reg _0844_;
  (* src = "libresoc.v:45107.3-45135.6" *)
  reg _0845_;
  (* src = "libresoc.v:45545.3-45573.6" *)
  reg _0846_;
  (* src = "libresoc.v:47151.3-47179.6" *)
  reg _0847_;
  (* src = "libresoc.v:47406.3-47434.6" *)
  reg [5:0] _0848_;
  (* src = "libresoc.v:47713.3-47741.6" *)
  reg [2:0] _0849_;
  (* src = "libresoc.v:48032.3-48060.6" *)
  reg [3:0] _0850_;
  (* src = "libresoc.v:43677.3-43705.6" *)
  reg [2:0] _0851_;
  (* src = "libresoc.v:43851.3-43879.6" *)
  reg [5:0] _0852_;
  (* src = "libresoc.v:44347.3-44375.6" *)
  reg [2:0] _0853_;
  (* src = "libresoc.v:44669.3-44697.6" *)
  reg [2:0] _0854_;
  (* src = "libresoc.v:45136.3-45164.6" *)
  reg [4:0] _0855_;
  (* src = "libresoc.v:45574.3-45602.6" *)
  reg [2:0] _0856_;
  (* src = "libresoc.v:47189.3-47217.6" *)
  reg [3:0] _0857_;
  (* src = "libresoc.v:47066.3-47094.6" *)
  reg [3:0] _0858_;
  (* src = "libresoc.v:46516.3-46544.6" *)
  reg [13:0] _0859_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg [63:0] _0860_;
  (* src = "libresoc.v:46564.3-46593.6" *)
  reg _0861_;
  (* src = "libresoc.v:46896.3-46924.6" *)
  reg [1:0] _0862_;
  (* src = "libresoc.v:47104.3-47132.6" *)
  reg [31:0] _0863_;
  (* src = "libresoc.v:46449.3-46477.6" *)
  reg [6:0] _0864_;
  (* src = "libresoc.v:46735.3-46763.6" *)
  reg _0865_;
  (* src = "libresoc.v:46811.3-46839.6" *)
  reg _0866_;
  (* src = "libresoc.v:46981.3-47009.6" *)
  reg _0867_;
  (* src = "libresoc.v:47019.3-47047.6" *)
  reg _0868_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0869_;
  (* src = "libresoc.v:46678.3-46707.6" *)
  reg _0870_;
  (* src = "libresoc.v:46943.3-46971.6" *)
  reg _0871_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0872_;
  (* src = "libresoc.v:46621.3-46650.6" *)
  reg _0873_;
  (* src = "libresoc.v:46849.3-46877.6" *)
  reg _0874_;
  (* src = "libresoc.v:46773.3-46801.6" *)
  reg _0875_;
  (* src = "libresoc.v:47444.3-47472.6" *)
  reg [63:0] _0876_;
  (* src = "libresoc.v:47529.3-47557.6" *)
  reg [13:0] _0877_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg [63:0] _0878_;
  (* src = "libresoc.v:47596.3-47625.6" *)
  reg _0879_;
  (* src = "libresoc.v:47567.3-47595.6" *)
  reg [31:0] _0880_;
  (* src = "libresoc.v:47482.3-47510.6" *)
  reg [6:0] _0881_;
  (* src = "libresoc.v:47655.3-47683.6" *)
  reg _0882_;
  (* src = "libresoc.v:47626.3-47654.6" *)
  reg _0883_;
  (* src = "libresoc.v:47274.3-47302.6" *)
  reg [13:0] _0884_;
  (* src = "libresoc.v:47321.3-47349.6" *)
  reg [31:0] _0885_;
  (* src = "libresoc.v:47236.3-47264.6" *)
  reg [6:0] _0886_;
  (* src = "libresoc.v:44260.3-44288.6" *)
  reg [3:0] _0887_;
  (* src = "libresoc.v:43909.3-43937.6" *)
  reg [13:0] _0888_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg [63:0] _0889_;
  (* src = "libresoc.v:43938.3-43967.6" *)
  reg _0890_;
  (* src = "libresoc.v:44086.3-44114.6" *)
  reg [1:0] _0891_;
  (* src = "libresoc.v:44289.3-44317.6" *)
  reg [31:0] _0892_;
  (* src = "libresoc.v:43880.3-43908.6" *)
  reg [6:0] _0893_;
  (* src = "libresoc.v:44028.3-44056.6" *)
  reg _0894_;
  (* src = "libresoc.v:44115.3-44143.6" *)
  reg _0895_;
  (* src = "libresoc.v:44202.3-44230.6" *)
  reg _0896_;
  (* src = "libresoc.v:44231.3-44259.6" *)
  reg _0897_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0898_;
  (* src = "libresoc.v:43998.3-44027.6" *)
  reg _0899_;
  (* src = "libresoc.v:44173.3-44201.6" *)
  reg _0900_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0901_;
  (* src = "libresoc.v:43968.3-43997.6" *)
  reg _0902_;
  (* src = "libresoc.v:44144.3-44172.6" *)
  reg _0903_;
  (* src = "libresoc.v:44057.3-44085.6" *)
  reg _0904_;
  (* src = "libresoc.v:43590.3-43618.6" *)
  reg [3:0] _0905_;
  (* src = "libresoc.v:48090.3-48118.6" *)
  reg [13:0] _0906_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg [63:0] _0907_;
  (* src = "libresoc.v:48119.3-48148.6" *)
  reg _0908_;
  (* src = "libresoc.v:48267.3-48295.6" *)
  reg [1:0] _0909_;
  (* src = "libresoc.v:43619.3-43647.6" *)
  reg [31:0] _0910_;
  (* src = "libresoc.v:48061.3-48089.6" *)
  reg [6:0] _0911_;
  (* src = "libresoc.v:48209.3-48237.6" *)
  reg _0912_;
  (* src = "libresoc.v:48296.3-48324.6" *)
  reg _0913_;
  (* src = "libresoc.v:43532.3-43560.6" *)
  reg _0914_;
  (* src = "libresoc.v:43561.3-43589.6" *)
  reg _0915_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0916_;
  (* src = "libresoc.v:48179.3-48208.6" *)
  reg _0917_;
  (* src = "libresoc.v:43503.3-43531.6" *)
  reg _0918_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0919_;
  (* src = "libresoc.v:48149.3-48178.6" *)
  reg _0920_;
  (* src = "libresoc.v:48325.3-48353.6" *)
  reg _0921_;
  (* src = "libresoc.v:48238.3-48266.6" *)
  reg _0922_;
  (* src = "libresoc.v:44405.3-44433.6" *)
  reg [13:0] _0923_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg [63:0] _0924_;
  (* src = "libresoc.v:44434.3-44463.6" *)
  reg _0925_;
  (* src = "libresoc.v:44611.3-44639.6" *)
  reg [31:0] _0926_;
  (* src = "libresoc.v:44376.3-44404.6" *)
  reg [6:0] _0927_;
  (* src = "libresoc.v:44553.3-44581.6" *)
  reg _0928_;
  (* src = "libresoc.v:44582.3-44610.6" *)
  reg _0929_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0930_;
  (* src = "libresoc.v:44494.3-44523.6" *)
  reg _0931_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0932_;
  (* src = "libresoc.v:44464.3-44493.6" *)
  reg _0933_;
  (* src = "libresoc.v:44524.3-44552.6" *)
  reg _0934_;
  (* src = "libresoc.v:44727.3-44755.6" *)
  reg [13:0] _0935_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg [63:0] _0936_;
  (* src = "libresoc.v:44756.3-44785.6" *)
  reg _0937_;
  (* src = "libresoc.v:44904.3-44932.6" *)
  reg [1:0] _0938_;
  (* src = "libresoc.v:44962.3-44990.6" *)
  reg _0939_;
  (* src = "libresoc.v:45078.3-45106.6" *)
  reg [31:0] _0940_;
  (* src = "libresoc.v:44698.3-44726.6" *)
  reg [6:0] _0941_;
  (* src = "libresoc.v:44875.3-44903.6" *)
  reg _0942_;
  (* src = "libresoc.v:45020.3-45048.6" *)
  reg _0943_;
  (* src = "libresoc.v:45049.3-45077.6" *)
  reg _0944_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0945_;
  (* src = "libresoc.v:44816.3-44845.6" *)
  reg _0946_;
  (* src = "libresoc.v:44933.3-44961.6" *)
  reg _0947_;
  (* src = "libresoc.v:44991.3-45019.6" *)
  reg _0948_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0949_;
  (* src = "libresoc.v:44786.3-44815.6" *)
  reg _0950_;
  (* src = "libresoc.v:44846.3-44874.6" *)
  reg _0951_;
  (* src = "libresoc.v:43735.3-43763.6" *)
  reg [13:0] _0952_;
  (* src = "libresoc.v:43764.3-43792.6" *)
  reg [31:0] _0953_;
  (* src = "libresoc.v:43706.3-43734.6" *)
  reg [6:0] _0954_;
  (* src = "libresoc.v:43793.3-43821.6" *)
  reg _0955_;
  (* src = "libresoc.v:47858.3-47886.6" *)
  reg [63:0] _0956_;
  (* src = "libresoc.v:47771.3-47799.6" *)
  reg [13:0] _0957_;
  (* src = "libresoc.v:47800.3-47828.6" *)
  reg [31:0] _0958_;
  (* src = "libresoc.v:47742.3-47770.6" *)
  reg [6:0] _0959_;
  (* src = "libresoc.v:47887.3-47915.6" *)
  reg _0960_;
  (* src = "libresoc.v:47974.3-48002.6" *)
  reg [7:0] _0961_;
  (* src = "libresoc.v:47829.3-47857.6" *)
  reg [63:0] _0962_;
  (* src = "libresoc.v:47945.3-47973.6" *)
  reg [12:0] _0963_;
  (* src = "libresoc.v:47916.3-47944.6" *)
  reg [7:0] _0964_;
  (* src = "libresoc.v:45429.3-45457.6" *)
  reg _0965_;
  (* src = "libresoc.v:45400.3-45428.6" *)
  reg [3:0] _0966_;
  (* src = "libresoc.v:45194.3-45222.6" *)
  reg [13:0] _0967_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg [63:0] _0968_;
  (* src = "libresoc.v:45223.3-45252.6" *)
  reg _0969_;
  (* src = "libresoc.v:45516.3-45544.6" *)
  reg [31:0] _0970_;
  (* src = "libresoc.v:45165.3-45193.6" *)
  reg [6:0] _0971_;
  (* src = "libresoc.v:45342.3-45370.6" *)
  reg _0972_;
  (* src = "libresoc.v:45371.3-45399.6" *)
  reg _0973_;
  (* src = "libresoc.v:45487.3-45515.6" *)
  reg [1:0] _0974_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0975_;
  (* src = "libresoc.v:45312.3-45341.6" *)
  reg _0976_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0977_;
  (* src = "libresoc.v:45282.3-45311.6" *)
  reg _0978_;
  (* src = "libresoc.v:45458.3-45486.6" *)
  reg _0979_;
  (* src = "libresoc.v:45253.3-45281.6" *)
  reg _0980_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0981_;
  (* src = "libresoc.v:46220.3-46250.6" *)
  reg [1:0] _0982_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0983_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0984_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0985_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0986_;
  (* src = "libresoc.v:46280.3-46370.6" *)
  reg _0987_;
  (* src = "libresoc.v:41908.20-41908.122" *)
  wire _0988_;
  (* src = "libresoc.v:41909.20-41909.126" *)
  wire _0989_;
  (* src = "libresoc.v:41911.20-41911.110" *)
  wire _0990_;
  (* src = "libresoc.v:41912.20-41912.123" *)
  wire _0991_;
  (* src = "libresoc.v:41914.20-41914.122" *)
  wire _0992_;
  (* src = "libresoc.v:41915.20-41915.126" *)
  wire _0993_;
  (* src = "libresoc.v:41917.20-41917.110" *)
  wire _0994_;
  (* src = "libresoc.v:41918.20-41918.123" *)
  wire _0995_;
  (* src = "libresoc.v:41920.20-41920.123" *)
  wire _0996_;
  (* src = "libresoc.v:41921.20-41921.126" *)
  wire _0997_;
  (* src = "libresoc.v:41923.20-41923.110" *)
  wire _0998_;
  (* src = "libresoc.v:41924.20-41924.123" *)
  wire _0999_;
  (* src = "libresoc.v:41926.20-41926.123" *)
  wire _1000_;
  (* src = "libresoc.v:41927.20-41927.126" *)
  wire _1001_;
  (* src = "libresoc.v:41929.20-41929.110" *)
  wire _1002_;
  (* src = "libresoc.v:41930.20-41930.123" *)
  wire _1003_;
  (* src = "libresoc.v:41932.20-41932.123" *)
  wire _1004_;
  (* src = "libresoc.v:41933.20-41933.126" *)
  wire _1005_;
  (* src = "libresoc.v:41935.20-41935.110" *)
  wire _1006_;
  (* src = "libresoc.v:41936.20-41936.123" *)
  wire _1007_;
  (* src = "libresoc.v:41938.20-41938.123" *)
  wire _1008_;
  (* src = "libresoc.v:41939.20-41939.126" *)
  wire _1009_;
  (* src = "libresoc.v:41941.20-41941.110" *)
  wire _1010_;
  (* src = "libresoc.v:41942.20-41942.123" *)
  wire _1011_;
  (* src = "libresoc.v:41944.20-41944.113" *)
  wire _1012_;
  (* src = "libresoc.v:41945.20-41945.126" *)
  wire _1013_;
  (* src = "libresoc.v:41947.20-41947.110" *)
  wire _1014_;
  (* src = "libresoc.v:41948.20-41948.123" *)
  wire _1015_;
  (* src = "libresoc.v:41950.20-41950.114" *)
  wire _1016_;
  (* src = "libresoc.v:41951.20-41951.126" *)
  wire _1017_;
  (* src = "libresoc.v:41953.20-41953.110" *)
  wire _1018_;
  (* src = "libresoc.v:41954.20-41954.123" *)
  wire _1019_;
  (* src = "libresoc.v:41983.20-41983.123" *)
  wire _1020_;
  (* src = "libresoc.v:41984.20-41984.128" *)
  wire _1021_;
  (* src = "libresoc.v:41985.20-41985.133" *)
  wire _1022_;
  (* src = "libresoc.v:41987.20-41987.110" *)
  wire _1023_;
  (* src = "libresoc.v:41988.20-41988.128" *)
  wire _1024_;
  (* src = "libresoc.v:41990.20-41990.116" *)
  wire _1025_;
  (* src = "libresoc.v:41991.20-41991.123" *)
  wire _1026_;
  (* src = "libresoc.v:41992.20-41992.128" *)
  wire _1027_;
  (* src = "libresoc.v:41993.20-41993.128" *)
  wire _1028_;
  (* src = "libresoc.v:41994.20-41994.129" *)
  wire _1029_;
  (* src = "libresoc.v:41995.20-41995.129" *)
  wire _1030_;
  (* src = "libresoc.v:41996.20-41996.129" *)
  wire _1031_;
  (* src = "libresoc.v:41997.20-41997.130" *)
  wire _1032_;
  (* src = "libresoc.v:41999.20-41999.110" *)
  wire _1033_;
  (* src = "libresoc.v:42000.20-42000.125" *)
  wire _1034_;
  (* src = "libresoc.v:42004.20-42004.126" *)
  wire _1035_;
  (* src = "libresoc.v:42005.20-42005.130" *)
  wire _1036_;
  (* src = "libresoc.v:42007.20-42007.110" *)
  wire _1037_;
  (* src = "libresoc.v:42008.20-42008.125" *)
  wire _1038_;
  (* src = "libresoc.v:42012.20-42012.126" *)
  wire _1039_;
  (* src = "libresoc.v:42013.20-42013.130" *)
  wire _1040_;
  (* src = "libresoc.v:42015.20-42015.110" *)
  wire _1041_;
  (* src = "libresoc.v:42016.20-42016.125" *)
  wire _1042_;
  (* src = "libresoc.v:42020.20-42020.126" *)
  wire _1043_;
  (* src = "libresoc.v:42021.20-42021.130" *)
  wire _1044_;
  (* src = "libresoc.v:42023.20-42023.110" *)
  wire _1045_;
  (* src = "libresoc.v:42024.20-42024.125" *)
  wire _1046_;
  (* src = "libresoc.v:42028.20-42028.126" *)
  wire _1047_;
  (* src = "libresoc.v:42029.20-42029.130" *)
  wire _1048_;
  (* src = "libresoc.v:42031.20-42031.110" *)
  wire _1049_;
  (* src = "libresoc.v:42032.20-42032.125" *)
  wire _1050_;
  (* src = "libresoc.v:42036.20-42036.126" *)
  wire _1051_;
  (* src = "libresoc.v:42037.20-42037.130" *)
  wire _1052_;
  (* src = "libresoc.v:42039.20-42039.110" *)
  wire _1053_;
  (* src = "libresoc.v:42040.20-42040.125" *)
  wire _1054_;
  (* src = "libresoc.v:42054.20-42054.118" *)
  wire _1055_;
  (* src = "libresoc.v:42055.20-42055.123" *)
  wire _1056_;
  (* src = "libresoc.v:42056.20-42056.129" *)
  wire _1057_;
  (* src = "libresoc.v:42057.20-42057.129" *)
  wire _1058_;
  (* src = "libresoc.v:42058.20-42058.136" *)
  wire _1059_;
  (* src = "libresoc.v:42060.20-42060.110" *)
  wire _1060_;
  (* src = "libresoc.v:42061.20-42061.128" *)
  wire _1061_;
  (* src = "libresoc.v:42063.20-42063.128" *)
  wire _1062_;
  (* src = "libresoc.v:42064.20-42064.136" *)
  wire _1063_;
  (* src = "libresoc.v:42066.20-42066.110" *)
  wire _1064_;
  (* src = "libresoc.v:42067.20-42067.128" *)
  wire _1065_;
  (* src = "libresoc.v:42069.20-42069.128" *)
  wire _1066_;
  (* src = "libresoc.v:42070.20-42070.136" *)
  wire _1067_;
  (* src = "libresoc.v:42072.20-42072.110" *)
  wire _1068_;
  (* src = "libresoc.v:42073.20-42073.128" *)
  wire _1069_;
  (* src = "libresoc.v:42080.20-42080.118" *)
  wire _1070_;
  (* src = "libresoc.v:42081.20-42081.123" *)
  wire _1071_;
  (* src = "libresoc.v:42082.20-42082.129" *)
  wire _1072_;
  (* src = "libresoc.v:42083.20-42083.129" *)
  wire _1073_;
  (* src = "libresoc.v:42084.20-42084.129" *)
  wire _1074_;
  (* src = "libresoc.v:42085.20-42085.136" *)
  wire _1075_;
  (* src = "libresoc.v:42087.20-42087.110" *)
  wire _1076_;
  (* src = "libresoc.v:42088.20-42088.128" *)
  wire _1077_;
  (* src = "libresoc.v:42090.20-42090.128" *)
  wire _1078_;
  (* src = "libresoc.v:42091.20-42091.136" *)
  wire _1079_;
  (* src = "libresoc.v:42093.20-42093.110" *)
  wire _1080_;
  (* src = "libresoc.v:42094.20-42094.128" *)
  wire _1081_;
  (* src = "libresoc.v:42096.20-42096.128" *)
  wire _1082_;
  (* src = "libresoc.v:42097.20-42097.136" *)
  wire _1083_;
  (* src = "libresoc.v:42099.20-42099.110" *)
  wire _1084_;
  (* src = "libresoc.v:42100.20-42100.128" *)
  wire _1085_;
  (* src = "libresoc.v:42102.20-42102.128" *)
  wire _1086_;
  (* src = "libresoc.v:42103.20-42103.136" *)
  wire _1087_;
  (* src = "libresoc.v:42105.20-42105.110" *)
  wire _1088_;
  (* src = "libresoc.v:42106.20-42106.128" *)
  wire _1089_;
  (* src = "libresoc.v:42114.20-42114.118" *)
  wire _1090_;
  (* src = "libresoc.v:42115.20-42115.123" *)
  wire _1091_;
  (* src = "libresoc.v:42116.20-42116.129" *)
  wire _1092_;
  (* src = "libresoc.v:42117.20-42117.129" *)
  wire _1093_;
  (* src = "libresoc.v:42118.20-42118.129" *)
  wire _1094_;
  (* src = "libresoc.v:42119.20-42119.136" *)
  wire _1095_;
  (* src = "libresoc.v:42121.20-42121.110" *)
  wire _1096_;
  (* src = "libresoc.v:42122.20-42122.128" *)
  wire _1097_;
  (* src = "libresoc.v:42124.20-42124.128" *)
  wire _1098_;
  (* src = "libresoc.v:42125.20-42125.136" *)
  wire _1099_;
  (* src = "libresoc.v:42127.20-42127.110" *)
  wire _1100_;
  (* src = "libresoc.v:42128.20-42128.128" *)
  wire _1101_;
  (* src = "libresoc.v:42130.20-42130.128" *)
  wire _1102_;
  (* src = "libresoc.v:42131.20-42131.136" *)
  wire _1103_;
  (* src = "libresoc.v:42133.20-42133.110" *)
  wire _1104_;
  (* src = "libresoc.v:42134.20-42134.128" *)
  wire _1105_;
  (* src = "libresoc.v:42136.20-42136.128" *)
  wire _1106_;
  (* src = "libresoc.v:42137.20-42137.136" *)
  wire _1107_;
  (* src = "libresoc.v:42139.20-42139.110" *)
  wire _1108_;
  (* src = "libresoc.v:42140.20-42140.128" *)
  wire _1109_;
  (* src = "libresoc.v:42150.20-42150.121" *)
  wire _1110_;
  (* src = "libresoc.v:42151.20-42151.129" *)
  wire _1111_;
  (* src = "libresoc.v:42152.20-42152.128" *)
  wire _1112_;
  (* src = "libresoc.v:42153.20-42153.129" *)
  wire _1113_;
  (* src = "libresoc.v:42154.20-42154.129" *)
  wire _1114_;
  (* src = "libresoc.v:42155.20-42155.128" *)
  wire _1115_;
  (* src = "libresoc.v:42156.20-42156.136" *)
  wire _1116_;
  (* src = "libresoc.v:42158.20-42158.110" *)
  wire _1117_;
  (* src = "libresoc.v:42159.20-42159.128" *)
  wire _1118_;
  (* src = "libresoc.v:42161.20-42161.127" *)
  wire _1119_;
  (* src = "libresoc.v:42162.20-42162.136" *)
  wire _1120_;
  (* src = "libresoc.v:42164.20-42164.110" *)
  wire _1121_;
  (* src = "libresoc.v:42165.20-42165.128" *)
  wire _1122_;
  (* src = "libresoc.v:42167.20-42167.127" *)
  wire _1123_;
  (* src = "libresoc.v:42168.20-42168.136" *)
  wire _1124_;
  (* src = "libresoc.v:42170.20-42170.110" *)
  wire _1125_;
  (* src = "libresoc.v:42171.20-42171.128" *)
  wire _1126_;
  (* src = "libresoc.v:42173.20-42173.121" *)
  wire _1127_;
  (* src = "libresoc.v:42174.20-42174.136" *)
  wire _1128_;
  (* src = "libresoc.v:42176.20-42176.110" *)
  wire _1129_;
  (* src = "libresoc.v:42177.20-42177.128" *)
  wire _1130_;
  (* src = "libresoc.v:42179.20-42179.127" *)
  wire _1131_;
  (* src = "libresoc.v:42180.20-42180.136" *)
  wire _1132_;
  (* src = "libresoc.v:42182.20-42182.110" *)
  wire _1133_;
  (* src = "libresoc.v:42183.20-42183.128" *)
  wire _1134_;
  (* src = "libresoc.v:42197.20-42197.119" *)
  wire _1135_;
  (* src = "libresoc.v:42198.20-42198.129" *)
  wire _1136_;
  (* src = "libresoc.v:42199.20-42199.128" *)
  wire _1137_;
  (* src = "libresoc.v:42200.20-42200.134" *)
  wire _1138_;
  (* src = "libresoc.v:42202.20-42202.110" *)
  wire _1139_;
  (* src = "libresoc.v:42203.20-42203.127" *)
  wire _1140_;
  (* src = "libresoc.v:42205.20-42205.125" *)
  wire _1141_;
  (* src = "libresoc.v:42206.20-42206.134" *)
  wire _1142_;
  (* src = "libresoc.v:42208.20-42208.110" *)
  wire _1143_;
  (* src = "libresoc.v:42209.20-42209.127" *)
  wire _1144_;
  (* src = "libresoc.v:42214.20-42214.119" *)
  wire _1145_;
  (* src = "libresoc.v:42215.20-42215.128" *)
  wire _1146_;
  (* src = "libresoc.v:42216.20-42216.131" *)
  wire _1147_;
  (* src = "libresoc.v:42218.20-42218.110" *)
  wire _1148_;
  (* src = "libresoc.v:42219.20-42219.127" *)
  wire _1149_;
  (* src = "libresoc.v:42222.20-42222.120" *)
  wire _1150_;
  (* src = "libresoc.v:42223.20-42223.129" *)
  wire _1151_;
  (* src = "libresoc.v:42224.20-42224.129" *)
  wire _1152_;
  (* src = "libresoc.v:42226.20-42226.110" *)
  wire _1153_;
  (* src = "libresoc.v:42227.20-42227.126" *)
  wire _1154_;
  (* src = "libresoc.v:42229.19-42229.112" *)
  wire [13:0] _1155_;
  (* src = "libresoc.v:42231.19-42231.113" *)
  wire [13:0] _1156_;
  (* src = "libresoc.v:42233.19-42233.113" *)
  wire [13:0] _1157_;
  (* src = "libresoc.v:42235.19-42235.113" *)
  wire [13:0] _1158_;
  (* src = "libresoc.v:42237.19-42237.113" *)
  wire [13:0] _1159_;
  (* src = "libresoc.v:42239.19-42239.115" *)
  wire [13:0] _1160_;
  (* src = "libresoc.v:42241.19-42241.115" *)
  wire [13:0] _1161_;
  (* src = "libresoc.v:42243.19-42243.114" *)
  wire [13:0] _1162_;
  (* src = "libresoc.v:42245.19-42245.112" *)
  wire [13:0] _1163_;
  (* src = "libresoc.v:42247.19-42247.112" *)
  wire [13:0] _1164_;
  (* src = "libresoc.v:42252.19-42252.131" *)
  wire _1165_;
  (* src = "libresoc.v:42253.19-42253.119" *)
  wire [2:0] _1166_;
  (* src = "libresoc.v:42256.19-42256.131" *)
  wire _1167_;
  (* src = "libresoc.v:42259.19-42259.119" *)
  wire [2:0] _1168_;
  (* src = "libresoc.v:42266.19-42266.131" *)
  wire _1169_;
  (* src = "libresoc.v:42267.19-42267.119" *)
  wire [2:0] _1170_;
  (* src = "libresoc.v:42270.19-42270.131" *)
  wire _1171_;
  (* src = "libresoc.v:42273.19-42273.131" *)
  wire _1172_;
  (* src = "libresoc.v:42274.19-42274.119" *)
  wire [2:0] _1173_;
  (* src = "libresoc.v:42277.19-42277.131" *)
  wire _1174_;
  (* src = "libresoc.v:42279.19-42279.131" *)
  wire _1175_;
  (* src = "libresoc.v:42280.19-42280.119" *)
  wire [2:0] _1176_;
  (* src = "libresoc.v:42284.19-42284.119" *)
  wire [2:0] _1177_;
  (* src = "libresoc.v:42288.19-42288.131" *)
  wire _1178_;
  (* src = "libresoc.v:42289.19-42289.119" *)
  wire [2:0] _1179_;
  (* src = "libresoc.v:42292.19-42292.131" *)
  wire _1180_;
  (* src = "libresoc.v:42295.19-42295.131" *)
  wire _1181_;
  (* src = "libresoc.v:42296.19-42296.119" *)
  wire [2:0] _1182_;
  (* src = "libresoc.v:42299.19-42299.131" *)
  wire _1183_;
  (* src = "libresoc.v:42302.19-42302.131" *)
  wire _1184_;
  (* src = "libresoc.v:42303.19-42303.119" *)
  wire [2:0] _1185_;
  (* src = "libresoc.v:42306.19-42306.131" *)
  wire _1186_;
  (* src = "libresoc.v:42309.19-42309.119" *)
  wire [2:0] _1187_;
  (* src = "libresoc.v:42314.19-42314.122" *)
  wire _1188_;
  (* src = "libresoc.v:42315.19-42315.114" *)
  wire _1189_;
  (* src = "libresoc.v:42317.19-42317.102" *)
  wire _1190_;
  (* src = "libresoc.v:42318.19-42318.131" *)
  wire _1191_;
  (* src = "libresoc.v:42320.19-42320.127" *)
  wire _1192_;
  (* src = "libresoc.v:42321.19-42321.114" *)
  wire _1193_;
  (* src = "libresoc.v:42323.19-42323.102" *)
  wire _1194_;
  (* src = "libresoc.v:42324.19-42324.131" *)
  wire _1195_;
  (* src = "libresoc.v:42326.19-42326.127" *)
  wire _1196_;
  (* src = "libresoc.v:42327.19-42327.114" *)
  wire _1197_;
  (* src = "libresoc.v:42329.19-42329.102" *)
  wire _1198_;
  (* src = "libresoc.v:42330.19-42330.131" *)
  wire _1199_;
  (* src = "libresoc.v:42332.19-42332.127" *)
  wire _1200_;
  (* src = "libresoc.v:42333.19-42333.114" *)
  wire _1201_;
  (* src = "libresoc.v:42335.19-42335.102" *)
  wire _1202_;
  (* src = "libresoc.v:42336.19-42336.131" *)
  wire _1203_;
  (* src = "libresoc.v:42338.19-42338.127" *)
  wire _1204_;
  (* src = "libresoc.v:42339.19-42339.114" *)
  wire _1205_;
  (* src = "libresoc.v:42341.19-42341.102" *)
  wire _1206_;
  (* src = "libresoc.v:42342.19-42342.131" *)
  wire _1207_;
  (* src = "libresoc.v:42344.19-42344.127" *)
  wire _1208_;
  (* src = "libresoc.v:42345.19-42345.114" *)
  wire _1209_;
  (* src = "libresoc.v:42347.19-42347.102" *)
  wire _1210_;
  (* src = "libresoc.v:42348.19-42348.131" *)
  wire _1211_;
  (* src = "libresoc.v:42350.19-42350.127" *)
  wire _1212_;
  (* src = "libresoc.v:42351.19-42351.114" *)
  wire _1213_;
  (* src = "libresoc.v:42353.19-42353.102" *)
  wire _1214_;
  (* src = "libresoc.v:42354.19-42354.131" *)
  wire _1215_;
  (* src = "libresoc.v:42356.19-42356.127" *)
  wire _1216_;
  (* src = "libresoc.v:42357.19-42357.114" *)
  wire _1217_;
  (* src = "libresoc.v:42359.19-42359.102" *)
  wire _1218_;
  (* src = "libresoc.v:42360.19-42360.131" *)
  wire _1219_;
  (* src = "libresoc.v:42362.19-42362.127" *)
  wire _1220_;
  (* src = "libresoc.v:42363.19-42363.114" *)
  wire _1221_;
  (* src = "libresoc.v:42365.19-42365.102" *)
  wire _1222_;
  (* src = "libresoc.v:42366.19-42366.131" *)
  wire _1223_;
  (* src = "libresoc.v:42368.19-42368.127" *)
  wire _1224_;
  (* src = "libresoc.v:42369.19-42369.114" *)
  wire _1225_;
  (* src = "libresoc.v:42371.19-42371.102" *)
  wire _1226_;
  (* src = "libresoc.v:42372.19-42372.131" *)
  wire _1227_;
  (* src = "libresoc.v:42374.19-42374.122" *)
  wire _1228_;
  (* src = "libresoc.v:42375.19-42375.114" *)
  wire _1229_;
  (* src = "libresoc.v:42377.19-42377.102" *)
  wire _1230_;
  (* src = "libresoc.v:42378.19-42378.132" *)
  wire _1231_;
  (* src = "libresoc.v:42380.19-42380.127" *)
  wire _1232_;
  (* src = "libresoc.v:42381.19-42381.114" *)
  wire _1233_;
  (* src = "libresoc.v:42383.19-42383.102" *)
  wire _1234_;
  (* src = "libresoc.v:42384.19-42384.132" *)
  wire _1235_;
  (* src = "libresoc.v:42386.19-42386.127" *)
  wire _1236_;
  (* src = "libresoc.v:42387.19-42387.114" *)
  wire _1237_;
  (* src = "libresoc.v:42389.19-42389.102" *)
  wire _1238_;
  (* src = "libresoc.v:42390.19-42390.132" *)
  wire _1239_;
  (* src = "libresoc.v:42392.19-42392.127" *)
  wire _1240_;
  (* src = "libresoc.v:42393.19-42393.114" *)
  wire _1241_;
  (* src = "libresoc.v:42395.19-42395.102" *)
  wire _1242_;
  (* src = "libresoc.v:42396.19-42396.132" *)
  wire _1243_;
  (* src = "libresoc.v:42398.19-42398.127" *)
  wire _1244_;
  (* src = "libresoc.v:42399.19-42399.114" *)
  wire _1245_;
  (* src = "libresoc.v:42401.19-42401.102" *)
  wire _1246_;
  (* src = "libresoc.v:42402.19-42402.132" *)
  wire _1247_;
  (* src = "libresoc.v:42404.19-42404.127" *)
  wire _1248_;
  (* src = "libresoc.v:42405.19-42405.114" *)
  wire _1249_;
  (* src = "libresoc.v:42407.19-42407.102" *)
  wire _1250_;
  (* src = "libresoc.v:42408.19-42408.132" *)
  wire _1251_;
  (* src = "libresoc.v:42410.19-42410.127" *)
  wire _1252_;
  (* src = "libresoc.v:42411.19-42411.114" *)
  wire _1253_;
  (* src = "libresoc.v:42413.19-42413.102" *)
  wire _1254_;
  (* src = "libresoc.v:42414.19-42414.132" *)
  wire _1255_;
  (* src = "libresoc.v:42416.19-42416.127" *)
  wire _1256_;
  (* src = "libresoc.v:42417.19-42417.114" *)
  wire _1257_;
  (* src = "libresoc.v:42419.19-42419.102" *)
  wire _1258_;
  (* src = "libresoc.v:42420.19-42420.132" *)
  wire _1259_;
  (* src = "libresoc.v:42422.19-42422.127" *)
  wire _1260_;
  (* src = "libresoc.v:42423.19-42423.114" *)
  wire _1261_;
  (* src = "libresoc.v:42425.19-42425.102" *)
  wire _1262_;
  (* src = "libresoc.v:42426.19-42426.132" *)
  wire _1263_;
  (* src = "libresoc.v:42447.19-42447.131" *)
  wire _1264_;
  (* src = "libresoc.v:42448.19-42448.119" *)
  wire [2:0] _1265_;
  (* src = "libresoc.v:42451.19-42451.131" *)
  wire _1266_;
  (* src = "libresoc.v:42453.19-42453.122" *)
  wire _1267_;
  (* src = "libresoc.v:42454.19-42454.116" *)
  wire _1268_;
  (* src = "libresoc.v:42456.19-42456.102" *)
  wire _1269_;
  (* src = "libresoc.v:42457.19-42457.135" *)
  wire _1270_;
  (* src = "libresoc.v:42459.19-42459.127" *)
  wire _1271_;
  (* src = "libresoc.v:42460.19-42460.116" *)
  wire _1272_;
  (* src = "libresoc.v:42462.19-42462.102" *)
  wire _1273_;
  (* src = "libresoc.v:42463.19-42463.135" *)
  wire _1274_;
  (* src = "libresoc.v:42465.19-42465.127" *)
  wire _1275_;
  (* src = "libresoc.v:42466.19-42466.116" *)
  wire _1276_;
  (* src = "libresoc.v:42468.19-42468.102" *)
  wire _1277_;
  (* src = "libresoc.v:42469.19-42469.135" *)
  wire _1278_;
  (* src = "libresoc.v:42471.19-42471.127" *)
  wire _1279_;
  (* src = "libresoc.v:42472.19-42472.116" *)
  wire _1280_;
  (* src = "libresoc.v:42474.19-42474.102" *)
  wire _1281_;
  (* src = "libresoc.v:42475.19-42475.135" *)
  wire _1282_;
  (* src = "libresoc.v:42477.19-42477.127" *)
  wire _1283_;
  (* src = "libresoc.v:42478.19-42478.116" *)
  wire _1284_;
  (* src = "libresoc.v:42480.19-42480.102" *)
  wire _1285_;
  (* src = "libresoc.v:42481.19-42481.135" *)
  wire _1286_;
  (* src = "libresoc.v:42483.19-42483.127" *)
  wire _1287_;
  (* src = "libresoc.v:42484.19-42484.116" *)
  wire _1288_;
  (* src = "libresoc.v:42486.19-42486.102" *)
  wire _1289_;
  (* src = "libresoc.v:42487.19-42487.135" *)
  wire _1290_;
  (* src = "libresoc.v:42496.19-42496.119" *)
  wire [2:0] _1291_;
  (* src = "libresoc.v:42499.19-42499.122" *)
  wire _1292_;
  (* src = "libresoc.v:42500.19-42500.116" *)
  wire _1293_;
  (* src = "libresoc.v:42502.19-42502.102" *)
  wire _1294_;
  (* src = "libresoc.v:42503.19-42503.135" *)
  wire _1295_;
  (* src = "libresoc.v:42505.19-42505.127" *)
  wire _1296_;
  (* src = "libresoc.v:42506.19-42506.116" *)
  wire _1297_;
  (* src = "libresoc.v:42508.19-42508.102" *)
  wire _1298_;
  (* src = "libresoc.v:42509.19-42509.135" *)
  wire _1299_;
  (* src = "libresoc.v:42511.19-42511.127" *)
  wire _1300_;
  (* src = "libresoc.v:42512.19-42512.116" *)
  wire _1301_;
  (* src = "libresoc.v:42514.19-42514.102" *)
  wire _1302_;
  (* src = "libresoc.v:42515.19-42515.135" *)
  wire _1303_;
  (* src = "libresoc.v:42520.19-42520.131" *)
  wire _1304_;
  (* src = "libresoc.v:42521.19-42521.119" *)
  wire [2:0] _1305_;
  (* src = "libresoc.v:42524.19-42524.127" *)
  wire _1306_;
  (* src = "libresoc.v:42525.19-42525.116" *)
  wire _1307_;
  (* src = "libresoc.v:42527.19-42527.102" *)
  wire _1308_;
  (* src = "libresoc.v:42528.19-42528.132" *)
  wire _1309_;
  (* src = "libresoc.v:42530.19-42530.127" *)
  wire _1310_;
  (* src = "libresoc.v:42531.19-42531.116" *)
  wire _1311_;
  (* src = "libresoc.v:42533.19-42533.102" *)
  wire _1312_;
  (* src = "libresoc.v:42534.19-42534.132" *)
  wire _1313_;
  (* src = "libresoc.v:42536.19-42536.127" *)
  wire _1314_;
  (* src = "libresoc.v:42537.19-42537.113" *)
  wire _1315_;
  (* src = "libresoc.v:42539.19-42539.102" *)
  wire _1316_;
  (* src = "libresoc.v:42540.19-42540.129" *)
  wire _1317_;
  (* src = "libresoc.v:42544.19-42544.127" *)
  wire _1318_;
  (* src = "libresoc.v:42545.19-42545.113" *)
  wire _1319_;
  (* src = "libresoc.v:42547.19-42547.102" *)
  wire _1320_;
  (* src = "libresoc.v:42548.19-42548.129" *)
  wire _1321_;
  (* src = "libresoc.v:42553.19-42553.127" *)
  wire _1322_;
  (* src = "libresoc.v:42554.19-42554.113" *)
  wire _1323_;
  (* src = "libresoc.v:42556.19-42556.102" *)
  wire _1324_;
  (* src = "libresoc.v:42557.19-42557.126" *)
  wire _1325_;
  (* src = "libresoc.v:42561.19-42561.127" *)
  wire _1326_;
  (* src = "libresoc.v:42562.19-42562.113" *)
  wire _1327_;
  (* src = "libresoc.v:42564.19-42564.102" *)
  wire _1328_;
  (* src = "libresoc.v:42565.19-42565.126" *)
  wire _1329_;
  (* src = "libresoc.v:42569.19-42569.127" *)
  wire _1330_;
  (* src = "libresoc.v:42570.19-42570.116" *)
  wire _1331_;
  (* src = "libresoc.v:42572.19-42572.102" *)
  wire _1332_;
  (* src = "libresoc.v:42573.19-42573.135" *)
  wire _1333_;
  (* src = "libresoc.v:42575.19-42575.127" *)
  wire _1334_;
  (* src = "libresoc.v:42576.19-42576.116" *)
  wire _1335_;
  (* src = "libresoc.v:42578.19-42578.102" *)
  wire _1336_;
  (* src = "libresoc.v:42579.19-42579.135" *)
  wire _1337_;
  (* src = "libresoc.v:42581.19-42581.127" *)
  wire _1338_;
  (* src = "libresoc.v:42582.19-42582.116" *)
  wire _1339_;
  (* src = "libresoc.v:42584.19-42584.102" *)
  wire _1340_;
  (* src = "libresoc.v:42585.19-42585.135" *)
  wire _1341_;
  (* src = "libresoc.v:42587.19-42587.127" *)
  wire _1342_;
  (* src = "libresoc.v:42588.19-42588.116" *)
  wire _1343_;
  (* src = "libresoc.v:42590.19-42590.102" *)
  wire _1344_;
  (* src = "libresoc.v:42591.19-42591.135" *)
  wire _1345_;
  (* src = "libresoc.v:42593.19-42593.127" *)
  wire _1346_;
  (* src = "libresoc.v:42594.19-42594.116" *)
  wire _1347_;
  (* src = "libresoc.v:42596.19-42596.102" *)
  wire _1348_;
  (* src = "libresoc.v:42597.19-42597.135" *)
  wire _1349_;
  (* src = "libresoc.v:42604.19-42604.127" *)
  wire _1350_;
  (* src = "libresoc.v:42605.19-42605.114" *)
  wire _1351_;
  (* src = "libresoc.v:42607.19-42607.102" *)
  wire _1352_;
  (* src = "libresoc.v:42608.19-42608.128" *)
  wire _1353_;
  (* src = "libresoc.v:42611.19-42611.112" *)
  wire _1354_;
  (* src = "libresoc.v:42612.19-42612.122" *)
  wire _1355_;
  (* src = "libresoc.v:42613.19-42613.127" *)
  wire _1356_;
  (* src = "libresoc.v:42614.19-42614.127" *)
  wire _1357_;
  (* src = "libresoc.v:42615.19-42615.127" *)
  wire _1358_;
  (* src = "libresoc.v:42616.19-42616.128" *)
  wire _1359_;
  (* src = "libresoc.v:42617.19-42617.128" *)
  wire _1360_;
  (* src = "libresoc.v:42618.19-42618.128" *)
  wire _1361_;
  (* src = "libresoc.v:42619.19-42619.128" *)
  wire _1362_;
  (* src = "libresoc.v:42620.19-42620.128" *)
  wire _1363_;
  (* src = "libresoc.v:42621.19-42621.128" *)
  wire _1364_;
  (* src = "libresoc.v:42622.19-42622.125" *)
  wire _1365_;
  (* src = "libresoc.v:42624.19-42624.101" *)
  wire _1366_;
  (* src = "libresoc.v:42625.19-42625.115" *)
  wire _1367_;
  (* src = "libresoc.v:42627.19-42627.121" *)
  wire _1368_;
  (* src = "libresoc.v:42628.19-42628.125" *)
  wire _1369_;
  (* src = "libresoc.v:42630.19-42630.107" *)
  wire _1370_;
  (* src = "libresoc.v:42631.19-42631.121" *)
  wire _1371_;
  (* src = "libresoc.v:42254.19-42254.115" *)
  wire _1372_;
  (* src = "libresoc.v:42258.19-42258.130" *)
  wire _1373_;
  (* src = "libresoc.v:42260.19-42260.115" *)
  wire _1374_;
  (* src = "libresoc.v:42268.19-42268.115" *)
  wire _1375_;
  (* src = "libresoc.v:42275.19-42275.115" *)
  wire _1376_;
  (* src = "libresoc.v:42281.19-42281.115" *)
  wire _1377_;
  (* src = "libresoc.v:42283.19-42283.130" *)
  wire _1378_;
  (* src = "libresoc.v:42285.19-42285.115" *)
  wire _1379_;
  (* src = "libresoc.v:42290.19-42290.115" *)
  wire _1380_;
  (* src = "libresoc.v:42297.19-42297.115" *)
  wire _1381_;
  (* src = "libresoc.v:42304.19-42304.115" *)
  wire _1382_;
  (* src = "libresoc.v:42308.19-42308.130" *)
  wire _1383_;
  (* src = "libresoc.v:42310.19-42310.115" *)
  wire _1384_;
  (* src = "libresoc.v:42449.19-42449.115" *)
  wire _1385_;
  (* src = "libresoc.v:42495.19-42495.130" *)
  wire _1386_;
  (* src = "libresoc.v:42497.19-42497.115" *)
  wire _1387_;
  (* src = "libresoc.v:42522.19-42522.115" *)
  wire _1388_;
  (* src = "libresoc.v:42079.20-42079.95" *)
  wire [2:0] _1389_;
  (* src = "libresoc.v:42145.20-42145.95" *)
  wire [1:0] _1390_;
  (* src = "libresoc.v:42149.20-42149.95" *)
  wire [2:0] _1391_;
  (* src = "libresoc.v:42213.20-42213.95" *)
  wire [2:0] _1392_;
  (* src = "libresoc.v:42221.20-42221.104" *)
  wire [2:0] _1393_;
  (* src = "libresoc.v:42494.19-42494.93" *)
  wire [2:0] _1394_;
  (* src = "libresoc.v:42519.19-42519.93" *)
  wire [2:0] _1395_;
  (* src = "libresoc.v:42249.19-42249.103" *)
  wire _1396_;
  (* src = "libresoc.v:42251.19-42251.103" *)
  wire _1397_;
  (* src = "libresoc.v:41910.20-41910.106" *)
  wire _1398_;
  (* src = "libresoc.v:41916.20-41916.106" *)
  wire _1399_;
  (* src = "libresoc.v:41922.20-41922.106" *)
  wire _1400_;
  (* src = "libresoc.v:41928.20-41928.106" *)
  wire _1401_;
  (* src = "libresoc.v:41934.20-41934.106" *)
  wire _1402_;
  (* src = "libresoc.v:41940.20-41940.106" *)
  wire _1403_;
  (* src = "libresoc.v:41946.20-41946.106" *)
  wire _1404_;
  (* src = "libresoc.v:41952.20-41952.106" *)
  wire _1405_;
  (* src = "libresoc.v:41986.20-41986.106" *)
  wire _1406_;
  (* src = "libresoc.v:41998.20-41998.106" *)
  wire _1407_;
  (* src = "libresoc.v:42006.20-42006.106" *)
  wire _1408_;
  (* src = "libresoc.v:42014.20-42014.106" *)
  wire _1409_;
  (* src = "libresoc.v:42022.20-42022.106" *)
  wire _1410_;
  (* src = "libresoc.v:42030.20-42030.106" *)
  wire _1411_;
  (* src = "libresoc.v:42038.20-42038.106" *)
  wire _1412_;
  (* src = "libresoc.v:42059.20-42059.106" *)
  wire _1413_;
  (* src = "libresoc.v:42065.20-42065.106" *)
  wire _1414_;
  (* src = "libresoc.v:42071.20-42071.106" *)
  wire _1415_;
  (* src = "libresoc.v:42086.20-42086.106" *)
  wire _1416_;
  (* src = "libresoc.v:42092.20-42092.106" *)
  wire _1417_;
  (* src = "libresoc.v:42098.20-42098.106" *)
  wire _1418_;
  (* src = "libresoc.v:42104.20-42104.106" *)
  wire _1419_;
  (* src = "libresoc.v:42120.20-42120.106" *)
  wire _1420_;
  (* src = "libresoc.v:42126.20-42126.106" *)
  wire _1421_;
  (* src = "libresoc.v:42132.20-42132.106" *)
  wire _1422_;
  (* src = "libresoc.v:42138.20-42138.106" *)
  wire _1423_;
  (* src = "libresoc.v:42157.20-42157.106" *)
  wire _1424_;
  (* src = "libresoc.v:42163.20-42163.106" *)
  wire _1425_;
  (* src = "libresoc.v:42169.20-42169.106" *)
  wire _1426_;
  (* src = "libresoc.v:42175.20-42175.106" *)
  wire _1427_;
  (* src = "libresoc.v:42181.20-42181.106" *)
  wire _1428_;
  (* src = "libresoc.v:42201.20-42201.106" *)
  wire _1429_;
  (* src = "libresoc.v:42207.20-42207.106" *)
  wire _1430_;
  (* src = "libresoc.v:42217.20-42217.106" *)
  wire _1431_;
  (* src = "libresoc.v:42225.20-42225.106" *)
  wire _1432_;
  (* src = "libresoc.v:42262.19-42262.136" *)
  wire [3:0] _1433_;
  (* src = "libresoc.v:42263.19-42263.192" *)
  wire [5:0] _1434_;
  (* src = "libresoc.v:42264.19-42264.138" *)
  wire [2:0] _1435_;
  (* src = "libresoc.v:42265.19-42265.150" *)
  wire [3:0] _1436_;
  (* src = "libresoc.v:42272.19-42272.128" *)
  wire [2:0] _1437_;
  (* src = "libresoc.v:42287.19-42287.159" *)
  wire [5:0] _1438_;
  (* src = "libresoc.v:42294.19-42294.128" *)
  wire [2:0] _1439_;
  (* src = "libresoc.v:42301.19-42301.128" *)
  wire [2:0] _1440_;
  (* src = "libresoc.v:42312.19-42312.150" *)
  wire [4:0] _1441_;
  (* src = "libresoc.v:42313.19-42313.134" *)
  wire [2:0] _1442_;
  (* src = "libresoc.v:42316.19-42316.108" *)
  wire _1443_;
  (* src = "libresoc.v:42322.19-42322.107" *)
  wire _1444_;
  (* src = "libresoc.v:42328.19-42328.109" *)
  wire _1445_;
  (* src = "libresoc.v:42334.19-42334.112" *)
  wire _1446_;
  (* src = "libresoc.v:42340.19-42340.108" *)
  wire _1447_;
  (* src = "libresoc.v:42346.19-42346.108" *)
  wire _1448_;
  (* src = "libresoc.v:42352.19-42352.113" *)
  wire _1449_;
  (* src = "libresoc.v:42358.19-42358.109" *)
  wire _1450_;
  (* src = "libresoc.v:42364.19-42364.113" *)
  wire _1451_;
  (* src = "libresoc.v:42370.19-42370.109" *)
  wire _1452_;
  (* src = "libresoc.v:42376.19-42376.109" *)
  wire _1453_;
  (* src = "libresoc.v:42382.19-42382.108" *)
  wire _1454_;
  (* src = "libresoc.v:42388.19-42388.110" *)
  wire _1455_;
  (* src = "libresoc.v:42394.19-42394.113" *)
  wire _1456_;
  (* src = "libresoc.v:42400.19-42400.109" *)
  wire _1457_;
  (* src = "libresoc.v:42406.19-42406.109" *)
  wire _1458_;
  (* src = "libresoc.v:42412.19-42412.109" *)
  wire _1459_;
  (* src = "libresoc.v:42418.19-42418.114" *)
  wire _1460_;
  (* src = "libresoc.v:42424.19-42424.110" *)
  wire _1461_;
  (* src = "libresoc.v:42455.19-42455.110" *)
  wire _1462_;
  (* src = "libresoc.v:42461.19-42461.114" *)
  wire _1463_;
  (* src = "libresoc.v:42467.19-42467.110" *)
  wire _1464_;
  (* src = "libresoc.v:42473.19-42473.110" *)
  wire _1465_;
  (* src = "libresoc.v:42479.19-42479.110" *)
  wire _1466_;
  (* src = "libresoc.v:42485.19-42485.115" *)
  wire _1467_;
  (* src = "libresoc.v:42501.19-42501.110" *)
  wire _1468_;
  (* src = "libresoc.v:42507.19-42507.110" *)
  wire _1469_;
  (* src = "libresoc.v:42513.19-42513.115" *)
  wire _1470_;
  (* src = "libresoc.v:42526.19-42526.110" *)
  wire _1471_;
  (* src = "libresoc.v:42532.19-42532.109" *)
  wire _1472_;
  (* src = "libresoc.v:42538.19-42538.106" *)
  wire _1473_;
  (* src = "libresoc.v:42546.19-42546.110" *)
  wire _1474_;
  (* src = "libresoc.v:42555.19-42555.106" *)
  wire _1475_;
  (* src = "libresoc.v:42563.19-42563.106" *)
  wire _1476_;
  (* src = "libresoc.v:42571.19-42571.113" *)
  wire _1477_;
  (* src = "libresoc.v:42577.19-42577.111" *)
  wire _1478_;
  (* src = "libresoc.v:42583.19-42583.110" *)
  wire _1479_;
  (* src = "libresoc.v:42589.19-42589.113" *)
  wire _1480_;
  (* src = "libresoc.v:42595.19-42595.111" *)
  wire _1481_;
  (* src = "libresoc.v:42606.19-42606.108" *)
  wire _1482_;
  (* src = "libresoc.v:42623.19-42623.99" *)
  wire _1483_;
  (* src = "libresoc.v:42629.19-42629.104" *)
  wire _1484_;
  (* src = "libresoc.v:41956.20-41956.117" *)
  wire [63:0] _1485_;
  (* src = "libresoc.v:41957.20-41957.123" *)
  wire [63:0] _1486_;
  (* src = "libresoc.v:41958.20-41958.113" *)
  wire [63:0] _1487_;
  (* src = "libresoc.v:41959.20-41959.103" *)
  wire [63:0] _1488_;
  (* src = "libresoc.v:41960.20-41960.123" *)
  wire [63:0] _1489_;
  (* src = "libresoc.v:41961.20-41961.122" *)
  wire [64:0] _1490_;
  (* src = "libresoc.v:41962.20-41962.113" *)
  wire [64:0] _1491_;
  (* src = "libresoc.v:41963.20-41963.103" *)
  wire [64:0] _1492_;
  (* src = "libresoc.v:41964.20-41964.103" *)
  wire [64:0] _1493_;
  (* src = "libresoc.v:41965.20-41965.110" *)
  wire [6:0] _1494_;
  (* src = "libresoc.v:41966.20-41966.117" *)
  wire [6:0] _1495_;
  (* src = "libresoc.v:41967.20-41967.110" *)
  wire [6:0] _1496_;
  (* src = "libresoc.v:41968.20-41968.103" *)
  wire [6:0] _1497_;
  (* src = "libresoc.v:41969.20-41969.117" *)
  wire [6:0] _1498_;
  (* src = "libresoc.v:41970.20-41970.117" *)
  wire [6:0] _1499_;
  (* src = "libresoc.v:41971.20-41971.110" *)
  wire [6:0] _1500_;
  (* src = "libresoc.v:41972.20-41972.103" *)
  wire [6:0] _1501_;
  (* src = "libresoc.v:41973.20-41973.103" *)
  wire [6:0] _1502_;
  (* src = "libresoc.v:41974.20-41974.99" *)
  wire _1503_;
  (* src = "libresoc.v:41975.20-41975.107" *)
  wire _1504_;
  (* src = "libresoc.v:41976.20-41976.105" *)
  wire _1505_;
  (* src = "libresoc.v:41977.20-41977.103" *)
  wire _1506_;
  (* src = "libresoc.v:41978.20-41978.107" *)
  wire _1507_;
  (* src = "libresoc.v:41979.20-41979.107" *)
  wire _1508_;
  (* src = "libresoc.v:41980.20-41980.105" *)
  wire _1509_;
  (* src = "libresoc.v:41981.20-41981.103" *)
  wire _1510_;
  (* src = "libresoc.v:41982.20-41982.103" *)
  wire _1511_;
  (* src = "libresoc.v:42044.20-42044.117" *)
  wire [3:0] _1512_;
  (* src = "libresoc.v:42045.20-42045.113" *)
  wire [3:0] _1513_;
  (* src = "libresoc.v:42046.20-42046.123" *)
  wire [3:0] _1514_;
  (* src = "libresoc.v:42047.20-42047.113" *)
  wire [3:0] _1515_;
  (* src = "libresoc.v:42048.20-42048.103" *)
  wire [3:0] _1516_;
  (* src = "libresoc.v:42049.20-42049.117" *)
  wire [255:0] _1517_;
  (* src = "libresoc.v:42050.20-42050.110" *)
  wire [255:0] _1518_;
  (* src = "libresoc.v:42051.20-42051.117" *)
  wire [255:0] _1519_;
  (* src = "libresoc.v:42052.20-42052.110" *)
  wire [255:0] _1520_;
  (* src = "libresoc.v:42053.20-42053.103" *)
  wire [255:0] _1521_;
  (* src = "libresoc.v:42075.20-42075.117" *)
  wire [1:0] _1522_;
  (* src = "libresoc.v:42076.20-42076.113" *)
  wire [1:0] _1523_;
  (* src = "libresoc.v:42077.20-42077.117" *)
  wire [1:0] _1524_;
  (* src = "libresoc.v:42078.20-42078.110" *)
  wire [1:0] _1525_;
  (* src = "libresoc.v:42108.20-42108.112" *)
  wire [1:0] _1526_;
  (* src = "libresoc.v:42109.20-42109.123" *)
  wire [1:0] _1527_;
  (* src = "libresoc.v:42110.20-42110.103" *)
  wire [1:0] _1528_;
  (* src = "libresoc.v:42111.20-42111.117" *)
  wire [2:0] _1529_;
  (* src = "libresoc.v:42112.20-42112.117" *)
  wire [2:0] _1530_;
  (* src = "libresoc.v:42113.20-42113.103" *)
  wire [2:0] _1531_;
  (* src = "libresoc.v:42142.20-42142.123" *)
  wire _1532_;
  (* src = "libresoc.v:42143.20-42143.123" *)
  wire _1533_;
  (* src = "libresoc.v:42144.20-42144.103" *)
  wire _1534_;
  (* src = "libresoc.v:42146.20-42146.117" *)
  wire _1535_;
  (* src = "libresoc.v:42147.20-42147.117" *)
  wire _1536_;
  (* src = "libresoc.v:42148.20-42148.103" *)
  wire _1537_;
  (* src = "libresoc.v:42185.20-42185.123" *)
  wire [63:0] _1538_;
  (* src = "libresoc.v:42186.20-42186.123" *)
  wire [63:0] _1539_;
  (* src = "libresoc.v:42187.20-42187.113" *)
  wire [63:0] _1540_;
  (* src = "libresoc.v:42188.20-42188.103" *)
  wire [63:0] _1541_;
  (* src = "libresoc.v:42189.20-42189.117" *)
  wire [2:0] _1542_;
  (* src = "libresoc.v:42190.20-42190.117" *)
  wire [2:0] _1543_;
  (* src = "libresoc.v:42191.20-42191.110" *)
  wire [2:0] _1544_;
  (* src = "libresoc.v:42192.20-42192.103" *)
  wire [2:0] _1545_;
  (* src = "libresoc.v:42193.20-42193.107" *)
  wire _1546_;
  (* src = "libresoc.v:42194.20-42194.107" *)
  wire _1547_;
  (* src = "libresoc.v:42195.20-42195.105" *)
  wire _1548_;
  (* src = "libresoc.v:42196.20-42196.103" *)
  wire _1549_;
  (* src = "libresoc.v:42211.20-42211.123" *)
  wire [63:0] _1550_;
  (* src = "libresoc.v:42212.20-42212.117" *)
  wire _1551_;
  (* src = "libresoc.v:42255.19-42255.115" *)
  wire _1552_;
  (* src = "libresoc.v:42257.19-42257.115" *)
  wire _1553_;
  (* src = "libresoc.v:42261.19-42261.115" *)
  wire _1554_;
  (* src = "libresoc.v:42269.19-42269.115" *)
  wire _1555_;
  (* src = "libresoc.v:42271.19-42271.115" *)
  wire _1556_;
  (* src = "libresoc.v:42276.19-42276.115" *)
  wire _1557_;
  (* src = "libresoc.v:42278.19-42278.115" *)
  wire _1558_;
  (* src = "libresoc.v:42282.19-42282.115" *)
  wire _1559_;
  (* src = "libresoc.v:42286.19-42286.115" *)
  wire _1560_;
  (* src = "libresoc.v:42291.19-42291.115" *)
  wire _1561_;
  (* src = "libresoc.v:42293.19-42293.115" *)
  wire _1562_;
  (* src = "libresoc.v:42298.19-42298.115" *)
  wire _1563_;
  (* src = "libresoc.v:42300.19-42300.115" *)
  wire _1564_;
  (* src = "libresoc.v:42305.19-42305.115" *)
  wire _1565_;
  (* src = "libresoc.v:42307.19-42307.115" *)
  wire _1566_;
  (* src = "libresoc.v:42311.19-42311.115" *)
  wire _1567_;
  (* src = "libresoc.v:42428.19-42428.134" *)
  wire [6:0] _1568_;
  (* src = "libresoc.v:42429.19-42429.140" *)
  wire [6:0] _1569_;
  (* src = "libresoc.v:42430.19-42430.100" *)
  wire [6:0] _1570_;
  (* src = "libresoc.v:42431.19-42431.135" *)
  wire [6:0] _1571_;
  (* src = "libresoc.v:42432.19-42432.141" *)
  wire [6:0] _1572_;
  (* src = "libresoc.v:42433.19-42433.122" *)
  wire [6:0] _1573_;
  (* src = "libresoc.v:42434.19-42434.100" *)
  wire [6:0] _1574_;
  (* src = "libresoc.v:42435.19-42435.100" *)
  wire [6:0] _1575_;
  (* src = "libresoc.v:42436.19-42436.137" *)
  wire [6:0] _1576_;
  (* src = "libresoc.v:42437.19-42437.142" *)
  wire [6:0] _1577_;
  (* src = "libresoc.v:42438.19-42438.117" *)
  wire [6:0] _1578_;
  (* src = "libresoc.v:42439.19-42439.100" *)
  wire [6:0] _1579_;
  (* src = "libresoc.v:42440.19-42440.137" *)
  wire [6:0] _1580_;
  (* src = "libresoc.v:42441.19-42441.143" *)
  wire [6:0] _1581_;
  (* src = "libresoc.v:42442.19-42442.118" *)
  wire [6:0] _1582_;
  (* src = "libresoc.v:42443.19-42443.100" *)
  wire [6:0] _1583_;
  (* src = "libresoc.v:42444.19-42444.100" *)
  wire [6:0] _1584_;
  (* src = "libresoc.v:42445.19-42445.100" *)
  wire [6:0] _1585_;
  (* src = "libresoc.v:42450.19-42450.115" *)
  wire _1586_;
  (* src = "libresoc.v:42452.19-42452.115" *)
  wire _1587_;
  (* src = "libresoc.v:42489.19-42489.143" *)
  wire _1588_;
  (* src = "libresoc.v:42490.19-42490.119" *)
  wire _1589_;
  (* src = "libresoc.v:42491.19-42491.144" *)
  wire _1590_;
  (* src = "libresoc.v:42492.19-42492.119" *)
  wire _1591_;
  (* src = "libresoc.v:42493.19-42493.100" *)
  wire _1592_;
  (* src = "libresoc.v:42498.19-42498.115" *)
  wire _1593_;
  (* src = "libresoc.v:42517.19-42517.144" *)
  wire [1:0] _1594_;
  (* src = "libresoc.v:42518.19-42518.119" *)
  wire [1:0] _1595_;
  (* src = "libresoc.v:42523.19-42523.115" *)
  wire _1596_;
  (* src = "libresoc.v:42552.19-42552.135" *)
  wire [255:0] _1597_;
  (* src = "libresoc.v:42599.19-42599.143" *)
  wire [2:0] _1598_;
  (* src = "libresoc.v:42600.19-42600.143" *)
  wire [2:0] _1599_;
  (* src = "libresoc.v:42601.19-42601.119" *)
  wire [2:0] _1600_;
  (* src = "libresoc.v:42602.19-42602.100" *)
  wire [2:0] _1601_;
  (* src = "libresoc.v:42079.20-42079.95" *)
  wire [2:0] _1602_;
  (* src = "libresoc.v:42145.20-42145.95" *)
  wire [1:0] _1603_;
  (* src = "libresoc.v:42149.20-42149.95" *)
  wire [2:0] _1604_;
  (* src = "libresoc.v:42213.20-42213.95" *)
  wire [2:0] _1605_;
  (* src = "libresoc.v:42221.20-42221.104" *)
  wire [2:0] _1606_;
  (* src = "libresoc.v:42494.19-42494.93" *)
  wire [2:0] _1607_;
  (* src = "libresoc.v:42519.19-42519.93" *)
  wire [2:0] _1608_;
  (* src = "libresoc.v:42230.19-42230.95" *)
  wire _1609_;
  (* src = "libresoc.v:42232.19-42232.95" *)
  wire _1610_;
  (* src = "libresoc.v:42234.19-42234.95" *)
  wire _1611_;
  (* src = "libresoc.v:42236.19-42236.95" *)
  wire _1612_;
  (* src = "libresoc.v:42238.19-42238.95" *)
  wire _1613_;
  (* src = "libresoc.v:42240.19-42240.95" *)
  wire _1614_;
  (* src = "libresoc.v:42242.19-42242.95" *)
  wire _1615_;
  (* src = "libresoc.v:42244.19-42244.95" *)
  wire _1616_;
  (* src = "libresoc.v:42246.19-42246.95" *)
  wire _1617_;
  (* src = "libresoc.v:42248.19-42248.95" *)
  wire _1618_;
  (* src = "libresoc.v:42446.19-42446.507" *)
  wire _1619_;
  (* src = "libresoc.v:42603.19-42603.210" *)
  wire _1620_;
  (* src = "libresoc.v:42610.19-42610.108" *)
  wire _1621_;
  (* src = "libresoc.v:42002.20-42002.118" *)
  wire [255:0] _1622_;
  (* src = "libresoc.v:42010.20-42010.118" *)
  wire [255:0] _1623_;
  (* src = "libresoc.v:42018.20-42018.118" *)
  wire [255:0] _1624_;
  (* src = "libresoc.v:42026.20-42026.118" *)
  wire [255:0] _1625_;
  (* src = "libresoc.v:42034.20-42034.118" *)
  wire [255:0] _1626_;
  (* src = "libresoc.v:42042.20-42042.118" *)
  wire [255:0] _1627_;
  (* src = "libresoc.v:42542.19-42542.115" *)
  wire [255:0] _1628_;
  (* src = "libresoc.v:42550.19-42550.115" *)
  wire [255:0] _1629_;
  (* src = "libresoc.v:42559.19-42559.115" *)
  wire [255:0] _1630_;
  (* src = "libresoc.v:42567.19-42567.115" *)
  wire [255:0] _1631_;
  (* src = "libresoc.v:42001.20-42001.121" *)
  wire [7:0] _1632_;
  (* src = "libresoc.v:42009.20-42009.121" *)
  wire [7:0] _1633_;
  (* src = "libresoc.v:42017.20-42017.121" *)
  wire [7:0] _1634_;
  (* src = "libresoc.v:42025.20-42025.121" *)
  wire [7:0] _1635_;
  (* src = "libresoc.v:42033.20-42033.121" *)
  wire [7:0] _1636_;
  (* src = "libresoc.v:42041.20-42041.121" *)
  wire [7:0] _1637_;
  (* src = "libresoc.v:42250.19-42250.102" *)
  wire [2:0] _1638_;
  (* src = "libresoc.v:42541.19-42541.119" *)
  wire [7:0] _1639_;
  (* src = "libresoc.v:42549.19-42549.119" *)
  wire [7:0] _1640_;
  (* src = "libresoc.v:42558.19-42558.119" *)
  wire [7:0] _1641_;
  (* src = "libresoc.v:42566.19-42566.122" *)
  wire [7:0] _1642_;
  (* src = "libresoc.v:41907.20-41907.117" *)
  wire [6:0] _1643_;
  (* src = "libresoc.v:41913.20-41913.118" *)
  wire [6:0] _1644_;
  (* src = "libresoc.v:41919.20-41919.118" *)
  wire [6:0] _1645_;
  (* src = "libresoc.v:41925.20-41925.118" *)
  wire [6:0] _1646_;
  (* src = "libresoc.v:41931.20-41931.118" *)
  wire [6:0] _1647_;
  (* src = "libresoc.v:41937.20-41937.118" *)
  wire [6:0] _1648_;
  (* src = "libresoc.v:41943.20-41943.118" *)
  wire [6:0] _1649_;
  (* src = "libresoc.v:41949.20-41949.118" *)
  wire [6:0] _1650_;
  (* src = "libresoc.v:41955.20-41955.116" *)
  wire [6:0] _1651_;
  (* src = "libresoc.v:41989.20-41989.124" *)
  wire [7:0] _1652_;
  (* src = "libresoc.v:42003.20-42003.180" *)
  wire [255:0] _1653_;
  (* src = "libresoc.v:42011.20-42011.180" *)
  wire [255:0] _1654_;
  (* src = "libresoc.v:42019.20-42019.180" *)
  wire [255:0] _1655_;
  (* src = "libresoc.v:42027.20-42027.180" *)
  wire [255:0] _1656_;
  (* src = "libresoc.v:42035.20-42035.180" *)
  wire [255:0] _1657_;
  (* src = "libresoc.v:42043.20-42043.180" *)
  wire [255:0] _1658_;
  (* src = "libresoc.v:42062.20-42062.112" *)
  wire [1:0] _1659_;
  (* src = "libresoc.v:42068.20-42068.112" *)
  wire [1:0] _1660_;
  (* src = "libresoc.v:42074.20-42074.112" *)
  wire [1:0] _1661_;
  (* src = "libresoc.v:42089.20-42089.112" *)
  wire [2:0] _1662_;
  (* src = "libresoc.v:42095.20-42095.112" *)
  wire [2:0] _1663_;
  (* src = "libresoc.v:42101.20-42101.112" *)
  wire [2:0] _1664_;
  (* src = "libresoc.v:42107.20-42107.112" *)
  wire [2:0] _1665_;
  (* src = "libresoc.v:42123.20-42123.112" *)
  wire _1666_;
  (* src = "libresoc.v:42129.20-42129.112" *)
  wire _1667_;
  (* src = "libresoc.v:42135.20-42135.112" *)
  wire _1668_;
  (* src = "libresoc.v:42141.20-42141.112" *)
  wire _1669_;
  (* src = "libresoc.v:42160.20-42160.119" *)
  wire [2:0] _1670_;
  (* src = "libresoc.v:42166.20-42166.119" *)
  wire [2:0] _1671_;
  (* src = "libresoc.v:42172.20-42172.119" *)
  wire [2:0] _1672_;
  (* src = "libresoc.v:42178.20-42178.119" *)
  wire [2:0] _1673_;
  (* src = "libresoc.v:42184.20-42184.119" *)
  wire [2:0] _1674_;
  (* src = "libresoc.v:42204.20-42204.112" *)
  wire _1675_;
  (* src = "libresoc.v:42210.20-42210.112" *)
  wire _1676_;
  (* src = "libresoc.v:42220.20-42220.112" *)
  wire [1:0] _1677_;
  (* src = "libresoc.v:42228.20-42228.120" *)
  wire [9:0] _1678_;
  (* src = "libresoc.v:42319.19-42319.126" *)
  wire [6:0] _1679_;
  (* src = "libresoc.v:42325.19-42325.125" *)
  wire [6:0] _1680_;
  (* src = "libresoc.v:42331.19-42331.127" *)
  wire [6:0] _1681_;
  (* src = "libresoc.v:42337.19-42337.130" *)
  wire [6:0] _1682_;
  (* src = "libresoc.v:42343.19-42343.126" *)
  wire [6:0] _1683_;
  (* src = "libresoc.v:42349.19-42349.126" *)
  wire [6:0] _1684_;
  (* src = "libresoc.v:42355.19-42355.131" *)
  wire [6:0] _1685_;
  (* src = "libresoc.v:42361.19-42361.127" *)
  wire [6:0] _1686_;
  (* src = "libresoc.v:42367.19-42367.131" *)
  wire [6:0] _1687_;
  (* src = "libresoc.v:42373.19-42373.127" *)
  wire [6:0] _1688_;
  (* src = "libresoc.v:42379.19-42379.127" *)
  wire [6:0] _1689_;
  (* src = "libresoc.v:42385.19-42385.126" *)
  wire [6:0] _1690_;
  (* src = "libresoc.v:42391.19-42391.128" *)
  wire [6:0] _1691_;
  (* src = "libresoc.v:42397.19-42397.131" *)
  wire [6:0] _1692_;
  (* src = "libresoc.v:42403.19-42403.127" *)
  wire [6:0] _1693_;
  (* src = "libresoc.v:42409.19-42409.127" *)
  wire [6:0] _1694_;
  (* src = "libresoc.v:42415.19-42415.127" *)
  wire [6:0] _1695_;
  (* src = "libresoc.v:42421.19-42421.132" *)
  wire [6:0] _1696_;
  (* src = "libresoc.v:42427.19-42427.128" *)
  wire [6:0] _1697_;
  (* src = "libresoc.v:42458.19-42458.122" *)
  wire _1698_;
  (* src = "libresoc.v:42464.19-42464.126" *)
  wire _1699_;
  (* src = "libresoc.v:42470.19-42470.122" *)
  wire _1700_;
  (* src = "libresoc.v:42476.19-42476.122" *)
  wire _1701_;
  (* src = "libresoc.v:42482.19-42482.122" *)
  wire _1702_;
  (* src = "libresoc.v:42488.19-42488.127" *)
  wire _1703_;
  (* src = "libresoc.v:42504.19-42504.122" *)
  wire [1:0] _1704_;
  (* src = "libresoc.v:42510.19-42510.122" *)
  wire [1:0] _1705_;
  (* src = "libresoc.v:42516.19-42516.127" *)
  wire [1:0] _1706_;
  (* src = "libresoc.v:42529.19-42529.122" *)
  wire [2:0] _1707_;
  (* src = "libresoc.v:42535.19-42535.133" *)
  wire [7:0] _1708_;
  (* src = "libresoc.v:42543.19-42543.185" *)
  wire [255:0] _1709_;
  (* src = "libresoc.v:42551.19-42551.189" *)
  wire [255:0] _1710_;
  (* src = "libresoc.v:42560.19-42560.185" *)
  wire [255:0] _1711_;
  (* src = "libresoc.v:42568.19-42568.185" *)
  wire [255:0] _1712_;
  (* src = "libresoc.v:42574.19-42574.131" *)
  wire [2:0] _1713_;
  (* src = "libresoc.v:42580.19-42580.129" *)
  wire [2:0] _1714_;
  (* src = "libresoc.v:42586.19-42586.128" *)
  wire [2:0] _1715_;
  (* src = "libresoc.v:42592.19-42592.131" *)
  wire [2:0] _1716_;
  (* src = "libresoc.v:42598.19-42598.129" *)
  wire [2:0] _1717_;
  (* src = "libresoc.v:42609.19-42609.128" *)
  wire [9:0] _1718_;
  (* src = "libresoc.v:42626.19-42626.110" *)
  wire [6:0] _1719_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1001 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1003 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1006 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1010 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1012 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1019 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1022 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1024 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1027 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1031 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1033 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1037 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1040 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1042 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1045 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1049 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1051 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1059 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1062 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1064 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1067 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1071 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1073 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1079 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1082 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1084 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1087 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1091 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1093 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1099 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1107 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1111 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1126 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1130 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1144 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1147 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$1155 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [64:0] \$1157 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1158 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1160 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$1162 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$1164 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1166 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [64:0] \$1168 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [64:0] \$1170 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [64:0] \$1172 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [64:0] \$1174 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1176 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$1177 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$1179 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1181 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1183 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$1185 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$1187 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1189 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1191 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$1193 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1195 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1197 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1199 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1201 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1203 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1205 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1207 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1209 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1211 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1213 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1215 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1218 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1221 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1223 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1226 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [7:0] \$1229 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1231 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1233 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1235 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1237 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1239 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1241 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1243 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1246 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1249 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1251 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1254 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1257 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1259 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1261 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1263 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1266 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1269 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1271 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1274 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1277 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1279 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1281 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1283 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1286 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1289 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1291 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1294 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1297 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1299 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1301 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1303 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1306 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1309 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1311 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1314 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1317 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1319 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1321 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1323 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1326 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1329 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1331 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1334 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1337 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1339 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1341 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1343 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1346 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1349 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1351 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1354 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [7:0] \$1357 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *)
  wire [255:0] \$1359 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [255:0] \$1361 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$1363 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$1365 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$1367 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$1369 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$1371 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [255:0] \$1373 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [255:0] \$1374 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [255:0] \$1376 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [255:0] \$1378 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [255:0] \$1380 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [255:0] \$1382 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1384 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1386 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1388 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1390 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1393 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1396 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1398 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1401 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [1:0] \$1404 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1406 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1409 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1412 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1414 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1417 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [1:0] \$1420 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1422 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1425 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1428 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1430 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1433 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [1:0] \$1436 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$1438 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$1440 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$1442 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$1443 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$1445 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1448 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1450 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1452 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1454 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1456 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1459 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1462 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1464 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1467 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1470 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1472 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1475 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1478 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1480 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1483 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1486 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1488 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1491 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1494 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1496 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1499 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1502 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1504 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1507 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1510 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1512 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1515 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1518 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$1520 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$1522 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$1524 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$1526 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$1528 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$1530 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1532 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1534 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1536 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1538 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1540 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1543 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1546 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1548 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1551 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1554 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1556 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1559 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1562 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1564 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1567 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1570 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1572 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1575 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1578 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1580 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1583 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1586 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1588 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1591 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1594 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1596 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1599 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1602 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$1604 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1605 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1607 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1609 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$1612 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1613 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1615 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1617 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1620 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1622 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1624 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1626 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1628 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1630 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1633 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1637 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1639 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1644 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1647 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1649 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1652 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1655 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1657 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1660 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1663 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1665 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1668 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1671 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1673 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1676 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1679 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1681 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1684 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1687 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1689 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1692 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1695 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1697 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1700 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1703 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1705 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1708 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [2:0] \$1711 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1713 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1715 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$1717 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$1719 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$1721 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$1723 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$1725 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$1727 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1729 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1731 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1733 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$1735 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1737 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1739 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1741 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1744 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1747 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1749 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1752 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1755 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1757 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1760 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1763 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1765 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1768 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire \$1771 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$1773 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$1775 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$1776 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1779 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1781 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1784 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1787 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1789 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1792 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [1:0] \$1795 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \$1797 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$1799 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$1801 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$1804 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1807 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$1809 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$181 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$1812 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [9:0] \$1815 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$182 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$185 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$186 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$189 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$190 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$193 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$194 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$197 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$198 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$201 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$202 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$205 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$206 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$209 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$210 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$213 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$214 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire \$217 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *)
  wire [13:0] \$218 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
  wire \$221 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *)
  wire [2:0] \$223 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *)
  wire [2:0] \$224 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
  wire \$226 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [3:0] \$228 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$229 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$231 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$233 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$235 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$237 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$239 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *)
  wire \$241 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire [2:0] \$243 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$245 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$247 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [5:0] \$250 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [2:0] \$252 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [3:0] \$254 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [2:0] \$256 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$257 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$259 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$261 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$263 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$265 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$267 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [5:0] \$270 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$271 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$273 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$275 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$277 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$279 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$281 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *)
  wire \$283 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire [2:0] \$285 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire \$287 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire \$289 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *)
  wire \$291 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire [2:0] \$293 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$295 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$297 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [2:0] \$300 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$301 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$303 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$305 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$307 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$309 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$311 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [2:0] \$314 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$315 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$317 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$319 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$321 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$323 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$325 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [4:0] \$328 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$329 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$331 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$333 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$335 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$337 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$339 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *)
  wire \$341 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire [2:0] \$343 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$345 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$347 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *)
  wire [2:0] \$350 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$352 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$354 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$356 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$358 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$360 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$362 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$364 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$366 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$368 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$370 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$372 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$374 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$376 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$378 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$380 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$382 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$384 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$386 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$388 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$390 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$392 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$394 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$396 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$398 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$400 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$402 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$404 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$406 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$408 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$410 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$412 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$414 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$416 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$418 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$420 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$422 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$424 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$426 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$428 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$430 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$432 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$434 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$436 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$438 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$440 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$442 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$444 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$446 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$448 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$450 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$452 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$454 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$456 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$458 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$460 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$462 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$464 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$466 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$468 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$470 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$472 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$474 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$476 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$478 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$480 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$482 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$484 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$486 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$488 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$490 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$492 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$494 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$496 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$498 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$500 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$502 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$504 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$506 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$508 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$510 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$512 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$514 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$516 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$518 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$520 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$522 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$524 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$526 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$528 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$530 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$532 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$534 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$536 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$538 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$540 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$542 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$544 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$546 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$548 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$550 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$552 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$554 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$556 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$558 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$560 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$562 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$564 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$566 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$568 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$570 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$572 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$574 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$576 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [6:0] \$578 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$580 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$581 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$583 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$585 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$587 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$589 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$591 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$593 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$595 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$597 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$599 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$601 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$603 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$605 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [6:0] \$607 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$609 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$611 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$613 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [6:0] \$615 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
  wire \$617 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$619 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire [2:0] \$621 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$623 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *)
  wire \$625 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$627 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *)
  wire \$629 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$631 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$633 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$635 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$637 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$639 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$641 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$643 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$645 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$647 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$649 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$651 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$653 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$655 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$657 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$659 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$661 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$663 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$665 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$667 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$669 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$671 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$673 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$675 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$677 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$679 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$681 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$683 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$685 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$687 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$689 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$691 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$693 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$695 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$697 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$699 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire \$701 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$703 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$704 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$706 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire \$708 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$710 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire \$712 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *)
  wire \$715 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire [2:0] \$717 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$719 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *)
  wire \$721 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$723 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$725 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$727 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$729 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$731 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [1:0] \$733 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$735 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$737 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$739 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$741 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$743 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [1:0] \$745 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$747 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$749 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$751 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$753 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$755 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [1:0] \$757 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$759 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$760 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$762 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *)
  wire \$765 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire [2:0] \$767 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire \$769 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *)
  wire \$771 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$773 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$775 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$777 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$779 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$781 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$783 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$785 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$787 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$789 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$791 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$793 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [7:0] \$795 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$797 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$799 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$801 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$803 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$805 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
  wire [7:0] \$807 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
  wire [255:0] \$809 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [255:0] \$811 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$813 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$815 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$817 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$819 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$821 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
  wire [7:0] \$823 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *)
  wire [255:0] \$825 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [255:0] \$827 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [255:0] \$829 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [255:0] \$830 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$832 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$834 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$836 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$838 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$840 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *)
  wire [7:0] \$842 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *)
  wire [255:0] \$844 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [255:0] \$846 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$848 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$850 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$852 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$854 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$856 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *)
  wire [7:0] \$858 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *)
  wire [255:0] \$860 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [255:0] \$862 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$864 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$866 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$868 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$870 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$872 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$874 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$876 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$878 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$880 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$882 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$884 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$886 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$888 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$890 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$892 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$894 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$896 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$898 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$900 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$902 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$904 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$906 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$908 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$910 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$912 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$914 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$916 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$918 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$920 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [2:0] \$922 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$924 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [2:0] \$926 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$928 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [2:0] \$930 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
  wire \$932 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$934 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *)
  wire \$936 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$938 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *)
  wire \$940 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *)
  wire \$942 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *)
  wire [9:0] \$944 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *)
  wire \$946 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$948 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$950 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$952 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$954 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$956 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$958 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$960 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$962 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$964 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$966 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *)
  wire \$968 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$970 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$972 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$974 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$980 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *)
  wire [6:0] \$982 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *)
  wire \$984 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *)
  wire \$987 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$991 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$993 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *)
  wire \$998 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] addr_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1000 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1021 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1039 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1061 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1081 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1138 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [6:0] \addr_en$1154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [7:0] \addr_en$1228 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1256 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1276 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1296 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1316 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1336 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [255:0] \addr_en$1356 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [1:0] \addr_en$1403 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [1:0] \addr_en$1419 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [1:0] \addr_en$1435 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1469 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1485 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1501 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1517 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1553 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1569 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1585 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1601 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1646 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1662 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1678 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1694 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [2:0] \addr_en$1710 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1754 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire \addr_en$1770 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [1:0] \addr_en$1794 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *)
  wire [9:0] \addr_en$1814 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [255:0] addr_en_CR_cr_a_branch0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [255:0] addr_en_CR_cr_a_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [255:0] addr_en_CR_cr_b_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [255:0] addr_en_CR_cr_c_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [7:0] addr_en_CR_full_cr_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_FAST_fast1_branch0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_FAST_fast1_branch0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_FAST_fast1_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_FAST_fast1_trap0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_FAST_fast1_trap0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_alu0_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_cr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_cr0_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_div0_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_div0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_ldst0_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_ldst0_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_ldst0_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_logical0_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_logical0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_mul0_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_mul0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_shiftrot0_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_shiftrot0_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_shiftrot0_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_spr0_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_trap0_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [6:0] addr_en_INT_rabc_trap0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [9:0] addr_en_SPR_spr1_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [1:0] addr_en_XER_xer_ca_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [1:0] addr_en_XER_xer_ca_shiftrot0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [1:0] addr_en_XER_xer_ca_spr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire [2:0] addr_en_XER_xer_ov_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_div0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_logical0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_mul0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_shiftrot0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285" *)
  wire addr_en_XER_xer_so_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *)
  input bigendian_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] cia__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] cia__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  input [63:0] core_core_cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [7:0] core_core_cr_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_core_cr_rd_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [7:0] core_core_cr_wr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \core_core_exc_$signal$9 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  input [13:0] core_core_fn_unit;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  input [1:0] core_core_input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  input [31:0] core_core_insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  input [6:0] core_core_insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  input core_core_is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  input [63:0] core_core_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_core_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_core_oe_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_core_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_core_rc_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  input [12:0] core_core_trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  input [7:0] core_core_traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_cr_in1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_cr_in1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_cr_in2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] \core_cr_in2$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_cr_in2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input \core_cr_in2_ok$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [2:0] core_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [2:0] core_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [2:0] core_fasto1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [2:0] core_fasto2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  input [63:0] core_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_reg1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_reg1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_reg2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_reg2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_reg3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_reg3_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [6:0] core_rego;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [9:0] core_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input core_spr1_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [9:0] core_spro;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
  output core_terminate_o;
  reg core_terminate_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
  reg \core_terminate_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  input [2:0] core_xer_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *)
  output corebusy_o;
  reg corebusy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
  reg [1:0] counter;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:198" *)
  reg [1:0] \counter$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] cr_data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [31:0] cr_full_rd__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_full_rd__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [31:0] cr_full_wr__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_full_wr__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] cr_src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_src1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] cr_src2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_src2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] cr_src3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_src3__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] cr_wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_ad__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_ad__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_st__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_st__rel_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] \data_i$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [44:0] dbus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [63:0] dbus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [63:0] dbus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [7:0] dbus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] dec_ALU_ALU__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_ALU_ALU__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_ALU_ALU__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] dec_ALU_ALU__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_ALU_ALU__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_ALU_ALU__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_ALU_ALU__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_ALU_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_ALU_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire dec_ALU_sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_BRANCH_BRANCH__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_BRANCH_BRANCH__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_BRANCH_BRANCH__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_BRANCH_BRANCH__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_BRANCH_BRANCH__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_BRANCH_BRANCH__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_BRANCH_BRANCH__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_BRANCH_BRANCH__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_BRANCH_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_BRANCH_raw_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_CR_CR__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_CR_CR__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_CR_CR__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_CR_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_CR_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] dec_DIV_DIV__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_DIV_DIV__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_DIV_DIV__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] dec_DIV_DIV__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_DIV_DIV__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_DIV_DIV__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_DIV_DIV__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_DIV_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_DIV_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire dec_DIV_sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] dec_LDST_LDST__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_LDST_LDST__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_LDST_LDST__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_LDST_LDST__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_LDST_LDST__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__is_signed;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] dec_LDST_LDST__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LDST_LDST__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_LDST_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_LDST_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire dec_LDST_sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] dec_LOGICAL_LOGICAL__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_LOGICAL_LOGICAL__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_LOGICAL_LOGICAL__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] dec_LOGICAL_LOGICAL__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_LOGICAL_LOGICAL__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_LOGICAL_LOGICAL__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_LOGICAL_LOGICAL__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_LOGICAL_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_LOGICAL_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire dec_LOGICAL_sv_a_nz;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_MUL_MUL__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_MUL_MUL__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_MUL_MUL__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_MUL_MUL__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_MUL_MUL__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_MUL_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_MUL_raw_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_SHIFT_ROT_SHIFT_ROT__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dec_SHIFT_ROT_SHIFT_ROT__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] dec_SHIFT_ROT_SHIFT_ROT__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_SHIFT_ROT_SHIFT_ROT__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_SHIFT_ROT_SHIFT_ROT__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SHIFT_ROT_SHIFT_ROT__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_SHIFT_ROT_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_SHIFT_ROT_raw_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dec_SPR_SPR__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dec_SPR_SPR__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dec_SPR_SPR__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dec_SPR_SPR__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec_SPR_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  wire [31:0] dec_SPR_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [4:0] dmi__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] dmi__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dmi__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_CR_cr_a_branch0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_CR_cr_a_branch0_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_CR_cr_a_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_CR_cr_a_cr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_CR_cr_b_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_CR_cr_b_cr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_CR_cr_c_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_CR_cr_c_cr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_CR_full_cr_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_CR_full_cr_cr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_FAST_fast1_branch0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_FAST_fast1_branch0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_FAST_fast1_branch0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_FAST_fast1_branch0_3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_FAST_fast1_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_FAST_fast1_spr0_2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_FAST_fast1_trap0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_FAST_fast1_trap0_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_FAST_fast1_trap0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_FAST_fast1_trap0_4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_alu0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_alu0_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_alu0_10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_cr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_cr0_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_cr0_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_cr0_11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_div0_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_div0_15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_div0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_div0_4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_ldst0_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_ldst0_18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_ldst0_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_ldst0_7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_ldst0_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_ldst0_9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_logical0_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_logical0_13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_logical0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_logical0_3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_mul0_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_mul0_16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_mul0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_mul0_5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_shiftrot0_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_shiftrot0_17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_shiftrot0_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_shiftrot0_6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_shiftrot0_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_shiftrot0_8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_spr0_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_spr0_14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_trap0_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_trap0_12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_INT_rabc_trap0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_INT_rabc_trap0_2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_SPR_spr1_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_SPR_spr1_spr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_ca_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_ca_alu0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_ca_shiftrot0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_ca_shiftrot0_2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_ca_spr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_ca_spr0_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_ov_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_ov_spr0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_alu0_0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_div0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_div0_3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_logical0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_logical0_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_mul0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_mul0_4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_shiftrot0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_shiftrot0_5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg dp_XER_xer_so_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" *)
  reg \dp_XER_xer_so_spr0_2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire ea_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_alu0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_branch0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_div0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_ldst0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_logical0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_mul0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_shiftrot0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_spr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:193" *)
  wire en_trap0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] fast_dest1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] fast_dest1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire fast_dest1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] fast_src1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] fast_src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire fast_src1__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:183" *)
  wire [9:0] fu_enable;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [31:0] full_rd2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] full_rd2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [5:0] full_rd__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] full_rd__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_cr_a_ok$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_cr_a_ok$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_cr_a_ok$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_cr_a_ok$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_cr_a_ok$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire fus_cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  wire \fus_cu_busy_o$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg fus_cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  reg \fus_cu_issue_i$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] fus_cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_rd__go_i$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_rd__go_i$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__go_i$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__go_i$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__go_i$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] \fus_cu_rd__go_i$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__go_i$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_rd__go_i$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__go_i$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] fus_cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_rd__rel_o$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_rd__rel_o$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__rel_o$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__rel_o$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__rel_o$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] \fus_cu_rd__rel_o$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__rel_o$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_rd__rel_o$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_rd__rel_o$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [3:0] fus_cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [5:0] \fus_cu_rdmaskn_i$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [2:0] \fus_cu_rdmaskn_i$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [3:0] \fus_cu_rdmaskn_i$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [2:0] \fus_cu_rdmaskn_i$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [5:0] \fus_cu_rdmaskn_i$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [2:0] \fus_cu_rdmaskn_i$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [2:0] \fus_cu_rdmaskn_i$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [4:0] \fus_cu_rdmaskn_i$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  reg [2:0] \fus_cu_rdmaskn_i$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] fus_cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [1:0] \fus_cu_wr__go_i$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_wr__go_i$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_wr__go_i$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_wr__go_i$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__go_i$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [1:0] \fus_cu_wr__go_i$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__go_i$149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__go_i$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] \fus_cu_wr__go_i$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] fus_cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [5:0] \fus_cu_wr__rel_o$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_wr__rel_o$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [3:0] \fus_cu_wr__rel_o$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__rel_o$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [1:0] \fus_cu_wr__rel_o$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__rel_o$148 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [2:0] \fus_cu_wr__rel_o$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [4:0] \fus_cu_wr__rel_o$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire [1:0] \fus_cu_wr__rel_o$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] fus_dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest1_o$153 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [31:0] fus_dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] \fus_dest2_o$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] \fus_dest2_o$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] \fus_dest2_o$129 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] \fus_dest2_o$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] \fus_dest2_o$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest2_o$154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest2_o$156 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest2_o$162 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [3:0] fus_dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] \fus_dest3_o$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] \fus_dest3_o$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] \fus_dest3_o$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] \fus_dest3_o$140 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest3_o$155 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest3_o$157 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest3_o$159 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] fus_dest4_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire \fus_dest4_o$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire \fus_dest4_o$146 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire \fus_dest4_o$147 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest4_o$160 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] fus_dest5_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire \fus_dest5_o$144 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [63:0] \fus_dest5_o$161 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  wire [1:0] fus_dest6_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] fus_ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_fast1_ok$150 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_fast1_ok$151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_fast2_ok$152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [95:0] fus_ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  wire fus_ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  wire fus_ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  wire [3:0] fus_ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$163 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$164 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$165 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$166 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$167 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$168 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \fus_ldst_port0_exc_$signal$169 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  wire fus_ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  wire fus_ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] fus_ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] fus_ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_msr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_nia_ok$158 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] fus_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_o_ok$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] fus_oper_i_alu_alu0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_alu0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_alu0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] fus_oper_i_alu_alu0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_alu0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_alu0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_alu0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_branch0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_branch0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_branch0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_branch0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_branch0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_branch0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_branch0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_branch0__lk;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_cr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_cr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_cr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] fus_oper_i_alu_div0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_div0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_div0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] fus_oper_i_alu_div0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_div0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_div0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_div0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] fus_oper_i_alu_logical0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_logical0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_logical0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] fus_oper_i_alu_logical0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_logical0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_logical0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_logical0__zero_a;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_mul0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_mul0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_mul0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_mul0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_mul0__write_cr0;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_shift_rot0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_shift_rot0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] fus_oper_i_alu_shift_rot0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_shift_rot0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_shift_rot0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_shift_rot0__write_cr0;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_spr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_spr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_spr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_spr0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_trap0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_alu_trap0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_alu_trap0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_alu_trap0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_alu_trap0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] fus_oper_i_alu_trap0__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_alu_trap0__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [12:0] fus_oper_i_alu_trap0__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] fus_oper_i_alu_trap0__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] fus_oper_i_ldst_ldst0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] fus_oper_i_ldst_ldst0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] fus_oper_i_ldst_ldst0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] fus_oper_i_ldst_ldst0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] fus_oper_i_ldst_ldst0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__is_signed;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] fus_oper_i_ldst_ldst0__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg fus_oper_i_ldst_ldst0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] fus_src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src1_i$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] fus_src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src2_i$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] fus_src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src3_i$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg \fus_src3_i$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg \fus_src3_i$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg \fus_src3_i$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg \fus_src3_i$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [31:0] \fus_src3_i$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [3:0] \fus_src3_i$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src3_i$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src3_i$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg fus_src4_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg \fus_src4_i$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [1:0] \fus_src4_i$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [3:0] \fus_src4_i$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [63:0] \fus_src4_i$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [1:0] fus_src5_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [1:0] \fus_src5_i$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [3:0] \fus_src5_i$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [1:0] fus_src6_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  reg [3:0] \fus_src6_i$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_ca_ok$132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_ca_ok$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_ov_ok$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_ov_ok$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_ov_ok$138 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire fus_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_so_ok$141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_so_ok$142 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fus_xer_so_ok$143 ;
  (* src = "libresoc.v:36262.7-36262.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [4:0] int_dest1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] int_dest1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire int_dest1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [4:0] int_src1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] int_src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire int_src1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] issue__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \issue__addr$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] issue__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] issue__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input issue__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input issue__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *)
  input issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *)
  input ivalid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] msr__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] msr__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_CR_cr_a_branch0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_CR_cr_a_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_CR_cr_b_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_CR_cr_c_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_CR_full_cr_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_FAST_fast1_branch0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_FAST_fast1_branch0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_FAST_fast1_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_FAST_fast1_trap0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_FAST_fast1_trap0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_alu0_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_cr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_cr0_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_div0_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_div0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_ldst0_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_ldst0_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_ldst0_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_logical0_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_logical0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_mul0_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_mul0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_shiftrot0_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_shiftrot0_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_shiftrot0_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_spr0_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_trap0_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_INT_rabc_trap0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_SPR_spr1_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_ca_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_ca_shiftrot0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_ca_spr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_ov_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_div0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_logical0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_mul0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_shiftrot0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:286" *)
  wire pick_XER_xer_so_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *)
  input [31:0] raw_insn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_CR_cr_a_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_CR_cr_b_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_CR_cr_c_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_CR_full_cr_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_FAST_fast1_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_FAST_fast1_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_INT_rabc_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_INT_rabc_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_INT_rabc_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_SPR_spr1_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_XER_xer_ca_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_XER_xer_ov_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:262" *)
  wire rdflag_XER_xer_so_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_CR_cr_a_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [1:0] rdpick_CR_cr_a_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [1:0] rdpick_CR_cr_a_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_CR_cr_b_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire rdpick_CR_cr_b_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire rdpick_CR_cr_b_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_CR_cr_c_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire rdpick_CR_cr_c_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire rdpick_CR_cr_c_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_CR_full_cr_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire rdpick_CR_full_cr_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire rdpick_CR_full_cr_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_FAST_fast1_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [4:0] rdpick_FAST_fast1_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [4:0] rdpick_FAST_fast1_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_INT_rabc_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [18:0] rdpick_INT_rabc_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [18:0] rdpick_INT_rabc_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_SPR_spr1_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire rdpick_SPR_spr1_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire rdpick_SPR_spr1_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_XER_xer_ca_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [2:0] rdpick_XER_xer_ca_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [2:0] rdpick_XER_xer_ca_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_XER_xer_ov_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire rdpick_XER_xer_ov_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire rdpick_XER_xer_ov_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire rdpick_XER_xer_so_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [5:0] rdpick_XER_xer_so_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [5:0] rdpick_XER_xer_so_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_CR_cr_a_branch0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_CR_cr_a_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_CR_cr_b_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_CR_cr_c_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_CR_full_cr_cr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_FAST_fast1_branch0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_FAST_fast1_branch0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_FAST_fast1_spr0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_FAST_fast1_trap0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_FAST_fast1_trap0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_alu0_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_cr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_cr0_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_div0_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_div0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_ldst0_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_ldst0_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_ldst0_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_logical0_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_logical0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_mul0_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_mul0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_shiftrot0_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_shiftrot0_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_shiftrot0_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_spr0_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_trap0_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_INT_rabc_trap0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_SPR_spr1_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_ca_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_ca_shiftrot0_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_ca_spr0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_ov_spr0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_alu0_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_div0_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_logical0_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_mul0_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_shiftrot0_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" *)
  wire rp_XER_xer_so_spr0_2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] spr_spr1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] \spr_spr1__addr$175 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] spr_spr1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] spr_spr1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire spr_spr1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire spr_spr1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] state_data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] \state_data_i$174 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [2:0] state_nia_wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] state_wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] sv__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] sv__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *)
  input sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire \sv_a_nz$176 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire \sv_a_nz$177 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire \sv_a_nz$178 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire \sv_a_nz$179 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire \sv_a_nz$180 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  input wb_dcache_en;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \wen$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire wp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1018 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1036 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1058 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1078 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1098 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1225 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1253 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1273 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1293 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1313 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1333 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1353 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1400 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1416 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1432 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1466 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1482 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1498 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1514 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1550 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1566 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1582 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1598 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1643 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1659 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1675 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1691 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1707 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1751 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1767 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1791 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$1811 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:429" *)
  wire \wp$997 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire wr_pick;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1005 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1026 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1044 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1066 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1086 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1217 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1245 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1265 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1285 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1305 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1325 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1345 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1392 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1408 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1424 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1458 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1474 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1490 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1506 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1542 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1558 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1574 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1590 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1632 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1651 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1667 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1683 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1699 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1743 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1759 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1783 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$1803 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:421" *)
  wire \wr_pick$986 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg wr_pick_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1008 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1008$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1029 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1029$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1047 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1047$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1069 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1069$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1089 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1089$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1109 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1109$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1128 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1128$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1146 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1146$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1220 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1220$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1248 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1248$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1268 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1268$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1288 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1288$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1308 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1308$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1328 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1328$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1348 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1348$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1395 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1395$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1411 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1411$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1427 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1427$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1461 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1461$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1477 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1477$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1493 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1493$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1509 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1509$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1545 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1545$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1561 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1561$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1577 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1577$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1593 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1593$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1635 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1635$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1654 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1654$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1670 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1670$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1686 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1686$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1702 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1702$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1746 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1746$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1762 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1762$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1786 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1786$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1806 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$1806$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$989 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$989$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \wr_pick_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire wr_pick_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1009 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1014 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1015 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1016 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1017 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1030 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1035 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1048 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1053 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1054 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1055 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1056 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1057 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1070 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1075 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1076 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1077 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1090 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1095 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1096 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1097 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1110 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1116 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1129 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1134 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1636 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1641 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$1642 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$976 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$977 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$978 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$979 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$990 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$995 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire \wr_pick_rise$996 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_alu0_cr_a_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_alu0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_alu0_xer_ca_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_alu0_xer_ov_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_alu0_xer_so_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_branch0_fast1_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_branch0_fast1_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_branch0_nia_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_cr0_cr_a_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_cr0_full_cr_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_cr0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_div0_cr_a_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_div0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_div0_xer_ov_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_div0_xer_so_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_ldst0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_ldst0_o_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_logical0_cr_a_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_logical0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_mul0_cr_a_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_mul0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_mul0_xer_ov_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_mul0_xer_so_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_shiftrot0_cr_a_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_shiftrot0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_shiftrot0_xer_ca_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_fast1_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_o_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_spr1_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_xer_ca_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_xer_ov_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_spr0_xer_so_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_trap0_fast1_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_trap0_fast1_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_trap0_msr_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_trap0_nia_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:413" *)
  wire wrflag_trap0_o_0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_CR_cr_a_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [5:0] wrpick_CR_cr_a_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [5:0] wrpick_CR_cr_a_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_CR_full_cr_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire wrpick_CR_full_cr_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire wrpick_CR_full_cr_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_FAST_fast1_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [4:0] wrpick_FAST_fast1_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [4:0] wrpick_FAST_fast1_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_INT_o_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [9:0] wrpick_INT_o_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [9:0] wrpick_INT_o_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_SPR_spr1_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire wrpick_SPR_spr1_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire wrpick_SPR_spr1_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_STATE_msr_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire wrpick_STATE_msr_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire wrpick_STATE_msr_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_STATE_nia_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [1:0] wrpick_STATE_nia_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [1:0] wrpick_STATE_nia_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_XER_xer_ca_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [2:0] wrpick_XER_xer_ca_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [2:0] wrpick_XER_xer_ca_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_XER_xer_ov_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [3:0] wrpick_XER_xer_ov_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [3:0] wrpick_XER_xer_ov_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire wrpick_XER_xer_so_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  wire [3:0] wrpick_XER_xer_so_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [3:0] wrpick_XER_xer_so_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] xer_data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] \xer_data_i$170 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] \xer_data_i$172 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] xer_src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] xer_src1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] xer_src2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] xer_src2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] xer_src3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] xer_src3__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] xer_wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] \xer_wen$171 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] \xer_wen$173 ;
  assign _0988_ = \fus_o_ok$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
  assign _0989_ = wrpick_INT_o_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _0990_ = \wr_pick$1005  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1010 ;
  assign _0991_ = \wr_pick$1005  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _0992_ = \fus_o_ok$98  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ;
  assign _0993_ = wrpick_INT_o_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _0994_ = \wr_pick$1026  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1031 ;
  assign _0995_ = \wr_pick$1026  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _0996_ = \fus_o_ok$101  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _0997_ = wrpick_INT_o_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _0998_ = \wr_pick$1044  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1049 ;
  assign _0999_ = \wr_pick$1044  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1000_ = \fus_o_ok$104  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
  assign _1001_ = wrpick_INT_o_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1002_ = \wr_pick$1066  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1071 ;
  assign _1003_ = \wr_pick$1066  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1004_ = \fus_o_ok$107  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
  assign _1005_ = wrpick_INT_o_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1006_ = \wr_pick$1086  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1091 ;
  assign _1007_ = \wr_pick$1086  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1008_ = \fus_o_ok$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
  assign _1009_ = wrpick_INT_o_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1010_ = \wr_pick$1106  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1111 ;
  assign _1011_ = \wr_pick$1106  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1012_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ;
  assign _1013_ = wrpick_INT_o_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1014_ = \wr_pick$1125  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1130 ;
  assign _1015_ = \wr_pick$1125  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1016_ = ea_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$38 ;
  assign _1017_ = wrpick_INT_o_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1018_ = \wr_pick$1143  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1147 ;
  assign _1019_ = \wr_pick$1143  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1020_ = fus_full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
  assign _1021_ = \fus_cu_wr__rel_o$93 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
  assign _1022_ = wrpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_full_cr_en_o;
  assign _1023_ = \wr_pick$1217  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1221 ;
  assign _1024_ = \wr_pick$1217  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_full_cr_en_o;
  assign _1025_ = fus_cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
  assign _1026_ = fus_cu_wr__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
  assign _1027_ = \fus_cu_wr__rel_o$93 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
  assign _1028_ = \fus_cu_wr__rel_o$99 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4];
  assign _1029_ = \fus_cu_wr__rel_o$105 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
  assign _1030_ = \fus_cu_wr__rel_o$108 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
  assign _1031_ = \fus_cu_wr__rel_o$111 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
  assign _1032_ = wrpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1033_ = \wr_pick$1245  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1249 ;
  assign _1034_ = \wr_pick$1245  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1035_ = \fus_cr_a_ok$122  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
  assign _1036_ = wrpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1037_ = \wr_pick$1265  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1269 ;
  assign _1038_ = \wr_pick$1265  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1039_ = \fus_cr_a_ok$123  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$23 ;
  assign _1040_ = wrpick_CR_cr_a_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1041_ = \wr_pick$1285  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1289 ;
  assign _1042_ = \wr_pick$1285  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1043_ = \fus_cr_a_ok$124  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
  assign _1044_ = wrpick_CR_cr_a_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1045_ = \wr_pick$1305  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1309 ;
  assign _1046_ = \wr_pick$1305  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1047_ = \fus_cr_a_ok$125  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
  assign _1048_ = wrpick_CR_cr_a_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1049_ = \wr_pick$1325  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1329 ;
  assign _1050_ = \wr_pick$1325  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1051_ = \fus_cr_a_ok$126  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
  assign _1052_ = wrpick_CR_cr_a_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_CR_cr_a_en_o;
  assign _1053_ = \wr_pick$1345  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1349 ;
  assign _1054_ = \wr_pick$1345  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_CR_cr_a_en_o;
  assign _1055_ = fus_xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
  assign _1056_ = fus_cu_wr__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
  assign _1057_ = \fus_cu_wr__rel_o$102 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1058_ = \fus_cu_wr__rel_o$111 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
  assign _1059_ = wrpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
  assign _1060_ = \wr_pick$1392  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1396 ;
  assign _1061_ = \wr_pick$1392  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
  assign _1062_ = \fus_xer_ca_ok$132  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _1063_ = wrpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
  assign _1064_ = \wr_pick$1408  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1412 ;
  assign _1065_ = \wr_pick$1408  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
  assign _1066_ = \fus_xer_ca_ok$133  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$35 ;
  assign _1067_ = wrpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ca_en_o;
  assign _1068_ = \wr_pick$1424  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1428 ;
  assign _1069_ = \wr_pick$1424  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ca_en_o;
  assign _1070_ = fus_xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
  assign _1071_ = fus_cu_wr__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
  assign _1072_ = \fus_cu_wr__rel_o$102 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1073_ = \fus_cu_wr__rel_o$105 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
  assign _1074_ = \fus_cu_wr__rel_o$108 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
  assign _1075_ = wrpick_XER_xer_ov_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
  assign _1076_ = \wr_pick$1458  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1462 ;
  assign _1077_ = \wr_pick$1458  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
  assign _1078_ = \fus_xer_ov_ok$136  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _1079_ = wrpick_XER_xer_ov_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
  assign _1080_ = \wr_pick$1474  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1478 ;
  assign _1081_ = \wr_pick$1474  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
  assign _1082_ = \fus_xer_ov_ok$137  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
  assign _1083_ = wrpick_XER_xer_ov_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
  assign _1084_ = \wr_pick$1490  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1494 ;
  assign _1085_ = \wr_pick$1490  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
  assign _1086_ = \fus_xer_ov_ok$138  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
  assign _1087_ = wrpick_XER_xer_ov_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_ov_en_o;
  assign _1088_ = \wr_pick$1506  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1510 ;
  assign _1089_ = \wr_pick$1506  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_ov_en_o;
  assign _1090_ = fus_xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
  assign _1091_ = fus_cu_wr__rel_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
  assign _1092_ = \fus_cu_wr__rel_o$102 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1093_ = \fus_cu_wr__rel_o$105 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
  assign _1094_ = \fus_cu_wr__rel_o$108 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
  assign _1095_ = wrpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
  assign _1096_ = \wr_pick$1542  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1546 ;
  assign _1097_ = \wr_pick$1542  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
  assign _1098_ = \fus_xer_so_ok$141  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _1099_ = wrpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
  assign _1100_ = \wr_pick$1558  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1562 ;
  assign _1101_ = \wr_pick$1558  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
  assign _1102_ = \fus_xer_so_ok$142  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$29 ;
  assign _1103_ = wrpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
  assign _1104_ = \wr_pick$1574  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1578 ;
  assign _1105_ = \wr_pick$1574  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
  assign _1106_ = \fus_xer_so_ok$143  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$32 ;
  assign _1107_ = wrpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_XER_xer_so_en_o;
  assign _1108_ = \wr_pick$1590  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1594 ;
  assign _1109_ = \wr_pick$1590  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_XER_xer_so_en_o;
  assign _1110_ = fus_fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
  assign _1111_ = \fus_cu_wr__rel_o$148 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
  assign _1112_ = \fus_cu_wr__rel_o$96 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
  assign _1113_ = \fus_cu_wr__rel_o$102 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1114_ = \fus_cu_wr__rel_o$148 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
  assign _1115_ = \fus_cu_wr__rel_o$96 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
  assign _1116_ = wrpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
  assign _1117_ = \wr_pick$1632  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1637 ;
  assign _1118_ = \wr_pick$1632  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
  assign _1119_ = \fus_fast1_ok$150  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
  assign _1120_ = wrpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
  assign _1121_ = \wr_pick$1651  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1655 ;
  assign _1122_ = \wr_pick$1651  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
  assign _1123_ = \fus_fast1_ok$151  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _1124_ = wrpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
  assign _1125_ = \wr_pick$1667  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1671 ;
  assign _1126_ = \wr_pick$1667  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
  assign _1127_ = fus_fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
  assign _1128_ = wrpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
  assign _1129_ = \wr_pick$1683  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1687 ;
  assign _1130_ = \wr_pick$1683  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
  assign _1131_ = \fus_fast2_ok$152  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
  assign _1132_ = wrpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_FAST_fast1_en_o;
  assign _1133_ = \wr_pick$1699  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1703 ;
  assign _1134_ = \wr_pick$1699  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_FAST_fast1_en_o;
  assign _1135_ = fus_nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$17 ;
  assign _1136_ = \fus_cu_wr__rel_o$148 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[2];
  assign _1137_ = \fus_cu_wr__rel_o$96 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
  assign _1138_ = wrpick_STATE_nia_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o;
  assign _1139_ = \wr_pick$1743  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1747 ;
  assign _1140_ = \wr_pick$1743  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o;
  assign _1141_ = \fus_nia_ok$158  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
  assign _1142_ = wrpick_STATE_nia_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_nia_en_o;
  assign _1143_ = \wr_pick$1759  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1763 ;
  assign _1144_ = \wr_pick$1759  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_nia_en_o;
  assign _1145_ = fus_msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$20 ;
  assign _1146_ = \fus_cu_wr__rel_o$96 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
  assign _1147_ = wrpick_STATE_msr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_STATE_msr_en_o;
  assign _1148_ = \wr_pick$1783  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1787 ;
  assign _1149_ = \wr_pick$1783  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_STATE_msr_en_o;
  assign _1150_ = fus_spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$26 ;
  assign _1151_ = \fus_cu_wr__rel_o$102 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1152_ = wrpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_SPR_spr1_en_o;
  assign _1153_ = \wr_pick$1803  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$1807 ;
  assign _1154_ = \wr_pick$1803  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_SPR_spr1_en_o;
  assign _1155_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 2'h2;
  assign _1156_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 7'h40;
  assign _1157_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 6'h20;
  assign _1158_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 8'h80;
  assign _1159_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 5'h10;
  assign _1160_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 11'h400;
  assign _1161_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 10'h200;
  assign _1162_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 9'h100;
  assign _1163_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 4'h8;
  assign _1164_ = core_core_fn_unit & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) 3'h4;
  assign _1165_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1166_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1167_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1168_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1169_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1170_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1171_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1172_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1173_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1174_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1175_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
  assign _1176_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
  assign _1177_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1178_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1179_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1180_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1181_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1182_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1183_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1184_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1185_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1186_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1187_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1188_ = fus_cu_rd__rel_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
  assign _1189_ = \$352  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1190_ = \$354  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$356 ;
  assign _1191_ = rdpick_INT_rabc_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1192_ = \fus_cu_rd__rel_o$40 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1193_ = \$364  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1194_ = \$366  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$368 ;
  assign _1195_ = rdpick_INT_rabc_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1196_ = \fus_cu_rd__rel_o$43 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
  assign _1197_ = \$376  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1198_ = \$378  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$380 ;
  assign _1199_ = rdpick_INT_rabc_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1200_ = \fus_cu_rd__rel_o$46 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
  assign _1201_ = \$388  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1202_ = \$390  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$392 ;
  assign _1203_ = rdpick_INT_rabc_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1204_ = \fus_cu_rd__rel_o$49 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
  assign _1205_ = \$400  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1206_ = \$402  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$404 ;
  assign _1207_ = rdpick_INT_rabc_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1208_ = \fus_cu_rd__rel_o$52 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
  assign _1209_ = \$412  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1210_ = \$414  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$416 ;
  assign _1211_ = rdpick_INT_rabc_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1212_ = \fus_cu_rd__rel_o$55 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
  assign _1213_ = \$424  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1214_ = \$426  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$428 ;
  assign _1215_ = rdpick_INT_rabc_o[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1216_ = \fus_cu_rd__rel_o$58 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
  assign _1217_ = \$436  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_0;
  assign _1218_ = \$438  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$440 ;
  assign _1219_ = rdpick_INT_rabc_o[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1220_ = \fus_cu_rd__rel_o$55 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
  assign _1221_ = \$448  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1;
  assign _1222_ = \$450  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$452 ;
  assign _1223_ = rdpick_INT_rabc_o[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1224_ = \fus_cu_rd__rel_o$58 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
  assign _1225_ = \$460  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_1;
  assign _1226_ = \$462  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$464 ;
  assign _1227_ = rdpick_INT_rabc_o[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1228_ = fus_cu_rd__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
  assign _1229_ = \$472  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1230_ = \$474  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$476 ;
  assign _1231_ = rdpick_INT_rabc_o[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1232_ = \fus_cu_rd__rel_o$40 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1233_ = \$484  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1234_ = \$486  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$488 ;
  assign _1235_ = rdpick_INT_rabc_o[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1236_ = \fus_cu_rd__rel_o$43 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
  assign _1237_ = \$496  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1238_ = \$498  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$500 ;
  assign _1239_ = rdpick_INT_rabc_o[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1240_ = \fus_cu_rd__rel_o$46 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
  assign _1241_ = \$508  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1242_ = \$510  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$512 ;
  assign _1243_ = rdpick_INT_rabc_o[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1244_ = \fus_cu_rd__rel_o$65 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1245_ = \$520  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1246_ = \$522  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$524 ;
  assign _1247_ = rdpick_INT_rabc_o[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1248_ = \fus_cu_rd__rel_o$49 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
  assign _1249_ = \$532  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1250_ = \$534  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$536 ;
  assign _1251_ = rdpick_INT_rabc_o[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1252_ = \fus_cu_rd__rel_o$52 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
  assign _1253_ = \$544  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1254_ = \$546  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$548 ;
  assign _1255_ = rdpick_INT_rabc_o[16] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1256_ = \fus_cu_rd__rel_o$55 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
  assign _1257_ = \$556  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1258_ = \$558  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$560 ;
  assign _1259_ = rdpick_INT_rabc_o[17] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1260_ = \fus_cu_rd__rel_o$58 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[9];
  assign _1261_ = \$568  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_INT_rabc_2;
  assign _1262_ = \$570  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$572 ;
  assign _1263_ = rdpick_INT_rabc_o[18] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_INT_rabc_en_o;
  assign _1264_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) core_core_oe_ok;
  assign _1265_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1266_ = core_core_rc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) core_core_rc_ok;
  assign _1267_ = fus_cu_rd__rel_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
  assign _1268_ = \$631  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1269_ = \$633  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$635 ;
  assign _1270_ = rdpick_XER_xer_so_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1271_ = \fus_cu_rd__rel_o$46 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[4];
  assign _1272_ = \$643  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1273_ = \$645  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$647 ;
  assign _1274_ = rdpick_XER_xer_so_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1275_ = \fus_cu_rd__rel_o$65 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1276_ = \$655  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1277_ = \$657  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$659 ;
  assign _1278_ = rdpick_XER_xer_so_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1279_ = \fus_cu_rd__rel_o$49 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[6];
  assign _1280_ = \$667  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1281_ = \$669  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$671 ;
  assign _1282_ = rdpick_XER_xer_so_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1283_ = \fus_cu_rd__rel_o$52 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[7];
  assign _1284_ = \$679  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1285_ = \$681  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$683 ;
  assign _1286_ = rdpick_XER_xer_so_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1287_ = \fus_cu_rd__rel_o$55 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
  assign _1288_ = \$691  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_so_0;
  assign _1289_ = \$693  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$695 ;
  assign _1290_ = rdpick_XER_xer_so_o[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_so_en_o;
  assign _1291_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1292_ = fus_cu_rd__rel_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[0];
  assign _1293_ = \$723  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
  assign _1294_ = \$725  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$727 ;
  assign _1295_ = rdpick_XER_xer_ca_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
  assign _1296_ = \fus_cu_rd__rel_o$65 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1297_ = \$735  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
  assign _1298_ = \$737  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$739 ;
  assign _1299_ = rdpick_XER_xer_ca_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
  assign _1300_ = \fus_cu_rd__rel_o$55 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[8];
  assign _1301_ = \$747  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ca_0;
  assign _1302_ = \$749  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$751 ;
  assign _1303_ = rdpick_XER_xer_ca_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ca_en_o;
  assign _1304_ = core_core_oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" *) core_core_oe_ok;
  assign _1305_ = core_xer_in & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
  assign _1306_ = \fus_cu_rd__rel_o$65 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1307_ = \$773  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_XER_xer_ov_0;
  assign _1308_ = \$775  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$777 ;
  assign _1309_ = rdpick_XER_xer_ov_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_XER_xer_ov_en_o;
  assign _1310_ = \fus_cu_rd__rel_o$40 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1311_ = \$785  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_full_cr_0;
  assign _1312_ = \$787  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$789 ;
  assign _1313_ = rdpick_CR_full_cr_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_full_cr_en_o;
  assign _1314_ = \fus_cu_rd__rel_o$40 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1315_ = \$797  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0;
  assign _1316_ = \$799  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$801 ;
  assign _1317_ = rdpick_CR_cr_a_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o;
  assign _1318_ = \fus_cu_rd__rel_o$81 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
  assign _1319_ = \$813  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_a_0;
  assign _1320_ = \$815  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$817 ;
  assign _1321_ = rdpick_CR_cr_a_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_a_en_o;
  assign _1322_ = \fus_cu_rd__rel_o$40 [4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1323_ = \$832  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_b_0;
  assign _1324_ = \$834  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$836 ;
  assign _1325_ = rdpick_CR_cr_b_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_b_en_o;
  assign _1326_ = \fus_cu_rd__rel_o$40 [5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[1];
  assign _1327_ = \$848  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_CR_cr_c_0;
  assign _1328_ = \$850  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$852 ;
  assign _1329_ = rdpick_CR_cr_c_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_CR_cr_c_en_o;
  assign _1330_ = \fus_cu_rd__rel_o$81 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
  assign _1331_ = \$864  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
  assign _1332_ = \$866  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$868 ;
  assign _1333_ = rdpick_FAST_fast1_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
  assign _1334_ = \fus_cu_rd__rel_o$43 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
  assign _1335_ = \$876  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
  assign _1336_ = \$878  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$880 ;
  assign _1337_ = rdpick_FAST_fast1_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
  assign _1338_ = \fus_cu_rd__rel_o$65 [2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1339_ = \$888  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_0;
  assign _1340_ = \$890  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$892 ;
  assign _1341_ = rdpick_FAST_fast1_o[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
  assign _1342_ = \fus_cu_rd__rel_o$81 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[2];
  assign _1343_ = \$900  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1;
  assign _1344_ = \$902  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$904 ;
  assign _1345_ = rdpick_FAST_fast1_o[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
  assign _1346_ = \fus_cu_rd__rel_o$43 [3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[3];
  assign _1347_ = \$912  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_FAST_fast1_1;
  assign _1348_ = \$914  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$916 ;
  assign _1349_ = rdpick_FAST_fast1_o[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_FAST_fast1_en_o;
  assign _1350_ = \fus_cu_rd__rel_o$65 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) fu_enable[5];
  assign _1351_ = \$934  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291" *) rdflag_SPR_spr1_0;
  assign _1352_ = \$936  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) \$938 ;
  assign _1353_ = rdpick_SPR_spr1_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297" *) rdpick_SPR_spr1_en_o;
  assign _1354_ = fus_o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) fus_cu_busy_o;
  assign _1355_ = fus_cu_wr__rel_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[0];
  assign _1356_ = \fus_cu_wr__rel_o$93 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[1];
  assign _1357_ = \fus_cu_wr__rel_o$96 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[3];
  assign _1358_ = \fus_cu_wr__rel_o$99 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[4];
  assign _1359_ = \fus_cu_wr__rel_o$102 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[5];
  assign _1360_ = \fus_cu_wr__rel_o$105 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[6];
  assign _1361_ = \fus_cu_wr__rel_o$108 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[7];
  assign _1362_ = \fus_cu_wr__rel_o$111 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[8];
  assign _1363_ = \fus_cu_wr__rel_o$113 [0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9];
  assign _1364_ = \fus_cu_wr__rel_o$113 [1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:418" *) fu_enable[9];
  assign _1365_ = wrpick_INT_o_o[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1366_ = wr_pick & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$972 ;
  assign _1367_ = wr_pick & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1368_ = \fus_o_ok$92  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:414" *) \fus_cu_busy_o$14 ;
  assign _1369_ = wrpick_INT_o_o[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:422" *) wrpick_INT_o_en_o;
  assign _1370_ = \wr_pick$986  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$991 ;
  assign _1371_ = \wr_pick$986  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:430" *) wrpick_INT_o_en_o;
  assign _1372_ = \$231  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1373_ = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2;
  assign _1374_ = \$243  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1375_ = \$259  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1376_ = \$273  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1377_ = \$285  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
  assign _1378_ = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2;
  assign _1379_ = \$293  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1380_ = \$303  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1381_ = \$317  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1382_ = \$331  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1383_ = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2;
  assign _1384_ = \$343  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1385_ = \$621  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) 1'h1;
  assign _1386_ = core_core_input_carry == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" *) 2'h2;
  assign _1387_ = \$717  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) 3'h4;
  assign _1388_ = \$767  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) 2'h2;
  assign _1389_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1445 ;
  assign _1390_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1609 ;
  assign _1391_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1617 ;
  assign _1392_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \$1776 ;
  assign _1393_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) \addr_en$1794 ;
  assign _1394_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$712 ;
  assign _1395_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$762 ;
  assign _1396_ = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0;
  assign _1397_ = counter != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *) 1'h0;
  assign _1398_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1008 ;
  assign _1399_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1029 ;
  assign _1400_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1047 ;
  assign _1401_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1069 ;
  assign _1402_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1089 ;
  assign _1403_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1109 ;
  assign _1404_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1128 ;
  assign _1405_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1146 ;
  assign _1406_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1220 ;
  assign _1407_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1248 ;
  assign _1408_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1268 ;
  assign _1409_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1288 ;
  assign _1410_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1308 ;
  assign _1411_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1328 ;
  assign _1412_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1348 ;
  assign _1413_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1395 ;
  assign _1414_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1411 ;
  assign _1415_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1427 ;
  assign _1416_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1461 ;
  assign _1417_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1477 ;
  assign _1418_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1493 ;
  assign _1419_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1509 ;
  assign _1420_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1545 ;
  assign _1421_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1561 ;
  assign _1422_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1577 ;
  assign _1423_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1593 ;
  assign _1424_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1635 ;
  assign _1425_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1654 ;
  assign _1426_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1670 ;
  assign _1427_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1686 ;
  assign _1428_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1702 ;
  assign _1429_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1746 ;
  assign _1430_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1762 ;
  assign _1431_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1786 ;
  assign _1432_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$1806 ;
  assign _1433_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$247 , \$239 , core_reg2_ok, core_reg1_ok };
  assign _1434_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \core_cr_in2_ok$2 , core_cr_in2_ok, core_cr_in1_ok, core_core_cr_rd_ok, core_reg2_ok, core_reg1_ok };
  assign _1435_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_cr_in1_ok, core_fast2_ok, core_fast1_ok };
  assign _1436_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_fast2_ok, core_fast1_ok, core_reg2_ok, core_reg1_ok };
  assign _1437_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$267 , core_reg2_ok, core_reg1_ok };
  assign _1438_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$297 , \$289 , \$281 , core_fast1_ok, core_spr1_ok, core_reg1_ok };
  assign _1439_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$311 , core_reg2_ok, core_reg1_ok };
  assign _1440_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$325 , core_reg2_ok, core_reg1_ok };
  assign _1441_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { \$347 , \$339 , core_reg3_ok, core_reg2_ok, core_reg1_ok };
  assign _1442_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:230" *) { core_reg3_ok, core_reg2_ok, core_reg1_ok };
  assign _1443_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_0;
  assign _1444_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_1;
  assign _1445_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_2;
  assign _1446_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_3;
  assign _1447_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_4;
  assign _1448_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_5;
  assign _1449_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_6;
  assign _1450_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_7;
  assign _1451_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_8;
  assign _1452_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_9;
  assign _1453_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_alu0_10;
  assign _1454_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_cr0_11;
  assign _1455_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_trap0_12;
  assign _1456_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_logical0_13;
  assign _1457_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_spr0_14;
  assign _1458_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_div0_15;
  assign _1459_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_mul0_16;
  assign _1460_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_shiftrot0_17;
  assign _1461_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_INT_rabc_ldst0_18;
  assign _1462_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_alu0_0;
  assign _1463_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_logical0_1;
  assign _1464_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_spr0_2;
  assign _1465_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_div0_3;
  assign _1466_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_mul0_4;
  assign _1467_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_so_shiftrot0_5;
  assign _1468_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_alu0_0;
  assign _1469_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_spr0_1;
  assign _1470_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ca_shiftrot0_2;
  assign _1471_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_XER_xer_ov_spr0_0;
  assign _1472_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_full_cr_cr0_0;
  assign _1473_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_cr0_0;
  assign _1474_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_a_branch0_1;
  assign _1475_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_b_cr0_0;
  assign _1476_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_CR_cr_c_cr0_0;
  assign _1477_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_0;
  assign _1478_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_1;
  assign _1479_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_spr0_2;
  assign _1480_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_branch0_3;
  assign _1481_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_FAST_fast1_trap0_4;
  assign _1482_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292" *) dp_SPR_spr1_spr0_0;
  assign _1483_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wr_pick_dly;
  assign _1484_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \wr_pick_dly$989 ;
  assign _1485_ = fus_dest1_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$115 ;
  assign _1486_ = \fus_dest1_o$117  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$118 ;
  assign _1487_ = \fus_dest1_o$116  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1160 ;
  assign _1488_ = \$1158  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1162 ;
  assign _1489_ = \fus_dest1_o$119  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest1_o$120 ;
  assign _1490_ = { o_ok, fus_o } | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) { ea_ok, fus_ea };
  assign _1491_ = \fus_dest1_o$121  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1168 ;
  assign _1492_ = \$1166  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1170 ;
  assign _1493_ = \$1164  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1172 ;
  assign _1494_ = addr_en | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1000 ;
  assign _1495_ = \addr_en$1039  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1061 ;
  assign _1496_ = \addr_en$1021  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1179 ;
  assign _1497_ = \$1177  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1181 ;
  assign _1498_ = \addr_en$1081  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1101 ;
  assign _1499_ = \addr_en$1138  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1154 ;
  assign _1500_ = \addr_en$1120  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1187 ;
  assign _1501_ = \$1185  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1189 ;
  assign _1502_ = \$1183  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1191 ;
  assign _1503_ = wp | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$997 ;
  assign _1504_ = \wp$1036  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1058 ;
  assign _1505_ = \wp$1018  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1197 ;
  assign _1506_ = \$1195  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1199 ;
  assign _1507_ = \wp$1078  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1098 ;
  assign _1508_ = \wp$1135  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1151 ;
  assign _1509_ = \wp$1117  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1205 ;
  assign _1510_ = \$1203  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1207 ;
  assign _1511_ = \$1201  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1209 ;
  assign _1512_ = fus_dest3_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$128 ;
  assign _1513_ = \fus_dest2_o$127  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1363 ;
  assign _1514_ = \fus_dest2_o$130  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$131 ;
  assign _1515_ = \fus_dest2_o$129  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1367 ;
  assign _1516_ = \$1365  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1369 ;
  assign _1517_ = \addr_en$1276  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1296 ;
  assign _1518_ = \addr_en$1256  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1374 ;
  assign _1519_ = \addr_en$1336  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1356 ;
  assign _1520_ = \addr_en$1316  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1378 ;
  assign _1521_ = \$1376  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1380 ;
  assign _1522_ = fus_dest6_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$135 ;
  assign _1523_ = \fus_dest3_o$134  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1438 ;
  assign _1524_ = \addr_en$1419  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1435 ;
  assign _1525_ = \addr_en$1403  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1443 ;
  assign _1526_ = fus_dest4_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) fus_dest5_o;
  assign _1527_ = \fus_dest3_o$139  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$140 ;
  assign _1528_ = \$1520  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1522 ;
  assign _1529_ = \addr_en$1469  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1485 ;
  assign _1530_ = \addr_en$1501  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1517 ;
  assign _1531_ = \$1526  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1528 ;
  assign _1532_ = \fus_dest5_o$144  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$145 ;
  assign _1533_ = \fus_dest4_o$146  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$147 ;
  assign _1534_ = \$1605  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1607 ;
  assign _1535_ = \addr_en$1553  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1569 ;
  assign _1536_ = \addr_en$1585  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1601 ;
  assign _1537_ = \$1613  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1615 ;
  assign _1538_ = \fus_dest1_o$153  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest2_o$154 ;
  assign _1539_ = \fus_dest2_o$156  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest3_o$157 ;
  assign _1540_ = \fus_dest3_o$155  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1715 ;
  assign _1541_ = \$1713  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1717 ;
  assign _1542_ = \addr_en$1646  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1662 ;
  assign _1543_ = \addr_en$1694  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1710 ;
  assign _1544_ = \addr_en$1678  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1723 ;
  assign _1545_ = \$1721  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1725 ;
  assign _1546_ = \wp$1643  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1659 ;
  assign _1547_ = \wp$1691  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \wp$1707 ;
  assign _1548_ = \wp$1675  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1731 ;
  assign _1549_ = \$1729  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$1733 ;
  assign _1550_ = \fus_dest3_o$159  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \fus_dest4_o$160 ;
  assign _1551_ = \addr_en$1754  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) \addr_en$1770 ;
  assign _1552_ = \$229  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$233 ;
  assign _1553_ = \$235  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$237 ;
  assign _1554_ = \$241  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$245 ;
  assign _1555_ = \$257  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$261 ;
  assign _1556_ = \$263  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$265 ;
  assign _1557_ = \$271  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$275 ;
  assign _1558_ = \$277  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$279 ;
  assign _1559_ = \$283  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$287 ;
  assign _1560_ = \$291  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$295 ;
  assign _1561_ = \$301  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$305 ;
  assign _1562_ = \$307  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$309 ;
  assign _1563_ = \$315  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$319 ;
  assign _1564_ = \$321  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$323 ;
  assign _1565_ = \$329  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$333 ;
  assign _1566_ = \$335  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$337 ;
  assign _1567_ = \$341  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$345 ;
  assign _1568_ = addr_en_INT_rabc_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_cr0_1;
  assign _1569_ = addr_en_INT_rabc_trap0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_3;
  assign _1570_ = \$581  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$583 ;
  assign _1571_ = addr_en_INT_rabc_div0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_mul0_5;
  assign _1572_ = addr_en_INT_rabc_ldst0_7 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_shiftrot0_8;
  assign _1573_ = addr_en_INT_rabc_shiftrot0_6 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$589 ;
  assign _1574_ = \$587  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$591 ;
  assign _1575_ = \$585  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$593 ;
  assign _1576_ = addr_en_INT_rabc_ldst0_9 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_alu0_10;
  assign _1577_ = addr_en_INT_rabc_trap0_12 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_logical0_13;
  assign _1578_ = addr_en_INT_rabc_cr0_11 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$599 ;
  assign _1579_ = \$597  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$601 ;
  assign _1580_ = addr_en_INT_rabc_spr0_14 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_div0_15;
  assign _1581_ = addr_en_INT_rabc_shiftrot0_17 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_INT_rabc_ldst0_18;
  assign _1582_ = addr_en_INT_rabc_mul0_16 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$607 ;
  assign _1583_ = \$605  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$609 ;
  assign _1584_ = \$603  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$611 ;
  assign _1585_ = \$595  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$613 ;
  assign _1586_ = \$619  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" *) \$623 ;
  assign _1587_ = \$625  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" *) \$627 ;
  assign _1588_ = addr_en_XER_xer_so_logical0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_spr0_2;
  assign _1589_ = addr_en_XER_xer_so_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$704 ;
  assign _1590_ = addr_en_XER_xer_so_mul0_4 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_so_shiftrot0_5;
  assign _1591_ = addr_en_XER_xer_so_div0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$708 ;
  assign _1592_ = \$706  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$710 ;
  assign _1593_ = \$715  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" *) \$719 ;
  assign _1594_ = addr_en_XER_xer_ca_spr0_1 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_XER_xer_ca_shiftrot0_2;
  assign _1595_ = addr_en_XER_xer_ca_alu0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$760 ;
  assign _1596_ = \$765  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" *) \$769 ;
  assign _1597_ = addr_en_CR_cr_a_cr0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_CR_cr_a_branch0_1;
  assign _1598_ = addr_en_FAST_fast1_branch0_0 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_1;
  assign _1599_ = addr_en_FAST_fast1_branch0_3 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) addr_en_FAST_fast1_trap0_4;
  assign _1600_ = addr_en_FAST_fast1_spr0_2 | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$926 ;
  assign _1601_ = \$924  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$928 ;
  assign _1602_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) _1389_;
  assign _1603_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) _1390_;
  assign _1604_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) _1391_;
  assign _1605_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) _1392_;
  assign _1606_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:428" *) _1393_;
  assign _1607_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) _1394_;
  assign _1608_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) _1395_;
  assign _1609_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$182 ;
  assign _1610_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$186 ;
  assign _1611_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$190 ;
  assign _1612_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$194 ;
  assign _1613_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$198 ;
  assign _1614_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$202 ;
  assign _1615_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$206 ;
  assign _1616_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$210 ;
  assign _1617_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$214 ;
  assign _1618_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" *) \$218 ;
  assign _1619_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_INT_rabc_ldst0_18, rp_INT_rabc_shiftrot0_17, rp_INT_rabc_mul0_16, rp_INT_rabc_div0_15, rp_INT_rabc_spr0_14, rp_INT_rabc_logical0_13, rp_INT_rabc_trap0_12, rp_INT_rabc_cr0_11, rp_INT_rabc_alu0_10, rp_INT_rabc_ldst0_9, rp_INT_rabc_shiftrot0_8, rp_INT_rabc_ldst0_7, rp_INT_rabc_shiftrot0_6, rp_INT_rabc_mul0_5, rp_INT_rabc_div0_4, rp_INT_rabc_logical0_3, rp_INT_rabc_trap0_2, rp_INT_rabc_cr0_1, rp_INT_rabc_alu0_0 };
  assign _1620_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) { rp_FAST_fast1_trap0_4, rp_FAST_fast1_branch0_3, rp_FAST_fast1_spr0_2, rp_FAST_fast1_trap0_1, rp_FAST_fast1_branch0_0 };
  assign _1621_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:326" *) rp_SPR_spr1_spr0_0;
  assign _1622_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1257 ;
  assign _1623_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1277 ;
  assign _1624_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1297 ;
  assign _1625_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1317 ;
  assign _1626_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1337 ;
  assign _1627_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) \$1357 ;
  assign _1628_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$807 ;
  assign _1629_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) \$823 ;
  assign _1630_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) \$842 ;
  assign _1631_ = 1'h1 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \$858 ;
  assign _1632_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1633_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1634_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1635_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1636_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1637_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" *) core_cr_out;
  assign _1638_ = counter - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:200" *) 1'h1;
  assign _1639_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1;
  assign _1640_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" *) core_cr_in1;
  assign _1641_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" *) core_cr_in2;
  assign _1642_ = 3'h7 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" *) \core_cr_in2$1 ;
  assign _1643_ = \wp$997  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1644_ = \wp$1018  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1645_ = \wp$1036  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1646_ = \wp$1058  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1647_ = \wp$1078  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1648_ = \wp$1098  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1649_ = \wp$1117  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1650_ = \wp$1135  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  assign _1651_ = \wp$1151  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_ea : 7'h00;
  assign _1652_ = \wp$1225  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_core_cr_wr : 8'h00;
  assign _1653_ = \wp$1253  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1259  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1654_ = \wp$1273  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1279  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1655_ = \wp$1293  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1299  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1656_ = \wp$1313  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1319  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1657_ = \wp$1333  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1339  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1658_ = \wp$1353  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) \$1359  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1659_ = \wp$1400  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
  assign _1660_ = \wp$1416  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
  assign _1661_ = \wp$1432  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
  assign _1662_ = \wp$1466  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
  assign _1663_ = \wp$1482  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
  assign _1664_ = \wp$1498  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
  assign _1665_ = \wp$1514  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 3'h4 : 3'h0;
  assign _1666_ = \wp$1550  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1667_ = \wp$1566  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1668_ = \wp$1582  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1669_ = \wp$1598  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1670_ = \wp$1643  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
  assign _1671_ = \wp$1659  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
  assign _1672_ = \wp$1675  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto1 : 3'h0;
  assign _1673_ = \wp$1691  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0;
  assign _1674_ = \wp$1707  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_fasto2 : 3'h0;
  assign _1675_ = \wp$1751  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1676_ = \wp$1767  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 1'h1 : 1'h0;
  assign _1677_ = \wp$1791  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) 2'h2 : 2'h0;
  assign _1678_ = \wp$1811  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_spro : 10'h000;
  assign _1679_ = rp_INT_rabc_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1680_ = rp_INT_rabc_cr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1681_ = rp_INT_rabc_trap0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1682_ = rp_INT_rabc_logical0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1683_ = rp_INT_rabc_div0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1684_ = rp_INT_rabc_mul0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1685_ = rp_INT_rabc_shiftrot0_6 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1686_ = rp_INT_rabc_ldst0_7 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg2 : 7'h00;
  assign _1687_ = rp_INT_rabc_shiftrot0_8 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00;
  assign _1688_ = rp_INT_rabc_ldst0_9 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg3 : 7'h00;
  assign _1689_ = rp_INT_rabc_alu0_10 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1690_ = rp_INT_rabc_cr0_11 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1691_ = rp_INT_rabc_trap0_12 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1692_ = rp_INT_rabc_logical0_13 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1693_ = rp_INT_rabc_spr0_14 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1694_ = rp_INT_rabc_div0_15 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1695_ = rp_INT_rabc_mul0_16 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1696_ = rp_INT_rabc_shiftrot0_17 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1697_ = rp_INT_rabc_ldst0_18 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_reg1 : 7'h00;
  assign _1698_ = rp_XER_xer_so_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1699_ = rp_XER_xer_so_logical0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1700_ = rp_XER_xer_so_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1701_ = rp_XER_xer_so_div0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1702_ = rp_XER_xer_so_mul0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1703_ = rp_XER_xer_so_shiftrot0_5 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 1'h1 : 1'h0;
  assign _1704_ = rp_XER_xer_ca_alu0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
  assign _1705_ = rp_XER_xer_ca_spr0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
  assign _1706_ = rp_XER_xer_ca_shiftrot0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 2'h2 : 2'h0;
  assign _1707_ = rp_XER_xer_ov_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) 3'h4 : 3'h0;
  assign _1708_ = rp_CR_full_cr_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_core_cr_rd : 8'h00;
  assign _1709_ = rp_CR_cr_a_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$809  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1710_ = rp_CR_cr_a_branch0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$825  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1711_ = rp_CR_cr_b_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$844  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1712_ = rp_CR_cr_c_cr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) \$860  : 256'h0000000000000000000000000000000000000000000000000000000000000000;
  assign _1713_ = rp_FAST_fast1_branch0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
  assign _1714_ = rp_FAST_fast1_trap0_1 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
  assign _1715_ = rp_FAST_fast1_spr0_2 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast1 : 3'h0;
  assign _1716_ = rp_FAST_fast1_branch0_3 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0;
  assign _1717_ = rp_FAST_fast1_trap0_4 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_fast2 : 3'h0;
  assign _1718_ = rp_SPR_spr1_spr0_0 ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299" *) core_spr1 : 10'h000;
  assign _1719_ = wp ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:431" *) core_rego : 7'h00;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42790.6-42807.4" *)
  cr cr (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .data_i(cr_data_i),
    .full_rd2__data_o(full_rd2__data_o),
    .full_rd2__ren(full_rd2__ren),
    .full_rd__data_o(cr_full_rd__data_o),
    .full_rd__ren(cr_full_rd__ren),
    .full_wr__data_i(cr_full_wr__data_i),
    .full_wr__wen(cr_full_wr__wen),
    .src1__data_o(cr_src1__data_o),
    .src1__ren(cr_src1__ren),
    .src2__data_o(cr_src2__data_o),
    .src2__ren(cr_src2__ren),
    .src3__data_o(cr_src3__data_o),
    .src3__ren(cr_src3__ren),
    .wen(cr_wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42808.11-42830.4" *)
  dec_ALU dec_ALU (
    .ALU__data_len(dec_ALU_ALU__data_len),
    .ALU__fn_unit(dec_ALU_ALU__fn_unit),
    .ALU__imm_data__data(dec_ALU_ALU__imm_data__data),
    .ALU__imm_data__ok(dec_ALU_ALU__imm_data__ok),
    .ALU__input_carry(dec_ALU_ALU__input_carry),
    .ALU__insn(dec_ALU_ALU__insn),
    .ALU__insn_type(dec_ALU_ALU__insn_type),
    .ALU__invert_in(dec_ALU_ALU__invert_in),
    .ALU__invert_out(dec_ALU_ALU__invert_out),
    .ALU__is_32bit(dec_ALU_ALU__is_32bit),
    .ALU__is_signed(dec_ALU_ALU__is_signed),
    .ALU__oe__oe(dec_ALU_ALU__oe__oe),
    .ALU__oe__ok(dec_ALU_ALU__oe__ok),
    .ALU__output_carry(dec_ALU_ALU__output_carry),
    .ALU__rc__ok(dec_ALU_ALU__rc__ok),
    .ALU__rc__rc(dec_ALU_ALU__rc__rc),
    .ALU__write_cr0(dec_ALU_ALU__write_cr0),
    .ALU__zero_a(dec_ALU_ALU__zero_a),
    .bigendian(dec_ALU_bigendian),
    .raw_opcode_in(dec_ALU_raw_opcode_in),
    .sv_a_nz(dec_ALU_sv_a_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42831.14-42843.4" *)
  dec_BRANCH dec_BRANCH (
    .BRANCH__cia(dec_BRANCH_BRANCH__cia),
    .BRANCH__fn_unit(dec_BRANCH_BRANCH__fn_unit),
    .BRANCH__imm_data__data(dec_BRANCH_BRANCH__imm_data__data),
    .BRANCH__imm_data__ok(dec_BRANCH_BRANCH__imm_data__ok),
    .BRANCH__insn(dec_BRANCH_BRANCH__insn),
    .BRANCH__insn_type(dec_BRANCH_BRANCH__insn_type),
    .BRANCH__is_32bit(dec_BRANCH_BRANCH__is_32bit),
    .BRANCH__lk(dec_BRANCH_BRANCH__lk),
    .bigendian(dec_BRANCH_bigendian),
    .core_pc(core_pc),
    .raw_opcode_in(dec_BRANCH_raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42844.10-42850.4" *)
  dec_CR dec_CR (
    .CR__fn_unit(dec_CR_CR__fn_unit),
    .CR__insn(dec_CR_CR__insn),
    .CR__insn_type(dec_CR_CR__insn_type),
    .bigendian(dec_CR_bigendian),
    .raw_opcode_in(dec_CR_raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42851.11-42873.4" *)
  dec_DIV dec_DIV (
    .DIV__data_len(dec_DIV_DIV__data_len),
    .DIV__fn_unit(dec_DIV_DIV__fn_unit),
    .DIV__imm_data__data(dec_DIV_DIV__imm_data__data),
    .DIV__imm_data__ok(dec_DIV_DIV__imm_data__ok),
    .DIV__input_carry(dec_DIV_DIV__input_carry),
    .DIV__insn(dec_DIV_DIV__insn),
    .DIV__insn_type(dec_DIV_DIV__insn_type),
    .DIV__invert_in(dec_DIV_DIV__invert_in),
    .DIV__invert_out(dec_DIV_DIV__invert_out),
    .DIV__is_32bit(dec_DIV_DIV__is_32bit),
    .DIV__is_signed(dec_DIV_DIV__is_signed),
    .DIV__oe__oe(dec_DIV_DIV__oe__oe),
    .DIV__oe__ok(dec_DIV_DIV__oe__ok),
    .DIV__output_carry(dec_DIV_DIV__output_carry),
    .DIV__rc__ok(dec_DIV_DIV__rc__ok),
    .DIV__rc__rc(dec_DIV_DIV__rc__rc),
    .DIV__write_cr0(dec_DIV_DIV__write_cr0),
    .DIV__zero_a(dec_DIV_DIV__zero_a),
    .bigendian(dec_DIV_bigendian),
    .raw_opcode_in(dec_DIV_raw_opcode_in),
    .sv_a_nz(dec_DIV_sv_a_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42874.12-42894.4" *)
  dec_LDST dec_LDST (
    .LDST__byte_reverse(dec_LDST_LDST__byte_reverse),
    .LDST__data_len(dec_LDST_LDST__data_len),
    .LDST__fn_unit(dec_LDST_LDST__fn_unit),
    .LDST__imm_data__data(dec_LDST_LDST__imm_data__data),
    .LDST__imm_data__ok(dec_LDST_LDST__imm_data__ok),
    .LDST__insn(dec_LDST_LDST__insn),
    .LDST__insn_type(dec_LDST_LDST__insn_type),
    .LDST__is_32bit(dec_LDST_LDST__is_32bit),
    .LDST__is_signed(dec_LDST_LDST__is_signed),
    .LDST__ldst_mode(dec_LDST_LDST__ldst_mode),
    .LDST__oe__oe(dec_LDST_LDST__oe__oe),
    .LDST__oe__ok(dec_LDST_LDST__oe__ok),
    .LDST__rc__ok(dec_LDST_LDST__rc__ok),
    .LDST__rc__rc(dec_LDST_LDST__rc__rc),
    .LDST__sign_extend(dec_LDST_LDST__sign_extend),
    .LDST__zero_a(dec_LDST_LDST__zero_a),
    .bigendian(dec_LDST_bigendian),
    .raw_opcode_in(dec_LDST_raw_opcode_in),
    .sv_a_nz(dec_LDST_sv_a_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42895.15-42917.4" *)
  dec_LOGICAL dec_LOGICAL (
    .LOGICAL__data_len(dec_LOGICAL_LOGICAL__data_len),
    .LOGICAL__fn_unit(dec_LOGICAL_LOGICAL__fn_unit),
    .LOGICAL__imm_data__data(dec_LOGICAL_LOGICAL__imm_data__data),
    .LOGICAL__imm_data__ok(dec_LOGICAL_LOGICAL__imm_data__ok),
    .LOGICAL__input_carry(dec_LOGICAL_LOGICAL__input_carry),
    .LOGICAL__insn(dec_LOGICAL_LOGICAL__insn),
    .LOGICAL__insn_type(dec_LOGICAL_LOGICAL__insn_type),
    .LOGICAL__invert_in(dec_LOGICAL_LOGICAL__invert_in),
    .LOGICAL__invert_out(dec_LOGICAL_LOGICAL__invert_out),
    .LOGICAL__is_32bit(dec_LOGICAL_LOGICAL__is_32bit),
    .LOGICAL__is_signed(dec_LOGICAL_LOGICAL__is_signed),
    .LOGICAL__oe__oe(dec_LOGICAL_LOGICAL__oe__oe),
    .LOGICAL__oe__ok(dec_LOGICAL_LOGICAL__oe__ok),
    .LOGICAL__output_carry(dec_LOGICAL_LOGICAL__output_carry),
    .LOGICAL__rc__ok(dec_LOGICAL_LOGICAL__rc__ok),
    .LOGICAL__rc__rc(dec_LOGICAL_LOGICAL__rc__rc),
    .LOGICAL__write_cr0(dec_LOGICAL_LOGICAL__write_cr0),
    .LOGICAL__zero_a(dec_LOGICAL_LOGICAL__zero_a),
    .bigendian(dec_LOGICAL_bigendian),
    .raw_opcode_in(dec_LOGICAL_raw_opcode_in),
    .sv_a_nz(dec_LOGICAL_sv_a_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42918.11-42933.4" *)
  dec_MUL dec_MUL (
    .MUL__fn_unit(dec_MUL_MUL__fn_unit),
    .MUL__imm_data__data(dec_MUL_MUL__imm_data__data),
    .MUL__imm_data__ok(dec_MUL_MUL__imm_data__ok),
    .MUL__insn(dec_MUL_MUL__insn),
    .MUL__insn_type(dec_MUL_MUL__insn_type),
    .MUL__is_32bit(dec_MUL_MUL__is_32bit),
    .MUL__is_signed(dec_MUL_MUL__is_signed),
    .MUL__oe__oe(dec_MUL_MUL__oe__oe),
    .MUL__oe__ok(dec_MUL_MUL__oe__ok),
    .MUL__rc__ok(dec_MUL_MUL__rc__ok),
    .MUL__rc__rc(dec_MUL_MUL__rc__rc),
    .MUL__write_cr0(dec_MUL_MUL__write_cr0),
    .bigendian(dec_MUL_bigendian),
    .raw_opcode_in(dec_MUL_raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42934.17-42954.4" *)
  dec_SHIFT_ROT dec_SHIFT_ROT (
    .SHIFT_ROT__fn_unit(dec_SHIFT_ROT_SHIFT_ROT__fn_unit),
    .SHIFT_ROT__imm_data__data(dec_SHIFT_ROT_SHIFT_ROT__imm_data__data),
    .SHIFT_ROT__imm_data__ok(dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok),
    .SHIFT_ROT__input_carry(dec_SHIFT_ROT_SHIFT_ROT__input_carry),
    .SHIFT_ROT__input_cr(dec_SHIFT_ROT_SHIFT_ROT__input_cr),
    .SHIFT_ROT__insn(dec_SHIFT_ROT_SHIFT_ROT__insn),
    .SHIFT_ROT__insn_type(dec_SHIFT_ROT_SHIFT_ROT__insn_type),
    .SHIFT_ROT__invert_in(dec_SHIFT_ROT_SHIFT_ROT__invert_in),
    .SHIFT_ROT__is_32bit(dec_SHIFT_ROT_SHIFT_ROT__is_32bit),
    .SHIFT_ROT__is_signed(dec_SHIFT_ROT_SHIFT_ROT__is_signed),
    .SHIFT_ROT__oe__oe(dec_SHIFT_ROT_SHIFT_ROT__oe__oe),
    .SHIFT_ROT__oe__ok(dec_SHIFT_ROT_SHIFT_ROT__oe__ok),
    .SHIFT_ROT__output_carry(dec_SHIFT_ROT_SHIFT_ROT__output_carry),
    .SHIFT_ROT__output_cr(dec_SHIFT_ROT_SHIFT_ROT__output_cr),
    .SHIFT_ROT__rc__ok(dec_SHIFT_ROT_SHIFT_ROT__rc__ok),
    .SHIFT_ROT__rc__rc(dec_SHIFT_ROT_SHIFT_ROT__rc__rc),
    .SHIFT_ROT__write_cr0(dec_SHIFT_ROT_SHIFT_ROT__write_cr0),
    .bigendian(dec_SHIFT_ROT_bigendian),
    .raw_opcode_in(dec_SHIFT_ROT_raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42955.11-42962.4" *)
  dec_SPR dec_SPR (
    .SPR__fn_unit(dec_SPR_SPR__fn_unit),
    .SPR__insn(dec_SPR_SPR__insn),
    .SPR__insn_type(dec_SPR_SPR__insn_type),
    .SPR__is_32bit(dec_SPR_SPR__is_32bit),
    .bigendian(dec_SPR_bigendian),
    .raw_opcode_in(dec_SPR_raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42963.8-42978.4" *)
  fast fast (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest1__addr(fast_dest1__addr),
    .dest1__data_i(fast_dest1__data_i),
    .dest1__wen(fast_dest1__wen),
    .issue__addr(issue__addr),
    .\issue__addr$1 (\issue__addr$12 ),
    .issue__data_i(issue__data_i),
    .issue__data_o(issue__data_o),
    .issue__ren(issue__ren),
    .issue__wen(issue__wen),
    .src1__addr(fast_src1__addr),
    .src1__data_o(fast_src1__data_o),
    .src1__ren(fast_src1__ren)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:42979.7-43310.4" *)
  fus fus (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(fus_cr_a_ok),
    .\cr_a_ok$110 (\fus_cr_a_ok$122 ),
    .\cr_a_ok$111 (\fus_cr_a_ok$123 ),
    .\cr_a_ok$112 (\fus_cr_a_ok$124 ),
    .\cr_a_ok$113 (\fus_cr_a_ok$125 ),
    .\cr_a_ok$114 (\fus_cr_a_ok$126 ),
    .cu_ad__go_i(cu_ad__go_i),
    .cu_ad__rel_o(cu_ad__rel_o),
    .cu_busy_o(fus_cu_busy_o),
    .\cu_busy_o$11 (\fus_cu_busy_o$23 ),
    .\cu_busy_o$14 (\fus_cu_busy_o$26 ),
    .\cu_busy_o$17 (\fus_cu_busy_o$29 ),
    .\cu_busy_o$2 (\fus_cu_busy_o$14 ),
    .\cu_busy_o$20 (\fus_cu_busy_o$32 ),
    .\cu_busy_o$23 (\fus_cu_busy_o$35 ),
    .\cu_busy_o$26 (\fus_cu_busy_o$38 ),
    .\cu_busy_o$5 (\fus_cu_busy_o$17 ),
    .\cu_busy_o$8 (\fus_cu_busy_o$20 ),
    .cu_issue_i(fus_cu_issue_i),
    .\cu_issue_i$1 (\fus_cu_issue_i$13 ),
    .\cu_issue_i$10 (\fus_cu_issue_i$22 ),
    .\cu_issue_i$13 (\fus_cu_issue_i$25 ),
    .\cu_issue_i$16 (\fus_cu_issue_i$28 ),
    .\cu_issue_i$19 (\fus_cu_issue_i$31 ),
    .\cu_issue_i$22 (\fus_cu_issue_i$34 ),
    .\cu_issue_i$25 (\fus_cu_issue_i$37 ),
    .\cu_issue_i$4 (\fus_cu_issue_i$16 ),
    .\cu_issue_i$7 (\fus_cu_issue_i$19 ),
    .cu_rd__go_i(fus_cu_rd__go_i),
    .\cu_rd__go_i$29 (\fus_cu_rd__go_i$41 ),
    .\cu_rd__go_i$32 (\fus_cu_rd__go_i$44 ),
    .\cu_rd__go_i$35 (\fus_cu_rd__go_i$47 ),
    .\cu_rd__go_i$38 (\fus_cu_rd__go_i$50 ),
    .\cu_rd__go_i$41 (\fus_cu_rd__go_i$53 ),
    .\cu_rd__go_i$44 (\fus_cu_rd__go_i$56 ),
    .\cu_rd__go_i$47 (\fus_cu_rd__go_i$59 ),
    .\cu_rd__go_i$54 (\fus_cu_rd__go_i$66 ),
    .\cu_rd__go_i$70 (\fus_cu_rd__go_i$82 ),
    .cu_rd__rel_o(fus_cu_rd__rel_o),
    .\cu_rd__rel_o$28 (\fus_cu_rd__rel_o$40 ),
    .\cu_rd__rel_o$31 (\fus_cu_rd__rel_o$43 ),
    .\cu_rd__rel_o$34 (\fus_cu_rd__rel_o$46 ),
    .\cu_rd__rel_o$37 (\fus_cu_rd__rel_o$49 ),
    .\cu_rd__rel_o$40 (\fus_cu_rd__rel_o$52 ),
    .\cu_rd__rel_o$43 (\fus_cu_rd__rel_o$55 ),
    .\cu_rd__rel_o$46 (\fus_cu_rd__rel_o$58 ),
    .\cu_rd__rel_o$53 (\fus_cu_rd__rel_o$65 ),
    .\cu_rd__rel_o$69 (\fus_cu_rd__rel_o$81 ),
    .cu_rdmaskn_i(fus_cu_rdmaskn_i),
    .\cu_rdmaskn_i$12 (\fus_cu_rdmaskn_i$24 ),
    .\cu_rdmaskn_i$15 (\fus_cu_rdmaskn_i$27 ),
    .\cu_rdmaskn_i$18 (\fus_cu_rdmaskn_i$30 ),
    .\cu_rdmaskn_i$21 (\fus_cu_rdmaskn_i$33 ),
    .\cu_rdmaskn_i$24 (\fus_cu_rdmaskn_i$36 ),
    .\cu_rdmaskn_i$27 (\fus_cu_rdmaskn_i$39 ),
    .\cu_rdmaskn_i$3 (\fus_cu_rdmaskn_i$15 ),
    .\cu_rdmaskn_i$6 (\fus_cu_rdmaskn_i$18 ),
    .\cu_rdmaskn_i$9 (\fus_cu_rdmaskn_i$21 ),
    .cu_st__go_i(cu_st__go_i),
    .cu_st__rel_o(cu_st__rel_o),
    .cu_wr__go_i(fus_cu_wr__go_i),
    .\cu_wr__go_i$100 (\fus_cu_wr__go_i$112 ),
    .\cu_wr__go_i$102 (\fus_cu_wr__go_i$114 ),
    .\cu_wr__go_i$137 (\fus_cu_wr__go_i$149 ),
    .\cu_wr__go_i$82 (\fus_cu_wr__go_i$94 ),
    .\cu_wr__go_i$85 (\fus_cu_wr__go_i$97 ),
    .\cu_wr__go_i$88 (\fus_cu_wr__go_i$100 ),
    .\cu_wr__go_i$91 (\fus_cu_wr__go_i$103 ),
    .\cu_wr__go_i$94 (\fus_cu_wr__go_i$106 ),
    .\cu_wr__go_i$97 (\fus_cu_wr__go_i$109 ),
    .cu_wr__rel_o(fus_cu_wr__rel_o),
    .\cu_wr__rel_o$101 (\fus_cu_wr__rel_o$113 ),
    .\cu_wr__rel_o$136 (\fus_cu_wr__rel_o$148 ),
    .\cu_wr__rel_o$81 (\fus_cu_wr__rel_o$93 ),
    .\cu_wr__rel_o$84 (\fus_cu_wr__rel_o$96 ),
    .\cu_wr__rel_o$87 (\fus_cu_wr__rel_o$99 ),
    .\cu_wr__rel_o$90 (\fus_cu_wr__rel_o$102 ),
    .\cu_wr__rel_o$93 (\fus_cu_wr__rel_o$105 ),
    .\cu_wr__rel_o$96 (\fus_cu_wr__rel_o$108 ),
    .\cu_wr__rel_o$99 (\fus_cu_wr__rel_o$111 ),
    .dest1_o(fus_dest1_o),
    .\dest1_o$103 (\fus_dest1_o$115 ),
    .\dest1_o$104 (\fus_dest1_o$116 ),
    .\dest1_o$105 (\fus_dest1_o$117 ),
    .\dest1_o$106 (\fus_dest1_o$118 ),
    .\dest1_o$107 (\fus_dest1_o$119 ),
    .\dest1_o$108 (\fus_dest1_o$120 ),
    .\dest1_o$109 (\fus_dest1_o$121 ),
    .\dest1_o$141 (\fus_dest1_o$153 ),
    .dest2_o(fus_dest2_o),
    .\dest2_o$115 (\fus_dest2_o$127 ),
    .\dest2_o$116 (\fus_dest2_o$128 ),
    .\dest2_o$117 (\fus_dest2_o$129 ),
    .\dest2_o$118 (\fus_dest2_o$130 ),
    .\dest2_o$119 (\fus_dest2_o$131 ),
    .\dest2_o$142 (\fus_dest2_o$154 ),
    .\dest2_o$144 (\fus_dest2_o$156 ),
    .\dest2_o$150 (\fus_dest2_o$162 ),
    .dest3_o(fus_dest3_o),
    .\dest3_o$122 (\fus_dest3_o$134 ),
    .\dest3_o$123 (\fus_dest3_o$135 ),
    .\dest3_o$127 (\fus_dest3_o$139 ),
    .\dest3_o$128 (\fus_dest3_o$140 ),
    .\dest3_o$143 (\fus_dest3_o$155 ),
    .\dest3_o$145 (\fus_dest3_o$157 ),
    .\dest3_o$147 (\fus_dest3_o$159 ),
    .dest4_o(fus_dest4_o),
    .\dest4_o$133 (\fus_dest4_o$145 ),
    .\dest4_o$134 (\fus_dest4_o$146 ),
    .\dest4_o$135 (\fus_dest4_o$147 ),
    .\dest4_o$148 (\fus_dest4_o$160 ),
    .dest5_o(fus_dest5_o),
    .\dest5_o$132 (\fus_dest5_o$144 ),
    .\dest5_o$149 (\fus_dest5_o$161 ),
    .dest6_o(fus_dest6_o),
    .ea(fus_ea),
    .fast1_ok(fus_fast1_ok),
    .\fast1_ok$138 (\fus_fast1_ok$150 ),
    .\fast1_ok$139 (\fus_fast1_ok$151 ),
    .fast2_ok(fus_fast2_ok),
    .\fast2_ok$140 (\fus_fast2_ok$152 ),
    .full_cr_ok(fus_full_cr_ok),
    .ldst_port0_addr_i(fus_ldst_port0_addr_i),
    .ldst_port0_addr_i_ok(fus_ldst_port0_addr_i_ok),
    .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o),
    .ldst_port0_busy_o(fus_ldst_port0_busy_o),
    .ldst_port0_data_len(fus_ldst_port0_data_len),
    .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ),
    .\ldst_port0_exc_$signal$151 (\fus_ldst_port0_exc_$signal$163 ),
    .\ldst_port0_exc_$signal$152 (\fus_ldst_port0_exc_$signal$164 ),
    .\ldst_port0_exc_$signal$153 (\fus_ldst_port0_exc_$signal$165 ),
    .\ldst_port0_exc_$signal$154 (\fus_ldst_port0_exc_$signal$166 ),
    .\ldst_port0_exc_$signal$155 (\fus_ldst_port0_exc_$signal$167 ),
    .\ldst_port0_exc_$signal$156 (\fus_ldst_port0_exc_$signal$168 ),
    .\ldst_port0_exc_$signal$157 (\fus_ldst_port0_exc_$signal$169 ),
    .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i),
    .ldst_port0_is_st_i(fus_ldst_port0_is_st_i),
    .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o),
    .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok),
    .ldst_port0_st_data_i(fus_ldst_port0_st_data_i),
    .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok),
    .msr_ok(fus_msr_ok),
    .nia_ok(fus_nia_ok),
    .\nia_ok$146 (\fus_nia_ok$158 ),
    .o(fus_o),
    .o_ok(fus_o_ok),
    .\o_ok$80 (\fus_o_ok$92 ),
    .\o_ok$83 (\fus_o_ok$95 ),
    .\o_ok$86 (\fus_o_ok$98 ),
    .\o_ok$89 (\fus_o_ok$101 ),
    .\o_ok$92 (\fus_o_ok$104 ),
    .\o_ok$95 (\fus_o_ok$107 ),
    .\o_ok$98 (\fus_o_ok$110 ),
    .oper_i_alu_alu0__data_len(fus_oper_i_alu_alu0__data_len),
    .oper_i_alu_alu0__fn_unit(fus_oper_i_alu_alu0__fn_unit),
    .oper_i_alu_alu0__imm_data__data(fus_oper_i_alu_alu0__imm_data__data),
    .oper_i_alu_alu0__imm_data__ok(fus_oper_i_alu_alu0__imm_data__ok),
    .oper_i_alu_alu0__input_carry(fus_oper_i_alu_alu0__input_carry),
    .oper_i_alu_alu0__insn(fus_oper_i_alu_alu0__insn),
    .oper_i_alu_alu0__insn_type(fus_oper_i_alu_alu0__insn_type),
    .oper_i_alu_alu0__invert_in(fus_oper_i_alu_alu0__invert_in),
    .oper_i_alu_alu0__invert_out(fus_oper_i_alu_alu0__invert_out),
    .oper_i_alu_alu0__is_32bit(fus_oper_i_alu_alu0__is_32bit),
    .oper_i_alu_alu0__is_signed(fus_oper_i_alu_alu0__is_signed),
    .oper_i_alu_alu0__oe__oe(fus_oper_i_alu_alu0__oe__oe),
    .oper_i_alu_alu0__oe__ok(fus_oper_i_alu_alu0__oe__ok),
    .oper_i_alu_alu0__output_carry(fus_oper_i_alu_alu0__output_carry),
    .oper_i_alu_alu0__rc__ok(fus_oper_i_alu_alu0__rc__ok),
    .oper_i_alu_alu0__rc__rc(fus_oper_i_alu_alu0__rc__rc),
    .oper_i_alu_alu0__write_cr0(fus_oper_i_alu_alu0__write_cr0),
    .oper_i_alu_alu0__zero_a(fus_oper_i_alu_alu0__zero_a),
    .oper_i_alu_branch0__cia(fus_oper_i_alu_branch0__cia),
    .oper_i_alu_branch0__fn_unit(fus_oper_i_alu_branch0__fn_unit),
    .oper_i_alu_branch0__imm_data__data(fus_oper_i_alu_branch0__imm_data__data),
    .oper_i_alu_branch0__imm_data__ok(fus_oper_i_alu_branch0__imm_data__ok),
    .oper_i_alu_branch0__insn(fus_oper_i_alu_branch0__insn),
    .oper_i_alu_branch0__insn_type(fus_oper_i_alu_branch0__insn_type),
    .oper_i_alu_branch0__is_32bit(fus_oper_i_alu_branch0__is_32bit),
    .oper_i_alu_branch0__lk(fus_oper_i_alu_branch0__lk),
    .oper_i_alu_cr0__fn_unit(fus_oper_i_alu_cr0__fn_unit),
    .oper_i_alu_cr0__insn(fus_oper_i_alu_cr0__insn),
    .oper_i_alu_cr0__insn_type(fus_oper_i_alu_cr0__insn_type),
    .oper_i_alu_div0__data_len(fus_oper_i_alu_div0__data_len),
    .oper_i_alu_div0__fn_unit(fus_oper_i_alu_div0__fn_unit),
    .oper_i_alu_div0__imm_data__data(fus_oper_i_alu_div0__imm_data__data),
    .oper_i_alu_div0__imm_data__ok(fus_oper_i_alu_div0__imm_data__ok),
    .oper_i_alu_div0__input_carry(fus_oper_i_alu_div0__input_carry),
    .oper_i_alu_div0__insn(fus_oper_i_alu_div0__insn),
    .oper_i_alu_div0__insn_type(fus_oper_i_alu_div0__insn_type),
    .oper_i_alu_div0__invert_in(fus_oper_i_alu_div0__invert_in),
    .oper_i_alu_div0__invert_out(fus_oper_i_alu_div0__invert_out),
    .oper_i_alu_div0__is_32bit(fus_oper_i_alu_div0__is_32bit),
    .oper_i_alu_div0__is_signed(fus_oper_i_alu_div0__is_signed),
    .oper_i_alu_div0__oe__oe(fus_oper_i_alu_div0__oe__oe),
    .oper_i_alu_div0__oe__ok(fus_oper_i_alu_div0__oe__ok),
    .oper_i_alu_div0__output_carry(fus_oper_i_alu_div0__output_carry),
    .oper_i_alu_div0__rc__ok(fus_oper_i_alu_div0__rc__ok),
    .oper_i_alu_div0__rc__rc(fus_oper_i_alu_div0__rc__rc),
    .oper_i_alu_div0__write_cr0(fus_oper_i_alu_div0__write_cr0),
    .oper_i_alu_div0__zero_a(fus_oper_i_alu_div0__zero_a),
    .oper_i_alu_logical0__data_len(fus_oper_i_alu_logical0__data_len),
    .oper_i_alu_logical0__fn_unit(fus_oper_i_alu_logical0__fn_unit),
    .oper_i_alu_logical0__imm_data__data(fus_oper_i_alu_logical0__imm_data__data),
    .oper_i_alu_logical0__imm_data__ok(fus_oper_i_alu_logical0__imm_data__ok),
    .oper_i_alu_logical0__input_carry(fus_oper_i_alu_logical0__input_carry),
    .oper_i_alu_logical0__insn(fus_oper_i_alu_logical0__insn),
    .oper_i_alu_logical0__insn_type(fus_oper_i_alu_logical0__insn_type),
    .oper_i_alu_logical0__invert_in(fus_oper_i_alu_logical0__invert_in),
    .oper_i_alu_logical0__invert_out(fus_oper_i_alu_logical0__invert_out),
    .oper_i_alu_logical0__is_32bit(fus_oper_i_alu_logical0__is_32bit),
    .oper_i_alu_logical0__is_signed(fus_oper_i_alu_logical0__is_signed),
    .oper_i_alu_logical0__oe__oe(fus_oper_i_alu_logical0__oe__oe),
    .oper_i_alu_logical0__oe__ok(fus_oper_i_alu_logical0__oe__ok),
    .oper_i_alu_logical0__output_carry(fus_oper_i_alu_logical0__output_carry),
    .oper_i_alu_logical0__rc__ok(fus_oper_i_alu_logical0__rc__ok),
    .oper_i_alu_logical0__rc__rc(fus_oper_i_alu_logical0__rc__rc),
    .oper_i_alu_logical0__write_cr0(fus_oper_i_alu_logical0__write_cr0),
    .oper_i_alu_logical0__zero_a(fus_oper_i_alu_logical0__zero_a),
    .oper_i_alu_mul0__fn_unit(fus_oper_i_alu_mul0__fn_unit),
    .oper_i_alu_mul0__imm_data__data(fus_oper_i_alu_mul0__imm_data__data),
    .oper_i_alu_mul0__imm_data__ok(fus_oper_i_alu_mul0__imm_data__ok),
    .oper_i_alu_mul0__insn(fus_oper_i_alu_mul0__insn),
    .oper_i_alu_mul0__insn_type(fus_oper_i_alu_mul0__insn_type),
    .oper_i_alu_mul0__is_32bit(fus_oper_i_alu_mul0__is_32bit),
    .oper_i_alu_mul0__is_signed(fus_oper_i_alu_mul0__is_signed),
    .oper_i_alu_mul0__oe__oe(fus_oper_i_alu_mul0__oe__oe),
    .oper_i_alu_mul0__oe__ok(fus_oper_i_alu_mul0__oe__ok),
    .oper_i_alu_mul0__rc__ok(fus_oper_i_alu_mul0__rc__ok),
    .oper_i_alu_mul0__rc__rc(fus_oper_i_alu_mul0__rc__rc),
    .oper_i_alu_mul0__write_cr0(fus_oper_i_alu_mul0__write_cr0),
    .oper_i_alu_shift_rot0__fn_unit(fus_oper_i_alu_shift_rot0__fn_unit),
    .oper_i_alu_shift_rot0__imm_data__data(fus_oper_i_alu_shift_rot0__imm_data__data),
    .oper_i_alu_shift_rot0__imm_data__ok(fus_oper_i_alu_shift_rot0__imm_data__ok),
    .oper_i_alu_shift_rot0__input_carry(fus_oper_i_alu_shift_rot0__input_carry),
    .oper_i_alu_shift_rot0__input_cr(fus_oper_i_alu_shift_rot0__input_cr),
    .oper_i_alu_shift_rot0__insn(fus_oper_i_alu_shift_rot0__insn),
    .oper_i_alu_shift_rot0__insn_type(fus_oper_i_alu_shift_rot0__insn_type),
    .oper_i_alu_shift_rot0__invert_in(fus_oper_i_alu_shift_rot0__invert_in),
    .oper_i_alu_shift_rot0__is_32bit(fus_oper_i_alu_shift_rot0__is_32bit),
    .oper_i_alu_shift_rot0__is_signed(fus_oper_i_alu_shift_rot0__is_signed),
    .oper_i_alu_shift_rot0__oe__oe(fus_oper_i_alu_shift_rot0__oe__oe),
    .oper_i_alu_shift_rot0__oe__ok(fus_oper_i_alu_shift_rot0__oe__ok),
    .oper_i_alu_shift_rot0__output_carry(fus_oper_i_alu_shift_rot0__output_carry),
    .oper_i_alu_shift_rot0__output_cr(fus_oper_i_alu_shift_rot0__output_cr),
    .oper_i_alu_shift_rot0__rc__ok(fus_oper_i_alu_shift_rot0__rc__ok),
    .oper_i_alu_shift_rot0__rc__rc(fus_oper_i_alu_shift_rot0__rc__rc),
    .oper_i_alu_shift_rot0__write_cr0(fus_oper_i_alu_shift_rot0__write_cr0),
    .oper_i_alu_spr0__fn_unit(fus_oper_i_alu_spr0__fn_unit),
    .oper_i_alu_spr0__insn(fus_oper_i_alu_spr0__insn),
    .oper_i_alu_spr0__insn_type(fus_oper_i_alu_spr0__insn_type),
    .oper_i_alu_spr0__is_32bit(fus_oper_i_alu_spr0__is_32bit),
    .oper_i_alu_trap0__cia(fus_oper_i_alu_trap0__cia),
    .oper_i_alu_trap0__fn_unit(fus_oper_i_alu_trap0__fn_unit),
    .oper_i_alu_trap0__insn(fus_oper_i_alu_trap0__insn),
    .oper_i_alu_trap0__insn_type(fus_oper_i_alu_trap0__insn_type),
    .oper_i_alu_trap0__is_32bit(fus_oper_i_alu_trap0__is_32bit),
    .oper_i_alu_trap0__ldst_exc(fus_oper_i_alu_trap0__ldst_exc),
    .oper_i_alu_trap0__msr(fus_oper_i_alu_trap0__msr),
    .oper_i_alu_trap0__trapaddr(fus_oper_i_alu_trap0__trapaddr),
    .oper_i_alu_trap0__traptype(fus_oper_i_alu_trap0__traptype),
    .oper_i_ldst_ldst0__byte_reverse(fus_oper_i_ldst_ldst0__byte_reverse),
    .oper_i_ldst_ldst0__data_len(fus_oper_i_ldst_ldst0__data_len),
    .oper_i_ldst_ldst0__fn_unit(fus_oper_i_ldst_ldst0__fn_unit),
    .oper_i_ldst_ldst0__imm_data__data(fus_oper_i_ldst_ldst0__imm_data__data),
    .oper_i_ldst_ldst0__imm_data__ok(fus_oper_i_ldst_ldst0__imm_data__ok),
    .oper_i_ldst_ldst0__insn(fus_oper_i_ldst_ldst0__insn),
    .oper_i_ldst_ldst0__insn_type(fus_oper_i_ldst_ldst0__insn_type),
    .oper_i_ldst_ldst0__is_32bit(fus_oper_i_ldst_ldst0__is_32bit),
    .oper_i_ldst_ldst0__is_signed(fus_oper_i_ldst_ldst0__is_signed),
    .oper_i_ldst_ldst0__ldst_mode(fus_oper_i_ldst_ldst0__ldst_mode),
    .oper_i_ldst_ldst0__oe__oe(fus_oper_i_ldst_ldst0__oe__oe),
    .oper_i_ldst_ldst0__oe__ok(fus_oper_i_ldst_ldst0__oe__ok),
    .oper_i_ldst_ldst0__rc__ok(fus_oper_i_ldst_ldst0__rc__ok),
    .oper_i_ldst_ldst0__rc__rc(fus_oper_i_ldst_ldst0__rc__rc),
    .oper_i_ldst_ldst0__sign_extend(fus_oper_i_ldst_ldst0__sign_extend),
    .oper_i_ldst_ldst0__zero_a(fus_oper_i_ldst_ldst0__zero_a),
    .spr1_ok(fus_spr1_ok),
    .src1_i(fus_src1_i),
    .\src1_i$50 (\fus_src1_i$62 ),
    .\src1_i$51 (\fus_src1_i$63 ),
    .\src1_i$52 (\fus_src1_i$64 ),
    .\src1_i$55 (\fus_src1_i$67 ),
    .\src1_i$56 (\fus_src1_i$68 ),
    .\src1_i$57 (\fus_src1_i$69 ),
    .\src1_i$58 (\fus_src1_i$70 ),
    .\src1_i$59 (\fus_src1_i$71 ),
    .\src1_i$74 (\fus_src1_i$86 ),
    .src2_i(fus_src2_i),
    .\src2_i$30 (\fus_src2_i$42 ),
    .\src2_i$33 (\fus_src2_i$45 ),
    .\src2_i$36 (\fus_src2_i$48 ),
    .\src2_i$39 (\fus_src2_i$51 ),
    .\src2_i$42 (\fus_src2_i$54 ),
    .\src2_i$45 (\fus_src2_i$57 ),
    .\src2_i$48 (\fus_src2_i$60 ),
    .\src2_i$77 (\fus_src2_i$89 ),
    .\src2_i$79 (\fus_src2_i$91 ),
    .src3_i(fus_src3_i),
    .\src3_i$49 (\fus_src3_i$61 ),
    .\src3_i$60 (\fus_src3_i$72 ),
    .\src3_i$61 (\fus_src3_i$73 ),
    .\src3_i$62 (\fus_src3_i$74 ),
    .\src3_i$63 (\fus_src3_i$75 ),
    .\src3_i$67 (\fus_src3_i$79 ),
    .\src3_i$71 (\fus_src3_i$83 ),
    .\src3_i$75 (\fus_src3_i$87 ),
    .\src3_i$76 (\fus_src3_i$88 ),
    .src4_i(fus_src4_i),
    .\src4_i$64 (\fus_src4_i$76 ),
    .\src4_i$65 (\fus_src4_i$77 ),
    .\src4_i$68 (\fus_src4_i$80 ),
    .\src4_i$78 (\fus_src4_i$90 ),
    .src5_i(fus_src5_i),
    .\src5_i$66 (\fus_src5_i$78 ),
    .\src5_i$72 (\fus_src5_i$84 ),
    .src6_i(fus_src6_i),
    .\src6_i$73 (\fus_src6_i$85 ),
    .xer_ca_ok(fus_xer_ca_ok),
    .\xer_ca_ok$120 (\fus_xer_ca_ok$132 ),
    .\xer_ca_ok$121 (\fus_xer_ca_ok$133 ),
    .xer_ov_ok(fus_xer_ov_ok),
    .\xer_ov_ok$124 (\fus_xer_ov_ok$136 ),
    .\xer_ov_ok$125 (\fus_xer_ov_ok$137 ),
    .\xer_ov_ok$126 (\fus_xer_ov_ok$138 ),
    .xer_so_ok(fus_xer_so_ok),
    .\xer_so_ok$129 (\fus_xer_so_ok$141 ),
    .\xer_so_ok$130 (\fus_xer_so_ok$142 ),
    .\xer_so_ok$131 (\fus_xer_so_ok$143 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43311.9-43323.4" *)
  \int  \int  (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest1__addr(int_dest1__addr),
    .dest1__data_i(int_dest1__data_i),
    .dest1__wen(int_dest1__wen),
    .dmi__addr(dmi__addr),
    .dmi__data_o(dmi__data_o),
    .dmi__ren(dmi__ren),
    .src1__addr(int_src1__addr),
    .src1__data_o(int_src1__data_o),
    .src1__ren(int_src1__ren)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43324.6-43356.4" *)
  l0 l0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dbus__ack(dbus__ack),
    .dbus__adr(dbus__adr),
    .dbus__cyc(dbus__cyc),
    .dbus__dat_r(dbus__dat_r),
    .dbus__dat_w(dbus__dat_w),
    .dbus__err(dbus__err),
    .dbus__sel(dbus__sel),
    .dbus__stb(dbus__stb),
    .dbus__we(dbus__we),
    .ldst_port0_addr_i(fus_ldst_port0_addr_i),
    .ldst_port0_addr_i_ok(fus_ldst_port0_addr_i_ok),
    .ldst_port0_addr_ok_o(fus_ldst_port0_addr_ok_o),
    .ldst_port0_busy_o(fus_ldst_port0_busy_o),
    .ldst_port0_data_len(fus_ldst_port0_data_len),
    .\ldst_port0_exc_$signal (\fus_ldst_port0_exc_$signal ),
    .\ldst_port0_exc_$signal$1 (\fus_ldst_port0_exc_$signal$163 ),
    .\ldst_port0_exc_$signal$2 (\fus_ldst_port0_exc_$signal$164 ),
    .\ldst_port0_exc_$signal$3 (\fus_ldst_port0_exc_$signal$165 ),
    .\ldst_port0_exc_$signal$4 (\fus_ldst_port0_exc_$signal$166 ),
    .\ldst_port0_exc_$signal$5 (\fus_ldst_port0_exc_$signal$167 ),
    .\ldst_port0_exc_$signal$6 (\fus_ldst_port0_exc_$signal$168 ),
    .\ldst_port0_exc_$signal$7 (\fus_ldst_port0_exc_$signal$169 ),
    .ldst_port0_is_ld_i(fus_ldst_port0_is_ld_i),
    .ldst_port0_is_st_i(fus_ldst_port0_is_st_i),
    .ldst_port0_ld_data_o(fus_ldst_port0_ld_data_o),
    .ldst_port0_ld_data_o_ok(fus_ldst_port0_ld_data_o_ok),
    .ldst_port0_st_data_i(fus_ldst_port0_st_data_i),
    .ldst_port0_st_data_i_ok(fus_ldst_port0_st_data_i_ok),
    .wb_dcache_en(wb_dcache_en)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43357.18-43361.4" *)
  rdpick_CR_cr_a rdpick_CR_cr_a (
    .en_o(rdpick_CR_cr_a_en_o),
    .i(rdpick_CR_cr_a_i),
    .o(rdpick_CR_cr_a_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43362.18-43366.4" *)
  rdpick_CR_cr_b rdpick_CR_cr_b (
    .en_o(rdpick_CR_cr_b_en_o),
    .i(rdpick_CR_cr_b_i),
    .o(rdpick_CR_cr_b_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43367.18-43371.4" *)
  rdpick_CR_cr_c rdpick_CR_cr_c (
    .en_o(rdpick_CR_cr_c_en_o),
    .i(rdpick_CR_cr_c_i),
    .o(rdpick_CR_cr_c_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43372.21-43376.4" *)
  rdpick_CR_full_cr rdpick_CR_full_cr (
    .en_o(rdpick_CR_full_cr_en_o),
    .i(rdpick_CR_full_cr_i),
    .o(rdpick_CR_full_cr_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43377.21-43381.4" *)
  rdpick_FAST_fast1 rdpick_FAST_fast1 (
    .en_o(rdpick_FAST_fast1_en_o),
    .i(rdpick_FAST_fast1_i),
    .o(rdpick_FAST_fast1_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43382.19-43386.4" *)
  rdpick_INT_rabc rdpick_INT_rabc (
    .en_o(rdpick_INT_rabc_en_o),
    .i(rdpick_INT_rabc_i),
    .o(rdpick_INT_rabc_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43387.19-43391.4" *)
  rdpick_SPR_spr1 rdpick_SPR_spr1 (
    .en_o(rdpick_SPR_spr1_en_o),
    .i(rdpick_SPR_spr1_i),
    .o(rdpick_SPR_spr1_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43392.21-43396.4" *)
  rdpick_XER_xer_ca rdpick_XER_xer_ca (
    .en_o(rdpick_XER_xer_ca_en_o),
    .i(rdpick_XER_xer_ca_i),
    .o(rdpick_XER_xer_ca_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43397.21-43401.4" *)
  rdpick_XER_xer_ov rdpick_XER_xer_ov (
    .en_o(rdpick_XER_xer_ov_en_o),
    .i(rdpick_XER_xer_ov_i),
    .o(rdpick_XER_xer_ov_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43402.21-43406.4" *)
  rdpick_XER_xer_so rdpick_XER_xer_so (
    .en_o(rdpick_XER_xer_so_en_o),
    .i(rdpick_XER_xer_so_i),
    .o(rdpick_XER_xer_so_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43407.7-43416.4" *)
  spr spr (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .spr1__addr(spr_spr1__addr),
    .\spr1__addr$1 (\spr_spr1__addr$175 ),
    .spr1__data_i(spr_spr1__data_i),
    .spr1__data_o(spr_spr1__data_o),
    .spr1__ren(spr_spr1__ren),
    .spr1__wen(spr_spr1__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43417.9-43434.4" *)
  state state (
    .cia__data_o(cia__data_o),
    .cia__ren(cia__ren),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .data_i(data_i),
    .\data_i$2 (\data_i$11 ),
    .\data_i$3 (state_data_i),
    .\data_i$4 (\state_data_i$174 ),
    .msr__data_o(msr__data_o),
    .msr__ren(msr__ren),
    .state_nia_wen(state_nia_wen),
    .sv__data_o(sv__data_o),
    .sv__ren(sv__ren),
    .wen(wen),
    .\wen$1 (\wen$10 ),
    .\wen$5 (state_wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43435.18-43439.4" *)
  wrpick_CR_cr_a wrpick_CR_cr_a (
    .en_o(wrpick_CR_cr_a_en_o),
    .i(wrpick_CR_cr_a_i),
    .o(wrpick_CR_cr_a_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43440.21-43444.4" *)
  wrpick_CR_full_cr wrpick_CR_full_cr (
    .en_o(wrpick_CR_full_cr_en_o),
    .i(wrpick_CR_full_cr_i),
    .o(wrpick_CR_full_cr_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43445.21-43449.4" *)
  wrpick_FAST_fast1 wrpick_FAST_fast1 (
    .en_o(wrpick_FAST_fast1_en_o),
    .i(wrpick_FAST_fast1_i),
    .o(wrpick_FAST_fast1_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43450.16-43454.4" *)
  wrpick_INT_o wrpick_INT_o (
    .en_o(wrpick_INT_o_en_o),
    .i(wrpick_INT_o_i),
    .o(wrpick_INT_o_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43455.19-43459.4" *)
  wrpick_SPR_spr1 wrpick_SPR_spr1 (
    .en_o(wrpick_SPR_spr1_en_o),
    .i(wrpick_SPR_spr1_i),
    .o(wrpick_SPR_spr1_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43460.20-43464.4" *)
  wrpick_STATE_msr wrpick_STATE_msr (
    .en_o(wrpick_STATE_msr_en_o),
    .i(wrpick_STATE_msr_i),
    .o(wrpick_STATE_msr_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43465.20-43469.4" *)
  wrpick_STATE_nia wrpick_STATE_nia (
    .en_o(wrpick_STATE_nia_en_o),
    .i(wrpick_STATE_nia_i),
    .o(wrpick_STATE_nia_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43470.21-43474.4" *)
  wrpick_XER_xer_ca wrpick_XER_xer_ca (
    .en_o(wrpick_XER_xer_ca_en_o),
    .i(wrpick_XER_xer_ca_i),
    .o(wrpick_XER_xer_ca_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43475.21-43479.4" *)
  wrpick_XER_xer_ov wrpick_XER_xer_ov (
    .en_o(wrpick_XER_xer_ov_en_o),
    .i(wrpick_XER_xer_ov_i),
    .o(wrpick_XER_xer_ov_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43480.21-43484.4" *)
  wrpick_XER_xer_so wrpick_XER_xer_so (
    .en_o(wrpick_XER_xer_so_en_o),
    .i(wrpick_XER_xer_so_i),
    .o(wrpick_XER_xer_so_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:43485.7-43502.4" *)
  xer xer (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .data_i(xer_data_i),
    .\data_i$1 (\xer_data_i$170 ),
    .\data_i$3 (\xer_data_i$172 ),
    .full_rd__data_o(full_rd__data_o),
    .full_rd__ren(full_rd__ren),
    .src1__data_o(xer_src1__data_o),
    .src1__ren(xer_src1__ren),
    .src2__data_o(xer_src2__data_o),
    .src2__ren(xer_src2__ren),
    .src3__data_o(xer_src3__data_o),
    .src3__ren(xer_src3__ren),
    .wen(xer_wen),
    .\wen$2 (\xer_wen$171 ),
    .\wen$4 (\xer_wen$173 )
  );
  always @* begin
    if (\initial ) begin end
    _0268_ = 1'h0;
  end
  always @* begin
      \initial  <= _0268_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0384_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_terminate_o <= _0384_;
  end
  always @* begin
    if (\initial ) begin end
    _0387_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      counter <= _0387_;
  end
  always @* begin
    if (\initial ) begin end
    _0389_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_CR_cr_a_branch0_1 <= _0389_;
  end
  always @* begin
    if (\initial ) begin end
    _0391_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_CR_cr_a_cr0_0 <= _0391_;
  end
  always @* begin
    if (\initial ) begin end
    _0393_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_CR_cr_b_cr0_0 <= _0393_;
  end
  always @* begin
    if (\initial ) begin end
    _0395_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_CR_cr_c_cr0_0 <= _0395_;
  end
  always @* begin
    if (\initial ) begin end
    _0397_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_CR_full_cr_cr0_0 <= _0397_;
  end
  always @* begin
    if (\initial ) begin end
    _0399_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_FAST_fast1_branch0_0 <= _0399_;
  end
  always @* begin
    if (\initial ) begin end
    _0401_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_FAST_fast1_branch0_3 <= _0401_;
  end
  always @* begin
    if (\initial ) begin end
    _0403_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_FAST_fast1_spr0_2 <= _0403_;
  end
  always @* begin
    if (\initial ) begin end
    _0405_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_FAST_fast1_trap0_1 <= _0405_;
  end
  always @* begin
    if (\initial ) begin end
    _0407_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_FAST_fast1_trap0_4 <= _0407_;
  end
  always @* begin
    if (\initial ) begin end
    _0409_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_alu0_0 <= _0409_;
  end
  always @* begin
    if (\initial ) begin end
    _0411_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_alu0_10 <= _0411_;
  end
  always @* begin
    if (\initial ) begin end
    _0415_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_cr0_1 <= _0415_;
  end
  always @* begin
    if (\initial ) begin end
    _0414_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_cr0_11 <= _0414_;
  end
  always @* begin
    if (\initial ) begin end
    _0417_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_div0_15 <= _0417_;
  end
  always @* begin
    if (\initial ) begin end
    _0419_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_div0_4 <= _0419_;
  end
  always @* begin
    if (\initial ) begin end
    _0421_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_ldst0_18 <= _0421_;
  end
  always @* begin
    if (\initial ) begin end
    _0423_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_ldst0_7 <= _0423_;
  end
  always @* begin
    if (\initial ) begin end
    _0425_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_ldst0_9 <= _0425_;
  end
  always @* begin
    if (\initial ) begin end
    _0427_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_logical0_13 <= _0427_;
  end
  always @* begin
    if (\initial ) begin end
    _0429_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_logical0_3 <= _0429_;
  end
  always @* begin
    if (\initial ) begin end
    _0431_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_mul0_16 <= _0431_;
  end
  always @* begin
    if (\initial ) begin end
    _0433_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_mul0_5 <= _0433_;
  end
  always @* begin
    if (\initial ) begin end
    _0435_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_shiftrot0_17 <= _0435_;
  end
  always @* begin
    if (\initial ) begin end
    _0437_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_shiftrot0_6 <= _0437_;
  end
  always @* begin
    if (\initial ) begin end
    _0439_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_shiftrot0_8 <= _0439_;
  end
  always @* begin
    if (\initial ) begin end
    _0441_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_spr0_14 <= _0441_;
  end
  always @* begin
    if (\initial ) begin end
    _0443_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_trap0_12 <= _0443_;
  end
  always @* begin
    if (\initial ) begin end
    _0445_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_INT_rabc_trap0_2 <= _0445_;
  end
  always @* begin
    if (\initial ) begin end
    _0447_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_SPR_spr1_spr0_0 <= _0447_;
  end
  always @* begin
    if (\initial ) begin end
    _0449_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_ca_alu0_0 <= _0449_;
  end
  always @* begin
    if (\initial ) begin end
    _0451_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_ca_shiftrot0_2 <= _0451_;
  end
  always @* begin
    if (\initial ) begin end
    _0453_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_ca_spr0_1 <= _0453_;
  end
  always @* begin
    if (\initial ) begin end
    _0455_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_ov_spr0_0 <= _0455_;
  end
  always @* begin
    if (\initial ) begin end
    _0457_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_alu0_0 <= _0457_;
  end
  always @* begin
    if (\initial ) begin end
    _0459_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_div0_3 <= _0459_;
  end
  always @* begin
    if (\initial ) begin end
    _0461_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_logical0_1 <= _0461_;
  end
  always @* begin
    if (\initial ) begin end
    _0463_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_mul0_4 <= _0463_;
  end
  always @* begin
    if (\initial ) begin end
    _0465_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_shiftrot0_5 <= _0465_;
  end
  always @* begin
    if (\initial ) begin end
    _0467_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dp_XER_xer_so_spr0_2 <= _0467_;
  end
  always @* begin
    if (\initial ) begin end
    _0688_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      wr_pick_dly <= _0688_;
  end
  always @* begin
    if (\initial ) begin end
    _0271_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1008  <= _0271_;
  end
  always @* begin
    if (\initial ) begin end
    _0274_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1029  <= _0274_;
  end
  always @* begin
    if (\initial ) begin end
    _0277_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1047  <= _0277_;
  end
  always @* begin
    if (\initial ) begin end
    _0280_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1069  <= _0280_;
  end
  always @* begin
    if (\initial ) begin end
    _0283_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1089  <= _0283_;
  end
  always @* begin
    if (\initial ) begin end
    _0286_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1109  <= _0286_;
  end
  always @* begin
    if (\initial ) begin end
    _0289_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1128  <= _0289_;
  end
  always @* begin
    if (\initial ) begin end
    _0292_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1146  <= _0292_;
  end
  always @* begin
    if (\initial ) begin end
    _0295_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1220  <= _0295_;
  end
  always @* begin
    if (\initial ) begin end
    _0298_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1248  <= _0298_;
  end
  always @* begin
    if (\initial ) begin end
    _0301_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1268  <= _0301_;
  end
  always @* begin
    if (\initial ) begin end
    _0304_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1288  <= _0304_;
  end
  always @* begin
    if (\initial ) begin end
    _0307_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1308  <= _0307_;
  end
  always @* begin
    if (\initial ) begin end
    _0310_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1328  <= _0310_;
  end
  always @* begin
    if (\initial ) begin end
    _0313_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1348  <= _0313_;
  end
  always @* begin
    if (\initial ) begin end
    _0316_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1395  <= _0316_;
  end
  always @* begin
    if (\initial ) begin end
    _0319_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1411  <= _0319_;
  end
  always @* begin
    if (\initial ) begin end
    _0322_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1427  <= _0322_;
  end
  always @* begin
    if (\initial ) begin end
    _0325_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1461  <= _0325_;
  end
  always @* begin
    if (\initial ) begin end
    _0328_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1477  <= _0328_;
  end
  always @* begin
    if (\initial ) begin end
    _0331_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1493  <= _0331_;
  end
  always @* begin
    if (\initial ) begin end
    _0334_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1509  <= _0334_;
  end
  always @* begin
    if (\initial ) begin end
    _0337_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1545  <= _0337_;
  end
  always @* begin
    if (\initial ) begin end
    _0340_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1561  <= _0340_;
  end
  always @* begin
    if (\initial ) begin end
    _0343_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1577  <= _0343_;
  end
  always @* begin
    if (\initial ) begin end
    _0346_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1593  <= _0346_;
  end
  always @* begin
    if (\initial ) begin end
    _0349_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1635  <= _0349_;
  end
  always @* begin
    if (\initial ) begin end
    _0352_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1654  <= _0352_;
  end
  always @* begin
    if (\initial ) begin end
    _0355_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1670  <= _0355_;
  end
  always @* begin
    if (\initial ) begin end
    _0358_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1686  <= _0358_;
  end
  always @* begin
    if (\initial ) begin end
    _0361_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1702  <= _0361_;
  end
  always @* begin
    if (\initial ) begin end
    _0364_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1746  <= _0364_;
  end
  always @* begin
    if (\initial ) begin end
    _0367_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1762  <= _0367_;
  end
  always @* begin
    if (\initial ) begin end
    _0370_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1786  <= _0370_;
  end
  always @* begin
    if (\initial ) begin end
    _0373_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$1806  <= _0373_;
  end
  always @* begin
    if (\initial ) begin end
    _0376_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \wr_pick_dly$989  <= _0376_;
  end
  always @* begin
    if (\initial ) begin end
    _0372_ = \wr_pick_dly$1806$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1806  <= _0372_;
  end
  always @* begin
    if (\initial ) begin end
    _0369_ = \wr_pick_dly$1786$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1786  <= _0369_;
  end
  always @* begin
    if (\initial ) begin end
    _0366_ = \wr_pick_dly$1762$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1762  <= _0366_;
  end
  always @* begin
    if (\initial ) begin end
    _0363_ = \wr_pick_dly$1746$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1746  <= _0363_;
  end
  always @* begin
    if (\initial ) begin end
    _0360_ = \wr_pick_dly$1702$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1702  <= _0360_;
  end
  always @* begin
    if (\initial ) begin end
    _0357_ = \wr_pick_dly$1686$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1686  <= _0357_;
  end
  always @* begin
    if (\initial ) begin end
    _0354_ = \wr_pick_dly$1670$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1670  <= _0354_;
  end
  always @* begin
    if (\initial ) begin end
    _0351_ = \wr_pick_dly$1654$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1654  <= _0351_;
  end
  always @* begin
    if (\initial ) begin end
    _0348_ = \wr_pick_dly$1635$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1635  <= _0348_;
  end
  always @* begin
    if (\initial ) begin end
    _0345_ = \wr_pick_dly$1593$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1593  <= _0345_;
  end
  always @* begin
    if (\initial ) begin end
    _0342_ = \wr_pick_dly$1577$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1577  <= _0342_;
  end
  always @* begin
    if (\initial ) begin end
    _0339_ = \wr_pick_dly$1561$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1561  <= _0339_;
  end
  always @* begin
    if (\initial ) begin end
    _0336_ = \wr_pick_dly$1545$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1545  <= _0336_;
  end
  always @* begin
    if (\initial ) begin end
    _0333_ = \wr_pick_dly$1509$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1509  <= _0333_;
  end
  always @* begin
    if (\initial ) begin end
    _0330_ = \wr_pick_dly$1493$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1493  <= _0330_;
  end
  always @* begin
    if (\initial ) begin end
    _0327_ = \wr_pick_dly$1477$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1477  <= _0327_;
  end
  always @* begin
    if (\initial ) begin end
    _0324_ = \wr_pick_dly$1461$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1461  <= _0324_;
  end
  always @* begin
    if (\initial ) begin end
    _0321_ = \wr_pick_dly$1427$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1427  <= _0321_;
  end
  always @* begin
    if (\initial ) begin end
    _0318_ = \wr_pick_dly$1411$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1411  <= _0318_;
  end
  always @* begin
    if (\initial ) begin end
    _0315_ = \wr_pick_dly$1395$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1395  <= _0315_;
  end
  always @* begin
    if (\initial ) begin end
    _0312_ = \wr_pick_dly$1348$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1348  <= _0312_;
  end
  always @* begin
    if (\initial ) begin end
    _0309_ = \wr_pick_dly$1328$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1328  <= _0309_;
  end
  always @* begin
    if (\initial ) begin end
    _0306_ = \wr_pick_dly$1308$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1308  <= _0306_;
  end
  always @* begin
    if (\initial ) begin end
    _0303_ = \wr_pick_dly$1288$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1288  <= _0303_;
  end
  always @* begin
    if (\initial ) begin end
    _0300_ = \wr_pick_dly$1268$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1268  <= _0300_;
  end
  always @* begin
    if (\initial ) begin end
    _0297_ = \wr_pick_dly$1248$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1248  <= _0297_;
  end
  always @* begin
    if (\initial ) begin end
    _0294_ = \wr_pick_dly$1220$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1220  <= _0294_;
  end
  always @* begin
    if (\initial ) begin end
    _0291_ = \wr_pick_dly$1146$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1146  <= _0291_;
  end
  always @* begin
    if (\initial ) begin end
    _0288_ = \wr_pick_dly$1128$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1128  <= _0288_;
  end
  always @* begin
    if (\initial ) begin end
    _0285_ = \wr_pick_dly$1109$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1109  <= _0285_;
  end
  always @* begin
    if (\initial ) begin end
    _0282_ = \wr_pick_dly$1089$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1089  <= _0282_;
  end
  always @* begin
    if (\initial ) begin end
    _0279_ = \wr_pick_dly$1069$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1069  <= _0279_;
  end
  always @* begin
    if (\initial ) begin end
    _0276_ = \wr_pick_dly$1047$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1047  <= _0276_;
  end
  always @* begin
    if (\initial ) begin end
    _0273_ = \wr_pick_dly$1029$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1029  <= _0273_;
  end
  always @* begin
    if (\initial ) begin end
    _0270_ = \wr_pick_dly$1008$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$1008  <= _0270_;
  end
  always @* begin
    if (\initial ) begin end
    _0375_ = \wr_pick_dly$989$next ;
  end
  always @(posedge coresync_clk) begin
      \wr_pick_dly$989  <= _0375_;
  end
  always @* begin
    if (\initial ) begin end
    _0378_ = \wr_pick_dly$next ;
  end
  always @(posedge coresync_clk) begin
      wr_pick_dly <= _0378_;
  end
  always @* begin
    if (\initial ) begin end
    _0064_ = \dp_SPR_spr1_spr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_SPR_spr1_spr0_0 <= _0064_;
  end
  always @* begin
    if (\initial ) begin end
    _0024_ = \dp_FAST_fast1_trap0_4$next ;
  end
  always @(posedge coresync_clk) begin
      dp_FAST_fast1_trap0_4 <= _0024_;
  end
  always @* begin
    if (\initial ) begin end
    _0018_ = \dp_FAST_fast1_branch0_3$next ;
  end
  always @(posedge coresync_clk) begin
      dp_FAST_fast1_branch0_3 <= _0018_;
  end
  always @* begin
    if (\initial ) begin end
    _0020_ = \dp_FAST_fast1_spr0_2$next ;
  end
  always @(posedge coresync_clk) begin
      dp_FAST_fast1_spr0_2 <= _0020_;
  end
  always @* begin
    if (\initial ) begin end
    _0022_ = \dp_FAST_fast1_trap0_1$next ;
  end
  always @(posedge coresync_clk) begin
      dp_FAST_fast1_trap0_1 <= _0022_;
  end
  always @* begin
    if (\initial ) begin end
    _0016_ = \dp_FAST_fast1_branch0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_FAST_fast1_branch0_0 <= _0016_;
  end
  always @* begin
    if (\initial ) begin end
    _0012_ = \dp_CR_cr_c_cr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_CR_cr_c_cr0_0 <= _0012_;
  end
  always @* begin
    if (\initial ) begin end
    _0010_ = \dp_CR_cr_b_cr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_CR_cr_b_cr0_0 <= _0010_;
  end
  always @* begin
    if (\initial ) begin end
    _0006_ = \dp_CR_cr_a_branch0_1$next ;
  end
  always @(posedge coresync_clk) begin
      dp_CR_cr_a_branch0_1 <= _0006_;
  end
  always @* begin
    if (\initial ) begin end
    _0008_ = \dp_CR_cr_a_cr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_CR_cr_a_cr0_0 <= _0008_;
  end
  always @* begin
    if (\initial ) begin end
    _0014_ = \dp_CR_full_cr_cr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_CR_full_cr_cr0_0 <= _0014_;
  end
  always @* begin
    if (\initial ) begin end
    _0072_ = \dp_XER_xer_ov_spr0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_ov_spr0_0 <= _0072_;
  end
  always @* begin
    if (\initial ) begin end
    _0068_ = \dp_XER_xer_ca_shiftrot0_2$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_ca_shiftrot0_2 <= _0068_;
  end
  always @* begin
    if (\initial ) begin end
    _0070_ = \dp_XER_xer_ca_spr0_1$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_ca_spr0_1 <= _0070_;
  end
  always @* begin
    if (\initial ) begin end
    _0066_ = \dp_XER_xer_ca_alu0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_ca_alu0_0 <= _0066_;
  end
  always @* begin
    if (\initial ) begin end
    _0082_ = \dp_XER_xer_so_shiftrot0_5$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_shiftrot0_5 <= _0082_;
  end
  always @* begin
    if (\initial ) begin end
    _0080_ = \dp_XER_xer_so_mul0_4$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_mul0_4 <= _0080_;
  end
  always @* begin
    if (\initial ) begin end
    _0076_ = \dp_XER_xer_so_div0_3$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_div0_3 <= _0076_;
  end
  always @* begin
    if (\initial ) begin end
    _0084_ = \dp_XER_xer_so_spr0_2$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_spr0_2 <= _0084_;
  end
  always @* begin
    if (\initial ) begin end
    _0078_ = \dp_XER_xer_so_logical0_1$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_logical0_1 <= _0078_;
  end
  always @* begin
    if (\initial ) begin end
    _0074_ = \dp_XER_xer_so_alu0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_XER_xer_so_alu0_0 <= _0074_;
  end
  always @* begin
    if (\initial ) begin end
    _0038_ = \dp_INT_rabc_ldst0_18$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_ldst0_18 <= _0038_;
  end
  always @* begin
    if (\initial ) begin end
    _0052_ = \dp_INT_rabc_shiftrot0_17$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_shiftrot0_17 <= _0052_;
  end
  always @* begin
    if (\initial ) begin end
    _0048_ = \dp_INT_rabc_mul0_16$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_mul0_16 <= _0048_;
  end
  always @* begin
    if (\initial ) begin end
    _0034_ = \dp_INT_rabc_div0_15$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_div0_15 <= _0034_;
  end
  always @* begin
    if (\initial ) begin end
    _0058_ = \dp_INT_rabc_spr0_14$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_spr0_14 <= _0058_;
  end
  always @* begin
    if (\initial ) begin end
    _0044_ = \dp_INT_rabc_logical0_13$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_logical0_13 <= _0044_;
  end
  always @* begin
    if (\initial ) begin end
    _0060_ = \dp_INT_rabc_trap0_12$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_trap0_12 <= _0060_;
  end
  always @* begin
    if (\initial ) begin end
    _0031_ = \dp_INT_rabc_cr0_11$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_cr0_11 <= _0031_;
  end
  always @* begin
    if (\initial ) begin end
    _0028_ = \dp_INT_rabc_alu0_10$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_alu0_10 <= _0028_;
  end
  always @* begin
    if (\initial ) begin end
    _0042_ = \dp_INT_rabc_ldst0_9$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_ldst0_9 <= _0042_;
  end
  always @* begin
    if (\initial ) begin end
    _0056_ = \dp_INT_rabc_shiftrot0_8$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_shiftrot0_8 <= _0056_;
  end
  always @* begin
    if (\initial ) begin end
    _0040_ = \dp_INT_rabc_ldst0_7$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_ldst0_7 <= _0040_;
  end
  always @* begin
    if (\initial ) begin end
    _0054_ = \dp_INT_rabc_shiftrot0_6$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_shiftrot0_6 <= _0054_;
  end
  always @* begin
    if (\initial ) begin end
    _0050_ = \dp_INT_rabc_mul0_5$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_mul0_5 <= _0050_;
  end
  always @* begin
    if (\initial ) begin end
    _0036_ = \dp_INT_rabc_div0_4$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_div0_4 <= _0036_;
  end
  always @* begin
    if (\initial ) begin end
    _0046_ = \dp_INT_rabc_logical0_3$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_logical0_3 <= _0046_;
  end
  always @* begin
    if (\initial ) begin end
    _0062_ = \dp_INT_rabc_trap0_2$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_trap0_2 <= _0062_;
  end
  always @* begin
    if (\initial ) begin end
    _0032_ = \dp_INT_rabc_cr0_1$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_cr0_1 <= _0032_;
  end
  always @* begin
    if (\initial ) begin end
    _0026_ = \dp_INT_rabc_alu0_0$next ;
  end
  always @(posedge coresync_clk) begin
      dp_INT_rabc_alu0_0 <= _0026_;
  end
  always @* begin
    if (\initial ) begin end
    _0001_ = \core_terminate_o$next ;
  end
  always @(posedge coresync_clk) begin
      core_terminate_o <= _0001_;
  end
  always @* begin
    if (\initial ) begin end
    _0004_ = \counter$next ;
  end
  always @(posedge coresync_clk) begin
      counter <= _0004_;
  end
  always @* begin
    if (\initial ) begin end
    _0165_ = _0548_;
    (* src = "libresoc.v:43504.5-43504.29" *)
    casez (\initial )
      /* src = "libresoc.v:43504.9-43504.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0548_ = _0772_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0772_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0772_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0772_ = _0918_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0918_ = dec_LOGICAL_LOGICAL__output_carry;
                    end
                  default:
                      _0918_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0548_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__output_carry <= _0165_;
  end
  always @* begin
    if (\initial ) begin end
    _0161_ = _0544_;
    (* src = "libresoc.v:43533.5-43533.29" *)
    casez (\initial )
      /* src = "libresoc.v:43533.9-43533.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0544_ = _0768_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0768_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0768_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0768_ = _0914_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0914_ = dec_LOGICAL_LOGICAL__is_32bit;
                    end
                  default:
                      _0914_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0544_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__is_32bit <= _0161_;
  end
  always @* begin
    if (\initial ) begin end
    _0162_ = _0545_;
    (* src = "libresoc.v:43562.5-43562.29" *)
    casez (\initial )
      /* src = "libresoc.v:43562.9-43562.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0545_ = _0769_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0769_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0769_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0769_ = _0915_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0915_ = dec_LOGICAL_LOGICAL__is_signed;
                    end
                  default:
                      _0915_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0545_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__is_signed <= _0162_;
  end
  always @* begin
    if (\initial ) begin end
    _0152_ = _0535_;
    (* src = "libresoc.v:43591.5-43591.29" *)
    casez (\initial )
      /* src = "libresoc.v:43591.9-43591.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0535_ = _0759_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0759_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0759_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0759_ = _0905_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0905_ = dec_LOGICAL_LOGICAL__data_len;
                    end
                  default:
                      _0905_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0535_ = 4'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__data_len <= _0152_;
  end
  always @* begin
    if (\initial ) begin end
    _0157_ = _0540_;
    (* src = "libresoc.v:43620.5-43620.29" *)
    casez (\initial )
      /* src = "libresoc.v:43620.9-43620.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0540_ = _0764_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0764_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0764_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0764_ = _0910_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0910_ = dec_LOGICAL_LOGICAL__insn;
                    end
                  default:
                      _0910_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0540_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__insn <= _0157_;
  end
  always @* begin
    if (\initial ) begin end
    _0088_ = _0471_;
    (* src = "libresoc.v:43649.5-43649.29" *)
    casez (\initial )
      /* src = "libresoc.v:43649.9-43649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0471_ = _0695_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0695_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0695_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0695_ = _0841_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0841_ = issue_i;
                    end
                  default:
                      _0841_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0471_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$22  <= _0088_;
  end
  always @* begin
    if (\initial ) begin end
    _0098_ = _0481_;
    (* src = "libresoc.v:43678.5-43678.29" *)
    casez (\initial )
      /* src = "libresoc.v:43678.9-43678.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0481_ = _0705_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0705_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0705_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0705_ = _0851_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0851_ = \$256 ;
                    end
                  default:
                      _0851_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _0481_ = 3'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$24  <= _0098_;
  end
  always @* begin
    if (\initial ) begin end
    _0201_ = _0584_;
    (* src = "libresoc.v:43707.5-43707.29" *)
    casez (\initial )
      /* src = "libresoc.v:43707.9-43707.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0584_ = _0808_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0808_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0808_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0808_ = _0954_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0954_ = dec_SPR_SPR__insn_type;
                    end
                  default:
                      _0954_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0584_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_spr0__insn_type <= _0201_;
  end
  always @* begin
    if (\initial ) begin end
    _0199_ = _0582_;
    (* src = "libresoc.v:43736.5-43736.29" *)
    casez (\initial )
      /* src = "libresoc.v:43736.9-43736.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0582_ = _0806_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0806_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0806_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0806_ = _0952_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0952_ = dec_SPR_SPR__fn_unit;
                    end
                  default:
                      _0952_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0582_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_spr0__fn_unit <= _0199_;
  end
  always @* begin
    if (\initial ) begin end
    _0200_ = _0583_;
    (* src = "libresoc.v:43765.5-43765.29" *)
    casez (\initial )
      /* src = "libresoc.v:43765.9-43765.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0583_ = _0807_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0807_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0807_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0807_ = _0953_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0953_ = dec_SPR_SPR__insn;
                    end
                  default:
                      _0953_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0583_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_spr0__insn <= _0200_;
  end
  always @* begin
    if (\initial ) begin end
    _0202_ = _0585_;
    (* src = "libresoc.v:43794.5-43794.29" *)
    casez (\initial )
      /* src = "libresoc.v:43794.9-43794.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0585_ = _0809_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0809_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0809_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0809_ = _0955_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0955_ = dec_SPR_SPR__is_32bit;
                    end
                  default:
                      _0955_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0585_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_spr0__is_32bit <= _0202_;
  end
  always @* begin
    if (\initial ) begin end
    _0089_ = _0472_;
    (* src = "libresoc.v:43823.5-43823.29" *)
    casez (\initial )
      /* src = "libresoc.v:43823.9-43823.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0472_ = _0696_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0696_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0696_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0696_ = _0842_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0842_ = issue_i;
                    end
                  default:
                      _0842_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0472_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$25  <= _0089_;
  end
  always @* begin
    if (\initial ) begin end
    _0099_ = _0482_;
    (* src = "libresoc.v:43852.5-43852.29" *)
    casez (\initial )
      /* src = "libresoc.v:43852.9-43852.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0482_ = _0706_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0706_ = 6'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0706_ = 6'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0706_ = _0852_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0852_ = \$270 ;
                    end
                  default:
                      _0852_ = 6'h00;
                endcase
              end
          endcase
        end
      default:
          _0482_ = 6'h00;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$27  <= _0099_;
  end
  always @* begin
    if (\initial ) begin end
    _0140_ = _0523_;
    (* src = "libresoc.v:43881.5-43881.29" *)
    casez (\initial )
      /* src = "libresoc.v:43881.9-43881.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0523_ = _0747_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0747_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0747_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0747_ = _0893_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0893_ = dec_DIV_DIV__insn_type;
                    end
                  default:
                      _0893_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0523_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__insn_type <= _0140_;
  end
  always @* begin
    if (\initial ) begin end
    _0135_ = _0518_;
    (* src = "libresoc.v:43910.5-43910.29" *)
    casez (\initial )
      /* src = "libresoc.v:43910.9-43910.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0518_ = _0742_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0742_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0742_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0742_ = _0888_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0888_ = dec_DIV_DIV__fn_unit;
                    end
                  default:
                      _0888_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0518_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__fn_unit <= _0135_;
  end
  always @* begin
    if (\initial ) begin end
    _0136_ = _0519_;
    _0137_ = _0520_;
    (* src = "libresoc.v:43939.5-43939.29" *)
    casez (\initial )
      /* src = "libresoc.v:43939.9-43939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0519_ = _0743_;
          _0520_ = _0744_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0743_ = 64'h0000000000000000;
                _0744_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0743_ = 64'h0000000000000000;
                _0744_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0743_ = _0889_;
                _0744_ = _0890_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0890_, _0889_ } = { dec_DIV_DIV__imm_data__ok, dec_DIV_DIV__imm_data__data };
                    end
                  default:
                    begin
                      _0889_ = 64'h0000000000000000;
                      _0890_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0519_ = 64'h0000000000000000;
          _0520_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__imm_data__data <= _0136_;
      fus_oper_i_alu_div0__imm_data__ok <= _0137_;
  end
  always @* begin
    if (\initial ) begin end
    _0148_ = _0531_;
    _0149_ = _0532_;
    (* src = "libresoc.v:43969.5-43969.29" *)
    casez (\initial )
      /* src = "libresoc.v:43969.9-43969.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0531_ = _0755_;
          _0532_ = _0756_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0755_ = 1'h0;
                _0756_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0755_ = 1'h0;
                _0756_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0755_ = _0901_;
                _0756_ = _0902_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0901_, _0902_ } = { dec_DIV_DIV__rc__ok, dec_DIV_DIV__rc__rc };
                    end
                  default:
                    begin
                      _0901_ = 1'h0;
                      _0902_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0531_ = 1'h0;
          _0532_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__rc__ok <= _0148_;
      fus_oper_i_alu_div0__rc__rc <= _0149_;
  end
  always @* begin
    if (\initial ) begin end
    _0145_ = _0528_;
    _0146_ = _0529_;
    (* src = "libresoc.v:43999.5-43999.29" *)
    casez (\initial )
      /* src = "libresoc.v:43999.9-43999.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0528_ = _0752_;
          _0529_ = _0753_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0752_ = 1'h0;
                _0753_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0752_ = 1'h0;
                _0753_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0752_ = _0898_;
                _0753_ = _0899_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0899_, _0898_ } = { dec_DIV_DIV__oe__ok, dec_DIV_DIV__oe__oe };
                    end
                  default:
                    begin
                      _0898_ = 1'h0;
                      _0899_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0528_ = 1'h0;
          _0529_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__oe__oe <= _0145_;
      fus_oper_i_alu_div0__oe__ok <= _0146_;
  end
  always @* begin
    if (\initial ) begin end
    _0141_ = _0524_;
    (* src = "libresoc.v:44029.5-44029.29" *)
    casez (\initial )
      /* src = "libresoc.v:44029.9-44029.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0524_ = _0748_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0748_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0748_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0748_ = _0894_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0894_ = dec_DIV_DIV__invert_in;
                    end
                  default:
                      _0894_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0524_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__invert_in <= _0141_;
  end
  always @* begin
    if (\initial ) begin end
    _0151_ = _0534_;
    (* src = "libresoc.v:44058.5-44058.29" *)
    casez (\initial )
      /* src = "libresoc.v:44058.9-44058.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0534_ = _0758_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0758_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0758_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0758_ = _0904_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0904_ = dec_DIV_DIV__zero_a;
                    end
                  default:
                      _0904_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0534_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__zero_a <= _0151_;
  end
  always @* begin
    if (\initial ) begin end
    _0138_ = _0521_;
    (* src = "libresoc.v:44087.5-44087.29" *)
    casez (\initial )
      /* src = "libresoc.v:44087.9-44087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0521_ = _0745_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0745_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0745_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0745_ = _0891_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0891_ = dec_DIV_DIV__input_carry;
                    end
                  default:
                      _0891_ = 2'h0;
                endcase
              end
          endcase
        end
      default:
          _0521_ = 2'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__input_carry <= _0138_;
  end
  always @* begin
    if (\initial ) begin end
    _0142_ = _0525_;
    (* src = "libresoc.v:44116.5-44116.29" *)
    casez (\initial )
      /* src = "libresoc.v:44116.9-44116.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0525_ = _0749_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0749_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0749_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0749_ = _0895_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0895_ = dec_DIV_DIV__invert_out;
                    end
                  default:
                      _0895_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0525_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__invert_out <= _0142_;
  end
  always @* begin
    if (\initial ) begin end
    _0150_ = _0533_;
    (* src = "libresoc.v:44145.5-44145.29" *)
    casez (\initial )
      /* src = "libresoc.v:44145.9-44145.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0533_ = _0757_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0757_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0757_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0757_ = _0903_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0903_ = dec_DIV_DIV__write_cr0;
                    end
                  default:
                      _0903_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0533_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__write_cr0 <= _0150_;
  end
  always @* begin
    if (\initial ) begin end
    _0147_ = _0530_;
    (* src = "libresoc.v:44174.5-44174.29" *)
    casez (\initial )
      /* src = "libresoc.v:44174.9-44174.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0530_ = _0754_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0754_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0754_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0754_ = _0900_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0900_ = dec_DIV_DIV__output_carry;
                    end
                  default:
                      _0900_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0530_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__output_carry <= _0147_;
  end
  always @* begin
    if (\initial ) begin end
    _0143_ = _0526_;
    (* src = "libresoc.v:44203.5-44203.29" *)
    casez (\initial )
      /* src = "libresoc.v:44203.9-44203.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0526_ = _0750_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0750_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0750_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0750_ = _0896_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0896_ = dec_DIV_DIV__is_32bit;
                    end
                  default:
                      _0896_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0526_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__is_32bit <= _0143_;
  end
  always @* begin
    if (\initial ) begin end
    _0144_ = _0527_;
    (* src = "libresoc.v:44232.5-44232.29" *)
    casez (\initial )
      /* src = "libresoc.v:44232.9-44232.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0527_ = _0751_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0751_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0751_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0751_ = _0897_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0897_ = dec_DIV_DIV__is_signed;
                    end
                  default:
                      _0897_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0527_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__is_signed <= _0144_;
  end
  always @* begin
    if (\initial ) begin end
    _0134_ = _0517_;
    (* src = "libresoc.v:44261.5-44261.29" *)
    casez (\initial )
      /* src = "libresoc.v:44261.9-44261.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0517_ = _0741_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0741_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0741_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0741_ = _0887_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0887_ = dec_DIV_DIV__data_len;
                    end
                  default:
                      _0887_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0517_ = 4'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__data_len <= _0134_;
  end
  always @* begin
    if (\initial ) begin end
    _0139_ = _0522_;
    (* src = "libresoc.v:44290.5-44290.29" *)
    casez (\initial )
      /* src = "libresoc.v:44290.9-44290.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0522_ = _0746_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0746_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0746_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0746_ = _0892_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0892_ = dec_DIV_DIV__insn;
                    end
                  default:
                      _0892_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0522_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_div0__insn <= _0139_;
  end
  always @* begin
    if (\initial ) begin end
    _0090_ = _0473_;
    (* src = "libresoc.v:44319.5-44319.29" *)
    casez (\initial )
      /* src = "libresoc.v:44319.9-44319.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0473_ = _0697_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0697_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0697_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0697_ = _0843_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0843_ = issue_i;
                    end
                  default:
                      _0843_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0473_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$28  <= _0090_;
  end
  always @* begin
    if (\initial ) begin end
    _0100_ = _0483_;
    (* src = "libresoc.v:44348.5-44348.29" *)
    casez (\initial )
      /* src = "libresoc.v:44348.9-44348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0483_ = _0707_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0707_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0707_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0707_ = _0853_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0853_ = \$300 ;
                    end
                  default:
                      _0853_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _0483_ = 3'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$30  <= _0100_;
  end
  always @* begin
    if (\initial ) begin end
    _0174_ = _0557_;
    (* src = "libresoc.v:44377.5-44377.29" *)
    casez (\initial )
      /* src = "libresoc.v:44377.9-44377.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0557_ = _0781_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0781_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0781_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0781_ = _0927_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0927_ = dec_MUL_MUL__insn_type;
                    end
                  default:
                      _0927_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0557_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__insn_type <= _0174_;
  end
  always @* begin
    if (\initial ) begin end
    _0170_ = _0553_;
    (* src = "libresoc.v:44406.5-44406.29" *)
    casez (\initial )
      /* src = "libresoc.v:44406.9-44406.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0553_ = _0777_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0777_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0777_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0777_ = _0923_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0923_ = dec_MUL_MUL__fn_unit;
                    end
                  default:
                      _0923_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0553_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__fn_unit <= _0170_;
  end
  always @* begin
    if (\initial ) begin end
    _0171_ = _0554_;
    _0172_ = _0555_;
    (* src = "libresoc.v:44435.5-44435.29" *)
    casez (\initial )
      /* src = "libresoc.v:44435.9-44435.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0554_ = _0778_;
          _0555_ = _0779_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0778_ = 64'h0000000000000000;
                _0779_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0778_ = 64'h0000000000000000;
                _0779_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0778_ = _0924_;
                _0779_ = _0925_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0925_, _0924_ } = { dec_MUL_MUL__imm_data__ok, dec_MUL_MUL__imm_data__data };
                    end
                  default:
                    begin
                      _0924_ = 64'h0000000000000000;
                      _0925_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0554_ = 64'h0000000000000000;
          _0555_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__imm_data__data <= _0171_;
      fus_oper_i_alu_mul0__imm_data__ok <= _0172_;
  end
  always @* begin
    if (\initial ) begin end
    _0179_ = _0562_;
    _0180_ = _0563_;
    (* src = "libresoc.v:44465.5-44465.29" *)
    casez (\initial )
      /* src = "libresoc.v:44465.9-44465.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0562_ = _0786_;
          _0563_ = _0787_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0786_ = 1'h0;
                _0787_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0786_ = 1'h0;
                _0787_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0786_ = _0932_;
                _0787_ = _0933_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0932_, _0933_ } = { dec_MUL_MUL__rc__ok, dec_MUL_MUL__rc__rc };
                    end
                  default:
                    begin
                      _0932_ = 1'h0;
                      _0933_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0562_ = 1'h0;
          _0563_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__rc__ok <= _0179_;
      fus_oper_i_alu_mul0__rc__rc <= _0180_;
  end
  always @* begin
    if (\initial ) begin end
    _0177_ = _0560_;
    _0178_ = _0561_;
    (* src = "libresoc.v:44495.5-44495.29" *)
    casez (\initial )
      /* src = "libresoc.v:44495.9-44495.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0560_ = _0784_;
          _0561_ = _0785_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0784_ = 1'h0;
                _0785_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0784_ = 1'h0;
                _0785_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0784_ = _0930_;
                _0785_ = _0931_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0931_, _0930_ } = { dec_MUL_MUL__oe__ok, dec_MUL_MUL__oe__oe };
                    end
                  default:
                    begin
                      _0930_ = 1'h0;
                      _0931_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0560_ = 1'h0;
          _0561_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__oe__oe <= _0177_;
      fus_oper_i_alu_mul0__oe__ok <= _0178_;
  end
  always @* begin
    if (\initial ) begin end
    _0181_ = _0564_;
    (* src = "libresoc.v:44525.5-44525.29" *)
    casez (\initial )
      /* src = "libresoc.v:44525.9-44525.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0564_ = _0788_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0788_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0788_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0788_ = _0934_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0934_ = dec_MUL_MUL__write_cr0;
                    end
                  default:
                      _0934_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0564_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__write_cr0 <= _0181_;
  end
  always @* begin
    if (\initial ) begin end
    _0175_ = _0558_;
    (* src = "libresoc.v:44554.5-44554.29" *)
    casez (\initial )
      /* src = "libresoc.v:44554.9-44554.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0558_ = _0782_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0782_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0782_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0782_ = _0928_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0928_ = dec_MUL_MUL__is_32bit;
                    end
                  default:
                      _0928_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0558_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__is_32bit <= _0175_;
  end
  always @* begin
    if (\initial ) begin end
    _0176_ = _0559_;
    (* src = "libresoc.v:44583.5-44583.29" *)
    casez (\initial )
      /* src = "libresoc.v:44583.9-44583.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0559_ = _0783_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0783_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0783_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0783_ = _0929_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0929_ = dec_MUL_MUL__is_signed;
                    end
                  default:
                      _0929_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0559_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__is_signed <= _0176_;
  end
  always @* begin
    if (\initial ) begin end
    _0173_ = _0556_;
    (* src = "libresoc.v:44612.5-44612.29" *)
    casez (\initial )
      /* src = "libresoc.v:44612.9-44612.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0556_ = _0780_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0780_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0780_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0780_ = _0926_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0926_ = dec_MUL_MUL__insn;
                    end
                  default:
                      _0926_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0556_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_mul0__insn <= _0173_;
  end
  always @* begin
    if (\initial ) begin end
    _0091_ = _0474_;
    (* src = "libresoc.v:44641.5-44641.29" *)
    casez (\initial )
      /* src = "libresoc.v:44641.9-44641.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0474_ = _0698_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0698_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0698_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0698_ = _0844_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0844_ = issue_i;
                    end
                  default:
                      _0844_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0474_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$31  <= _0091_;
  end
  always @* begin
    if (\initial ) begin end
    _0101_ = _0484_;
    (* src = "libresoc.v:44670.5-44670.29" *)
    casez (\initial )
      /* src = "libresoc.v:44670.9-44670.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0484_ = _0708_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0708_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0708_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0708_ = _0854_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0854_ = \$314 ;
                    end
                  default:
                      _0854_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _0484_ = 3'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$33  <= _0101_;
  end
  always @* begin
    if (\initial ) begin end
    _0188_ = _0571_;
    (* src = "libresoc.v:44699.5-44699.29" *)
    casez (\initial )
      /* src = "libresoc.v:44699.9-44699.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0571_ = _0795_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0795_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0795_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0795_ = _0941_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0941_ = dec_SHIFT_ROT_SHIFT_ROT__insn_type;
                    end
                  default:
                      _0941_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0571_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__insn_type <= _0188_;
  end
  always @* begin
    if (\initial ) begin end
    _0182_ = _0565_;
    (* src = "libresoc.v:44728.5-44728.29" *)
    casez (\initial )
      /* src = "libresoc.v:44728.9-44728.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0565_ = _0789_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0789_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0789_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0789_ = _0935_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0935_ = dec_SHIFT_ROT_SHIFT_ROT__fn_unit;
                    end
                  default:
                      _0935_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0565_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__fn_unit <= _0182_;
  end
  always @* begin
    if (\initial ) begin end
    _0183_ = _0566_;
    _0184_ = _0567_;
    (* src = "libresoc.v:44757.5-44757.29" *)
    casez (\initial )
      /* src = "libresoc.v:44757.9-44757.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0566_ = _0790_;
          _0567_ = _0791_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0790_ = 64'h0000000000000000;
                _0791_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0790_ = 64'h0000000000000000;
                _0791_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0790_ = _0936_;
                _0791_ = _0937_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0937_, _0936_ } = { dec_SHIFT_ROT_SHIFT_ROT__imm_data__ok, dec_SHIFT_ROT_SHIFT_ROT__imm_data__data };
                    end
                  default:
                    begin
                      _0936_ = 64'h0000000000000000;
                      _0937_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0566_ = 64'h0000000000000000;
          _0567_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__imm_data__data <= _0183_;
      fus_oper_i_alu_shift_rot0__imm_data__ok <= _0184_;
  end
  always @* begin
    if (\initial ) begin end
    _0196_ = _0579_;
    _0197_ = _0580_;
    (* src = "libresoc.v:44787.5-44787.29" *)
    casez (\initial )
      /* src = "libresoc.v:44787.9-44787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0579_ = _0803_;
          _0580_ = _0804_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0803_ = 1'h0;
                _0804_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0803_ = 1'h0;
                _0804_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0803_ = _0949_;
                _0804_ = _0950_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0949_, _0950_ } = { dec_SHIFT_ROT_SHIFT_ROT__rc__ok, dec_SHIFT_ROT_SHIFT_ROT__rc__rc };
                    end
                  default:
                    begin
                      _0949_ = 1'h0;
                      _0950_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0579_ = 1'h0;
          _0580_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__rc__ok <= _0196_;
      fus_oper_i_alu_shift_rot0__rc__rc <= _0197_;
  end
  always @* begin
    if (\initial ) begin end
    _0192_ = _0575_;
    _0193_ = _0576_;
    (* src = "libresoc.v:44817.5-44817.29" *)
    casez (\initial )
      /* src = "libresoc.v:44817.9-44817.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0575_ = _0799_;
          _0576_ = _0800_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0799_ = 1'h0;
                _0800_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0799_ = 1'h0;
                _0800_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0799_ = _0945_;
                _0800_ = _0946_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0946_, _0945_ } = { dec_SHIFT_ROT_SHIFT_ROT__oe__ok, dec_SHIFT_ROT_SHIFT_ROT__oe__oe };
                    end
                  default:
                    begin
                      _0945_ = 1'h0;
                      _0946_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0575_ = 1'h0;
          _0576_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__oe__oe <= _0192_;
      fus_oper_i_alu_shift_rot0__oe__ok <= _0193_;
  end
  always @* begin
    if (\initial ) begin end
    _0198_ = _0581_;
    (* src = "libresoc.v:44847.5-44847.29" *)
    casez (\initial )
      /* src = "libresoc.v:44847.9-44847.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0581_ = _0805_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0805_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0805_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0805_ = _0951_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0951_ = dec_SHIFT_ROT_SHIFT_ROT__write_cr0;
                    end
                  default:
                      _0951_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0581_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__write_cr0 <= _0198_;
  end
  always @* begin
    if (\initial ) begin end
    _0189_ = _0572_;
    (* src = "libresoc.v:44876.5-44876.29" *)
    casez (\initial )
      /* src = "libresoc.v:44876.9-44876.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0572_ = _0796_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0796_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0796_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0796_ = _0942_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0942_ = dec_SHIFT_ROT_SHIFT_ROT__invert_in;
                    end
                  default:
                      _0942_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0572_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__invert_in <= _0189_;
  end
  always @* begin
    if (\initial ) begin end
    _0185_ = _0568_;
    (* src = "libresoc.v:44905.5-44905.29" *)
    casez (\initial )
      /* src = "libresoc.v:44905.9-44905.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0568_ = _0792_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0792_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0792_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0792_ = _0938_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0938_ = dec_SHIFT_ROT_SHIFT_ROT__input_carry;
                    end
                  default:
                      _0938_ = 2'h0;
                endcase
              end
          endcase
        end
      default:
          _0568_ = 2'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__input_carry <= _0185_;
  end
  always @* begin
    if (\initial ) begin end
    _0194_ = _0577_;
    (* src = "libresoc.v:44934.5-44934.29" *)
    casez (\initial )
      /* src = "libresoc.v:44934.9-44934.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0577_ = _0801_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0801_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0801_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0801_ = _0947_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0947_ = dec_SHIFT_ROT_SHIFT_ROT__output_carry;
                    end
                  default:
                      _0947_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0577_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__output_carry <= _0194_;
  end
  always @* begin
    if (\initial ) begin end
    _0186_ = _0569_;
    (* src = "libresoc.v:44963.5-44963.29" *)
    casez (\initial )
      /* src = "libresoc.v:44963.9-44963.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0569_ = _0793_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0793_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0793_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0793_ = _0939_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0939_ = dec_SHIFT_ROT_SHIFT_ROT__input_cr;
                    end
                  default:
                      _0939_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0569_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__input_cr <= _0186_;
  end
  always @* begin
    if (\initial ) begin end
    _0195_ = _0578_;
    (* src = "libresoc.v:44992.5-44992.29" *)
    casez (\initial )
      /* src = "libresoc.v:44992.9-44992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0578_ = _0802_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0802_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0802_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0802_ = _0948_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0948_ = dec_SHIFT_ROT_SHIFT_ROT__output_cr;
                    end
                  default:
                      _0948_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0578_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__output_cr <= _0195_;
  end
  always @* begin
    if (\initial ) begin end
    _0190_ = _0573_;
    (* src = "libresoc.v:45021.5-45021.29" *)
    casez (\initial )
      /* src = "libresoc.v:45021.9-45021.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0573_ = _0797_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0797_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0797_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0797_ = _0943_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0943_ = dec_SHIFT_ROT_SHIFT_ROT__is_32bit;
                    end
                  default:
                      _0943_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0573_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__is_32bit <= _0190_;
  end
  always @* begin
    if (\initial ) begin end
    _0191_ = _0574_;
    (* src = "libresoc.v:45050.5-45050.29" *)
    casez (\initial )
      /* src = "libresoc.v:45050.9-45050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0574_ = _0798_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0798_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0798_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0798_ = _0944_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0944_ = dec_SHIFT_ROT_SHIFT_ROT__is_signed;
                    end
                  default:
                      _0944_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0574_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__is_signed <= _0191_;
  end
  always @* begin
    if (\initial ) begin end
    _0187_ = _0570_;
    (* src = "libresoc.v:45079.5-45079.29" *)
    casez (\initial )
      /* src = "libresoc.v:45079.9-45079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0570_ = _0794_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0794_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0794_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0794_ = _0940_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0940_ = dec_SHIFT_ROT_SHIFT_ROT__insn;
                    end
                  default:
                      _0940_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0570_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_shift_rot0__insn <= _0187_;
  end
  always @* begin
    if (\initial ) begin end
    _0092_ = _0475_;
    (* src = "libresoc.v:45108.5-45108.29" *)
    casez (\initial )
      /* src = "libresoc.v:45108.9-45108.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0475_ = _0699_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0699_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0699_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0699_ = _0845_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0845_ = issue_i;
                    end
                  default:
                      _0845_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0475_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$34  <= _0092_;
  end
  always @* begin
    if (\initial ) begin end
    _0102_ = _0485_;
    (* src = "libresoc.v:45137.5-45137.29" *)
    casez (\initial )
      /* src = "libresoc.v:45137.9-45137.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0485_ = _0709_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0709_ = 5'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0709_ = 5'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0709_ = _0855_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0855_ = \$328 ;
                    end
                  default:
                      _0855_ = 5'h00;
                endcase
              end
          endcase
        end
      default:
          _0485_ = 5'h00;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$36  <= _0102_;
  end
  always @* begin
    if (\initial ) begin end
    _0218_ = _0601_;
    (* src = "libresoc.v:45166.5-45166.29" *)
    casez (\initial )
      /* src = "libresoc.v:45166.9-45166.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0601_ = _0825_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0825_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0825_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0825_ = _0971_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0971_ = dec_LDST_LDST__insn_type;
                    end
                  default:
                      _0971_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0601_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__insn_type <= _0218_;
  end
  always @* begin
    if (\initial ) begin end
    _0214_ = _0597_;
    (* src = "libresoc.v:45195.5-45195.29" *)
    casez (\initial )
      /* src = "libresoc.v:45195.9-45195.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0597_ = _0821_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0821_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0821_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0821_ = _0967_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0967_ = dec_LDST_LDST__fn_unit;
                    end
                  default:
                      _0967_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0597_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__fn_unit <= _0214_;
  end
  always @* begin
    if (\initial ) begin end
    _0215_ = _0598_;
    _0216_ = _0599_;
    (* src = "libresoc.v:45224.5-45224.29" *)
    casez (\initial )
      /* src = "libresoc.v:45224.9-45224.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0598_ = _0822_;
          _0599_ = _0823_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0822_ = 64'h0000000000000000;
                _0823_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0822_ = 64'h0000000000000000;
                _0823_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0822_ = _0968_;
                _0823_ = _0969_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0969_, _0968_ } = { dec_LDST_LDST__imm_data__ok, dec_LDST_LDST__imm_data__data };
                    end
                  default:
                    begin
                      _0968_ = 64'h0000000000000000;
                      _0969_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0598_ = 64'h0000000000000000;
          _0599_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__imm_data__data <= _0215_;
      fus_oper_i_ldst_ldst0__imm_data__ok <= _0216_;
  end
  always @* begin
    if (\initial ) begin end
    _0227_ = _0610_;
    (* src = "libresoc.v:45254.5-45254.29" *)
    casez (\initial )
      /* src = "libresoc.v:45254.9-45254.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0610_ = _0834_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0834_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0834_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0834_ = _0980_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0980_ = dec_LDST_LDST__zero_a;
                    end
                  default:
                      _0980_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0610_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__zero_a <= _0227_;
  end
  always @* begin
    if (\initial ) begin end
    _0224_ = _0607_;
    _0225_ = _0608_;
    (* src = "libresoc.v:45283.5-45283.29" *)
    casez (\initial )
      /* src = "libresoc.v:45283.9-45283.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0607_ = _0831_;
          _0608_ = _0832_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0831_ = 1'h0;
                _0832_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0831_ = 1'h0;
                _0832_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0831_ = _0977_;
                _0832_ = _0978_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0977_, _0978_ } = { dec_LDST_LDST__rc__ok, dec_LDST_LDST__rc__rc };
                    end
                  default:
                    begin
                      _0977_ = 1'h0;
                      _0978_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0607_ = 1'h0;
          _0608_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__rc__ok <= _0224_;
      fus_oper_i_ldst_ldst0__rc__rc <= _0225_;
  end
  always @* begin
    if (\initial ) begin end
    _0222_ = _0605_;
    _0223_ = _0606_;
    (* src = "libresoc.v:45313.5-45313.29" *)
    casez (\initial )
      /* src = "libresoc.v:45313.9-45313.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0605_ = _0829_;
          _0606_ = _0830_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0829_ = 1'h0;
                _0830_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0829_ = 1'h0;
                _0830_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0829_ = _0975_;
                _0830_ = _0976_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0976_, _0975_ } = { dec_LDST_LDST__oe__ok, dec_LDST_LDST__oe__oe };
                    end
                  default:
                    begin
                      _0975_ = 1'h0;
                      _0976_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0605_ = 1'h0;
          _0606_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__oe__oe <= _0222_;
      fus_oper_i_ldst_ldst0__oe__ok <= _0223_;
  end
  always @* begin
    if (\initial ) begin end
    _0219_ = _0602_;
    (* src = "libresoc.v:45343.5-45343.29" *)
    casez (\initial )
      /* src = "libresoc.v:45343.9-45343.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0602_ = _0826_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0826_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0826_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0826_ = _0972_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0972_ = dec_LDST_LDST__is_32bit;
                    end
                  default:
                      _0972_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0602_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__is_32bit <= _0219_;
  end
  always @* begin
    if (\initial ) begin end
    _0220_ = _0603_;
    (* src = "libresoc.v:45372.5-45372.29" *)
    casez (\initial )
      /* src = "libresoc.v:45372.9-45372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0603_ = _0827_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0827_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0827_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0827_ = _0973_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0973_ = dec_LDST_LDST__is_signed;
                    end
                  default:
                      _0973_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0603_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__is_signed <= _0220_;
  end
  always @* begin
    if (\initial ) begin end
    _0213_ = _0596_;
    (* src = "libresoc.v:45401.5-45401.29" *)
    casez (\initial )
      /* src = "libresoc.v:45401.9-45401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0596_ = _0820_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0820_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0820_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0820_ = _0966_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0966_ = dec_LDST_LDST__data_len;
                    end
                  default:
                      _0966_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0596_ = 4'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__data_len <= _0213_;
  end
  always @* begin
    if (\initial ) begin end
    _0212_ = _0595_;
    (* src = "libresoc.v:45430.5-45430.29" *)
    casez (\initial )
      /* src = "libresoc.v:45430.9-45430.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0595_ = _0819_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0819_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0819_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0819_ = _0965_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0965_ = dec_LDST_LDST__byte_reverse;
                    end
                  default:
                      _0965_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0595_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__byte_reverse <= _0212_;
  end
  always @* begin
    if (\initial ) begin end
    _0226_ = _0609_;
    (* src = "libresoc.v:45459.5-45459.29" *)
    casez (\initial )
      /* src = "libresoc.v:45459.9-45459.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0609_ = _0833_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0833_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0833_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0833_ = _0979_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0979_ = dec_LDST_LDST__sign_extend;
                    end
                  default:
                      _0979_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0609_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__sign_extend <= _0226_;
  end
  always @* begin
    if (\initial ) begin end
    _0221_ = _0604_;
    (* src = "libresoc.v:45488.5-45488.29" *)
    casez (\initial )
      /* src = "libresoc.v:45488.9-45488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0604_ = _0828_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0828_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0828_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0828_ = _0974_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0974_ = dec_LDST_LDST__ldst_mode;
                    end
                  default:
                      _0974_ = 2'h0;
                endcase
              end
          endcase
        end
      default:
          _0604_ = 2'h0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__ldst_mode <= _0221_;
  end
  always @* begin
    if (\initial ) begin end
    _0217_ = _0600_;
    (* src = "libresoc.v:45517.5-45517.29" *)
    casez (\initial )
      /* src = "libresoc.v:45517.9-45517.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0600_ = _0824_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0824_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0824_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0824_ = _0970_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0970_ = dec_LDST_LDST__insn;
                    end
                  default:
                      _0970_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0600_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_ldst_ldst0__insn <= _0217_;
  end
  always @* begin
    if (\initial ) begin end
    _0093_ = _0476_;
    (* src = "libresoc.v:45546.5-45546.29" *)
    casez (\initial )
      /* src = "libresoc.v:45546.9-45546.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0476_ = _0700_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0700_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0700_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0700_ = _0846_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0846_ = issue_i;
                    end
                  default:
                      _0846_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0476_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$37  <= _0093_;
  end
  always @* begin
    if (\initial ) begin end
    _0103_ = _0486_;
    (* src = "libresoc.v:45575.5-45575.29" *)
    casez (\initial )
      /* src = "libresoc.v:45575.9-45575.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0486_ = _0710_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0710_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0710_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0710_ = _0856_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0856_ = \$350 ;
                    end
                  default:
                      _0856_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _0486_ = 3'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$39  <= _0103_;
  end
  always @* begin
    if (\initial ) begin end
    _0025_ = _0408_;
    (* src = "libresoc.v:45604.5-45604.29" *)
    casez (\initial )
      /* src = "libresoc.v:45604.9-45604.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0408_ = 1'h0;
        end
      default:
          _0408_ = rp_INT_rabc_alu0_0;
    endcase
  end
  always @* begin
      \dp_INT_rabc_alu0_0$next  <= _0025_;
  end
  always @* begin
    if (\initial ) begin end
    _0247_ = _0630_;
    (* src = "libresoc.v:45613.5-45613.29" *)
    casez (\initial )
      /* src = "libresoc.v:45613.9-45613.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_alu0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0630_ = int_src1__data_o;
        end
      default:
          _0630_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_src2_i <= _0247_;
  end
  always @* begin
    if (\initial ) begin end
    _0029_ = _0412_;
    (* src = "libresoc.v:45623.5-45623.29" *)
    casez (\initial )
      /* src = "libresoc.v:45623.9-45623.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0412_ = 1'h0;
        end
      default:
          _0412_ = rp_INT_rabc_cr0_1;
    endcase
  end
  always @* begin
      \dp_INT_rabc_cr0_1$next  <= _0029_;
  end
  always @* begin
    if (\initial ) begin end
    _0238_ = _0621_;
    (* src = "libresoc.v:45632.5-45632.29" *)
    casez (\initial )
      /* src = "libresoc.v:45632.9-45632.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_cr0_1)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0621_ = int_src1__data_o;
        end
      default:
          _0621_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$42  <= _0238_;
  end
  always @* begin
    if (\initial ) begin end
    _0061_ = _0444_;
    (* src = "libresoc.v:45642.5-45642.29" *)
    casez (\initial )
      /* src = "libresoc.v:45642.9-45642.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0444_ = 1'h0;
        end
      default:
          _0444_ = rp_INT_rabc_trap0_2;
    endcase
  end
  always @* begin
      \dp_INT_rabc_trap0_2$next  <= _0061_;
  end
  always @* begin
    if (\initial ) begin end
    _0239_ = _0622_;
    (* src = "libresoc.v:45651.5-45651.29" *)
    casez (\initial )
      /* src = "libresoc.v:45651.9-45651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_trap0_2)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0622_ = int_src1__data_o;
        end
      default:
          _0622_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$45  <= _0239_;
  end
  always @* begin
    if (\initial ) begin end
    _0045_ = _0428_;
    (* src = "libresoc.v:45661.5-45661.29" *)
    casez (\initial )
      /* src = "libresoc.v:45661.9-45661.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0428_ = 1'h0;
        end
      default:
          _0428_ = rp_INT_rabc_logical0_3;
    endcase
  end
  always @* begin
      \dp_INT_rabc_logical0_3$next  <= _0045_;
  end
  always @* begin
    if (\initial ) begin end
    _0240_ = _0623_;
    (* src = "libresoc.v:45670.5-45670.29" *)
    casez (\initial )
      /* src = "libresoc.v:45670.9-45670.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_logical0_3)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0623_ = int_src1__data_o;
        end
      default:
          _0623_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$48  <= _0240_;
  end
  always @* begin
    if (\initial ) begin end
    _0035_ = _0418_;
    (* src = "libresoc.v:45680.5-45680.29" *)
    casez (\initial )
      /* src = "libresoc.v:45680.9-45680.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0418_ = 1'h0;
        end
      default:
          _0418_ = rp_INT_rabc_div0_4;
    endcase
  end
  always @* begin
      \dp_INT_rabc_div0_4$next  <= _0035_;
  end
  always @* begin
    if (\initial ) begin end
    _0241_ = _0624_;
    (* src = "libresoc.v:45689.5-45689.29" *)
    casez (\initial )
      /* src = "libresoc.v:45689.9-45689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_div0_4)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0624_ = int_src1__data_o;
        end
      default:
          _0624_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$51  <= _0241_;
  end
  always @* begin
    if (\initial ) begin end
    _0049_ = _0432_;
    (* src = "libresoc.v:45699.5-45699.29" *)
    casez (\initial )
      /* src = "libresoc.v:45699.9-45699.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0432_ = 1'h0;
        end
      default:
          _0432_ = rp_INT_rabc_mul0_5;
    endcase
  end
  always @* begin
      \dp_INT_rabc_mul0_5$next  <= _0049_;
  end
  always @* begin
    if (\initial ) begin end
    _0242_ = _0625_;
    (* src = "libresoc.v:45708.5-45708.29" *)
    casez (\initial )
      /* src = "libresoc.v:45708.9-45708.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_mul0_5)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0625_ = int_src1__data_o;
        end
      default:
          _0625_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$54  <= _0242_;
  end
  always @* begin
    if (\initial ) begin end
    _0053_ = _0436_;
    (* src = "libresoc.v:45718.5-45718.29" *)
    casez (\initial )
      /* src = "libresoc.v:45718.9-45718.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0436_ = 1'h0;
        end
      default:
          _0436_ = rp_INT_rabc_shiftrot0_6;
    endcase
  end
  always @* begin
      \dp_INT_rabc_shiftrot0_6$next  <= _0053_;
  end
  always @* begin
    if (\initial ) begin end
    _0243_ = _0626_;
    (* src = "libresoc.v:45727.5-45727.29" *)
    casez (\initial )
      /* src = "libresoc.v:45727.9-45727.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_shiftrot0_6)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0626_ = int_src1__data_o;
        end
      default:
          _0626_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$57  <= _0243_;
  end
  always @* begin
    if (\initial ) begin end
    _0039_ = _0422_;
    (* src = "libresoc.v:45737.5-45737.29" *)
    casez (\initial )
      /* src = "libresoc.v:45737.9-45737.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0422_ = 1'h0;
        end
      default:
          _0422_ = rp_INT_rabc_ldst0_7;
    endcase
  end
  always @* begin
      \dp_INT_rabc_ldst0_7$next  <= _0039_;
  end
  always @* begin
    if (\initial ) begin end
    _0244_ = _0627_;
    (* src = "libresoc.v:45746.5-45746.29" *)
    casez (\initial )
      /* src = "libresoc.v:45746.9-45746.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_ldst0_7)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0627_ = int_src1__data_o;
        end
      default:
          _0627_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$60  <= _0244_;
  end
  always @* begin
    if (\initial ) begin end
    _0055_ = _0438_;
    (* src = "libresoc.v:45756.5-45756.29" *)
    casez (\initial )
      /* src = "libresoc.v:45756.9-45756.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0438_ = 1'h0;
        end
      default:
          _0438_ = rp_INT_rabc_shiftrot0_8;
    endcase
  end
  always @* begin
      \dp_INT_rabc_shiftrot0_8$next  <= _0055_;
  end
  always @* begin
    if (\initial ) begin end
    _0257_ = _0640_;
    (* src = "libresoc.v:45765.5-45765.29" *)
    casez (\initial )
      /* src = "libresoc.v:45765.9-45765.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_shiftrot0_8)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0640_ = int_src1__data_o;
        end
      default:
          _0640_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_src3_i <= _0257_;
  end
  always @* begin
    if (\initial ) begin end
    _0041_ = _0424_;
    (* src = "libresoc.v:45775.5-45775.29" *)
    casez (\initial )
      /* src = "libresoc.v:45775.9-45775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0424_ = 1'h0;
        end
      default:
          _0424_ = rp_INT_rabc_ldst0_9;
    endcase
  end
  always @* begin
      \dp_INT_rabc_ldst0_9$next  <= _0041_;
  end
  always @* begin
    if (\initial ) begin end
    _0248_ = _0631_;
    (* src = "libresoc.v:45784.5-45784.29" *)
    casez (\initial )
      /* src = "libresoc.v:45784.9-45784.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_ldst0_9)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0631_ = int_src1__data_o;
        end
      default:
          _0631_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src3_i$61  <= _0248_;
  end
  always @* begin
    if (\initial ) begin end
    _0027_ = _0410_;
    (* src = "libresoc.v:45794.5-45794.29" *)
    casez (\initial )
      /* src = "libresoc.v:45794.9-45794.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0410_ = 1'h0;
        end
      default:
          _0410_ = rp_INT_rabc_alu0_10;
    endcase
  end
  always @* begin
      \dp_INT_rabc_alu0_10$next  <= _0027_;
  end
  always @* begin
    if (\initial ) begin end
    _0237_ = _0620_;
    (* src = "libresoc.v:45803.5-45803.29" *)
    casez (\initial )
      /* src = "libresoc.v:45803.9-45803.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_alu0_10)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0620_ = int_src1__data_o;
        end
      default:
          _0620_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_src1_i <= _0237_;
  end
  always @* begin
    if (\initial ) begin end
    _0030_ = _0413_;
    (* src = "libresoc.v:45813.5-45813.29" *)
    casez (\initial )
      /* src = "libresoc.v:45813.9-45813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0413_ = 1'h0;
        end
      default:
          _0413_ = rp_INT_rabc_cr0_11;
    endcase
  end
  always @* begin
      \dp_INT_rabc_cr0_11$next  <= _0030_;
  end
  always @* begin
    if (\initial ) begin end
    _0228_ = _0611_;
    (* src = "libresoc.v:45822.5-45822.29" *)
    casez (\initial )
      /* src = "libresoc.v:45822.9-45822.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_cr0_11)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0611_ = int_src1__data_o;
        end
      default:
          _0611_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$62  <= _0228_;
  end
  always @* begin
    if (\initial ) begin end
    _0059_ = _0442_;
    (* src = "libresoc.v:45832.5-45832.29" *)
    casez (\initial )
      /* src = "libresoc.v:45832.9-45832.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0442_ = 1'h0;
        end
      default:
          _0442_ = rp_INT_rabc_trap0_12;
    endcase
  end
  always @* begin
      \dp_INT_rabc_trap0_12$next  <= _0059_;
  end
  always @* begin
    if (\initial ) begin end
    _0229_ = _0612_;
    (* src = "libresoc.v:45841.5-45841.29" *)
    casez (\initial )
      /* src = "libresoc.v:45841.9-45841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_trap0_12)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0612_ = int_src1__data_o;
        end
      default:
          _0612_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$63  <= _0229_;
  end
  always @* begin
    if (\initial ) begin end
    _0043_ = _0426_;
    (* src = "libresoc.v:45851.5-45851.29" *)
    casez (\initial )
      /* src = "libresoc.v:45851.9-45851.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0426_ = 1'h0;
        end
      default:
          _0426_ = rp_INT_rabc_logical0_13;
    endcase
  end
  always @* begin
      \dp_INT_rabc_logical0_13$next  <= _0043_;
  end
  always @* begin
    if (\initial ) begin end
    _0230_ = _0613_;
    (* src = "libresoc.v:45860.5-45860.29" *)
    casez (\initial )
      /* src = "libresoc.v:45860.9-45860.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_logical0_13)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0613_ = int_src1__data_o;
        end
      default:
          _0613_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$64  <= _0230_;
  end
  always @* begin
    if (\initial ) begin end
    _0057_ = _0440_;
    (* src = "libresoc.v:45870.5-45870.29" *)
    casez (\initial )
      /* src = "libresoc.v:45870.9-45870.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0440_ = 1'h0;
        end
      default:
          _0440_ = rp_INT_rabc_spr0_14;
    endcase
  end
  always @* begin
      \dp_INT_rabc_spr0_14$next  <= _0057_;
  end
  always @* begin
    if (\initial ) begin end
    _0231_ = _0614_;
    (* src = "libresoc.v:45879.5-45879.29" *)
    casez (\initial )
      /* src = "libresoc.v:45879.9-45879.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_spr0_14)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0614_ = int_src1__data_o;
        end
      default:
          _0614_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$67  <= _0231_;
  end
  always @* begin
    if (\initial ) begin end
    _0033_ = _0416_;
    (* src = "libresoc.v:45889.5-45889.29" *)
    casez (\initial )
      /* src = "libresoc.v:45889.9-45889.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0416_ = 1'h0;
        end
      default:
          _0416_ = rp_INT_rabc_div0_15;
    endcase
  end
  always @* begin
      \dp_INT_rabc_div0_15$next  <= _0033_;
  end
  always @* begin
    if (\initial ) begin end
    _0232_ = _0615_;
    (* src = "libresoc.v:45898.5-45898.29" *)
    casez (\initial )
      /* src = "libresoc.v:45898.9-45898.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_div0_15)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0615_ = int_src1__data_o;
        end
      default:
          _0615_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$68  <= _0232_;
  end
  always @* begin
    if (\initial ) begin end
    _0047_ = _0430_;
    (* src = "libresoc.v:45908.5-45908.29" *)
    casez (\initial )
      /* src = "libresoc.v:45908.9-45908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0430_ = 1'h0;
        end
      default:
          _0430_ = rp_INT_rabc_mul0_16;
    endcase
  end
  always @* begin
      \dp_INT_rabc_mul0_16$next  <= _0047_;
  end
  always @* begin
    if (\initial ) begin end
    _0233_ = _0616_;
    (* src = "libresoc.v:45917.5-45917.29" *)
    casez (\initial )
      /* src = "libresoc.v:45917.9-45917.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_mul0_16)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0616_ = int_src1__data_o;
        end
      default:
          _0616_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$69  <= _0233_;
  end
  always @* begin
    if (\initial ) begin end
    _0051_ = _0434_;
    (* src = "libresoc.v:45927.5-45927.29" *)
    casez (\initial )
      /* src = "libresoc.v:45927.9-45927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0434_ = 1'h0;
        end
      default:
          _0434_ = rp_INT_rabc_shiftrot0_17;
    endcase
  end
  always @* begin
      \dp_INT_rabc_shiftrot0_17$next  <= _0051_;
  end
  always @* begin
    if (\initial ) begin end
    _0234_ = _0617_;
    (* src = "libresoc.v:45936.5-45936.29" *)
    casez (\initial )
      /* src = "libresoc.v:45936.9-45936.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_shiftrot0_17)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0617_ = int_src1__data_o;
        end
      default:
          _0617_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$70  <= _0234_;
  end
  always @* begin
    if (\initial ) begin end
    _0037_ = _0420_;
    (* src = "libresoc.v:45946.5-45946.29" *)
    casez (\initial )
      /* src = "libresoc.v:45946.9-45946.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0420_ = 1'h0;
        end
      default:
          _0420_ = rp_INT_rabc_ldst0_18;
    endcase
  end
  always @* begin
      \dp_INT_rabc_ldst0_18$next  <= _0037_;
  end
  always @* begin
    if (\initial ) begin end
    _0235_ = _0618_;
    (* src = "libresoc.v:45955.5-45955.29" *)
    casez (\initial )
      /* src = "libresoc.v:45955.9-45955.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_INT_rabc_ldst0_18)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0618_ = int_src1__data_o;
        end
      default:
          _0618_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$71  <= _0235_;
  end
  always @* begin
    if (\initial ) begin end
    _0073_ = _0456_;
    (* src = "libresoc.v:45965.5-45965.29" *)
    casez (\initial )
      /* src = "libresoc.v:45965.9-45965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0456_ = 1'h0;
        end
      default:
          _0456_ = rp_XER_xer_so_alu0_0;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_alu0_0$next  <= _0073_;
  end
  always @* begin
    if (\initial ) begin end
    _0249_ = _0632_;
    (* src = "libresoc.v:45974.5-45974.29" *)
    casez (\initial )
      /* src = "libresoc.v:45974.9-45974.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_alu0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0632_ = xer_src1__data_o[0];
        end
      default:
          _0632_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_src3_i$72  <= _0249_;
  end
  always @* begin
    if (\initial ) begin end
    _0077_ = _0460_;
    (* src = "libresoc.v:45984.5-45984.29" *)
    casez (\initial )
      /* src = "libresoc.v:45984.9-45984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0460_ = 1'h0;
        end
      default:
          _0460_ = rp_XER_xer_so_logical0_1;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_logical0_1$next  <= _0077_;
  end
  always @* begin
    if (\initial ) begin end
    _0250_ = _0633_;
    (* src = "libresoc.v:45993.5-45993.29" *)
    casez (\initial )
      /* src = "libresoc.v:45993.9-45993.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_logical0_1)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0633_ = xer_src1__data_o[0];
        end
      default:
          _0633_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_src3_i$73  <= _0250_;
  end
  always @* begin
    if (\initial ) begin end
    _0083_ = _0466_;
    (* src = "libresoc.v:46003.5-46003.29" *)
    casez (\initial )
      /* src = "libresoc.v:46003.9-46003.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0466_ = 1'h0;
        end
      default:
          _0466_ = rp_XER_xer_so_spr0_2;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_spr0_2$next  <= _0083_;
  end
  always @* begin
    if (\initial ) begin end
    _0262_ = _0645_;
    (* src = "libresoc.v:46012.5-46012.29" *)
    casez (\initial )
      /* src = "libresoc.v:46012.9-46012.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_spr0_2)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0645_ = xer_src1__data_o[0];
        end
      default:
          _0645_ = 1'h0;
    endcase
  end
  always @* begin
      fus_src4_i <= _0262_;
  end
  always @* begin
    if (\initial ) begin end
    _0075_ = _0458_;
    (* src = "libresoc.v:46022.5-46022.29" *)
    casez (\initial )
      /* src = "libresoc.v:46022.9-46022.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0458_ = 1'h0;
        end
      default:
          _0458_ = rp_XER_xer_so_div0_3;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_div0_3$next  <= _0075_;
  end
  always @* begin
    if (\initial ) begin end
    _0251_ = _0634_;
    (* src = "libresoc.v:46031.5-46031.29" *)
    casez (\initial )
      /* src = "libresoc.v:46031.9-46031.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_div0_3)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0634_ = xer_src1__data_o[0];
        end
      default:
          _0634_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_src3_i$74  <= _0251_;
  end
  always @* begin
    if (\initial ) begin end
    _0079_ = _0462_;
    (* src = "libresoc.v:46041.5-46041.29" *)
    casez (\initial )
      /* src = "libresoc.v:46041.9-46041.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0462_ = 1'h0;
        end
      default:
          _0462_ = rp_XER_xer_so_mul0_4;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_mul0_4$next  <= _0079_;
  end
  always @* begin
    if (\initial ) begin end
    _0252_ = _0635_;
    (* src = "libresoc.v:46050.5-46050.29" *)
    casez (\initial )
      /* src = "libresoc.v:46050.9-46050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_mul0_4)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0635_ = xer_src1__data_o[0];
        end
      default:
          _0635_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_src3_i$75  <= _0252_;
  end
  always @* begin
    if (\initial ) begin end
    _0081_ = _0464_;
    (* src = "libresoc.v:46060.5-46060.29" *)
    casez (\initial )
      /* src = "libresoc.v:46060.9-46060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0464_ = 1'h0;
        end
      default:
          _0464_ = rp_XER_xer_so_shiftrot0_5;
    endcase
  end
  always @* begin
      \dp_XER_xer_so_shiftrot0_5$next  <= _0081_;
  end
  always @* begin
    if (\initial ) begin end
    _0258_ = _0641_;
    (* src = "libresoc.v:46069.5-46069.29" *)
    casez (\initial )
      /* src = "libresoc.v:46069.9-46069.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_so_shiftrot0_5)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0641_ = xer_src1__data_o[0];
        end
      default:
          _0641_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_src4_i$76  <= _0258_;
  end
  always @* begin
    if (\initial ) begin end
    _0065_ = _0448_;
    (* src = "libresoc.v:46079.5-46079.29" *)
    casez (\initial )
      /* src = "libresoc.v:46079.9-46079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0448_ = 1'h0;
        end
      default:
          _0448_ = rp_XER_xer_ca_alu0_0;
    endcase
  end
  always @* begin
      \dp_XER_xer_ca_alu0_0$next  <= _0065_;
  end
  always @* begin
    if (\initial ) begin end
    _0259_ = _0642_;
    (* src = "libresoc.v:46088.5-46088.29" *)
    casez (\initial )
      /* src = "libresoc.v:46088.9-46088.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_ca_alu0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0642_ = xer_src2__data_o;
        end
      default:
          _0642_ = 2'h0;
    endcase
  end
  always @* begin
      \fus_src4_i$77  <= _0259_;
  end
  always @* begin
    if (\initial ) begin end
    _0069_ = _0452_;
    (* src = "libresoc.v:46098.5-46098.29" *)
    casez (\initial )
      /* src = "libresoc.v:46098.9-46098.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0452_ = 1'h0;
        end
      default:
          _0452_ = rp_XER_xer_ca_spr0_1;
    endcase
  end
  always @* begin
      \dp_XER_xer_ca_spr0_1$next  <= _0069_;
  end
  always @* begin
    if (\initial ) begin end
    _0267_ = _0650_;
    (* src = "libresoc.v:46107.5-46107.29" *)
    casez (\initial )
      /* src = "libresoc.v:46107.9-46107.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_ca_spr0_1)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0650_ = xer_src2__data_o;
        end
      default:
          _0650_ = 2'h0;
    endcase
  end
  always @* begin
      fus_src6_i <= _0267_;
  end
  always @* begin
    if (\initial ) begin end
    _0067_ = _0450_;
    (* src = "libresoc.v:46117.5-46117.29" *)
    casez (\initial )
      /* src = "libresoc.v:46117.9-46117.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0450_ = 1'h0;
        end
      default:
          _0450_ = rp_XER_xer_ca_shiftrot0_2;
    endcase
  end
  always @* begin
      \dp_XER_xer_ca_shiftrot0_2$next  <= _0067_;
  end
  always @* begin
    if (\initial ) begin end
    _0265_ = _0648_;
    (* src = "libresoc.v:46126.5-46126.29" *)
    casez (\initial )
      /* src = "libresoc.v:46126.9-46126.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_ca_shiftrot0_2)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0648_ = xer_src2__data_o;
        end
      default:
          _0648_ = 2'h0;
    endcase
  end
  always @* begin
      fus_src5_i <= _0265_;
  end
  always @* begin
    if (\initial ) begin end
    _0071_ = _0454_;
    (* src = "libresoc.v:46136.5-46136.29" *)
    casez (\initial )
      /* src = "libresoc.v:46136.9-46136.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0454_ = 1'h0;
        end
      default:
          _0454_ = rp_XER_xer_ov_spr0_0;
    endcase
  end
  always @* begin
      \dp_XER_xer_ov_spr0_0$next  <= _0071_;
  end
  always @* begin
    if (\initial ) begin end
    _0263_ = _0646_;
    (* src = "libresoc.v:46145.5-46145.29" *)
    casez (\initial )
      /* src = "libresoc.v:46145.9-46145.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_XER_xer_ov_spr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0646_ = xer_src3__data_o;
        end
      default:
          _0646_ = 2'h0;
    endcase
  end
  always @* begin
      \fus_src5_i$78  <= _0263_;
  end
  always @* begin
    if (\initial ) begin end
    _0013_ = _0396_;
    (* src = "libresoc.v:46155.5-46155.29" *)
    casez (\initial )
      /* src = "libresoc.v:46155.9-46155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0396_ = 1'h0;
        end
      default:
          _0396_ = rp_CR_full_cr_cr0_0;
    endcase
  end
  always @* begin
      \dp_CR_full_cr_cr0_0$next  <= _0013_;
  end
  always @* begin
    if (\initial ) begin end
    _0253_ = _0636_;
    (* src = "libresoc.v:46164.5-46164.29" *)
    casez (\initial )
      /* src = "libresoc.v:46164.9-46164.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_CR_full_cr_cr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0636_ = cr_full_rd__data_o;
        end
      default:
          _0636_ = 32'd0;
    endcase
  end
  always @* begin
      \fus_src3_i$79  <= _0253_;
  end
  always @* begin
    if (\initial ) begin end
    _0007_ = _0390_;
    (* src = "libresoc.v:46174.5-46174.29" *)
    casez (\initial )
      /* src = "libresoc.v:46174.9-46174.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0390_ = 1'h0;
        end
      default:
          _0390_ = rp_CR_cr_a_cr0_0;
    endcase
  end
  always @* begin
      \dp_CR_cr_a_cr0_0$next  <= _0007_;
  end
  always @* begin
    if (\initial ) begin end
    _0260_ = _0643_;
    (* src = "libresoc.v:46183.5-46183.29" *)
    casez (\initial )
      /* src = "libresoc.v:46183.9-46183.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_CR_cr_a_cr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0643_ = cr_src1__data_o;
        end
      default:
          _0643_ = 4'h0;
    endcase
  end
  always @* begin
      \fus_src4_i$80  <= _0260_;
  end
  always @* begin
    if (\initial ) begin end
    _0005_ = _0388_;
    (* src = "libresoc.v:46193.5-46193.29" *)
    casez (\initial )
      /* src = "libresoc.v:46193.9-46193.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0388_ = 1'h0;
        end
      default:
          _0388_ = rp_CR_cr_a_branch0_1;
    endcase
  end
  always @* begin
      \dp_CR_cr_a_branch0_1$next  <= _0005_;
  end
  always @* begin
    if (\initial ) begin end
    _0254_ = _0637_;
    (* src = "libresoc.v:46202.5-46202.29" *)
    casez (\initial )
      /* src = "libresoc.v:46202.9-46202.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_CR_cr_a_branch0_1)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0637_ = cr_src1__data_o;
        end
      default:
          _0637_ = 4'h0;
    endcase
  end
  always @* begin
      \fus_src3_i$83  <= _0254_;
  end
  always @* begin
    if (\initial ) begin end
    _0009_ = _0392_;
    (* src = "libresoc.v:46212.5-46212.29" *)
    casez (\initial )
      /* src = "libresoc.v:46212.9-46212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0392_ = 1'h0;
        end
      default:
          _0392_ = rp_CR_cr_b_cr0_0;
    endcase
  end
  always @* begin
      \dp_CR_cr_b_cr0_0$next  <= _0009_;
  end
  always @* begin
    if (\initial ) begin end
    _0003_ = _0982_;
    (* src = "libresoc.v:46221.5-46221.29" *)
    casez (\initial )
      /* src = "libresoc.v:46221.9-46221.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
    casez (\$221 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0386_ = \$223 [1:0];
        end
      default:
          _0386_ = counter;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0691_ = _0837_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0837_ = _0386_;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0837_ = 2'h2;
              end
            default:
                _0837_ = _0386_;
          endcase
        end
      default:
          _0691_ = _0386_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0982_ = 2'h0;
        end
      default:
          _0982_ = _0691_;
    endcase
  end
  always @* begin
      \counter$next  <= _0003_;
  end
  always @* begin
    if (\initial ) begin end
    _0264_ = _0647_;
    (* src = "libresoc.v:46252.5-46252.29" *)
    casez (\initial )
      /* src = "libresoc.v:46252.9-46252.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_CR_cr_b_cr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0647_ = cr_src2__data_o;
        end
      default:
          _0647_ = 4'h0;
    endcase
  end
  always @* begin
      \fus_src5_i$84  <= _0264_;
  end
  always @* begin
    if (\initial ) begin end
    _0011_ = _0394_;
    (* src = "libresoc.v:46262.5-46262.29" *)
    casez (\initial )
      /* src = "libresoc.v:46262.9-46262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0394_ = 1'h0;
        end
      default:
          _0394_ = rp_CR_cr_c_cr0_0;
    endcase
  end
  always @* begin
      \dp_CR_cr_c_cr0_0$next  <= _0011_;
  end
  always @* begin
    if (\initial ) begin end
    _0266_ = _0649_;
    (* src = "libresoc.v:46271.5-46271.29" *)
    casez (\initial )
      /* src = "libresoc.v:46271.9-46271.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_CR_cr_c_cr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0649_ = cr_src3__data_o;
        end
      default:
          _0649_ = 4'h0;
    endcase
  end
  always @* begin
      \fus_src6_i$85  <= _0266_;
  end
  always @* begin
    if (\initial ) begin end
    _0002_ = _0690_;
    (* src = "libresoc.v:46281.5-46281.29" *)
    casez (\initial )
      /* src = "libresoc.v:46281.9-46281.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" *)
    casez (\$226 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0385_ = 1'h1;
        end
      default:
          _0385_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0690_ = _0836_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0836_ = _0385_;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0836_ = 1'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0836_ = _0382_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0981_ = fus_cu_busy_o;
                    end
                  default:
                      _0981_ = _0385_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0983_ = \fus_cu_busy_o$14 ;
                    end
                  default:
                      _0983_ = _0981_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0984_ = \fus_cu_busy_o$17 ;
                    end
                  default:
                      _0984_ = _0983_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0985_ = \fus_cu_busy_o$20 ;
                    end
                  default:
                      _0985_ = _0984_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0986_ = \fus_cu_busy_o$23 ;
                    end
                  default:
                      _0986_ = _0985_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[5])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0987_ = \fus_cu_busy_o$26 ;
                    end
                  default:
                      _0987_ = _0986_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[6])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0379_ = \fus_cu_busy_o$29 ;
                    end
                  default:
                      _0379_ = _0987_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[7])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0380_ = \fus_cu_busy_o$32 ;
                    end
                  default:
                      _0380_ = _0379_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[8])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0381_ = \fus_cu_busy_o$35 ;
                    end
                  default:
                      _0381_ = _0380_;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[9])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0382_ = \fus_cu_busy_o$38 ;
                    end
                  default:
                      _0382_ = _0381_;
                endcase
              end
          endcase
        end
      default:
          _0690_ = _0385_;
    endcase
  end
  always @* begin
      corebusy_o <= _0002_;
  end
  always @* begin
    if (\initial ) begin end
    _0015_ = _0398_;
    (* src = "libresoc.v:46372.5-46372.29" *)
    casez (\initial )
      /* src = "libresoc.v:46372.9-46372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0398_ = 1'h0;
        end
      default:
          _0398_ = rp_FAST_fast1_branch0_0;
    endcase
  end
  always @* begin
      \dp_FAST_fast1_branch0_0$next  <= _0015_;
  end
  always @* begin
    if (\initial ) begin end
    _0236_ = _0619_;
    (* src = "libresoc.v:46381.5-46381.29" *)
    casez (\initial )
      /* src = "libresoc.v:46381.9-46381.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_FAST_fast1_branch0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0619_ = fast_src1__data_o;
        end
      default:
          _0619_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src1_i$86  <= _0236_;
  end
  always @* begin
    if (\initial ) begin end
    _0000_ = _0835_;
    (* src = "libresoc.v:46391.5-46391.29" *)
    casez (\initial )
      /* src = "libresoc.v:46391.9-46391.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0383_ = _0689_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0689_ = 1'h1;
              end
            default:
                _0689_ = core_terminate_o;
          endcase
        end
      default:
          _0383_ = core_terminate_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0835_ = 1'h0;
        end
      default:
          _0835_ = _0383_;
    endcase
  end
  always @* begin
      \core_terminate_o$next  <= _0000_;
  end
  always @* begin
    if (\initial ) begin end
    _0021_ = _0404_;
    (* src = "libresoc.v:46412.5-46412.29" *)
    casez (\initial )
      /* src = "libresoc.v:46412.9-46412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0404_ = 1'h0;
        end
      default:
          _0404_ = rp_FAST_fast1_trap0_1;
    endcase
  end
  always @* begin
      \dp_FAST_fast1_trap0_1$next  <= _0021_;
  end
  always @* begin
    if (\initial ) begin end
    _0255_ = _0638_;
    (* src = "libresoc.v:46421.5-46421.29" *)
    casez (\initial )
      /* src = "libresoc.v:46421.9-46421.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_FAST_fast1_trap0_1)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0638_ = fast_src1__data_o;
        end
      default:
          _0638_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src3_i$87  <= _0255_;
  end
  always @* begin
    if (\initial ) begin end
    _0019_ = _0402_;
    (* src = "libresoc.v:46431.5-46431.29" *)
    casez (\initial )
      /* src = "libresoc.v:46431.9-46431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0402_ = 1'h0;
        end
      default:
          _0402_ = rp_FAST_fast1_spr0_2;
    endcase
  end
  always @* begin
      \dp_FAST_fast1_spr0_2$next  <= _0019_;
  end
  always @* begin
    if (\initial ) begin end
    _0256_ = _0639_;
    (* src = "libresoc.v:46440.5-46440.29" *)
    casez (\initial )
      /* src = "libresoc.v:46440.9-46440.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_FAST_fast1_spr0_2)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0639_ = fast_src1__data_o;
        end
      default:
          _0639_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src3_i$88  <= _0256_;
  end
  always @* begin
    if (\initial ) begin end
    _0111_ = _0494_;
    (* src = "libresoc.v:46450.5-46450.29" *)
    casez (\initial )
      /* src = "libresoc.v:46450.9-46450.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0494_ = _0718_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0718_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0718_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0718_ = _0864_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0864_ = dec_ALU_ALU__insn_type;
                    end
                  default:
                      _0864_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0494_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__insn_type <= _0111_;
  end
  always @* begin
    if (\initial ) begin end
    _0017_ = _0400_;
    (* src = "libresoc.v:46479.5-46479.29" *)
    casez (\initial )
      /* src = "libresoc.v:46479.9-46479.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0400_ = 1'h0;
        end
      default:
          _0400_ = rp_FAST_fast1_branch0_3;
    endcase
  end
  always @* begin
      \dp_FAST_fast1_branch0_3$next  <= _0017_;
  end
  always @* begin
    if (\initial ) begin end
    _0245_ = _0628_;
    (* src = "libresoc.v:46488.5-46488.29" *)
    casez (\initial )
      /* src = "libresoc.v:46488.9-46488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_FAST_fast1_branch0_3)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0628_ = fast_src1__data_o;
        end
      default:
          _0628_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$89  <= _0245_;
  end
  always @* begin
    if (\initial ) begin end
    _0023_ = _0406_;
    (* src = "libresoc.v:46498.5-46498.29" *)
    casez (\initial )
      /* src = "libresoc.v:46498.9-46498.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0406_ = 1'h0;
        end
      default:
          _0406_ = rp_FAST_fast1_trap0_4;
    endcase
  end
  always @* begin
      \dp_FAST_fast1_trap0_4$next  <= _0023_;
  end
  always @* begin
    if (\initial ) begin end
    _0261_ = _0644_;
    (* src = "libresoc.v:46507.5-46507.29" *)
    casez (\initial )
      /* src = "libresoc.v:46507.9-46507.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_FAST_fast1_trap0_4)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0644_ = fast_src1__data_o;
        end
      default:
          _0644_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src4_i$90  <= _0261_;
  end
  always @* begin
    if (\initial ) begin end
    _0106_ = _0489_;
    (* src = "libresoc.v:46517.5-46517.29" *)
    casez (\initial )
      /* src = "libresoc.v:46517.9-46517.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0489_ = _0713_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0713_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0713_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0713_ = _0859_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0859_ = dec_ALU_ALU__fn_unit;
                    end
                  default:
                      _0859_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0489_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__fn_unit <= _0106_;
  end
  always @* begin
    if (\initial ) begin end
    _0063_ = _0446_;
    (* src = "libresoc.v:46546.5-46546.29" *)
    casez (\initial )
      /* src = "libresoc.v:46546.9-46546.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0446_ = 1'h0;
        end
      default:
          _0446_ = rp_SPR_spr1_spr0_0;
    endcase
  end
  always @* begin
      \dp_SPR_spr1_spr0_0$next  <= _0063_;
  end
  always @* begin
    if (\initial ) begin end
    _0246_ = _0629_;
    (* src = "libresoc.v:46555.5-46555.29" *)
    casez (\initial )
      /* src = "libresoc.v:46555.9-46555.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:310" *)
    casez (dp_SPR_spr1_spr0_0)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0629_ = spr_spr1__data_o;
        end
      default:
          _0629_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fus_src2_i$91  <= _0246_;
  end
  always @* begin
    if (\initial ) begin end
    _0107_ = _0490_;
    _0108_ = _0491_;
    (* src = "libresoc.v:46565.5-46565.29" *)
    casez (\initial )
      /* src = "libresoc.v:46565.9-46565.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0490_ = _0714_;
          _0491_ = _0715_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0714_ = 64'h0000000000000000;
                _0715_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0714_ = 64'h0000000000000000;
                _0715_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0714_ = _0860_;
                _0715_ = _0861_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0861_, _0860_ } = { dec_ALU_ALU__imm_data__ok, dec_ALU_ALU__imm_data__data };
                    end
                  default:
                    begin
                      _0860_ = 64'h0000000000000000;
                      _0861_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0490_ = 64'h0000000000000000;
          _0491_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__imm_data__data <= _0107_;
      fus_oper_i_alu_alu0__imm_data__ok <= _0108_;
  end
  always @* begin
    if (\initial ) begin end
    _0377_ = _0687_;
    (* src = "libresoc.v:46595.5-46595.29" *)
    casez (\initial )
      /* src = "libresoc.v:46595.9-46595.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0687_ = 1'h0;
        end
      default:
          _0687_ = wr_pick;
    endcase
  end
  always @* begin
      \wr_pick_dly$next  <= _0377_;
  end
  always @* begin
    if (\initial ) begin end
    _0374_ = _0686_;
    (* src = "libresoc.v:46604.5-46604.29" *)
    casez (\initial )
      /* src = "libresoc.v:46604.9-46604.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0686_ = 1'h0;
        end
      default:
          _0686_ = \wr_pick$986 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$989$next  <= _0374_;
  end
  always @* begin
    if (\initial ) begin end
    _0269_ = _0651_;
    (* src = "libresoc.v:46613.5-46613.29" *)
    casez (\initial )
      /* src = "libresoc.v:46613.9-46613.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0651_ = 1'h0;
        end
      default:
          _0651_ = \wr_pick$1005 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1008$next  <= _0269_;
  end
  always @* begin
    if (\initial ) begin end
    _0119_ = _0502_;
    _0120_ = _0503_;
    (* src = "libresoc.v:46622.5-46622.29" *)
    casez (\initial )
      /* src = "libresoc.v:46622.9-46622.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0502_ = _0726_;
          _0503_ = _0727_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0726_ = 1'h0;
                _0727_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0726_ = 1'h0;
                _0727_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0726_ = _0872_;
                _0727_ = _0873_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0872_, _0873_ } = { dec_ALU_ALU__rc__ok, dec_ALU_ALU__rc__rc };
                    end
                  default:
                    begin
                      _0872_ = 1'h0;
                      _0873_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0502_ = 1'h0;
          _0503_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__rc__ok <= _0119_;
      fus_oper_i_alu_alu0__rc__rc <= _0120_;
  end
  always @* begin
    if (\initial ) begin end
    _0272_ = _0652_;
    (* src = "libresoc.v:46652.5-46652.29" *)
    casez (\initial )
      /* src = "libresoc.v:46652.9-46652.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0652_ = 1'h0;
        end
      default:
          _0652_ = \wr_pick$1026 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1029$next  <= _0272_;
  end
  always @* begin
    if (\initial ) begin end
    _0275_ = _0653_;
    (* src = "libresoc.v:46661.5-46661.29" *)
    casez (\initial )
      /* src = "libresoc.v:46661.9-46661.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0653_ = 1'h0;
        end
      default:
          _0653_ = \wr_pick$1044 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1047$next  <= _0275_;
  end
  always @* begin
    if (\initial ) begin end
    _0278_ = _0654_;
    (* src = "libresoc.v:46670.5-46670.29" *)
    casez (\initial )
      /* src = "libresoc.v:46670.9-46670.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0654_ = 1'h0;
        end
      default:
          _0654_ = \wr_pick$1066 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1069$next  <= _0278_;
  end
  always @* begin
    if (\initial ) begin end
    _0116_ = _0499_;
    _0117_ = _0500_;
    (* src = "libresoc.v:46679.5-46679.29" *)
    casez (\initial )
      /* src = "libresoc.v:46679.9-46679.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0499_ = _0723_;
          _0500_ = _0724_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0723_ = 1'h0;
                _0724_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0723_ = 1'h0;
                _0724_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0723_ = _0869_;
                _0724_ = _0870_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0870_, _0869_ } = { dec_ALU_ALU__oe__ok, dec_ALU_ALU__oe__oe };
                    end
                  default:
                    begin
                      _0869_ = 1'h0;
                      _0870_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0499_ = 1'h0;
          _0500_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__oe__oe <= _0116_;
      fus_oper_i_alu_alu0__oe__ok <= _0117_;
  end
  always @* begin
    if (\initial ) begin end
    _0281_ = _0655_;
    (* src = "libresoc.v:46709.5-46709.29" *)
    casez (\initial )
      /* src = "libresoc.v:46709.9-46709.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0655_ = 1'h0;
        end
      default:
          _0655_ = \wr_pick$1086 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1089$next  <= _0281_;
  end
  always @* begin
    if (\initial ) begin end
    _0284_ = _0656_;
    (* src = "libresoc.v:46718.5-46718.29" *)
    casez (\initial )
      /* src = "libresoc.v:46718.9-46718.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0656_ = 1'h0;
        end
      default:
          _0656_ = \wr_pick$1106 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1109$next  <= _0284_;
  end
  always @* begin
    if (\initial ) begin end
    _0287_ = _0657_;
    (* src = "libresoc.v:46727.5-46727.29" *)
    casez (\initial )
      /* src = "libresoc.v:46727.9-46727.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0657_ = 1'h0;
        end
      default:
          _0657_ = \wr_pick$1125 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1128$next  <= _0287_;
  end
  always @* begin
    if (\initial ) begin end
    _0112_ = _0495_;
    (* src = "libresoc.v:46736.5-46736.29" *)
    casez (\initial )
      /* src = "libresoc.v:46736.9-46736.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0495_ = _0719_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0719_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0719_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0719_ = _0865_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0865_ = dec_ALU_ALU__invert_in;
                    end
                  default:
                      _0865_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0495_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__invert_in <= _0112_;
  end
  always @* begin
    if (\initial ) begin end
    _0290_ = _0658_;
    (* src = "libresoc.v:46765.5-46765.29" *)
    casez (\initial )
      /* src = "libresoc.v:46765.9-46765.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0658_ = 1'h0;
        end
      default:
          _0658_ = \wr_pick$1143 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1146$next  <= _0290_;
  end
  always @* begin
    if (\initial ) begin end
    _0122_ = _0505_;
    (* src = "libresoc.v:46774.5-46774.29" *)
    casez (\initial )
      /* src = "libresoc.v:46774.9-46774.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0505_ = _0729_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0729_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0729_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0729_ = _0875_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0875_ = dec_ALU_ALU__zero_a;
                    end
                  default:
                      _0875_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0505_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__zero_a <= _0122_;
  end
  always @* begin
    if (\initial ) begin end
    _0293_ = _0659_;
    (* src = "libresoc.v:46803.5-46803.29" *)
    casez (\initial )
      /* src = "libresoc.v:46803.9-46803.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0659_ = 1'h0;
        end
      default:
          _0659_ = \wr_pick$1217 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1220$next  <= _0293_;
  end
  always @* begin
    if (\initial ) begin end
    _0113_ = _0496_;
    (* src = "libresoc.v:46812.5-46812.29" *)
    casez (\initial )
      /* src = "libresoc.v:46812.9-46812.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0496_ = _0720_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0720_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0720_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0720_ = _0866_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0866_ = dec_ALU_ALU__invert_out;
                    end
                  default:
                      _0866_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0496_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__invert_out <= _0113_;
  end
  always @* begin
    if (\initial ) begin end
    _0296_ = _0660_;
    (* src = "libresoc.v:46841.5-46841.29" *)
    casez (\initial )
      /* src = "libresoc.v:46841.9-46841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0660_ = 1'h0;
        end
      default:
          _0660_ = \wr_pick$1245 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1248$next  <= _0296_;
  end
  always @* begin
    if (\initial ) begin end
    _0121_ = _0504_;
    (* src = "libresoc.v:46850.5-46850.29" *)
    casez (\initial )
      /* src = "libresoc.v:46850.9-46850.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0504_ = _0728_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0728_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0728_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0728_ = _0874_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0874_ = dec_ALU_ALU__write_cr0;
                    end
                  default:
                      _0874_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0504_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__write_cr0 <= _0121_;
  end
  always @* begin
    if (\initial ) begin end
    _0299_ = _0661_;
    (* src = "libresoc.v:46879.5-46879.29" *)
    casez (\initial )
      /* src = "libresoc.v:46879.9-46879.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0661_ = 1'h0;
        end
      default:
          _0661_ = \wr_pick$1265 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1268$next  <= _0299_;
  end
  always @* begin
    if (\initial ) begin end
    _0302_ = _0662_;
    (* src = "libresoc.v:46888.5-46888.29" *)
    casez (\initial )
      /* src = "libresoc.v:46888.9-46888.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0662_ = 1'h0;
        end
      default:
          _0662_ = \wr_pick$1285 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1288$next  <= _0302_;
  end
  always @* begin
    if (\initial ) begin end
    _0109_ = _0492_;
    (* src = "libresoc.v:46897.5-46897.29" *)
    casez (\initial )
      /* src = "libresoc.v:46897.9-46897.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0492_ = _0716_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0716_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0716_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0716_ = _0862_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0862_ = dec_ALU_ALU__input_carry;
                    end
                  default:
                      _0862_ = 2'h0;
                endcase
              end
          endcase
        end
      default:
          _0492_ = 2'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__input_carry <= _0109_;
  end
  always @* begin
    if (\initial ) begin end
    _0305_ = _0663_;
    (* src = "libresoc.v:46926.5-46926.29" *)
    casez (\initial )
      /* src = "libresoc.v:46926.9-46926.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0663_ = 1'h0;
        end
      default:
          _0663_ = \wr_pick$1305 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1308$next  <= _0305_;
  end
  always @* begin
    if (\initial ) begin end
    _0308_ = _0664_;
    (* src = "libresoc.v:46935.5-46935.29" *)
    casez (\initial )
      /* src = "libresoc.v:46935.9-46935.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0664_ = 1'h0;
        end
      default:
          _0664_ = \wr_pick$1325 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1328$next  <= _0308_;
  end
  always @* begin
    if (\initial ) begin end
    _0118_ = _0501_;
    (* src = "libresoc.v:46944.5-46944.29" *)
    casez (\initial )
      /* src = "libresoc.v:46944.9-46944.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0501_ = _0725_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0725_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0725_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0725_ = _0871_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0871_ = dec_ALU_ALU__output_carry;
                    end
                  default:
                      _0871_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0501_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__output_carry <= _0118_;
  end
  always @* begin
    if (\initial ) begin end
    _0311_ = _0665_;
    (* src = "libresoc.v:46973.5-46973.29" *)
    casez (\initial )
      /* src = "libresoc.v:46973.9-46973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0665_ = 1'h0;
        end
      default:
          _0665_ = \wr_pick$1345 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1348$next  <= _0311_;
  end
  always @* begin
    if (\initial ) begin end
    _0114_ = _0497_;
    (* src = "libresoc.v:46982.5-46982.29" *)
    casez (\initial )
      /* src = "libresoc.v:46982.9-46982.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0497_ = _0721_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0721_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0721_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0721_ = _0867_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0867_ = dec_ALU_ALU__is_32bit;
                    end
                  default:
                      _0867_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0497_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__is_32bit <= _0114_;
  end
  always @* begin
    if (\initial ) begin end
    _0314_ = _0666_;
    (* src = "libresoc.v:47011.5-47011.29" *)
    casez (\initial )
      /* src = "libresoc.v:47011.9-47011.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0666_ = 1'h0;
        end
      default:
          _0666_ = \wr_pick$1392 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1395$next  <= _0314_;
  end
  always @* begin
    if (\initial ) begin end
    _0115_ = _0498_;
    (* src = "libresoc.v:47020.5-47020.29" *)
    casez (\initial )
      /* src = "libresoc.v:47020.9-47020.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0498_ = _0722_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0722_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0722_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0722_ = _0868_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0868_ = dec_ALU_ALU__is_signed;
                    end
                  default:
                      _0868_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0498_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__is_signed <= _0115_;
  end
  always @* begin
    if (\initial ) begin end
    _0317_ = _0667_;
    (* src = "libresoc.v:47049.5-47049.29" *)
    casez (\initial )
      /* src = "libresoc.v:47049.9-47049.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0667_ = 1'h0;
        end
      default:
          _0667_ = \wr_pick$1408 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1411$next  <= _0317_;
  end
  always @* begin
    if (\initial ) begin end
    _0320_ = _0668_;
    (* src = "libresoc.v:47058.5-47058.29" *)
    casez (\initial )
      /* src = "libresoc.v:47058.9-47058.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0668_ = 1'h0;
        end
      default:
          _0668_ = \wr_pick$1424 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1427$next  <= _0320_;
  end
  always @* begin
    if (\initial ) begin end
    _0105_ = _0488_;
    (* src = "libresoc.v:47067.5-47067.29" *)
    casez (\initial )
      /* src = "libresoc.v:47067.9-47067.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0488_ = _0712_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0712_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0712_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0712_ = _0858_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0858_ = dec_ALU_ALU__data_len;
                    end
                  default:
                      _0858_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0488_ = 4'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__data_len <= _0105_;
  end
  always @* begin
    if (\initial ) begin end
    _0323_ = _0669_;
    (* src = "libresoc.v:47096.5-47096.29" *)
    casez (\initial )
      /* src = "libresoc.v:47096.9-47096.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0669_ = 1'h0;
        end
      default:
          _0669_ = \wr_pick$1458 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1461$next  <= _0323_;
  end
  always @* begin
    if (\initial ) begin end
    _0110_ = _0493_;
    (* src = "libresoc.v:47105.5-47105.29" *)
    casez (\initial )
      /* src = "libresoc.v:47105.9-47105.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0493_ = _0717_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0717_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0717_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0717_ = _0863_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0863_ = dec_ALU_ALU__insn;
                    end
                  default:
                      _0863_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0493_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_alu0__insn <= _0110_;
  end
  always @* begin
    if (\initial ) begin end
    _0326_ = _0670_;
    (* src = "libresoc.v:47134.5-47134.29" *)
    casez (\initial )
      /* src = "libresoc.v:47134.9-47134.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0670_ = 1'h0;
        end
      default:
          _0670_ = \wr_pick$1474 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1477$next  <= _0326_;
  end
  always @* begin
    if (\initial ) begin end
    _0329_ = _0671_;
    (* src = "libresoc.v:47143.5-47143.29" *)
    casez (\initial )
      /* src = "libresoc.v:47143.9-47143.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0671_ = 1'h0;
        end
      default:
          _0671_ = \wr_pick$1490 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1493$next  <= _0329_;
  end
  always @* begin
    if (\initial ) begin end
    _0094_ = _0477_;
    (* src = "libresoc.v:47152.5-47152.29" *)
    casez (\initial )
      /* src = "libresoc.v:47152.9-47152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0477_ = _0701_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0701_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0701_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0701_ = _0847_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0847_ = issue_i;
                    end
                  default:
                      _0847_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0477_ = 1'h0;
    endcase
  end
  always @* begin
      fus_cu_issue_i <= _0094_;
  end
  always @* begin
    if (\initial ) begin end
    _0332_ = _0672_;
    (* src = "libresoc.v:47181.5-47181.29" *)
    casez (\initial )
      /* src = "libresoc.v:47181.9-47181.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0672_ = 1'h0;
        end
      default:
          _0672_ = \wr_pick$1506 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1509$next  <= _0332_;
  end
  always @* begin
    if (\initial ) begin end
    _0104_ = _0487_;
    (* src = "libresoc.v:47190.5-47190.29" *)
    casez (\initial )
      /* src = "libresoc.v:47190.9-47190.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0487_ = _0711_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0711_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0711_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0711_ = _0857_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[0])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0857_ = \$228 ;
                    end
                  default:
                      _0857_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0487_ = 4'h0;
    endcase
  end
  always @* begin
      fus_cu_rdmaskn_i <= _0104_;
  end
  always @* begin
    if (\initial ) begin end
    _0335_ = _0673_;
    (* src = "libresoc.v:47219.5-47219.29" *)
    casez (\initial )
      /* src = "libresoc.v:47219.9-47219.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0673_ = 1'h0;
        end
      default:
          _0673_ = \wr_pick$1542 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1545$next  <= _0335_;
  end
  always @* begin
    if (\initial ) begin end
    _0338_ = _0674_;
    (* src = "libresoc.v:47228.5-47228.29" *)
    casez (\initial )
      /* src = "libresoc.v:47228.9-47228.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0674_ = 1'h0;
        end
      default:
          _0674_ = \wr_pick$1558 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1561$next  <= _0338_;
  end
  always @* begin
    if (\initial ) begin end
    _0133_ = _0516_;
    (* src = "libresoc.v:47237.5-47237.29" *)
    casez (\initial )
      /* src = "libresoc.v:47237.9-47237.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0516_ = _0740_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0740_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0740_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0740_ = _0886_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0886_ = dec_CR_CR__insn_type;
                    end
                  default:
                      _0886_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0516_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_cr0__insn_type <= _0133_;
  end
  always @* begin
    if (\initial ) begin end
    _0341_ = _0675_;
    (* src = "libresoc.v:47266.5-47266.29" *)
    casez (\initial )
      /* src = "libresoc.v:47266.9-47266.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0675_ = 1'h0;
        end
      default:
          _0675_ = \wr_pick$1574 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1577$next  <= _0341_;
  end
  always @* begin
    if (\initial ) begin end
    _0131_ = _0514_;
    (* src = "libresoc.v:47275.5-47275.29" *)
    casez (\initial )
      /* src = "libresoc.v:47275.9-47275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0514_ = _0738_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0738_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0738_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0738_ = _0884_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0884_ = dec_CR_CR__fn_unit;
                    end
                  default:
                      _0884_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0514_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_cr0__fn_unit <= _0131_;
  end
  always @* begin
    if (\initial ) begin end
    _0344_ = _0676_;
    (* src = "libresoc.v:47304.5-47304.29" *)
    casez (\initial )
      /* src = "libresoc.v:47304.9-47304.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0676_ = 1'h0;
        end
      default:
          _0676_ = \wr_pick$1590 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1593$next  <= _0344_;
  end
  always @* begin
    if (\initial ) begin end
    _0347_ = _0677_;
    (* src = "libresoc.v:47313.5-47313.29" *)
    casez (\initial )
      /* src = "libresoc.v:47313.9-47313.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0677_ = 1'h0;
        end
      default:
          _0677_ = \wr_pick$1632 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1635$next  <= _0347_;
  end
  always @* begin
    if (\initial ) begin end
    _0132_ = _0515_;
    (* src = "libresoc.v:47322.5-47322.29" *)
    casez (\initial )
      /* src = "libresoc.v:47322.9-47322.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0515_ = _0739_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0739_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0739_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0739_ = _0885_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0885_ = dec_CR_CR__insn;
                    end
                  default:
                      _0885_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0515_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_cr0__insn <= _0132_;
  end
  always @* begin
    if (\initial ) begin end
    _0350_ = _0678_;
    (* src = "libresoc.v:47351.5-47351.29" *)
    casez (\initial )
      /* src = "libresoc.v:47351.9-47351.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0678_ = 1'h0;
        end
      default:
          _0678_ = \wr_pick$1651 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1654$next  <= _0350_;
  end
  always @* begin
    if (\initial ) begin end
    _0085_ = _0468_;
    (* src = "libresoc.v:47360.5-47360.29" *)
    casez (\initial )
      /* src = "libresoc.v:47360.9-47360.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0468_ = _0692_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0692_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0692_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0692_ = _0838_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0838_ = issue_i;
                    end
                  default:
                      _0838_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0468_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$13  <= _0085_;
  end
  always @* begin
    if (\initial ) begin end
    _0353_ = _0679_;
    (* src = "libresoc.v:47389.5-47389.29" *)
    casez (\initial )
      /* src = "libresoc.v:47389.9-47389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0679_ = 1'h0;
        end
      default:
          _0679_ = \wr_pick$1667 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1670$next  <= _0353_;
  end
  always @* begin
    if (\initial ) begin end
    _0356_ = _0680_;
    (* src = "libresoc.v:47398.5-47398.29" *)
    casez (\initial )
      /* src = "libresoc.v:47398.9-47398.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0680_ = 1'h0;
        end
      default:
          _0680_ = \wr_pick$1683 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1686$next  <= _0356_;
  end
  always @* begin
    if (\initial ) begin end
    _0095_ = _0478_;
    (* src = "libresoc.v:47407.5-47407.29" *)
    casez (\initial )
      /* src = "libresoc.v:47407.9-47407.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0478_ = _0702_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0702_ = 6'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0702_ = 6'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0702_ = _0848_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0848_ = \$250 ;
                    end
                  default:
                      _0848_ = 6'h00;
                endcase
              end
          endcase
        end
      default:
          _0478_ = 6'h00;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$15  <= _0095_;
  end
  always @* begin
    if (\initial ) begin end
    _0359_ = _0681_;
    (* src = "libresoc.v:47436.5-47436.29" *)
    casez (\initial )
      /* src = "libresoc.v:47436.9-47436.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0681_ = 1'h0;
        end
      default:
          _0681_ = \wr_pick$1699 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1702$next  <= _0359_;
  end
  always @* begin
    if (\initial ) begin end
    _0123_ = _0506_;
    (* src = "libresoc.v:47445.5-47445.29" *)
    casez (\initial )
      /* src = "libresoc.v:47445.9-47445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0506_ = _0730_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0730_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0730_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0730_ = _0876_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0876_ = dec_BRANCH_BRANCH__cia;
                    end
                  default:
                      _0876_ = 64'h0000000000000000;
                endcase
              end
          endcase
        end
      default:
          _0506_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__cia <= _0123_;
  end
  always @* begin
    if (\initial ) begin end
    _0362_ = _0682_;
    (* src = "libresoc.v:47474.5-47474.29" *)
    casez (\initial )
      /* src = "libresoc.v:47474.9-47474.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0682_ = 1'h0;
        end
      default:
          _0682_ = \wr_pick$1743 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1746$next  <= _0362_;
  end
  always @* begin
    if (\initial ) begin end
    _0128_ = _0511_;
    (* src = "libresoc.v:47483.5-47483.29" *)
    casez (\initial )
      /* src = "libresoc.v:47483.9-47483.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0511_ = _0735_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0735_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0735_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0735_ = _0881_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0881_ = dec_BRANCH_BRANCH__insn_type;
                    end
                  default:
                      _0881_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0511_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__insn_type <= _0128_;
  end
  always @* begin
    if (\initial ) begin end
    _0365_ = _0683_;
    (* src = "libresoc.v:47512.5-47512.29" *)
    casez (\initial )
      /* src = "libresoc.v:47512.9-47512.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0683_ = 1'h0;
        end
      default:
          _0683_ = \wr_pick$1759 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1762$next  <= _0365_;
  end
  always @* begin
    if (\initial ) begin end
    _0368_ = _0684_;
    (* src = "libresoc.v:47521.5-47521.29" *)
    casez (\initial )
      /* src = "libresoc.v:47521.9-47521.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0684_ = 1'h0;
        end
      default:
          _0684_ = \wr_pick$1783 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1786$next  <= _0368_;
  end
  always @* begin
    if (\initial ) begin end
    _0124_ = _0507_;
    (* src = "libresoc.v:47530.5-47530.29" *)
    casez (\initial )
      /* src = "libresoc.v:47530.9-47530.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0507_ = _0731_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0731_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0731_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0731_ = _0877_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0877_ = dec_BRANCH_BRANCH__fn_unit;
                    end
                  default:
                      _0877_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0507_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__fn_unit <= _0124_;
  end
  always @* begin
    if (\initial ) begin end
    _0371_ = _0685_;
    (* src = "libresoc.v:47559.5-47559.29" *)
    casez (\initial )
      /* src = "libresoc.v:47559.9-47559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0685_ = 1'h0;
        end
      default:
          _0685_ = \wr_pick$1803 ;
    endcase
  end
  always @* begin
      \wr_pick_dly$1806$next  <= _0371_;
  end
  always @* begin
    if (\initial ) begin end
    _0127_ = _0510_;
    (* src = "libresoc.v:47568.5-47568.29" *)
    casez (\initial )
      /* src = "libresoc.v:47568.9-47568.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0510_ = _0734_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0734_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0734_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0734_ = _0880_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0880_ = dec_BRANCH_BRANCH__insn;
                    end
                  default:
                      _0880_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0510_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__insn <= _0127_;
  end
  always @* begin
    if (\initial ) begin end
    _0125_ = _0508_;
    _0126_ = _0509_;
    (* src = "libresoc.v:47597.5-47597.29" *)
    casez (\initial )
      /* src = "libresoc.v:47597.9-47597.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0508_ = _0732_;
          _0509_ = _0733_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0732_ = 64'h0000000000000000;
                _0733_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0732_ = 64'h0000000000000000;
                _0733_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0732_ = _0878_;
                _0733_ = _0879_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0879_, _0878_ } = { dec_BRANCH_BRANCH__imm_data__ok, dec_BRANCH_BRANCH__imm_data__data };
                    end
                  default:
                    begin
                      _0878_ = 64'h0000000000000000;
                      _0879_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0508_ = 64'h0000000000000000;
          _0509_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__imm_data__data <= _0125_;
      fus_oper_i_alu_branch0__imm_data__ok <= _0126_;
  end
  always @* begin
    if (\initial ) begin end
    _0130_ = _0513_;
    (* src = "libresoc.v:47627.5-47627.29" *)
    casez (\initial )
      /* src = "libresoc.v:47627.9-47627.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0513_ = _0737_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0737_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0737_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0737_ = _0883_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0883_ = dec_BRANCH_BRANCH__lk;
                    end
                  default:
                      _0883_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0513_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__lk <= _0130_;
  end
  always @* begin
    if (\initial ) begin end
    _0129_ = _0512_;
    (* src = "libresoc.v:47656.5-47656.29" *)
    casez (\initial )
      /* src = "libresoc.v:47656.9-47656.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0512_ = _0736_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0736_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0736_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0736_ = _0882_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0882_ = dec_BRANCH_BRANCH__is_32bit;
                    end
                  default:
                      _0882_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0512_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_branch0__is_32bit <= _0129_;
  end
  always @* begin
    if (\initial ) begin end
    _0086_ = _0469_;
    (* src = "libresoc.v:47685.5-47685.29" *)
    casez (\initial )
      /* src = "libresoc.v:47685.9-47685.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0469_ = _0693_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0693_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0693_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0693_ = _0839_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0839_ = issue_i;
                    end
                  default:
                      _0839_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0469_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$16  <= _0086_;
  end
  always @* begin
    if (\initial ) begin end
    _0096_ = _0479_;
    (* src = "libresoc.v:47714.5-47714.29" *)
    casez (\initial )
      /* src = "libresoc.v:47714.9-47714.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0479_ = _0703_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0703_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0703_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0703_ = _0849_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[2])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0849_ = \$252 ;
                    end
                  default:
                      _0849_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _0479_ = 3'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$18  <= _0096_;
  end
  always @* begin
    if (\initial ) begin end
    _0206_ = _0589_;
    (* src = "libresoc.v:47743.5-47743.29" *)
    casez (\initial )
      /* src = "libresoc.v:47743.9-47743.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0589_ = _0813_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0813_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0813_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0813_ = _0959_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0959_ = core_core_insn_type;
                    end
                  default:
                      _0959_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0589_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__insn_type <= _0206_;
  end
  always @* begin
    if (\initial ) begin end
    _0204_ = _0587_;
    (* src = "libresoc.v:47772.5-47772.29" *)
    casez (\initial )
      /* src = "libresoc.v:47772.9-47772.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0587_ = _0811_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0811_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0811_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0811_ = _0957_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0957_ = core_core_fn_unit;
                    end
                  default:
                      _0957_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0587_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__fn_unit <= _0204_;
  end
  always @* begin
    if (\initial ) begin end
    _0205_ = _0588_;
    (* src = "libresoc.v:47801.5-47801.29" *)
    casez (\initial )
      /* src = "libresoc.v:47801.9-47801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0588_ = _0812_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0812_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0812_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0812_ = _0958_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0958_ = core_core_insn;
                    end
                  default:
                      _0958_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _0588_ = 32'd0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__insn <= _0205_;
  end
  always @* begin
    if (\initial ) begin end
    _0209_ = _0592_;
    (* src = "libresoc.v:47830.5-47830.29" *)
    casez (\initial )
      /* src = "libresoc.v:47830.9-47830.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0592_ = _0816_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0816_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0816_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0816_ = _0962_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0962_ = core_core_msr;
                    end
                  default:
                      _0962_ = 64'h0000000000000000;
                endcase
              end
          endcase
        end
      default:
          _0592_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__msr <= _0209_;
  end
  always @* begin
    if (\initial ) begin end
    _0203_ = _0586_;
    (* src = "libresoc.v:47859.5-47859.29" *)
    casez (\initial )
      /* src = "libresoc.v:47859.9-47859.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0586_ = _0810_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0810_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0810_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0810_ = _0956_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0956_ = core_core_cia;
                    end
                  default:
                      _0956_ = 64'h0000000000000000;
                endcase
              end
          endcase
        end
      default:
          _0586_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__cia <= _0203_;
  end
  always @* begin
    if (\initial ) begin end
    _0207_ = _0590_;
    (* src = "libresoc.v:47888.5-47888.29" *)
    casez (\initial )
      /* src = "libresoc.v:47888.9-47888.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0590_ = _0814_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0814_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0814_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0814_ = _0960_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0960_ = core_core_is_32bit;
                    end
                  default:
                      _0960_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0590_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__is_32bit <= _0207_;
  end
  always @* begin
    if (\initial ) begin end
    _0211_ = _0594_;
    (* src = "libresoc.v:47917.5-47917.29" *)
    casez (\initial )
      /* src = "libresoc.v:47917.9-47917.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0594_ = _0818_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0818_ = 8'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0818_ = 8'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0818_ = _0964_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0964_ = core_core_traptype;
                    end
                  default:
                      _0964_ = 8'h00;
                endcase
              end
          endcase
        end
      default:
          _0594_ = 8'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__traptype <= _0211_;
  end
  always @* begin
    if (\initial ) begin end
    _0210_ = _0593_;
    (* src = "libresoc.v:47946.5-47946.29" *)
    casez (\initial )
      /* src = "libresoc.v:47946.9-47946.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0593_ = _0817_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0817_ = 13'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0817_ = 13'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0817_ = _0963_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0963_ = core_core_trapaddr;
                    end
                  default:
                      _0963_ = 13'h0000;
                endcase
              end
          endcase
        end
      default:
          _0593_ = 13'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__trapaddr <= _0210_;
  end
  always @* begin
    if (\initial ) begin end
    _0208_ = _0591_;
    (* src = "libresoc.v:47975.5-47975.29" *)
    casez (\initial )
      /* src = "libresoc.v:47975.9-47975.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0591_ = _0815_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0815_ = 8'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0815_ = 8'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0815_ = _0961_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0961_ = { \core_core_exc_$signal$9 , \core_core_exc_$signal$8 , \core_core_exc_$signal$7 , \core_core_exc_$signal$6 , \core_core_exc_$signal$5 , \core_core_exc_$signal$4 , \core_core_exc_$signal$3 , \core_core_exc_$signal  };
                    end
                  default:
                      _0961_ = 8'h00;
                endcase
              end
          endcase
        end
      default:
          _0591_ = 8'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_trap0__ldst_exc <= _0208_;
  end
  always @* begin
    if (\initial ) begin end
    _0087_ = _0470_;
    (* src = "libresoc.v:48004.5-48004.29" *)
    casez (\initial )
      /* src = "libresoc.v:48004.9-48004.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0470_ = _0694_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0694_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0694_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0694_ = _0840_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0840_ = issue_i;
                    end
                  default:
                      _0840_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0470_ = 1'h0;
    endcase
  end
  always @* begin
      \fus_cu_issue_i$19  <= _0087_;
  end
  always @* begin
    if (\initial ) begin end
    _0097_ = _0480_;
    (* src = "libresoc.v:48033.5-48033.29" *)
    casez (\initial )
      /* src = "libresoc.v:48033.9-48033.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0480_ = _0704_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0704_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0704_ = 4'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0704_ = _0850_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[3])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0850_ = \$254 ;
                    end
                  default:
                      _0850_ = 4'h0;
                endcase
              end
          endcase
        end
      default:
          _0480_ = 4'h0;
    endcase
  end
  always @* begin
      \fus_cu_rdmaskn_i$21  <= _0097_;
  end
  always @* begin
    if (\initial ) begin end
    _0158_ = _0541_;
    (* src = "libresoc.v:48062.5-48062.29" *)
    casez (\initial )
      /* src = "libresoc.v:48062.9-48062.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0541_ = _0765_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0765_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0765_ = 7'h00;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0765_ = _0911_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0911_ = dec_LOGICAL_LOGICAL__insn_type;
                    end
                  default:
                      _0911_ = 7'h00;
                endcase
              end
          endcase
        end
      default:
          _0541_ = 7'h00;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__insn_type <= _0158_;
  end
  always @* begin
    if (\initial ) begin end
    _0153_ = _0536_;
    (* src = "libresoc.v:48091.5-48091.29" *)
    casez (\initial )
      /* src = "libresoc.v:48091.9-48091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0536_ = _0760_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0760_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0760_ = 14'h0000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0760_ = _0906_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0906_ = dec_LOGICAL_LOGICAL__fn_unit;
                    end
                  default:
                      _0906_ = 14'h0000;
                endcase
              end
          endcase
        end
      default:
          _0536_ = 14'h0000;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__fn_unit <= _0153_;
  end
  always @* begin
    if (\initial ) begin end
    _0154_ = _0537_;
    _0155_ = _0538_;
    (* src = "libresoc.v:48120.5-48120.29" *)
    casez (\initial )
      /* src = "libresoc.v:48120.9-48120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0537_ = _0761_;
          _0538_ = _0762_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0761_ = 64'h0000000000000000;
                _0762_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0761_ = 64'h0000000000000000;
                _0762_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0761_ = _0907_;
                _0762_ = _0908_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0908_, _0907_ } = { dec_LOGICAL_LOGICAL__imm_data__ok, dec_LOGICAL_LOGICAL__imm_data__data };
                    end
                  default:
                    begin
                      _0907_ = 64'h0000000000000000;
                      _0908_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0537_ = 64'h0000000000000000;
          _0538_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__imm_data__data <= _0154_;
      fus_oper_i_alu_logical0__imm_data__ok <= _0155_;
  end
  always @* begin
    if (\initial ) begin end
    _0166_ = _0549_;
    _0167_ = _0550_;
    (* src = "libresoc.v:48150.5-48150.29" *)
    casez (\initial )
      /* src = "libresoc.v:48150.9-48150.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0549_ = _0773_;
          _0550_ = _0774_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0773_ = 1'h0;
                _0774_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0773_ = 1'h0;
                _0774_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0773_ = _0919_;
                _0774_ = _0920_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0919_, _0920_ } = { dec_LOGICAL_LOGICAL__rc__ok, dec_LOGICAL_LOGICAL__rc__rc };
                    end
                  default:
                    begin
                      _0919_ = 1'h0;
                      _0920_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0549_ = 1'h0;
          _0550_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__rc__ok <= _0166_;
      fus_oper_i_alu_logical0__rc__rc <= _0167_;
  end
  always @* begin
    if (\initial ) begin end
    _0163_ = _0546_;
    _0164_ = _0547_;
    (* src = "libresoc.v:48180.5-48180.29" *)
    casez (\initial )
      /* src = "libresoc.v:48180.9-48180.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0546_ = _0770_;
          _0547_ = _0771_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
              begin
                _0770_ = 1'h0;
                _0771_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
              begin
                _0770_ = 1'h0;
                _0771_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0770_ = _0916_;
                _0771_ = _0917_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _0917_, _0916_ } = { dec_LOGICAL_LOGICAL__oe__ok, dec_LOGICAL_LOGICAL__oe__oe };
                    end
                  default:
                    begin
                      _0916_ = 1'h0;
                      _0917_ = 1'h0;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _0546_ = 1'h0;
          _0547_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__oe__oe <= _0163_;
      fus_oper_i_alu_logical0__oe__ok <= _0164_;
  end
  always @* begin
    if (\initial ) begin end
    _0159_ = _0542_;
    (* src = "libresoc.v:48210.5-48210.29" *)
    casez (\initial )
      /* src = "libresoc.v:48210.9-48210.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0542_ = _0766_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0766_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0766_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0766_ = _0912_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0912_ = dec_LOGICAL_LOGICAL__invert_in;
                    end
                  default:
                      _0912_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0542_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__invert_in <= _0159_;
  end
  always @* begin
    if (\initial ) begin end
    _0169_ = _0552_;
    (* src = "libresoc.v:48239.5-48239.29" *)
    casez (\initial )
      /* src = "libresoc.v:48239.9-48239.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0552_ = _0776_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0776_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0776_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0776_ = _0922_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0922_ = dec_LOGICAL_LOGICAL__zero_a;
                    end
                  default:
                      _0922_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0552_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__zero_a <= _0169_;
  end
  always @* begin
    if (\initial ) begin end
    _0156_ = _0539_;
    (* src = "libresoc.v:48268.5-48268.29" *)
    casez (\initial )
      /* src = "libresoc.v:48268.9-48268.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0539_ = _0763_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0763_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0763_ = 2'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0763_ = _0909_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0909_ = dec_LOGICAL_LOGICAL__input_carry;
                    end
                  default:
                      _0909_ = 2'h0;
                endcase
              end
          endcase
        end
      default:
          _0539_ = 2'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__input_carry <= _0156_;
  end
  always @* begin
    if (\initial ) begin end
    _0160_ = _0543_;
    (* src = "libresoc.v:48297.5-48297.29" *)
    casez (\initial )
      /* src = "libresoc.v:48297.9-48297.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0543_ = _0767_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0767_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0767_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0767_ = _0913_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0913_ = dec_LOGICAL_LOGICAL__invert_out;
                    end
                  default:
                      _0913_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0543_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__invert_out <= _0160_;
  end
  always @* begin
    if (\initial ) begin end
    _0168_ = _0551_;
    (* src = "libresoc.v:48326.5-48326.29" *)
    casez (\initial )
      /* src = "libresoc.v:48326.9-48326.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:203" *)
    casez (ivalid_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _0551_ = _0775_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:204" *)
          casez (core_core_insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h05:
                _0775_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            7'h01:
                _0775_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _0775_ = _0921_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:221" *)
                casez (fu_enable[4])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _0921_ = dec_LOGICAL_LOGICAL__write_cr0;
                    end
                  default:
                      _0921_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _0551_ = 1'h0;
    endcase
  end
  always @* begin
      fus_oper_i_alu_logical0__write_cr0 <= _0168_;
  end
  assign \$1001  = _1643_;
  assign \$1003  = _0988_;
  assign \$1006  = _0989_;
  assign \$1010  = _1398_;
  assign \$1012  = _0990_;
  assign \$1019  = _0991_;
  assign \$1022  = _1644_;
  assign \$1024  = _0992_;
  assign \$1027  = _0993_;
  assign \$1031  = _1399_;
  assign \$1033  = _0994_;
  assign \$1037  = _0995_;
  assign \$1040  = _1645_;
  assign \$1042  = _0996_;
  assign \$1045  = _0997_;
  assign \$1049  = _1400_;
  assign \$1051  = _0998_;
  assign \$1059  = _0999_;
  assign \$1062  = _1646_;
  assign \$1064  = _1000_;
  assign \$1067  = _1001_;
  assign \$1071  = _1401_;
  assign \$1073  = _1002_;
  assign \$1079  = _1003_;
  assign \$1082  = _1647_;
  assign \$1084  = _1004_;
  assign \$1087  = _1005_;
  assign \$1091  = _1402_;
  assign \$1093  = _1006_;
  assign \$1099  = _1007_;
  assign \$1102  = _1648_;
  assign \$1104  = _1008_;
  assign \$1107  = _1009_;
  assign \$1111  = _1403_;
  assign \$1113  = _1010_;
  assign \$1118  = _1011_;
  assign \$1121  = _1649_;
  assign \$1123  = _1012_;
  assign \$1126  = _1013_;
  assign \$1130  = _1404_;
  assign \$1132  = _1014_;
  assign \$1136  = _1015_;
  assign \$1139  = _1650_;
  assign \$1141  = _1016_;
  assign \$1144  = _1017_;
  assign \$1147  = _1405_;
  assign \$1149  = _1018_;
  assign \$1152  = _1019_;
  assign \$1155  = _1651_;
  assign \$1158  = _1485_;
  assign \$1160  = _1486_;
  assign \$1162  = _1487_;
  assign \$1164  = _1488_;
  assign \$1166  = _1489_;
  assign \$1168  = _1490_;
  assign \$1170  = _1491_;
  assign \$1172  = _1492_;
  assign \$1174  = _1493_;
  assign \$1177  = _1494_;
  assign \$1179  = _1495_;
  assign \$1181  = _1496_;
  assign \$1183  = _1497_;
  assign \$1185  = _1498_;
  assign \$1187  = _1499_;
  assign \$1189  = _1500_;
  assign \$1191  = _1501_;
  assign \$1193  = _1502_;
  assign \$1195  = _1503_;
  assign \$1197  = _1504_;
  assign \$1199  = _1505_;
  assign \$1201  = _1506_;
  assign \$1203  = _1507_;
  assign \$1205  = _1508_;
  assign \$1207  = _1509_;
  assign \$1209  = _1510_;
  assign \$1211  = _1511_;
  assign \$1213  = _1020_;
  assign \$1215  = _1021_;
  assign \$1218  = _1022_;
  assign \$1221  = _1406_;
  assign \$1223  = _1023_;
  assign \$1226  = _1024_;
  assign \$1229  = _1652_;
  assign \$1231  = _1025_;
  assign \$1233  = _1026_;
  assign \$1235  = _1027_;
  assign \$1237  = _1028_;
  assign \$1239  = _1029_;
  assign \$1241  = _1030_;
  assign \$1243  = _1031_;
  assign \$1246  = _1032_;
  assign \$1249  = _1407_;
  assign \$1251  = _1033_;
  assign \$1254  = _1034_;
  assign \$1257  = _1632_;
  assign \$1259  = _1622_;
  assign \$1261  = _1653_;
  assign \$1263  = _1035_;
  assign \$1266  = _1036_;
  assign \$1269  = _1408_;
  assign \$1271  = _1037_;
  assign \$1274  = _1038_;
  assign \$1277  = _1633_;
  assign \$1279  = _1623_;
  assign \$1281  = _1654_;
  assign \$1283  = _1039_;
  assign \$1286  = _1040_;
  assign \$1289  = _1409_;
  assign \$1291  = _1041_;
  assign \$1294  = _1042_;
  assign \$1297  = _1634_;
  assign \$1299  = _1624_;
  assign \$1301  = _1655_;
  assign \$1303  = _1043_;
  assign \$1306  = _1044_;
  assign \$1309  = _1410_;
  assign \$1311  = _1045_;
  assign \$1314  = _1046_;
  assign \$1317  = _1635_;
  assign \$1319  = _1625_;
  assign \$1321  = _1656_;
  assign \$1323  = _1047_;
  assign \$1326  = _1048_;
  assign \$1329  = _1411_;
  assign \$1331  = _1049_;
  assign \$1334  = _1050_;
  assign \$1337  = _1636_;
  assign \$1339  = _1626_;
  assign \$1341  = _1657_;
  assign \$1343  = _1051_;
  assign \$1346  = _1052_;
  assign \$1349  = _1412_;
  assign \$1351  = _1053_;
  assign \$1354  = _1054_;
  assign \$1357  = _1637_;
  assign \$1359  = _1627_;
  assign \$1361  = _1658_;
  assign \$1363  = _1512_;
  assign \$1365  = _1513_;
  assign \$1367  = _1514_;
  assign \$1369  = _1515_;
  assign \$1371  = _1516_;
  assign \$1374  = _1517_;
  assign \$1376  = _1518_;
  assign \$1378  = _1519_;
  assign \$1380  = _1520_;
  assign \$1382  = _1521_;
  assign \$1384  = _1055_;
  assign \$1386  = _1056_;
  assign \$1388  = _1057_;
  assign \$1390  = _1058_;
  assign \$1393  = _1059_;
  assign \$1396  = _1413_;
  assign \$1398  = _1060_;
  assign \$1401  = _1061_;
  assign \$1404  = _1659_;
  assign \$1406  = _1062_;
  assign \$1409  = _1063_;
  assign \$1412  = _1414_;
  assign \$1414  = _1064_;
  assign \$1417  = _1065_;
  assign \$1420  = _1660_;
  assign \$1422  = _1066_;
  assign \$1425  = _1067_;
  assign \$1428  = _1415_;
  assign \$1430  = _1068_;
  assign \$1433  = _1069_;
  assign \$1436  = _1661_;
  assign \$1438  = _1522_;
  assign \$1440  = _1523_;
  assign \$1443  = _1524_;
  assign \$1445  = _1525_;
  assign \$1442  = _1602_;
  assign \$1448  = _1070_;
  assign \$1450  = _1071_;
  assign \$1452  = _1072_;
  assign \$1454  = _1073_;
  assign \$1456  = _1074_;
  assign \$1459  = _1075_;
  assign \$1462  = _1416_;
  assign \$1464  = _1076_;
  assign \$1467  = _1077_;
  assign \$1470  = _1662_;
  assign \$1472  = _1078_;
  assign \$1475  = _1079_;
  assign \$1478  = _1417_;
  assign \$1480  = _1080_;
  assign \$1483  = _1081_;
  assign \$1486  = _1663_;
  assign \$1488  = _1082_;
  assign \$1491  = _1083_;
  assign \$1494  = _1418_;
  assign \$1496  = _1084_;
  assign \$1499  = _1085_;
  assign \$1502  = _1664_;
  assign \$1504  = _1086_;
  assign \$1507  = _1087_;
  assign \$1510  = _1419_;
  assign \$1512  = _1088_;
  assign \$1515  = _1089_;
  assign \$1518  = _1665_;
  assign \$1520  = _1526_;
  assign \$1522  = _1527_;
  assign \$1524  = _1528_;
  assign \$1526  = _1529_;
  assign \$1528  = _1530_;
  assign \$1530  = _1531_;
  assign \$1532  = _1090_;
  assign \$1534  = _1091_;
  assign \$1536  = _1092_;
  assign \$1538  = _1093_;
  assign \$1540  = _1094_;
  assign \$1543  = _1095_;
  assign \$1546  = _1420_;
  assign \$1548  = _1096_;
  assign \$1551  = _1097_;
  assign \$1554  = _1666_;
  assign \$1556  = _1098_;
  assign \$1559  = _1099_;
  assign \$1562  = _1421_;
  assign \$1564  = _1100_;
  assign \$1567  = _1101_;
  assign \$1570  = _1667_;
  assign \$1572  = _1102_;
  assign \$1575  = _1103_;
  assign \$1578  = _1422_;
  assign \$1580  = _1104_;
  assign \$1583  = _1105_;
  assign \$1586  = _1668_;
  assign \$1588  = _1106_;
  assign \$1591  = _1107_;
  assign \$1594  = _1423_;
  assign \$1596  = _1108_;
  assign \$1599  = _1109_;
  assign \$1602  = _1669_;
  assign \$1605  = _1532_;
  assign \$1607  = _1533_;
  assign \$1609  = _1534_;
  assign \$1604  = _1603_;
  assign \$1613  = _1535_;
  assign \$1615  = _1536_;
  assign \$1617  = _1537_;
  assign \$1612  = _1604_;
  assign \$1620  = _1110_;
  assign \$1622  = _1111_;
  assign \$1624  = _1112_;
  assign \$1626  = _1113_;
  assign \$1628  = _1114_;
  assign \$1630  = _1115_;
  assign \$1633  = _1116_;
  assign \$1637  = _1424_;
  assign \$1639  = _1117_;
  assign \$1644  = _1118_;
  assign \$1647  = _1670_;
  assign \$1649  = _1119_;
  assign \$1652  = _1120_;
  assign \$1655  = _1425_;
  assign \$1657  = _1121_;
  assign \$1660  = _1122_;
  assign \$1663  = _1671_;
  assign \$1665  = _1123_;
  assign \$1668  = _1124_;
  assign \$1671  = _1426_;
  assign \$1673  = _1125_;
  assign \$1676  = _1126_;
  assign \$1679  = _1672_;
  assign \$1681  = _1127_;
  assign \$1684  = _1128_;
  assign \$1687  = _1427_;
  assign \$1689  = _1129_;
  assign \$1692  = _1130_;
  assign \$1695  = _1673_;
  assign \$1697  = _1131_;
  assign \$1700  = _1132_;
  assign \$1703  = _1428_;
  assign \$1705  = _1133_;
  assign \$1708  = _1134_;
  assign \$1711  = _1674_;
  assign \$1713  = _1538_;
  assign \$1715  = _1539_;
  assign \$1717  = _1540_;
  assign \$1719  = _1541_;
  assign \$1721  = _1542_;
  assign \$1723  = _1543_;
  assign \$1725  = _1544_;
  assign \$1727  = _1545_;
  assign \$1729  = _1546_;
  assign \$1731  = _1547_;
  assign \$1733  = _1548_;
  assign \$1735  = _1549_;
  assign \$1737  = _1135_;
  assign \$1739  = _1136_;
  assign \$1741  = _1137_;
  assign \$1744  = _1138_;
  assign \$1747  = _1429_;
  assign \$1749  = _1139_;
  assign \$1752  = _1140_;
  assign \$1755  = _1675_;
  assign \$1757  = _1141_;
  assign \$1760  = _1142_;
  assign \$1763  = _1430_;
  assign \$1765  = _1143_;
  assign \$1768  = _1144_;
  assign \$1771  = _1676_;
  assign \$1773  = _1550_;
  assign \$1776  = _1551_;
  assign \$1775  = _1605_;
  assign \$1779  = _1145_;
  assign \$1781  = _1146_;
  assign \$1784  = _1147_;
  assign \$1787  = _1431_;
  assign \$1789  = _1148_;
  assign \$1792  = _1149_;
  assign \$1795  = _1677_;
  assign \$1797  = _1606_;
  assign \$1799  = _1150_;
  assign \$1801  = _1151_;
  assign \$1804  = _1152_;
  assign \$1807  = _1432_;
  assign \$1809  = _1153_;
  assign \$1812  = _1154_;
  assign \$1815  = _1678_;
  assign \$182  = _1155_;
  assign \$181  = _1609_;
  assign \$186  = _1156_;
  assign \$185  = _1610_;
  assign \$190  = _1157_;
  assign \$189  = _1611_;
  assign \$194  = _1158_;
  assign \$193  = _1612_;
  assign \$198  = _1159_;
  assign \$197  = _1613_;
  assign \$202  = _1160_;
  assign \$201  = _1614_;
  assign \$206  = _1161_;
  assign \$205  = _1615_;
  assign \$210  = _1162_;
  assign \$209  = _1616_;
  assign \$214  = _1163_;
  assign \$213  = _1617_;
  assign \$218  = _1164_;
  assign \$217  = _1618_;
  assign \$221  = _1396_;
  assign \$224  = _1638_;
  assign \$226  = _1397_;
  assign \$229  = _1165_;
  assign \$231  = _1166_;
  assign \$233  = _1372_;
  assign \$235  = _1552_;
  assign \$237  = _1167_;
  assign \$239  = _1553_;
  assign \$241  = _1373_;
  assign \$243  = _1168_;
  assign \$245  = _1374_;
  assign \$247  = _1554_;
  assign \$228  = _1433_;
  assign \$250  = _1434_;
  assign \$252  = _1435_;
  assign \$254  = _1436_;
  assign \$257  = _1169_;
  assign \$259  = _1170_;
  assign \$261  = _1375_;
  assign \$263  = _1555_;
  assign \$265  = _1171_;
  assign \$267  = _1556_;
  assign \$256  = _1437_;
  assign \$271  = _1172_;
  assign \$273  = _1173_;
  assign \$275  = _1376_;
  assign \$277  = _1557_;
  assign \$279  = _1174_;
  assign \$281  = _1558_;
  assign \$283  = _1175_;
  assign \$285  = _1176_;
  assign \$287  = _1377_;
  assign \$289  = _1559_;
  assign \$291  = _1378_;
  assign \$293  = _1177_;
  assign \$295  = _1379_;
  assign \$297  = _1560_;
  assign \$270  = _1438_;
  assign \$301  = _1178_;
  assign \$303  = _1179_;
  assign \$305  = _1380_;
  assign \$307  = _1561_;
  assign \$309  = _1180_;
  assign \$311  = _1562_;
  assign \$300  = _1439_;
  assign \$315  = _1181_;
  assign \$317  = _1182_;
  assign \$319  = _1381_;
  assign \$321  = _1563_;
  assign \$323  = _1183_;
  assign \$325  = _1564_;
  assign \$314  = _1440_;
  assign \$329  = _1184_;
  assign \$331  = _1185_;
  assign \$333  = _1382_;
  assign \$335  = _1565_;
  assign \$337  = _1186_;
  assign \$339  = _1566_;
  assign \$341  = _1383_;
  assign \$343  = _1187_;
  assign \$345  = _1384_;
  assign \$347  = _1567_;
  assign \$328  = _1441_;
  assign \$350  = _1442_;
  assign \$352  = _1188_;
  assign \$354  = _1189_;
  assign \$356  = _1443_;
  assign \$358  = _1190_;
  assign \$360  = _1191_;
  assign \$362  = _1679_;
  assign \$364  = _1192_;
  assign \$366  = _1193_;
  assign \$368  = _1444_;
  assign \$370  = _1194_;
  assign \$372  = _1195_;
  assign \$374  = _1680_;
  assign \$376  = _1196_;
  assign \$378  = _1197_;
  assign \$380  = _1445_;
  assign \$382  = _1198_;
  assign \$384  = _1199_;
  assign \$386  = _1681_;
  assign \$388  = _1200_;
  assign \$390  = _1201_;
  assign \$392  = _1446_;
  assign \$394  = _1202_;
  assign \$396  = _1203_;
  assign \$398  = _1682_;
  assign \$400  = _1204_;
  assign \$402  = _1205_;
  assign \$404  = _1447_;
  assign \$406  = _1206_;
  assign \$408  = _1207_;
  assign \$410  = _1683_;
  assign \$412  = _1208_;
  assign \$414  = _1209_;
  assign \$416  = _1448_;
  assign \$418  = _1210_;
  assign \$420  = _1211_;
  assign \$422  = _1684_;
  assign \$424  = _1212_;
  assign \$426  = _1213_;
  assign \$428  = _1449_;
  assign \$430  = _1214_;
  assign \$432  = _1215_;
  assign \$434  = _1685_;
  assign \$436  = _1216_;
  assign \$438  = _1217_;
  assign \$440  = _1450_;
  assign \$442  = _1218_;
  assign \$444  = _1219_;
  assign \$446  = _1686_;
  assign \$448  = _1220_;
  assign \$450  = _1221_;
  assign \$452  = _1451_;
  assign \$454  = _1222_;
  assign \$456  = _1223_;
  assign \$458  = _1687_;
  assign \$460  = _1224_;
  assign \$462  = _1225_;
  assign \$464  = _1452_;
  assign \$466  = _1226_;
  assign \$468  = _1227_;
  assign \$470  = _1688_;
  assign \$472  = _1228_;
  assign \$474  = _1229_;
  assign \$476  = _1453_;
  assign \$478  = _1230_;
  assign \$480  = _1231_;
  assign \$482  = _1689_;
  assign \$484  = _1232_;
  assign \$486  = _1233_;
  assign \$488  = _1454_;
  assign \$490  = _1234_;
  assign \$492  = _1235_;
  assign \$494  = _1690_;
  assign \$496  = _1236_;
  assign \$498  = _1237_;
  assign \$500  = _1455_;
  assign \$502  = _1238_;
  assign \$504  = _1239_;
  assign \$506  = _1691_;
  assign \$508  = _1240_;
  assign \$510  = _1241_;
  assign \$512  = _1456_;
  assign \$514  = _1242_;
  assign \$516  = _1243_;
  assign \$518  = _1692_;
  assign \$520  = _1244_;
  assign \$522  = _1245_;
  assign \$524  = _1457_;
  assign \$526  = _1246_;
  assign \$528  = _1247_;
  assign \$530  = _1693_;
  assign \$532  = _1248_;
  assign \$534  = _1249_;
  assign \$536  = _1458_;
  assign \$538  = _1250_;
  assign \$540  = _1251_;
  assign \$542  = _1694_;
  assign \$544  = _1252_;
  assign \$546  = _1253_;
  assign \$548  = _1459_;
  assign \$550  = _1254_;
  assign \$552  = _1255_;
  assign \$554  = _1695_;
  assign \$556  = _1256_;
  assign \$558  = _1257_;
  assign \$560  = _1460_;
  assign \$562  = _1258_;
  assign \$564  = _1259_;
  assign \$566  = _1696_;
  assign \$568  = _1260_;
  assign \$570  = _1261_;
  assign \$572  = _1461_;
  assign \$574  = _1262_;
  assign \$576  = _1263_;
  assign \$578  = _1697_;
  assign \$581  = _1568_;
  assign \$583  = _1569_;
  assign \$585  = _1570_;
  assign \$587  = _1571_;
  assign \$589  = _1572_;
  assign \$591  = _1573_;
  assign \$593  = _1574_;
  assign \$595  = _1575_;
  assign \$597  = _1576_;
  assign \$599  = _1577_;
  assign \$601  = _1578_;
  assign \$603  = _1579_;
  assign \$605  = _1580_;
  assign \$607  = _1581_;
  assign \$609  = _1582_;
  assign \$611  = _1583_;
  assign \$613  = _1584_;
  assign \$615  = _1585_;
  assign \$617  = _1619_;
  assign \$619  = _1264_;
  assign \$621  = _1265_;
  assign \$623  = _1385_;
  assign \$625  = _1586_;
  assign \$627  = _1266_;
  assign \$629  = _1587_;
  assign \$631  = _1267_;
  assign \$633  = _1268_;
  assign \$635  = _1462_;
  assign \$637  = _1269_;
  assign \$639  = _1270_;
  assign \$641  = _1698_;
  assign \$643  = _1271_;
  assign \$645  = _1272_;
  assign \$647  = _1463_;
  assign \$649  = _1273_;
  assign \$651  = _1274_;
  assign \$653  = _1699_;
  assign \$655  = _1275_;
  assign \$657  = _1276_;
  assign \$659  = _1464_;
  assign \$661  = _1277_;
  assign \$663  = _1278_;
  assign \$665  = _1700_;
  assign \$667  = _1279_;
  assign \$669  = _1280_;
  assign \$671  = _1465_;
  assign \$673  = _1281_;
  assign \$675  = _1282_;
  assign \$677  = _1701_;
  assign \$679  = _1283_;
  assign \$681  = _1284_;
  assign \$683  = _1466_;
  assign \$685  = _1285_;
  assign \$687  = _1286_;
  assign \$689  = _1702_;
  assign \$691  = _1287_;
  assign \$693  = _1288_;
  assign \$695  = _1467_;
  assign \$697  = _1289_;
  assign \$699  = _1290_;
  assign \$701  = _1703_;
  assign \$704  = _1588_;
  assign \$706  = _1589_;
  assign \$708  = _1590_;
  assign \$710  = _1591_;
  assign \$712  = _1592_;
  assign \$703  = _1607_;
  assign \$715  = _1386_;
  assign \$717  = _1291_;
  assign \$719  = _1387_;
  assign \$721  = _1593_;
  assign \$723  = _1292_;
  assign \$725  = _1293_;
  assign \$727  = _1468_;
  assign \$729  = _1294_;
  assign \$731  = _1295_;
  assign \$733  = _1704_;
  assign \$735  = _1296_;
  assign \$737  = _1297_;
  assign \$739  = _1469_;
  assign \$741  = _1298_;
  assign \$743  = _1299_;
  assign \$745  = _1705_;
  assign \$747  = _1300_;
  assign \$749  = _1301_;
  assign \$751  = _1470_;
  assign \$753  = _1302_;
  assign \$755  = _1303_;
  assign \$757  = _1706_;
  assign \$760  = _1594_;
  assign \$762  = _1595_;
  assign \$759  = _1608_;
  assign \$765  = _1304_;
  assign \$767  = _1305_;
  assign \$769  = _1388_;
  assign \$771  = _1596_;
  assign \$773  = _1306_;
  assign \$775  = _1307_;
  assign \$777  = _1471_;
  assign \$779  = _1308_;
  assign \$781  = _1309_;
  assign \$783  = _1707_;
  assign \$785  = _1310_;
  assign \$787  = _1311_;
  assign \$789  = _1472_;
  assign \$791  = _1312_;
  assign \$793  = _1313_;
  assign \$795  = _1708_;
  assign \$797  = _1314_;
  assign \$799  = _1315_;
  assign \$801  = _1473_;
  assign \$803  = _1316_;
  assign \$805  = _1317_;
  assign \$807  = _1639_;
  assign \$809  = _1628_;
  assign \$811  = _1709_;
  assign \$813  = _1318_;
  assign \$815  = _1319_;
  assign \$817  = _1474_;
  assign \$819  = _1320_;
  assign \$821  = _1321_;
  assign \$823  = _1640_;
  assign \$825  = _1629_;
  assign \$827  = _1710_;
  assign \$830  = _1597_;
  assign \$832  = _1322_;
  assign \$834  = _1323_;
  assign \$836  = _1475_;
  assign \$838  = _1324_;
  assign \$840  = _1325_;
  assign \$842  = _1641_;
  assign \$844  = _1630_;
  assign \$846  = _1711_;
  assign \$848  = _1326_;
  assign \$850  = _1327_;
  assign \$852  = _1476_;
  assign \$854  = _1328_;
  assign \$856  = _1329_;
  assign \$858  = _1642_;
  assign \$860  = _1631_;
  assign \$862  = _1712_;
  assign \$864  = _1330_;
  assign \$866  = _1331_;
  assign \$868  = _1477_;
  assign \$870  = _1332_;
  assign \$872  = _1333_;
  assign \$874  = _1713_;
  assign \$876  = _1334_;
  assign \$878  = _1335_;
  assign \$880  = _1478_;
  assign \$882  = _1336_;
  assign \$884  = _1337_;
  assign \$886  = _1714_;
  assign \$888  = _1338_;
  assign \$890  = _1339_;
  assign \$892  = _1479_;
  assign \$894  = _1340_;
  assign \$896  = _1341_;
  assign \$898  = _1715_;
  assign \$900  = _1342_;
  assign \$902  = _1343_;
  assign \$904  = _1480_;
  assign \$906  = _1344_;
  assign \$908  = _1345_;
  assign \$910  = _1716_;
  assign \$912  = _1346_;
  assign \$914  = _1347_;
  assign \$916  = _1481_;
  assign \$918  = _1348_;
  assign \$920  = _1349_;
  assign \$922  = _1717_;
  assign \$924  = _1598_;
  assign \$926  = _1599_;
  assign \$928  = _1600_;
  assign \$930  = _1601_;
  assign \$932  = _1620_;
  assign \$934  = _1350_;
  assign \$936  = _1351_;
  assign \$938  = _1482_;
  assign \$940  = _1352_;
  assign \$942  = _1353_;
  assign \$944  = _1718_;
  assign \$946  = _1621_;
  assign \$948  = _1354_;
  assign \$950  = _1355_;
  assign \$952  = _1356_;
  assign \$954  = _1357_;
  assign \$956  = _1358_;
  assign \$958  = _1359_;
  assign \$960  = _1360_;
  assign \$962  = _1361_;
  assign \$964  = _1362_;
  assign \$966  = _1363_;
  assign \$968  = _1364_;
  assign \$970  = _1365_;
  assign \$972  = _1483_;
  assign \$974  = _1366_;
  assign \$980  = _1367_;
  assign \$982  = _1719_;
  assign \$984  = _1368_;
  assign \$987  = _1369_;
  assign \$991  = _1484_;
  assign \$993  = _1370_;
  assign \$998  = _1371_;
  assign \$223  = \$224 ;
  assign \$580  = \$615 ;
  assign \$829  = \$830 ;
  assign \$1157  = \$1174 ;
  assign \$1176  = \$1193 ;
  assign \$1373  = \$1382 ;
  assign o_ok = 1'h0;
  assign ea_ok = 1'h0;
  assign spr_spr1__wen = \wp$1811 ;
  assign \spr_spr1__addr$175  = \addr_en$1814 [3:0];
  assign spr_spr1__data_i = \fus_dest2_o$162 ;
  assign \addr_en$1814  = \$1815 ;
  assign \wp$1811  = \$1812 ;
  assign \wr_pick_rise$1057  = \$1809 ;
  assign \wr_pick$1803  = \$1804 ;
  assign wrpick_SPR_spr1_i = \$1801 ;
  assign wrflag_spr0_spr1_1 = \$1799 ;
  assign state_wen = \$1797 ;
  assign \state_data_i$174  = \fus_dest5_o$161 ;
  assign \addr_en$1794  = \$1795 ;
  assign \wp$1791  = \$1792 ;
  assign \wr_pick_rise$1017  = \$1789 ;
  assign \wr_pick$1783  = \$1784 ;
  assign wrpick_STATE_msr_i = \$1781 ;
  assign wrflag_trap0_msr_4 = \$1779 ;
  assign state_nia_wen = \$1775 ;
  assign state_data_i = \$1773 ;
  assign \addr_en$1770  = \$1771 ;
  assign \wp$1767  = \$1768 ;
  assign \wr_pick_rise$1016  = \$1765 ;
  assign \wr_pick$1759  = \$1760 ;
  assign wrflag_trap0_nia_3 = \$1757 ;
  assign \addr_en$1754  = \$1755 ;
  assign \wp$1751  = \$1752 ;
  assign \wr_pick_rise$1642  = \$1749 ;
  assign \wr_pick$1743  = \$1744 ;
  assign wrpick_STATE_nia_i[1] = \$1741 ;
  assign wrpick_STATE_nia_i[0] = \$1739 ;
  assign wrflag_branch0_nia_2 = \$1737 ;
  assign fast_dest1__wen = \$1735 ;
  assign fast_dest1__addr = \$1727 ;
  assign fast_dest1__data_i = \$1719 ;
  assign \addr_en$1710  = \$1711 ;
  assign \wp$1707  = \$1708 ;
  assign \wr_pick_rise$1015  = \$1705 ;
  assign \wr_pick$1699  = \$1700 ;
  assign wrflag_trap0_fast1_2 = \$1697 ;
  assign \addr_en$1694  = \$1695 ;
  assign \wp$1691  = \$1692 ;
  assign \wr_pick_rise$1641  = \$1689 ;
  assign \wr_pick$1683  = \$1684 ;
  assign wrflag_branch0_fast1_1 = \$1681 ;
  assign \addr_en$1678  = \$1679 ;
  assign \wp$1675  = \$1676 ;
  assign \wr_pick_rise$1056  = \$1673 ;
  assign \wr_pick$1667  = \$1668 ;
  assign wrflag_spr0_fast1_2 = \$1665 ;
  assign \addr_en$1662  = \$1663 ;
  assign \wp$1659  = \$1660 ;
  assign \wr_pick_rise$1014  = \$1657 ;
  assign \wr_pick$1651  = \$1652 ;
  assign wrflag_trap0_fast1_1 = \$1649 ;
  assign \addr_en$1646  = \$1647 ;
  assign \wp$1643  = \$1644 ;
  assign \fus_cu_wr__go_i$149 [2] = \wr_pick_rise$1642 ;
  assign \fus_cu_wr__go_i$149 [1] = \wr_pick_rise$1641 ;
  assign \fus_cu_wr__go_i$149 [0] = \wr_pick_rise$1636 ;
  assign \wr_pick_rise$1636  = \$1639 ;
  assign \wr_pick$1632  = \$1633 ;
  assign wrpick_FAST_fast1_i[4] = \$1630 ;
  assign wrpick_FAST_fast1_i[3] = \$1628 ;
  assign wrpick_FAST_fast1_i[2] = \$1626 ;
  assign wrpick_FAST_fast1_i[1] = \$1624 ;
  assign wrpick_FAST_fast1_i[0] = \$1622 ;
  assign wrflag_branch0_fast1_0 = \$1620 ;
  assign \xer_wen$173  = \$1612 ;
  assign \xer_data_i$172  = \$1604 ;
  assign \addr_en$1601  = \$1602 ;
  assign \wp$1598  = \$1599 ;
  assign \wr_pick_rise$1097  = \$1596 ;
  assign \wr_pick$1590  = \$1591 ;
  assign wrflag_mul0_xer_so_3 = \$1588 ;
  assign \addr_en$1585  = \$1586 ;
  assign \wp$1582  = \$1583 ;
  assign \wr_pick_rise$1077  = \$1580 ;
  assign \wr_pick$1574  = \$1575 ;
  assign wrflag_div0_xer_so_3 = \$1572 ;
  assign \addr_en$1569  = \$1570 ;
  assign \wp$1566  = \$1567 ;
  assign \wr_pick_rise$1055  = \$1564 ;
  assign \wr_pick$1558  = \$1559 ;
  assign wrflag_spr0_xer_so_3 = \$1556 ;
  assign \addr_en$1553  = \$1554 ;
  assign \wp$1550  = \$1551 ;
  assign \wr_pick_rise$979  = \$1548 ;
  assign \wr_pick$1542  = \$1543 ;
  assign wrpick_XER_xer_so_i[3] = \$1540 ;
  assign wrpick_XER_xer_so_i[2] = \$1538 ;
  assign wrpick_XER_xer_so_i[1] = \$1536 ;
  assign wrpick_XER_xer_so_i[0] = \$1534 ;
  assign wrflag_alu0_xer_so_4 = \$1532 ;
  assign \xer_wen$171  = \$1530 ;
  assign \xer_data_i$170  = \$1524 ;
  assign \addr_en$1517  = \$1518 ;
  assign \wp$1514  = \$1515 ;
  assign \wr_pick_rise$1096  = \$1512 ;
  assign \wr_pick$1506  = \$1507 ;
  assign wrflag_mul0_xer_ov_2 = \$1504 ;
  assign \addr_en$1501  = \$1502 ;
  assign \wp$1498  = \$1499 ;
  assign \wr_pick_rise$1076  = \$1496 ;
  assign \wr_pick$1490  = \$1491 ;
  assign wrflag_div0_xer_ov_2 = \$1488 ;
  assign \addr_en$1485  = \$1486 ;
  assign \wp$1482  = \$1483 ;
  assign \wr_pick_rise$1054  = \$1480 ;
  assign \wr_pick$1474  = \$1475 ;
  assign wrflag_spr0_xer_ov_4 = \$1472 ;
  assign \addr_en$1469  = \$1470 ;
  assign \wp$1466  = \$1467 ;
  assign \wr_pick_rise$978  = \$1464 ;
  assign \wr_pick$1458  = \$1459 ;
  assign wrpick_XER_xer_ov_i[3] = \$1456 ;
  assign wrpick_XER_xer_ov_i[2] = \$1454 ;
  assign wrpick_XER_xer_ov_i[1] = \$1452 ;
  assign wrpick_XER_xer_ov_i[0] = \$1450 ;
  assign wrflag_alu0_xer_ov_3 = \$1448 ;
  assign xer_wen = \$1442 ;
  assign xer_data_i = \$1440 ;
  assign \addr_en$1435  = \$1436 ;
  assign \wp$1432  = \$1433 ;
  assign \wr_pick_rise$1116  = \$1430 ;
  assign \wr_pick$1424  = \$1425 ;
  assign wrflag_shiftrot0_xer_ca_2 = \$1422 ;
  assign \addr_en$1419  = \$1420 ;
  assign \wp$1416  = \$1417 ;
  assign \wr_pick_rise$1053  = \$1414 ;
  assign \wr_pick$1408  = \$1409 ;
  assign wrflag_spr0_xer_ca_5 = \$1406 ;
  assign \addr_en$1403  = \$1404 ;
  assign \wp$1400  = \$1401 ;
  assign \wr_pick_rise$977  = \$1398 ;
  assign \wr_pick$1392  = \$1393 ;
  assign wrpick_XER_xer_ca_i[2] = \$1390 ;
  assign wrpick_XER_xer_ca_i[1] = \$1388 ;
  assign wrpick_XER_xer_ca_i[0] = \$1386 ;
  assign wrflag_alu0_xer_ca_2 = \$1384 ;
  assign cr_wen = \$1382 [7:0];
  assign cr_data_i = \$1371 ;
  assign \addr_en$1356  = \$1361 ;
  assign \wp$1353  = \$1354 ;
  assign \wr_pick_rise$1115  = \$1351 ;
  assign \wr_pick$1345  = \$1346 ;
  assign wrflag_shiftrot0_cr_a_1 = \$1343 ;
  assign \addr_en$1336  = \$1341 ;
  assign \wp$1333  = \$1334 ;
  assign \wr_pick_rise$1095  = \$1331 ;
  assign \wr_pick$1325  = \$1326 ;
  assign wrflag_mul0_cr_a_1 = \$1323 ;
  assign \addr_en$1316  = \$1321 ;
  assign \wp$1313  = \$1314 ;
  assign \wr_pick_rise$1075  = \$1311 ;
  assign \wr_pick$1305  = \$1306 ;
  assign wrflag_div0_cr_a_1 = \$1303 ;
  assign \addr_en$1296  = \$1301 ;
  assign \wp$1293  = \$1294 ;
  assign \wr_pick_rise$1035  = \$1291 ;
  assign \wr_pick$1285  = \$1286 ;
  assign wrflag_logical0_cr_a_1 = \$1283 ;
  assign \addr_en$1276  = \$1281 ;
  assign \wp$1273  = \$1274 ;
  assign \wr_pick_rise$996  = \$1271 ;
  assign \wr_pick$1265  = \$1266 ;
  assign wrflag_cr0_cr_a_2 = \$1263 ;
  assign \addr_en$1256  = \$1261 ;
  assign \wp$1253  = \$1254 ;
  assign \wr_pick_rise$976  = \$1251 ;
  assign \wr_pick$1245  = \$1246 ;
  assign wrpick_CR_cr_a_i[5] = \$1243 ;
  assign wrpick_CR_cr_a_i[4] = \$1241 ;
  assign wrpick_CR_cr_a_i[3] = \$1239 ;
  assign wrpick_CR_cr_a_i[2] = \$1237 ;
  assign wrpick_CR_cr_a_i[1] = \$1235 ;
  assign wrpick_CR_cr_a_i[0] = \$1233 ;
  assign wrflag_alu0_cr_a_1 = \$1231 ;
  assign cr_full_wr__wen = \addr_en$1228 ;
  assign cr_full_wr__data_i = fus_dest2_o;
  assign \addr_en$1228  = \$1229 ;
  assign \wp$1225  = \$1226 ;
  assign \wr_pick_rise$995  = \$1223 ;
  assign \wr_pick$1217  = \$1218 ;
  assign wrpick_CR_full_cr_i = \$1215 ;
  assign wrflag_cr0_full_cr_1 = \$1213 ;
  assign int_dest1__wen = \$1211 ;
  assign int_dest1__addr = \$1193 [4:0];
  assign int_dest1__data_i = \$1174 [63:0];
  assign \addr_en$1154  = \$1155 ;
  assign \wp$1151  = \$1152 ;
  assign \wr_pick_rise$1134  = \$1149 ;
  assign \wr_pick$1143  = \$1144 ;
  assign wrflag_ldst0_o_1 = \$1141 ;
  assign \addr_en$1138  = \$1139 ;
  assign \wp$1135  = \$1136 ;
  assign \fus_cu_wr__go_i$114 [1] = \wr_pick_rise$1134 ;
  assign \fus_cu_wr__go_i$114 [0] = \wr_pick_rise$1129 ;
  assign \wr_pick_rise$1129  = \$1132 ;
  assign \wr_pick$1125  = \$1126 ;
  assign wrflag_ldst0_o_0 = \$1123 ;
  assign \addr_en$1120  = \$1121 ;
  assign \wp$1117  = \$1118 ;
  assign \fus_cu_wr__go_i$112 [2] = \wr_pick_rise$1116 ;
  assign \fus_cu_wr__go_i$112 [1] = \wr_pick_rise$1115 ;
  assign \fus_cu_wr__go_i$112 [0] = \wr_pick_rise$1110 ;
  assign \wr_pick_rise$1110  = \$1113 ;
  assign \wr_pick$1106  = \$1107 ;
  assign wrflag_shiftrot0_o_0 = \$1104 ;
  assign \addr_en$1101  = \$1102 ;
  assign \wp$1098  = \$1099 ;
  assign \fus_cu_wr__go_i$109 [3] = \wr_pick_rise$1097 ;
  assign \fus_cu_wr__go_i$109 [2] = \wr_pick_rise$1096 ;
  assign \fus_cu_wr__go_i$109 [1] = \wr_pick_rise$1095 ;
  assign \fus_cu_wr__go_i$109 [0] = \wr_pick_rise$1090 ;
  assign \wr_pick_rise$1090  = \$1093 ;
  assign \wr_pick$1086  = \$1087 ;
  assign wrflag_mul0_o_0 = \$1084 ;
  assign \addr_en$1081  = \$1082 ;
  assign \wp$1078  = \$1079 ;
  assign \fus_cu_wr__go_i$106 [3] = \wr_pick_rise$1077 ;
  assign \fus_cu_wr__go_i$106 [2] = \wr_pick_rise$1076 ;
  assign \fus_cu_wr__go_i$106 [1] = \wr_pick_rise$1075 ;
  assign \fus_cu_wr__go_i$106 [0] = \wr_pick_rise$1070 ;
  assign \wr_pick_rise$1070  = \$1073 ;
  assign \wr_pick$1066  = \$1067 ;
  assign wrflag_div0_o_0 = \$1064 ;
  assign \addr_en$1061  = \$1062 ;
  assign \wp$1058  = \$1059 ;
  assign \fus_cu_wr__go_i$103 [1] = \wr_pick_rise$1057 ;
  assign \fus_cu_wr__go_i$103 [2] = \wr_pick_rise$1056 ;
  assign \fus_cu_wr__go_i$103 [3] = \wr_pick_rise$1055 ;
  assign \fus_cu_wr__go_i$103 [4] = \wr_pick_rise$1054 ;
  assign \fus_cu_wr__go_i$103 [5] = \wr_pick_rise$1053 ;
  assign \fus_cu_wr__go_i$103 [0] = \wr_pick_rise$1048 ;
  assign \wr_pick_rise$1048  = \$1051 ;
  assign \wr_pick$1044  = \$1045 ;
  assign wrflag_spr0_o_0 = \$1042 ;
  assign \addr_en$1039  = \$1040 ;
  assign \wp$1036  = \$1037 ;
  assign \fus_cu_wr__go_i$100 [1] = \wr_pick_rise$1035 ;
  assign \fus_cu_wr__go_i$100 [0] = \wr_pick_rise$1030 ;
  assign \wr_pick_rise$1030  = \$1033 ;
  assign \wr_pick$1026  = \$1027 ;
  assign wrflag_logical0_o_0 = \$1024 ;
  assign \addr_en$1021  = \$1022 ;
  assign \wp$1018  = \$1019 ;
  assign \fus_cu_wr__go_i$97 [4] = \wr_pick_rise$1017 ;
  assign \fus_cu_wr__go_i$97 [3] = \wr_pick_rise$1016 ;
  assign \fus_cu_wr__go_i$97 [2] = \wr_pick_rise$1015 ;
  assign \fus_cu_wr__go_i$97 [1] = \wr_pick_rise$1014 ;
  assign \fus_cu_wr__go_i$97 [0] = \wr_pick_rise$1009 ;
  assign \wr_pick_rise$1009  = \$1012 ;
  assign \wr_pick$1005  = \$1006 ;
  assign wrflag_trap0_o_0 = \$1003 ;
  assign \addr_en$1000  = \$1001 ;
  assign \wp$997  = \$998 ;
  assign \fus_cu_wr__go_i$94 [2] = \wr_pick_rise$996 ;
  assign \fus_cu_wr__go_i$94 [1] = \wr_pick_rise$995 ;
  assign \fus_cu_wr__go_i$94 [0] = \wr_pick_rise$990 ;
  assign \wr_pick_rise$990  = \$993 ;
  assign \wr_pick$986  = \$987 ;
  assign wrflag_cr0_o_0 = \$984 ;
  assign addr_en = \$982 ;
  assign wp = \$980 ;
  assign fus_cu_wr__go_i[4] = \wr_pick_rise$979 ;
  assign fus_cu_wr__go_i[3] = \wr_pick_rise$978 ;
  assign fus_cu_wr__go_i[2] = \wr_pick_rise$977 ;
  assign fus_cu_wr__go_i[1] = \wr_pick_rise$976 ;
  assign fus_cu_wr__go_i[0] = wr_pick_rise;
  assign wr_pick_rise = \$974 ;
  assign wr_pick = \$970 ;
  assign wrpick_INT_o_i[9] = \$968 ;
  assign wrpick_INT_o_i[8] = \$966 ;
  assign wrpick_INT_o_i[7] = \$964 ;
  assign wrpick_INT_o_i[6] = \$962 ;
  assign wrpick_INT_o_i[5] = \$960 ;
  assign wrpick_INT_o_i[4] = \$958 ;
  assign wrpick_INT_o_i[3] = \$956 ;
  assign wrpick_INT_o_i[2] = \$954 ;
  assign wrpick_INT_o_i[1] = \$952 ;
  assign wrpick_INT_o_i[0] = \$950 ;
  assign wrflag_alu0_o_0 = \$948 ;
  assign spr_spr1__ren = \$946 ;
  assign spr_spr1__addr = addr_en_SPR_spr1_spr0_0[3:0];
  assign addr_en_SPR_spr1_spr0_0 = \$944 ;
  assign rp_SPR_spr1_spr0_0 = \$942 ;
  assign rdpick_SPR_spr1_i = pick_SPR_spr1_spr0_0;
  assign pick_SPR_spr1_spr0_0 = \$940 ;
  assign rdflag_SPR_spr1_0 = core_spr1_ok;
  assign fast_src1__ren = \$932 ;
  assign fast_src1__addr = \$930 ;
  assign addr_en_FAST_fast1_trap0_4 = \$922 ;
  assign rp_FAST_fast1_trap0_4 = \$920 ;
  assign pick_FAST_fast1_trap0_4 = \$918 ;
  assign addr_en_FAST_fast1_branch0_3 = \$910 ;
  assign rp_FAST_fast1_branch0_3 = \$908 ;
  assign pick_FAST_fast1_branch0_3 = \$906 ;
  assign addr_en_FAST_fast1_spr0_2 = \$898 ;
  assign rp_FAST_fast1_spr0_2 = \$896 ;
  assign pick_FAST_fast1_spr0_2 = \$894 ;
  assign addr_en_FAST_fast1_trap0_1 = \$886 ;
  assign rp_FAST_fast1_trap0_1 = \$884 ;
  assign pick_FAST_fast1_trap0_1 = \$882 ;
  assign addr_en_FAST_fast1_branch0_0 = \$874 ;
  assign rp_FAST_fast1_branch0_0 = \$872 ;
  assign rdpick_FAST_fast1_i[4] = pick_FAST_fast1_trap0_4;
  assign rdpick_FAST_fast1_i[3] = pick_FAST_fast1_branch0_3;
  assign rdpick_FAST_fast1_i[2] = pick_FAST_fast1_spr0_2;
  assign rdpick_FAST_fast1_i[1] = pick_FAST_fast1_trap0_1;
  assign rdpick_FAST_fast1_i[0] = pick_FAST_fast1_branch0_0;
  assign pick_FAST_fast1_branch0_0 = \$870 ;
  assign rdflag_FAST_fast1_1 = core_fast2_ok;
  assign rdflag_FAST_fast1_0 = core_fast1_ok;
  assign cr_src3__ren = addr_en_CR_cr_c_cr0_0[7:0];
  assign addr_en_CR_cr_c_cr0_0 = \$862 ;
  assign rp_CR_cr_c_cr0_0 = \$856 ;
  assign rdpick_CR_cr_c_i = pick_CR_cr_c_cr0_0;
  assign pick_CR_cr_c_cr0_0 = \$854 ;
  assign rdflag_CR_cr_c_0 = \core_cr_in2_ok$2 ;
  assign cr_src2__ren = addr_en_CR_cr_b_cr0_0[7:0];
  assign addr_en_CR_cr_b_cr0_0 = \$846 ;
  assign rp_CR_cr_b_cr0_0 = \$840 ;
  assign rdpick_CR_cr_b_i = pick_CR_cr_b_cr0_0;
  assign pick_CR_cr_b_cr0_0 = \$838 ;
  assign rdflag_CR_cr_b_0 = core_cr_in2_ok;
  assign cr_src1__ren = \$830 [7:0];
  assign addr_en_CR_cr_a_branch0_1 = \$827 ;
  assign rp_CR_cr_a_branch0_1 = \$821 ;
  assign \fus_cu_rd__go_i$82 [1] = dp_FAST_fast1_branch0_3;
  assign \fus_cu_rd__go_i$82 [0] = dp_FAST_fast1_branch0_0;
  assign \fus_cu_rd__go_i$82 [2] = dp_CR_cr_a_branch0_1;
  assign pick_CR_cr_a_branch0_1 = \$819 ;
  assign addr_en_CR_cr_a_cr0_0 = \$811 ;
  assign rp_CR_cr_a_cr0_0 = \$805 ;
  assign rdpick_CR_cr_a_i[1] = pick_CR_cr_a_branch0_1;
  assign rdpick_CR_cr_a_i[0] = pick_CR_cr_a_cr0_0;
  assign pick_CR_cr_a_cr0_0 = \$803 ;
  assign rdflag_CR_cr_a_0 = core_cr_in1_ok;
  assign cr_full_rd__ren = addr_en_CR_full_cr_cr0_0;
  assign addr_en_CR_full_cr_cr0_0 = \$795 ;
  assign rp_CR_full_cr_cr0_0 = \$793 ;
  assign rdpick_CR_full_cr_i = pick_CR_full_cr_cr0_0;
  assign pick_CR_full_cr_cr0_0 = \$791 ;
  assign rdflag_CR_full_cr_0 = core_core_cr_rd_ok;
  assign xer_src3__ren = addr_en_XER_xer_ov_spr0_0;
  assign addr_en_XER_xer_ov_spr0_0 = \$783 ;
  assign rp_XER_xer_ov_spr0_0 = \$781 ;
  assign rdpick_XER_xer_ov_i = pick_XER_xer_ov_spr0_0;
  assign pick_XER_xer_ov_spr0_0 = \$779 ;
  assign rdflag_XER_xer_ov_0 = \$771 ;
  assign xer_src2__ren = \$759 ;
  assign addr_en_XER_xer_ca_shiftrot0_2 = \$757 ;
  assign rp_XER_xer_ca_shiftrot0_2 = \$755 ;
  assign pick_XER_xer_ca_shiftrot0_2 = \$753 ;
  assign addr_en_XER_xer_ca_spr0_1 = \$745 ;
  assign rp_XER_xer_ca_spr0_1 = \$743 ;
  assign pick_XER_xer_ca_spr0_1 = \$741 ;
  assign addr_en_XER_xer_ca_alu0_0 = \$733 ;
  assign rp_XER_xer_ca_alu0_0 = \$731 ;
  assign rdpick_XER_xer_ca_i[2] = pick_XER_xer_ca_shiftrot0_2;
  assign rdpick_XER_xer_ca_i[1] = pick_XER_xer_ca_spr0_1;
  assign rdpick_XER_xer_ca_i[0] = pick_XER_xer_ca_alu0_0;
  assign pick_XER_xer_ca_alu0_0 = \$729 ;
  assign rdflag_XER_xer_ca_0 = \$721 ;
  assign xer_src1__ren = \$703 ;
  assign addr_en_XER_xer_so_shiftrot0_5 = \$701 ;
  assign rp_XER_xer_so_shiftrot0_5 = \$699 ;
  assign pick_XER_xer_so_shiftrot0_5 = \$697 ;
  assign addr_en_XER_xer_so_mul0_4 = \$689 ;
  assign rp_XER_xer_so_mul0_4 = \$687 ;
  assign pick_XER_xer_so_mul0_4 = \$685 ;
  assign addr_en_XER_xer_so_div0_3 = \$677 ;
  assign rp_XER_xer_so_div0_3 = \$675 ;
  assign pick_XER_xer_so_div0_3 = \$673 ;
  assign addr_en_XER_xer_so_spr0_2 = \$665 ;
  assign rp_XER_xer_so_spr0_2 = \$663 ;
  assign pick_XER_xer_so_spr0_2 = \$661 ;
  assign addr_en_XER_xer_so_logical0_1 = \$653 ;
  assign rp_XER_xer_so_logical0_1 = \$651 ;
  assign pick_XER_xer_so_logical0_1 = \$649 ;
  assign addr_en_XER_xer_so_alu0_0 = \$641 ;
  assign rp_XER_xer_so_alu0_0 = \$639 ;
  assign rdpick_XER_xer_so_i[5] = pick_XER_xer_so_shiftrot0_5;
  assign rdpick_XER_xer_so_i[4] = pick_XER_xer_so_mul0_4;
  assign rdpick_XER_xer_so_i[3] = pick_XER_xer_so_div0_3;
  assign rdpick_XER_xer_so_i[2] = pick_XER_xer_so_spr0_2;
  assign rdpick_XER_xer_so_i[1] = pick_XER_xer_so_logical0_1;
  assign rdpick_XER_xer_so_i[0] = pick_XER_xer_so_alu0_0;
  assign pick_XER_xer_so_alu0_0 = \$637 ;
  assign rdflag_XER_xer_so_0 = \$629 ;
  assign int_src1__ren = \$617 ;
  assign int_src1__addr = \$615 [4:0];
  assign addr_en_INT_rabc_ldst0_18 = \$578 ;
  assign rp_INT_rabc_ldst0_18 = \$576 ;
  assign pick_INT_rabc_ldst0_18 = \$574 ;
  assign addr_en_INT_rabc_shiftrot0_17 = \$566 ;
  assign rp_INT_rabc_shiftrot0_17 = \$564 ;
  assign pick_INT_rabc_shiftrot0_17 = \$562 ;
  assign addr_en_INT_rabc_mul0_16 = \$554 ;
  assign rp_INT_rabc_mul0_16 = \$552 ;
  assign pick_INT_rabc_mul0_16 = \$550 ;
  assign addr_en_INT_rabc_div0_15 = \$542 ;
  assign rp_INT_rabc_div0_15 = \$540 ;
  assign pick_INT_rabc_div0_15 = \$538 ;
  assign addr_en_INT_rabc_spr0_14 = \$530 ;
  assign rp_INT_rabc_spr0_14 = \$528 ;
  assign \fus_cu_rd__go_i$66 [1] = dp_SPR_spr1_spr0_0;
  assign \fus_cu_rd__go_i$66 [2] = dp_FAST_fast1_spr0_2;
  assign \fus_cu_rd__go_i$66 [4] = dp_XER_xer_ov_spr0_0;
  assign \fus_cu_rd__go_i$66 [5] = dp_XER_xer_ca_spr0_1;
  assign \fus_cu_rd__go_i$66 [3] = dp_XER_xer_so_spr0_2;
  assign \fus_cu_rd__go_i$66 [0] = dp_INT_rabc_spr0_14;
  assign pick_INT_rabc_spr0_14 = \$526 ;
  assign addr_en_INT_rabc_logical0_13 = \$518 ;
  assign rp_INT_rabc_logical0_13 = \$516 ;
  assign pick_INT_rabc_logical0_13 = \$514 ;
  assign addr_en_INT_rabc_trap0_12 = \$506 ;
  assign rp_INT_rabc_trap0_12 = \$504 ;
  assign pick_INT_rabc_trap0_12 = \$502 ;
  assign addr_en_INT_rabc_cr0_11 = \$494 ;
  assign rp_INT_rabc_cr0_11 = \$492 ;
  assign pick_INT_rabc_cr0_11 = \$490 ;
  assign addr_en_INT_rabc_alu0_10 = \$482 ;
  assign rp_INT_rabc_alu0_10 = \$480 ;
  assign pick_INT_rabc_alu0_10 = \$478 ;
  assign addr_en_INT_rabc_ldst0_9 = \$470 ;
  assign rp_INT_rabc_ldst0_9 = \$468 ;
  assign pick_INT_rabc_ldst0_9 = \$466 ;
  assign addr_en_INT_rabc_shiftrot0_8 = \$458 ;
  assign rp_INT_rabc_shiftrot0_8 = \$456 ;
  assign pick_INT_rabc_shiftrot0_8 = \$454 ;
  assign addr_en_INT_rabc_ldst0_7 = \$446 ;
  assign rp_INT_rabc_ldst0_7 = \$444 ;
  assign \fus_cu_rd__go_i$59 [0] = dp_INT_rabc_ldst0_18;
  assign \fus_cu_rd__go_i$59 [2] = dp_INT_rabc_ldst0_9;
  assign \fus_cu_rd__go_i$59 [1] = dp_INT_rabc_ldst0_7;
  assign pick_INT_rabc_ldst0_7 = \$442 ;
  assign addr_en_INT_rabc_shiftrot0_6 = \$434 ;
  assign rp_INT_rabc_shiftrot0_6 = \$432 ;
  assign \fus_cu_rd__go_i$56 [4] = dp_XER_xer_ca_shiftrot0_2;
  assign \fus_cu_rd__go_i$56 [3] = dp_XER_xer_so_shiftrot0_5;
  assign \fus_cu_rd__go_i$56 [0] = dp_INT_rabc_shiftrot0_17;
  assign \fus_cu_rd__go_i$56 [2] = dp_INT_rabc_shiftrot0_8;
  assign \fus_cu_rd__go_i$56 [1] = dp_INT_rabc_shiftrot0_6;
  assign pick_INT_rabc_shiftrot0_6 = \$430 ;
  assign addr_en_INT_rabc_mul0_5 = \$422 ;
  assign rp_INT_rabc_mul0_5 = \$420 ;
  assign \fus_cu_rd__go_i$53 [2] = dp_XER_xer_so_mul0_4;
  assign \fus_cu_rd__go_i$53 [0] = dp_INT_rabc_mul0_16;
  assign \fus_cu_rd__go_i$53 [1] = dp_INT_rabc_mul0_5;
  assign pick_INT_rabc_mul0_5 = \$418 ;
  assign addr_en_INT_rabc_div0_4 = \$410 ;
  assign rp_INT_rabc_div0_4 = \$408 ;
  assign \fus_cu_rd__go_i$50 [2] = dp_XER_xer_so_div0_3;
  assign \fus_cu_rd__go_i$50 [0] = dp_INT_rabc_div0_15;
  assign \fus_cu_rd__go_i$50 [1] = dp_INT_rabc_div0_4;
  assign pick_INT_rabc_div0_4 = \$406 ;
  assign addr_en_INT_rabc_logical0_3 = \$398 ;
  assign rp_INT_rabc_logical0_3 = \$396 ;
  assign \fus_cu_rd__go_i$47 [2] = dp_XER_xer_so_logical0_1;
  assign \fus_cu_rd__go_i$47 [0] = dp_INT_rabc_logical0_13;
  assign \fus_cu_rd__go_i$47 [1] = dp_INT_rabc_logical0_3;
  assign pick_INT_rabc_logical0_3 = \$394 ;
  assign addr_en_INT_rabc_trap0_2 = \$386 ;
  assign rp_INT_rabc_trap0_2 = \$384 ;
  assign \fus_cu_rd__go_i$44 [3] = dp_FAST_fast1_trap0_4;
  assign \fus_cu_rd__go_i$44 [2] = dp_FAST_fast1_trap0_1;
  assign \fus_cu_rd__go_i$44 [0] = dp_INT_rabc_trap0_12;
  assign \fus_cu_rd__go_i$44 [1] = dp_INT_rabc_trap0_2;
  assign pick_INT_rabc_trap0_2 = \$382 ;
  assign addr_en_INT_rabc_cr0_1 = \$374 ;
  assign rp_INT_rabc_cr0_1 = \$372 ;
  assign \fus_cu_rd__go_i$41 [5] = dp_CR_cr_c_cr0_0;
  assign \fus_cu_rd__go_i$41 [4] = dp_CR_cr_b_cr0_0;
  assign \fus_cu_rd__go_i$41 [3] = dp_CR_cr_a_cr0_0;
  assign \fus_cu_rd__go_i$41 [2] = dp_CR_full_cr_cr0_0;
  assign \fus_cu_rd__go_i$41 [0] = dp_INT_rabc_cr0_11;
  assign \fus_cu_rd__go_i$41 [1] = dp_INT_rabc_cr0_1;
  assign pick_INT_rabc_cr0_1 = \$370 ;
  assign addr_en_INT_rabc_alu0_0 = \$362 ;
  assign rp_INT_rabc_alu0_0 = \$360 ;
  assign fus_cu_rd__go_i[3] = dp_XER_xer_ca_alu0_0;
  assign fus_cu_rd__go_i[2] = dp_XER_xer_so_alu0_0;
  assign fus_cu_rd__go_i[0] = dp_INT_rabc_alu0_10;
  assign fus_cu_rd__go_i[1] = dp_INT_rabc_alu0_0;
  assign rdpick_INT_rabc_i[18] = pick_INT_rabc_ldst0_18;
  assign rdpick_INT_rabc_i[17] = pick_INT_rabc_shiftrot0_17;
  assign rdpick_INT_rabc_i[16] = pick_INT_rabc_mul0_16;
  assign rdpick_INT_rabc_i[15] = pick_INT_rabc_div0_15;
  assign rdpick_INT_rabc_i[14] = pick_INT_rabc_spr0_14;
  assign rdpick_INT_rabc_i[13] = pick_INT_rabc_logical0_13;
  assign rdpick_INT_rabc_i[12] = pick_INT_rabc_trap0_12;
  assign rdpick_INT_rabc_i[11] = pick_INT_rabc_cr0_11;
  assign rdpick_INT_rabc_i[10] = pick_INT_rabc_alu0_10;
  assign rdpick_INT_rabc_i[9] = pick_INT_rabc_ldst0_9;
  assign rdpick_INT_rabc_i[8] = pick_INT_rabc_shiftrot0_8;
  assign rdpick_INT_rabc_i[7] = pick_INT_rabc_ldst0_7;
  assign rdpick_INT_rabc_i[6] = pick_INT_rabc_shiftrot0_6;
  assign rdpick_INT_rabc_i[5] = pick_INT_rabc_mul0_5;
  assign rdpick_INT_rabc_i[4] = pick_INT_rabc_div0_4;
  assign rdpick_INT_rabc_i[3] = pick_INT_rabc_logical0_3;
  assign rdpick_INT_rabc_i[2] = pick_INT_rabc_trap0_2;
  assign rdpick_INT_rabc_i[1] = pick_INT_rabc_cr0_1;
  assign rdpick_INT_rabc_i[0] = pick_INT_rabc_alu0_0;
  assign pick_INT_rabc_alu0_0 = \$358 ;
  assign rdflag_INT_rabc_2 = core_reg1_ok;
  assign rdflag_INT_rabc_1 = core_reg3_ok;
  assign rdflag_INT_rabc_0 = core_reg2_ok;
  assign en_ldst0 = \$217 ;
  assign en_shiftrot0 = \$213 ;
  assign en_mul0 = \$209 ;
  assign en_div0 = \$205 ;
  assign en_spr0 = \$201 ;
  assign en_logical0 = \$197 ;
  assign en_trap0 = \$193 ;
  assign en_branch0 = \$189 ;
  assign en_cr0 = \$185 ;
  assign fu_enable[9] = en_ldst0;
  assign fu_enable[8] = en_shiftrot0;
  assign fu_enable[7] = en_mul0;
  assign fu_enable[6] = en_div0;
  assign fu_enable[5] = en_spr0;
  assign fu_enable[4] = en_logical0;
  assign fu_enable[3] = en_trap0;
  assign fu_enable[2] = en_branch0;
  assign fu_enable[1] = en_cr0;
  assign fu_enable[0] = en_alu0;
  assign en_alu0 = \$181 ;
  assign dec_LDST_sv_a_nz = sv_a_nz;
  assign dec_LDST_bigendian = bigendian_i;
  assign dec_LDST_raw_opcode_in = raw_insn_i;
  assign \sv_a_nz$180  = sv_a_nz;
  assign dec_SHIFT_ROT_bigendian = bigendian_i;
  assign dec_SHIFT_ROT_raw_opcode_in = raw_insn_i;
  assign \sv_a_nz$179  = sv_a_nz;
  assign dec_MUL_bigendian = bigendian_i;
  assign dec_MUL_raw_opcode_in = raw_insn_i;
  assign dec_DIV_sv_a_nz = sv_a_nz;
  assign dec_DIV_bigendian = bigendian_i;
  assign dec_DIV_raw_opcode_in = raw_insn_i;
  assign \sv_a_nz$178  = sv_a_nz;
  assign dec_SPR_bigendian = bigendian_i;
  assign dec_SPR_raw_opcode_in = raw_insn_i;
  assign dec_LOGICAL_sv_a_nz = sv_a_nz;
  assign dec_LOGICAL_bigendian = bigendian_i;
  assign dec_LOGICAL_raw_opcode_in = raw_insn_i;
  assign \sv_a_nz$177  = sv_a_nz;
  assign dec_BRANCH_bigendian = bigendian_i;
  assign dec_BRANCH_raw_opcode_in = raw_insn_i;
  assign \sv_a_nz$176  = sv_a_nz;
  assign dec_CR_bigendian = bigendian_i;
  assign dec_CR_raw_opcode_in = raw_insn_i;
  assign dec_ALU_sv_a_nz = sv_a_nz;
  assign dec_ALU_bigendian = bigendian_i;
  assign dec_ALU_raw_opcode_in = raw_insn_i;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:48921.1-49554.10" *)
module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_rd__ren, src1__data_o, src1__ren, src2__data_o, src2__ren, src3__data_o, src3__ren, full_wr__data_i, full_wr__wen, data_i, wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:48922.7-48922.20" *)
  reg _00_;
  (* src = "libresoc.v:49468.3-49476.6" *)
  reg [7:0] _01_;
  (* src = "libresoc.v:49304.3-49305.43" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:49250.13-49250.35" *)
  reg [7:0] _03_;
  (* src = "libresoc.v:49487.3-49495.6" *)
  reg [7:0] _04_;
  (* src = "libresoc.v:49302.3-49303.43" *)
  reg [7:0] _05_;
  (* src = "libresoc.v:49254.13-49254.35" *)
  reg [7:0] _06_;
  (* src = "libresoc.v:49506.3-49514.6" *)
  reg [7:0] _07_;
  (* src = "libresoc.v:49306.3-49307.35" *)
  reg [7:0] _08_;
  (* src = "libresoc.v:49515.3-49524.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:49477.3-49486.6" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:49496.3-49505.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:49468.3-49476.6" *)
  reg [7:0] _12_;
  (* src = "libresoc.v:49487.3-49495.6" *)
  reg [7:0] _13_;
  (* src = "libresoc.v:49506.3-49514.6" *)
  reg [7:0] _14_;
  (* src = "libresoc.v:49248.13-49248.30" *)
  reg [7:0] _15_;
  (* src = "libresoc.v:49515.3-49524.6" *)
  reg [3:0] _16_;
  (* src = "libresoc.v:49477.3-49486.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:49496.3-49505.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:49278.17-49278.125" *)
  wire [3:0] _19_;
  (* src = "libresoc.v:49279.18-49279.126" *)
  wire [3:0] _20_;
  (* src = "libresoc.v:49280.18-49280.96" *)
  wire [3:0] _21_;
  (* src = "libresoc.v:49281.18-49281.96" *)
  wire [3:0] _22_;
  (* src = "libresoc.v:49284.18-49284.126" *)
  wire [3:0] _23_;
  (* src = "libresoc.v:49285.18-49285.126" *)
  wire [3:0] _24_;
  (* src = "libresoc.v:49286.18-49286.97" *)
  wire [3:0] _25_;
  (* src = "libresoc.v:49287.18-49287.126" *)
  wire [3:0] _26_;
  (* src = "libresoc.v:49288.18-49288.126" *)
  wire [3:0] _27_;
  (* src = "libresoc.v:49289.18-49289.97" *)
  wire [3:0] _28_;
  (* src = "libresoc.v:49290.18-49290.97" *)
  wire [3:0] _29_;
  (* src = "libresoc.v:49292.18-49292.126" *)
  wire [3:0] _30_;
  (* src = "libresoc.v:49293.17-49293.125" *)
  wire [3:0] _31_;
  (* src = "libresoc.v:49294.18-49294.126" *)
  wire [3:0] _32_;
  (* src = "libresoc.v:49295.18-49295.97" *)
  wire [3:0] _33_;
  (* src = "libresoc.v:49296.18-49296.126" *)
  wire [3:0] _34_;
  (* src = "libresoc.v:49297.18-49297.126" *)
  wire [3:0] _35_;
  (* src = "libresoc.v:49298.18-49298.97" *)
  wire [3:0] _36_;
  (* src = "libresoc.v:49299.18-49299.97" *)
  wire [3:0] _37_;
  (* src = "libresoc.v:49300.17-49300.125" *)
  wire [3:0] _38_;
  (* src = "libresoc.v:49301.17-49301.94" *)
  wire [3:0] _39_;
  (* src = "libresoc.v:49282.18-49282.100" *)
  wire _40_;
  (* src = "libresoc.v:49283.17-49283.95" *)
  wire _41_;
  (* src = "libresoc.v:49291.18-49291.100" *)
  wire _42_;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$37 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [3:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [3:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] \data_i$52 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [31:0] full_rd2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] full_rd2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [31:0] full_rd__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] full_rd__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [31:0] full_wr__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] full_wr__wen;
  (* src = "libresoc.v:48922.7-48922.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_dest10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_dest10__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_dest20__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_dest20__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_r0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_r0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_r20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_r20__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_src10__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src10__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_src20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src20__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_src30__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src30__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_0_w0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_w0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_dest11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_dest11__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_dest21__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_dest21__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_r1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_r1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_r21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_r21__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_src11__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src11__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_src21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src21__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_src31__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src31__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_1_w1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_w1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_dest12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_dest12__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_dest22__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_dest22__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_r22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_r22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_r2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_r2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_src12__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src12__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_src22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_src32__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src32__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_2_w2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_w2__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_dest13__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_dest13__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_dest23__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_dest23__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_r23__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_r23__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_r3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_r3__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_src13__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_src13__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_src23__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_src23__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_src33__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_src33__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_3_w3__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_3_w3__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_dest14__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_dest14__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_dest24__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_dest24__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_r24__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_r24__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_r4__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_r4__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_src14__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_src14__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_src24__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_src24__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_src34__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_src34__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_4_w4__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_4_w4__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_dest15__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_dest15__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_dest25__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_dest25__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_r25__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_r25__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_r5__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_r5__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_src15__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_src15__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_src25__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_src25__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_src35__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_src35__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_5_w5__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_5_w5__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_dest16__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_dest16__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_dest26__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_dest26__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_r26__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_r26__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_r6__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_r6__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_src16__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_src16__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_src26__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_src26__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_src36__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_src36__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_6_w6__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_6_w6__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_dest17__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_dest17__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_dest27__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_dest27__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_r27__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_r27__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_r7__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_r7__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_src17__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_src17__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_src27__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_src27__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_src37__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_src37__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [3:0] reg_7_w7__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_7_w7__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] \ren_delay$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] \ren_delay$17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] \ren_delay$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] \ren_delay$34$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [7:0] \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src1__data_o;
  reg [3:0] src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] src1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src2__data_o;
  reg [3:0] src2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] src2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src3__data_o;
  reg [3:0] src3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] src3__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [7:0] wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [7:0] \wen$51 ;
  assign _19_ = reg_4_src14__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src15__data_o;
  assign _20_ = reg_6_src16__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src17__data_o;
  assign _21_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$11 ;
  assign _22_ = \$7  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$13 ;
  assign _23_ = reg_0_src20__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src21__data_o;
  assign _24_ = reg_2_src22__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src23__data_o;
  assign _25_ = \$20  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$22 ;
  assign _26_ = reg_4_src24__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src25__data_o;
  assign _27_ = reg_6_src26__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src27__data_o;
  assign _28_ = \$26  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$28 ;
  assign _29_ = \$24  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$30 ;
  assign _30_ = reg_0_src30__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src31__data_o;
  assign _31_ = reg_0_src10__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_1_src11__data_o;
  assign _32_ = reg_2_src32__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src33__data_o;
  assign _33_ = \$37  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$39 ;
  assign _34_ = reg_4_src34__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_5_src35__data_o;
  assign _35_ = reg_6_src36__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_7_src37__data_o;
  assign _36_ = \$43  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$45 ;
  assign _37_ = \$41  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$47 ;
  assign _38_ = reg_2_src12__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_3_src13__data_o;
  assign _39_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$5 ;
  assign _40_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$17 ;
  assign _41_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay;
  assign _42_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$34 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49308.9-49327.4" *)
  reg_0 reg_0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest10__data_i(reg_0_dest10__data_i),
    .dest10__wen(reg_0_dest10__wen),
    .dest20__data_i(reg_0_dest20__data_i),
    .dest20__wen(reg_0_dest20__wen),
    .r0__data_o(reg_0_r0__data_o),
    .r0__ren(reg_0_r0__ren),
    .r20__data_o(reg_0_r20__data_o),
    .r20__ren(reg_0_r20__ren),
    .src10__data_o(reg_0_src10__data_o),
    .src10__ren(reg_0_src10__ren),
    .src20__data_o(reg_0_src20__data_o),
    .src20__ren(reg_0_src20__ren),
    .src30__data_o(reg_0_src30__data_o),
    .src30__ren(reg_0_src30__ren),
    .w0__data_i(reg_0_w0__data_i),
    .w0__wen(reg_0_w0__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49328.9-49347.4" *)
  reg_1 reg_1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest11__data_i(reg_1_dest11__data_i),
    .dest11__wen(reg_1_dest11__wen),
    .dest21__data_i(reg_1_dest21__data_i),
    .dest21__wen(reg_1_dest21__wen),
    .r1__data_o(reg_1_r1__data_o),
    .r1__ren(reg_1_r1__ren),
    .r21__data_o(reg_1_r21__data_o),
    .r21__ren(reg_1_r21__ren),
    .src11__data_o(reg_1_src11__data_o),
    .src11__ren(reg_1_src11__ren),
    .src21__data_o(reg_1_src21__data_o),
    .src21__ren(reg_1_src21__ren),
    .src31__data_o(reg_1_src31__data_o),
    .src31__ren(reg_1_src31__ren),
    .w1__data_i(reg_1_w1__data_i),
    .w1__wen(reg_1_w1__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49348.9-49367.4" *)
  reg_2 reg_2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest12__data_i(reg_2_dest12__data_i),
    .dest12__wen(reg_2_dest12__wen),
    .dest22__data_i(reg_2_dest22__data_i),
    .dest22__wen(reg_2_dest22__wen),
    .r22__data_o(reg_2_r22__data_o),
    .r22__ren(reg_2_r22__ren),
    .r2__data_o(reg_2_r2__data_o),
    .r2__ren(reg_2_r2__ren),
    .src12__data_o(reg_2_src12__data_o),
    .src12__ren(reg_2_src12__ren),
    .src22__data_o(reg_2_src22__data_o),
    .src22__ren(reg_2_src22__ren),
    .src32__data_o(reg_2_src32__data_o),
    .src32__ren(reg_2_src32__ren),
    .w2__data_i(reg_2_w2__data_i),
    .w2__wen(reg_2_w2__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49368.9-49387.4" *)
  reg_3 reg_3 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest13__data_i(reg_3_dest13__data_i),
    .dest13__wen(reg_3_dest13__wen),
    .dest23__data_i(reg_3_dest23__data_i),
    .dest23__wen(reg_3_dest23__wen),
    .r23__data_o(reg_3_r23__data_o),
    .r23__ren(reg_3_r23__ren),
    .r3__data_o(reg_3_r3__data_o),
    .r3__ren(reg_3_r3__ren),
    .src13__data_o(reg_3_src13__data_o),
    .src13__ren(reg_3_src13__ren),
    .src23__data_o(reg_3_src23__data_o),
    .src23__ren(reg_3_src23__ren),
    .src33__data_o(reg_3_src33__data_o),
    .src33__ren(reg_3_src33__ren),
    .w3__data_i(reg_3_w3__data_i),
    .w3__wen(reg_3_w3__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49388.9-49407.4" *)
  reg_4 reg_4 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest14__data_i(reg_4_dest14__data_i),
    .dest14__wen(reg_4_dest14__wen),
    .dest24__data_i(reg_4_dest24__data_i),
    .dest24__wen(reg_4_dest24__wen),
    .r24__data_o(reg_4_r24__data_o),
    .r24__ren(reg_4_r24__ren),
    .r4__data_o(reg_4_r4__data_o),
    .r4__ren(reg_4_r4__ren),
    .src14__data_o(reg_4_src14__data_o),
    .src14__ren(reg_4_src14__ren),
    .src24__data_o(reg_4_src24__data_o),
    .src24__ren(reg_4_src24__ren),
    .src34__data_o(reg_4_src34__data_o),
    .src34__ren(reg_4_src34__ren),
    .w4__data_i(reg_4_w4__data_i),
    .w4__wen(reg_4_w4__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49408.9-49427.4" *)
  reg_5 reg_5 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest15__data_i(reg_5_dest15__data_i),
    .dest15__wen(reg_5_dest15__wen),
    .dest25__data_i(reg_5_dest25__data_i),
    .dest25__wen(reg_5_dest25__wen),
    .r25__data_o(reg_5_r25__data_o),
    .r25__ren(reg_5_r25__ren),
    .r5__data_o(reg_5_r5__data_o),
    .r5__ren(reg_5_r5__ren),
    .src15__data_o(reg_5_src15__data_o),
    .src15__ren(reg_5_src15__ren),
    .src25__data_o(reg_5_src25__data_o),
    .src25__ren(reg_5_src25__ren),
    .src35__data_o(reg_5_src35__data_o),
    .src35__ren(reg_5_src35__ren),
    .w5__data_i(reg_5_w5__data_i),
    .w5__wen(reg_5_w5__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49428.9-49447.4" *)
  reg_6 reg_6 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest16__data_i(reg_6_dest16__data_i),
    .dest16__wen(reg_6_dest16__wen),
    .dest26__data_i(reg_6_dest26__data_i),
    .dest26__wen(reg_6_dest26__wen),
    .r26__data_o(reg_6_r26__data_o),
    .r26__ren(reg_6_r26__ren),
    .r6__data_o(reg_6_r6__data_o),
    .r6__ren(reg_6_r6__ren),
    .src16__data_o(reg_6_src16__data_o),
    .src16__ren(reg_6_src16__ren),
    .src26__data_o(reg_6_src26__data_o),
    .src26__ren(reg_6_src26__ren),
    .src36__data_o(reg_6_src36__data_o),
    .src36__ren(reg_6_src36__ren),
    .w6__data_i(reg_6_w6__data_i),
    .w6__wen(reg_6_w6__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:49448.9-49467.4" *)
  reg_7 reg_7 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest17__data_i(reg_7_dest17__data_i),
    .dest17__wen(reg_7_dest17__wen),
    .dest27__data_i(reg_7_dest27__data_i),
    .dest27__wen(reg_7_dest27__wen),
    .r27__data_o(reg_7_r27__data_o),
    .r27__ren(reg_7_r27__ren),
    .r7__data_o(reg_7_r7__data_o),
    .r7__ren(reg_7_r7__ren),
    .src17__data_o(reg_7_src17__data_o),
    .src17__ren(reg_7_src17__ren),
    .src27__data_o(reg_7_src27__data_o),
    .src27__ren(reg_7_src27__ren),
    .src37__data_o(reg_7_src37__data_o),
    .src37__ren(reg_7_src37__ren),
    .w7__data_i(reg_7_w7__data_i),
    .w7__wen(reg_7_w7__wen)
  );
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      \ren_delay$17  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      \ren_delay$34  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = \ren_delay$34$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$34  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \ren_delay$17$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$17  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _12_;
    (* src = "libresoc.v:49469.5-49469.29" *)
    casez (\initial )
      /* src = "libresoc.v:49469.9-49469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 8'h00;
        end
      default:
          _12_ = src2__ren;
    endcase
  end
  always @* begin
      \ren_delay$17$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _17_;
    (* src = "libresoc.v:49478.5-49478.29" *)
    casez (\initial )
      /* src = "libresoc.v:49478.9-49478.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$18 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = \$32 ;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      src2__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:49488.5-49488.29" *)
    casez (\initial )
      /* src = "libresoc.v:49488.9-49488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = 8'h00;
        end
      default:
          _13_ = src3__ren;
    endcase
  end
  always @* begin
      \ren_delay$34$next  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _18_;
    (* src = "libresoc.v:49497.5-49497.29" *)
    casez (\initial )
      /* src = "libresoc.v:49497.9-49497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$35 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = \$49 ;
        end
      default:
          _18_ = 4'h0;
    endcase
  end
  always @* begin
      src3__data_o <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _14_;
    (* src = "libresoc.v:49507.5-49507.29" *)
    casez (\initial )
      /* src = "libresoc.v:49507.9-49507.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = 8'h00;
        end
      default:
          _14_ = src1__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _16_;
    (* src = "libresoc.v:49516.5-49516.29" *)
    casez (\initial )
      /* src = "libresoc.v:49516.9-49516.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = \$15 ;
        end
      default:
          _16_ = 4'h0;
    endcase
  end
  always @* begin
      src1__data_o <= _09_;
  end
  assign \$9  = _19_;
  assign \$11  = _20_;
  assign \$13  = _21_;
  assign \$15  = _22_;
  assign \$18  = _40_;
  assign \$1  = _41_;
  assign \$20  = _23_;
  assign \$22  = _24_;
  assign \$24  = _25_;
  assign \$26  = _26_;
  assign \$28  = _27_;
  assign \$30  = _28_;
  assign \$32  = _29_;
  assign \$35  = _42_;
  assign \$37  = _30_;
  assign \$3  = _31_;
  assign \$39  = _32_;
  assign \$41  = _33_;
  assign \$43  = _34_;
  assign \$45  = _35_;
  assign \$47  = _36_;
  assign \$49  = _37_;
  assign \$5  = _38_;
  assign \$7  = _39_;
  assign \wen$51  = 8'h00;
  assign \data_i$52  = 4'h0;
  assign { reg_7_w7__wen, reg_6_w6__wen, reg_5_w5__wen, reg_4_w4__wen, reg_3_w3__wen, reg_2_w2__wen, reg_1_w1__wen, reg_0_w0__wen } = full_wr__wen;
  assign { reg_7_w7__data_i, reg_6_w6__data_i, reg_5_w5__data_i, reg_4_w4__data_i, reg_3_w3__data_i, reg_2_w2__data_i, reg_1_w1__data_i, reg_0_w0__data_i } = full_wr__data_i;
  assign { reg_7_r27__ren, reg_6_r26__ren, reg_5_r25__ren, reg_4_r24__ren, reg_3_r23__ren, reg_2_r22__ren, reg_1_r21__ren, reg_0_r20__ren } = full_rd2__ren;
  assign full_rd2__data_o = { reg_7_r27__data_o, reg_6_r26__data_o, reg_5_r25__data_o, reg_4_r24__data_o, reg_3_r23__data_o, reg_2_r22__data_o, reg_1_r21__data_o, reg_0_r20__data_o };
  assign { reg_7_r7__ren, reg_6_r6__ren, reg_5_r5__ren, reg_4_r4__ren, reg_3_r3__ren, reg_2_r2__ren, reg_1_r1__ren, reg_0_r0__ren } = full_rd__ren;
  assign full_rd__data_o = { reg_7_r7__data_o, reg_6_r6__data_o, reg_5_r5__data_o, reg_4_r4__data_o, reg_3_r3__data_o, reg_2_r2__data_o, reg_1_r1__data_o, reg_0_r0__data_o };
  assign reg_7_dest27__data_i = 4'h0;
  assign reg_6_dest26__data_i = 4'h0;
  assign reg_5_dest25__data_i = 4'h0;
  assign reg_4_dest24__data_i = 4'h0;
  assign reg_3_dest23__data_i = 4'h0;
  assign reg_2_dest22__data_i = 4'h0;
  assign reg_1_dest21__data_i = 4'h0;
  assign reg_0_dest20__data_i = 4'h0;
  assign { reg_7_dest27__wen, reg_6_dest26__wen, reg_5_dest25__wen, reg_4_dest24__wen, reg_3_dest23__wen, reg_2_dest22__wen, reg_1_dest21__wen, reg_0_dest20__wen } = 8'h00;
  assign reg_7_dest17__data_i = data_i;
  assign reg_6_dest16__data_i = data_i;
  assign reg_5_dest15__data_i = data_i;
  assign reg_4_dest14__data_i = data_i;
  assign reg_3_dest13__data_i = data_i;
  assign reg_2_dest12__data_i = data_i;
  assign reg_1_dest11__data_i = data_i;
  assign reg_0_dest10__data_i = data_i;
  assign { reg_7_dest17__wen, reg_6_dest16__wen, reg_5_dest15__wen, reg_4_dest14__wen, reg_3_dest13__wen, reg_2_dest12__wen, reg_1_dest11__wen, reg_0_dest10__wen } = wen;
  assign { reg_7_src37__ren, reg_6_src36__ren, reg_5_src35__ren, reg_4_src34__ren, reg_3_src33__ren, reg_2_src32__ren, reg_1_src31__ren, reg_0_src30__ren } = src3__ren;
  assign { reg_7_src27__ren, reg_6_src26__ren, reg_5_src25__ren, reg_4_src24__ren, reg_3_src23__ren, reg_2_src22__ren, reg_1_src21__ren, reg_0_src20__ren } = src2__ren;
  assign { reg_7_src17__ren, reg_6_src16__ren, reg_5_src15__ren, reg_4_src14__ren, reg_3_src13__ren, reg_2_src12__ren, reg_1_src11__ren, reg_0_src10__ren } = src1__ren;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:49558.1-50615.10" *)
module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, src5_i, src6_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, full_cr_ok, dest2_o, cr_a_ok, dest3_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:50216.3-50217.25" *)
  reg _000_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [13:0] _001_;
  (* src = "libresoc.v:50188.3-50189.61" *)
  reg [13:0] _002_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [31:0] _003_;
  (* src = "libresoc.v:50190.3-50191.55" *)
  reg [31:0] _004_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [6:0] _005_;
  (* src = "libresoc.v:50186.3-50187.65" *)
  reg [6:0] _006_;
  (* src = "libresoc.v:50214.3-50215.39" *)
  reg _007_;
  (* src = "libresoc.v:50536.3-50544.6" *)
  reg _008_;
  (* src = "libresoc.v:50158.3-50159.39" *)
  reg _009_;
  (* src = "libresoc.v:50527.3-50535.6" *)
  reg _010_;
  (* src = "libresoc.v:50160.3-50161.43" *)
  reg _011_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg [63:0] _012_;
  (* src = "libresoc.v:50182.3-50183.37" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg _014_;
  (* src = "libresoc.v:50184.3-50185.43" *)
  reg _015_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg [31:0] _016_;
  (* src = "libresoc.v:50178.3-50179.49" *)
  reg [31:0] _017_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg _018_;
  (* src = "libresoc.v:50180.3-50181.55" *)
  reg _019_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg [3:0] _020_;
  (* src = "libresoc.v:50174.3-50175.43" *)
  reg [3:0] _021_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg _022_;
  (* src = "libresoc.v:50176.3-50177.49" *)
  reg _023_;
  (* src = "libresoc.v:50545.3-50554.6" *)
  reg [63:0] _024_;
  (* src = "libresoc.v:50555.3-50564.6" *)
  reg [31:0] _025_;
  (* src = "libresoc.v:50565.3-50574.6" *)
  reg [3:0] _026_;
  (* src = "libresoc.v:49559.7-49559.20" *)
  reg _027_;
  (* src = "libresoc.v:50344.3-50352.6" *)
  reg _028_;
  (* src = "libresoc.v:50200.3-50201.39" *)
  reg _029_;
  (* src = "libresoc.v:50335.3-50343.6" *)
  reg _030_;
  (* src = "libresoc.v:50202.3-50203.39" *)
  reg _031_;
  (* src = "libresoc.v:50575.3-50583.6" *)
  reg [2:0] _032_;
  (* src = "libresoc.v:50212.3-50213.37" *)
  reg [2:0] _033_;
  (* src = "libresoc.v:50289.3-50298.6" *)
  reg _034_;
  (* src = "libresoc.v:50380.3-50388.6" *)
  reg [2:0] _035_;
  (* src = "libresoc.v:50192.3-50193.39" *)
  reg [2:0] _036_;
  (* src = "libresoc.v:50371.3-50379.6" *)
  reg [2:0] _037_;
  (* src = "libresoc.v:50194.3-50195.39" *)
  reg [2:0] _038_;
  (* src = "libresoc.v:50308.3-50316.6" *)
  reg _039_;
  (* src = "libresoc.v:50208.3-50209.41" *)
  reg _040_;
  (* src = "libresoc.v:50299.3-50307.6" *)
  reg _041_;
  (* src = "libresoc.v:50210.3-50211.41" *)
  reg _042_;
  (* src = "libresoc.v:50326.3-50334.6" *)
  reg _043_;
  (* src = "libresoc.v:50204.3-50205.39" *)
  reg _044_;
  (* src = "libresoc.v:50317.3-50325.6" *)
  reg _045_;
  (* src = "libresoc.v:50206.3-50207.39" *)
  reg _046_;
  (* src = "libresoc.v:50362.3-50370.6" *)
  reg [5:0] _047_;
  (* src = "libresoc.v:50196.3-50197.39" *)
  reg [5:0] _048_;
  (* src = "libresoc.v:50353.3-50361.6" *)
  reg [5:0] _049_;
  (* src = "libresoc.v:50198.3-50199.39" *)
  reg [5:0] _050_;
  (* src = "libresoc.v:50467.3-50476.6" *)
  reg [63:0] _051_;
  (* src = "libresoc.v:50172.3-50173.29" *)
  reg [63:0] _052_;
  (* src = "libresoc.v:50477.3-50486.6" *)
  reg [63:0] _053_;
  (* src = "libresoc.v:50170.3-50171.29" *)
  reg [63:0] _054_;
  (* src = "libresoc.v:50487.3-50496.6" *)
  reg [31:0] _055_;
  (* src = "libresoc.v:50168.3-50169.29" *)
  reg [31:0] _056_;
  (* src = "libresoc.v:50497.3-50506.6" *)
  reg [3:0] _057_;
  (* src = "libresoc.v:50166.3-50167.29" *)
  reg [3:0] _058_;
  (* src = "libresoc.v:50507.3-50516.6" *)
  reg [3:0] _059_;
  (* src = "libresoc.v:50164.3-50165.29" *)
  reg [3:0] _060_;
  (* src = "libresoc.v:50517.3-50526.6" *)
  reg [3:0] _061_;
  (* src = "libresoc.v:50162.3-50163.29" *)
  reg [3:0] _062_;
  (* src = "libresoc.v:49677.7-49677.24" *)
  reg _063_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [13:0] _064_;
  (* src = "libresoc.v:49708.14-49708.47" *)
  reg [13:0] _065_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [31:0] _066_;
  (* src = "libresoc.v:49712.14-49712.41" *)
  reg [31:0] _067_;
  (* src = "libresoc.v:50389.3-50400.6" *)
  reg [6:0] _068_;
  (* src = "libresoc.v:49791.13-49791.45" *)
  reg [6:0] _069_;
  (* src = "libresoc.v:49815.7-49815.26" *)
  reg _070_;
  (* src = "libresoc.v:50536.3-50544.6" *)
  reg _071_;
  (* src = "libresoc.v:49823.7-49823.25" *)
  reg _072_;
  (* src = "libresoc.v:50527.3-50535.6" *)
  reg _073_;
  (* src = "libresoc.v:49835.7-49835.27" *)
  reg _074_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg [63:0] _075_;
  (* src = "libresoc.v:49869.14-49869.47" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg _077_;
  (* src = "libresoc.v:49873.7-49873.27" *)
  reg _078_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg [31:0] _079_;
  (* src = "libresoc.v:49877.14-49877.38" *)
  reg [31:0] _080_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg _081_;
  (* src = "libresoc.v:49881.7-49881.33" *)
  reg _082_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg [3:0] _083_;
  (* src = "libresoc.v:49885.13-49885.33" *)
  reg [3:0] _084_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg _085_;
  (* src = "libresoc.v:49889.7-49889.30" *)
  reg _086_;
  (* src = "libresoc.v:50545.3-50554.6" *)
  reg [63:0] _087_;
  (* src = "libresoc.v:50555.3-50564.6" *)
  reg [31:0] _088_;
  (* src = "libresoc.v:50565.3-50574.6" *)
  reg [3:0] _089_;
  (* src = "libresoc.v:50344.3-50352.6" *)
  reg _090_;
  (* src = "libresoc.v:49908.7-49908.25" *)
  reg _091_;
  (* src = "libresoc.v:50335.3-50343.6" *)
  reg _092_;
  (* src = "libresoc.v:49912.7-49912.25" *)
  reg _093_;
  (* src = "libresoc.v:50575.3-50583.6" *)
  reg [2:0] _094_;
  (* src = "libresoc.v:50012.13-50012.30" *)
  reg [2:0] _095_;
  (* src = "libresoc.v:50289.3-50298.6" *)
  reg _096_;
  (* src = "libresoc.v:50380.3-50388.6" *)
  reg [2:0] _097_;
  (* src = "libresoc.v:50020.13-50020.31" *)
  reg [2:0] _098_;
  (* src = "libresoc.v:50371.3-50379.6" *)
  reg [2:0] _099_;
  (* src = "libresoc.v:50024.13-50024.31" *)
  reg [2:0] _100_;
  (* src = "libresoc.v:50308.3-50316.6" *)
  reg _101_;
  (* src = "libresoc.v:50036.7-50036.26" *)
  reg _102_;
  (* src = "libresoc.v:50299.3-50307.6" *)
  reg _103_;
  (* src = "libresoc.v:50040.7-50040.26" *)
  reg _104_;
  (* src = "libresoc.v:50326.3-50334.6" *)
  reg _105_;
  (* src = "libresoc.v:50044.7-50044.25" *)
  reg _106_;
  (* src = "libresoc.v:50317.3-50325.6" *)
  reg _107_;
  (* src = "libresoc.v:50048.7-50048.25" *)
  reg _108_;
  (* src = "libresoc.v:50362.3-50370.6" *)
  reg [5:0] _109_;
  (* src = "libresoc.v:50068.13-50068.32" *)
  reg [5:0] _110_;
  (* src = "libresoc.v:50353.3-50361.6" *)
  reg [5:0] _111_;
  (* src = "libresoc.v:50072.13-50072.32" *)
  reg [5:0] _112_;
  (* src = "libresoc.v:50467.3-50476.6" *)
  reg [63:0] _113_;
  (* src = "libresoc.v:50076.14-50076.43" *)
  reg [63:0] _114_;
  (* src = "libresoc.v:50477.3-50486.6" *)
  reg [63:0] _115_;
  (* src = "libresoc.v:50080.14-50080.43" *)
  reg [63:0] _116_;
  (* src = "libresoc.v:50487.3-50496.6" *)
  reg [31:0] _117_;
  (* src = "libresoc.v:50084.14-50084.28" *)
  reg [31:0] _118_;
  (* src = "libresoc.v:50497.3-50506.6" *)
  reg [3:0] _119_;
  (* src = "libresoc.v:50088.13-50088.26" *)
  reg [3:0] _120_;
  (* src = "libresoc.v:50507.3-50516.6" *)
  reg [3:0] _121_;
  (* src = "libresoc.v:50092.13-50092.26" *)
  reg [3:0] _122_;
  (* src = "libresoc.v:50517.3-50526.6" *)
  reg [3:0] _123_;
  (* src = "libresoc.v:50096.13-50096.26" *)
  reg [3:0] _124_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg [63:0] _125_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg _126_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg [31:0] _127_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg _128_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg [3:0] _129_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg _130_;
  (* src = "libresoc.v:50401.3-50422.6" *)
  reg _131_;
  (* src = "libresoc.v:50423.3-50444.6" *)
  reg _132_;
  (* src = "libresoc.v:50445.3-50466.6" *)
  reg _133_;
  (* src = "libresoc.v:50102.18-50102.112" *)
  wire [5:0] _134_;
  (* src = "libresoc.v:50103.19-50103.125" *)
  wire _135_;
  (* src = "libresoc.v:50104.19-50104.125" *)
  wire _136_;
  (* src = "libresoc.v:50105.19-50105.125" *)
  wire _137_;
  (* src = "libresoc.v:50106.19-50106.141" *)
  wire [2:0] _138_;
  (* src = "libresoc.v:50107.19-50107.121" *)
  wire [2:0] _139_;
  (* src = "libresoc.v:50108.19-50108.127" *)
  wire _140_;
  (* src = "libresoc.v:50109.19-50109.127" *)
  wire _141_;
  (* src = "libresoc.v:50110.19-50110.127" *)
  wire _142_;
  (* src = "libresoc.v:50111.18-50111.110" *)
  wire _143_;
  (* src = "libresoc.v:50113.18-50113.98" *)
  wire _144_;
  (* src = "libresoc.v:50115.18-50115.100" *)
  wire _145_;
  (* src = "libresoc.v:50116.18-50116.149" *)
  wire [2:0] _146_;
  (* src = "libresoc.v:50118.18-50118.119" *)
  wire [2:0] _147_;
  (* src = "libresoc.v:50121.18-50121.116" *)
  wire _148_;
  (* src = "libresoc.v:50125.17-50125.123" *)
  wire _149_;
  (* src = "libresoc.v:50127.18-50127.113" *)
  wire _150_;
  (* src = "libresoc.v:50128.18-50128.125" *)
  wire [2:0] _151_;
  (* src = "libresoc.v:50130.18-50130.112" *)
  wire _152_;
  (* src = "libresoc.v:50132.18-50132.125" *)
  wire _153_;
  (* src = "libresoc.v:50133.18-50133.125" *)
  wire _154_;
  (* src = "libresoc.v:50134.18-50134.117" *)
  wire _155_;
  (* src = "libresoc.v:50139.18-50139.129" *)
  wire _156_;
  (* src = "libresoc.v:50140.18-50140.124" *)
  wire [2:0] _157_;
  (* src = "libresoc.v:50143.18-50143.116" *)
  wire _158_;
  (* src = "libresoc.v:50144.18-50144.122" *)
  wire _159_;
  (* src = "libresoc.v:50145.18-50145.119" *)
  wire _160_;
  (* src = "libresoc.v:50153.18-50153.133" *)
  wire _161_;
  (* src = "libresoc.v:50154.18-50154.131" *)
  wire _162_;
  (* src = "libresoc.v:50155.18-50155.182" *)
  wire [5:0] _163_;
  (* src = "libresoc.v:50156.18-50156.113" *)
  wire [5:0] _164_;
  (* src = "libresoc.v:50129.18-50129.113" *)
  wire _165_;
  (* src = "libresoc.v:50131.18-50131.119" *)
  wire _166_;
  (* src = "libresoc.v:50112.18-50112.97" *)
  wire _167_;
  (* src = "libresoc.v:50114.18-50114.99" *)
  wire _168_;
  (* src = "libresoc.v:50117.18-50117.113" *)
  wire [2:0] _169_;
  (* src = "libresoc.v:50120.18-50120.106" *)
  wire _170_;
  (* src = "libresoc.v:50126.18-50126.119" *)
  wire _171_;
  (* src = "libresoc.v:50141.17-50141.113" *)
  wire [5:0] _172_;
  (* src = "libresoc.v:50157.18-50157.114" *)
  wire [5:0] _173_;
  (* src = "libresoc.v:50124.18-50124.112" *)
  wire _174_;
  (* src = "libresoc.v:50135.18-50135.122" *)
  wire _175_;
  (* src = "libresoc.v:50136.18-50136.124" *)
  wire _176_;
  (* src = "libresoc.v:50137.18-50137.155" *)
  wire [2:0] _177_;
  (* src = "libresoc.v:50138.18-50138.194" *)
  wire [5:0] _178_;
  (* src = "libresoc.v:50142.18-50142.120" *)
  wire [2:0] _179_;
  (* src = "libresoc.v:50152.17-50152.117" *)
  wire [5:0] _180_;
  (* src = "libresoc.v:50101.17-50101.104" *)
  wire _181_;
  (* src = "libresoc.v:50119.18-50119.106" *)
  wire _182_;
  (* src = "libresoc.v:50122.18-50122.113" *)
  wire _183_;
  (* src = "libresoc.v:50123.18-50123.112" *)
  wire _184_;
  (* src = "libresoc.v:50146.18-50146.118" *)
  wire [63:0] _185_;
  (* src = "libresoc.v:50147.18-50147.118" *)
  wire [63:0] _186_;
  (* src = "libresoc.v:50148.18-50148.118" *)
  wire [31:0] _187_;
  (* src = "libresoc.v:50149.18-50149.118" *)
  wire [3:0] _188_;
  (* src = "libresoc.v:50150.18-50150.118" *)
  wire [3:0] _189_;
  (* src = "libresoc.v:50151.18-50151.118" *)
  wire [3:0] _190_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [2:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [2:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [5:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [2:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [5:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [2:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [2:0] \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$77 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [5:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [31:0] \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [3:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [3:0] \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [3:0] \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_cr0_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] \alu_cr0_cr_a$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] alu_cr0_cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] alu_cr0_cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_cr0_cr_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_cr0_cr_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_cr0_cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_cr0_cr_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_cr0_cr_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_cr0_cr_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [31:0] alu_cr0_full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [31:0] \alu_cr0_full_cr$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_cr0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_cr0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_cr0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_cr0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_cr0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_cr0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_cr0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [2:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [5:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [2:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [31:0] data_r1__full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [31:0] \data_r1__full_cr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__full_cr_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r2__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r2__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [31:0] dest2_o;
  reg [31:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest3_o;
  reg [3:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output full_cr_ok;
  (* src = "libresoc.v:49559.7-49559.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_cr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_cr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_cr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [5:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [2:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [31:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] src4_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] src5_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] src6_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [5:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [31:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [31:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] src_r3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] \src_r3$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] src_r4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] \src_r4$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] src_r5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [3:0] \src_r5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  assign _134_ = \$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ;
  assign _135_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _136_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _137_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _138_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105  };
  assign _139_ = \$107  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _140_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _141_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _142_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _143_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ;
  assign _144_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ;
  assign _145_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ;
  assign _146_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _147_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ;
  assign _148_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _149_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _150_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ;
  assign _151_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _152_ = \$41  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ;
  assign _153_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_cr0_n_ready_i;
  assign _154_ = \$51  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_cr0_n_valid_o;
  assign _155_ = \$53  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _156_ = alu_cr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _157_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _158_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _159_ = full_cr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _160_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _161_ = alu_cr0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _162_ = alu_cr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _163_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _164_ = \$93  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 6'h3f;
  assign _165_ = \$43  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _166_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _167_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _168_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _169_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _170_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _171_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_cr0_n_ready_i;
  assign _172_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _173_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _174_ = \$33  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ;
  assign _175_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _176_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _177_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _178_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _179_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _180_ = \$6  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _181_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ;
  assign _182_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ;
  assign _183_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _184_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _185_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _186_ = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1;
  assign _187_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  assign _188_ = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3;
  assign _189_ = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4;
  assign _190_ = src_l_q_src[5] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src6_i : src_r5;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50218.11-50240.4" *)
  alu_cr0 alu_cr0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_cr0_cr_a),
    .\cr_a$2 (\alu_cr0_cr_a$2 ),
    .cr_a_ok(cr_a_ok),
    .cr_b(alu_cr0_cr_b),
    .cr_c(alu_cr0_cr_c),
    .cr_op__fn_unit(alu_cr0_cr_op__fn_unit),
    .cr_op__insn(alu_cr0_cr_op__insn),
    .cr_op__insn_type(alu_cr0_cr_op__insn_type),
    .full_cr(alu_cr0_full_cr),
    .\full_cr$1 (\alu_cr0_full_cr$1 ),
    .full_cr_ok(full_cr_ok),
    .n_ready_i(alu_cr0_n_ready_i),
    .n_valid_o(alu_cr0_n_valid_o),
    .o(alu_cr0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_cr0_p_ready_o),
    .p_valid_i(alu_cr0_p_valid_i),
    .ra(alu_cr0_ra),
    .rb(alu_cr0_rb)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50241.14-50247.4" *)
  \alu_l$16  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50248.15-50254.4" *)
  \alui_l$15  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50255.14-50261.4" *)
  \opc_l$11  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50262.14-50268.4" *)
  \req_l$12  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50269.14-50275.4" *)
  \rok_l$14  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50276.14-50281.4" *)
  \rst_l$13  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:50282.14-50288.4" *)
  \src_l$10  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _027_ = 1'h0;
  end
  always @* begin
      \initial  <= _027_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _063_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_cr0_cr_op__fn_unit <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_cr0_cr_op__insn <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_cr0_cr_op__insn_type <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      data_r1__full_cr <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__full_cr_ok <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__cr_a <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__cr_a_ok <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 6'h3f;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_r3 <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_r4 <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_r5 <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \src_r5$next ;
  end
  always @(posedge coresync_clk) begin
      src_r5 <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \src_r4$next ;
  end
  always @(posedge coresync_clk) begin
      src_r4 <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \src_r3$next ;
  end
  always @(posedge coresync_clk) begin
      src_r3 <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \data_r2__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__cr_a <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \data_r2__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__cr_a_ok <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \data_r1__full_cr$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__full_cr <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \data_r1__full_cr_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__full_cr_ok <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \alu_cr0_cr_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_cr0_cr_op__insn_type <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \alu_cr0_cr_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_cr0_cr_op__fn_unit <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \alu_cr0_cr_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_cr0_cr_op__insn <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = alu_cr0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$11 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _096_;
    (* src = "libresoc.v:50290.5-50290.29" *)
    casez (\initial )
      /* src = "libresoc.v:50290.9-50290.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _096_ = 1'h1;
        end
      default:
          _096_ = \$47 ;
    endcase
  end
  always @* begin
      req_done <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _103_;
    (* src = "libresoc.v:50300.5-50300.29" *)
    casez (\initial )
      /* src = "libresoc.v:50300.9-50300.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = 1'h0;
        end
      default:
          _103_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = _101_;
    (* src = "libresoc.v:50309.5-50309.29" *)
    casez (\initial )
      /* src = "libresoc.v:50309.9-50309.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = 1'h1;
        end
      default:
          _101_ = \$65 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = _107_;
    (* src = "libresoc.v:50318.5-50318.29" *)
    casez (\initial )
      /* src = "libresoc.v:50318.9-50318.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _107_ = 1'h0;
        end
      default:
          _107_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _105_;
    (* src = "libresoc.v:50327.5-50327.29" *)
    casez (\initial )
      /* src = "libresoc.v:50327.9-50327.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = 1'h1;
        end
      default:
          _105_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _092_;
    (* src = "libresoc.v:50336.5-50336.29" *)
    casez (\initial )
      /* src = "libresoc.v:50336.9-50336.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _092_ = 1'h0;
        end
      default:
          _092_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _090_;
    (* src = "libresoc.v:50345.5-50345.29" *)
    casez (\initial )
      /* src = "libresoc.v:50345.9-50345.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _090_ = 1'h1;
        end
      default:
          _090_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _111_;
    (* src = "libresoc.v:50354.5-50354.29" *)
    casez (\initial )
      /* src = "libresoc.v:50354.9-50354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _111_ = 6'h00;
        end
      default:
          _111_ = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _109_;
    (* src = "libresoc.v:50363.5-50363.29" *)
    casez (\initial )
      /* src = "libresoc.v:50363.9-50363.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _109_ = 6'h3f;
        end
      default:
          _109_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = _099_;
    (* src = "libresoc.v:50372.5-50372.29" *)
    casez (\initial )
      /* src = "libresoc.v:50372.9-50372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _099_ = 3'h0;
        end
      default:
          _099_ = \$67 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = _097_;
    (* src = "libresoc.v:50381.5-50381.29" *)
    casez (\initial )
      /* src = "libresoc.v:50381.9-50381.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = 3'h7;
        end
      default:
          _097_ = \$69 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _064_;
    _003_ = _066_;
    _005_ = _068_;
    (* src = "libresoc.v:50390.5-50390.29" *)
    casez (\initial )
      /* src = "libresoc.v:50390.9-50390.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _066_, _064_, _068_ } = { oper_i_alu_cr0__insn, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn_type };
        end
      default:
        begin
          _064_ = alu_cr0_cr_op__fn_unit;
          _066_ = alu_cr0_cr_op__insn;
          _068_ = alu_cr0_cr_op__insn_type;
        end
    endcase
  end
  always @* begin
      \alu_cr0_cr_op__fn_unit$next  <= _001_;
      \alu_cr0_cr_op__insn$next  <= _003_;
      \alu_cr0_cr_op__insn_type$next  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _125_;
    _014_ = _131_;
    (* src = "libresoc.v:50402.5-50402.29" *)
    casez (\initial )
      /* src = "libresoc.v:50402.9-50402.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _077_, _075_ } = { o_ok, alu_cr0_o };
        end
      default:
        begin
          _075_ = data_r0__o;
          _077_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _126_, _125_ } = 65'h00000000000000000;
        end
      default:
        begin
          _125_ = _075_;
          _126_ = _077_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = 1'h0;
        end
      default:
          _131_ = _126_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _012_;
      \data_r0__o_ok$next  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _127_;
    _018_ = _132_;
    (* src = "libresoc.v:50424.5-50424.29" *)
    casez (\initial )
      /* src = "libresoc.v:50424.9-50424.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _081_, _079_ } = { full_cr_ok, alu_cr0_full_cr };
        end
      default:
        begin
          _079_ = data_r1__full_cr;
          _081_ = data_r1__full_cr_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _128_, _127_ } = 33'h000000000;
        end
      default:
        begin
          _127_ = _079_;
          _128_ = _081_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h0;
        end
      default:
          _132_ = _128_;
    endcase
  end
  always @* begin
      \data_r1__full_cr$next  <= _016_;
      \data_r1__full_cr_ok$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _129_;
    _022_ = _133_;
    (* src = "libresoc.v:50446.5-50446.29" *)
    casez (\initial )
      /* src = "libresoc.v:50446.9-50446.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _085_, _083_ } = { cr_a_ok, alu_cr0_cr_a };
        end
      default:
        begin
          _083_ = data_r2__cr_a;
          _085_ = data_r2__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _130_, _129_ } = 5'h00;
        end
      default:
        begin
          _129_ = _083_;
          _130_ = _085_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _133_ = 1'h0;
        end
      default:
          _133_ = _130_;
    endcase
  end
  always @* begin
      \data_r2__cr_a$next  <= _020_;
      \data_r2__cr_a_ok$next  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _113_;
    (* src = "libresoc.v:50468.5-50468.29" *)
    casez (\initial )
      /* src = "libresoc.v:50468.9-50468.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = src1_i;
        end
      default:
          _113_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _115_;
    (* src = "libresoc.v:50478.5-50478.29" *)
    casez (\initial )
      /* src = "libresoc.v:50478.9-50478.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[1])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _115_ = src2_i;
        end
      default:
          _115_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _117_;
    (* src = "libresoc.v:50488.5-50488.29" *)
    casez (\initial )
      /* src = "libresoc.v:50488.9-50488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _117_ = src3_i;
        end
      default:
          _117_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _119_;
    (* src = "libresoc.v:50498.5-50498.29" *)
    casez (\initial )
      /* src = "libresoc.v:50498.9-50498.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[3])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _119_ = src4_i;
        end
      default:
          _119_ = src_r3;
    endcase
  end
  always @* begin
      \src_r3$next  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _121_;
    (* src = "libresoc.v:50508.5-50508.29" *)
    casez (\initial )
      /* src = "libresoc.v:50508.9-50508.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[4])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = src5_i;
        end
      default:
          _121_ = src_r4;
    endcase
  end
  always @* begin
      \src_r4$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _123_;
    (* src = "libresoc.v:50518.5-50518.29" *)
    casez (\initial )
      /* src = "libresoc.v:50518.9-50518.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[5])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _123_ = src6_i;
        end
      default:
          _123_ = src_r5;
    endcase
  end
  always @* begin
      \src_r5$next  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _073_;
    (* src = "libresoc.v:50528.5-50528.29" *)
    casez (\initial )
      /* src = "libresoc.v:50528.9-50528.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _073_ = 1'h1;
        end
      default:
          _073_ = \$89 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _071_;
    (* src = "libresoc.v:50537.5-50537.29" *)
    casez (\initial )
      /* src = "libresoc.v:50537.9-50537.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _071_ = 1'h1;
        end
      default:
          _071_ = \$91 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _087_;
    (* src = "libresoc.v:50546.5-50546.29" *)
    casez (\initial )
      /* src = "libresoc.v:50546.9-50546.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$111 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = data_r0__o;
        end
      default:
          _087_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _088_;
    (* src = "libresoc.v:50556.5-50556.29" *)
    casez (\initial )
      /* src = "libresoc.v:50556.9-50556.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _088_ = data_r1__full_cr;
        end
      default:
          _088_ = 32'd0;
    endcase
  end
  always @* begin
      dest2_o <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _089_;
    (* src = "libresoc.v:50566.5-50566.29" *)
    casez (\initial )
      /* src = "libresoc.v:50566.9-50566.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _089_ = data_r2__cr_a;
        end
      default:
          _089_ = 4'h0;
    endcase
  end
  always @* begin
      dest3_o <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _094_;
    (* src = "libresoc.v:50576.5-50576.29" *)
    casez (\initial )
      /* src = "libresoc.v:50576.9-50576.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _094_ = 3'h0;
        end
      default:
          _094_ = \$21 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _032_;
  end
  assign \$5  = _181_;
  assign \$99  = _134_;
  assign \$101  = _135_;
  assign \$103  = _136_;
  assign \$105  = _137_;
  assign \$107  = _138_;
  assign \$109  = _139_;
  assign \$111  = _140_;
  assign \$113  = _141_;
  assign \$115  = _142_;
  assign \$11  = _143_;
  assign \$13  = _167_;
  assign \$15  = _144_;
  assign \$17  = _168_;
  assign \$19  = _145_;
  assign \$21  = _146_;
  assign \$25  = _169_;
  assign \$27  = _147_;
  assign \$24  = _182_;
  assign \$23  = _170_;
  assign \$31  = _148_;
  assign \$33  = _183_;
  assign \$35  = _184_;
  assign \$37  = _174_;
  assign \$3  = _149_;
  assign \$39  = _171_;
  assign \$41  = _150_;
  assign \$43  = _151_;
  assign \$45  = _165_;
  assign \$47  = _152_;
  assign \$49  = _166_;
  assign \$51  = _153_;
  assign \$53  = _154_;
  assign \$55  = _155_;
  assign \$57  = _175_;
  assign \$59  = _176_;
  assign \$61  = _177_;
  assign \$63  = _178_;
  assign \$65  = _156_;
  assign \$67  = _157_;
  assign \$6  = _172_;
  assign \$69  = _179_;
  assign \$71  = _158_;
  assign \$73  = _159_;
  assign \$75  = _160_;
  assign \$77  = _185_;
  assign \$79  = _186_;
  assign \$81  = _187_;
  assign \$83  = _188_;
  assign \$85  = _189_;
  assign \$87  = _190_;
  assign \$8  = _180_;
  assign \$89  = _161_;
  assign \$91  = _162_;
  assign \$93  = _163_;
  assign \$95  = _164_;
  assign \$97  = _173_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$109 ;
  assign cu_rd__rel_o = \$99 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_cr0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_cr0_p_valid_i = alui_l_q_alui;
  assign alu_cr0_cr_c = \$87 ;
  assign alu_cr0_cr_b = \$85 ;
  assign \alu_cr0_cr_a$2  = \$83 ;
  assign \alu_cr0_full_cr$1  = \$81 ;
  assign alu_cr0_rb = \$79 ;
  assign alu_cr0_ra = \$77 ;
  assign cu_wrmask_o = { \$75 , \$73 , \$71  };
  assign reset_r = \$63 ;
  assign reset_w = \$61 ;
  assign rst_r = \$59 ;
  assign reset = \$57 ;
  assign wr_any = \$37 ;
  assign cu_done_o = \$31 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$19 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_cr0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$15 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.cyc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:50619.1-50668.10" *)
module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:50620.7-50620.20" *)
  reg _00_;
  (* src = "libresoc.v:50656.3-50664.6" *)
  reg _01_;
  (* src = "libresoc.v:50654.3-50655.27" *)
  reg _02_;
  (* src = "libresoc.v:50656.3-50664.6" *)
  reg _03_;
  (* src = "libresoc.v:50638.7-50638.19" *)
  reg _04_;
  (* src = "libresoc.v:50651.17-50651.96" *)
  wire _05_;
  (* src = "libresoc.v:50650.17-50650.92" *)
  wire _06_;
  (* src = "libresoc.v:50653.17-50653.92" *)
  wire _07_;
  (* src = "libresoc.v:50649.17-50649.98" *)
  wire _08_;
  (* src = "libresoc.v:50652.17-50652.97" *)
  wire _09_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:50620.7-50620.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_cyc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_cyc;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_cyc;
  assign _08_ = q_cyc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _09_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_cyc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:50657.5-50657.29" *)
    casez (\initial )
      /* src = "libresoc.v:50657.9-50657.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _08_;
  assign \$1  = _06_;
  assign \$3  = _05_;
  assign \$5  = _09_;
  assign \$7  = _07_;
  assign qlq_cyc = \$9 ;
  assign qn_cyc = \$7 ;
  assign q_cyc = q_int;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dbg" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:50672.1-51413.10" *)
module dbg(dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, core_rst_o, rst, terminate_i, core_dbg_pc, core_dbg_core_dbg_svstep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_dststep, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_vl, core_dbg_core_dbg_maxvl, core_dbg_msr, core_stop_o, core_stopped_i, d_gpr_req, d_gpr_addr, d_gpr_data, d_gpr_ack, d_cr_req, d_cr_data, d_cr_ack, d_xer_req, d_xer_data, d_xer_ack, clk);
  reg \initial  = 0;
  (* src = "libresoc.v:51217.3-51229.6" *)
  reg _000_;
  (* src = "libresoc.v:51024.3-51033.6" *)
  reg _001_;
  (* src = "libresoc.v:51230.3-51245.6" *)
  reg _002_;
  (* src = "libresoc.v:51006.3-51023.6" *)
  reg _003_;
  (* src = "libresoc.v:51246.3-51279.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:51208.3-51216.6" *)
  reg _005_;
  (* src = "libresoc.v:50984.3-50985.51" *)
  reg _006_;
  (* src = "libresoc.v:51199.3-51207.6" *)
  reg _007_;
  (* src = "libresoc.v:50986.3-50987.55" *)
  reg _008_;
  (* src = "libresoc.v:51034.3-51042.6" *)
  reg _009_;
  (* src = "libresoc.v:50996.3-50997.39" *)
  reg _010_;
  (* src = "libresoc.v:51370.3-51403.6" *)
  reg _011_;
  (* src = "libresoc.v:50998.3-50999.43" *)
  reg _012_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _013_;
  (* src = "libresoc.v:51000.3-51001.37" *)
  reg _014_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _015_;
  (* src = "libresoc.v:51002.3-51003.33" *)
  reg _016_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _017_;
  (* src = "libresoc.v:51004.3-51005.31" *)
  reg _018_;
  (* src = "libresoc.v:51137.3-51164.6" *)
  reg [6:0] _019_;
  (* src = "libresoc.v:50990.3-50991.37" *)
  reg [6:0] _020_;
  (* src = "libresoc.v:50673.7-50673.20" *)
  reg _021_;
  (* src = "libresoc.v:51165.3-51198.6" *)
  reg [31:0] _022_;
  (* src = "libresoc.v:50988.3-50989.41" *)
  reg [31:0] _023_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _024_;
  (* src = "libresoc.v:50992.3-50993.33" *)
  reg _025_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _026_;
  (* src = "libresoc.v:50994.3-50995.37" *)
  reg _027_;
  (* src = "libresoc.v:51217.3-51229.6" *)
  reg _028_;
  (* src = "libresoc.v:51024.3-51033.6" *)
  reg _029_;
  (* src = "libresoc.v:51230.3-51245.6" *)
  reg _030_;
  (* src = "libresoc.v:51006.3-51023.6" *)
  reg _031_;
  (* src = "libresoc.v:51246.3-51279.6" *)
  reg [63:0] _032_;
  (* src = "libresoc.v:51208.3-51216.6" *)
  reg _033_;
  (* src = "libresoc.v:50860.7-50860.31" *)
  reg _034_;
  (* src = "libresoc.v:51199.3-51207.6" *)
  reg _035_;
  (* src = "libresoc.v:50864.7-50864.33" *)
  reg _036_;
  (* src = "libresoc.v:51034.3-51042.6" *)
  reg _037_;
  (* src = "libresoc.v:50870.7-50870.25" *)
  reg _038_;
  (* src = "libresoc.v:51370.3-51403.6" *)
  reg _039_;
  (* src = "libresoc.v:50876.7-50876.27" *)
  reg _040_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _041_;
  (* src = "libresoc.v:50880.7-50880.24" *)
  reg _042_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _043_;
  (* src = "libresoc.v:50884.7-50884.22" *)
  reg _044_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _045_;
  (* src = "libresoc.v:50888.7-50888.21" *)
  reg _046_;
  (* src = "libresoc.v:51137.3-51164.6" *)
  reg [6:0] _047_;
  (* src = "libresoc.v:50892.13-50892.31" *)
  reg [6:0] _048_;
  (* src = "libresoc.v:51165.3-51198.6" *)
  reg [31:0] _049_;
  (* src = "libresoc.v:50898.14-50898.34" *)
  reg [31:0] _050_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _051_;
  (* src = "libresoc.v:50910.7-50910.22" *)
  reg _052_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _053_;
  (* src = "libresoc.v:50916.7-50916.24" *)
  reg _054_;
  (* src = "libresoc.v:51370.3-51403.6" *)
  reg _055_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _056_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _057_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _058_;
  (* src = "libresoc.v:51137.3-51164.6" *)
  reg [6:0] _059_;
  (* src = "libresoc.v:51165.3-51198.6" *)
  reg [31:0] _060_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _061_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _062_;
  (* src = "libresoc.v:51370.3-51403.6" *)
  reg _063_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _064_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _065_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _066_;
  (* src = "libresoc.v:51137.3-51164.6" *)
  reg [6:0] _067_;
  (* src = "libresoc.v:51165.3-51198.6" *)
  reg [31:0] _068_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _069_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _070_;
  (* src = "libresoc.v:51370.3-51403.6" *)
  reg _071_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _072_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _073_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _074_;
  (* src = "libresoc.v:51137.3-51164.6" *)
  reg [6:0] _075_;
  (* src = "libresoc.v:51165.3-51198.6" *)
  reg [31:0] _076_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _077_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _078_;
  (* src = "libresoc.v:51340.3-51369.6" *)
  reg _079_;
  (* src = "libresoc.v:51310.3-51339.6" *)
  reg _080_;
  (* src = "libresoc.v:51280.3-51309.6" *)
  reg _081_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _082_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _083_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _084_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _085_;
  (* src = "libresoc.v:51093.3-51136.6" *)
  reg _086_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _087_;
  (* src = "libresoc.v:51043.3-51092.6" *)
  reg _088_;
  (* src = "libresoc.v:50931.19-50931.110" *)
  wire [2:0] _089_;
  (* src = "libresoc.v:50925.19-50925.103" *)
  wire _090_;
  (* src = "libresoc.v:50927.19-50927.113" *)
  wire _091_;
  (* src = "libresoc.v:50932.18-50932.110" *)
  wire _092_;
  (* src = "libresoc.v:50934.19-50934.103" *)
  wire _093_;
  (* src = "libresoc.v:50936.19-50936.102" *)
  wire _094_;
  (* src = "libresoc.v:50942.18-50942.101" *)
  wire _095_;
  (* src = "libresoc.v:50944.18-50944.111" *)
  wire _096_;
  (* src = "libresoc.v:50949.18-50949.101" *)
  wire _097_;
  (* src = "libresoc.v:50952.18-50952.111" *)
  wire _098_;
  (* src = "libresoc.v:50957.18-50957.101" *)
  wire _099_;
  (* src = "libresoc.v:50959.18-50959.111" *)
  wire _100_;
  (* src = "libresoc.v:50965.18-50965.101" *)
  wire _101_;
  (* src = "libresoc.v:50967.18-50967.111" *)
  wire _102_;
  (* src = "libresoc.v:50972.18-50972.101" *)
  wire _103_;
  (* src = "libresoc.v:50973.17-50973.99" *)
  wire _104_;
  (* src = "libresoc.v:50975.18-50975.111" *)
  wire _105_;
  (* src = "libresoc.v:50980.18-50980.101" *)
  wire _106_;
  (* src = "libresoc.v:50982.18-50982.111" *)
  wire _107_;
  (* src = "libresoc.v:50922.18-50922.103" *)
  wire _108_;
  (* src = "libresoc.v:50923.19-50923.104" *)
  wire _109_;
  (* src = "libresoc.v:50928.19-50928.104" *)
  wire _110_;
  (* src = "libresoc.v:50929.19-50929.104" *)
  wire _111_;
  (* src = "libresoc.v:50930.19-50930.104" *)
  wire _112_;
  (* src = "libresoc.v:50933.19-50933.104" *)
  wire _113_;
  (* src = "libresoc.v:50937.18-50937.103" *)
  wire _114_;
  (* src = "libresoc.v:50938.18-50938.103" *)
  wire _115_;
  (* src = "libresoc.v:50939.18-50939.103" *)
  wire _116_;
  (* src = "libresoc.v:50945.18-50945.103" *)
  wire _117_;
  (* src = "libresoc.v:50946.18-50946.103" *)
  wire _118_;
  (* src = "libresoc.v:50947.18-50947.103" *)
  wire _119_;
  (* src = "libresoc.v:50953.18-50953.103" *)
  wire _120_;
  (* src = "libresoc.v:50954.18-50954.103" *)
  wire _121_;
  (* src = "libresoc.v:50955.18-50955.103" *)
  wire _122_;
  (* src = "libresoc.v:50960.18-50960.103" *)
  wire _123_;
  (* src = "libresoc.v:50961.18-50961.103" *)
  wire _124_;
  (* src = "libresoc.v:50963.18-50963.103" *)
  wire _125_;
  (* src = "libresoc.v:50968.18-50968.103" *)
  wire _126_;
  (* src = "libresoc.v:50969.18-50969.103" *)
  wire _127_;
  (* src = "libresoc.v:50970.18-50970.103" *)
  wire _128_;
  (* src = "libresoc.v:50976.18-50976.103" *)
  wire _129_;
  (* src = "libresoc.v:50977.18-50977.103" *)
  wire _130_;
  (* src = "libresoc.v:50978.18-50978.103" *)
  wire _131_;
  (* src = "libresoc.v:50983.18-50983.103" *)
  wire _132_;
  (* src = "libresoc.v:50921.17-50921.103" *)
  wire _133_;
  (* src = "libresoc.v:50924.19-50924.99" *)
  wire _134_;
  (* src = "libresoc.v:50926.19-50926.105" *)
  wire _135_;
  (* src = "libresoc.v:50935.19-50935.95" *)
  wire _136_;
  (* src = "libresoc.v:50941.18-50941.98" *)
  wire _137_;
  (* src = "libresoc.v:50943.18-50943.104" *)
  wire _138_;
  (* src = "libresoc.v:50948.18-50948.98" *)
  wire _139_;
  (* src = "libresoc.v:50950.18-50950.104" *)
  wire _140_;
  (* src = "libresoc.v:50956.18-50956.98" *)
  wire _141_;
  (* src = "libresoc.v:50958.18-50958.104" *)
  wire _142_;
  (* src = "libresoc.v:50962.17-50962.97" *)
  wire _143_;
  (* src = "libresoc.v:50964.18-50964.98" *)
  wire _144_;
  (* src = "libresoc.v:50966.18-50966.104" *)
  wire _145_;
  (* src = "libresoc.v:50971.18-50971.98" *)
  wire _146_;
  (* src = "libresoc.v:50974.18-50974.104" *)
  wire _147_;
  (* src = "libresoc.v:50979.18-50979.98" *)
  wire _148_;
  (* src = "libresoc.v:50981.18-50981.104" *)
  wire _149_;
  (* src = "libresoc.v:50940.17-50940.126" *)
  wire [63:0] _150_;
  (* src = "libresoc.v:50951.17-50951.245" *)
  wire [63:0] _151_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *)
  wire [2:0] \$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *)
  wire [2:0] \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *)
  wire \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *)
  wire \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *)
  wire \$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  input [6:0] core_dbg_core_dbg_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  input [6:0] core_dbg_core_dbg_maxvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  input [6:0] core_dbg_core_dbg_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  input [1:0] core_dbg_core_dbg_subvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  input [1:0] core_dbg_core_dbg_svstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  input [6:0] core_dbg_core_dbg_vl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  input [63:0] core_dbg_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  input [63:0] core_dbg_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *)
  output core_rst_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" *)
  output core_stop_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" *)
  input core_stopped_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  input d_cr_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  input [63:0] d_cr_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  output d_cr_req;
  reg d_cr_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  input d_gpr_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" *)
  output [6:0] d_gpr_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  input [63:0] d_gpr_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  output d_gpr_req;
  reg d_gpr_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  input d_xer_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  input [63:0] d_xer_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  output d_xer_req;
  reg d_xer_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" *)
  output dmi_ack_o;
  reg dmi_ack_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *)
  input [3:0] dmi_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *)
  input [63:0] dmi_din;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" *)
  output [63:0] dmi_dout;
  reg [63:0] dmi_dout;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" *)
  reg dmi_read_log_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149" *)
  reg \dmi_read_log_data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" *)
  reg dmi_read_log_data_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" *)
  reg \dmi_read_log_data_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *)
  input dmi_req_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" *)
  reg dmi_req_i_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" *)
  reg \dmi_req_i_1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *)
  input dmi_we_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" *)
  reg do_dmi_log_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:148" *)
  reg \do_dmi_log_rd$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" *)
  reg do_icreset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" *)
  reg \do_icreset$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" *)
  reg do_reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" *)
  reg \do_reset$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" *)
  reg do_step;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" *)
  reg \do_step$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" *)
  reg [6:0] gspr_index;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:144" *)
  reg [6:0] \gspr_index$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" *)
  wire icache_rst_o;
  (* src = "libresoc.v:50673.7-50673.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" *)
  reg [31:0] log_dmi_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" *)
  reg [31:0] \log_dmi_addr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" *)
  wire [63:0] log_dmi_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *)
  wire [31:0] log_write_addr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *)
  wire [63:0] stat_reg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" *)
  reg stopping;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" *)
  reg \stopping$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" *)
  input terminate_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" *)
  reg terminated;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:142" *)
  reg \terminated$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" *)
  wire terminated_o;
  assign _089_ = log_dmi_addr[1:0] + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" *) 1'h1;
  assign _090_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$103 ;
  assign _091_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$107 ;
  assign _092_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$9 ;
  assign _093_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) \$120 ;
  assign _094_ = stopping & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) \$124 ;
  assign _095_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$19 ;
  assign _096_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$23 ;
  assign _097_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$33 ;
  assign _098_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$37 ;
  assign _099_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$47 ;
  assign _100_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$51 ;
  assign _101_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$61 ;
  assign _102_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$65 ;
  assign _103_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$75 ;
  assign _104_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$5 ;
  assign _105_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$79 ;
  assign _106_ = dmi_req_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) \$89 ;
  assign _107_ = dmi_read_log_data_1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) \$93 ;
  assign _108_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _109_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _110_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _111_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _112_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _113_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" *) 3'h7;
  assign _114_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _115_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _116_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _117_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _118_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _119_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _120_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _121_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _122_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _123_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _124_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _125_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _126_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _127_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _128_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _129_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _130_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) 3'h4;
  assign _131_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" *) 3'h6;
  assign _132_ = dmi_addr_i == (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *) 1'h0;
  assign _133_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _134_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _135_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _136_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" *) do_step;
  assign _137_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _138_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _139_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _140_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _141_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _142_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _143_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _144_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _145_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _146_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _147_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _148_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *) dmi_req_i_1;
  assign _149_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" *) dmi_read_log_data;
  assign _150_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" *) { 61'h0000000000000000, terminated, core_stopped_i, stopping };
  assign _151_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) { 32'h00000000, core_dbg_core_dbg_maxvl, core_dbg_core_dbg_vl, core_dbg_core_dbg_srcstep, core_dbg_core_dbg_dststep, core_dbg_core_dbg_subvl, core_dbg_core_dbg_svstep };
  always @* begin
    if (\initial ) begin end
    _021_ = 1'h0;
  end
  always @* begin
      \initial  <= _021_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi_read_log_data <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi_read_log_data_1 <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi_req_i_1 <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      do_dmi_log_rd <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      do_icreset <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      do_reset <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      do_step <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      gspr_index <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      log_dmi_addr <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      stopping <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      terminated <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \dmi_read_log_data$next ;
  end
  always @(posedge clk) begin
      dmi_read_log_data <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \dmi_read_log_data_1$next ;
  end
  always @(posedge clk) begin
      dmi_read_log_data_1 <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \log_dmi_addr$next ;
  end
  always @(posedge clk) begin
      log_dmi_addr <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \gspr_index$next ;
  end
  always @(posedge clk) begin
      gspr_index <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \stopping$next ;
  end
  always @(posedge clk) begin
      stopping <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \terminated$next ;
  end
  always @(posedge clk) begin
      terminated <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \dmi_req_i_1$next ;
  end
  always @(posedge clk) begin
      dmi_req_i_1 <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \do_dmi_log_rd$next ;
  end
  always @(posedge clk) begin
      do_dmi_log_rd <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \do_icreset$next ;
  end
  always @(posedge clk) begin
      do_icreset <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \do_reset$next ;
  end
  always @(posedge clk) begin
      do_reset <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \do_step$next ;
  end
  always @(posedge clk) begin
      do_step <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _031_;
    (* src = "libresoc.v:51007.5-51007.29" *)
    casez (\initial )
      /* src = "libresoc.v:51007.9-51007.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *)
    casez (dmi_addr_i)
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _031_ = d_gpr_ack;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _031_ = d_cr_ack;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _031_ = d_xer_ack;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _031_ = dmi_req_i;
        end
    endcase
  end
  always @* begin
      dmi_ack_o <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _029_;
    (* src = "libresoc.v:51025.5-51025.29" *)
    casez (\initial )
      /* src = "libresoc.v:51025.9-51025.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *)
    casez (dmi_addr_i)
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _029_ = dmi_req_i;
        end
      default:
          _029_ = 1'h0;
    endcase
  end
  always @* begin
      d_gpr_req <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _037_;
    (* src = "libresoc.v:51035.5-51035.29" *)
    casez (\initial )
      /* src = "libresoc.v:51035.9-51035.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _037_ = 1'h0;
        end
      default:
          _037_ = dmi_req_i;
    endcase
  end
  always @* begin
      \dmi_req_i_1$next  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _088_;
    (* src = "libresoc.v:51044.5-51044.29" *)
    casez (\initial )
      /* src = "libresoc.v:51044.9-51044.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$67 , \$63  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _053_ = _062_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _062_ = _070_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$73 , \$71 , \$69  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                    begin
                      _070_ = _085_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" *)
                      casez (dmi_din[1])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _078_ = 1'h0;
                          end
                        default:
                            _078_ = terminated;
                      endcase
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" *)
                      casez (dmi_din[3])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _083_ = 1'h0;
                          end
                        default:
                            _083_ = _078_;
                      endcase
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" *)
                      casez (dmi_din[4])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _085_ = 1'h0;
                          end
                        default:
                            _085_ = _083_;
                      endcase
                    end
                  default:
                      _070_ = terminated;
                endcase
              end
            default:
                _062_ = terminated;
          endcase
        end
      default:
          _053_ = terminated;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" *)
    casez (terminate_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = 1'h1;
        end
      default:
          _087_ = _053_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _088_ = 1'h0;
        end
      default:
          _088_ = _087_;
    endcase
  end
  always @* begin
      \terminated$next  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _086_;
    (* src = "libresoc.v:51094.5-51094.29" *)
    casez (\initial )
      /* src = "libresoc.v:51094.9-51094.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$81 , \$77  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _051_ = _061_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _061_ = _069_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$87 , \$85 , \$83  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                    begin
                      _069_ = _082_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:214" *)
                      casez (dmi_din[0])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _077_ = 1'h1;
                          end
                        default:
                            _077_ = stopping;
                      endcase
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:221" *)
                      casez (dmi_din[4])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _082_ = 1'h0;
                          end
                        default:
                            _082_ = _077_;
                      endcase
                    end
                  default:
                      _069_ = stopping;
                endcase
              end
            default:
                _061_ = stopping;
          endcase
        end
      default:
          _051_ = stopping;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:250" *)
    casez (terminate_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _084_ = 1'h1;
        end
      default:
          _084_ = _051_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _086_ = 1'h0;
        end
      default:
          _086_ = _084_;
    endcase
  end
  always @* begin
      \stopping$next  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _075_;
    (* src = "libresoc.v:51138.5-51138.29" *)
    casez (\initial )
      /* src = "libresoc.v:51138.9-51138.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$95 , \$91  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _047_ = _059_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _059_ = _067_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$101 , \$99 , \$97  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                      _067_ = gspr_index;
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b?1?:
                    begin
                      _067_ = dmi_din[6:0];
                    end
                  default:
                      _067_ = gspr_index;
                endcase
              end
            default:
                _059_ = gspr_index;
          endcase
        end
      default:
          _047_ = gspr_index;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _075_ = 7'h00;
        end
      default:
          _075_ = _047_;
    endcase
  end
  always @* begin
      \gspr_index$next  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _076_;
    (* src = "libresoc.v:51166.5-51166.29" *)
    casez (\initial )
      /* src = "libresoc.v:51166.9-51166.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$109 , \$105  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _049_ = _060_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _060_ = _068_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$115 , \$113 , \$111  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                      _068_ = log_dmi_addr;
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b?1?:
                      _068_ = log_dmi_addr;
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b1??:
                    begin
                      _068_ = dmi_din[31:0];
                    end
                  default:
                      _068_ = log_dmi_addr;
                endcase
              end
            default:
                _060_ = log_dmi_addr;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _049_[31:2] = log_dmi_addr[31:2];
          _049_[1:0] = \$117 [1:0];
        end
      default:
          _049_ = log_dmi_addr;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _076_ = 32'd0;
        end
      default:
          _076_ = _049_;
    endcase
  end
  always @* begin
      \log_dmi_addr$next  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _035_;
    (* src = "libresoc.v:51200.5-51200.29" *)
    casez (\initial )
      /* src = "libresoc.v:51200.9-51200.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = 1'h0;
        end
      default:
          _035_ = dmi_read_log_data;
    endcase
  end
  always @* begin
      \dmi_read_log_data_1$next  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _033_;
    (* src = "libresoc.v:51209.5-51209.29" *)
    casez (\initial )
      /* src = "libresoc.v:51209.9-51209.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = 1'h0;
        end
      default:
          _033_ = \$122 ;
    endcase
  end
  always @* begin
      \dmi_read_log_data$next  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _028_;
    (* src = "libresoc.v:51218.5-51218.29" *)
    casez (\initial )
      /* src = "libresoc.v:51218.9-51218.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *)
    casez (dmi_addr_i)
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _028_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _028_ = dmi_req_i;
        end
      default:
          _028_ = 1'h0;
    endcase
  end
  always @* begin
      d_cr_req <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _030_;
    (* src = "libresoc.v:51231.5-51231.29" *)
    casez (\initial )
      /* src = "libresoc.v:51231.9-51231.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" *)
    casez (dmi_addr_i)
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _030_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
          _030_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _030_ = dmi_req_i;
        end
      default:
          _030_ = 1'h0;
    endcase
  end
  always @* begin
      d_xer_req <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _032_;
    (* src = "libresoc.v:51247.5-51247.29" *)
    casez (\initial )
      /* src = "libresoc.v:51247.9-51247.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" *)
    casez (dmi_addr_i)
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _032_ = stat_reg;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _032_ = core_dbg_pc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _032_ = core_dbg_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _032_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _032_ = d_gpr_data;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _032_ = { log_write_addr_o, log_dmi_addr };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _032_ = log_dmi_data;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _032_ = d_cr_data;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _032_ = d_xer_data;
        end
      default:
          _032_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dmi_dout <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _081_;
    (* src = "libresoc.v:51281.5-51281.29" *)
    casez (\initial )
      /* src = "libresoc.v:51281.9-51281.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$11 , \$7  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _045_ = _058_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _058_ = _066_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$17 , \$15 , \$13  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                    begin
                      _066_ = _074_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:216" *)
                      casez (dmi_din[3])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _074_ = 1'h1;
                          end
                        default:
                            _074_ = 1'h0;
                      endcase
                    end
                  default:
                      _066_ = 1'h0;
                endcase
              end
            default:
                _058_ = 1'h0;
          endcase
        end
      default:
          _045_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _081_ = 1'h0;
        end
      default:
          _081_ = _045_;
    endcase
  end
  always @* begin
      \do_step$next  <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _080_;
    (* src = "libresoc.v:51311.5-51311.29" *)
    casez (\initial )
      /* src = "libresoc.v:51311.9-51311.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$25 , \$21  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _043_ = _057_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _057_ = _065_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$31 , \$29 , \$27  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                    begin
                      _065_ = _073_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211" *)
                      casez (dmi_din[1])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _073_ = 1'h1;
                          end
                        default:
                            _073_ = 1'h0;
                      endcase
                    end
                  default:
                      _065_ = 1'h0;
                endcase
              end
            default:
                _057_ = 1'h0;
          endcase
        end
      default:
          _043_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _080_ = 1'h0;
        end
      default:
          _080_ = _043_;
    endcase
  end
  always @* begin
      \do_reset$next  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _079_;
    (* src = "libresoc.v:51341.5-51341.29" *)
    casez (\initial )
      /* src = "libresoc.v:51341.9-51341.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$39 , \$35  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _041_ = _056_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _056_ = _064_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$45 , \$43 , \$41  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                    begin
                      _064_ = _072_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" *)
                      casez (dmi_din[2])
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _072_ = 1'h1;
                          end
                        default:
                            _072_ = 1'h0;
                      endcase
                    end
                  default:
                      _064_ = 1'h0;
                endcase
              end
            default:
                _056_ = 1'h0;
          endcase
        end
      default:
          _041_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _079_ = 1'h0;
        end
      default:
          _079_ = _041_;
    endcase
  end
  always @* begin
      \do_icreset$next  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _071_;
    (* src = "libresoc.v:51371.5-51371.29" *)
    casez (\initial )
      /* src = "libresoc.v:51371.9-51371.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" *)
    casez ({ \$53 , \$49  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _039_ = _055_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:204" *)
          casez (dmi_we_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _055_ = _063_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" *)
                casez ({ \$59 , \$57 , \$55  })
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b??1:
                      _063_ = 1'h0;
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b?1?:
                      _063_ = 1'h0;
                  /* src = "libresoc.v:0.0-0.0" */
                  3'b1??:
                    begin
                      _063_ = 1'h1;
                    end
                  default:
                      _063_ = 1'h0;
                endcase
              end
            default:
                _055_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _039_ = 1'h1;
        end
      default:
          _039_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _071_ = 1'h0;
        end
      default:
          _071_ = _039_;
    endcase
  end
  always @* begin
      \do_dmi_log_rd$next  <= _011_;
  end
  assign \$9  = _133_;
  assign \$99  = _108_;
  assign \$101  = _109_;
  assign \$103  = _134_;
  assign \$105  = _090_;
  assign \$107  = _135_;
  assign \$109  = _091_;
  assign \$111  = _110_;
  assign \$113  = _111_;
  assign \$115  = _112_;
  assign \$118  = _089_;
  assign \$11  = _092_;
  assign \$120  = _113_;
  assign \$122  = _093_;
  assign \$124  = _136_;
  assign \$126  = _094_;
  assign \$13  = _114_;
  assign \$15  = _115_;
  assign \$17  = _116_;
  assign \$1  = _150_;
  assign \$19  = _137_;
  assign \$21  = _095_;
  assign \$23  = _138_;
  assign \$25  = _096_;
  assign \$27  = _117_;
  assign \$29  = _118_;
  assign \$31  = _119_;
  assign \$33  = _139_;
  assign \$35  = _097_;
  assign \$37  = _140_;
  assign \$3  = _151_;
  assign \$39  = _098_;
  assign \$41  = _120_;
  assign \$43  = _121_;
  assign \$45  = _122_;
  assign \$47  = _141_;
  assign \$49  = _099_;
  assign \$51  = _142_;
  assign \$53  = _100_;
  assign \$55  = _123_;
  assign \$57  = _124_;
  assign \$5  = _143_;
  assign \$59  = _125_;
  assign \$61  = _144_;
  assign \$63  = _101_;
  assign \$65  = _145_;
  assign \$67  = _102_;
  assign \$69  = _126_;
  assign \$71  = _127_;
  assign \$73  = _128_;
  assign \$75  = _146_;
  assign \$77  = _103_;
  assign \$7  = _104_;
  assign \$79  = _147_;
  assign \$81  = _105_;
  assign \$83  = _129_;
  assign \$85  = _130_;
  assign \$87  = _131_;
  assign \$89  = _148_;
  assign \$91  = _106_;
  assign \$93  = _149_;
  assign \$95  = _107_;
  assign \$97  = _132_;
  assign \$117  = \$118 ;
  assign log_write_addr_o = 32'd0;
  assign log_dmi_data = 64'h0000000000000000;
  assign terminated_o = terminated;
  assign icache_rst_o = do_icreset;
  assign core_rst_o = do_reset;
  assign core_stop_o = \$126 ;
  assign d_gpr_addr = gspr_index;
  assign stat_reg = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:51417.1-53467.10" *)
module dec(bigendian, opcode_in, ALU_rc_sel, ALU_internal_op, ALU_SPR, ALU_function_unit, ALU_in1_sel, ALU_in2_sel, ALU_cr_out, ALU_ldst_len, ALU_inv_a, ALU_inv_out, ALU_cry_in, ALU_cry_out, ALU_is_32b, ALU_sgn, ALU_RA, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_Rc, ALU_OE, ALU_BD, ALU_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:53028.3-53061.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:53062.3-53095.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:52688.3-52721.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:52790.3-52823.6" *)
  reg _03_;
  (* src = "libresoc.v:52892.3-52925.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:52960.3-52993.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:52994.3-53027.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:52926.3-52959.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:52722.3-52755.6" *)
  reg _08_;
  (* src = "libresoc.v:52756.3-52789.6" *)
  reg _09_;
  (* src = "libresoc.v:52824.3-52857.6" *)
  reg _10_;
  (* src = "libresoc.v:53096.3-53129.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:52654.3-52687.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:52858.3-52891.6" *)
  reg _13_;
  (* src = "libresoc.v:51418.7-51418.20" *)
  reg _14_;
  (* src = "libresoc.v:53028.3-53061.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:53062.3-53095.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:52688.3-52721.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:52790.3-52823.6" *)
  reg _18_;
  (* src = "libresoc.v:52892.3-52925.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:52960.3-52993.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:52994.3-53027.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:52926.3-52959.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:52722.3-52755.6" *)
  reg _23_;
  (* src = "libresoc.v:52756.3-52789.6" *)
  reg _24_;
  (* src = "libresoc.v:52824.3-52857.6" *)
  reg _25_;
  (* src = "libresoc.v:53096.3-53129.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:52654.3-52687.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:52858.3-52891.6" *)
  reg _28_;
  (* src = "libresoc.v:52619.17-52619.211" *)
  wire [31:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire ALU_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] ALU_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] ALU_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] ALU_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] ALU_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] ALU_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] ALU_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] ALU_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire ALU_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] ALU_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire ALU_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output ALU_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] ALU_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] ALU_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output ALU_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] ALU_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] ALU_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] ALU_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ALU_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] ALU_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] ALU_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_cr_out;
  reg [2:0] ALU_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_cry_in;
  reg [1:0] ALU_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_cry_out;
  reg ALU_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec19_ALU_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec19_ALU_dec19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec19_ALU_dec19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec19_ALU_dec19_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec19_ALU_dec19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec19_ALU_dec19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec19_ALU_dec19_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec19_ALU_dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec19_ALU_dec19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec19_ALU_dec19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec19_ALU_dec19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec19_ALU_dec19_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec19_ALU_dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec19_ALU_dec19_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec19_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_ALU_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_ALU_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_ALU_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_ALU_dec31_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] ALU_dec31_ALU_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] ALU_dec31_ALU_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_ALU_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] ALU_dec31_ALU_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_ALU_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_ALU_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_ALU_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] ALU_dec31_ALU_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] ALU_dec31_ALU_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire ALU_dec31_ALU_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] ALU_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] ALU_function_unit;
  reg [13:0] ALU_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] ALU_in1_sel;
  reg [2:0] ALU_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_in2_sel;
  reg [3:0] ALU_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] ALU_internal_op;
  reg [6:0] ALU_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_inv_a;
  reg ALU_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_inv_out;
  reg ALU_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_is_32b;
  reg ALU_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] ALU_ldst_len;
  reg [3:0] ALU_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] ALU_rc_sel;
  reg [1:0] ALU_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output ALU_sgn;
  reg ALU_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] ALU_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:51418.7-51418.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _29_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:52620.13-52636.4" *)
  ALU_dec19 ALU_dec19 (
    .ALU_dec19_cr_in(ALU_dec19_ALU_dec19_cr_in),
    .ALU_dec19_cr_out(ALU_dec19_ALU_dec19_cr_out),
    .ALU_dec19_cry_in(ALU_dec19_ALU_dec19_cry_in),
    .ALU_dec19_cry_out(ALU_dec19_ALU_dec19_cry_out),
    .ALU_dec19_function_unit(ALU_dec19_ALU_dec19_function_unit),
    .ALU_dec19_in1_sel(ALU_dec19_ALU_dec19_in1_sel),
    .ALU_dec19_in2_sel(ALU_dec19_ALU_dec19_in2_sel),
    .ALU_dec19_internal_op(ALU_dec19_ALU_dec19_internal_op),
    .ALU_dec19_inv_a(ALU_dec19_ALU_dec19_inv_a),
    .ALU_dec19_inv_out(ALU_dec19_ALU_dec19_inv_out),
    .ALU_dec19_is_32b(ALU_dec19_ALU_dec19_is_32b),
    .ALU_dec19_ldst_len(ALU_dec19_ALU_dec19_ldst_len),
    .ALU_dec19_rc_sel(ALU_dec19_ALU_dec19_rc_sel),
    .ALU_dec19_sgn(ALU_dec19_ALU_dec19_sgn),
    .opcode_in(ALU_dec19_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:52637.13-52653.4" *)
  ALU_dec31 ALU_dec31 (
    .ALU_dec31_cr_in(ALU_dec31_ALU_dec31_cr_in),
    .ALU_dec31_cr_out(ALU_dec31_ALU_dec31_cr_out),
    .ALU_dec31_cry_in(ALU_dec31_ALU_dec31_cry_in),
    .ALU_dec31_cry_out(ALU_dec31_ALU_dec31_cry_out),
    .ALU_dec31_function_unit(ALU_dec31_ALU_dec31_function_unit),
    .ALU_dec31_in1_sel(ALU_dec31_ALU_dec31_in1_sel),
    .ALU_dec31_in2_sel(ALU_dec31_ALU_dec31_in2_sel),
    .ALU_dec31_internal_op(ALU_dec31_ALU_dec31_internal_op),
    .ALU_dec31_inv_a(ALU_dec31_ALU_dec31_inv_a),
    .ALU_dec31_inv_out(ALU_dec31_ALU_dec31_inv_out),
    .ALU_dec31_is_32b(ALU_dec31_ALU_dec31_is_32b),
    .ALU_dec31_ldst_len(ALU_dec31_ALU_dec31_ldst_len),
    .ALU_dec31_rc_sel(ALU_dec31_ALU_dec31_rc_sel),
    .ALU_dec31_sgn(ALU_dec31_ALU_dec31_sgn),
    .opcode_in(ALU_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:52655.5-52655.29" *)
    casez (\initial )
      /* src = "libresoc.v:52655.9-52655.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _27_ = ALU_dec19_ALU_dec19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _27_ = ALU_dec31_ALU_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _27_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_rc_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:52689.5-52689.29" *)
    casez (\initial )
      /* src = "libresoc.v:52689.9-52689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _17_ = ALU_dec19_ALU_dec19_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _17_ = ALU_dec31_ALU_dec31_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _17_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _17_ = 2'h1;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ALU_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:52723.5-52723.29" *)
    casez (\initial )
      /* src = "libresoc.v:52723.9-52723.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _23_ = ALU_dec19_ALU_dec19_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _23_ = ALU_dec31_ALU_dec31_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _23_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _23_ = 1'h1;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:52757.5-52757.29" *)
    casez (\initial )
      /* src = "libresoc.v:52757.9-52757.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _24_ = ALU_dec19_ALU_dec19_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _24_ = ALU_dec31_ALU_dec31_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:52791.5-52791.29" *)
    casez (\initial )
      /* src = "libresoc.v:52791.9-52791.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _18_ = ALU_dec19_ALU_dec19_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _18_ = ALU_dec31_ALU_dec31_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _18_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _18_ = 1'h1;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:52825.5-52825.29" *)
    casez (\initial )
      /* src = "libresoc.v:52825.9-52825.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _25_ = ALU_dec19_ALU_dec19_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _25_ = ALU_dec31_ALU_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:52859.5-52859.29" *)
    casez (\initial )
      /* src = "libresoc.v:52859.9-52859.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _28_ = ALU_dec19_ALU_dec19_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _28_ = ALU_dec31_ALU_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _28_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      ALU_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:52893.5-52893.29" *)
    casez (\initial )
      /* src = "libresoc.v:52893.9-52893.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _19_ = ALU_dec19_ALU_dec19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _19_ = ALU_dec31_ALU_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _19_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _19_ = 14'h0002;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      ALU_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:52927.5-52927.29" *)
    casez (\initial )
      /* src = "libresoc.v:52927.9-52927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _22_ = ALU_dec19_ALU_dec19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _22_ = ALU_dec31_ALU_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _22_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _22_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _22_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _22_ = 7'h02;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      ALU_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:52961.5-52961.29" *)
    casez (\initial )
      /* src = "libresoc.v:52961.9-52961.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _20_ = ALU_dec19_ALU_dec19_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _20_ = ALU_dec31_ALU_dec31_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _20_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _20_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _20_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _20_ = 3'h1;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:52995.5-52995.29" *)
    casez (\initial )
      /* src = "libresoc.v:52995.9-52995.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _21_ = ALU_dec19_ALU_dec19_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _21_ = ALU_dec31_ALU_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _21_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _21_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _21_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _21_ = 4'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _21_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _21_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _21_ = 4'h3;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:53029.5-53029.29" *)
    casez (\initial )
      /* src = "libresoc.v:53029.9-53029.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _15_ = ALU_dec19_ALU_dec19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = ALU_dec31_ALU_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:53063.5-53063.29" *)
    casez (\initial )
      /* src = "libresoc.v:53063.9-53063.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _16_ = ALU_dec19_ALU_dec19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = ALU_dec31_ALU_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _16_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _16_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      ALU_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:53097.5-53097.29" *)
    casez (\initial )
      /* src = "libresoc.v:53097.9-53097.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _26_ = ALU_dec19_ALU_dec19_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _26_ = ALU_dec31_ALU_dec31_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      ALU_ldst_len <= _11_;
  end
  assign \$1  = _29_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign ALU_SPR = opcode_in[20:11];
  assign ALU_MB = opcode_in[10:6];
  assign ALU_ME = opcode_in[5:1];
  assign ALU_SH = opcode_in[15:11];
  assign ALU_BC = opcode_in[10:6];
  assign ALU_TO = opcode_in[25:21];
  assign ALU_DS = opcode_in[15:2];
  assign ALU_D = opcode_in[15:0];
  assign ALU_BH = opcode_in[12:11];
  assign ALU_BI = opcode_in[20:16];
  assign ALU_BO = opcode_in[25:21];
  assign ALU_FXM = opcode_in[19:12];
  assign ALU_BT = opcode_in[25:21];
  assign ALU_BA = opcode_in[20:16];
  assign ALU_BB = opcode_in[15:11];
  assign ALU_CR = opcode_in[10:1];
  assign ALU_BF = opcode_in[25:23];
  assign ALU_BD = opcode_in[15:2];
  assign ALU_OE = opcode_in[10];
  assign ALU_Rc = opcode_in[0];
  assign ALU_AA = opcode_in[1];
  assign ALU_LK = opcode_in[0];
  assign ALU_LI = opcode_in[25:2];
  assign ALU_ME32 = opcode_in[5:1];
  assign ALU_MB32 = opcode_in[10:6];
  assign ALU_sh = { opcode_in[1], opcode_in[15:11] };
  assign ALU_SH32 = opcode_in[15:11];
  assign ALU_L = opcode_in[21];
  assign ALU_UI = opcode_in[15:0];
  assign ALU_SI = opcode_in[15:0];
  assign ALU_RB = opcode_in[15:11];
  assign ALU_RA = opcode_in[20:16];
  assign ALU_RT = opcode_in[25:21];
  assign ALU_RS = opcode_in[25:21];
  assign ALU_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign ALU_dec31_opcode_in = opcode_in;
  assign ALU_dec19_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:53471.1-54936.10" *)
module \dec$138 (bigendian, opcode_in, CR_rc_sel, CR_internal_op, CR_SPR, CR_function_unit, CR_cr_out, CR_Rc, CR_OE, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:54560.3-54572.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:54573.3-54585.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:54534.3-54546.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:54547.3-54559.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:54586.3-54598.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:53472.7-53472.20" *)
  reg _05_;
  (* src = "libresoc.v:54560.3-54572.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:54573.3-54585.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:54534.3-54546.6" *)
  reg [13:0] _08_;
  (* src = "libresoc.v:54547.3-54559.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:54586.3-54598.6" *)
  reg [1:0] _10_;
  (* src = "libresoc.v:54517.17-54517.211" *)
  wire [31:0] _11_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire CR_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] CR_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] CR_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] CR_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] CR_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] CR_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] CR_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] CR_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire CR_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] CR_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire CR_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output CR_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] CR_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output CR_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] CR_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] CR_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] CR_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] CR_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] CR_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] CR_cr_out;
  reg [2:0] CR_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec19_CR_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec19_CR_dec19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec19_CR_dec19_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec19_CR_dec19_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec19_CR_dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec19_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_CR_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] CR_dec31_CR_dec31_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] CR_dec31_CR_dec31_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] CR_dec31_CR_dec31_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] CR_dec31_CR_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] CR_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] CR_function_unit;
  reg [13:0] CR_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] CR_internal_op;
  reg [6:0] CR_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] CR_rc_sel;
  reg [1:0] CR_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] CR_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:53472.7-53472.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _11_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:54518.12-54525.4" *)
  CR_dec19 CR_dec19 (
    .CR_dec19_cr_in(CR_dec19_CR_dec19_cr_in),
    .CR_dec19_cr_out(CR_dec19_CR_dec19_cr_out),
    .CR_dec19_function_unit(CR_dec19_CR_dec19_function_unit),
    .CR_dec19_internal_op(CR_dec19_CR_dec19_internal_op),
    .CR_dec19_rc_sel(CR_dec19_CR_dec19_rc_sel),
    .opcode_in(CR_dec19_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:54526.12-54533.4" *)
  CR_dec31 CR_dec31 (
    .CR_dec31_cr_in(CR_dec31_CR_dec31_cr_in),
    .CR_dec31_cr_out(CR_dec31_CR_dec31_cr_out),
    .CR_dec31_function_unit(CR_dec31_CR_dec31_function_unit),
    .CR_dec31_internal_op(CR_dec31_CR_dec31_internal_op),
    .CR_dec31_rc_sel(CR_dec31_CR_dec31_rc_sel),
    .opcode_in(CR_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:54535.5-54535.29" *)
    casez (\initial )
      /* src = "libresoc.v:54535.9-54535.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _08_ = CR_dec19_CR_dec19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _08_ = CR_dec31_CR_dec31_function_unit;
        end
      default:
          _08_ = 14'h0000;
    endcase
  end
  always @* begin
      CR_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:54548.5-54548.29" *)
    casez (\initial )
      /* src = "libresoc.v:54548.9-54548.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _09_ = CR_dec19_CR_dec19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _09_ = CR_dec31_CR_dec31_internal_op;
        end
      default:
          _09_ = 7'h00;
    endcase
  end
  always @* begin
      CR_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _06_;
    (* src = "libresoc.v:54561.5-54561.29" *)
    casez (\initial )
      /* src = "libresoc.v:54561.9-54561.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _06_ = CR_dec19_CR_dec19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _06_ = CR_dec31_CR_dec31_cr_in;
        end
      default:
          _06_ = 3'h0;
    endcase
  end
  always @* begin
      CR_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _07_;
    (* src = "libresoc.v:54574.5-54574.29" *)
    casez (\initial )
      /* src = "libresoc.v:54574.9-54574.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _07_ = CR_dec19_CR_dec19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _07_ = CR_dec31_CR_dec31_cr_out;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      CR_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:54587.5-54587.29" *)
    casez (\initial )
      /* src = "libresoc.v:54587.9-54587.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _10_ = CR_dec19_CR_dec19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _10_ = CR_dec31_CR_dec31_rc_sel;
        end
      default:
          _10_ = 2'h0;
    endcase
  end
  always @* begin
      CR_rc_sel <= _04_;
  end
  assign \$1  = _11_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign CR_SPR = opcode_in[20:11];
  assign CR_MB = opcode_in[10:6];
  assign CR_ME = opcode_in[5:1];
  assign CR_SH = opcode_in[15:11];
  assign CR_BC = opcode_in[10:6];
  assign CR_TO = opcode_in[25:21];
  assign CR_DS = opcode_in[15:2];
  assign CR_D = opcode_in[15:0];
  assign CR_BH = opcode_in[12:11];
  assign CR_BI = opcode_in[20:16];
  assign CR_BO = opcode_in[25:21];
  assign CR_FXM = opcode_in[19:12];
  assign CR_BT = opcode_in[25:21];
  assign CR_BA = opcode_in[20:16];
  assign CR_BB = opcode_in[15:11];
  assign CR_CR = opcode_in[10:1];
  assign CR_BF = opcode_in[25:23];
  assign CR_BD = opcode_in[15:2];
  assign CR_OE = opcode_in[10];
  assign CR_Rc = opcode_in[0];
  assign CR_AA = opcode_in[1];
  assign CR_LK = opcode_in[0];
  assign CR_LI = opcode_in[25:2];
  assign CR_ME32 = opcode_in[5:1];
  assign CR_MB32 = opcode_in[10:6];
  assign CR_sh = { opcode_in[1], opcode_in[15:11] };
  assign CR_SH32 = opcode_in[15:11];
  assign CR_L = opcode_in[21];
  assign CR_UI = opcode_in[15:0];
  assign CR_SI = opcode_in[15:0];
  assign CR_RB = opcode_in[15:11];
  assign CR_RA = opcode_in[20:16];
  assign CR_RT = opcode_in[25:21];
  assign CR_RS = opcode_in[25:21];
  assign CR_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign CR_dec31_opcode_in = opcode_in;
  assign CR_dec19_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:54940.1-56385.10" *)
module \dec$141 (bigendian, opcode_in, BRANCH_rc_sel, BRANCH_internal_op, BRANCH_SPR, BRANCH_function_unit, BRANCH_in2_sel, BRANCH_cr_out, BRANCH_is_32b, BRANCH_lk, BRANCH_LK, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_Rc, BRANCH_OE, BRANCH_BD, BRANCH_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:55969.3-55984.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:55985.3-56000.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:55921.3-55936.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:55953.3-55968.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:55937.3-55952.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:56017.3-56032.6" *)
  reg _05_;
  (* src = "libresoc.v:56033.3-56048.6" *)
  reg _06_;
  (* src = "libresoc.v:56001.3-56016.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:54941.7-54941.20" *)
  reg _08_;
  (* src = "libresoc.v:55969.3-55984.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:55985.3-56000.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:55921.3-55936.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:55953.3-55968.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:55937.3-55952.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:56017.3-56032.6" *)
  reg _14_;
  (* src = "libresoc.v:56033.3-56048.6" *)
  reg _15_;
  (* src = "libresoc.v:56001.3-56016.6" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:55909.17-55909.211" *)
  wire [31:0] _17_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire BRANCH_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] BRANCH_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] BRANCH_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] BRANCH_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] BRANCH_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] BRANCH_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] BRANCH_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] BRANCH_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire BRANCH_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] BRANCH_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output BRANCH_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output BRANCH_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] BRANCH_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output BRANCH_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BRANCH_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] BRANCH_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] BRANCH_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] BRANCH_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] BRANCH_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] BRANCH_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] BRANCH_cr_out;
  reg [2:0] BRANCH_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] BRANCH_dec19_BRANCH_dec19_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] BRANCH_dec19_BRANCH_dec19_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] BRANCH_dec19_BRANCH_dec19_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] BRANCH_dec19_BRANCH_dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire BRANCH_dec19_BRANCH_dec19_is_32b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire BRANCH_dec19_BRANCH_dec19_lk;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] BRANCH_dec19_BRANCH_dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] BRANCH_dec19_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] BRANCH_function_unit;
  reg [13:0] BRANCH_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] BRANCH_in2_sel;
  reg [3:0] BRANCH_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] BRANCH_internal_op;
  reg [6:0] BRANCH_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output BRANCH_is_32b;
  reg BRANCH_is_32b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output BRANCH_lk;
  reg BRANCH_lk;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] BRANCH_rc_sel;
  reg [1:0] BRANCH_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] BRANCH_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:54941.7-54941.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _17_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:55910.16-55920.4" *)
  BRANCH_dec19 BRANCH_dec19 (
    .BRANCH_dec19_cr_in(BRANCH_dec19_BRANCH_dec19_cr_in),
    .BRANCH_dec19_cr_out(BRANCH_dec19_BRANCH_dec19_cr_out),
    .BRANCH_dec19_function_unit(BRANCH_dec19_BRANCH_dec19_function_unit),
    .BRANCH_dec19_in2_sel(BRANCH_dec19_BRANCH_dec19_in2_sel),
    .BRANCH_dec19_internal_op(BRANCH_dec19_BRANCH_dec19_internal_op),
    .BRANCH_dec19_is_32b(BRANCH_dec19_BRANCH_dec19_is_32b),
    .BRANCH_dec19_lk(BRANCH_dec19_BRANCH_dec19_lk),
    .BRANCH_dec19_rc_sel(BRANCH_dec19_BRANCH_dec19_rc_sel),
    .opcode_in(BRANCH_dec19_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:55922.5-55922.29" *)
    casez (\initial )
      /* src = "libresoc.v:55922.9-55922.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _11_ = BRANCH_dec19_BRANCH_dec19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _11_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _11_ = 14'h0020;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      BRANCH_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:55938.5-55938.29" *)
    casez (\initial )
      /* src = "libresoc.v:55938.9-55938.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _13_ = BRANCH_dec19_BRANCH_dec19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _13_ = 7'h06;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _13_ = 7'h07;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      BRANCH_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:55954.5-55954.29" *)
    casez (\initial )
      /* src = "libresoc.v:55954.9-55954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _12_ = BRANCH_dec19_BRANCH_dec19_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _12_ = 4'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _12_ = 4'h7;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      BRANCH_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:55970.5-55970.29" *)
    casez (\initial )
      /* src = "libresoc.v:55970.9-55970.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _09_ = BRANCH_dec19_BRANCH_dec19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _09_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _09_ = 3'h2;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      BRANCH_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:55986.5-55986.29" *)
    casez (\initial )
      /* src = "libresoc.v:55986.9-55986.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _10_ = BRANCH_dec19_BRANCH_dec19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _10_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _10_ = 3'h0;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      BRANCH_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:56002.5-56002.29" *)
    casez (\initial )
      /* src = "libresoc.v:56002.9-56002.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _16_ = BRANCH_dec19_BRANCH_dec19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _16_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _16_ = 2'h0;
        end
      default:
          _16_ = 2'h0;
    endcase
  end
  always @* begin
      BRANCH_rc_sel <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:56018.5-56018.29" *)
    casez (\initial )
      /* src = "libresoc.v:56018.9-56018.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _14_ = BRANCH_dec19_BRANCH_dec19_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      BRANCH_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:56034.5-56034.29" *)
    casez (\initial )
      /* src = "libresoc.v:56034.9-56034.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _15_ = BRANCH_dec19_BRANCH_dec19_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _15_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _15_ = 1'h1;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      BRANCH_lk <= _06_;
  end
  assign \$1  = _17_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign BRANCH_SPR = opcode_in[20:11];
  assign BRANCH_MB = opcode_in[10:6];
  assign BRANCH_ME = opcode_in[5:1];
  assign BRANCH_SH = opcode_in[15:11];
  assign BRANCH_BC = opcode_in[10:6];
  assign BRANCH_TO = opcode_in[25:21];
  assign BRANCH_DS = opcode_in[15:2];
  assign BRANCH_D = opcode_in[15:0];
  assign BRANCH_BH = opcode_in[12:11];
  assign BRANCH_BI = opcode_in[20:16];
  assign BRANCH_BO = opcode_in[25:21];
  assign BRANCH_FXM = opcode_in[19:12];
  assign BRANCH_BT = opcode_in[25:21];
  assign BRANCH_BA = opcode_in[20:16];
  assign BRANCH_BB = opcode_in[15:11];
  assign BRANCH_CR = opcode_in[10:1];
  assign BRANCH_BF = opcode_in[25:23];
  assign BRANCH_BD = opcode_in[15:2];
  assign BRANCH_OE = opcode_in[10];
  assign BRANCH_Rc = opcode_in[0];
  assign BRANCH_AA = opcode_in[1];
  assign BRANCH_LK = opcode_in[0];
  assign BRANCH_LI = opcode_in[25:2];
  assign BRANCH_ME32 = opcode_in[5:1];
  assign BRANCH_MB32 = opcode_in[10:6];
  assign BRANCH_sh = { opcode_in[1], opcode_in[15:11] };
  assign BRANCH_SH32 = opcode_in[15:11];
  assign BRANCH_L = opcode_in[21];
  assign BRANCH_UI = opcode_in[15:0];
  assign BRANCH_SI = opcode_in[15:0];
  assign BRANCH_RB = opcode_in[15:11];
  assign BRANCH_RA = opcode_in[20:16];
  assign BRANCH_RT = opcode_in[25:21];
  assign BRANCH_RS = opcode_in[25:21];
  assign BRANCH_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign BRANCH_dec19_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:56389.1-58166.10" *)
module \dec$145 (bigendian, opcode_in, LOGICAL_rc_sel, LOGICAL_internal_op, LOGICAL_SPR, LOGICAL_function_unit, LOGICAL_in1_sel, LOGICAL_in2_sel, LOGICAL_cr_out, LOGICAL_ldst_len, LOGICAL_inv_a, LOGICAL_inv_out, LOGICAL_cry_in, LOGICAL_cry_out, LOGICAL_is_32b, LOGICAL_sgn, LOGICAL_RA, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_Rc, LOGICAL_OE, LOGICAL_BD, LOGICAL_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:57718.3-57745.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:57746.3-57773.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:57438.3-57465.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:57522.3-57549.6" *)
  reg _03_;
  (* src = "libresoc.v:57606.3-57633.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:57662.3-57689.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:57690.3-57717.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:57634.3-57661.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:57466.3-57493.6" *)
  reg _08_;
  (* src = "libresoc.v:57494.3-57521.6" *)
  reg _09_;
  (* src = "libresoc.v:57550.3-57577.6" *)
  reg _10_;
  (* src = "libresoc.v:57774.3-57801.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:57802.3-57829.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:57578.3-57605.6" *)
  reg _13_;
  (* src = "libresoc.v:56390.7-56390.20" *)
  reg _14_;
  (* src = "libresoc.v:57718.3-57745.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:57746.3-57773.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:57438.3-57465.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:57522.3-57549.6" *)
  reg _18_;
  (* src = "libresoc.v:57606.3-57633.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:57662.3-57689.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:57690.3-57717.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:57634.3-57661.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:57466.3-57493.6" *)
  reg _23_;
  (* src = "libresoc.v:57494.3-57521.6" *)
  reg _24_;
  (* src = "libresoc.v:57550.3-57577.6" *)
  reg _25_;
  (* src = "libresoc.v:57774.3-57801.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:57802.3-57829.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:57578.3-57605.6" *)
  reg _28_;
  (* src = "libresoc.v:57420.17-57420.211" *)
  wire [31:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LOGICAL_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] LOGICAL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] LOGICAL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] LOGICAL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] LOGICAL_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] LOGICAL_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] LOGICAL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] LOGICAL_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LOGICAL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] LOGICAL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LOGICAL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output LOGICAL_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] LOGICAL_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] LOGICAL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output LOGICAL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] LOGICAL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] LOGICAL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] LOGICAL_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LOGICAL_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] LOGICAL_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] LOGICAL_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_cr_out;
  reg [2:0] LOGICAL_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_cry_in;
  reg [1:0] LOGICAL_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_cry_out;
  reg LOGICAL_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_LOGICAL_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_LOGICAL_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_LOGICAL_dec31_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LOGICAL_dec31_LOGICAL_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LOGICAL_dec31_LOGICAL_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_LOGICAL_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LOGICAL_dec31_LOGICAL_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_LOGICAL_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_LOGICAL_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_LOGICAL_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LOGICAL_dec31_LOGICAL_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LOGICAL_dec31_LOGICAL_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LOGICAL_dec31_LOGICAL_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LOGICAL_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LOGICAL_function_unit;
  reg [13:0] LOGICAL_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LOGICAL_in1_sel;
  reg [2:0] LOGICAL_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_in2_sel;
  reg [3:0] LOGICAL_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LOGICAL_internal_op;
  reg [6:0] LOGICAL_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_inv_a;
  reg LOGICAL_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_inv_out;
  reg LOGICAL_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_is_32b;
  reg LOGICAL_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LOGICAL_ldst_len;
  reg [3:0] LOGICAL_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LOGICAL_rc_sel;
  reg [1:0] LOGICAL_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LOGICAL_sgn;
  reg LOGICAL_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] LOGICAL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:56390.7-56390.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _29_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:57421.17-57437.4" *)
  LOGICAL_dec31 LOGICAL_dec31 (
    .LOGICAL_dec31_cr_in(LOGICAL_dec31_LOGICAL_dec31_cr_in),
    .LOGICAL_dec31_cr_out(LOGICAL_dec31_LOGICAL_dec31_cr_out),
    .LOGICAL_dec31_cry_in(LOGICAL_dec31_LOGICAL_dec31_cry_in),
    .LOGICAL_dec31_cry_out(LOGICAL_dec31_LOGICAL_dec31_cry_out),
    .LOGICAL_dec31_function_unit(LOGICAL_dec31_LOGICAL_dec31_function_unit),
    .LOGICAL_dec31_in1_sel(LOGICAL_dec31_LOGICAL_dec31_in1_sel),
    .LOGICAL_dec31_in2_sel(LOGICAL_dec31_LOGICAL_dec31_in2_sel),
    .LOGICAL_dec31_internal_op(LOGICAL_dec31_LOGICAL_dec31_internal_op),
    .LOGICAL_dec31_inv_a(LOGICAL_dec31_LOGICAL_dec31_inv_a),
    .LOGICAL_dec31_inv_out(LOGICAL_dec31_LOGICAL_dec31_inv_out),
    .LOGICAL_dec31_is_32b(LOGICAL_dec31_LOGICAL_dec31_is_32b),
    .LOGICAL_dec31_ldst_len(LOGICAL_dec31_LOGICAL_dec31_ldst_len),
    .LOGICAL_dec31_rc_sel(LOGICAL_dec31_LOGICAL_dec31_rc_sel),
    .LOGICAL_dec31_sgn(LOGICAL_dec31_LOGICAL_dec31_sgn),
    .opcode_in(LOGICAL_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:57439.5-57439.29" *)
    casez (\initial )
      /* src = "libresoc.v:57439.9-57439.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _17_ = LOGICAL_dec31_LOGICAL_dec31_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _17_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _17_ = 2'h0;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:57467.5-57467.29" *)
    casez (\initial )
      /* src = "libresoc.v:57467.9-57467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _23_ = LOGICAL_dec31_LOGICAL_dec31_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _23_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _23_ = 1'h0;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:57495.5-57495.29" *)
    casez (\initial )
      /* src = "libresoc.v:57495.9-57495.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _24_ = LOGICAL_dec31_LOGICAL_dec31_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:57523.5-57523.29" *)
    casez (\initial )
      /* src = "libresoc.v:57523.9-57523.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _18_ = LOGICAL_dec31_LOGICAL_dec31_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _18_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _18_ = 1'h0;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:57551.5-57551.29" *)
    casez (\initial )
      /* src = "libresoc.v:57551.9-57551.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _25_ = LOGICAL_dec31_LOGICAL_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:57579.5-57579.29" *)
    casez (\initial )
      /* src = "libresoc.v:57579.9-57579.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _28_ = LOGICAL_dec31_LOGICAL_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _28_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _28_ = 1'h0;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:57607.5-57607.29" *)
    casez (\initial )
      /* src = "libresoc.v:57607.9-57607.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _19_ = LOGICAL_dec31_LOGICAL_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _19_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _19_ = 14'h0010;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      LOGICAL_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:57635.5-57635.29" *)
    casez (\initial )
      /* src = "libresoc.v:57635.9-57635.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _22_ = LOGICAL_dec31_LOGICAL_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _22_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _22_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _22_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _22_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _22_ = 7'h43;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _22_ = 7'h43;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      LOGICAL_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:57663.5-57663.29" *)
    casez (\initial )
      /* src = "libresoc.v:57663.9-57663.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _20_ = LOGICAL_dec31_LOGICAL_dec31_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _20_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _20_ = 3'h4;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:57691.5-57691.29" *)
    casez (\initial )
      /* src = "libresoc.v:57691.9-57691.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _21_ = LOGICAL_dec31_LOGICAL_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _21_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _21_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _21_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _21_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _21_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _21_ = 4'h4;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:57719.5-57719.29" *)
    casez (\initial )
      /* src = "libresoc.v:57719.9-57719.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = LOGICAL_dec31_LOGICAL_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:57747.5-57747.29" *)
    casez (\initial )
      /* src = "libresoc.v:57747.9-57747.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = LOGICAL_dec31_LOGICAL_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _16_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LOGICAL_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:57775.5-57775.29" *)
    casez (\initial )
      /* src = "libresoc.v:57775.9-57775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _26_ = LOGICAL_dec31_LOGICAL_dec31_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _26_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _26_ = 4'h0;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      LOGICAL_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:57803.5-57803.29" *)
    casez (\initial )
      /* src = "libresoc.v:57803.9-57803.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _27_ = LOGICAL_dec31_LOGICAL_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _27_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _27_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _27_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _27_ = 2'h0;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      LOGICAL_rc_sel <= _12_;
  end
  assign \$1  = _29_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign LOGICAL_SPR = opcode_in[20:11];
  assign LOGICAL_MB = opcode_in[10:6];
  assign LOGICAL_ME = opcode_in[5:1];
  assign LOGICAL_SH = opcode_in[15:11];
  assign LOGICAL_BC = opcode_in[10:6];
  assign LOGICAL_TO = opcode_in[25:21];
  assign LOGICAL_DS = opcode_in[15:2];
  assign LOGICAL_D = opcode_in[15:0];
  assign LOGICAL_BH = opcode_in[12:11];
  assign LOGICAL_BI = opcode_in[20:16];
  assign LOGICAL_BO = opcode_in[25:21];
  assign LOGICAL_FXM = opcode_in[19:12];
  assign LOGICAL_BT = opcode_in[25:21];
  assign LOGICAL_BA = opcode_in[20:16];
  assign LOGICAL_BB = opcode_in[15:11];
  assign LOGICAL_CR = opcode_in[10:1];
  assign LOGICAL_BF = opcode_in[25:23];
  assign LOGICAL_BD = opcode_in[15:2];
  assign LOGICAL_OE = opcode_in[10];
  assign LOGICAL_Rc = opcode_in[0];
  assign LOGICAL_AA = opcode_in[1];
  assign LOGICAL_LK = opcode_in[0];
  assign LOGICAL_LI = opcode_in[25:2];
  assign LOGICAL_ME32 = opcode_in[5:1];
  assign LOGICAL_MB32 = opcode_in[10:6];
  assign LOGICAL_sh = { opcode_in[1], opcode_in[15:11] };
  assign LOGICAL_SH32 = opcode_in[15:11];
  assign LOGICAL_L = opcode_in[21];
  assign LOGICAL_UI = opcode_in[15:0];
  assign LOGICAL_SI = opcode_in[15:0];
  assign LOGICAL_RB = opcode_in[15:11];
  assign LOGICAL_RA = opcode_in[20:16];
  assign LOGICAL_RT = opcode_in[25:21];
  assign LOGICAL_RS = opcode_in[25:21];
  assign LOGICAL_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign LOGICAL_dec31_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:58170.1-59505.10" *)
module \dec$150 (bigendian, opcode_in, SPR_rc_sel, SPR_internal_op, SPR_SPR, SPR_function_unit, SPR_cr_out, SPR_is_32b, SPR_Rc, SPR_OE, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:59129.3-59138.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:59139.3-59148.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:59109.3-59118.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:59119.3-59128.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:59159.3-59168.6" *)
  reg _04_;
  (* src = "libresoc.v:59149.3-59158.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:58171.7-58171.20" *)
  reg _06_;
  (* src = "libresoc.v:59129.3-59138.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:59139.3-59148.6" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:59109.3-59118.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:59119.3-59128.6" *)
  reg [6:0] _10_;
  (* src = "libresoc.v:59159.3-59168.6" *)
  reg _11_;
  (* src = "libresoc.v:59149.3-59158.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:59099.17-59099.211" *)
  wire [31:0] _13_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SPR_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] SPR_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] SPR_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] SPR_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] SPR_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] SPR_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] SPR_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] SPR_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SPR_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] SPR_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SPR_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output SPR_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] SPR_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output SPR_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] SPR_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] SPR_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SPR_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] SPR_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] SPR_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SPR_cr_out;
  reg [2:0] SPR_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SPR_dec31_SPR_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SPR_dec31_SPR_dec31_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SPR_dec31_SPR_dec31_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SPR_dec31_SPR_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SPR_dec31_SPR_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SPR_dec31_SPR_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SPR_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SPR_function_unit;
  reg [13:0] SPR_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SPR_internal_op;
  reg [6:0] SPR_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SPR_is_32b;
  reg SPR_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SPR_rc_sel;
  reg [1:0] SPR_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] SPR_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:58171.7-58171.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _13_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:59100.13-59108.4" *)
  SPR_dec31 SPR_dec31 (
    .SPR_dec31_cr_in(SPR_dec31_SPR_dec31_cr_in),
    .SPR_dec31_cr_out(SPR_dec31_SPR_dec31_cr_out),
    .SPR_dec31_function_unit(SPR_dec31_SPR_dec31_function_unit),
    .SPR_dec31_internal_op(SPR_dec31_SPR_dec31_internal_op),
    .SPR_dec31_is_32b(SPR_dec31_SPR_dec31_is_32b),
    .SPR_dec31_rc_sel(SPR_dec31_SPR_dec31_rc_sel),
    .opcode_in(SPR_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _06_ = 1'h0;
  end
  always @* begin
      \initial  <= _06_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _09_;
    (* src = "libresoc.v:59110.5-59110.29" *)
    casez (\initial )
      /* src = "libresoc.v:59110.9-59110.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _09_ = SPR_dec31_SPR_dec31_function_unit;
        end
      default:
          _09_ = 14'h0000;
    endcase
  end
  always @* begin
      SPR_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _10_;
    (* src = "libresoc.v:59120.5-59120.29" *)
    casez (\initial )
      /* src = "libresoc.v:59120.9-59120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _10_ = SPR_dec31_SPR_dec31_internal_op;
        end
      default:
          _10_ = 7'h00;
    endcase
  end
  always @* begin
      SPR_internal_op <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _07_;
    (* src = "libresoc.v:59130.5-59130.29" *)
    casez (\initial )
      /* src = "libresoc.v:59130.9-59130.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _07_ = SPR_dec31_SPR_dec31_cr_in;
        end
      default:
          _07_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _08_;
    (* src = "libresoc.v:59140.5-59140.29" *)
    casez (\initial )
      /* src = "libresoc.v:59140.9-59140.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _08_ = SPR_dec31_SPR_dec31_cr_out;
        end
      default:
          _08_ = 3'h0;
    endcase
  end
  always @* begin
      SPR_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:59150.5-59150.29" *)
    casez (\initial )
      /* src = "libresoc.v:59150.9-59150.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _12_ = SPR_dec31_SPR_dec31_rc_sel;
        end
      default:
          _12_ = 2'h0;
    endcase
  end
  always @* begin
      SPR_rc_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _11_;
    (* src = "libresoc.v:59160.5-59160.29" *)
    casez (\initial )
      /* src = "libresoc.v:59160.9-59160.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _11_ = SPR_dec31_SPR_dec31_is_32b;
        end
      default:
          _11_ = 1'h0;
    endcase
  end
  always @* begin
      SPR_is_32b <= _04_;
  end
  assign \$1  = _13_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign SPR_SPR = opcode_in[20:11];
  assign SPR_MB = opcode_in[10:6];
  assign SPR_ME = opcode_in[5:1];
  assign SPR_SH = opcode_in[15:11];
  assign SPR_BC = opcode_in[10:6];
  assign SPR_TO = opcode_in[25:21];
  assign SPR_DS = opcode_in[15:2];
  assign SPR_D = opcode_in[15:0];
  assign SPR_BH = opcode_in[12:11];
  assign SPR_BI = opcode_in[20:16];
  assign SPR_BO = opcode_in[25:21];
  assign SPR_FXM = opcode_in[19:12];
  assign SPR_BT = opcode_in[25:21];
  assign SPR_BA = opcode_in[20:16];
  assign SPR_BB = opcode_in[15:11];
  assign SPR_CR = opcode_in[10:1];
  assign SPR_BF = opcode_in[25:23];
  assign SPR_BD = opcode_in[15:2];
  assign SPR_OE = opcode_in[10];
  assign SPR_Rc = opcode_in[0];
  assign SPR_AA = opcode_in[1];
  assign SPR_LK = opcode_in[0];
  assign SPR_LI = opcode_in[25:2];
  assign SPR_ME32 = opcode_in[5:1];
  assign SPR_MB32 = opcode_in[10:6];
  assign SPR_sh = { opcode_in[1], opcode_in[15:11] };
  assign SPR_SH32 = opcode_in[15:11];
  assign SPR_L = opcode_in[21];
  assign SPR_UI = opcode_in[15:0];
  assign SPR_SI = opcode_in[15:0];
  assign SPR_RB = opcode_in[15:11];
  assign SPR_RA = opcode_in[20:16];
  assign SPR_RT = opcode_in[25:21];
  assign SPR_RS = opcode_in[25:21];
  assign SPR_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign SPR_dec31_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:59509.1-61034.10" *)
module \dec$153 (bigendian, opcode_in, DIV_rc_sel, DIV_internal_op, DIV_SPR, DIV_function_unit, DIV_in1_sel, DIV_in2_sel, DIV_cr_out, DIV_ldst_len, DIV_inv_a, DIV_inv_out, DIV_cry_in, DIV_cry_out, DIV_is_32b, DIV_sgn, DIV_RA, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_Rc, DIV_OE, DIV_BD, DIV_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:60658.3-60667.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:60668.3-60677.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:60558.3-60567.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:60588.3-60597.6" *)
  reg _03_;
  (* src = "libresoc.v:60618.3-60627.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:60638.3-60647.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:60648.3-60657.6" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:60628.3-60637.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:60568.3-60577.6" *)
  reg _08_;
  (* src = "libresoc.v:60578.3-60587.6" *)
  reg _09_;
  (* src = "libresoc.v:60598.3-60607.6" *)
  reg _10_;
  (* src = "libresoc.v:60678.3-60687.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:60688.3-60697.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:60608.3-60617.6" *)
  reg _13_;
  (* src = "libresoc.v:59510.7-59510.20" *)
  reg _14_;
  (* src = "libresoc.v:60658.3-60667.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:60668.3-60677.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:60558.3-60567.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:60588.3-60597.6" *)
  reg _18_;
  (* src = "libresoc.v:60618.3-60627.6" *)
  reg [13:0] _19_;
  (* src = "libresoc.v:60638.3-60647.6" *)
  reg [2:0] _20_;
  (* src = "libresoc.v:60648.3-60657.6" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:60628.3-60637.6" *)
  reg [6:0] _22_;
  (* src = "libresoc.v:60568.3-60577.6" *)
  reg _23_;
  (* src = "libresoc.v:60578.3-60587.6" *)
  reg _24_;
  (* src = "libresoc.v:60598.3-60607.6" *)
  reg _25_;
  (* src = "libresoc.v:60678.3-60687.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:60688.3-60697.6" *)
  reg [1:0] _27_;
  (* src = "libresoc.v:60608.3-60617.6" *)
  reg _28_;
  (* src = "libresoc.v:60540.17-60540.211" *)
  wire [31:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire DIV_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] DIV_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] DIV_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] DIV_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] DIV_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] DIV_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] DIV_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] DIV_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire DIV_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] DIV_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire DIV_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output DIV_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] DIV_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] DIV_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output DIV_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] DIV_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] DIV_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] DIV_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] DIV_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] DIV_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] DIV_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_cr_out;
  reg [2:0] DIV_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_cry_in;
  reg [1:0] DIV_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_cry_out;
  reg DIV_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_DIV_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_DIV_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_DIV_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_DIV_dec31_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] DIV_dec31_DIV_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] DIV_dec31_DIV_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_DIV_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] DIV_dec31_DIV_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_DIV_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_DIV_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_DIV_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] DIV_dec31_DIV_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] DIV_dec31_DIV_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire DIV_dec31_DIV_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] DIV_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] DIV_function_unit;
  reg [13:0] DIV_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] DIV_in1_sel;
  reg [2:0] DIV_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_in2_sel;
  reg [3:0] DIV_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] DIV_internal_op;
  reg [6:0] DIV_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_inv_a;
  reg DIV_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_inv_out;
  reg DIV_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_is_32b;
  reg DIV_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] DIV_ldst_len;
  reg [3:0] DIV_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] DIV_rc_sel;
  reg [1:0] DIV_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output DIV_sgn;
  reg DIV_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] DIV_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:59510.7-59510.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _29_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:60541.13-60557.4" *)
  DIV_dec31 DIV_dec31 (
    .DIV_dec31_cr_in(DIV_dec31_DIV_dec31_cr_in),
    .DIV_dec31_cr_out(DIV_dec31_DIV_dec31_cr_out),
    .DIV_dec31_cry_in(DIV_dec31_DIV_dec31_cry_in),
    .DIV_dec31_cry_out(DIV_dec31_DIV_dec31_cry_out),
    .DIV_dec31_function_unit(DIV_dec31_DIV_dec31_function_unit),
    .DIV_dec31_in1_sel(DIV_dec31_DIV_dec31_in1_sel),
    .DIV_dec31_in2_sel(DIV_dec31_DIV_dec31_in2_sel),
    .DIV_dec31_internal_op(DIV_dec31_DIV_dec31_internal_op),
    .DIV_dec31_inv_a(DIV_dec31_DIV_dec31_inv_a),
    .DIV_dec31_inv_out(DIV_dec31_DIV_dec31_inv_out),
    .DIV_dec31_is_32b(DIV_dec31_DIV_dec31_is_32b),
    .DIV_dec31_ldst_len(DIV_dec31_DIV_dec31_ldst_len),
    .DIV_dec31_rc_sel(DIV_dec31_DIV_dec31_rc_sel),
    .DIV_dec31_sgn(DIV_dec31_DIV_dec31_sgn),
    .opcode_in(DIV_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
      \initial  <= _14_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _17_;
    (* src = "libresoc.v:60559.5-60559.29" *)
    casez (\initial )
      /* src = "libresoc.v:60559.9-60559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _17_ = DIV_dec31_DIV_dec31_cry_in;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_cry_in <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _23_;
    (* src = "libresoc.v:60569.5-60569.29" *)
    casez (\initial )
      /* src = "libresoc.v:60569.9-60569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _23_ = DIV_dec31_DIV_dec31_inv_a;
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_inv_a <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _24_;
    (* src = "libresoc.v:60579.5-60579.29" *)
    casez (\initial )
      /* src = "libresoc.v:60579.9-60579.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _24_ = DIV_dec31_DIV_dec31_inv_out;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_inv_out <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _18_;
    (* src = "libresoc.v:60589.5-60589.29" *)
    casez (\initial )
      /* src = "libresoc.v:60589.9-60589.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _18_ = DIV_dec31_DIV_dec31_cry_out;
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _25_;
    (* src = "libresoc.v:60599.5-60599.29" *)
    casez (\initial )
      /* src = "libresoc.v:60599.9-60599.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _25_ = DIV_dec31_DIV_dec31_is_32b;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_is_32b <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:60609.5-60609.29" *)
    casez (\initial )
      /* src = "libresoc.v:60609.9-60609.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _28_ = DIV_dec31_DIV_dec31_sgn;
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      DIV_sgn <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _19_;
    (* src = "libresoc.v:60619.5-60619.29" *)
    casez (\initial )
      /* src = "libresoc.v:60619.9-60619.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _19_ = DIV_dec31_DIV_dec31_function_unit;
        end
      default:
          _19_ = 14'h0000;
    endcase
  end
  always @* begin
      DIV_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _22_;
    (* src = "libresoc.v:60629.5-60629.29" *)
    casez (\initial )
      /* src = "libresoc.v:60629.9-60629.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _22_ = DIV_dec31_DIV_dec31_internal_op;
        end
      default:
          _22_ = 7'h00;
    endcase
  end
  always @* begin
      DIV_internal_op <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _20_;
    (* src = "libresoc.v:60639.5-60639.29" *)
    casez (\initial )
      /* src = "libresoc.v:60639.9-60639.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _20_ = DIV_dec31_DIV_dec31_in1_sel;
        end
      default:
          _20_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_in1_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _21_;
    (* src = "libresoc.v:60649.5-60649.29" *)
    casez (\initial )
      /* src = "libresoc.v:60649.9-60649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _21_ = DIV_dec31_DIV_dec31_in2_sel;
        end
      default:
          _21_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_in2_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _15_;
    (* src = "libresoc.v:60659.5-60659.29" *)
    casez (\initial )
      /* src = "libresoc.v:60659.9-60659.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = DIV_dec31_DIV_dec31_cr_in;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _16_;
    (* src = "libresoc.v:60669.5-60669.29" *)
    casez (\initial )
      /* src = "libresoc.v:60669.9-60669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = DIV_dec31_DIV_dec31_cr_out;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      DIV_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _26_;
    (* src = "libresoc.v:60679.5-60679.29" *)
    casez (\initial )
      /* src = "libresoc.v:60679.9-60679.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _26_ = DIV_dec31_DIV_dec31_ldst_len;
        end
      default:
          _26_ = 4'h0;
    endcase
  end
  always @* begin
      DIV_ldst_len <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _27_;
    (* src = "libresoc.v:60689.5-60689.29" *)
    casez (\initial )
      /* src = "libresoc.v:60689.9-60689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _27_ = DIV_dec31_DIV_dec31_rc_sel;
        end
      default:
          _27_ = 2'h0;
    endcase
  end
  always @* begin
      DIV_rc_sel <= _12_;
  end
  assign \$1  = _29_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign DIV_SPR = opcode_in[20:11];
  assign DIV_MB = opcode_in[10:6];
  assign DIV_ME = opcode_in[5:1];
  assign DIV_SH = opcode_in[15:11];
  assign DIV_BC = opcode_in[10:6];
  assign DIV_TO = opcode_in[25:21];
  assign DIV_DS = opcode_in[15:2];
  assign DIV_D = opcode_in[15:0];
  assign DIV_BH = opcode_in[12:11];
  assign DIV_BI = opcode_in[20:16];
  assign DIV_BO = opcode_in[25:21];
  assign DIV_FXM = opcode_in[19:12];
  assign DIV_BT = opcode_in[25:21];
  assign DIV_BA = opcode_in[20:16];
  assign DIV_BB = opcode_in[15:11];
  assign DIV_CR = opcode_in[10:1];
  assign DIV_BF = opcode_in[25:23];
  assign DIV_BD = opcode_in[15:2];
  assign DIV_OE = opcode_in[10];
  assign DIV_Rc = opcode_in[0];
  assign DIV_AA = opcode_in[1];
  assign DIV_LK = opcode_in[0];
  assign DIV_LI = opcode_in[25:2];
  assign DIV_ME32 = opcode_in[5:1];
  assign DIV_MB32 = opcode_in[10:6];
  assign DIV_sh = { opcode_in[1], opcode_in[15:11] };
  assign DIV_SH32 = opcode_in[15:11];
  assign DIV_L = opcode_in[21];
  assign DIV_UI = opcode_in[15:0];
  assign DIV_SI = opcode_in[15:0];
  assign DIV_RB = opcode_in[15:11];
  assign DIV_RA = opcode_in[20:16];
  assign DIV_RT = opcode_in[25:21];
  assign DIV_RS = opcode_in[25:21];
  assign DIV_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign DIV_dec31_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:61038.1-62459.10" *)
module \dec$158 (bigendian, opcode_in, MUL_rc_sel, MUL_internal_op, MUL_SPR, MUL_function_unit, MUL_in2_sel, MUL_cr_out, MUL_is_32b, MUL_sgn, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_Rc, MUL_OE, MUL_BD, MUL_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:62058.3-62070.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:62071.3-62083.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:62019.3-62031.6" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:62045.3-62057.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:62032.3-62044.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:62097.3-62109.6" *)
  reg _05_;
  (* src = "libresoc.v:62084.3-62096.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:62110.3-62122.6" *)
  reg _07_;
  (* src = "libresoc.v:61039.7-61039.20" *)
  reg _08_;
  (* src = "libresoc.v:62058.3-62070.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:62071.3-62083.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:62019.3-62031.6" *)
  reg [13:0] _11_;
  (* src = "libresoc.v:62045.3-62057.6" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:62032.3-62044.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:62097.3-62109.6" *)
  reg _14_;
  (* src = "libresoc.v:62084.3-62096.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:62110.3-62122.6" *)
  reg _16_;
  (* src = "libresoc.v:62007.17-62007.211" *)
  wire [31:0] _17_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire MUL_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] MUL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] MUL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] MUL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] MUL_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] MUL_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] MUL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] MUL_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire MUL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] MUL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire MUL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output MUL_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] MUL_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output MUL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] MUL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] MUL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] MUL_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MUL_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] MUL_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] MUL_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] MUL_cr_out;
  reg [2:0] MUL_cr_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_MUL_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] MUL_dec31_MUL_dec31_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] MUL_dec31_MUL_dec31_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] MUL_dec31_MUL_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] MUL_dec31_MUL_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_MUL_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] MUL_dec31_MUL_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire MUL_dec31_MUL_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] MUL_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] MUL_function_unit;
  reg [13:0] MUL_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] MUL_in2_sel;
  reg [3:0] MUL_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] MUL_internal_op;
  reg [6:0] MUL_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_is_32b;
  reg MUL_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] MUL_rc_sel;
  reg [1:0] MUL_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output MUL_sgn;
  reg MUL_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] MUL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:61039.7-61039.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _17_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:62008.13-62018.4" *)
  MUL_dec31 MUL_dec31 (
    .MUL_dec31_cr_in(MUL_dec31_MUL_dec31_cr_in),
    .MUL_dec31_cr_out(MUL_dec31_MUL_dec31_cr_out),
    .MUL_dec31_function_unit(MUL_dec31_MUL_dec31_function_unit),
    .MUL_dec31_in2_sel(MUL_dec31_MUL_dec31_in2_sel),
    .MUL_dec31_internal_op(MUL_dec31_MUL_dec31_internal_op),
    .MUL_dec31_is_32b(MUL_dec31_MUL_dec31_is_32b),
    .MUL_dec31_rc_sel(MUL_dec31_MUL_dec31_rc_sel),
    .MUL_dec31_sgn(MUL_dec31_MUL_dec31_sgn),
    .opcode_in(MUL_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:62020.5-62020.29" *)
    casez (\initial )
      /* src = "libresoc.v:62020.9-62020.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _11_ = MUL_dec31_MUL_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _11_ = 14'h0100;
        end
      default:
          _11_ = 14'h0000;
    endcase
  end
  always @* begin
      MUL_function_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:62033.5-62033.29" *)
    casez (\initial )
      /* src = "libresoc.v:62033.9-62033.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _13_ = MUL_dec31_MUL_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _13_ = 7'h32;
        end
      default:
          _13_ = 7'h00;
    endcase
  end
  always @* begin
      MUL_internal_op <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:62046.5-62046.29" *)
    casez (\initial )
      /* src = "libresoc.v:62046.9-62046.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _12_ = MUL_dec31_MUL_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _12_ = 4'h3;
        end
      default:
          _12_ = 4'h0;
    endcase
  end
  always @* begin
      MUL_in2_sel <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:62059.5-62059.29" *)
    casez (\initial )
      /* src = "libresoc.v:62059.9-62059.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _09_ = MUL_dec31_MUL_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _09_ = 3'h0;
        end
      default:
          _09_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:62072.5-62072.29" *)
    casez (\initial )
      /* src = "libresoc.v:62072.9-62072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _10_ = MUL_dec31_MUL_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _10_ = 3'h1;
        end
      default:
          _10_ = 3'h0;
    endcase
  end
  always @* begin
      MUL_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:62085.5-62085.29" *)
    casez (\initial )
      /* src = "libresoc.v:62085.9-62085.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = MUL_dec31_MUL_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _15_ = 2'h0;
        end
      default:
          _15_ = 2'h0;
    endcase
  end
  always @* begin
      MUL_rc_sel <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:62098.5-62098.29" *)
    casez (\initial )
      /* src = "libresoc.v:62098.9-62098.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _14_ = MUL_dec31_MUL_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_is_32b <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:62111.5-62111.29" *)
    casez (\initial )
      /* src = "libresoc.v:62111.9-62111.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = MUL_dec31_MUL_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _16_ = 1'h1;
        end
      default:
          _16_ = 1'h0;
    endcase
  end
  always @* begin
      MUL_sgn <= _07_;
  end
  assign \$1  = _17_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign MUL_SPR = opcode_in[20:11];
  assign MUL_MB = opcode_in[10:6];
  assign MUL_ME = opcode_in[5:1];
  assign MUL_SH = opcode_in[15:11];
  assign MUL_BC = opcode_in[10:6];
  assign MUL_TO = opcode_in[25:21];
  assign MUL_DS = opcode_in[15:2];
  assign MUL_D = opcode_in[15:0];
  assign MUL_BH = opcode_in[12:11];
  assign MUL_BI = opcode_in[20:16];
  assign MUL_BO = opcode_in[25:21];
  assign MUL_FXM = opcode_in[19:12];
  assign MUL_BT = opcode_in[25:21];
  assign MUL_BA = opcode_in[20:16];
  assign MUL_BB = opcode_in[15:11];
  assign MUL_CR = opcode_in[10:1];
  assign MUL_BF = opcode_in[25:23];
  assign MUL_BD = opcode_in[15:2];
  assign MUL_OE = opcode_in[10];
  assign MUL_Rc = opcode_in[0];
  assign MUL_AA = opcode_in[1];
  assign MUL_LK = opcode_in[0];
  assign MUL_LI = opcode_in[25:2];
  assign MUL_ME32 = opcode_in[5:1];
  assign MUL_MB32 = opcode_in[10:6];
  assign MUL_sh = { opcode_in[1], opcode_in[15:11] };
  assign MUL_SH32 = opcode_in[15:11];
  assign MUL_L = opcode_in[21];
  assign MUL_UI = opcode_in[15:0];
  assign MUL_SI = opcode_in[15:0];
  assign MUL_RB = opcode_in[15:11];
  assign MUL_RA = opcode_in[20:16];
  assign MUL_RT = opcode_in[25:21];
  assign MUL_RS = opcode_in[25:21];
  assign MUL_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign MUL_dec31_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:62463.1-64217.10" *)
module \dec$162 (bigendian, opcode_in, SHIFT_ROT_rc_sel, SHIFT_ROT_internal_op, SHIFT_ROT_SPR, SHIFT_ROT_function_unit, SHIFT_ROT_in2_sel, SHIFT_ROT_cr_out, SHIFT_ROT_cr_in, SHIFT_ROT_inv_a, SHIFT_ROT_cry_in, SHIFT_ROT_cry_out, SHIFT_ROT_is_32b, SHIFT_ROT_sgn, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_Rc, SHIFT_ROT_OE, SHIFT_ROT_BD, SHIFT_ROT_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:63792.3-63813.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:63814.3-63835.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:63858.3-63879.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:63660.3-63681.6" *)
  reg _03_;
  (* src = "libresoc.v:63726.3-63747.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:63770.3-63791.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:63748.3-63769.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:63638.3-63659.6" *)
  reg _07_;
  (* src = "libresoc.v:63682.3-63703.6" *)
  reg _08_;
  (* src = "libresoc.v:63836.3-63857.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:63704.3-63725.6" *)
  reg _10_;
  (* src = "libresoc.v:62464.7-62464.20" *)
  reg _11_;
  (* src = "libresoc.v:63792.3-63813.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:63814.3-63835.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:63858.3-63879.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:63660.3-63681.6" *)
  reg _15_;
  (* src = "libresoc.v:63726.3-63747.6" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:63770.3-63791.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:63748.3-63769.6" *)
  reg [6:0] _18_;
  (* src = "libresoc.v:63638.3-63659.6" *)
  reg _19_;
  (* src = "libresoc.v:63682.3-63703.6" *)
  reg _20_;
  (* src = "libresoc.v:63836.3-63857.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:63704.3-63725.6" *)
  reg _22_;
  (* src = "libresoc.v:63609.17-63609.211" *)
  wire [31:0] _23_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SHIFT_ROT_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] SHIFT_ROT_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] SHIFT_ROT_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] SHIFT_ROT_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] SHIFT_ROT_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] SHIFT_ROT_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] SHIFT_ROT_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] SHIFT_ROT_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SHIFT_ROT_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] SHIFT_ROT_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire SHIFT_ROT_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output SHIFT_ROT_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] SHIFT_ROT_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output SHIFT_ROT_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] SHIFT_ROT_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] SHIFT_ROT_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] SHIFT_ROT_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SHIFT_ROT_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] SHIFT_ROT_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_cr_in;
  reg [2:0] SHIFT_ROT_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] SHIFT_ROT_cr_out;
  reg [2:0] SHIFT_ROT_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_cry_in;
  reg [1:0] SHIFT_ROT_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_cry_out;
  reg SHIFT_ROT_cry_out;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SHIFT_ROT_dec30_opcode_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] SHIFT_ROT_dec31_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] SHIFT_ROT_function_unit;
  reg [13:0] SHIFT_ROT_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] SHIFT_ROT_in2_sel;
  reg [3:0] SHIFT_ROT_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] SHIFT_ROT_internal_op;
  reg [6:0] SHIFT_ROT_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_inv_a;
  reg SHIFT_ROT_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_is_32b;
  reg SHIFT_ROT_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] SHIFT_ROT_rc_sel;
  reg [1:0] SHIFT_ROT_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output SHIFT_ROT_sgn;
  reg SHIFT_ROT_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] SHIFT_ROT_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:62464.7-62464.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _23_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:63610.19-63623.4" *)
  SHIFT_ROT_dec30 SHIFT_ROT_dec30 (
    .SHIFT_ROT_dec30_cr_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in),
    .SHIFT_ROT_dec30_cr_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out),
    .SHIFT_ROT_dec30_cry_in(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in),
    .SHIFT_ROT_dec30_cry_out(SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out),
    .SHIFT_ROT_dec30_function_unit(SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit),
    .SHIFT_ROT_dec30_in2_sel(SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel),
    .SHIFT_ROT_dec30_internal_op(SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op),
    .SHIFT_ROT_dec30_inv_a(SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a),
    .SHIFT_ROT_dec30_is_32b(SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b),
    .SHIFT_ROT_dec30_rc_sel(SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel),
    .SHIFT_ROT_dec30_sgn(SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn),
    .opcode_in(SHIFT_ROT_dec30_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:63624.19-63637.4" *)
  SHIFT_ROT_dec31 SHIFT_ROT_dec31 (
    .SHIFT_ROT_dec31_cr_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in),
    .SHIFT_ROT_dec31_cr_out(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out),
    .SHIFT_ROT_dec31_cry_in(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in),
    .SHIFT_ROT_dec31_cry_out(SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out),
    .SHIFT_ROT_dec31_function_unit(SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit),
    .SHIFT_ROT_dec31_in2_sel(SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel),
    .SHIFT_ROT_dec31_internal_op(SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op),
    .SHIFT_ROT_dec31_inv_a(SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a),
    .SHIFT_ROT_dec31_is_32b(SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b),
    .SHIFT_ROT_dec31_rc_sel(SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel),
    .SHIFT_ROT_dec31_sgn(SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn),
    .opcode_in(SHIFT_ROT_dec31_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
      \initial  <= _11_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:63639.5-63639.29" *)
    casez (\initial )
      /* src = "libresoc.v:63639.9-63639.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _19_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _19_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _19_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_inv_a <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:63661.5-63661.29" *)
    casez (\initial )
      /* src = "libresoc.v:63661.9-63661.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _15_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _15_ = 1'h0;
        end
      default:
          _15_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_cry_out <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:63683.5-63683.29" *)
    casez (\initial )
      /* src = "libresoc.v:63683.9-63683.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _20_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _20_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _20_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _20_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _20_ = 1'h1;
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_is_32b <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:63705.5-63705.29" *)
    casez (\initial )
      /* src = "libresoc.v:63705.9-63705.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _22_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _22_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _22_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _22_ = 1'h0;
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:63727.5-63727.29" *)
    casez (\initial )
      /* src = "libresoc.v:63727.9-63727.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _16_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _16_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _16_ = 14'h0008;
        end
      default:
          _16_ = 14'h0000;
    endcase
  end
  always @* begin
      SHIFT_ROT_function_unit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:63749.5-63749.29" *)
    casez (\initial )
      /* src = "libresoc.v:63749.9-63749.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _18_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _18_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _18_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _18_ = 7'h38;
        end
      default:
          _18_ = 7'h00;
    endcase
  end
  always @* begin
      SHIFT_ROT_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:63771.5-63771.29" *)
    casez (\initial )
      /* src = "libresoc.v:63771.9-63771.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _17_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _17_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _17_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _17_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _17_ = 4'h1;
        end
      default:
          _17_ = 4'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:63793.5-63793.29" *)
    casez (\initial )
      /* src = "libresoc.v:63793.9-63793.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _12_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _12_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_cr_in <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:63815.5-63815.29" *)
    casez (\initial )
      /* src = "libresoc.v:63815.9-63815.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _13_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _13_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _13_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _13_ = 3'h1;
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_cr_out <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:63837.5-63837.29" *)
    casez (\initial )
      /* src = "libresoc.v:63837.9-63837.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _21_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _21_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _21_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _21_ = 2'h2;
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:63859.5-63859.29" *)
    casez (\initial )
      /* src = "libresoc.v:63859.9-63859.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _14_ = SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _14_ = SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _14_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _14_ = 2'h0;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT_cry_in <= _02_;
  end
  assign \$1  = _23_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign SHIFT_ROT_SPR = opcode_in[20:11];
  assign SHIFT_ROT_MB = opcode_in[10:6];
  assign SHIFT_ROT_ME = opcode_in[5:1];
  assign SHIFT_ROT_SH = opcode_in[15:11];
  assign SHIFT_ROT_BC = opcode_in[10:6];
  assign SHIFT_ROT_TO = opcode_in[25:21];
  assign SHIFT_ROT_DS = opcode_in[15:2];
  assign SHIFT_ROT_D = opcode_in[15:0];
  assign SHIFT_ROT_BH = opcode_in[12:11];
  assign SHIFT_ROT_BI = opcode_in[20:16];
  assign SHIFT_ROT_BO = opcode_in[25:21];
  assign SHIFT_ROT_FXM = opcode_in[19:12];
  assign SHIFT_ROT_BT = opcode_in[25:21];
  assign SHIFT_ROT_BA = opcode_in[20:16];
  assign SHIFT_ROT_BB = opcode_in[15:11];
  assign SHIFT_ROT_CR = opcode_in[10:1];
  assign SHIFT_ROT_BF = opcode_in[25:23];
  assign SHIFT_ROT_BD = opcode_in[15:2];
  assign SHIFT_ROT_OE = opcode_in[10];
  assign SHIFT_ROT_Rc = opcode_in[0];
  assign SHIFT_ROT_AA = opcode_in[1];
  assign SHIFT_ROT_LK = opcode_in[0];
  assign SHIFT_ROT_LI = opcode_in[25:2];
  assign SHIFT_ROT_ME32 = opcode_in[5:1];
  assign SHIFT_ROT_MB32 = opcode_in[10:6];
  assign SHIFT_ROT_sh = { opcode_in[1], opcode_in[15:11] };
  assign SHIFT_ROT_SH32 = opcode_in[15:11];
  assign SHIFT_ROT_L = opcode_in[21];
  assign SHIFT_ROT_UI = opcode_in[15:0];
  assign SHIFT_ROT_SI = opcode_in[15:0];
  assign SHIFT_ROT_RB = opcode_in[15:11];
  assign SHIFT_ROT_RA = opcode_in[20:16];
  assign SHIFT_ROT_RT = opcode_in[25:21];
  assign SHIFT_ROT_RS = opcode_in[25:21];
  assign SHIFT_ROT_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign SHIFT_ROT_dec31_opcode_in = opcode_in;
  assign SHIFT_ROT_dec30_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:64221.1-66730.10" *)
module \dec$166 (bigendian, opcode_in, LDST_rc_sel, LDST_internal_op, LDST_SPR, LDST_function_unit, LDST_in1_sel, LDST_in2_sel, LDST_cr_out, LDST_ldst_len, LDST_is_32b, LDST_sgn, LDST_br, LDST_sgn_ext, LDST_upd, LDST_RA, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_Rc, LDST_OE, LDST_BD, LDST_DS, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:65812.3-65869.6" *)
  reg _00_;
  (* src = "libresoc.v:66276.3-66333.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:66334.3-66391.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:66044.3-66101.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:66160.3-66217.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:66218.3-66275.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:66102.3-66159.6" *)
  reg [6:0] _06_;
  (* src = "libresoc.v:65928.3-65985.6" *)
  reg _07_;
  (* src = "libresoc.v:65638.3-65695.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:65754.3-65811.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:65986.3-66043.6" *)
  reg _10_;
  (* src = "libresoc.v:65870.3-65927.6" *)
  reg _11_;
  (* src = "libresoc.v:65696.3-65753.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:64222.7-64222.20" *)
  reg _13_;
  (* src = "libresoc.v:65812.3-65869.6" *)
  reg _14_;
  (* src = "libresoc.v:66276.3-66333.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:66334.3-66391.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:66044.3-66101.6" *)
  reg [13:0] _17_;
  (* src = "libresoc.v:66160.3-66217.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:66218.3-66275.6" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:66102.3-66159.6" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:65928.3-65985.6" *)
  reg _21_;
  (* src = "libresoc.v:65638.3-65695.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:65754.3-65811.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:65986.3-66043.6" *)
  reg _24_;
  (* src = "libresoc.v:65870.3-65927.6" *)
  reg _25_;
  (* src = "libresoc.v:65696.3-65753.6" *)
  reg [1:0] _26_;
  (* src = "libresoc.v:65589.17-65589.211" *)
  wire [31:0] _27_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LDST_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] LDST_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] LDST_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] LDST_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] LDST_CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] LDST_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [13:0] LDST_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] LDST_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LDST_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [23:0] LDST_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire LDST_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output LDST_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] LDST_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] LDST_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output LDST_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] LDST_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] LDST_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] LDST_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] LDST_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [15:0] LDST_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_br;
  reg LDST_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] LDST_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_cr_out;
  reg [2:0] LDST_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_LDST_dec31_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_LDST_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_LDST_dec31_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec31_LDST_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec31_LDST_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_LDST_dec31_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec31_LDST_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_LDST_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec31_LDST_dec31_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_LDST_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_LDST_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec31_LDST_dec31_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec31_LDST_dec31_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec31_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec58_LDST_dec58_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec58_LDST_dec58_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec58_LDST_dec58_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec58_LDST_dec58_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec58_LDST_dec58_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec58_LDST_dec58_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec58_LDST_dec58_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec58_LDST_dec58_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec58_LDST_dec58_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec58_LDST_dec58_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec58_LDST_dec58_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec58_LDST_dec58_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec58_LDST_dec58_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec58_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec62_LDST_dec62_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec62_LDST_dec62_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec62_LDST_dec62_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] LDST_dec62_LDST_dec62_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] LDST_dec62_LDST_dec62_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec62_LDST_dec62_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] LDST_dec62_LDST_dec62_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec62_LDST_dec62_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] LDST_dec62_LDST_dec62_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec62_LDST_dec62_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec62_LDST_dec62_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire LDST_dec62_LDST_dec62_sgn_ext;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] LDST_dec62_LDST_dec62_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] LDST_dec62_opcode_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] LDST_function_unit;
  reg [13:0] LDST_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] LDST_in1_sel;
  reg [2:0] LDST_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_in2_sel;
  reg [3:0] LDST_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] LDST_internal_op;
  reg [6:0] LDST_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_is_32b;
  reg LDST_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] LDST_ldst_len;
  reg [3:0] LDST_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_rc_sel;
  reg [1:0] LDST_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_sgn;
  reg LDST_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output LDST_sgn_ext;
  reg LDST_sgn_ext;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [5:0] LDST_sh;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] LDST_upd;
  reg [1:0] LDST_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "libresoc.v:64222.7-64222.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  assign _27_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:65590.14-65605.4" *)
  LDST_dec31 LDST_dec31 (
    .LDST_dec31_br(LDST_dec31_LDST_dec31_br),
    .LDST_dec31_cr_in(LDST_dec31_LDST_dec31_cr_in),
    .LDST_dec31_cr_out(LDST_dec31_LDST_dec31_cr_out),
    .LDST_dec31_function_unit(LDST_dec31_LDST_dec31_function_unit),
    .LDST_dec31_in1_sel(LDST_dec31_LDST_dec31_in1_sel),
    .LDST_dec31_in2_sel(LDST_dec31_LDST_dec31_in2_sel),
    .LDST_dec31_internal_op(LDST_dec31_LDST_dec31_internal_op),
    .LDST_dec31_is_32b(LDST_dec31_LDST_dec31_is_32b),
    .LDST_dec31_ldst_len(LDST_dec31_LDST_dec31_ldst_len),
    .LDST_dec31_rc_sel(LDST_dec31_LDST_dec31_rc_sel),
    .LDST_dec31_sgn(LDST_dec31_LDST_dec31_sgn),
    .LDST_dec31_sgn_ext(LDST_dec31_LDST_dec31_sgn_ext),
    .LDST_dec31_upd(LDST_dec31_LDST_dec31_upd),
    .opcode_in(LDST_dec31_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:65606.14-65621.4" *)
  LDST_dec58 LDST_dec58 (
    .LDST_dec58_br(LDST_dec58_LDST_dec58_br),
    .LDST_dec58_cr_in(LDST_dec58_LDST_dec58_cr_in),
    .LDST_dec58_cr_out(LDST_dec58_LDST_dec58_cr_out),
    .LDST_dec58_function_unit(LDST_dec58_LDST_dec58_function_unit),
    .LDST_dec58_in1_sel(LDST_dec58_LDST_dec58_in1_sel),
    .LDST_dec58_in2_sel(LDST_dec58_LDST_dec58_in2_sel),
    .LDST_dec58_internal_op(LDST_dec58_LDST_dec58_internal_op),
    .LDST_dec58_is_32b(LDST_dec58_LDST_dec58_is_32b),
    .LDST_dec58_ldst_len(LDST_dec58_LDST_dec58_ldst_len),
    .LDST_dec58_rc_sel(LDST_dec58_LDST_dec58_rc_sel),
    .LDST_dec58_sgn(LDST_dec58_LDST_dec58_sgn),
    .LDST_dec58_sgn_ext(LDST_dec58_LDST_dec58_sgn_ext),
    .LDST_dec58_upd(LDST_dec58_LDST_dec58_upd),
    .opcode_in(LDST_dec58_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:65622.14-65637.4" *)
  LDST_dec62 LDST_dec62 (
    .LDST_dec62_br(LDST_dec62_LDST_dec62_br),
    .LDST_dec62_cr_in(LDST_dec62_LDST_dec62_cr_in),
    .LDST_dec62_cr_out(LDST_dec62_LDST_dec62_cr_out),
    .LDST_dec62_function_unit(LDST_dec62_LDST_dec62_function_unit),
    .LDST_dec62_in1_sel(LDST_dec62_LDST_dec62_in1_sel),
    .LDST_dec62_in2_sel(LDST_dec62_LDST_dec62_in2_sel),
    .LDST_dec62_internal_op(LDST_dec62_LDST_dec62_internal_op),
    .LDST_dec62_is_32b(LDST_dec62_LDST_dec62_is_32b),
    .LDST_dec62_ldst_len(LDST_dec62_LDST_dec62_ldst_len),
    .LDST_dec62_rc_sel(LDST_dec62_LDST_dec62_rc_sel),
    .LDST_dec62_sgn(LDST_dec62_LDST_dec62_sgn),
    .LDST_dec62_sgn_ext(LDST_dec62_LDST_dec62_sgn_ext),
    .LDST_dec62_upd(LDST_dec62_LDST_dec62_upd),
    .opcode_in(LDST_dec62_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:65639.5-65639.29" *)
    casez (\initial )
      /* src = "libresoc.v:65639.9-65639.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _22_ = LDST_dec31_LDST_dec31_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _22_ = LDST_dec58_LDST_dec58_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _22_ = LDST_dec62_LDST_dec62_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _22_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _22_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _22_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _22_ = 4'h4;
        end
      default:
          _22_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_ldst_len <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:65697.5-65697.29" *)
    casez (\initial )
      /* src = "libresoc.v:65697.9-65697.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _26_ = LDST_dec31_LDST_dec31_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _26_ = LDST_dec58_LDST_dec58_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _26_ = LDST_dec62_LDST_dec62_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _26_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _26_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _26_ = 2'h1;
        end
      default:
          _26_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_upd <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:65755.5-65755.29" *)
    casez (\initial )
      /* src = "libresoc.v:65755.9-65755.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _23_ = LDST_dec31_LDST_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _23_ = LDST_dec58_LDST_dec58_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _23_ = LDST_dec62_LDST_dec62_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _23_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _23_ = 2'h0;
        end
      default:
          _23_ = 2'h0;
    endcase
  end
  always @* begin
      LDST_rc_sel <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:65813.5-65813.29" *)
    casez (\initial )
      /* src = "libresoc.v:65813.9-65813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _14_ = LDST_dec31_LDST_dec31_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _14_ = LDST_dec58_LDST_dec58_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _14_ = LDST_dec62_LDST_dec62_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _14_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _14_ = 1'h0;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_br <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:65871.5-65871.29" *)
    casez (\initial )
      /* src = "libresoc.v:65871.9-65871.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _25_ = LDST_dec31_LDST_dec31_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _25_ = LDST_dec58_LDST_dec58_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _25_ = LDST_dec62_LDST_dec62_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _25_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _25_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_sgn_ext <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:65929.5-65929.29" *)
    casez (\initial )
      /* src = "libresoc.v:65929.9-65929.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _21_ = LDST_dec31_LDST_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _21_ = LDST_dec58_LDST_dec58_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _21_ = LDST_dec62_LDST_dec62_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _21_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _21_ = 1'h0;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_is_32b <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:65987.5-65987.29" *)
    casez (\initial )
      /* src = "libresoc.v:65987.9-65987.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _24_ = LDST_dec31_LDST_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _24_ = LDST_dec58_LDST_dec58_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _24_ = LDST_dec62_LDST_dec62_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _24_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _24_ = 1'h0;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      LDST_sgn <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:66045.5-66045.29" *)
    casez (\initial )
      /* src = "libresoc.v:66045.9-66045.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _17_ = LDST_dec31_LDST_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _17_ = LDST_dec58_LDST_dec58_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _17_ = LDST_dec62_LDST_dec62_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _17_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _17_ = 14'h0004;
        end
      default:
          _17_ = 14'h0000;
    endcase
  end
  always @* begin
      LDST_function_unit <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:66103.5-66103.29" *)
    casez (\initial )
      /* src = "libresoc.v:66103.9-66103.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _20_ = LDST_dec31_LDST_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _20_ = LDST_dec58_LDST_dec58_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _20_ = LDST_dec62_LDST_dec62_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _20_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _20_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _20_ = 7'h26;
        end
      default:
          _20_ = 7'h00;
    endcase
  end
  always @* begin
      LDST_internal_op <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:66161.5-66161.29" *)
    casez (\initial )
      /* src = "libresoc.v:66161.9-66161.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _18_ = LDST_dec31_LDST_dec31_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _18_ = LDST_dec58_LDST_dec58_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _18_ = LDST_dec62_LDST_dec62_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _18_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _18_ = 3'h2;
        end
      default:
          _18_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_in1_sel <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:66219.5-66219.29" *)
    casez (\initial )
      /* src = "libresoc.v:66219.9-66219.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _19_ = LDST_dec31_LDST_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _19_ = LDST_dec58_LDST_dec58_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _19_ = LDST_dec62_LDST_dec62_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _19_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _19_ = 4'h3;
        end
      default:
          _19_ = 4'h0;
    endcase
  end
  always @* begin
      LDST_in2_sel <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:66277.5-66277.29" *)
    casez (\initial )
      /* src = "libresoc.v:66277.9-66277.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _15_ = LDST_dec31_LDST_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _15_ = LDST_dec58_LDST_dec58_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _15_ = LDST_dec62_LDST_dec62_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _15_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_cr_in <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:66335.5-66335.29" *)
    casez (\initial )
      /* src = "libresoc.v:66335.9-66335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _16_ = LDST_dec31_LDST_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _16_ = LDST_dec58_LDST_dec58_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _16_ = LDST_dec62_LDST_dec62_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _16_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = 3'h0;
    endcase
  end
  always @* begin
      LDST_cr_out <= _02_;
  end
  assign \$1  = _27_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign LDST_SPR = opcode_in[20:11];
  assign LDST_MB = opcode_in[10:6];
  assign LDST_ME = opcode_in[5:1];
  assign LDST_SH = opcode_in[15:11];
  assign LDST_BC = opcode_in[10:6];
  assign LDST_TO = opcode_in[25:21];
  assign LDST_DS = opcode_in[15:2];
  assign LDST_D = opcode_in[15:0];
  assign LDST_BH = opcode_in[12:11];
  assign LDST_BI = opcode_in[20:16];
  assign LDST_BO = opcode_in[25:21];
  assign LDST_FXM = opcode_in[19:12];
  assign LDST_BT = opcode_in[25:21];
  assign LDST_BA = opcode_in[20:16];
  assign LDST_BB = opcode_in[15:11];
  assign LDST_CR = opcode_in[10:1];
  assign LDST_BF = opcode_in[25:23];
  assign LDST_BD = opcode_in[15:2];
  assign LDST_OE = opcode_in[10];
  assign LDST_Rc = opcode_in[0];
  assign LDST_AA = opcode_in[1];
  assign LDST_LK = opcode_in[0];
  assign LDST_LI = opcode_in[25:2];
  assign LDST_ME32 = opcode_in[5:1];
  assign LDST_MB32 = opcode_in[10:6];
  assign LDST_sh = { opcode_in[1], opcode_in[15:11] };
  assign LDST_SH32 = opcode_in[15:11];
  assign LDST_L = opcode_in[21];
  assign LDST_UI = opcode_in[15:0];
  assign LDST_SI = opcode_in[15:0];
  assign LDST_RB = opcode_in[15:11];
  assign LDST_RA = opcode_in[20:16];
  assign LDST_RT = opcode_in[25:21];
  assign LDST_RS = opcode_in[25:21];
  assign LDST_PO = opcode_in[31:26];
  assign opcode_in = \$1 ;
  assign LDST_dec62_opcode_in = opcode_in;
  assign LDST_dec58_opcode_in = opcode_in;
  assign LDST_dec31_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:66734.1-74954.10" *)
module \dec$171 (raw_opcode_in, opcode_in, rc_sel, internal_op, SPR, function_unit, cr_out, cry_in, is_32b, lk, LK, cr_in, in1_sel, in2_sel, in3_sel, out_sel, asmcode, upd, RS, RT, RA, RB, Rc, OE, BB, BA, BT, FXM, BO, BI, BC, X_BF, X_BFA, XL_BT, XL_XO, bigendian);
  reg \initial  = 0;
  (* src = "libresoc.v:70117.3-70261.6" *)
  reg [1:0] _000_;
  (* src = "libresoc.v:70262.3-70406.6" *)
  reg [1:0] _001_;
  (* src = "libresoc.v:69972.3-70116.6" *)
  reg [7:0] _002_;
  (* src = "libresoc.v:73307.3-73451.6" *)
  reg _003_;
  (* src = "libresoc.v:70987.3-71131.6" *)
  reg [2:0] _004_;
  (* src = "libresoc.v:71132.3-71276.6" *)
  reg [2:0] _005_;
  (* src = "libresoc.v:72727.3-72871.6" *)
  reg [1:0] _006_;
  (* src = "libresoc.v:73162.3-73306.6" *)
  reg _007_;
  (* src = "libresoc.v:69827.3-69971.6" *)
  reg [4:0] _008_;
  (* src = "libresoc.v:74322.3-74466.6" *)
  reg [13:0] _009_;
  (* src = "libresoc.v:70407.3-70551.6" *)
  reg [2:0] _010_;
  (* src = "libresoc.v:70552.3-70696.6" *)
  reg [3:0] _011_;
  (* src = "libresoc.v:70697.3-70841.6" *)
  reg [1:0] _012_;
  (* src = "libresoc.v:66735.7-66735.20" *)
  reg _013_;
  (* src = "libresoc.v:74467.3-74611.6" *)
  reg [6:0] _014_;
  (* src = "libresoc.v:72872.3-73016.6" *)
  reg _015_;
  (* src = "libresoc.v:73017.3-73161.6" *)
  reg _016_;
  (* src = "libresoc.v:73742.3-73886.6" *)
  reg _017_;
  (* src = "libresoc.v:72292.3-72436.6" *)
  reg [3:0] _018_;
  (* src = "libresoc.v:74032.3-74176.6" *)
  reg _019_;
  (* src = "libresoc.v:70842.3-70986.6" *)
  reg [2:0] _020_;
  (* src = "libresoc.v:72582.3-72726.6" *)
  reg [1:0] _021_;
  (* src = "libresoc.v:73597.3-73741.6" *)
  reg _022_;
  (* src = "libresoc.v:74177.3-74321.6" *)
  reg _023_;
  (* src = "libresoc.v:73887.3-74031.6" *)
  reg _024_;
  (* src = "libresoc.v:73452.3-73596.6" *)
  reg _025_;
  (* src = "libresoc.v:72002.3-72146.6" *)
  reg [2:0] _026_;
  (* src = "libresoc.v:72147.3-72291.6" *)
  reg [2:0] _027_;
  (* src = "libresoc.v:71277.3-71421.6" *)
  reg [2:0] _028_;
  (* src = "libresoc.v:71422.3-71566.6" *)
  reg [2:0] _029_;
  (* src = "libresoc.v:71567.3-71711.6" *)
  reg [2:0] _030_;
  (* src = "libresoc.v:71857.3-72001.6" *)
  reg [2:0] _031_;
  (* src = "libresoc.v:71712.3-71856.6" *)
  reg [2:0] _032_;
  (* src = "libresoc.v:72437.3-72581.6" *)
  reg [1:0] _033_;
  (* src = "libresoc.v:70117.3-70261.6" *)
  reg [1:0] _034_;
  (* src = "libresoc.v:70262.3-70406.6" *)
  reg [1:0] _035_;
  (* src = "libresoc.v:69972.3-70116.6" *)
  reg [7:0] _036_;
  (* src = "libresoc.v:73307.3-73451.6" *)
  reg _037_;
  (* src = "libresoc.v:70987.3-71131.6" *)
  reg [2:0] _038_;
  (* src = "libresoc.v:71132.3-71276.6" *)
  reg [2:0] _039_;
  (* src = "libresoc.v:72727.3-72871.6" *)
  reg [1:0] _040_;
  (* src = "libresoc.v:73162.3-73306.6" *)
  reg _041_;
  (* src = "libresoc.v:69827.3-69971.6" *)
  reg [4:0] _042_;
  (* src = "libresoc.v:74322.3-74466.6" *)
  reg [13:0] _043_;
  (* src = "libresoc.v:70407.3-70551.6" *)
  reg [2:0] _044_;
  (* src = "libresoc.v:70552.3-70696.6" *)
  reg [3:0] _045_;
  (* src = "libresoc.v:70697.3-70841.6" *)
  reg [1:0] _046_;
  (* src = "libresoc.v:74467.3-74611.6" *)
  reg [6:0] _047_;
  (* src = "libresoc.v:72872.3-73016.6" *)
  reg _048_;
  (* src = "libresoc.v:73017.3-73161.6" *)
  reg _049_;
  (* src = "libresoc.v:73742.3-73886.6" *)
  reg _050_;
  (* src = "libresoc.v:72292.3-72436.6" *)
  reg [3:0] _051_;
  (* src = "libresoc.v:74032.3-74176.6" *)
  reg _052_;
  (* src = "libresoc.v:70842.3-70986.6" *)
  reg [2:0] _053_;
  (* src = "libresoc.v:72582.3-72726.6" *)
  reg [1:0] _054_;
  (* src = "libresoc.v:73597.3-73741.6" *)
  reg _055_;
  (* src = "libresoc.v:74177.3-74321.6" *)
  reg _056_;
  (* src = "libresoc.v:73887.3-74031.6" *)
  reg _057_;
  (* src = "libresoc.v:73452.3-73596.6" *)
  reg _058_;
  (* src = "libresoc.v:72002.3-72146.6" *)
  reg [2:0] _059_;
  (* src = "libresoc.v:72147.3-72291.6" *)
  reg [2:0] _060_;
  (* src = "libresoc.v:71277.3-71421.6" *)
  reg [2:0] _061_;
  (* src = "libresoc.v:71422.3-71566.6" *)
  reg [2:0] _062_;
  (* src = "libresoc.v:71567.3-71711.6" *)
  reg [2:0] _063_;
  (* src = "libresoc.v:71857.3-72001.6" *)
  reg [2:0] _064_;
  (* src = "libresoc.v:71712.3-71856.6" *)
  reg [2:0] _065_;
  (* src = "libresoc.v:72437.3-72581.6" *)
  reg [1:0] _066_;
  (* src = "libresoc.v:70117.3-70261.6" *)
  reg [1:0] _067_;
  (* src = "libresoc.v:70262.3-70406.6" *)
  reg [1:0] _068_;
  (* src = "libresoc.v:69972.3-70116.6" *)
  reg [7:0] _069_;
  (* src = "libresoc.v:73307.3-73451.6" *)
  reg _070_;
  (* src = "libresoc.v:70987.3-71131.6" *)
  reg [2:0] _071_;
  (* src = "libresoc.v:71132.3-71276.6" *)
  reg [2:0] _072_;
  (* src = "libresoc.v:72727.3-72871.6" *)
  reg [1:0] _073_;
  (* src = "libresoc.v:73162.3-73306.6" *)
  reg _074_;
  (* src = "libresoc.v:69827.3-69971.6" *)
  reg [4:0] _075_;
  (* src = "libresoc.v:74322.3-74466.6" *)
  reg [13:0] _076_;
  (* src = "libresoc.v:70407.3-70551.6" *)
  reg [2:0] _077_;
  (* src = "libresoc.v:70552.3-70696.6" *)
  reg [3:0] _078_;
  (* src = "libresoc.v:70697.3-70841.6" *)
  reg [1:0] _079_;
  (* src = "libresoc.v:74467.3-74611.6" *)
  reg [6:0] _080_;
  (* src = "libresoc.v:72872.3-73016.6" *)
  reg _081_;
  (* src = "libresoc.v:73017.3-73161.6" *)
  reg _082_;
  (* src = "libresoc.v:73742.3-73886.6" *)
  reg _083_;
  (* src = "libresoc.v:72292.3-72436.6" *)
  reg [3:0] _084_;
  (* src = "libresoc.v:74032.3-74176.6" *)
  reg _085_;
  (* src = "libresoc.v:70842.3-70986.6" *)
  reg [2:0] _086_;
  (* src = "libresoc.v:72582.3-72726.6" *)
  reg [1:0] _087_;
  (* src = "libresoc.v:73597.3-73741.6" *)
  reg _088_;
  (* src = "libresoc.v:74177.3-74321.6" *)
  reg _089_;
  (* src = "libresoc.v:73887.3-74031.6" *)
  reg _090_;
  (* src = "libresoc.v:73452.3-73596.6" *)
  reg _091_;
  (* src = "libresoc.v:72002.3-72146.6" *)
  reg [2:0] _092_;
  (* src = "libresoc.v:72147.3-72291.6" *)
  reg [2:0] _093_;
  (* src = "libresoc.v:71277.3-71421.6" *)
  reg [2:0] _094_;
  (* src = "libresoc.v:71422.3-71566.6" *)
  reg [2:0] _095_;
  (* src = "libresoc.v:71567.3-71711.6" *)
  reg [2:0] _096_;
  (* src = "libresoc.v:71857.3-72001.6" *)
  reg [2:0] _097_;
  (* src = "libresoc.v:71712.3-71856.6" *)
  reg [2:0] _098_;
  (* src = "libresoc.v:72437.3-72581.6" *)
  reg [1:0] _099_;
  (* src = "libresoc.v:69610.17-69610.211" *)
  wire [31:0] _100_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *)
  wire [31:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire A_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] A_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [2:0] BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [1:0] BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] B_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] B_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire B_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] CR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQE_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DQE_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [11:0] DQ_DQ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] DQ_PT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DQ_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DQ_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] DQ_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] DQ_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [13:0] DS_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DS_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] DS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] DX_d0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] DX_d0_d1_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] DX_d1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire DX_d2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] D_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_D;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire D_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] D_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [15:0] D_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] EVS_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [7:0] FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_AA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [23:0] I_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire I_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] MB32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_IS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MDS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MDS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XBI_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] MDS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MDS_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] MD_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire MD_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] MD_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] MD_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] ME32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_MB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_ME;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire M_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] M_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [4:0] RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] SC_LEV;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] SC_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  output [9:0] SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] SVL_SVi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] SVL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_ms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire SVL_vs;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [1:0] SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [1:0] SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] TX_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] TX_XBI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] TX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VA_SHB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VA_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] VA_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VC_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VC_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VC_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire VX_PS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_SIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] VX_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] VX_UIM_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] VX_UIM_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] VX_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] VX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [10:0] VX_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFL_FLM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFL_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XFL_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_BHRBE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_DUI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_DUIS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XFX_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XFX_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] XFX_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XL_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XL_BH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XL_BO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  output [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [14:0] XL_OC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XL_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  output [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XO_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XO_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XO_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XS_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XS_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XS_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XS_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX2_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX2_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX2_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX2_UIM_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX2_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] XX2_dc_dm_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX2_dm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX2_dx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] XX3_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_DM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX3_SHW;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX3_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX3_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX3_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] XX3_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] XX3_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] XX3_XO_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_AX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_AX_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_BX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_BX_B;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_CX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_CX_C;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] XX4_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire XX4_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] XX4_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] XX4_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_A;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  output [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  output [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_CT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [6:0] X_DCMX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_DRM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_E;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_EO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_EO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_EX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_E_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] X_IH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_IMM8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_L1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_L3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_MO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_NB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_PRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RIC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_RM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_RO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RSp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_RTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_R_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_SP;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_SR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_SX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_SX_S;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_TBR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_TO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_TX;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] X_TX_T;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [3:0] X_U;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_UIM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] X_VRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire X_W;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] X_WC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] X_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] X_XO_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] Z22_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DCM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_DGM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z22_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z22_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] Z22_SH;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [8:0] Z22_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRAp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRBp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_FRTp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_R;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [1:0] Z23_RMC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire Z23_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] Z23_TE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [7:0] Z23_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [5:0] all_PO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] asmcode;
  reg [7:0] asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] cr_in;
  reg [2:0] cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] cr_out;
  reg [2:0] cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] cry_in;
  reg [1:0] cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg cry_out;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec19_dec19_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec19_dec19_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec19_dec19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec19_dec19_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec19_dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec19_dec19_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec19_dec19_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec19_dec19_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec19_dec19_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec19_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec22_dec22_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec22_dec22_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec22_dec22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec22_dec22_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec22_dec22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec22_dec22_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec22_dec22_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec22_dec22_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec22_dec22_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec22_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec30_dec30_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec30_dec30_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec30_dec30_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec30_dec30_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec30_dec30_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec30_dec30_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec30_dec30_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec30_dec30_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec30_dec30_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec30_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec31_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec31_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec31_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec31_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec31_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec31_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec31_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec58_dec58_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec58_dec58_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec58_dec58_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec58_dec58_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec58_dec58_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec58_dec58_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec58_dec58_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec58_dec58_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec58_dec58_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec58_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec62_dec62_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec62_dec62_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec62_dec62_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec62_dec62_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec62_dec62_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec62_dec62_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec62_dec62_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec62_dec62_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec62_dec62_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec62_opcode_in;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [4:0] form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] function_unit;
  reg [13:0] function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] in1_sel;
  reg [2:0] in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] in2_sel;
  reg [3:0] in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] in3_sel;
  reg [1:0] in3_sel;
  (* src = "libresoc.v:66735.7-66735.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] internal_op;
  reg [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output is_32b;
  reg is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [3:0] ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output lk;
  reg lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  output [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [5:0] opcode_switch;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [31:0] \opcode_switch$1 ;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] out_sel;
  reg [2:0] out_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] rc_sel;
  reg [1:0] rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  reg sgn_ext;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] sh;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  reg [2:0] sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] upd;
  reg [1:0] upd;
  assign _100_ = bigendian ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" *) { raw_opcode_in[7:0], raw_opcode_in[15:8], raw_opcode_in[23:16], raw_opcode_in[31:24] } : raw_opcode_in;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69611.9-69646.4" *)
  dec19 dec19 (
    .dec19_SV_Etype(dec19_dec19_SV_Etype),
    .dec19_SV_Ptype(dec19_dec19_SV_Ptype),
    .dec19_asmcode(dec19_dec19_asmcode),
    .dec19_br(dec19_dec19_br),
    .dec19_cr_in(dec19_dec19_cr_in),
    .dec19_cr_out(dec19_dec19_cr_out),
    .dec19_cry_in(dec19_dec19_cry_in),
    .dec19_cry_out(dec19_dec19_cry_out),
    .dec19_form(dec19_dec19_form),
    .dec19_function_unit(dec19_dec19_function_unit),
    .dec19_in1_sel(dec19_dec19_in1_sel),
    .dec19_in2_sel(dec19_dec19_in2_sel),
    .dec19_in3_sel(dec19_dec19_in3_sel),
    .dec19_internal_op(dec19_dec19_internal_op),
    .dec19_inv_a(dec19_dec19_inv_a),
    .dec19_inv_out(dec19_dec19_inv_out),
    .dec19_is_32b(dec19_dec19_is_32b),
    .dec19_ldst_len(dec19_dec19_ldst_len),
    .dec19_lk(dec19_dec19_lk),
    .dec19_out_sel(dec19_dec19_out_sel),
    .dec19_rc_sel(dec19_dec19_rc_sel),
    .dec19_rsrv(dec19_dec19_rsrv),
    .dec19_sgl_pipe(dec19_dec19_sgl_pipe),
    .dec19_sgn(dec19_dec19_sgn),
    .dec19_sgn_ext(dec19_dec19_sgn_ext),
    .dec19_sv_cr_in(dec19_dec19_sv_cr_in),
    .dec19_sv_cr_out(dec19_dec19_sv_cr_out),
    .dec19_sv_in1(dec19_dec19_sv_in1),
    .dec19_sv_in2(dec19_dec19_sv_in2),
    .dec19_sv_in3(dec19_dec19_sv_in3),
    .dec19_sv_out(dec19_dec19_sv_out),
    .dec19_sv_out2(dec19_dec19_sv_out2),
    .dec19_upd(dec19_dec19_upd),
    .opcode_in(dec19_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69647.9-69682.4" *)
  dec22 dec22 (
    .dec22_SV_Etype(dec22_dec22_SV_Etype),
    .dec22_SV_Ptype(dec22_dec22_SV_Ptype),
    .dec22_asmcode(dec22_dec22_asmcode),
    .dec22_br(dec22_dec22_br),
    .dec22_cr_in(dec22_dec22_cr_in),
    .dec22_cr_out(dec22_dec22_cr_out),
    .dec22_cry_in(dec22_dec22_cry_in),
    .dec22_cry_out(dec22_dec22_cry_out),
    .dec22_form(dec22_dec22_form),
    .dec22_function_unit(dec22_dec22_function_unit),
    .dec22_in1_sel(dec22_dec22_in1_sel),
    .dec22_in2_sel(dec22_dec22_in2_sel),
    .dec22_in3_sel(dec22_dec22_in3_sel),
    .dec22_internal_op(dec22_dec22_internal_op),
    .dec22_inv_a(dec22_dec22_inv_a),
    .dec22_inv_out(dec22_dec22_inv_out),
    .dec22_is_32b(dec22_dec22_is_32b),
    .dec22_ldst_len(dec22_dec22_ldst_len),
    .dec22_lk(dec22_dec22_lk),
    .dec22_out_sel(dec22_dec22_out_sel),
    .dec22_rc_sel(dec22_dec22_rc_sel),
    .dec22_rsrv(dec22_dec22_rsrv),
    .dec22_sgl_pipe(dec22_dec22_sgl_pipe),
    .dec22_sgn(dec22_dec22_sgn),
    .dec22_sgn_ext(dec22_dec22_sgn_ext),
    .dec22_sv_cr_in(dec22_dec22_sv_cr_in),
    .dec22_sv_cr_out(dec22_dec22_sv_cr_out),
    .dec22_sv_in1(dec22_dec22_sv_in1),
    .dec22_sv_in2(dec22_dec22_sv_in2),
    .dec22_sv_in3(dec22_dec22_sv_in3),
    .dec22_sv_out(dec22_dec22_sv_out),
    .dec22_sv_out2(dec22_dec22_sv_out2),
    .dec22_upd(dec22_dec22_upd),
    .opcode_in(dec22_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69683.9-69718.4" *)
  dec30 dec30 (
    .dec30_SV_Etype(dec30_dec30_SV_Etype),
    .dec30_SV_Ptype(dec30_dec30_SV_Ptype),
    .dec30_asmcode(dec30_dec30_asmcode),
    .dec30_br(dec30_dec30_br),
    .dec30_cr_in(dec30_dec30_cr_in),
    .dec30_cr_out(dec30_dec30_cr_out),
    .dec30_cry_in(dec30_dec30_cry_in),
    .dec30_cry_out(dec30_dec30_cry_out),
    .dec30_form(dec30_dec30_form),
    .dec30_function_unit(dec30_dec30_function_unit),
    .dec30_in1_sel(dec30_dec30_in1_sel),
    .dec30_in2_sel(dec30_dec30_in2_sel),
    .dec30_in3_sel(dec30_dec30_in3_sel),
    .dec30_internal_op(dec30_dec30_internal_op),
    .dec30_inv_a(dec30_dec30_inv_a),
    .dec30_inv_out(dec30_dec30_inv_out),
    .dec30_is_32b(dec30_dec30_is_32b),
    .dec30_ldst_len(dec30_dec30_ldst_len),
    .dec30_lk(dec30_dec30_lk),
    .dec30_out_sel(dec30_dec30_out_sel),
    .dec30_rc_sel(dec30_dec30_rc_sel),
    .dec30_rsrv(dec30_dec30_rsrv),
    .dec30_sgl_pipe(dec30_dec30_sgl_pipe),
    .dec30_sgn(dec30_dec30_sgn),
    .dec30_sgn_ext(dec30_dec30_sgn_ext),
    .dec30_sv_cr_in(dec30_dec30_sv_cr_in),
    .dec30_sv_cr_out(dec30_dec30_sv_cr_out),
    .dec30_sv_in1(dec30_dec30_sv_in1),
    .dec30_sv_in2(dec30_dec30_sv_in2),
    .dec30_sv_in3(dec30_dec30_sv_in3),
    .dec30_sv_out(dec30_dec30_sv_out),
    .dec30_sv_out2(dec30_dec30_sv_out2),
    .dec30_upd(dec30_dec30_upd),
    .opcode_in(dec30_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69719.9-69754.4" *)
  dec31 dec31 (
    .dec31_SV_Etype(dec31_dec31_SV_Etype),
    .dec31_SV_Ptype(dec31_dec31_SV_Ptype),
    .dec31_asmcode(dec31_dec31_asmcode),
    .dec31_br(dec31_dec31_br),
    .dec31_cr_in(dec31_dec31_cr_in),
    .dec31_cr_out(dec31_dec31_cr_out),
    .dec31_cry_in(dec31_dec31_cry_in),
    .dec31_cry_out(dec31_dec31_cry_out),
    .dec31_form(dec31_dec31_form),
    .dec31_function_unit(dec31_dec31_function_unit),
    .dec31_in1_sel(dec31_dec31_in1_sel),
    .dec31_in2_sel(dec31_dec31_in2_sel),
    .dec31_in3_sel(dec31_dec31_in3_sel),
    .dec31_internal_op(dec31_dec31_internal_op),
    .dec31_inv_a(dec31_dec31_inv_a),
    .dec31_inv_out(dec31_dec31_inv_out),
    .dec31_is_32b(dec31_dec31_is_32b),
    .dec31_ldst_len(dec31_dec31_ldst_len),
    .dec31_lk(dec31_dec31_lk),
    .dec31_out_sel(dec31_dec31_out_sel),
    .dec31_rc_sel(dec31_dec31_rc_sel),
    .dec31_rsrv(dec31_dec31_rsrv),
    .dec31_sgl_pipe(dec31_dec31_sgl_pipe),
    .dec31_sgn(dec31_dec31_sgn),
    .dec31_sgn_ext(dec31_dec31_sgn_ext),
    .dec31_sv_cr_in(dec31_dec31_sv_cr_in),
    .dec31_sv_cr_out(dec31_dec31_sv_cr_out),
    .dec31_sv_in1(dec31_dec31_sv_in1),
    .dec31_sv_in2(dec31_dec31_sv_in2),
    .dec31_sv_in3(dec31_dec31_sv_in3),
    .dec31_sv_out(dec31_dec31_sv_out),
    .dec31_sv_out2(dec31_dec31_sv_out2),
    .dec31_upd(dec31_dec31_upd),
    .opcode_in(dec31_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69755.9-69790.4" *)
  dec58 dec58 (
    .dec58_SV_Etype(dec58_dec58_SV_Etype),
    .dec58_SV_Ptype(dec58_dec58_SV_Ptype),
    .dec58_asmcode(dec58_dec58_asmcode),
    .dec58_br(dec58_dec58_br),
    .dec58_cr_in(dec58_dec58_cr_in),
    .dec58_cr_out(dec58_dec58_cr_out),
    .dec58_cry_in(dec58_dec58_cry_in),
    .dec58_cry_out(dec58_dec58_cry_out),
    .dec58_form(dec58_dec58_form),
    .dec58_function_unit(dec58_dec58_function_unit),
    .dec58_in1_sel(dec58_dec58_in1_sel),
    .dec58_in2_sel(dec58_dec58_in2_sel),
    .dec58_in3_sel(dec58_dec58_in3_sel),
    .dec58_internal_op(dec58_dec58_internal_op),
    .dec58_inv_a(dec58_dec58_inv_a),
    .dec58_inv_out(dec58_dec58_inv_out),
    .dec58_is_32b(dec58_dec58_is_32b),
    .dec58_ldst_len(dec58_dec58_ldst_len),
    .dec58_lk(dec58_dec58_lk),
    .dec58_out_sel(dec58_dec58_out_sel),
    .dec58_rc_sel(dec58_dec58_rc_sel),
    .dec58_rsrv(dec58_dec58_rsrv),
    .dec58_sgl_pipe(dec58_dec58_sgl_pipe),
    .dec58_sgn(dec58_dec58_sgn),
    .dec58_sgn_ext(dec58_dec58_sgn_ext),
    .dec58_sv_cr_in(dec58_dec58_sv_cr_in),
    .dec58_sv_cr_out(dec58_dec58_sv_cr_out),
    .dec58_sv_in1(dec58_dec58_sv_in1),
    .dec58_sv_in2(dec58_dec58_sv_in2),
    .dec58_sv_in3(dec58_dec58_sv_in3),
    .dec58_sv_out(dec58_dec58_sv_out),
    .dec58_sv_out2(dec58_dec58_sv_out2),
    .dec58_upd(dec58_dec58_upd),
    .opcode_in(dec58_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:69791.9-69826.4" *)
  dec62 dec62 (
    .dec62_SV_Etype(dec62_dec62_SV_Etype),
    .dec62_SV_Ptype(dec62_dec62_SV_Ptype),
    .dec62_asmcode(dec62_dec62_asmcode),
    .dec62_br(dec62_dec62_br),
    .dec62_cr_in(dec62_dec62_cr_in),
    .dec62_cr_out(dec62_dec62_cr_out),
    .dec62_cry_in(dec62_dec62_cry_in),
    .dec62_cry_out(dec62_dec62_cry_out),
    .dec62_form(dec62_dec62_form),
    .dec62_function_unit(dec62_dec62_function_unit),
    .dec62_in1_sel(dec62_dec62_in1_sel),
    .dec62_in2_sel(dec62_dec62_in2_sel),
    .dec62_in3_sel(dec62_dec62_in3_sel),
    .dec62_internal_op(dec62_dec62_internal_op),
    .dec62_inv_a(dec62_dec62_inv_a),
    .dec62_inv_out(dec62_dec62_inv_out),
    .dec62_is_32b(dec62_dec62_is_32b),
    .dec62_ldst_len(dec62_dec62_ldst_len),
    .dec62_lk(dec62_dec62_lk),
    .dec62_out_sel(dec62_dec62_out_sel),
    .dec62_rc_sel(dec62_dec62_rc_sel),
    .dec62_rsrv(dec62_dec62_rsrv),
    .dec62_sgl_pipe(dec62_dec62_sgl_pipe),
    .dec62_sgn(dec62_dec62_sgn),
    .dec62_sgn_ext(dec62_dec62_sgn_ext),
    .dec62_sv_cr_in(dec62_dec62_sv_cr_in),
    .dec62_sv_cr_out(dec62_dec62_sv_cr_out),
    .dec62_sv_in1(dec62_dec62_sv_in1),
    .dec62_sv_in2(dec62_dec62_sv_in2),
    .dec62_sv_in3(dec62_dec62_sv_in3),
    .dec62_sv_out(dec62_dec62_sv_out),
    .dec62_sv_out2(dec62_dec62_sv_out2),
    .dec62_upd(dec62_dec62_upd),
    .opcode_in(dec62_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _013_ = 1'h0;
  end
  always @* begin
      \initial  <= _013_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _075_;
    (* src = "libresoc.v:69828.5-69828.29" *)
    casez (\initial )
      /* src = "libresoc.v:69828.9-69828.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _042_ = dec19_dec19_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _042_ = dec30_dec30_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _042_ = dec31_dec31_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _042_ = dec58_dec58_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _042_ = dec62_dec62_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _042_ = dec22_dec22_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _042_ = 5'h03;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _042_ = 5'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _042_ = 5'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _042_ = 5'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _042_ = 5'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _042_ = 5'h13;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _042_ = 5'h13;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _042_ = 5'h13;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _042_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _042_ = 5'h04;
        end
      default:
          _042_ = 5'h00;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _075_ = 5'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _075_ = 5'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _075_ = 5'h00;
        end
      default:
          _075_ = _042_;
    endcase
  end
  always @* begin
      form <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _069_;
    (* src = "libresoc.v:69973.5-69973.29" *)
    casez (\initial )
      /* src = "libresoc.v:69973.9-69973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _036_ = dec19_dec19_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _036_ = dec30_dec30_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _036_ = dec31_dec31_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _036_ = dec58_dec58_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _036_ = dec62_dec62_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _036_ = dec22_dec22_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _036_ = 8'h07;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _036_ = 8'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _036_ = 8'h06;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _036_ = 8'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
          _036_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _036_ = 8'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _036_ = 8'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _036_ = 8'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _036_ = 8'h15;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _036_ = 8'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _036_ = 8'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _036_ = 8'h4e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _036_ = 8'h4f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _036_ = 8'h58;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _036_ = 8'h5a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _036_ = 8'h5e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _036_ = 8'h5f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _036_ = 8'h67;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _036_ = 8'h69;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _036_ = 8'h80;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _036_ = 8'h8a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _036_ = 8'h8b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _036_ = 8'h98;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _036_ = 8'h99;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _036_ = 8'h9a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _036_ = 8'ha7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _036_ = 8'haa;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _036_ = 8'hb3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _036_ = 8'hb6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _036_ = 8'hb9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _036_ = 8'hbc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _036_ = 8'hc4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _036_ = 8'hcc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _036_ = 8'hd0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _036_ = 8'hd2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _036_ = 8'hd3;
        end
      default:
          _036_ = 8'h00;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _069_ = 8'h13;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _069_ = 8'h86;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _069_ = 8'h9d;
        end
      default:
          _069_ = _036_;
    endcase
  end
  always @* begin
      asmcode <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _067_;
    (* src = "libresoc.v:70118.5-70118.29" *)
    casez (\initial )
      /* src = "libresoc.v:70118.9-70118.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _034_ = dec19_dec19_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _034_ = dec30_dec30_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _034_ = dec31_dec31_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _034_ = dec58_dec58_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _034_ = dec62_dec62_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _034_ = dec22_dec22_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _034_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _034_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _034_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _034_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _034_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _034_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _034_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _034_ = 2'h2;
        end
      default:
          _034_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _067_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _067_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _067_ = 2'h0;
        end
      default:
          _067_ = _034_;
    endcase
  end
  always @* begin
      SV_Etype <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _068_;
    (* src = "libresoc.v:70263.5-70263.29" *)
    casez (\initial )
      /* src = "libresoc.v:70263.9-70263.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _035_ = dec19_dec19_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _035_ = dec30_dec30_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _035_ = dec31_dec31_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _035_ = dec58_dec58_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _035_ = dec62_dec62_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _035_ = dec22_dec22_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _035_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _035_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _035_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _035_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _035_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _035_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _035_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _035_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _035_ = 2'h2;
        end
      default:
          _035_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _068_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _068_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _068_ = 2'h0;
        end
      default:
          _068_ = _035_;
    endcase
  end
  always @* begin
      SV_Ptype <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _077_;
    (* src = "libresoc.v:70408.5-70408.29" *)
    casez (\initial )
      /* src = "libresoc.v:70408.9-70408.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _044_ = dec19_dec19_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _044_ = dec30_dec30_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _044_ = dec31_dec31_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _044_ = dec58_dec58_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _044_ = dec62_dec62_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _044_ = dec22_dec22_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _044_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _044_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _044_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _044_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _044_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _044_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _044_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _044_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _044_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _044_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _044_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _044_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _044_ = 3'h4;
        end
      default:
          _044_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _077_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _077_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _077_ = 3'h0;
        end
      default:
          _077_ = _044_;
    endcase
  end
  always @* begin
      in1_sel <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _078_;
    (* src = "libresoc.v:70553.5-70553.29" *)
    casez (\initial )
      /* src = "libresoc.v:70553.9-70553.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _045_ = dec19_dec19_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _045_ = dec30_dec30_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _045_ = dec31_dec31_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _045_ = dec58_dec58_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _045_ = dec62_dec62_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _045_ = dec22_dec22_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _045_ = 4'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _045_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _045_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _045_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _045_ = 4'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _045_ = 4'h7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _045_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _045_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _045_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _045_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _045_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _045_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _045_ = 4'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _045_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _045_ = 4'h4;
        end
      default:
          _045_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _078_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _078_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _078_ = 4'h0;
        end
      default:
          _078_ = _045_;
    endcase
  end
  always @* begin
      in2_sel <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _079_;
    (* src = "libresoc.v:70698.5-70698.29" *)
    casez (\initial )
      /* src = "libresoc.v:70698.9-70698.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _046_ = dec19_dec19_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _046_ = dec30_dec30_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _046_ = dec31_dec31_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _046_ = dec58_dec58_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _046_ = dec62_dec62_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _046_ = dec22_dec22_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _046_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _046_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _046_ = 2'h0;
        end
      default:
          _046_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _079_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _079_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _079_ = 2'h0;
        end
      default:
          _079_ = _046_;
    endcase
  end
  always @* begin
      in3_sel <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _086_;
    (* src = "libresoc.v:70843.5-70843.29" *)
    casez (\initial )
      /* src = "libresoc.v:70843.9-70843.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _053_ = dec19_dec19_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _053_ = dec30_dec30_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _053_ = dec31_dec31_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _053_ = dec58_dec58_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _053_ = dec62_dec62_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _053_ = dec22_dec22_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _053_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _053_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _053_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _053_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _053_ = 3'h2;
        end
      default:
          _053_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _086_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _086_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _086_ = 3'h1;
        end
      default:
          _086_ = _053_;
    endcase
  end
  always @* begin
      out_sel <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _071_;
    (* src = "libresoc.v:70988.5-70988.29" *)
    casez (\initial )
      /* src = "libresoc.v:70988.9-70988.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _038_ = dec19_dec19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _038_ = dec30_dec30_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _038_ = dec31_dec31_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _038_ = dec58_dec58_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _038_ = dec62_dec62_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _038_ = dec22_dec22_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _038_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _038_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _038_ = 3'h0;
        end
      default:
          _038_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _071_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _071_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _071_ = 3'h0;
        end
      default:
          _071_ = _038_;
    endcase
  end
  always @* begin
      cr_in <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _072_;
    (* src = "libresoc.v:71133.5-71133.29" *)
    casez (\initial )
      /* src = "libresoc.v:71133.9-71133.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _039_ = dec19_dec19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _039_ = dec30_dec30_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _039_ = dec31_dec31_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _039_ = dec58_dec58_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _039_ = dec62_dec62_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _039_ = dec22_dec22_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _039_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _039_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _039_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _039_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _039_ = 3'h0;
        end
      default:
          _039_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _072_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _072_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _072_ = 3'h0;
        end
      default:
          _072_ = _039_;
    endcase
  end
  always @* begin
      cr_out <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _094_;
    (* src = "libresoc.v:71278.5-71278.29" *)
    casez (\initial )
      /* src = "libresoc.v:71278.9-71278.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _061_ = dec19_dec19_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _061_ = dec30_dec30_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _061_ = dec31_dec31_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _061_ = dec58_dec58_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _061_ = dec62_dec62_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _061_ = dec22_dec22_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _061_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _061_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _061_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _061_ = 3'h2;
        end
      default:
          _061_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _094_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _094_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _094_ = 3'h0;
        end
      default:
          _094_ = _061_;
    endcase
  end
  always @* begin
      sv_in1 <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = _095_;
    (* src = "libresoc.v:71423.5-71423.29" *)
    casez (\initial )
      /* src = "libresoc.v:71423.9-71423.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _062_ = dec19_dec19_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _062_ = dec30_dec30_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _062_ = dec31_dec31_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _062_ = dec58_dec58_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _062_ = dec62_dec62_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _062_ = dec22_dec22_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _062_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _062_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _062_ = 3'h0;
        end
      default:
          _062_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _095_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _095_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _095_ = 3'h0;
        end
      default:
          _095_ = _062_;
    endcase
  end
  always @* begin
      sv_in2 <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _096_;
    (* src = "libresoc.v:71568.5-71568.29" *)
    casez (\initial )
      /* src = "libresoc.v:71568.9-71568.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _063_ = dec19_dec19_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _063_ = dec30_dec30_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _063_ = dec31_dec31_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _063_ = dec58_dec58_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _063_ = dec62_dec62_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _063_ = dec22_dec22_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _063_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _063_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _063_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _063_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _063_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _063_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _063_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _063_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _063_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _063_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _063_ = 3'h0;
        end
      default:
          _063_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _096_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _096_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _096_ = 3'h0;
        end
      default:
          _096_ = _063_;
    endcase
  end
  always @* begin
      sv_in3 <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _098_;
    (* src = "libresoc.v:71713.5-71713.29" *)
    casez (\initial )
      /* src = "libresoc.v:71713.9-71713.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _065_ = dec19_dec19_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _065_ = dec30_dec30_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _065_ = dec31_dec31_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _065_ = dec58_dec58_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _065_ = dec62_dec62_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _065_ = dec22_dec22_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _065_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _065_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _065_ = 3'h1;
        end
      default:
          _065_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _098_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _098_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _098_ = 3'h0;
        end
      default:
          _098_ = _065_;
    endcase
  end
  always @* begin
      sv_out <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = _097_;
    (* src = "libresoc.v:71858.5-71858.29" *)
    casez (\initial )
      /* src = "libresoc.v:71858.9-71858.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _064_ = dec19_dec19_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _064_ = dec30_dec30_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _064_ = dec31_dec31_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _064_ = dec58_dec58_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _064_ = dec62_dec62_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _064_ = dec22_dec22_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _064_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _064_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _064_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _064_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _064_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _064_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _064_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _064_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _064_ = 3'h0;
        end
      default:
          _064_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _097_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _097_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _097_ = 3'h0;
        end
      default:
          _097_ = _064_;
    endcase
  end
  always @* begin
      sv_out2 <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _092_;
    (* src = "libresoc.v:72003.5-72003.29" *)
    casez (\initial )
      /* src = "libresoc.v:72003.9-72003.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _059_ = dec19_dec19_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _059_ = dec30_dec30_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _059_ = dec31_dec31_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _059_ = dec58_dec58_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _059_ = dec62_dec62_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _059_ = dec22_dec22_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _059_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _059_ = 3'h0;
        end
      default:
          _059_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _092_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _092_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _092_ = 3'h0;
        end
      default:
          _092_ = _059_;
    endcase
  end
  always @* begin
      sv_cr_in <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _093_;
    (* src = "libresoc.v:72148.5-72148.29" *)
    casez (\initial )
      /* src = "libresoc.v:72148.9-72148.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _060_ = dec19_dec19_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _060_ = dec30_dec30_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _060_ = dec31_dec31_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _060_ = dec58_dec58_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _060_ = dec62_dec62_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _060_ = dec22_dec22_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _060_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _060_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _060_ = 3'h0;
        end
      default:
          _060_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _093_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _093_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _093_ = 3'h0;
        end
      default:
          _093_ = _060_;
    endcase
  end
  always @* begin
      sv_cr_out <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _084_;
    (* src = "libresoc.v:72293.5-72293.29" *)
    casez (\initial )
      /* src = "libresoc.v:72293.9-72293.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _051_ = dec19_dec19_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _051_ = dec30_dec30_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _051_ = dec31_dec31_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _051_ = dec58_dec58_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _051_ = dec62_dec62_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _051_ = dec22_dec22_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _051_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _051_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _051_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _051_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _051_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _051_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _051_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _051_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _051_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _051_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _051_ = 4'h0;
        end
      default:
          _051_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _084_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _084_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _084_ = 4'h0;
        end
      default:
          _084_ = _051_;
    endcase
  end
  always @* begin
      ldst_len <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = _099_;
    (* src = "libresoc.v:72438.5-72438.29" *)
    casez (\initial )
      /* src = "libresoc.v:72438.9-72438.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _066_ = dec19_dec19_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _066_ = dec30_dec30_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _066_ = dec31_dec31_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _066_ = dec58_dec58_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _066_ = dec62_dec62_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _066_ = dec22_dec22_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _066_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _066_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _066_ = 2'h0;
        end
      default:
          _066_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _099_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _099_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _099_ = 2'h0;
        end
      default:
          _099_ = _066_;
    endcase
  end
  always @* begin
      upd <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _087_;
    (* src = "libresoc.v:72583.5-72583.29" *)
    casez (\initial )
      /* src = "libresoc.v:72583.9-72583.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _054_ = dec19_dec19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _054_ = dec30_dec30_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _054_ = dec31_dec31_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _054_ = dec58_dec58_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _054_ = dec62_dec62_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _054_ = dec22_dec22_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _054_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _054_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _054_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _054_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _054_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _054_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _054_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _054_ = 2'h0;
        end
      default:
          _054_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _087_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _087_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _087_ = 2'h0;
        end
      default:
          _087_ = _054_;
    endcase
  end
  always @* begin
      rc_sel <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _073_;
    (* src = "libresoc.v:72728.5-72728.29" *)
    casez (\initial )
      /* src = "libresoc.v:72728.9-72728.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _040_ = dec19_dec19_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _040_ = dec30_dec30_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _040_ = dec31_dec31_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _040_ = dec58_dec58_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _040_ = dec62_dec62_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _040_ = dec22_dec22_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _040_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _040_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _040_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _040_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _040_ = 2'h0;
        end
      default:
          _040_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _073_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _073_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _073_ = 2'h0;
        end
      default:
          _073_ = _040_;
    endcase
  end
  always @* begin
      cry_in <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _081_;
    (* src = "libresoc.v:72873.5-72873.29" *)
    casez (\initial )
      /* src = "libresoc.v:72873.9-72873.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _048_ = dec19_dec19_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _048_ = dec30_dec30_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _048_ = dec31_dec31_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _048_ = dec58_dec58_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _048_ = dec62_dec62_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _048_ = dec22_dec22_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _048_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _048_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _048_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _048_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _048_ = 1'h0;
        end
      default:
          _048_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _081_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _081_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _081_ = 1'h0;
        end
      default:
          _081_ = _048_;
    endcase
  end
  always @* begin
      inv_a <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _082_;
    (* src = "libresoc.v:73018.5-73018.29" *)
    casez (\initial )
      /* src = "libresoc.v:73018.9-73018.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _049_ = dec19_dec19_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _049_ = dec30_dec30_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _049_ = dec31_dec31_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _049_ = dec58_dec58_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _049_ = dec62_dec62_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _049_ = dec22_dec22_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _049_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _049_ = 1'h0;
        end
      default:
          _049_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _082_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _082_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _082_ = 1'h0;
        end
      default:
          _082_ = _049_;
    endcase
  end
  always @* begin
      inv_out <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _074_;
    (* src = "libresoc.v:73163.5-73163.29" *)
    casez (\initial )
      /* src = "libresoc.v:73163.9-73163.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _041_ = dec19_dec19_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _041_ = dec30_dec30_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _041_ = dec31_dec31_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _041_ = dec58_dec58_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _041_ = dec62_dec62_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _041_ = dec22_dec22_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _041_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _041_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _041_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _041_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _041_ = 1'h0;
        end
      default:
          _041_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _074_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _074_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _074_ = 1'h0;
        end
      default:
          _074_ = _041_;
    endcase
  end
  always @* begin
      cry_out <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _070_;
    (* src = "libresoc.v:73308.5-73308.29" *)
    casez (\initial )
      /* src = "libresoc.v:73308.9-73308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _037_ = dec19_dec19_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _037_ = dec30_dec30_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _037_ = dec31_dec31_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _037_ = dec58_dec58_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _037_ = dec62_dec62_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _037_ = dec22_dec22_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _037_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _037_ = 1'h0;
        end
      default:
          _037_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _070_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _070_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _070_ = 1'h0;
        end
      default:
          _070_ = _037_;
    endcase
  end
  always @* begin
      br <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _091_;
    (* src = "libresoc.v:73453.5-73453.29" *)
    casez (\initial )
      /* src = "libresoc.v:73453.9-73453.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _058_ = dec19_dec19_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _058_ = dec30_dec30_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _058_ = dec31_dec31_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _058_ = dec58_dec58_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _058_ = dec62_dec62_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _058_ = dec22_dec22_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _058_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _058_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _058_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _058_ = 1'h0;
        end
      default:
          _058_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _091_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _091_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _091_ = 1'h0;
        end
      default:
          _091_ = _058_;
    endcase
  end
  always @* begin
      sgn_ext <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _088_;
    (* src = "libresoc.v:73598.5-73598.29" *)
    casez (\initial )
      /* src = "libresoc.v:73598.9-73598.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _055_ = dec19_dec19_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _055_ = dec30_dec30_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _055_ = dec31_dec31_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _055_ = dec58_dec58_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _055_ = dec62_dec62_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _055_ = dec22_dec22_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _055_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _055_ = 1'h0;
        end
      default:
          _055_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _088_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _088_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _088_ = 1'h0;
        end
      default:
          _088_ = _055_;
    endcase
  end
  always @* begin
      rsrv <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _083_;
    (* src = "libresoc.v:73743.5-73743.29" *)
    casez (\initial )
      /* src = "libresoc.v:73743.9-73743.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _050_ = dec19_dec19_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _050_ = dec30_dec30_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _050_ = dec31_dec31_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _050_ = dec58_dec58_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _050_ = dec62_dec62_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _050_ = dec22_dec22_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _050_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _050_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _050_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _050_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _050_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _050_ = 1'h0;
        end
      default:
          _050_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _083_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _083_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _083_ = 1'h0;
        end
      default:
          _083_ = _050_;
    endcase
  end
  always @* begin
      is_32b <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _090_;
    (* src = "libresoc.v:73888.5-73888.29" *)
    casez (\initial )
      /* src = "libresoc.v:73888.9-73888.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _057_ = dec19_dec19_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _057_ = dec30_dec30_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _057_ = dec31_dec31_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _057_ = dec58_dec58_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _057_ = dec62_dec62_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _057_ = dec22_dec22_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _057_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _057_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _057_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _057_ = 1'h0;
        end
      default:
          _057_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _090_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _090_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _090_ = 1'h0;
        end
      default:
          _090_ = _057_;
    endcase
  end
  always @* begin
      sgn <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _085_;
    (* src = "libresoc.v:74033.5-74033.29" *)
    casez (\initial )
      /* src = "libresoc.v:74033.9-74033.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _052_ = dec19_dec19_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _052_ = dec30_dec30_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _052_ = dec31_dec31_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _052_ = dec58_dec58_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _052_ = dec62_dec62_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _052_ = dec22_dec22_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _052_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _052_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _052_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _052_ = 1'h0;
        end
      default:
          _052_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _085_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _085_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _085_ = 1'h0;
        end
      default:
          _085_ = _052_;
    endcase
  end
  always @* begin
      lk <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = _089_;
    (* src = "libresoc.v:74178.5-74178.29" *)
    casez (\initial )
      /* src = "libresoc.v:74178.9-74178.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _056_ = dec19_dec19_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _056_ = dec30_dec30_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _056_ = dec31_dec31_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _056_ = dec58_dec58_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _056_ = dec62_dec62_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _056_ = dec22_dec22_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _056_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _056_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _056_ = 1'h0;
        end
      default:
          _056_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _089_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _089_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _089_ = 1'h1;
        end
      default:
          _089_ = _056_;
    endcase
  end
  always @* begin
      sgl_pipe <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _076_;
    (* src = "libresoc.v:74323.5-74323.29" *)
    casez (\initial )
      /* src = "libresoc.v:74323.9-74323.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _043_ = dec19_dec19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _043_ = dec30_dec30_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _043_ = dec31_dec31_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _043_ = dec58_dec58_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _043_ = dec62_dec62_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _043_ = dec22_dec22_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _043_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _043_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _043_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _043_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _043_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _043_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _043_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _043_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _043_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _043_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _043_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _043_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _043_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _043_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _043_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _043_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _043_ = 14'h0010;
        end
      default:
          _043_ = 14'h0000;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _076_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _076_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _076_ = 14'h0000;
        end
      default:
          _076_ = _043_;
    endcase
  end
  always @* begin
      function_unit <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _080_;
    (* src = "libresoc.v:74468.5-74468.29" *)
    casez (\initial )
      /* src = "libresoc.v:74468.9-74468.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      6'h13:
        begin
          _047_ = dec19_dec19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1e:
        begin
          _047_ = dec30_dec30_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1f:
        begin
          _047_ = dec31_dec31_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3a:
        begin
          _047_ = dec58_dec58_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h3e:
        begin
          _047_ = dec62_dec62_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h16:
        begin
          _047_ = dec22_dec22_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0c:
        begin
          _047_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0d:
        begin
          _047_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0e:
        begin
          _047_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0f:
        begin
          _047_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h11:
        begin
          _047_ = 7'h49;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1c:
        begin
          _047_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1d:
        begin
          _047_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h12:
        begin
          _047_ = 7'h06;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h10:
        begin
          _047_ = 7'h07;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0b:
        begin
          _047_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h0a:
        begin
          _047_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h22:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h23:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2a:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2b:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h28:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h29:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h20:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h21:
        begin
          _047_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h07:
        begin
          _047_ = 7'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h18:
        begin
          _047_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h19:
        begin
          _047_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h14:
        begin
          _047_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h15:
        begin
          _047_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h17:
        begin
          _047_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h26:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h27:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2c:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h2d:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h24:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h25:
        begin
          _047_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h08:
        begin
          _047_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h02:
        begin
          _047_ = 7'h3f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h03:
        begin
          _047_ = 7'h3f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1a:
        begin
          _047_ = 7'h43;
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'h1b:
        begin
          _047_ = 7'h43;
        end
      default:
          _047_ = 7'h00;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (\opcode_switch$1 )
      /* src = "libresoc.v:0.0-0.0" */
      32'b000000???????????????0100000000?:
        begin
          _080_ = 7'h05;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'd1610612736:
        begin
          _080_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      32'b000001???????????????0000000011?:
        begin
          _080_ = 7'h44;
        end
      default:
          _080_ = _047_;
    endcase
  end
  always @* begin
      internal_op <= _014_;
  end
  assign \$2  = _100_;
  assign VC_XO = opcode_in[9:0];
  assign VC_VRT = opcode_in[25:21];
  assign VC_VRB = opcode_in[15:11];
  assign VC_VRA = opcode_in[20:16];
  assign VC_Rc = opcode_in[10];
  assign XS_XO = opcode_in[10:2];
  assign XS_sh = { opcode_in[1], opcode_in[15:11] };
  assign XS_RS = opcode_in[25:21];
  assign XS_Rc = opcode_in[0];
  assign XS_RA = opcode_in[20:16];
  assign VA_XO = opcode_in[5:0];
  assign VA_VRT = opcode_in[25:21];
  assign VA_VRC = opcode_in[10:6];
  assign VA_VRB = opcode_in[15:11];
  assign VA_VRA = opcode_in[20:16];
  assign VA_SHB = opcode_in[9:6];
  assign VA_RT = opcode_in[25:21];
  assign VA_RC = opcode_in[10:6];
  assign VA_RB = opcode_in[15:11];
  assign VA_RA = opcode_in[20:16];
  assign TX_XO = opcode_in[6:1];
  assign TX_XBI = opcode_in[10:7];
  assign TX_UI = opcode_in[15:11];
  assign TX_RA = opcode_in[20:16];
  assign DQE_XO = opcode_in[1:0];
  assign DQE_RT = opcode_in[25:21];
  assign DQE_RA = opcode_in[20:16];
  assign all_PO = opcode_in[31:26];
  assign XO_XO = opcode_in[9:1];
  assign XO_RT = opcode_in[25:21];
  assign XO_Rc = opcode_in[0];
  assign XO_RB = opcode_in[15:11];
  assign XO_RA = opcode_in[20:16];
  assign XO_OE = opcode_in[10];
  assign SVL_XO = opcode_in[5:1];
  assign SVL_vs = opcode_in[7];
  assign SVL_SVi = opcode_in[15:8];
  assign SVL_RT = opcode_in[25:21];
  assign SVL_Rc = opcode_in[0];
  assign SVL_RA = opcode_in[20:16];
  assign SVL_ms = opcode_in[6];
  assign MD_XO = opcode_in[4:2];
  assign MD_sh = { opcode_in[1], opcode_in[15:11] };
  assign MD_RS = opcode_in[25:21];
  assign MD_Rc = opcode_in[0];
  assign MD_RA = opcode_in[20:16];
  assign MD_me = opcode_in[10:5];
  assign MD_mb = opcode_in[10:5];
  assign M_SH = opcode_in[15:11];
  assign M_RS = opcode_in[25:21];
  assign M_Rc = opcode_in[0];
  assign M_RB = opcode_in[15:11];
  assign M_RA = opcode_in[20:16];
  assign M_ME = opcode_in[5:1];
  assign M_MB = opcode_in[10:6];
  assign SC_XO_1 = opcode_in[1:0];
  assign SC_XO = opcode_in[1];
  assign SC_LEV = opcode_in[11:5];
  assign MDS_XO = opcode_in[4:1];
  assign MDS_XBI_1 = opcode_in[10:7];
  assign MDS_XBI = opcode_in[10:7];
  assign MDS_RS = opcode_in[25:21];
  assign MDS_Rc = opcode_in[0];
  assign MDS_RB = opcode_in[15:11];
  assign MDS_RA = opcode_in[20:16];
  assign MDS_me = opcode_in[10:5];
  assign MDS_mb = opcode_in[10:5];
  assign MDS_IS = opcode_in[25:21];
  assign MDS_IB = opcode_in[15:11];
  assign Z23_XO = opcode_in[8:1];
  assign Z23_TE = opcode_in[20:16];
  assign Z23_RMC = opcode_in[10:9];
  assign Z23_Rc = opcode_in[0];
  assign Z23_R = opcode_in[16];
  assign Z23_FRTp = opcode_in[25:21];
  assign Z23_FRT = opcode_in[25:21];
  assign Z23_FRBp = opcode_in[15:11];
  assign Z23_FRB = opcode_in[15:11];
  assign Z23_FRAp = opcode_in[20:16];
  assign Z23_FRA = opcode_in[20:16];
  assign XFL_XO = opcode_in[10:1];
  assign XFL_W = opcode_in[16];
  assign XFL_Rc = opcode_in[0];
  assign XFL_L = opcode_in[25];
  assign XFL_FRB = opcode_in[15:11];
  assign XFL_FLM = opcode_in[24:17];
  assign VX_XO_1 = opcode_in[10:0];
  assign VX_XO = { opcode_in[10], opcode_in[8:0] };
  assign VX_VRT = opcode_in[25:21];
  assign VX_VRB = opcode_in[15:11];
  assign VX_VRA = opcode_in[20:16];
  assign VX_UIM_3 = opcode_in[17:16];
  assign VX_UIM_2 = opcode_in[18:16];
  assign VX_UIM_1 = opcode_in[19:16];
  assign VX_UIM = opcode_in[20:16];
  assign VX_SIM = opcode_in[20:16];
  assign VX_RT = opcode_in[25:21];
  assign VX_RA = opcode_in[20:16];
  assign VX_PS = opcode_in[9];
  assign VX_EO = opcode_in[20:16];
  assign DS_XO = opcode_in[1:0];
  assign DS_VRT = opcode_in[25:21];
  assign DS_VRS = opcode_in[25:21];
  assign DS_RT = opcode_in[25:21];
  assign DS_RSp = opcode_in[25:21];
  assign DS_RS = opcode_in[25:21];
  assign DS_RA = opcode_in[20:16];
  assign DS_FRTp = opcode_in[25:21];
  assign DS_FRSp = opcode_in[25:21];
  assign DS_DS = opcode_in[15:2];
  assign DQ_XO = opcode_in[2:0];
  assign DQ_TX_T = { opcode_in[3], opcode_in[25:21] };
  assign DQ_T = opcode_in[25:21];
  assign DQ_TX = opcode_in[3];
  assign DQ_SX_S = { opcode_in[3], opcode_in[25:21] };
  assign DQ_S = opcode_in[25:21];
  assign DQ_SX = opcode_in[3];
  assign DQ_RTp = opcode_in[25:21];
  assign DQ_RA = opcode_in[20:16];
  assign DQ_PT = opcode_in[3:0];
  assign DQ_DQ = opcode_in[15:4];
  assign DX_XO = opcode_in[5:1];
  assign DX_RT = opcode_in[25:21];
  assign DX_d0_d1_d2 = { opcode_in[15:6], opcode_in[20:16], opcode_in[0] };
  assign DX_d2 = opcode_in[0];
  assign DX_d1 = opcode_in[20:16];
  assign DX_d0 = opcode_in[15:6];
  assign XFX_XO = opcode_in[10:1];
  assign XFX_SPR = opcode_in[20:11];
  assign XFX_RT = opcode_in[25:21];
  assign XFX_RS = opcode_in[25:21];
  assign XFX_FXM = opcode_in[19:12];
  assign XFX_DUIS = opcode_in[20:11];
  assign XFX_DUI = opcode_in[25:21];
  assign XFX_BHRBE = opcode_in[20:11];
  assign EVS_BFA = opcode_in[2:0];
  assign Z22_XO = opcode_in[9:1];
  assign Z22_SH = opcode_in[15:10];
  assign Z22_Rc = opcode_in[0];
  assign Z22_FRTp = opcode_in[25:21];
  assign Z22_FRT = opcode_in[25:21];
  assign Z22_FRAp = opcode_in[20:16];
  assign Z22_FRA = opcode_in[20:16];
  assign Z22_DGM = opcode_in[15:10];
  assign Z22_DCM = opcode_in[15:10];
  assign Z22_BF = opcode_in[25:23];
  assign XX2_XO_1 = opcode_in[10:2];
  assign XX2_XO = { opcode_in[10:7], opcode_in[5:3] };
  assign XX2_UIM_1 = opcode_in[17:16];
  assign XX2_UIM = opcode_in[19:16];
  assign XX2_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX2_T = opcode_in[25:21];
  assign XX2_TX = opcode_in[0];
  assign XX2_RT = opcode_in[25:21];
  assign XX2_EO = opcode_in[20:16];
  assign XX2_DCMX = opcode_in[22:16];
  assign XX2_dc_dm_dx = { opcode_in[6], opcode_in[2], opcode_in[20:16] };
  assign XX2_dx = opcode_in[20:16];
  assign XX2_dm = opcode_in[2];
  assign XX2_dc = opcode_in[6];
  assign XX2_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX2_B = opcode_in[15:11];
  assign XX2_BX = opcode_in[1];
  assign XX2_BF = opcode_in[25:23];
  assign D_UI = opcode_in[15:0];
  assign D_TO = opcode_in[25:21];
  assign D_SI = opcode_in[15:0];
  assign D_RT = opcode_in[25:21];
  assign D_RS = opcode_in[25:21];
  assign D_RA = opcode_in[20:16];
  assign D_L = opcode_in[21];
  assign D_FRT = opcode_in[25:21];
  assign D_FRS = opcode_in[25:21];
  assign D_D = opcode_in[15:0];
  assign D_BF = opcode_in[25:23];
  assign A_XO = opcode_in[5:1];
  assign A_RT = opcode_in[25:21];
  assign A_Rc = opcode_in[0];
  assign A_RB = opcode_in[15:11];
  assign A_RA = opcode_in[20:16];
  assign A_FRT = opcode_in[25:21];
  assign A_FRC = opcode_in[10:6];
  assign A_FRB = opcode_in[15:11];
  assign A_FRA = opcode_in[20:16];
  assign A_BC = opcode_in[10:6];
  assign XL_XO = opcode_in[10:1];
  assign XL_S = opcode_in[11];
  assign XL_OC = opcode_in[25:11];
  assign XL_LK = opcode_in[0];
  assign XL_BT = opcode_in[25:21];
  assign XL_BO_1 = opcode_in[25:21];
  assign XL_BO = opcode_in[25:21];
  assign XL_BI = opcode_in[20:16];
  assign XL_BH = opcode_in[12:11];
  assign XL_BFA = opcode_in[20:18];
  assign XL_BF = opcode_in[25:23];
  assign XL_BB = opcode_in[15:11];
  assign XL_BA = opcode_in[20:16];
  assign XX4_XO = opcode_in[5:4];
  assign XX4_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX4_T = opcode_in[25:21];
  assign XX4_TX = opcode_in[0];
  assign XX4_CX_C = { opcode_in[3], opcode_in[10:6] };
  assign XX4_C = opcode_in[10:6];
  assign XX4_CX = opcode_in[3];
  assign XX4_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX4_B = opcode_in[15:11];
  assign XX4_BX = opcode_in[1];
  assign XX4_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX4_A = opcode_in[20:16];
  assign XX4_AX = opcode_in[2];
  assign XX3_XO_2 = opcode_in[9:1];
  assign XX3_XO_1 = opcode_in[10:3];
  assign XX3_XO = opcode_in[10:7];
  assign XX3_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign XX3_T = opcode_in[25:21];
  assign XX3_TX = opcode_in[0];
  assign XX3_SHW = opcode_in[9:8];
  assign XX3_Rc = opcode_in[10];
  assign XX3_DM = opcode_in[9:8];
  assign XX3_BX_B = { opcode_in[1], opcode_in[15:11] };
  assign XX3_B = opcode_in[15:11];
  assign XX3_BX = opcode_in[1];
  assign XX3_BF = opcode_in[25:23];
  assign XX3_AX_A = { opcode_in[2], opcode_in[20:16] };
  assign XX3_A = opcode_in[20:16];
  assign XX3_AX = opcode_in[2];
  assign I_LK = opcode_in[0];
  assign I_LI = opcode_in[25:2];
  assign I_AA = opcode_in[1];
  assign B_LK = opcode_in[0];
  assign B_BO = opcode_in[25:21];
  assign B_BI = opcode_in[20:16];
  assign B_BD = opcode_in[15:2];
  assign B_AA = opcode_in[1];
  assign X_XO_1 = opcode_in[8:1];
  assign X_XO = opcode_in[10:1];
  assign X_WC = opcode_in[22:21];
  assign X_W = opcode_in[16];
  assign X_VRT = opcode_in[25:21];
  assign X_VRS = opcode_in[25:21];
  assign X_UIM = opcode_in[20:16];
  assign X_U = opcode_in[15:12];
  assign X_TX_T = { opcode_in[0], opcode_in[25:21] };
  assign X_TX = opcode_in[0];
  assign X_TO = opcode_in[25:21];
  assign X_TH = opcode_in[25:21];
  assign X_TBR = opcode_in[20:11];
  assign X_T = opcode_in[25:21];
  assign X_SX_S = { opcode_in[0], opcode_in[25:21] };
  assign X_SX = opcode_in[0];
  assign X_SR = opcode_in[19:16];
  assign X_SP = opcode_in[20:19];
  assign X_SI = opcode_in[15:11];
  assign X_SH = opcode_in[15:11];
  assign X_S = opcode_in[25:21];
  assign X_RTp = opcode_in[25:21];
  assign X_RT = opcode_in[25:21];
  assign X_RSp = opcode_in[25:21];
  assign X_RS = opcode_in[25:21];
  assign X_RO = opcode_in[0];
  assign X_RM = opcode_in[12:11];
  assign X_RIC = opcode_in[19:18];
  assign X_Rc = opcode_in[0];
  assign X_RB = opcode_in[15:11];
  assign X_RA = opcode_in[20:16];
  assign X_R_1 = opcode_in[16];
  assign X_R = opcode_in[21];
  assign X_PRS = opcode_in[17];
  assign X_NB = opcode_in[15:11];
  assign X_MO = opcode_in[25:21];
  assign X_L3 = opcode_in[17:16];
  assign X_L1 = opcode_in[16];
  assign X_L = opcode_in[21];
  assign X_L2 = opcode_in[22:21];
  assign X_IMM8 = opcode_in[18:11];
  assign X_IH = opcode_in[23:21];
  assign X_FRTp = opcode_in[25:21];
  assign X_FRT = opcode_in[25:21];
  assign X_FRSp = opcode_in[25:21];
  assign X_FRS = opcode_in[25:21];
  assign X_FRBp = opcode_in[15:11];
  assign X_FRB = opcode_in[15:11];
  assign X_FRAp = opcode_in[20:16];
  assign X_FRA = opcode_in[20:16];
  assign X_FC = opcode_in[15:11];
  assign X_EX = opcode_in[0];
  assign X_EO_1 = opcode_in[20:16];
  assign X_EO = opcode_in[20:19];
  assign X_E_1 = opcode_in[19:16];
  assign X_E = opcode_in[15];
  assign X_DRM = opcode_in[13:11];
  assign X_DCMX = opcode_in[22:16];
  assign X_CT = opcode_in[24:21];
  assign X_BO = opcode_in[25:21];
  assign X_BFA = opcode_in[20:18];
  assign X_BF = opcode_in[25:23];
  assign X_A = opcode_in[25];
  assign SPR = opcode_in[20:11];
  assign MB = opcode_in[10:6];
  assign ME = opcode_in[5:1];
  assign SH = opcode_in[15:11];
  assign BC = opcode_in[10:6];
  assign TO = opcode_in[25:21];
  assign DS = opcode_in[15:2];
  assign D = opcode_in[15:0];
  assign BH = opcode_in[12:11];
  assign BI = opcode_in[20:16];
  assign BO = opcode_in[25:21];
  assign FXM = opcode_in[19:12];
  assign BT = opcode_in[25:21];
  assign BA = opcode_in[20:16];
  assign BB = opcode_in[15:11];
  assign CR = opcode_in[10:1];
  assign BF = opcode_in[25:23];
  assign BD = opcode_in[15:2];
  assign OE = opcode_in[10];
  assign Rc = opcode_in[0];
  assign AA = opcode_in[1];
  assign LK = opcode_in[0];
  assign LI = opcode_in[25:2];
  assign ME32 = opcode_in[5:1];
  assign MB32 = opcode_in[10:6];
  assign sh = { opcode_in[1], opcode_in[15:11] };
  assign SH32 = opcode_in[15:11];
  assign L = opcode_in[21];
  assign UI = opcode_in[15:0];
  assign SI = opcode_in[15:0];
  assign RB = opcode_in[15:11];
  assign RA = opcode_in[20:16];
  assign RT = opcode_in[25:21];
  assign RS = opcode_in[25:21];
  assign PO = opcode_in[31:26];
  assign opcode_in = \$2 ;
  assign \opcode_switch$1  = opcode_in;
  assign dec22_opcode_in = opcode_in;
  assign dec62_opcode_in = opcode_in;
  assign dec58_opcode_in = opcode_in;
  assign dec31_opcode_in = opcode_in;
  assign dec30_opcode_in = opcode_in;
  assign dec19_opcode_in = opcode_in;
  assign opcode_switch = opcode_in[31:26];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:74958.1-77024.10" *)
module dec19(dec19_function_unit, dec19_internal_op, dec19_form, dec19_asmcode, dec19_SV_Etype, dec19_SV_Ptype, dec19_in1_sel, dec19_in2_sel, dec19_in3_sel, dec19_out_sel, dec19_cr_in, dec19_cr_out, dec19_sv_in1, dec19_sv_in2, dec19_sv_in3, dec19_sv_out, dec19_sv_out2, dec19_sv_cr_in, dec19_sv_cr_out, dec19_ldst_len, dec19_upd, dec19_rc_sel, dec19_cry_in, dec19_inv_a, dec19_inv_out, dec19_cry_out, dec19_br, dec19_sgn_ext, dec19_rsrv, dec19_is_32b, dec19_sgn, dec19_lk, dec19_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:76711.3-76762.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:76763.3-76814.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:76087.3-76138.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:76295.3-76346.6" *)
  reg _03_;
  (* src = "libresoc.v:75359.3-75410.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:75411.3-75462.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:76035.3-76086.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:76243.3-76294.6" *)
  reg _07_;
  (* src = "libresoc.v:76451.3-76502.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:75307.3-75358.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:76815.3-76866.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:76867.3-76918.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:76919.3-76970.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:75879.3-75930.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:76139.3-76190.6" *)
  reg _14_;
  (* src = "libresoc.v:76191.3-76242.6" *)
  reg _15_;
  (* src = "libresoc.v:76503.3-76554.6" *)
  reg _16_;
  (* src = "libresoc.v:75827.3-75878.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:76607.3-76658.6" *)
  reg _18_;
  (* src = "libresoc.v:76971.3-77022.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:75983.3-76034.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:76399.3-76450.6" *)
  reg _21_;
  (* src = "libresoc.v:76659.3-76710.6" *)
  reg _22_;
  (* src = "libresoc.v:76555.3-76606.6" *)
  reg _23_;
  (* src = "libresoc.v:76347.3-76398.6" *)
  reg _24_;
  (* src = "libresoc.v:75723.3-75774.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:75775.3-75826.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:75463.3-75514.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:75515.3-75566.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:75567.3-75618.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:75671.3-75722.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:75619.3-75670.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:75931.3-75982.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:74959.7-74959.20" *)
  reg _33_;
  (* src = "libresoc.v:76711.3-76762.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:76763.3-76814.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:76087.3-76138.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:76295.3-76346.6" *)
  reg _37_;
  (* src = "libresoc.v:75359.3-75410.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:75411.3-75462.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:76035.3-76086.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:76243.3-76294.6" *)
  reg _41_;
  (* src = "libresoc.v:76451.3-76502.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:75307.3-75358.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:76815.3-76866.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:76867.3-76918.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:76919.3-76970.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:75879.3-75930.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:76139.3-76190.6" *)
  reg _48_;
  (* src = "libresoc.v:76191.3-76242.6" *)
  reg _49_;
  (* src = "libresoc.v:76503.3-76554.6" *)
  reg _50_;
  (* src = "libresoc.v:75827.3-75878.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:76607.3-76658.6" *)
  reg _52_;
  (* src = "libresoc.v:76971.3-77022.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:75983.3-76034.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:76399.3-76450.6" *)
  reg _55_;
  (* src = "libresoc.v:76659.3-76710.6" *)
  reg _56_;
  (* src = "libresoc.v:76555.3-76606.6" *)
  reg _57_;
  (* src = "libresoc.v:76347.3-76398.6" *)
  reg _58_;
  (* src = "libresoc.v:75723.3-75774.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:75775.3-75826.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:75463.3-75514.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:75515.3-75566.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:75567.3-75618.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:75671.3-75722.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:75619.3-75670.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:75931.3-75982.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_SV_Etype;
  reg [1:0] dec19_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_SV_Ptype;
  reg [1:0] dec19_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec19_asmcode;
  reg [7:0] dec19_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_br;
  reg dec19_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_cr_in;
  reg [2:0] dec19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_cr_out;
  reg [2:0] dec19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_cry_in;
  reg [1:0] dec19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_cry_out;
  reg dec19_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec19_form;
  reg [4:0] dec19_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec19_function_unit;
  reg [13:0] dec19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_in1_sel;
  reg [2:0] dec19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec19_in2_sel;
  reg [3:0] dec19_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_in3_sel;
  reg [1:0] dec19_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec19_internal_op;
  reg [6:0] dec19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_inv_a;
  reg dec19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_inv_out;
  reg dec19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_is_32b;
  reg dec19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec19_ldst_len;
  reg [3:0] dec19_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_lk;
  reg dec19_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_out_sel;
  reg [2:0] dec19_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_rc_sel;
  reg [1:0] dec19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_rsrv;
  reg dec19_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_sgl_pipe;
  reg dec19_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_sgn;
  reg dec19_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec19_sgn_ext;
  reg dec19_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_cr_in;
  reg [2:0] dec19_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_cr_out;
  reg [2:0] dec19_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_in1;
  reg [2:0] dec19_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_in2;
  reg [2:0] dec19_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_in3;
  reg [2:0] dec19_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_out;
  reg [2:0] dec19_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec19_sv_out2;
  reg [2:0] dec19_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec19_upd;
  reg [1:0] dec19_upd;
  (* src = "libresoc.v:74959.7-74959.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:75308.5-75308.29" *)
    casez (\initial )
      /* src = "libresoc.v:75308.9-75308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _43_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _43_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _43_ = 14'h0020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _43_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _43_ = 14'h0080;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec19_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:75360.5-75360.29" *)
    casez (\initial )
      /* src = "libresoc.v:75360.9-75360.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _38_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _38_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _38_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _38_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _38_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:75412.5-75412.29" *)
    casez (\initial )
      /* src = "libresoc.v:75412.9-75412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _39_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _39_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:75464.5-75464.29" *)
    casez (\initial )
      /* src = "libresoc.v:75464.9-75464.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:75516.5-75516.29" *)
    casez (\initial )
      /* src = "libresoc.v:75516.9-75516.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:75568.5-75568.29" *)
    casez (\initial )
      /* src = "libresoc.v:75568.9-75568.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:75620.5-75620.29" *)
    casez (\initial )
      /* src = "libresoc.v:75620.9-75620.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:75672.5-75672.29" *)
    casez (\initial )
      /* src = "libresoc.v:75672.9-75672.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:75724.5-75724.29" *)
    casez (\initial )
      /* src = "libresoc.v:75724.9-75724.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _59_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _59_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:75776.5-75776.29" *)
    casez (\initial )
      /* src = "libresoc.v:75776.9-75776.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:75828.5-75828.29" *)
    casez (\initial )
      /* src = "libresoc.v:75828.9-75828.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec19_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:75880.5-75880.29" *)
    casez (\initial )
      /* src = "libresoc.v:75880.9-75880.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _47_ = 7'h2a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _47_ = 7'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _47_ = 7'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _47_ = 7'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _47_ = 7'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _47_ = 7'h24;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _47_ = 7'h46;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _47_ = 7'h46;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec19_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:75932.5-75932.29" *)
    casez (\initial )
      /* src = "libresoc.v:75932.9-75932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:75984.5-75984.29" *)
    casez (\initial )
      /* src = "libresoc.v:75984.9-75984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:76036.5-76036.29" *)
    casez (\initial )
      /* src = "libresoc.v:76036.9-76036.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:76088.5-76088.29" *)
    casez (\initial )
      /* src = "libresoc.v:76088.9-76088.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _36_ = 8'h6c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _36_ = 8'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _36_ = 8'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _36_ = 8'h27;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _36_ = 8'h28;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _36_ = 8'h29;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _36_ = 8'h2a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _36_ = 8'h2b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _36_ = 8'h2c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _36_ = 8'h16;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _36_ = 8'h17;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _36_ = 8'h18;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _36_ = 8'h4c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _36_ = 8'h91;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _36_ = 8'h48;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec19_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:76140.5-76140.29" *)
    casez (\initial )
      /* src = "libresoc.v:76140.9-76140.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:76192.5-76192.29" *)
    casez (\initial )
      /* src = "libresoc.v:76192.9-76192.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:76244.5-76244.29" *)
    casez (\initial )
      /* src = "libresoc.v:76244.9-76244.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:76296.5-76296.29" *)
    casez (\initial )
      /* src = "libresoc.v:76296.9-76296.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:76348.5-76348.29" *)
    casez (\initial )
      /* src = "libresoc.v:76348.9-76348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:76400.5-76400.29" *)
    casez (\initial )
      /* src = "libresoc.v:76400.9-76400.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:76452.5-76452.29" *)
    casez (\initial )
      /* src = "libresoc.v:76452.9-76452.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _42_ = 5'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _42_ = 5'h09;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec19_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:76504.5-76504.29" *)
    casez (\initial )
      /* src = "libresoc.v:76504.9-76504.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:76556.5-76556.29" *)
    casez (\initial )
      /* src = "libresoc.v:76556.9-76556.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:76608.5-76608.29" *)
    casez (\initial )
      /* src = "libresoc.v:76608.9-76608.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _52_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _52_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _52_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:76660.5-76660.29" *)
    casez (\initial )
      /* src = "libresoc.v:76660.9-76660.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec19_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:76712.5-76712.29" *)
    casez (\initial )
      /* src = "libresoc.v:76712.9-76712.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _34_ = 2'h0;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:76764.5-76764.29" *)
    casez (\initial )
      /* src = "libresoc.v:76764.9-76764.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _35_ = 2'h0;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:76816.5-76816.29" *)
    casez (\initial )
      /* src = "libresoc.v:76816.9-76816.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _44_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _44_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _44_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _44_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _44_ = 3'h3;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:76868.5-76868.29" *)
    casez (\initial )
      /* src = "libresoc.v:76868.9-76868.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _45_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _45_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _45_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _45_ = 4'hc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _45_ = 4'hc;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec19_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:76920.5-76920.29" *)
    casez (\initial )
      /* src = "libresoc.v:76920.9-76920.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec19_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:76972.5-76972.29" *)
    casez (\initial )
      /* src = "libresoc.v:76972.9-76972.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      10'h000:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h101:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h121:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0e1:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h021:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1c1:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1a1:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0c1:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h210:
        begin
          _53_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h010:
        begin
          _53_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h230:
        begin
          _53_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h096:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec19_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:77028.1-79249.10" *)
module dec2(bigendian, cur_pc, cur_msr, cur_dec, raw_opcode_in, asmcode, rego, rego_ok, ea, ea_ok, reg1, reg1_ok, reg2, reg2_ok, reg3, reg3_ok, spro, spro_ok, spr1, spr1_ok, xer_in, xer_out, fast1, fast1_ok, fast2, fast2_ok, fasto1, fasto1_ok, fasto2, fasto2_ok, cr_in1, cr_in1_ok, cr_in2, cr_in2_ok, \cr_in2$1 , \cr_in2_ok$2 , cr_out, cr_out_ok, msr, cia, insn, insn_type, fn_unit, lk, rc, rc_ok, oe, oe_ok, input_carry, traptype, \exc_$signal , \exc_$signal$3 , \exc_$signal$4 , \exc_$signal$5 , \exc_$signal$6 , \exc_$signal$7 , \exc_$signal$8 , \exc_$signal$9 , trapaddr, cr_rd, cr_rd_ok, cr_wr, cr_wr_ok, is_32bit, sv_a_nz, cur_eint);
  reg \initial  = 0;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _000_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _002_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _003_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _004_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _005_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _006_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _007_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _008_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _009_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _010_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _011_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _012_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _013_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _014_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _015_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _016_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _017_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _018_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _019_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _020_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _021_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _022_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _023_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _024_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _025_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _026_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _027_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _028_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _029_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _030_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _031_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [13:0] _032_;
  (* src = "libresoc.v:77029.7-77029.20" *)
  reg _033_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [1:0] _034_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [31:0] _035_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _036_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _037_;
  (* src = "libresoc.v:78988.3-79011.6" *)
  reg _038_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _039_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _040_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _041_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _042_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _043_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _044_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _045_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _046_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _047_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _048_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _049_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _050_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _051_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _052_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _053_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _054_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _055_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _056_;
  (* src = "libresoc.v:78914.3-78928.6" *)
  reg [13:0] _057_;
  (* src = "libresoc.v:78939.3-78951.6" *)
  reg [6:0] _058_;
  (* src = "libresoc.v:78929.3-78938.6" *)
  reg _059_;
  (* src = "libresoc.v:78978.3-78987.6" *)
  reg [12:0] _060_;
  (* src = "libresoc.v:78952.3-78967.6" *)
  reg [2:0] _061_;
  (* src = "libresoc.v:78968.3-78977.6" *)
  reg _062_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [12:0] _063_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _064_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _065_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _066_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _067_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _068_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _069_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _070_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _071_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _072_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _073_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _074_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _075_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _076_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _077_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _078_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _079_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _080_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _081_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _082_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _083_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _084_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _085_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _086_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _087_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _088_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _089_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _090_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _091_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _092_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _093_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _094_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _095_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _096_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _097_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _098_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [13:0] _099_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [1:0] _100_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [31:0] _101_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _102_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _103_;
  (* src = "libresoc.v:78988.3-79011.6" *)
  reg _104_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _105_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _106_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _107_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _108_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _109_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _110_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _111_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _112_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _113_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _114_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _115_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _116_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _117_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _118_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _119_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _120_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _121_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _122_;
  (* src = "libresoc.v:78914.3-78928.6" *)
  reg [13:0] _123_;
  (* src = "libresoc.v:78939.3-78951.6" *)
  reg [6:0] _124_;
  (* src = "libresoc.v:78929.3-78938.6" *)
  reg _125_;
  (* src = "libresoc.v:78978.3-78987.6" *)
  reg [12:0] _126_;
  (* src = "libresoc.v:78952.3-78967.6" *)
  reg [2:0] _127_;
  (* src = "libresoc.v:78968.3-78977.6" *)
  reg _128_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [12:0] _129_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _130_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _131_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _132_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _133_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _134_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _135_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _136_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _137_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _138_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _139_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _140_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _141_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _142_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _143_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _144_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _145_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _146_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _147_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _148_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _149_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _150_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _151_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _152_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _153_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _154_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _155_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _156_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _157_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _158_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _159_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _160_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _161_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _162_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _163_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _164_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [13:0] _165_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [1:0] _166_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [31:0] _167_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _168_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _169_;
  (* src = "libresoc.v:78988.3-79011.6" *)
  reg _170_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _171_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _172_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _173_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _174_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _175_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _176_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _177_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _178_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _179_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _180_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _181_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _182_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _183_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _184_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _185_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _186_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _187_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _188_;
  (* src = "libresoc.v:78952.3-78967.6" *)
  reg [2:0] _189_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [12:0] _190_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _191_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _192_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _193_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _194_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _195_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _196_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _197_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _198_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _199_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _200_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _201_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _202_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _203_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _204_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _205_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _206_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _207_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _208_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _209_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _210_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _211_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _212_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _213_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _214_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _215_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _216_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _217_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _218_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _219_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _220_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _221_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _222_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _223_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _224_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _225_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [13:0] _226_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [1:0] _227_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [31:0] _228_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _229_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _230_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _231_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _232_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _233_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _234_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _235_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _236_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _237_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _238_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _239_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _240_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _241_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _242_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _243_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _244_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _245_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _246_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _247_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _248_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [12:0] _249_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _250_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _251_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _252_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _253_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _254_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _255_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _256_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _257_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _258_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _259_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _260_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _261_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _262_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _263_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _264_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _265_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _266_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _267_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _268_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _269_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _270_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _271_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _272_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _273_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _274_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _275_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _276_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _277_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _278_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _279_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _280_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _281_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _282_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _283_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _284_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [13:0] _285_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [1:0] _286_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [31:0] _287_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _288_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _289_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _290_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [63:0] _291_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _292_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _293_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _294_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _295_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _296_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _297_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _298_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _299_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _300_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _301_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [6:0] _302_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _303_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _304_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _305_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [9:0] _306_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _307_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [12:0] _308_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [7:0] _309_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _310_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _311_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _312_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _313_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _314_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _315_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _316_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _317_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg [2:0] _318_;
  (* src = "libresoc.v:79012.3-79169.6" *)
  reg _319_;
  (* src = "libresoc.v:78735.19-78735.122" *)
  wire _320_;
  (* src = "libresoc.v:78736.19-78736.125" *)
  wire _321_;
  (* src = "libresoc.v:78737.19-78737.126" *)
  wire _322_;
  (* src = "libresoc.v:78744.18-78744.114" *)
  wire _323_;
  (* src = "libresoc.v:78745.18-78745.116" *)
  wire _324_;
  (* src = "libresoc.v:78747.18-78747.114" *)
  wire _325_;
  (* src = "libresoc.v:78749.18-78749.110" *)
  wire _326_;
  (* src = "libresoc.v:78761.18-78761.114" *)
  wire _327_;
  (* src = "libresoc.v:78762.18-78762.116" *)
  wire _328_;
  (* src = "libresoc.v:78764.18-78764.114" *)
  wire _329_;
  (* src = "libresoc.v:78766.18-78766.110" *)
  wire _330_;
  (* src = "libresoc.v:78731.19-78731.124" *)
  wire _331_;
  (* src = "libresoc.v:78732.19-78732.124" *)
  wire _332_;
  (* src = "libresoc.v:78733.19-78733.124" *)
  wire _333_;
  (* src = "libresoc.v:78734.19-78734.124" *)
  wire _334_;
  (* src = "libresoc.v:78738.19-78738.124" *)
  wire _335_;
  (* src = "libresoc.v:78739.18-78739.117" *)
  wire _336_;
  (* src = "libresoc.v:78740.18-78740.117" *)
  wire _337_;
  (* src = "libresoc.v:78742.18-78742.117" *)
  wire _338_;
  (* src = "libresoc.v:78743.18-78743.127" *)
  wire _339_;
  (* src = "libresoc.v:78746.18-78746.127" *)
  wire _340_;
  (* src = "libresoc.v:78750.18-78750.122" *)
  wire _341_;
  (* src = "libresoc.v:78751.18-78751.122" *)
  wire _342_;
  (* src = "libresoc.v:78753.18-78753.110" *)
  wire _343_;
  (* src = "libresoc.v:78754.18-78754.110" *)
  wire _344_;
  (* src = "libresoc.v:78756.18-78756.112" *)
  wire _345_;
  (* src = "libresoc.v:78758.18-78758.110" *)
  wire _346_;
  (* src = "libresoc.v:78760.18-78760.127" *)
  wire _347_;
  (* src = "libresoc.v:78763.18-78763.127" *)
  wire _348_;
  (* src = "libresoc.v:78728.19-78728.124" *)
  wire [6:0] _349_;
  (* src = "libresoc.v:78729.19-78729.124" *)
  wire [6:0] _350_;
  (* src = "libresoc.v:78730.19-78730.123" *)
  wire [6:0] _351_;
  (* src = "libresoc.v:78767.18-78767.111" *)
  wire [6:0] _352_;
  (* src = "libresoc.v:78768.18-78768.111" *)
  wire [6:0] _353_;
  (* src = "libresoc.v:78769.18-78769.111" *)
  wire [6:0] _354_;
  (* src = "libresoc.v:78770.18-78770.113" *)
  wire [6:0] _355_;
  (* src = "libresoc.v:78771.18-78771.121" *)
  wire [6:0] _356_;
  (* src = "libresoc.v:78748.18-78748.110" *)
  wire _357_;
  (* src = "libresoc.v:78765.18-78765.110" *)
  wire _358_;
  (* src = "libresoc.v:78741.18-78741.111" *)
  wire _359_;
  (* src = "libresoc.v:78752.18-78752.110" *)
  wire _360_;
  (* src = "libresoc.v:78755.18-78755.110" *)
  wire _361_;
  (* src = "libresoc.v:78757.18-78757.110" *)
  wire _362_;
  (* src = "libresoc.v:78759.18-78759.110" *)
  wire _363_;
  (* src = "libresoc.v:78728.19-78728.124" *)
  wire [6:0] _364_;
  (* src = "libresoc.v:78729.19-78729.124" *)
  wire [6:0] _365_;
  (* src = "libresoc.v:78730.19-78730.123" *)
  wire [6:0] _366_;
  (* src = "libresoc.v:78767.18-78767.111" *)
  wire [6:0] _367_;
  (* src = "libresoc.v:78768.18-78768.111" *)
  wire [6:0] _368_;
  (* src = "libresoc.v:78769.18-78769.111" *)
  wire [6:0] _369_;
  (* src = "libresoc.v:78770.18-78770.113" *)
  wire [6:0] _370_;
  (* src = "libresoc.v:78771.18-78771.121" *)
  wire [6:0] _371_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *)
  wire \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *)
  wire \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *)
  wire \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *)
  wire \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
  output [7:0] asmcode;
  reg [7:0] asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  output [63:0] cia;
  reg [63:0] cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] cr_in1;
  reg [6:0] cr_in1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_in1_ok;
  reg cr_in1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] cr_in2;
  reg [6:0] cr_in2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] \cr_in2$1 ;
  reg [6:0] \cr_in2$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_in2_ok;
  reg cr_in2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_in2_ok$2 ;
  reg \cr_in2_ok$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] cr_out;
  reg [6:0] cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_out_ok;
  reg cr_out_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [7:0] cr_rd;
  reg [7:0] cr_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_rd_ok;
  reg cr_rd_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [7:0] cr_wr;
  reg [7:0] cr_wr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_wr_ok;
  reg cr_wr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *)
  input [63:0] cur_dec;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *)
  input cur_eint;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  input [63:0] cur_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  input [63:0] cur_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [7:0] dec_FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [4:0] dec_XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [9:0] dec_XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] dec_X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  wire [2:0] dec_X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_a_fast_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_a_fast_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [4:0] dec_a_reg_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_a_reg_a_ok;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *)
  wire [2:0] dec_a_sel_in;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] dec_a_spr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_a_spr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *)
  wire dec_a_sv_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_b_fast_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_b_fast_b_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec_b_reg_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_b_reg_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *)
  wire [3:0] dec_b_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [4:0] dec_c_reg_c;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_c_reg_c_ok;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *)
  wire [1:0] dec_c_sel_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_cr_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_cr_in_cr_bitfield;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_cr_in_cr_bitfield_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_in_cr_bitfield_b_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_cr_in_cr_bitfield_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_in_cr_bitfield_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_in_cr_bitfield_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] dec_cr_in_cr_fxm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_in_cr_fxm_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *)
  wire [31:0] dec_cr_in_insn_in;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *)
  wire [2:0] dec_cr_in_sel_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_cr_out_cr_bitfield;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_out_cr_bitfield_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] dec_cr_out_cr_fxm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_cr_out_cr_fxm_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *)
  wire [31:0] dec_cr_out_insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *)
  wire dec_cr_out_rc_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *)
  wire [2:0] dec_cr_out_sel_in;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_cry_in;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1244" *)
  wire dec_irq_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_is_32b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_o2_fast_o2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_o2_fast_o2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *)
  wire dec_o2_lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [4:0] dec_o2_reg_o2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_o2_reg_o2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec_o_fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_o_fast_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [4:0] dec_o_reg_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_o_reg_o_ok;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *)
  wire [2:0] dec_o_sel_in;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] dec_o_spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_o_spr_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_out_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_rc_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] ea;
  reg [6:0] ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ea_ok;
  reg ea_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal ;
  reg \exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$3 ;
  reg \exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$4 ;
  reg \exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$5 ;
  reg \exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$6 ;
  reg \exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$7 ;
  reg \exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$8 ;
  reg \exc_$signal$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \exc_$signal$9 ;
  reg \exc_$signal$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1243" *)
  wire ext_irq_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast1;
  reg [2:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast2;
  reg [2:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  reg fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fasto1;
  reg [2:0] fasto1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fasto1_ok;
  reg fasto1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fasto2;
  reg [2:0] fasto2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fasto2_ok;
  reg fasto2_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  output [13:0] fn_unit;
  reg [13:0] fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1246" *)
  wire illeg_ok;
  (* src = "libresoc.v:77029.7-77029.15" *)
  reg \initial ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  output [1:0] input_carry;
  reg [1:0] input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  output [31:0] insn;
  reg [31:0] insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" *)
  wire [31:0] \insn_in$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210" *)
  wire [31:0] \insn_in$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316" *)
  wire [31:0] \insn_in$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352" *)
  wire [31:0] \insn_in$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" *)
  wire [31:0] \insn_in$89 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  output [6:0] insn_type;
  reg [6:0] insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  output is_32bit;
  reg is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:53" *)
  reg is_priv_insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *)
  output lk;
  reg lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  output [63:0] msr;
  reg [63:0] msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1245" *)
  wire priv_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] reg1;
  reg [6:0] reg1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg1_ok;
  reg reg1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] reg2;
  reg [6:0] reg2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg2_ok;
  reg reg2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] reg3;
  reg [6:0] reg3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg3_ok;
  reg reg3_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] rego;
  reg [6:0] rego;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rego_ok;
  reg rego_ok;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:415" *)
  wire [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spr1;
  reg [9:0] spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  reg spr1_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spro;
  reg [9:0] spro;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spro_ok;
  reg spro_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  input sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
  wire [7:0] tmp_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_cr_in1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_cr_in1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_cr_in2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \tmp_cr_in2$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_cr_in2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \tmp_cr_in2_ok$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_cr_out_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_ea_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] tmp_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] tmp_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] tmp_fasto1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_fasto1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] tmp_fasto2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_fasto2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_reg1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_reg1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_reg2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_reg2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_reg3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_reg3_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] tmp_rego;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_rego_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] tmp_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_spr1_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] tmp_spro;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_spro_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  wire [63:0] tmp_tmp_cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] tmp_tmp_cr_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_cr_rd_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] tmp_tmp_cr_wr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_cr_wr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \tmp_tmp_exc_$signal$27 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  reg [13:0] tmp_tmp_fn_unit;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  wire [1:0] tmp_tmp_input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  wire [31:0] tmp_tmp_insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  reg [6:0] tmp_tmp_insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  wire tmp_tmp_is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *)
  reg tmp_tmp_lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  wire [63:0] tmp_tmp_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_oe_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire tmp_tmp_rc_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  reg [12:0] tmp_tmp_trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  wire [7:0] tmp_tmp_traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  reg [2:0] tmp_xer_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
  reg tmp_xer_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  output [12:0] trapaddr;
  reg [12:0] trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  output [7:0] traptype;
  reg [7:0] traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  output [2:0] xer_in;
  reg [2:0] xer_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
  output xer_out;
  reg xer_out;
  assign _320_ = cur_eint & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1249" *) cur_msr[15];
  assign _321_ = cur_dec[63] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1250" *) cur_msr[15];
  assign _322_ = is_priv_insn & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1251" *) cur_msr[14];
  assign _323_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$37 ;
  assign _324_ = \$39  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _325_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$43 ;
  assign _326_ = \$45  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$47 ;
  assign _327_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$71 ;
  assign _328_ = \$73  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _329_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$77 ;
  assign _330_ = \$79  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$81 ;
  assign _331_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *) 7'h2e;
  assign _332_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *) 7'h0a;
  assign _333_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *) 7'h31;
  assign _334_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *) 7'h3f;
  assign _335_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1252" *) 7'h00;
  assign _336_ = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1300" *) 7'h3f;
  assign _337_ = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) 7'h49;
  assign _338_ = insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *) 7'h46;
  assign _339_ = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _340_ = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _341_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _342_ = dec_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _343_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _344_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _345_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _346_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _347_ = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _348_ = dec_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _349_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_b;
  assign _350_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield_o;
  assign _351_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_out_cr_bitfield;
  assign _352_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_a_reg_a;
  assign _353_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_c_reg_c;
  assign _354_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o_reg_o;
  assign _355_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_o2_reg_o2;
  assign _356_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) dec_cr_in_cr_bitfield;
  assign _357_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _358_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _359_ = \$28  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *) \$30 ;
  assign _360_ = \$51  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$53 ;
  assign _361_ = \$57  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$59 ;
  assign _362_ = \$61  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$63 ;
  assign _363_ = \$65  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$67 ;
  assign _364_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _349_;
  assign _365_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _350_;
  assign _366_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _351_;
  assign _367_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _352_;
  assign _368_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _353_;
  assign _369_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _354_;
  assign _370_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _355_;
  assign _371_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _356_;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78772.13-78809.4" *)
  \dec$171  dec (
    .BA(dec_BA),
    .BB(dec_BB),
    .BC(dec_BC),
    .BI(dec_BI),
    .BO(dec_BO),
    .BT(dec_BT),
    .FXM(dec_FXM),
    .LK(dec_LK),
    .OE(dec_OE),
    .RA(dec_RA),
    .RB(dec_RB),
    .RS(dec_RS),
    .RT(dec_RT),
    .Rc(dec_Rc),
    .SPR(dec_SPR),
    .XL_BT(dec_XL_BT),
    .XL_XO(dec_XL_XO),
    .X_BF(dec_X_BF),
    .X_BFA(dec_X_BFA),
    .asmcode(dec_asmcode),
    .bigendian(bigendian),
    .cr_in(dec_cr_in),
    .cr_out(dec_cr_out),
    .cry_in(dec_cry_in),
    .function_unit(dec_function_unit),
    .in1_sel(dec_in1_sel),
    .in2_sel(dec_in2_sel),
    .in3_sel(dec_in3_sel),
    .internal_op(dec_internal_op),
    .is_32b(dec_is_32b),
    .lk(dec_lk),
    .opcode_in(dec_opcode_in),
    .out_sel(dec_out_sel),
    .raw_opcode_in(raw_opcode_in),
    .rc_sel(dec_rc_sel),
    .upd(dec_upd)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78810.9-78825.4" *)
  dec_a dec_a (
    .BO(dec_BO),
    .RA(dec_RA),
    .RS(dec_RS),
    .SPR(dec_SPR),
    .XL_XO(dec_XL_XO),
    .fast_a(dec_a_fast_a),
    .fast_a_ok(dec_a_fast_a_ok),
    .internal_op(dec_internal_op),
    .reg_a(dec_a_reg_a),
    .reg_a_ok(dec_a_reg_a_ok),
    .sel_in(dec_a_sel_in),
    .spr_a(dec_a_spr_a),
    .spr_a_ok(dec_a_spr_a_ok),
    .sv_nz(dec_a_sv_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78826.9-78836.4" *)
  dec_b dec_b (
    .RB(dec_RB),
    .RS(dec_RS),
    .XL_XO(dec_XL_XO),
    .fast_b(dec_b_fast_b),
    .fast_b_ok(dec_b_fast_b_ok),
    .internal_op(dec_internal_op),
    .reg_b(dec_b_reg_b),
    .reg_b_ok(dec_b_reg_b_ok),
    .sel_in(dec_b_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78837.9-78843.4" *)
  dec_c dec_c (
    .RB(dec_RB),
    .RS(dec_RS),
    .reg_c(dec_c_reg_c),
    .reg_c_ok(dec_c_reg_c_ok),
    .sel_in(dec_c_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78844.13-78863.4" *)
  dec_cr_in \dec_cr_in$10  (
    .BA(dec_BA),
    .BB(dec_BB),
    .BC(dec_BC),
    .BI(dec_BI),
    .BT(dec_BT),
    .FXM(dec_FXM),
    .X_BFA(dec_X_BFA),
    .cr_bitfield(dec_cr_in_cr_bitfield),
    .cr_bitfield_b(dec_cr_in_cr_bitfield_b),
    .cr_bitfield_b_ok(dec_cr_in_cr_bitfield_b_ok),
    .cr_bitfield_o(dec_cr_in_cr_bitfield_o),
    .cr_bitfield_o_ok(dec_cr_in_cr_bitfield_o_ok),
    .cr_bitfield_ok(dec_cr_in_cr_bitfield_ok),
    .cr_fxm(dec_cr_in_cr_fxm),
    .cr_fxm_ok(dec_cr_in_cr_fxm_ok),
    .insn_in(dec_cr_in_insn_in),
    .internal_op(dec_internal_op),
    .sel_in(dec_cr_in_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78864.14-78876.4" *)
  dec_cr_out \dec_cr_out$11  (
    .FXM(dec_FXM),
    .XL_BT(dec_XL_BT),
    .X_BF(dec_X_BF),
    .cr_bitfield(dec_cr_out_cr_bitfield),
    .cr_bitfield_ok(dec_cr_out_cr_bitfield_ok),
    .cr_fxm(dec_cr_out_cr_fxm),
    .cr_fxm_ok(dec_cr_out_cr_fxm_ok),
    .insn_in(dec_cr_out_insn_in),
    .internal_op(dec_internal_op),
    .rc_in(dec_cr_out_rc_in),
    .sel_in(dec_cr_out_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78877.9-78890.4" *)
  dec_o dec_o (
    .BO(dec_BO),
    .RA(dec_RA),
    .RT(dec_RT),
    .SPR(dec_SPR),
    .fast_o(dec_o_fast_o),
    .fast_o_ok(dec_o_fast_o_ok),
    .internal_op(dec_internal_op),
    .reg_o(dec_o_reg_o),
    .reg_o_ok(dec_o_reg_o_ok),
    .sel_in(dec_o_sel_in),
    .spr_o(dec_o_spr_o),
    .spr_o_ok(dec_o_spr_o_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78891.10-78900.4" *)
  dec_o2 dec_o2 (
    .RA(dec_RA),
    .fast_o2(dec_o2_fast_o2),
    .fast_o2_ok(dec_o2_fast_o2_ok),
    .internal_op(dec_internal_op),
    .lk(dec_o2_lk),
    .reg_o2(dec_o2_reg_o2),
    .reg_o2_ok(dec_o2_reg_o2_ok),
    .upd(dec_upd)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78901.16-78907.4" *)
  \dec_oe$173  dec_oe (
    .OE(dec_OE),
    .internal_op(dec_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:78908.16-78913.4" *)
  \dec_rc$172  dec_rc (
    .Rc(dec_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _033_ = 1'h0;
  end
  always @* begin
      \initial  <= _033_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _123_;
    (* src = "libresoc.v:78915.5-78915.29" *)
    casez (\initial )
      /* src = "libresoc.v:78915.9-78915.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$83 , \$75  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _123_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _123_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _123_ = dec_function_unit;
        end
    endcase
  end
  always @* begin
      tmp_tmp_fn_unit <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _125_;
    (* src = "libresoc.v:78930.5-78930.29" *)
    casez (\initial )
      /* src = "libresoc.v:78930.9-78930.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *)
    casez (dec_lk)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _125_ = dec_LK;
        end
      default:
          _125_ = 1'h0;
    endcase
  end
  always @* begin
      tmp_tmp_lk <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _124_;
    (* src = "libresoc.v:78940.5-78940.29" *)
    casez (\initial )
      /* src = "libresoc.v:78940.9-78940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$49 , \$41  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _124_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _124_ = 7'h00;
        end
      default:
          _124_ = dec_internal_op;
    endcase
  end
  always @* begin
      tmp_tmp_insn_type <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _189_;
    (* src = "libresoc.v:78953.5-78953.29" *)
    casez (\initial )
      /* src = "libresoc.v:78953.9-78953.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1218" *)
    casez (\$106 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = 3'h7;
        end
      default:
          _127_ = 3'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" *)
    casez (\$108 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _189_ = 3'h1;
        end
      default:
          _189_ = _127_;
    endcase
  end
  always @* begin
      tmp_xer_in <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _128_;
    (* src = "libresoc.v:78969.5-78969.29" *)
    casez (\initial )
      /* src = "libresoc.v:78969.9-78969.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" *)
    casez (\$110 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = 1'h1;
        end
      default:
          _128_ = 1'h0;
    endcase
  end
  always @* begin
      tmp_xer_out <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _126_;
    (* src = "libresoc.v:78979.5-78979.29" *)
    casez (\initial )
      /* src = "libresoc.v:78979.9-78979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1226" *)
    casez (\$112 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = 13'h0070;
        end
      default:
          _126_ = 13'h0000;
    endcase
  end
  always @* begin
      tmp_tmp_trapaddr <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _104_;
    (* src = "libresoc.v:78989.5-78989.29" *)
    casez (\initial )
      /* src = "libresoc.v:78989.9-78989.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54" *)
    casez (dec_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h05, 7'h47, 7'h48, 7'h4a, 7'h46:
        begin
          _104_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h4b:
        begin
          _104_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e, 7'h31:
        begin
          _104_ = _170_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60" *)
          casez (tmp_tmp_insn[20])
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _170_ = 1'h1;
              end
            default:
                _170_ = 1'h0;
          endcase
        end
      default:
          _104_ = 1'h0;
    endcase
  end
  always @* begin
      is_priv_insn <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _109_;
    _053_ = _119_;
    _054_ = _120_;
    _040_ = _106_;
    _015_ = _082_;
    _014_ = _081_;
    _008_ = _075_;
    _039_ = _105_;
    _001_ = _068_;
    _002_ = _069_;
    _003_ = _070_;
    _005_ = _072_;
    _004_ = _071_;
    _007_ = _074_;
    _006_ = _073_;
    _009_ = _076_;
    _010_ = _077_;
    _011_ = _078_;
    _012_ = _079_;
    _013_ = _080_;
    _023_ = _090_;
    _016_ = _083_;
    _017_ = _084_;
    _018_ = _085_;
    _019_ = _086_;
    _020_ = _087_;
    _021_ = _088_;
    _022_ = _089_;
    _032_ = _099_;
    _034_ = _100_;
    _035_ = _101_;
    _036_ = _102_;
    _037_ = _103_;
    _041_ = _107_;
    _042_ = _108_;
    _044_ = _110_;
    _045_ = _111_;
    _046_ = _112_;
    _047_ = _113_;
    _048_ = _114_;
    _049_ = _115_;
    _050_ = _116_;
    _051_ = _117_;
    _052_ = _118_;
    _055_ = _121_;
    _056_ = _122_;
    _063_ = _129_;
    _064_ = _130_;
    _065_ = _131_;
    _066_ = _132_;
    _028_ = _316_;
    _029_ = _317_;
    _030_ = _318_;
    _031_ = _319_;
    _024_ = _312_;
    _025_ = _313_;
    _026_ = _314_;
    _027_ = _315_;
    _000_ = dec_asmcode;
    (* src = "libresoc.v:79013.5-79013.29" *)
    casez (\initial )
      /* src = "libresoc.v:79013.9-79013.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1256" *)
    casez ({ illeg_ok, priv_ok, ext_irq_ok, dec_irq_ok, \dec2_exc_$signal  })
      /* src = "libresoc.v:0.0-0.0" */
      5'b????1:
        begin
          _091_ = _157_;
          _092_ = _158_;
          _093_ = _159_;
          _094_ = _160_;
          _109_ = _175_;
          _119_ = _185_;
          _120_ = _186_;
          _106_ = _172_;
          _082_ = _148_;
          _081_ = _147_;
          _067_ = _133_;
          _075_ = _141_;
          _105_ = _171_;
          _068_ = _134_;
          _069_ = _135_;
          _070_ = _136_;
          _072_ = _138_;
          _071_ = _137_;
          _074_ = _140_;
          _073_ = _139_;
          _076_ = _142_;
          _077_ = _143_;
          _078_ = _144_;
          _079_ = _145_;
          _080_ = _146_;
          _090_ = _156_;
          _083_ = _149_;
          _084_ = _150_;
          _085_ = _151_;
          _086_ = _152_;
          _087_ = _153_;
          _088_ = _154_;
          _089_ = _155_;
          _095_ = _161_;
          _096_ = _162_;
          _097_ = _163_;
          _098_ = _164_;
          _099_ = _165_;
          _100_ = _166_;
          _101_ = _167_;
          _102_ = _168_;
          _103_ = _169_;
          _107_ = _173_;
          _108_ = _174_;
          _110_ = _176_;
          _111_ = _177_;
          _112_ = _178_;
          _113_ = _179_;
          _114_ = _180_;
          _115_ = _181_;
          _116_ = _182_;
          _117_ = _183_;
          _118_ = _184_;
          _121_ = _187_;
          _122_ = _188_;
          _129_ = _190_;
          _130_ = _191_;
          _131_ = _192_;
          _132_ = _193_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1257" *)
          casez ({ \dec2_exc_$signal$13 , \dec2_exc_$signal$12  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                { _169_, _146_, _145_, _144_, _143_, _155_, _154_, _153_, _152_, _151_, _150_, _149_, _156_, _166_, _174_, _173_, _176_, _175_, _171_, _142_, _141_, _139_, _137_, _140_, _138_, _136_, _135_, _164_, _163_, _162_, _161_, _160_, _159_, _158_, _157_, _193_, _192_, _186_, _185_, _188_, _187_, _182_, _181_, _180_, _179_, _178_, _177_, _148_, _147_, _184_, _183_, _133_ } = 156'h000000000000000000000000000000000000000;
                _167_ = dec_opcode_in;
                _168_ = 7'h3f;
                _165_ = 14'h0080;
                _190_ = 13'h0060;
                _191_ = 8'h02;
                _172_ = cur_msr;
                _134_ = cur_pc;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _157_ = _218_;
                _158_ = _219_;
                _159_ = _220_;
                _160_ = _221_;
                _175_ = _235_;
                _185_ = _245_;
                _186_ = _246_;
                _172_ = _232_;
                _148_ = _209_;
                _147_ = _208_;
                _133_ = _194_;
                _141_ = _202_;
                _171_ = _231_;
                _134_ = _195_;
                _135_ = _196_;
                _136_ = _197_;
                _138_ = _199_;
                _137_ = _198_;
                _140_ = _201_;
                _139_ = _200_;
                _142_ = _203_;
                _143_ = _204_;
                _144_ = _205_;
                _145_ = _206_;
                _146_ = _207_;
                _156_ = _217_;
                _149_ = _210_;
                _150_ = _211_;
                _151_ = _212_;
                _152_ = _213_;
                _153_ = _214_;
                _154_ = _215_;
                _155_ = _216_;
                _161_ = _222_;
                _162_ = _223_;
                _163_ = _224_;
                _164_ = _225_;
                _165_ = _226_;
                _166_ = _227_;
                _167_ = _228_;
                _168_ = _229_;
                _169_ = _230_;
                _173_ = _233_;
                _174_ = _234_;
                _176_ = _236_;
                _177_ = _237_;
                _178_ = _238_;
                _179_ = _239_;
                _180_ = _240_;
                _181_ = _241_;
                _182_ = _242_;
                _183_ = _243_;
                _184_ = _244_;
                _187_ = _247_;
                _188_ = _248_;
                _190_ = _249_;
                _191_ = _250_;
                _192_ = _251_;
                _193_ = _252_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1260" *)
                casez (\dec2_exc_$signal$14 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _230_, _207_, _206_, _205_, _204_, _216_, _215_, _214_, _213_, _212_, _211_, _210_, _217_, _227_, _234_, _233_, _236_, _235_, _231_, _203_, _202_, _200_, _198_, _201_, _199_, _197_, _196_, _225_, _224_, _223_, _222_, _221_, _220_, _219_, _218_, _252_, _251_, _246_, _245_, _248_, _247_, _242_, _241_, _240_, _239_, _238_, _237_, _209_, _208_, _244_, _243_, _194_ } = 156'h000000000000000000000000000000000000000;
                      _228_ = dec_opcode_in;
                      _229_ = 7'h3f;
                      _226_ = 14'h0080;
                      _249_ = 13'h0048;
                      _250_ = 8'h02;
                      _232_ = cur_msr;
                      _195_ = cur_pc;
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      { _230_, _207_, _206_, _205_, _204_, _227_, _234_, _233_, _236_, _235_, _231_, _203_, _202_, _200_, _198_, _201_, _199_, _197_, _196_, _225_, _224_, _223_, _222_, _221_, _220_, _219_, _218_, _252_, _251_, _246_, _245_, _248_, _247_, _242_, _241_, _240_, _239_, _238_, _237_, _209_, _208_, _244_, _243_, _194_ } = 148'h0000000000000000000000000000000000000;
                      _228_ = dec_opcode_in;
                      _229_ = 7'h3f;
                      _226_ = 14'h0080;
                      _249_ = 13'h0040;
                      _250_ = 8'h40;
                      { _216_, _215_, _214_, _213_, _212_, _211_, _210_, _217_ } = { \dec2_exc_$signal$14 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal$15 , \dec2_exc_$signal$13 , \dec2_exc_$signal$12 , \dec2_exc_$signal  };
                      _232_ = cur_msr;
                      _195_ = cur_pc;
                    end
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _157_ = _277_;
                _158_ = _278_;
                _159_ = _279_;
                _160_ = _280_;
                _175_ = _294_;
                _185_ = _304_;
                _186_ = _305_;
                _172_ = _291_;
                _148_ = _268_;
                _147_ = _267_;
                _133_ = _253_;
                _141_ = _261_;
                _171_ = _290_;
                _134_ = _254_;
                _135_ = _255_;
                _136_ = _256_;
                _138_ = _258_;
                _137_ = _257_;
                _140_ = _260_;
                _139_ = _259_;
                _142_ = _262_;
                _143_ = _263_;
                _144_ = _264_;
                _145_ = _265_;
                _146_ = _266_;
                _156_ = _276_;
                _149_ = _269_;
                _150_ = _270_;
                _151_ = _271_;
                _152_ = _272_;
                _153_ = _273_;
                _154_ = _274_;
                _155_ = _275_;
                _161_ = _281_;
                _162_ = _282_;
                _163_ = _283_;
                _164_ = _284_;
                _165_ = _285_;
                _166_ = _286_;
                _167_ = _287_;
                _168_ = _288_;
                _169_ = _289_;
                _173_ = _292_;
                _174_ = _293_;
                _176_ = _295_;
                _177_ = _296_;
                _178_ = _297_;
                _179_ = _298_;
                _180_ = _299_;
                _181_ = _300_;
                _182_ = _301_;
                _183_ = _302_;
                _184_ = _303_;
                _187_ = _306_;
                _188_ = _307_;
                _190_ = _308_;
                _191_ = _309_;
                _192_ = _310_;
                _193_ = _311_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1266" *)
                casez (\dec2_exc_$signal$14 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _289_, _266_, _265_, _264_, _263_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _276_, _286_, _293_, _292_, _295_, _294_, _290_, _262_, _261_, _259_, _257_, _260_, _258_, _256_, _255_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _311_, _310_, _305_, _304_, _307_, _306_, _301_, _300_, _299_, _298_, _297_, _296_, _268_, _267_, _303_, _302_, _253_ } = 156'h000000000000000000000000000000000000000;
                      _287_ = dec_opcode_in;
                      _288_ = 7'h3f;
                      _285_ = 14'h0080;
                      _308_ = 13'h0038;
                      _309_ = 8'h02;
                      _291_ = cur_msr;
                      _254_ = cur_pc;
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      { _289_, _266_, _265_, _264_, _263_, _275_, _274_, _273_, _272_, _271_, _270_, _269_, _276_, _286_, _293_, _292_, _295_, _294_, _290_, _262_, _261_, _259_, _257_, _260_, _258_, _256_, _255_, _284_, _283_, _282_, _281_, _280_, _279_, _278_, _277_, _311_, _310_, _305_, _304_, _307_, _306_, _301_, _300_, _299_, _298_, _297_, _296_, _268_, _267_, _303_, _302_, _253_ } = 156'h000000000000000000000000000000000000000;
                      _287_ = dec_opcode_in;
                      _288_ = 7'h3f;
                      _285_ = 14'h0080;
                      _308_ = 13'h0030;
                      _309_ = 8'h02;
                      _291_ = cur_msr;
                      _254_ = cur_pc;
                    end
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'b???1?:
        begin
          { _103_, _080_, _079_, _078_, _077_, _089_, _088_, _087_, _086_, _085_, _084_, _083_, _090_, _100_, _108_, _107_, _110_, _109_, _105_, _076_, _075_, _073_, _071_, _074_, _072_, _070_, _069_, _098_, _097_, _096_, _095_, _094_, _093_, _092_, _091_, _132_, _131_, _120_, _119_, _122_, _121_, _116_, _115_, _114_, _113_, _112_, _111_, _082_, _081_, _118_, _117_, _067_ } = 156'h000000000000000000000000000000000000000;
          _101_ = dec_opcode_in;
          _102_ = 7'h3f;
          _099_ = 14'h0080;
          _129_ = 13'h0090;
          _130_ = 8'h20;
          _106_ = cur_msr;
          _068_ = cur_pc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'b??1??:
        begin
          { _103_, _080_, _079_, _078_, _077_, _089_, _088_, _087_, _086_, _085_, _084_, _083_, _090_, _100_, _108_, _107_, _110_, _109_, _105_, _076_, _075_, _073_, _071_, _074_, _072_, _070_, _069_, _098_, _097_, _096_, _095_, _094_, _093_, _092_, _091_, _132_, _131_, _120_, _119_, _122_, _121_, _116_, _115_, _114_, _113_, _112_, _111_, _082_, _081_, _118_, _117_, _067_ } = 156'h000000000000000000000000000000000000000;
          _101_ = dec_opcode_in;
          _102_ = 7'h3f;
          _099_ = 14'h0080;
          _129_ = 13'h0050;
          _130_ = 8'h10;
          _106_ = cur_msr;
          _068_ = cur_pc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'b?1???:
        begin
          { _103_, _080_, _079_, _078_, _077_, _089_, _088_, _087_, _086_, _085_, _084_, _083_, _090_, _100_, _108_, _107_, _110_, _109_, _105_, _076_, _075_, _073_, _071_, _074_, _072_, _070_, _069_, _098_, _097_, _096_, _095_, _094_, _093_, _092_, _091_, _132_, _131_, _120_, _119_, _122_, _121_, _116_, _115_, _114_, _113_, _112_, _111_, _082_, _081_, _118_, _117_, _067_ } = 156'h000000000000000000000000000000000000000;
          _101_ = dec_opcode_in;
          _102_ = 7'h3f;
          _099_ = 14'h0080;
          _129_ = 13'h0070;
          _130_ = 8'h02;
          _106_ = cur_msr;
          _068_ = cur_pc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1?:
        begin
          { _103_, _080_, _079_, _078_, _077_, _089_, _088_, _087_, _086_, _085_, _084_, _083_, _090_, _100_, _108_, _107_, _110_, _109_, _105_, _076_, _075_, _073_, _071_, _074_, _072_, _070_, _069_, _098_, _097_, _096_, _095_, _094_, _093_, _092_, _091_, _132_, _131_, _120_, _119_, _122_, _121_, _116_, _115_, _114_, _113_, _112_, _111_, _082_, _081_, _118_, _117_, _067_ } = 156'h000000000000000000000000000000000000000;
          _101_ = dec_opcode_in;
          _102_ = 7'h3f;
          _099_ = 14'h0080;
          _129_ = 13'h0070;
          _130_ = 8'h80;
          _106_ = cur_msr;
          _068_ = cur_pc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          { _103_, _080_, _079_, _078_, _077_, _129_, _089_, _088_, _087_, _086_, _085_, _084_, _083_, _090_, _130_, _100_, _108_, _107_, _110_, _109_, _105_, _099_, _102_, _101_, _068_, _106_, _076_, _075_, _073_, _071_, _074_, _072_, _070_, _069_, _098_, _097_, _096_, _095_, _094_, _093_, _092_, _091_, _132_, _131_, _120_, _119_, _122_, _121_, _116_, _115_, _114_, _113_, _112_, _111_, _082_, _081_, _118_, _117_, _067_ } = { tmp_tmp_is_32bit, tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr, tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd, tmp_tmp_trapaddr, \tmp_tmp_exc_$signal$27 , \tmp_tmp_exc_$signal$26 , \tmp_tmp_exc_$signal$25 , \tmp_tmp_exc_$signal$24 , \tmp_tmp_exc_$signal$23 , \tmp_tmp_exc_$signal$22 , \tmp_tmp_exc_$signal$21 , \tmp_tmp_exc_$signal , tmp_tmp_traptype, tmp_tmp_input_carry, tmp_tmp_oe_ok, tmp_tmp_oe, tmp_tmp_rc_ok, tmp_tmp_rc, tmp_tmp_lk, tmp_tmp_fn_unit, tmp_tmp_insn_type, tmp_tmp_insn, tmp_tmp_cia, tmp_tmp_msr, tmp_cr_out_ok, tmp_cr_out, \tmp_cr_in2_ok$20 , \tmp_cr_in2$19 , tmp_cr_in2_ok, tmp_cr_in2, tmp_cr_in1_ok, tmp_cr_in1, tmp_fasto2_ok, tmp_fasto2, tmp_fasto1_ok, tmp_fasto1, tmp_fast2_ok, tmp_fast2, tmp_fast1_ok, tmp_fast1, tmp_xer_out, tmp_xer_in, tmp_spr1_ok, tmp_spr1, tmp_spro_ok, tmp_spro, tmp_reg3_ok, tmp_reg3, tmp_reg2_ok, tmp_reg2, tmp_reg1_ok, tmp_reg1, tmp_ea_ok, tmp_ea, tmp_rego_ok, tmp_rego, tmp_asmcode };
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1301" *)
    casez (\$32 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _316_ = 3'h3;
          _317_ = 1'h1;
          _318_ = 3'h4;
          _319_ = 1'h1;
        end
      default:
        begin
          _316_ = _095_;
          _317_ = _096_;
          _318_ = _097_;
          _319_ = _098_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1310" *)
    casez (\$34 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _312_ = 3'h3;
          _313_ = 1'h1;
          _314_ = 3'h4;
          _315_ = 1'h1;
        end
      default:
        begin
          _312_ = _091_;
          _313_ = _092_;
          _314_ = _093_;
          _315_ = _094_;
        end
    endcase
  end
  always @* begin
      fast1 <= _024_;
      fast1_ok <= _025_;
      fast2 <= _026_;
      fast2_ok <= _027_;
      rc <= _043_;
      spr1 <= _053_;
      spr1_ok <= _054_;
      msr <= _040_;
      ea_ok <= _015_;
      ea <= _014_;
      asmcode <= _000_;
      cr_out <= _008_;
      lk <= _039_;
      cia <= _001_;
      cr_in1 <= _002_;
      cr_in1_ok <= _003_;
      cr_in2 <= _005_;
      \cr_in2$1  <= _004_;
      cr_in2_ok <= _007_;
      \cr_in2_ok$2  <= _006_;
      cr_out_ok <= _009_;
      cr_rd <= _010_;
      cr_rd_ok <= _011_;
      cr_wr <= _012_;
      cr_wr_ok <= _013_;
      \exc_$signal  <= _023_;
      \exc_$signal$3  <= _016_;
      \exc_$signal$4  <= _017_;
      \exc_$signal$5  <= _018_;
      \exc_$signal$6  <= _019_;
      \exc_$signal$7  <= _020_;
      \exc_$signal$8  <= _021_;
      \exc_$signal$9  <= _022_;
      fasto1 <= _028_;
      fasto1_ok <= _029_;
      fasto2 <= _030_;
      fasto2_ok <= _031_;
      fn_unit <= _032_;
      input_carry <= _034_;
      insn <= _035_;
      insn_type <= _036_;
      is_32bit <= _037_;
      oe <= _041_;
      oe_ok <= _042_;
      rc_ok <= _044_;
      reg1 <= _045_;
      reg1_ok <= _046_;
      reg2 <= _047_;
      reg2_ok <= _048_;
      reg3 <= _049_;
      reg3_ok <= _050_;
      rego <= _051_;
      rego_ok <= _052_;
      spro <= _055_;
      spro_ok <= _056_;
      trapaddr <= _063_;
      traptype <= _064_;
      xer_in <= _065_;
      xer_out <= _066_;
  end
  assign \$100  = _364_;
  assign \$102  = _365_;
  assign \$104  = _366_;
  assign \$106  = _331_;
  assign \$108  = _332_;
  assign \$110  = _333_;
  assign \$112  = _334_;
  assign \$114  = _320_;
  assign \$116  = _321_;
  assign \$118  = _322_;
  assign \$120  = _335_;
  assign \$28  = _336_;
  assign \$30  = _337_;
  assign \$32  = _359_;
  assign \$34  = _338_;
  assign \$37  = _339_;
  assign \$39  = _323_;
  assign \$41  = _324_;
  assign \$43  = _340_;
  assign \$45  = _325_;
  assign \$47  = _357_;
  assign \$49  = _326_;
  assign \$51  = _341_;
  assign \$53  = _342_;
  assign \$55  = _360_;
  assign \$57  = _343_;
  assign \$59  = _344_;
  assign \$61  = _361_;
  assign \$63  = _345_;
  assign \$65  = _362_;
  assign \$67  = _346_;
  assign \$69  = _363_;
  assign \$71  = _347_;
  assign \$73  = _327_;
  assign \$75  = _328_;
  assign \$77  = _348_;
  assign \$79  = _329_;
  assign \$81  = _358_;
  assign \$83  = _330_;
  assign \$90  = _367_;
  assign \$92  = _368_;
  assign \$94  = _369_;
  assign \$96  = _370_;
  assign \$98  = _371_;
  assign \dec2_exc_$signal  = 1'h0;
  assign \dec2_exc_$signal$12  = 1'h0;
  assign \dec2_exc_$signal$13  = 1'h0;
  assign \dec2_exc_$signal$14  = 1'h0;
  assign \dec2_exc_$signal$15  = 1'h0;
  assign \dec2_exc_$signal$16  = 1'h0;
  assign \dec2_exc_$signal$17  = 1'h0;
  assign \dec2_exc_$signal$18  = 1'h0;
  assign tmp_asmcode = 8'h00;
  assign tmp_tmp_traptype = 8'h00;
  assign \tmp_tmp_exc_$signal  = 1'h0;
  assign \tmp_tmp_exc_$signal$21  = 1'h0;
  assign \tmp_tmp_exc_$signal$22  = 1'h0;
  assign \tmp_tmp_exc_$signal$23  = 1'h0;
  assign \tmp_tmp_exc_$signal$24  = 1'h0;
  assign \tmp_tmp_exc_$signal$25  = 1'h0;
  assign \tmp_tmp_exc_$signal$26  = 1'h0;
  assign \tmp_tmp_exc_$signal$27  = 1'h0;
  assign illeg_ok = \$120 ;
  assign priv_ok = \$118 ;
  assign dec_irq_ok = \$116 ;
  assign ext_irq_ok = \$114 ;
  assign { tmp_fasto2_ok, tmp_fasto2 } = { dec_o2_fast_o2_ok, dec_o2_fast_o2 };
  assign { tmp_fasto1_ok, tmp_fasto1 } = { dec_o_fast_o_ok, dec_o_fast_o };
  assign { tmp_fast2_ok, tmp_fast2 } = { dec_b_fast_b_ok, dec_b_fast_b };
  assign { tmp_fast1_ok, tmp_fast1 } = { dec_a_fast_a_ok, dec_a_fast_a };
  assign { tmp_spro_ok, tmp_spro } = { dec_o_spr_o_ok, dec_o_spr_o };
  assign { tmp_spr1_ok, tmp_spr1 } = { dec_a_spr_a_ok, dec_a_spr_a };
  assign tmp_cr_out_ok = dec_cr_out_cr_bitfield_ok;
  assign tmp_cr_out = \$104 ;
  assign \tmp_cr_in2_ok$20  = dec_cr_in_cr_bitfield_o_ok;
  assign \tmp_cr_in2$19  = \$102 ;
  assign tmp_cr_in2_ok = dec_cr_in_cr_bitfield_b_ok;
  assign tmp_cr_in2 = \$100 ;
  assign tmp_cr_in1_ok = dec_cr_in_cr_bitfield_ok;
  assign tmp_cr_in1 = \$98 ;
  assign tmp_ea_ok = dec_o2_reg_o2_ok;
  assign tmp_ea = \$96 ;
  assign tmp_rego_ok = dec_o_reg_o_ok;
  assign tmp_rego = \$94 ;
  assign tmp_reg3_ok = dec_c_reg_c_ok;
  assign tmp_reg3 = \$92 ;
  assign tmp_reg2_ok = dec_b_reg_b_ok;
  assign tmp_reg2 = dec_b_reg_b;
  assign tmp_reg1_ok = dec_a_reg_a_ok;
  assign tmp_reg1 = \$90 ;
  assign dec_o2_lk = tmp_tmp_lk;
  assign sel_in = dec_out_sel;
  assign dec_o_sel_in = dec_out_sel;
  assign dec_c_sel_in = dec_in3_sel;
  assign dec_b_sel_in = dec_in2_sel;
  assign dec_a_sel_in = dec_in1_sel;
  assign { tmp_tmp_cr_wr_ok, tmp_tmp_cr_wr } = { dec_cr_out_cr_fxm_ok, dec_cr_out_cr_fxm };
  assign { tmp_tmp_cr_rd_ok, tmp_tmp_cr_rd } = { dec_cr_in_cr_fxm_ok, dec_cr_in_cr_fxm };
  assign dec_cr_out_rc_in = dec_rc_rc;
  assign dec_cr_out_sel_in = dec_cr_out;
  assign dec_cr_in_sel_in = dec_cr_in;
  assign \insn_in$89  = dec_opcode_in;
  assign \insn_in$88  = dec_opcode_in;
  assign \insn_in$87  = dec_opcode_in;
  assign dec_cr_out_insn_in = dec_opcode_in;
  assign dec_cr_in_insn_in = dec_opcode_in;
  assign \insn_in$86  = dec_opcode_in;
  assign \insn_in$85  = dec_opcode_in;
  assign tmp_tmp_insn = dec_opcode_in;
  assign dec_a_sv_nz = sv_a_nz;
  assign tmp_tmp_is_32bit = dec_is_32b;
  assign tmp_tmp_input_carry = dec_cry_in;
  assign { tmp_tmp_oe_ok, tmp_tmp_oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { tmp_tmp_rc_ok, tmp_tmp_rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign is_mmu_spr = \$69 ;
  assign is_spr_mv = \$55 ;
  assign spr = { dec_SPR[4:0], dec_SPR[9:5] };
  assign tmp_tmp_cia = cur_pc;
  assign tmp_tmp_msr = cur_msr;
  assign dec_oe_sel_in = dec_rc_sel;
  assign dec_rc_sel_in = dec_rc_sel;
  assign \insn_in$36  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec22" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:79253.1-79933.10" *)
module dec22(dec22_function_unit, dec22_internal_op, dec22_form, dec22_asmcode, dec22_SV_Etype, dec22_SV_Ptype, dec22_in1_sel, dec22_in2_sel, dec22_in3_sel, dec22_out_sel, dec22_cr_in, dec22_cr_out, dec22_sv_in1, dec22_sv_in2, dec22_sv_in3, dec22_sv_out, dec22_sv_out2, dec22_sv_cr_in, dec22_sv_cr_out, dec22_ldst_len, dec22_upd, dec22_rc_sel, dec22_cry_in, dec22_inv_a, dec22_inv_out, dec22_cry_out, dec22_br, dec22_sgn_ext, dec22_rsrv, dec22_is_32b, dec22_sgn, dec22_lk, dec22_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:79872.3-79881.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:79882.3-79891.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:79752.3-79761.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:79792.3-79801.6" *)
  reg _03_;
  (* src = "libresoc.v:79612.3-79621.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:79622.3-79631.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:79742.3-79751.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:79782.3-79791.6" *)
  reg _07_;
  (* src = "libresoc.v:79822.3-79831.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:79602.3-79611.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:79892.3-79901.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:79902.3-79911.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:79912.3-79921.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:79712.3-79721.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:79762.3-79771.6" *)
  reg _14_;
  (* src = "libresoc.v:79772.3-79781.6" *)
  reg _15_;
  (* src = "libresoc.v:79832.3-79841.6" *)
  reg _16_;
  (* src = "libresoc.v:79702.3-79711.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:79852.3-79861.6" *)
  reg _18_;
  (* src = "libresoc.v:79922.3-79931.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:79732.3-79741.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:79812.3-79821.6" *)
  reg _21_;
  (* src = "libresoc.v:79862.3-79871.6" *)
  reg _22_;
  (* src = "libresoc.v:79842.3-79851.6" *)
  reg _23_;
  (* src = "libresoc.v:79802.3-79811.6" *)
  reg _24_;
  (* src = "libresoc.v:79682.3-79691.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:79692.3-79701.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:79632.3-79641.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:79642.3-79651.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:79652.3-79661.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:79672.3-79681.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:79662.3-79671.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:79722.3-79731.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:79254.7-79254.20" *)
  reg _33_;
  (* src = "libresoc.v:79872.3-79881.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:79882.3-79891.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:79752.3-79761.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:79792.3-79801.6" *)
  reg _37_;
  (* src = "libresoc.v:79612.3-79621.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:79622.3-79631.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:79742.3-79751.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:79782.3-79791.6" *)
  reg _41_;
  (* src = "libresoc.v:79822.3-79831.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:79602.3-79611.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:79892.3-79901.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:79902.3-79911.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:79912.3-79921.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:79712.3-79721.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:79762.3-79771.6" *)
  reg _48_;
  (* src = "libresoc.v:79772.3-79781.6" *)
  reg _49_;
  (* src = "libresoc.v:79832.3-79841.6" *)
  reg _50_;
  (* src = "libresoc.v:79702.3-79711.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:79852.3-79861.6" *)
  reg _52_;
  (* src = "libresoc.v:79922.3-79931.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:79732.3-79741.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:79812.3-79821.6" *)
  reg _55_;
  (* src = "libresoc.v:79862.3-79871.6" *)
  reg _56_;
  (* src = "libresoc.v:79842.3-79851.6" *)
  reg _57_;
  (* src = "libresoc.v:79802.3-79811.6" *)
  reg _58_;
  (* src = "libresoc.v:79682.3-79691.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:79692.3-79701.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:79632.3-79641.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:79642.3-79651.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:79652.3-79661.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:79672.3-79681.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:79662.3-79671.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:79722.3-79731.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_SV_Etype;
  reg [1:0] dec22_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_SV_Ptype;
  reg [1:0] dec22_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec22_asmcode;
  reg [7:0] dec22_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_br;
  reg dec22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_cr_in;
  reg [2:0] dec22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_cr_out;
  reg [2:0] dec22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_cry_in;
  reg [1:0] dec22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_cry_out;
  reg dec22_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec22_form;
  reg [4:0] dec22_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec22_function_unit;
  reg [13:0] dec22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_in1_sel;
  reg [2:0] dec22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec22_in2_sel;
  reg [3:0] dec22_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_in3_sel;
  reg [1:0] dec22_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec22_internal_op;
  reg [6:0] dec22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_inv_a;
  reg dec22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_inv_out;
  reg dec22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_is_32b;
  reg dec22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec22_ldst_len;
  reg [3:0] dec22_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_lk;
  reg dec22_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_out_sel;
  reg [2:0] dec22_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_rc_sel;
  reg [1:0] dec22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_rsrv;
  reg dec22_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_sgl_pipe;
  reg dec22_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_sgn;
  reg dec22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec22_sgn_ext;
  reg dec22_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_cr_in;
  reg [2:0] dec22_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_cr_out;
  reg [2:0] dec22_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_in1;
  reg [2:0] dec22_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_in2;
  reg [2:0] dec22_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_in3;
  reg [2:0] dec22_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_out;
  reg [2:0] dec22_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec22_sv_out2;
  reg [2:0] dec22_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec22_upd;
  reg [1:0] dec22_upd;
  (* src = "libresoc.v:79254.7-79254.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [3:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:79603.5-79603.29" *)
    casez (\initial )
      /* src = "libresoc.v:79603.9-79603.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _43_ = 14'h2000;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec22_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:79613.5-79613.29" *)
    casez (\initial )
      /* src = "libresoc.v:79613.9-79613.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:79623.5-79623.29" *)
    casez (\initial )
      /* src = "libresoc.v:79623.9-79623.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:79633.5-79633.29" *)
    casez (\initial )
      /* src = "libresoc.v:79633.9-79633.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:79643.5-79643.29" *)
    casez (\initial )
      /* src = "libresoc.v:79643.9-79643.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:79653.5-79653.29" *)
    casez (\initial )
      /* src = "libresoc.v:79653.9-79653.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:79663.5-79663.29" *)
    casez (\initial )
      /* src = "libresoc.v:79663.9-79663.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:79673.5-79673.29" *)
    casez (\initial )
      /* src = "libresoc.v:79673.9-79673.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:79683.5-79683.29" *)
    casez (\initial )
      /* src = "libresoc.v:79683.9-79683.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:79693.5-79693.29" *)
    casez (\initial )
      /* src = "libresoc.v:79693.9-79693.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:79703.5-79703.29" *)
    casez (\initial )
      /* src = "libresoc.v:79703.9-79703.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec22_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:79713.5-79713.29" *)
    casez (\initial )
      /* src = "libresoc.v:79713.9-79713.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _47_ = 7'h4c;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec22_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:79723.5-79723.29" *)
    casez (\initial )
      /* src = "libresoc.v:79723.9-79723.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:79733.5-79733.29" *)
    casez (\initial )
      /* src = "libresoc.v:79733.9-79733.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:79743.5-79743.29" *)
    casez (\initial )
      /* src = "libresoc.v:79743.9-79743.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:79753.5-79753.29" *)
    casez (\initial )
      /* src = "libresoc.v:79753.9-79753.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _36_ = 8'h9c;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec22_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:79763.5-79763.29" *)
    casez (\initial )
      /* src = "libresoc.v:79763.9-79763.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:79773.5-79773.29" *)
    casez (\initial )
      /* src = "libresoc.v:79773.9-79773.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:79783.5-79783.29" *)
    casez (\initial )
      /* src = "libresoc.v:79783.9-79783.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:79793.5-79793.29" *)
    casez (\initial )
      /* src = "libresoc.v:79793.9-79793.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:79803.5-79803.29" *)
    casez (\initial )
      /* src = "libresoc.v:79803.9-79803.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:79813.5-79813.29" *)
    casez (\initial )
      /* src = "libresoc.v:79813.9-79813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:79823.5-79823.29" *)
    casez (\initial )
      /* src = "libresoc.v:79823.9-79823.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _42_ = 5'h1d;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec22_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:79833.5-79833.29" *)
    casez (\initial )
      /* src = "libresoc.v:79833.9-79833.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:79843.5-79843.29" *)
    casez (\initial )
      /* src = "libresoc.v:79843.9-79843.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:79853.5-79853.29" *)
    casez (\initial )
      /* src = "libresoc.v:79853.9-79853.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:79863.5-79863.29" *)
    casez (\initial )
      /* src = "libresoc.v:79863.9-79863.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec22_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:79873.5-79873.29" *)
    casez (\initial )
      /* src = "libresoc.v:79873.9-79873.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _34_ = 2'h0;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:79883.5-79883.29" *)
    casez (\initial )
      /* src = "libresoc.v:79883.9-79883.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _35_ = 2'h0;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:79893.5-79893.29" *)
    casez (\initial )
      /* src = "libresoc.v:79893.9-79893.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:79903.5-79903.29" *)
    casez (\initial )
      /* src = "libresoc.v:79903.9-79903.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec22_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:79913.5-79913.29" *)
    casez (\initial )
      /* src = "libresoc.v:79913.9-79913.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec22_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:79923.5-79923.29" *)
    casez (\initial )
      /* src = "libresoc.v:79923.9-79923.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _53_ = 3'h4;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec22_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[4:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec30" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:79937.1-81508.10" *)
module dec30(dec30_function_unit, dec30_internal_op, dec30_form, dec30_asmcode, dec30_SV_Etype, dec30_SV_Ptype, dec30_in1_sel, dec30_in2_sel, dec30_in3_sel, dec30_out_sel, dec30_cr_in, dec30_cr_out, dec30_sv_in1, dec30_sv_in2, dec30_sv_in3, dec30_sv_out, dec30_sv_out2, dec30_sv_cr_in, dec30_sv_cr_out, dec30_ldst_len, dec30_upd, dec30_rc_sel, dec30_cry_in, dec30_inv_a, dec30_inv_out, dec30_cry_out, dec30_br, dec30_sgn_ext, dec30_rsrv, dec30_is_32b, dec30_sgn, dec30_lk, dec30_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:81285.3-81321.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:81322.3-81358.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:80841.3-80877.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:80989.3-81025.6" *)
  reg _03_;
  (* src = "libresoc.v:80323.3-80359.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:80360.3-80396.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:80804.3-80840.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:80952.3-80988.6" *)
  reg _07_;
  (* src = "libresoc.v:81100.3-81136.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:80286.3-80322.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:81359.3-81395.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:81396.3-81432.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:81433.3-81469.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:80693.3-80729.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:80878.3-80914.6" *)
  reg _14_;
  (* src = "libresoc.v:80915.3-80951.6" *)
  reg _15_;
  (* src = "libresoc.v:81137.3-81173.6" *)
  reg _16_;
  (* src = "libresoc.v:80656.3-80692.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:81211.3-81247.6" *)
  reg _18_;
  (* src = "libresoc.v:81470.3-81506.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:80767.3-80803.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:81063.3-81099.6" *)
  reg _21_;
  (* src = "libresoc.v:81248.3-81284.6" *)
  reg _22_;
  (* src = "libresoc.v:81174.3-81210.6" *)
  reg _23_;
  (* src = "libresoc.v:81026.3-81062.6" *)
  reg _24_;
  (* src = "libresoc.v:80582.3-80618.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:80619.3-80655.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:80397.3-80433.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:80434.3-80470.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:80471.3-80507.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:80545.3-80581.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:80508.3-80544.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:80730.3-80766.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:79938.7-79938.20" *)
  reg _33_;
  (* src = "libresoc.v:81285.3-81321.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:81322.3-81358.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:80841.3-80877.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:80989.3-81025.6" *)
  reg _37_;
  (* src = "libresoc.v:80323.3-80359.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:80360.3-80396.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:80804.3-80840.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:80952.3-80988.6" *)
  reg _41_;
  (* src = "libresoc.v:81100.3-81136.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:80286.3-80322.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:81359.3-81395.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:81396.3-81432.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:81433.3-81469.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:80693.3-80729.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:80878.3-80914.6" *)
  reg _48_;
  (* src = "libresoc.v:80915.3-80951.6" *)
  reg _49_;
  (* src = "libresoc.v:81137.3-81173.6" *)
  reg _50_;
  (* src = "libresoc.v:80656.3-80692.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:81211.3-81247.6" *)
  reg _52_;
  (* src = "libresoc.v:81470.3-81506.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:80767.3-80803.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:81063.3-81099.6" *)
  reg _55_;
  (* src = "libresoc.v:81248.3-81284.6" *)
  reg _56_;
  (* src = "libresoc.v:81174.3-81210.6" *)
  reg _57_;
  (* src = "libresoc.v:81026.3-81062.6" *)
  reg _58_;
  (* src = "libresoc.v:80582.3-80618.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:80619.3-80655.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:80397.3-80433.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:80434.3-80470.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:80471.3-80507.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:80545.3-80581.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:80508.3-80544.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:80730.3-80766.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_SV_Etype;
  reg [1:0] dec30_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_SV_Ptype;
  reg [1:0] dec30_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec30_asmcode;
  reg [7:0] dec30_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_br;
  reg dec30_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_cr_in;
  reg [2:0] dec30_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_cr_out;
  reg [2:0] dec30_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_cry_in;
  reg [1:0] dec30_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_cry_out;
  reg dec30_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec30_form;
  reg [4:0] dec30_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec30_function_unit;
  reg [13:0] dec30_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_in1_sel;
  reg [2:0] dec30_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec30_in2_sel;
  reg [3:0] dec30_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_in3_sel;
  reg [1:0] dec30_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec30_internal_op;
  reg [6:0] dec30_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_inv_a;
  reg dec30_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_inv_out;
  reg dec30_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_is_32b;
  reg dec30_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec30_ldst_len;
  reg [3:0] dec30_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_lk;
  reg dec30_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_out_sel;
  reg [2:0] dec30_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_rc_sel;
  reg [1:0] dec30_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_rsrv;
  reg dec30_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_sgl_pipe;
  reg dec30_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_sgn;
  reg dec30_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec30_sgn_ext;
  reg dec30_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_cr_in;
  reg [2:0] dec30_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_cr_out;
  reg [2:0] dec30_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_in1;
  reg [2:0] dec30_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_in2;
  reg [2:0] dec30_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_in3;
  reg [2:0] dec30_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_out;
  reg [2:0] dec30_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec30_sv_out2;
  reg [2:0] dec30_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec30_upd;
  reg [1:0] dec30_upd;
  (* src = "libresoc.v:79938.7-79938.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [3:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:80287.5-80287.29" *)
    casez (\initial )
      /* src = "libresoc.v:80287.9-80287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _43_ = 14'h0008;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec30_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:80324.5-80324.29" *)
    casez (\initial )
      /* src = "libresoc.v:80324.9-80324.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:80361.5-80361.29" *)
    casez (\initial )
      /* src = "libresoc.v:80361.9-80361.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:80398.5-80398.29" *)
    casez (\initial )
      /* src = "libresoc.v:80398.9-80398.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:80435.5-80435.29" *)
    casez (\initial )
      /* src = "libresoc.v:80435.9-80435.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _62_ = 3'h2;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:80472.5-80472.29" *)
    casez (\initial )
      /* src = "libresoc.v:80472.9-80472.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _63_ = 3'h3;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:80509.5-80509.29" *)
    casez (\initial )
      /* src = "libresoc.v:80509.9-80509.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:80546.5-80546.29" *)
    casez (\initial )
      /* src = "libresoc.v:80546.9-80546.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:80583.5-80583.29" *)
    casez (\initial )
      /* src = "libresoc.v:80583.9-80583.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:80620.5-80620.29" *)
    casez (\initial )
      /* src = "libresoc.v:80620.9-80620.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:80657.5-80657.29" *)
    casez (\initial )
      /* src = "libresoc.v:80657.9-80657.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec30_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:80694.5-80694.29" *)
    casez (\initial )
      /* src = "libresoc.v:80694.9-80694.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _47_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _47_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _47_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _47_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _47_ = 7'h3a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _47_ = 7'h3a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _47_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _47_ = 7'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _47_ = 7'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _47_ = 7'h3a;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec30_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:80731.5-80731.29" *)
    casez (\initial )
      /* src = "libresoc.v:80731.9-80731.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:80768.5-80768.29" *)
    casez (\initial )
      /* src = "libresoc.v:80768.9-80768.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:80805.5-80805.29" *)
    casez (\initial )
      /* src = "libresoc.v:80805.9-80805.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:80842.5-80842.29" *)
    casez (\initial )
      /* src = "libresoc.v:80842.9-80842.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _36_ = 8'h94;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _36_ = 8'h94;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _36_ = 8'h95;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _36_ = 8'h95;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _36_ = 8'h96;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _36_ = 8'h96;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _36_ = 8'h97;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _36_ = 8'h97;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _36_ = 8'h92;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _36_ = 8'h93;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec30_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:80879.5-80879.29" *)
    casez (\initial )
      /* src = "libresoc.v:80879.9-80879.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:80916.5-80916.29" *)
    casez (\initial )
      /* src = "libresoc.v:80916.9-80916.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:80953.5-80953.29" *)
    casez (\initial )
      /* src = "libresoc.v:80953.9-80953.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:80990.5-80990.29" *)
    casez (\initial )
      /* src = "libresoc.v:80990.9-80990.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:81027.5-81027.29" *)
    casez (\initial )
      /* src = "libresoc.v:81027.9-81027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:81064.5-81064.29" *)
    casez (\initial )
      /* src = "libresoc.v:81064.9-81064.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:81101.5-81101.29" *)
    casez (\initial )
      /* src = "libresoc.v:81101.9-81101.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _42_ = 5'h15;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _42_ = 5'h15;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _42_ = 5'h14;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _42_ = 5'h14;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec30_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:81138.5-81138.29" *)
    casez (\initial )
      /* src = "libresoc.v:81138.9-81138.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:81175.5-81175.29" *)
    casez (\initial )
      /* src = "libresoc.v:81175.9-81175.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:81212.5-81212.29" *)
    casez (\initial )
      /* src = "libresoc.v:81212.9-81212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:81249.5-81249.29" *)
    casez (\initial )
      /* src = "libresoc.v:81249.9-81249.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec30_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:81286.5-81286.29" *)
    casez (\initial )
      /* src = "libresoc.v:81286.9-81286.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:81323.5-81323.29" *)
    casez (\initial )
      /* src = "libresoc.v:81323.9-81323.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:81360.5-81360.29" *)
    casez (\initial )
      /* src = "libresoc.v:81360.9-81360.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:81397.5-81397.29" *)
    casez (\initial )
      /* src = "libresoc.v:81397.9-81397.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec30_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:81434.5-81434.29" *)
    casez (\initial )
      /* src = "libresoc.v:81434.9-81434.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec30_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:81471.5-81471.29" *)
    casez (\initial )
      /* src = "libresoc.v:81471.9-81471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h0:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _53_ = 3'h2;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec30_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[4:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:81512.1-90160.10" *)
module dec31(dec31_function_unit, dec31_internal_op, dec31_form, dec31_asmcode, dec31_SV_Etype, dec31_SV_Ptype, dec31_in1_sel, dec31_in2_sel, dec31_in3_sel, dec31_out_sel, dec31_cr_in, dec31_cr_out, dec31_sv_in1, dec31_sv_in2, dec31_sv_in3, dec31_sv_out, dec31_sv_out2, dec31_sv_cr_in, dec31_sv_cr_out, dec31_ldst_len, dec31_upd, dec31_rc_sel, dec31_cry_in, dec31_inv_a, dec31_inv_out, dec31_cry_out, dec31_br, dec31_sgn_ext, dec31_rsrv, dec31_is_32b, dec31_sgn, dec31_lk, dec31_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:88371.3-88431.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:88432.3-88492.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:88310.3-88370.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:89713.3-89773.6" *)
  reg _03_;
  (* src = "libresoc.v:88737.3-88797.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:88798.3-88858.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:89469.3-89529.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:89652.3-89712.6" *)
  reg _07_;
  (* src = "libresoc.v:88249.3-88309.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:88127.3-88187.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:88493.3-88553.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:88554.3-88614.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:88615.3-88675.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:88188.3-88248.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:89530.3-89590.6" *)
  reg _14_;
  (* src = "libresoc.v:89591.3-89651.6" *)
  reg _15_;
  (* src = "libresoc.v:89896.3-89956.6" *)
  reg _16_;
  (* src = "libresoc.v:89286.3-89346.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:90018.3-90078.6" *)
  reg _18_;
  (* src = "libresoc.v:88676.3-88736.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:89408.3-89468.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:89835.3-89895.6" *)
  reg _21_;
  (* src = "libresoc.v:90079.3-90139.6" *)
  reg _22_;
  (* src = "libresoc.v:89957.3-90017.6" *)
  reg _23_;
  (* src = "libresoc.v:89774.3-89834.6" *)
  reg _24_;
  (* src = "libresoc.v:89164.3-89224.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:89225.3-89285.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:88859.3-88919.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:88920.3-88980.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:88981.3-89041.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:89103.3-89163.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:89042.3-89102.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:89347.3-89407.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:81513.7-81513.20" *)
  reg _33_;
  (* src = "libresoc.v:88371.3-88431.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:88432.3-88492.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:88310.3-88370.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:89713.3-89773.6" *)
  reg _37_;
  (* src = "libresoc.v:88737.3-88797.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:88798.3-88858.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:89469.3-89529.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:89652.3-89712.6" *)
  reg _41_;
  (* src = "libresoc.v:88249.3-88309.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:88127.3-88187.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:88493.3-88553.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:88554.3-88614.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:88615.3-88675.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:88188.3-88248.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:89530.3-89590.6" *)
  reg _48_;
  (* src = "libresoc.v:89591.3-89651.6" *)
  reg _49_;
  (* src = "libresoc.v:89896.3-89956.6" *)
  reg _50_;
  (* src = "libresoc.v:89286.3-89346.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:90018.3-90078.6" *)
  reg _52_;
  (* src = "libresoc.v:88676.3-88736.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:89408.3-89468.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:89835.3-89895.6" *)
  reg _55_;
  (* src = "libresoc.v:90079.3-90139.6" *)
  reg _56_;
  (* src = "libresoc.v:89957.3-90017.6" *)
  reg _57_;
  (* src = "libresoc.v:89774.3-89834.6" *)
  reg _58_;
  (* src = "libresoc.v:89164.3-89224.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:89225.3-89285.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:88859.3-88919.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:88920.3-88980.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:88981.3-89041.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:89103.3-89163.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:89042.3-89102.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:89347.3-89407.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_SV_Etype;
  reg [1:0] dec31_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_SV_Ptype;
  reg [1:0] dec31_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_asmcode;
  reg [7:0] dec31_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_br;
  reg dec31_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_cr_in;
  reg [2:0] dec31_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_cr_out;
  reg [2:0] dec31_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_cry_in;
  reg [1:0] dec31_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_cry_out;
  reg dec31_cry_out;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub0_dec31_dec_sub0_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub0_dec31_dec_sub0_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub0_dec31_dec_sub0_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub0_dec31_dec_sub0_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub0_dec31_dec_sub0_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub0_dec31_dec_sub0_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub0_dec31_dec_sub0_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub0_dec31_dec_sub0_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub0_dec31_dec_sub0_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub0_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub10_dec31_dec_sub10_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub10_dec31_dec_sub10_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub10_dec31_dec_sub10_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub10_dec31_dec_sub10_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub10_dec31_dec_sub10_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub10_dec31_dec_sub10_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub10_dec31_dec_sub10_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub10_dec31_dec_sub10_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub10_dec31_dec_sub10_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub10_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub11_dec31_dec_sub11_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub11_dec31_dec_sub11_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub11_dec31_dec_sub11_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub11_dec31_dec_sub11_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub11_dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub11_dec31_dec_sub11_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub11_dec31_dec_sub11_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub11_dec31_dec_sub11_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub11_dec31_dec_sub11_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub11_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub15_dec31_dec_sub15_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub15_dec31_dec_sub15_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub15_dec31_dec_sub15_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub15_dec31_dec_sub15_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub15_dec31_dec_sub15_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub15_dec31_dec_sub15_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub15_dec31_dec_sub15_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub15_dec31_dec_sub15_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub15_dec31_dec_sub15_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub15_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub16_dec31_dec_sub16_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub16_dec31_dec_sub16_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub16_dec31_dec_sub16_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub16_dec31_dec_sub16_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub16_dec31_dec_sub16_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub16_dec31_dec_sub16_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub16_dec31_dec_sub16_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub16_dec31_dec_sub16_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub16_dec31_dec_sub16_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub16_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub18_dec31_dec_sub18_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub18_dec31_dec_sub18_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub18_dec31_dec_sub18_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub18_dec31_dec_sub18_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub18_dec31_dec_sub18_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub18_dec31_dec_sub18_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub18_dec31_dec_sub18_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub18_dec31_dec_sub18_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub18_dec31_dec_sub18_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub18_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub19_dec31_dec_sub19_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub19_dec31_dec_sub19_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub19_dec31_dec_sub19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub19_dec31_dec_sub19_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub19_dec31_dec_sub19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub19_dec31_dec_sub19_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub19_dec31_dec_sub19_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub19_dec31_dec_sub19_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub19_dec31_dec_sub19_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub19_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub20_dec31_dec_sub20_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub20_dec31_dec_sub20_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub20_dec31_dec_sub20_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub20_dec31_dec_sub20_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub20_dec31_dec_sub20_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub20_dec31_dec_sub20_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub20_dec31_dec_sub20_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub20_dec31_dec_sub20_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub20_dec31_dec_sub20_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub20_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub21_dec31_dec_sub21_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub21_dec31_dec_sub21_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub21_dec31_dec_sub21_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub21_dec31_dec_sub21_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub21_dec31_dec_sub21_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub21_dec31_dec_sub21_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub21_dec31_dec_sub21_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub21_dec31_dec_sub21_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub21_dec31_dec_sub21_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub21_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub22_dec31_dec_sub22_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub22_dec31_dec_sub22_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub22_dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub22_dec31_dec_sub22_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub22_dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub22_dec31_dec_sub22_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub22_dec31_dec_sub22_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub22_dec31_dec_sub22_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub22_dec31_dec_sub22_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub22_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub23_dec31_dec_sub23_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub23_dec31_dec_sub23_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub23_dec31_dec_sub23_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub23_dec31_dec_sub23_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub23_dec31_dec_sub23_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub23_dec31_dec_sub23_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub23_dec31_dec_sub23_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub23_dec31_dec_sub23_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub23_dec31_dec_sub23_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub23_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub24_dec31_dec_sub24_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub24_dec31_dec_sub24_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub24_dec31_dec_sub24_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub24_dec31_dec_sub24_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub24_dec31_dec_sub24_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub24_dec31_dec_sub24_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub24_dec31_dec_sub24_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub24_dec31_dec_sub24_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub24_dec31_dec_sub24_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub24_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub26_dec31_dec_sub26_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub26_dec31_dec_sub26_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub26_dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub26_dec31_dec_sub26_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub26_dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub26_dec31_dec_sub26_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub26_dec31_dec_sub26_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub26_dec31_dec_sub26_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub26_dec31_dec_sub26_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub26_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub27_dec31_dec_sub27_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub27_dec31_dec_sub27_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub27_dec31_dec_sub27_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub27_dec31_dec_sub27_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub27_dec31_dec_sub27_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub27_dec31_dec_sub27_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub27_dec31_dec_sub27_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub27_dec31_dec_sub27_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub27_dec31_dec_sub27_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub27_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub28_dec31_dec_sub28_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub28_dec31_dec_sub28_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub28_dec31_dec_sub28_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub28_dec31_dec_sub28_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub28_dec31_dec_sub28_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub28_dec31_dec_sub28_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub28_dec31_dec_sub28_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub28_dec31_dec_sub28_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub28_dec31_dec_sub28_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub28_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub4_dec31_dec_sub4_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub4_dec31_dec_sub4_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub4_dec31_dec_sub4_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub4_dec31_dec_sub4_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub4_dec31_dec_sub4_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub4_dec31_dec_sub4_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub4_dec31_dec_sub4_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub4_dec31_dec_sub4_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub4_dec31_dec_sub4_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub4_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub8_dec31_dec_sub8_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub8_dec31_dec_sub8_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub8_dec31_dec_sub8_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub8_dec31_dec_sub8_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub8_dec31_dec_sub8_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub8_dec31_dec_sub8_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub8_dec31_dec_sub8_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub8_dec31_dec_sub8_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub8_dec31_dec_sub8_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub8_opcode_in;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [7:0] dec31_dec_sub9_dec31_dec_sub9_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [4:0] dec31_dec_sub9_dec31_dec_sub9_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec31_dec_sub9_dec31_dec_sub9_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub9_dec31_dec_sub9_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec31_dec_sub9_dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec31_dec_sub9_dec31_dec_sub9_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec31_dec_sub9_dec31_dec_sub9_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec31_dec_sub9_dec31_dec_sub9_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec31_dec_sub9_dec31_dec_sub9_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec31_dec_sub9_opcode_in;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_form;
  reg [4:0] dec31_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_function_unit;
  reg [13:0] dec31_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_in1_sel;
  reg [2:0] dec31_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_in2_sel;
  reg [3:0] dec31_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_in3_sel;
  reg [1:0] dec31_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_internal_op;
  reg [6:0] dec31_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_inv_a;
  reg dec31_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_inv_out;
  reg dec31_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_is_32b;
  reg dec31_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_ldst_len;
  reg [3:0] dec31_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_lk;
  reg dec31_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_out_sel;
  reg [2:0] dec31_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_rc_sel;
  reg [1:0] dec31_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_rsrv;
  reg dec31_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_sgl_pipe;
  reg dec31_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_sgn;
  reg dec31_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_sgn_ext;
  reg dec31_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_cr_in;
  reg [2:0] dec31_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_cr_out;
  reg [2:0] dec31_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_in1;
  reg [2:0] dec31_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_in2;
  reg [2:0] dec31_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_in3;
  reg [2:0] dec31_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_out;
  reg [2:0] dec31_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_sv_out2;
  reg [2:0] dec31_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_upd;
  reg [1:0] dec31_upd;
  (* src = "libresoc.v:81513.7-81513.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" *)
  wire [4:0] opc_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [9:0] opcode_switch;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87479.18-87514.4" *)
  dec31_dec_sub0 dec31_dec_sub0 (
    .dec31_dec_sub0_SV_Etype(dec31_dec_sub0_dec31_dec_sub0_SV_Etype),
    .dec31_dec_sub0_SV_Ptype(dec31_dec_sub0_dec31_dec_sub0_SV_Ptype),
    .dec31_dec_sub0_asmcode(dec31_dec_sub0_dec31_dec_sub0_asmcode),
    .dec31_dec_sub0_br(dec31_dec_sub0_dec31_dec_sub0_br),
    .dec31_dec_sub0_cr_in(dec31_dec_sub0_dec31_dec_sub0_cr_in),
    .dec31_dec_sub0_cr_out(dec31_dec_sub0_dec31_dec_sub0_cr_out),
    .dec31_dec_sub0_cry_in(dec31_dec_sub0_dec31_dec_sub0_cry_in),
    .dec31_dec_sub0_cry_out(dec31_dec_sub0_dec31_dec_sub0_cry_out),
    .dec31_dec_sub0_form(dec31_dec_sub0_dec31_dec_sub0_form),
    .dec31_dec_sub0_function_unit(dec31_dec_sub0_dec31_dec_sub0_function_unit),
    .dec31_dec_sub0_in1_sel(dec31_dec_sub0_dec31_dec_sub0_in1_sel),
    .dec31_dec_sub0_in2_sel(dec31_dec_sub0_dec31_dec_sub0_in2_sel),
    .dec31_dec_sub0_in3_sel(dec31_dec_sub0_dec31_dec_sub0_in3_sel),
    .dec31_dec_sub0_internal_op(dec31_dec_sub0_dec31_dec_sub0_internal_op),
    .dec31_dec_sub0_inv_a(dec31_dec_sub0_dec31_dec_sub0_inv_a),
    .dec31_dec_sub0_inv_out(dec31_dec_sub0_dec31_dec_sub0_inv_out),
    .dec31_dec_sub0_is_32b(dec31_dec_sub0_dec31_dec_sub0_is_32b),
    .dec31_dec_sub0_ldst_len(dec31_dec_sub0_dec31_dec_sub0_ldst_len),
    .dec31_dec_sub0_lk(dec31_dec_sub0_dec31_dec_sub0_lk),
    .dec31_dec_sub0_out_sel(dec31_dec_sub0_dec31_dec_sub0_out_sel),
    .dec31_dec_sub0_rc_sel(dec31_dec_sub0_dec31_dec_sub0_rc_sel),
    .dec31_dec_sub0_rsrv(dec31_dec_sub0_dec31_dec_sub0_rsrv),
    .dec31_dec_sub0_sgl_pipe(dec31_dec_sub0_dec31_dec_sub0_sgl_pipe),
    .dec31_dec_sub0_sgn(dec31_dec_sub0_dec31_dec_sub0_sgn),
    .dec31_dec_sub0_sgn_ext(dec31_dec_sub0_dec31_dec_sub0_sgn_ext),
    .dec31_dec_sub0_sv_cr_in(dec31_dec_sub0_dec31_dec_sub0_sv_cr_in),
    .dec31_dec_sub0_sv_cr_out(dec31_dec_sub0_dec31_dec_sub0_sv_cr_out),
    .dec31_dec_sub0_sv_in1(dec31_dec_sub0_dec31_dec_sub0_sv_in1),
    .dec31_dec_sub0_sv_in2(dec31_dec_sub0_dec31_dec_sub0_sv_in2),
    .dec31_dec_sub0_sv_in3(dec31_dec_sub0_dec31_dec_sub0_sv_in3),
    .dec31_dec_sub0_sv_out(dec31_dec_sub0_dec31_dec_sub0_sv_out),
    .dec31_dec_sub0_sv_out2(dec31_dec_sub0_dec31_dec_sub0_sv_out2),
    .dec31_dec_sub0_upd(dec31_dec_sub0_dec31_dec_sub0_upd),
    .opcode_in(dec31_dec_sub0_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87515.19-87550.4" *)
  dec31_dec_sub10 dec31_dec_sub10 (
    .dec31_dec_sub10_SV_Etype(dec31_dec_sub10_dec31_dec_sub10_SV_Etype),
    .dec31_dec_sub10_SV_Ptype(dec31_dec_sub10_dec31_dec_sub10_SV_Ptype),
    .dec31_dec_sub10_asmcode(dec31_dec_sub10_dec31_dec_sub10_asmcode),
    .dec31_dec_sub10_br(dec31_dec_sub10_dec31_dec_sub10_br),
    .dec31_dec_sub10_cr_in(dec31_dec_sub10_dec31_dec_sub10_cr_in),
    .dec31_dec_sub10_cr_out(dec31_dec_sub10_dec31_dec_sub10_cr_out),
    .dec31_dec_sub10_cry_in(dec31_dec_sub10_dec31_dec_sub10_cry_in),
    .dec31_dec_sub10_cry_out(dec31_dec_sub10_dec31_dec_sub10_cry_out),
    .dec31_dec_sub10_form(dec31_dec_sub10_dec31_dec_sub10_form),
    .dec31_dec_sub10_function_unit(dec31_dec_sub10_dec31_dec_sub10_function_unit),
    .dec31_dec_sub10_in1_sel(dec31_dec_sub10_dec31_dec_sub10_in1_sel),
    .dec31_dec_sub10_in2_sel(dec31_dec_sub10_dec31_dec_sub10_in2_sel),
    .dec31_dec_sub10_in3_sel(dec31_dec_sub10_dec31_dec_sub10_in3_sel),
    .dec31_dec_sub10_internal_op(dec31_dec_sub10_dec31_dec_sub10_internal_op),
    .dec31_dec_sub10_inv_a(dec31_dec_sub10_dec31_dec_sub10_inv_a),
    .dec31_dec_sub10_inv_out(dec31_dec_sub10_dec31_dec_sub10_inv_out),
    .dec31_dec_sub10_is_32b(dec31_dec_sub10_dec31_dec_sub10_is_32b),
    .dec31_dec_sub10_ldst_len(dec31_dec_sub10_dec31_dec_sub10_ldst_len),
    .dec31_dec_sub10_lk(dec31_dec_sub10_dec31_dec_sub10_lk),
    .dec31_dec_sub10_out_sel(dec31_dec_sub10_dec31_dec_sub10_out_sel),
    .dec31_dec_sub10_rc_sel(dec31_dec_sub10_dec31_dec_sub10_rc_sel),
    .dec31_dec_sub10_rsrv(dec31_dec_sub10_dec31_dec_sub10_rsrv),
    .dec31_dec_sub10_sgl_pipe(dec31_dec_sub10_dec31_dec_sub10_sgl_pipe),
    .dec31_dec_sub10_sgn(dec31_dec_sub10_dec31_dec_sub10_sgn),
    .dec31_dec_sub10_sgn_ext(dec31_dec_sub10_dec31_dec_sub10_sgn_ext),
    .dec31_dec_sub10_sv_cr_in(dec31_dec_sub10_dec31_dec_sub10_sv_cr_in),
    .dec31_dec_sub10_sv_cr_out(dec31_dec_sub10_dec31_dec_sub10_sv_cr_out),
    .dec31_dec_sub10_sv_in1(dec31_dec_sub10_dec31_dec_sub10_sv_in1),
    .dec31_dec_sub10_sv_in2(dec31_dec_sub10_dec31_dec_sub10_sv_in2),
    .dec31_dec_sub10_sv_in3(dec31_dec_sub10_dec31_dec_sub10_sv_in3),
    .dec31_dec_sub10_sv_out(dec31_dec_sub10_dec31_dec_sub10_sv_out),
    .dec31_dec_sub10_sv_out2(dec31_dec_sub10_dec31_dec_sub10_sv_out2),
    .dec31_dec_sub10_upd(dec31_dec_sub10_dec31_dec_sub10_upd),
    .opcode_in(dec31_dec_sub10_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87551.19-87586.4" *)
  dec31_dec_sub11 dec31_dec_sub11 (
    .dec31_dec_sub11_SV_Etype(dec31_dec_sub11_dec31_dec_sub11_SV_Etype),
    .dec31_dec_sub11_SV_Ptype(dec31_dec_sub11_dec31_dec_sub11_SV_Ptype),
    .dec31_dec_sub11_asmcode(dec31_dec_sub11_dec31_dec_sub11_asmcode),
    .dec31_dec_sub11_br(dec31_dec_sub11_dec31_dec_sub11_br),
    .dec31_dec_sub11_cr_in(dec31_dec_sub11_dec31_dec_sub11_cr_in),
    .dec31_dec_sub11_cr_out(dec31_dec_sub11_dec31_dec_sub11_cr_out),
    .dec31_dec_sub11_cry_in(dec31_dec_sub11_dec31_dec_sub11_cry_in),
    .dec31_dec_sub11_cry_out(dec31_dec_sub11_dec31_dec_sub11_cry_out),
    .dec31_dec_sub11_form(dec31_dec_sub11_dec31_dec_sub11_form),
    .dec31_dec_sub11_function_unit(dec31_dec_sub11_dec31_dec_sub11_function_unit),
    .dec31_dec_sub11_in1_sel(dec31_dec_sub11_dec31_dec_sub11_in1_sel),
    .dec31_dec_sub11_in2_sel(dec31_dec_sub11_dec31_dec_sub11_in2_sel),
    .dec31_dec_sub11_in3_sel(dec31_dec_sub11_dec31_dec_sub11_in3_sel),
    .dec31_dec_sub11_internal_op(dec31_dec_sub11_dec31_dec_sub11_internal_op),
    .dec31_dec_sub11_inv_a(dec31_dec_sub11_dec31_dec_sub11_inv_a),
    .dec31_dec_sub11_inv_out(dec31_dec_sub11_dec31_dec_sub11_inv_out),
    .dec31_dec_sub11_is_32b(dec31_dec_sub11_dec31_dec_sub11_is_32b),
    .dec31_dec_sub11_ldst_len(dec31_dec_sub11_dec31_dec_sub11_ldst_len),
    .dec31_dec_sub11_lk(dec31_dec_sub11_dec31_dec_sub11_lk),
    .dec31_dec_sub11_out_sel(dec31_dec_sub11_dec31_dec_sub11_out_sel),
    .dec31_dec_sub11_rc_sel(dec31_dec_sub11_dec31_dec_sub11_rc_sel),
    .dec31_dec_sub11_rsrv(dec31_dec_sub11_dec31_dec_sub11_rsrv),
    .dec31_dec_sub11_sgl_pipe(dec31_dec_sub11_dec31_dec_sub11_sgl_pipe),
    .dec31_dec_sub11_sgn(dec31_dec_sub11_dec31_dec_sub11_sgn),
    .dec31_dec_sub11_sgn_ext(dec31_dec_sub11_dec31_dec_sub11_sgn_ext),
    .dec31_dec_sub11_sv_cr_in(dec31_dec_sub11_dec31_dec_sub11_sv_cr_in),
    .dec31_dec_sub11_sv_cr_out(dec31_dec_sub11_dec31_dec_sub11_sv_cr_out),
    .dec31_dec_sub11_sv_in1(dec31_dec_sub11_dec31_dec_sub11_sv_in1),
    .dec31_dec_sub11_sv_in2(dec31_dec_sub11_dec31_dec_sub11_sv_in2),
    .dec31_dec_sub11_sv_in3(dec31_dec_sub11_dec31_dec_sub11_sv_in3),
    .dec31_dec_sub11_sv_out(dec31_dec_sub11_dec31_dec_sub11_sv_out),
    .dec31_dec_sub11_sv_out2(dec31_dec_sub11_dec31_dec_sub11_sv_out2),
    .dec31_dec_sub11_upd(dec31_dec_sub11_dec31_dec_sub11_upd),
    .opcode_in(dec31_dec_sub11_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87587.19-87622.4" *)
  dec31_dec_sub15 dec31_dec_sub15 (
    .dec31_dec_sub15_SV_Etype(dec31_dec_sub15_dec31_dec_sub15_SV_Etype),
    .dec31_dec_sub15_SV_Ptype(dec31_dec_sub15_dec31_dec_sub15_SV_Ptype),
    .dec31_dec_sub15_asmcode(dec31_dec_sub15_dec31_dec_sub15_asmcode),
    .dec31_dec_sub15_br(dec31_dec_sub15_dec31_dec_sub15_br),
    .dec31_dec_sub15_cr_in(dec31_dec_sub15_dec31_dec_sub15_cr_in),
    .dec31_dec_sub15_cr_out(dec31_dec_sub15_dec31_dec_sub15_cr_out),
    .dec31_dec_sub15_cry_in(dec31_dec_sub15_dec31_dec_sub15_cry_in),
    .dec31_dec_sub15_cry_out(dec31_dec_sub15_dec31_dec_sub15_cry_out),
    .dec31_dec_sub15_form(dec31_dec_sub15_dec31_dec_sub15_form),
    .dec31_dec_sub15_function_unit(dec31_dec_sub15_dec31_dec_sub15_function_unit),
    .dec31_dec_sub15_in1_sel(dec31_dec_sub15_dec31_dec_sub15_in1_sel),
    .dec31_dec_sub15_in2_sel(dec31_dec_sub15_dec31_dec_sub15_in2_sel),
    .dec31_dec_sub15_in3_sel(dec31_dec_sub15_dec31_dec_sub15_in3_sel),
    .dec31_dec_sub15_internal_op(dec31_dec_sub15_dec31_dec_sub15_internal_op),
    .dec31_dec_sub15_inv_a(dec31_dec_sub15_dec31_dec_sub15_inv_a),
    .dec31_dec_sub15_inv_out(dec31_dec_sub15_dec31_dec_sub15_inv_out),
    .dec31_dec_sub15_is_32b(dec31_dec_sub15_dec31_dec_sub15_is_32b),
    .dec31_dec_sub15_ldst_len(dec31_dec_sub15_dec31_dec_sub15_ldst_len),
    .dec31_dec_sub15_lk(dec31_dec_sub15_dec31_dec_sub15_lk),
    .dec31_dec_sub15_out_sel(dec31_dec_sub15_dec31_dec_sub15_out_sel),
    .dec31_dec_sub15_rc_sel(dec31_dec_sub15_dec31_dec_sub15_rc_sel),
    .dec31_dec_sub15_rsrv(dec31_dec_sub15_dec31_dec_sub15_rsrv),
    .dec31_dec_sub15_sgl_pipe(dec31_dec_sub15_dec31_dec_sub15_sgl_pipe),
    .dec31_dec_sub15_sgn(dec31_dec_sub15_dec31_dec_sub15_sgn),
    .dec31_dec_sub15_sgn_ext(dec31_dec_sub15_dec31_dec_sub15_sgn_ext),
    .dec31_dec_sub15_sv_cr_in(dec31_dec_sub15_dec31_dec_sub15_sv_cr_in),
    .dec31_dec_sub15_sv_cr_out(dec31_dec_sub15_dec31_dec_sub15_sv_cr_out),
    .dec31_dec_sub15_sv_in1(dec31_dec_sub15_dec31_dec_sub15_sv_in1),
    .dec31_dec_sub15_sv_in2(dec31_dec_sub15_dec31_dec_sub15_sv_in2),
    .dec31_dec_sub15_sv_in3(dec31_dec_sub15_dec31_dec_sub15_sv_in3),
    .dec31_dec_sub15_sv_out(dec31_dec_sub15_dec31_dec_sub15_sv_out),
    .dec31_dec_sub15_sv_out2(dec31_dec_sub15_dec31_dec_sub15_sv_out2),
    .dec31_dec_sub15_upd(dec31_dec_sub15_dec31_dec_sub15_upd),
    .opcode_in(dec31_dec_sub15_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87623.19-87658.4" *)
  dec31_dec_sub16 dec31_dec_sub16 (
    .dec31_dec_sub16_SV_Etype(dec31_dec_sub16_dec31_dec_sub16_SV_Etype),
    .dec31_dec_sub16_SV_Ptype(dec31_dec_sub16_dec31_dec_sub16_SV_Ptype),
    .dec31_dec_sub16_asmcode(dec31_dec_sub16_dec31_dec_sub16_asmcode),
    .dec31_dec_sub16_br(dec31_dec_sub16_dec31_dec_sub16_br),
    .dec31_dec_sub16_cr_in(dec31_dec_sub16_dec31_dec_sub16_cr_in),
    .dec31_dec_sub16_cr_out(dec31_dec_sub16_dec31_dec_sub16_cr_out),
    .dec31_dec_sub16_cry_in(dec31_dec_sub16_dec31_dec_sub16_cry_in),
    .dec31_dec_sub16_cry_out(dec31_dec_sub16_dec31_dec_sub16_cry_out),
    .dec31_dec_sub16_form(dec31_dec_sub16_dec31_dec_sub16_form),
    .dec31_dec_sub16_function_unit(dec31_dec_sub16_dec31_dec_sub16_function_unit),
    .dec31_dec_sub16_in1_sel(dec31_dec_sub16_dec31_dec_sub16_in1_sel),
    .dec31_dec_sub16_in2_sel(dec31_dec_sub16_dec31_dec_sub16_in2_sel),
    .dec31_dec_sub16_in3_sel(dec31_dec_sub16_dec31_dec_sub16_in3_sel),
    .dec31_dec_sub16_internal_op(dec31_dec_sub16_dec31_dec_sub16_internal_op),
    .dec31_dec_sub16_inv_a(dec31_dec_sub16_dec31_dec_sub16_inv_a),
    .dec31_dec_sub16_inv_out(dec31_dec_sub16_dec31_dec_sub16_inv_out),
    .dec31_dec_sub16_is_32b(dec31_dec_sub16_dec31_dec_sub16_is_32b),
    .dec31_dec_sub16_ldst_len(dec31_dec_sub16_dec31_dec_sub16_ldst_len),
    .dec31_dec_sub16_lk(dec31_dec_sub16_dec31_dec_sub16_lk),
    .dec31_dec_sub16_out_sel(dec31_dec_sub16_dec31_dec_sub16_out_sel),
    .dec31_dec_sub16_rc_sel(dec31_dec_sub16_dec31_dec_sub16_rc_sel),
    .dec31_dec_sub16_rsrv(dec31_dec_sub16_dec31_dec_sub16_rsrv),
    .dec31_dec_sub16_sgl_pipe(dec31_dec_sub16_dec31_dec_sub16_sgl_pipe),
    .dec31_dec_sub16_sgn(dec31_dec_sub16_dec31_dec_sub16_sgn),
    .dec31_dec_sub16_sgn_ext(dec31_dec_sub16_dec31_dec_sub16_sgn_ext),
    .dec31_dec_sub16_sv_cr_in(dec31_dec_sub16_dec31_dec_sub16_sv_cr_in),
    .dec31_dec_sub16_sv_cr_out(dec31_dec_sub16_dec31_dec_sub16_sv_cr_out),
    .dec31_dec_sub16_sv_in1(dec31_dec_sub16_dec31_dec_sub16_sv_in1),
    .dec31_dec_sub16_sv_in2(dec31_dec_sub16_dec31_dec_sub16_sv_in2),
    .dec31_dec_sub16_sv_in3(dec31_dec_sub16_dec31_dec_sub16_sv_in3),
    .dec31_dec_sub16_sv_out(dec31_dec_sub16_dec31_dec_sub16_sv_out),
    .dec31_dec_sub16_sv_out2(dec31_dec_sub16_dec31_dec_sub16_sv_out2),
    .dec31_dec_sub16_upd(dec31_dec_sub16_dec31_dec_sub16_upd),
    .opcode_in(dec31_dec_sub16_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87659.19-87694.4" *)
  dec31_dec_sub18 dec31_dec_sub18 (
    .dec31_dec_sub18_SV_Etype(dec31_dec_sub18_dec31_dec_sub18_SV_Etype),
    .dec31_dec_sub18_SV_Ptype(dec31_dec_sub18_dec31_dec_sub18_SV_Ptype),
    .dec31_dec_sub18_asmcode(dec31_dec_sub18_dec31_dec_sub18_asmcode),
    .dec31_dec_sub18_br(dec31_dec_sub18_dec31_dec_sub18_br),
    .dec31_dec_sub18_cr_in(dec31_dec_sub18_dec31_dec_sub18_cr_in),
    .dec31_dec_sub18_cr_out(dec31_dec_sub18_dec31_dec_sub18_cr_out),
    .dec31_dec_sub18_cry_in(dec31_dec_sub18_dec31_dec_sub18_cry_in),
    .dec31_dec_sub18_cry_out(dec31_dec_sub18_dec31_dec_sub18_cry_out),
    .dec31_dec_sub18_form(dec31_dec_sub18_dec31_dec_sub18_form),
    .dec31_dec_sub18_function_unit(dec31_dec_sub18_dec31_dec_sub18_function_unit),
    .dec31_dec_sub18_in1_sel(dec31_dec_sub18_dec31_dec_sub18_in1_sel),
    .dec31_dec_sub18_in2_sel(dec31_dec_sub18_dec31_dec_sub18_in2_sel),
    .dec31_dec_sub18_in3_sel(dec31_dec_sub18_dec31_dec_sub18_in3_sel),
    .dec31_dec_sub18_internal_op(dec31_dec_sub18_dec31_dec_sub18_internal_op),
    .dec31_dec_sub18_inv_a(dec31_dec_sub18_dec31_dec_sub18_inv_a),
    .dec31_dec_sub18_inv_out(dec31_dec_sub18_dec31_dec_sub18_inv_out),
    .dec31_dec_sub18_is_32b(dec31_dec_sub18_dec31_dec_sub18_is_32b),
    .dec31_dec_sub18_ldst_len(dec31_dec_sub18_dec31_dec_sub18_ldst_len),
    .dec31_dec_sub18_lk(dec31_dec_sub18_dec31_dec_sub18_lk),
    .dec31_dec_sub18_out_sel(dec31_dec_sub18_dec31_dec_sub18_out_sel),
    .dec31_dec_sub18_rc_sel(dec31_dec_sub18_dec31_dec_sub18_rc_sel),
    .dec31_dec_sub18_rsrv(dec31_dec_sub18_dec31_dec_sub18_rsrv),
    .dec31_dec_sub18_sgl_pipe(dec31_dec_sub18_dec31_dec_sub18_sgl_pipe),
    .dec31_dec_sub18_sgn(dec31_dec_sub18_dec31_dec_sub18_sgn),
    .dec31_dec_sub18_sgn_ext(dec31_dec_sub18_dec31_dec_sub18_sgn_ext),
    .dec31_dec_sub18_sv_cr_in(dec31_dec_sub18_dec31_dec_sub18_sv_cr_in),
    .dec31_dec_sub18_sv_cr_out(dec31_dec_sub18_dec31_dec_sub18_sv_cr_out),
    .dec31_dec_sub18_sv_in1(dec31_dec_sub18_dec31_dec_sub18_sv_in1),
    .dec31_dec_sub18_sv_in2(dec31_dec_sub18_dec31_dec_sub18_sv_in2),
    .dec31_dec_sub18_sv_in3(dec31_dec_sub18_dec31_dec_sub18_sv_in3),
    .dec31_dec_sub18_sv_out(dec31_dec_sub18_dec31_dec_sub18_sv_out),
    .dec31_dec_sub18_sv_out2(dec31_dec_sub18_dec31_dec_sub18_sv_out2),
    .dec31_dec_sub18_upd(dec31_dec_sub18_dec31_dec_sub18_upd),
    .opcode_in(dec31_dec_sub18_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87695.19-87730.4" *)
  dec31_dec_sub19 dec31_dec_sub19 (
    .dec31_dec_sub19_SV_Etype(dec31_dec_sub19_dec31_dec_sub19_SV_Etype),
    .dec31_dec_sub19_SV_Ptype(dec31_dec_sub19_dec31_dec_sub19_SV_Ptype),
    .dec31_dec_sub19_asmcode(dec31_dec_sub19_dec31_dec_sub19_asmcode),
    .dec31_dec_sub19_br(dec31_dec_sub19_dec31_dec_sub19_br),
    .dec31_dec_sub19_cr_in(dec31_dec_sub19_dec31_dec_sub19_cr_in),
    .dec31_dec_sub19_cr_out(dec31_dec_sub19_dec31_dec_sub19_cr_out),
    .dec31_dec_sub19_cry_in(dec31_dec_sub19_dec31_dec_sub19_cry_in),
    .dec31_dec_sub19_cry_out(dec31_dec_sub19_dec31_dec_sub19_cry_out),
    .dec31_dec_sub19_form(dec31_dec_sub19_dec31_dec_sub19_form),
    .dec31_dec_sub19_function_unit(dec31_dec_sub19_dec31_dec_sub19_function_unit),
    .dec31_dec_sub19_in1_sel(dec31_dec_sub19_dec31_dec_sub19_in1_sel),
    .dec31_dec_sub19_in2_sel(dec31_dec_sub19_dec31_dec_sub19_in2_sel),
    .dec31_dec_sub19_in3_sel(dec31_dec_sub19_dec31_dec_sub19_in3_sel),
    .dec31_dec_sub19_internal_op(dec31_dec_sub19_dec31_dec_sub19_internal_op),
    .dec31_dec_sub19_inv_a(dec31_dec_sub19_dec31_dec_sub19_inv_a),
    .dec31_dec_sub19_inv_out(dec31_dec_sub19_dec31_dec_sub19_inv_out),
    .dec31_dec_sub19_is_32b(dec31_dec_sub19_dec31_dec_sub19_is_32b),
    .dec31_dec_sub19_ldst_len(dec31_dec_sub19_dec31_dec_sub19_ldst_len),
    .dec31_dec_sub19_lk(dec31_dec_sub19_dec31_dec_sub19_lk),
    .dec31_dec_sub19_out_sel(dec31_dec_sub19_dec31_dec_sub19_out_sel),
    .dec31_dec_sub19_rc_sel(dec31_dec_sub19_dec31_dec_sub19_rc_sel),
    .dec31_dec_sub19_rsrv(dec31_dec_sub19_dec31_dec_sub19_rsrv),
    .dec31_dec_sub19_sgl_pipe(dec31_dec_sub19_dec31_dec_sub19_sgl_pipe),
    .dec31_dec_sub19_sgn(dec31_dec_sub19_dec31_dec_sub19_sgn),
    .dec31_dec_sub19_sgn_ext(dec31_dec_sub19_dec31_dec_sub19_sgn_ext),
    .dec31_dec_sub19_sv_cr_in(dec31_dec_sub19_dec31_dec_sub19_sv_cr_in),
    .dec31_dec_sub19_sv_cr_out(dec31_dec_sub19_dec31_dec_sub19_sv_cr_out),
    .dec31_dec_sub19_sv_in1(dec31_dec_sub19_dec31_dec_sub19_sv_in1),
    .dec31_dec_sub19_sv_in2(dec31_dec_sub19_dec31_dec_sub19_sv_in2),
    .dec31_dec_sub19_sv_in3(dec31_dec_sub19_dec31_dec_sub19_sv_in3),
    .dec31_dec_sub19_sv_out(dec31_dec_sub19_dec31_dec_sub19_sv_out),
    .dec31_dec_sub19_sv_out2(dec31_dec_sub19_dec31_dec_sub19_sv_out2),
    .dec31_dec_sub19_upd(dec31_dec_sub19_dec31_dec_sub19_upd),
    .opcode_in(dec31_dec_sub19_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87731.19-87766.4" *)
  dec31_dec_sub20 dec31_dec_sub20 (
    .dec31_dec_sub20_SV_Etype(dec31_dec_sub20_dec31_dec_sub20_SV_Etype),
    .dec31_dec_sub20_SV_Ptype(dec31_dec_sub20_dec31_dec_sub20_SV_Ptype),
    .dec31_dec_sub20_asmcode(dec31_dec_sub20_dec31_dec_sub20_asmcode),
    .dec31_dec_sub20_br(dec31_dec_sub20_dec31_dec_sub20_br),
    .dec31_dec_sub20_cr_in(dec31_dec_sub20_dec31_dec_sub20_cr_in),
    .dec31_dec_sub20_cr_out(dec31_dec_sub20_dec31_dec_sub20_cr_out),
    .dec31_dec_sub20_cry_in(dec31_dec_sub20_dec31_dec_sub20_cry_in),
    .dec31_dec_sub20_cry_out(dec31_dec_sub20_dec31_dec_sub20_cry_out),
    .dec31_dec_sub20_form(dec31_dec_sub20_dec31_dec_sub20_form),
    .dec31_dec_sub20_function_unit(dec31_dec_sub20_dec31_dec_sub20_function_unit),
    .dec31_dec_sub20_in1_sel(dec31_dec_sub20_dec31_dec_sub20_in1_sel),
    .dec31_dec_sub20_in2_sel(dec31_dec_sub20_dec31_dec_sub20_in2_sel),
    .dec31_dec_sub20_in3_sel(dec31_dec_sub20_dec31_dec_sub20_in3_sel),
    .dec31_dec_sub20_internal_op(dec31_dec_sub20_dec31_dec_sub20_internal_op),
    .dec31_dec_sub20_inv_a(dec31_dec_sub20_dec31_dec_sub20_inv_a),
    .dec31_dec_sub20_inv_out(dec31_dec_sub20_dec31_dec_sub20_inv_out),
    .dec31_dec_sub20_is_32b(dec31_dec_sub20_dec31_dec_sub20_is_32b),
    .dec31_dec_sub20_ldst_len(dec31_dec_sub20_dec31_dec_sub20_ldst_len),
    .dec31_dec_sub20_lk(dec31_dec_sub20_dec31_dec_sub20_lk),
    .dec31_dec_sub20_out_sel(dec31_dec_sub20_dec31_dec_sub20_out_sel),
    .dec31_dec_sub20_rc_sel(dec31_dec_sub20_dec31_dec_sub20_rc_sel),
    .dec31_dec_sub20_rsrv(dec31_dec_sub20_dec31_dec_sub20_rsrv),
    .dec31_dec_sub20_sgl_pipe(dec31_dec_sub20_dec31_dec_sub20_sgl_pipe),
    .dec31_dec_sub20_sgn(dec31_dec_sub20_dec31_dec_sub20_sgn),
    .dec31_dec_sub20_sgn_ext(dec31_dec_sub20_dec31_dec_sub20_sgn_ext),
    .dec31_dec_sub20_sv_cr_in(dec31_dec_sub20_dec31_dec_sub20_sv_cr_in),
    .dec31_dec_sub20_sv_cr_out(dec31_dec_sub20_dec31_dec_sub20_sv_cr_out),
    .dec31_dec_sub20_sv_in1(dec31_dec_sub20_dec31_dec_sub20_sv_in1),
    .dec31_dec_sub20_sv_in2(dec31_dec_sub20_dec31_dec_sub20_sv_in2),
    .dec31_dec_sub20_sv_in3(dec31_dec_sub20_dec31_dec_sub20_sv_in3),
    .dec31_dec_sub20_sv_out(dec31_dec_sub20_dec31_dec_sub20_sv_out),
    .dec31_dec_sub20_sv_out2(dec31_dec_sub20_dec31_dec_sub20_sv_out2),
    .dec31_dec_sub20_upd(dec31_dec_sub20_dec31_dec_sub20_upd),
    .opcode_in(dec31_dec_sub20_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87767.19-87802.4" *)
  dec31_dec_sub21 dec31_dec_sub21 (
    .dec31_dec_sub21_SV_Etype(dec31_dec_sub21_dec31_dec_sub21_SV_Etype),
    .dec31_dec_sub21_SV_Ptype(dec31_dec_sub21_dec31_dec_sub21_SV_Ptype),
    .dec31_dec_sub21_asmcode(dec31_dec_sub21_dec31_dec_sub21_asmcode),
    .dec31_dec_sub21_br(dec31_dec_sub21_dec31_dec_sub21_br),
    .dec31_dec_sub21_cr_in(dec31_dec_sub21_dec31_dec_sub21_cr_in),
    .dec31_dec_sub21_cr_out(dec31_dec_sub21_dec31_dec_sub21_cr_out),
    .dec31_dec_sub21_cry_in(dec31_dec_sub21_dec31_dec_sub21_cry_in),
    .dec31_dec_sub21_cry_out(dec31_dec_sub21_dec31_dec_sub21_cry_out),
    .dec31_dec_sub21_form(dec31_dec_sub21_dec31_dec_sub21_form),
    .dec31_dec_sub21_function_unit(dec31_dec_sub21_dec31_dec_sub21_function_unit),
    .dec31_dec_sub21_in1_sel(dec31_dec_sub21_dec31_dec_sub21_in1_sel),
    .dec31_dec_sub21_in2_sel(dec31_dec_sub21_dec31_dec_sub21_in2_sel),
    .dec31_dec_sub21_in3_sel(dec31_dec_sub21_dec31_dec_sub21_in3_sel),
    .dec31_dec_sub21_internal_op(dec31_dec_sub21_dec31_dec_sub21_internal_op),
    .dec31_dec_sub21_inv_a(dec31_dec_sub21_dec31_dec_sub21_inv_a),
    .dec31_dec_sub21_inv_out(dec31_dec_sub21_dec31_dec_sub21_inv_out),
    .dec31_dec_sub21_is_32b(dec31_dec_sub21_dec31_dec_sub21_is_32b),
    .dec31_dec_sub21_ldst_len(dec31_dec_sub21_dec31_dec_sub21_ldst_len),
    .dec31_dec_sub21_lk(dec31_dec_sub21_dec31_dec_sub21_lk),
    .dec31_dec_sub21_out_sel(dec31_dec_sub21_dec31_dec_sub21_out_sel),
    .dec31_dec_sub21_rc_sel(dec31_dec_sub21_dec31_dec_sub21_rc_sel),
    .dec31_dec_sub21_rsrv(dec31_dec_sub21_dec31_dec_sub21_rsrv),
    .dec31_dec_sub21_sgl_pipe(dec31_dec_sub21_dec31_dec_sub21_sgl_pipe),
    .dec31_dec_sub21_sgn(dec31_dec_sub21_dec31_dec_sub21_sgn),
    .dec31_dec_sub21_sgn_ext(dec31_dec_sub21_dec31_dec_sub21_sgn_ext),
    .dec31_dec_sub21_sv_cr_in(dec31_dec_sub21_dec31_dec_sub21_sv_cr_in),
    .dec31_dec_sub21_sv_cr_out(dec31_dec_sub21_dec31_dec_sub21_sv_cr_out),
    .dec31_dec_sub21_sv_in1(dec31_dec_sub21_dec31_dec_sub21_sv_in1),
    .dec31_dec_sub21_sv_in2(dec31_dec_sub21_dec31_dec_sub21_sv_in2),
    .dec31_dec_sub21_sv_in3(dec31_dec_sub21_dec31_dec_sub21_sv_in3),
    .dec31_dec_sub21_sv_out(dec31_dec_sub21_dec31_dec_sub21_sv_out),
    .dec31_dec_sub21_sv_out2(dec31_dec_sub21_dec31_dec_sub21_sv_out2),
    .dec31_dec_sub21_upd(dec31_dec_sub21_dec31_dec_sub21_upd),
    .opcode_in(dec31_dec_sub21_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87803.19-87838.4" *)
  dec31_dec_sub22 dec31_dec_sub22 (
    .dec31_dec_sub22_SV_Etype(dec31_dec_sub22_dec31_dec_sub22_SV_Etype),
    .dec31_dec_sub22_SV_Ptype(dec31_dec_sub22_dec31_dec_sub22_SV_Ptype),
    .dec31_dec_sub22_asmcode(dec31_dec_sub22_dec31_dec_sub22_asmcode),
    .dec31_dec_sub22_br(dec31_dec_sub22_dec31_dec_sub22_br),
    .dec31_dec_sub22_cr_in(dec31_dec_sub22_dec31_dec_sub22_cr_in),
    .dec31_dec_sub22_cr_out(dec31_dec_sub22_dec31_dec_sub22_cr_out),
    .dec31_dec_sub22_cry_in(dec31_dec_sub22_dec31_dec_sub22_cry_in),
    .dec31_dec_sub22_cry_out(dec31_dec_sub22_dec31_dec_sub22_cry_out),
    .dec31_dec_sub22_form(dec31_dec_sub22_dec31_dec_sub22_form),
    .dec31_dec_sub22_function_unit(dec31_dec_sub22_dec31_dec_sub22_function_unit),
    .dec31_dec_sub22_in1_sel(dec31_dec_sub22_dec31_dec_sub22_in1_sel),
    .dec31_dec_sub22_in2_sel(dec31_dec_sub22_dec31_dec_sub22_in2_sel),
    .dec31_dec_sub22_in3_sel(dec31_dec_sub22_dec31_dec_sub22_in3_sel),
    .dec31_dec_sub22_internal_op(dec31_dec_sub22_dec31_dec_sub22_internal_op),
    .dec31_dec_sub22_inv_a(dec31_dec_sub22_dec31_dec_sub22_inv_a),
    .dec31_dec_sub22_inv_out(dec31_dec_sub22_dec31_dec_sub22_inv_out),
    .dec31_dec_sub22_is_32b(dec31_dec_sub22_dec31_dec_sub22_is_32b),
    .dec31_dec_sub22_ldst_len(dec31_dec_sub22_dec31_dec_sub22_ldst_len),
    .dec31_dec_sub22_lk(dec31_dec_sub22_dec31_dec_sub22_lk),
    .dec31_dec_sub22_out_sel(dec31_dec_sub22_dec31_dec_sub22_out_sel),
    .dec31_dec_sub22_rc_sel(dec31_dec_sub22_dec31_dec_sub22_rc_sel),
    .dec31_dec_sub22_rsrv(dec31_dec_sub22_dec31_dec_sub22_rsrv),
    .dec31_dec_sub22_sgl_pipe(dec31_dec_sub22_dec31_dec_sub22_sgl_pipe),
    .dec31_dec_sub22_sgn(dec31_dec_sub22_dec31_dec_sub22_sgn),
    .dec31_dec_sub22_sgn_ext(dec31_dec_sub22_dec31_dec_sub22_sgn_ext),
    .dec31_dec_sub22_sv_cr_in(dec31_dec_sub22_dec31_dec_sub22_sv_cr_in),
    .dec31_dec_sub22_sv_cr_out(dec31_dec_sub22_dec31_dec_sub22_sv_cr_out),
    .dec31_dec_sub22_sv_in1(dec31_dec_sub22_dec31_dec_sub22_sv_in1),
    .dec31_dec_sub22_sv_in2(dec31_dec_sub22_dec31_dec_sub22_sv_in2),
    .dec31_dec_sub22_sv_in3(dec31_dec_sub22_dec31_dec_sub22_sv_in3),
    .dec31_dec_sub22_sv_out(dec31_dec_sub22_dec31_dec_sub22_sv_out),
    .dec31_dec_sub22_sv_out2(dec31_dec_sub22_dec31_dec_sub22_sv_out2),
    .dec31_dec_sub22_upd(dec31_dec_sub22_dec31_dec_sub22_upd),
    .opcode_in(dec31_dec_sub22_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87839.19-87874.4" *)
  dec31_dec_sub23 dec31_dec_sub23 (
    .dec31_dec_sub23_SV_Etype(dec31_dec_sub23_dec31_dec_sub23_SV_Etype),
    .dec31_dec_sub23_SV_Ptype(dec31_dec_sub23_dec31_dec_sub23_SV_Ptype),
    .dec31_dec_sub23_asmcode(dec31_dec_sub23_dec31_dec_sub23_asmcode),
    .dec31_dec_sub23_br(dec31_dec_sub23_dec31_dec_sub23_br),
    .dec31_dec_sub23_cr_in(dec31_dec_sub23_dec31_dec_sub23_cr_in),
    .dec31_dec_sub23_cr_out(dec31_dec_sub23_dec31_dec_sub23_cr_out),
    .dec31_dec_sub23_cry_in(dec31_dec_sub23_dec31_dec_sub23_cry_in),
    .dec31_dec_sub23_cry_out(dec31_dec_sub23_dec31_dec_sub23_cry_out),
    .dec31_dec_sub23_form(dec31_dec_sub23_dec31_dec_sub23_form),
    .dec31_dec_sub23_function_unit(dec31_dec_sub23_dec31_dec_sub23_function_unit),
    .dec31_dec_sub23_in1_sel(dec31_dec_sub23_dec31_dec_sub23_in1_sel),
    .dec31_dec_sub23_in2_sel(dec31_dec_sub23_dec31_dec_sub23_in2_sel),
    .dec31_dec_sub23_in3_sel(dec31_dec_sub23_dec31_dec_sub23_in3_sel),
    .dec31_dec_sub23_internal_op(dec31_dec_sub23_dec31_dec_sub23_internal_op),
    .dec31_dec_sub23_inv_a(dec31_dec_sub23_dec31_dec_sub23_inv_a),
    .dec31_dec_sub23_inv_out(dec31_dec_sub23_dec31_dec_sub23_inv_out),
    .dec31_dec_sub23_is_32b(dec31_dec_sub23_dec31_dec_sub23_is_32b),
    .dec31_dec_sub23_ldst_len(dec31_dec_sub23_dec31_dec_sub23_ldst_len),
    .dec31_dec_sub23_lk(dec31_dec_sub23_dec31_dec_sub23_lk),
    .dec31_dec_sub23_out_sel(dec31_dec_sub23_dec31_dec_sub23_out_sel),
    .dec31_dec_sub23_rc_sel(dec31_dec_sub23_dec31_dec_sub23_rc_sel),
    .dec31_dec_sub23_rsrv(dec31_dec_sub23_dec31_dec_sub23_rsrv),
    .dec31_dec_sub23_sgl_pipe(dec31_dec_sub23_dec31_dec_sub23_sgl_pipe),
    .dec31_dec_sub23_sgn(dec31_dec_sub23_dec31_dec_sub23_sgn),
    .dec31_dec_sub23_sgn_ext(dec31_dec_sub23_dec31_dec_sub23_sgn_ext),
    .dec31_dec_sub23_sv_cr_in(dec31_dec_sub23_dec31_dec_sub23_sv_cr_in),
    .dec31_dec_sub23_sv_cr_out(dec31_dec_sub23_dec31_dec_sub23_sv_cr_out),
    .dec31_dec_sub23_sv_in1(dec31_dec_sub23_dec31_dec_sub23_sv_in1),
    .dec31_dec_sub23_sv_in2(dec31_dec_sub23_dec31_dec_sub23_sv_in2),
    .dec31_dec_sub23_sv_in3(dec31_dec_sub23_dec31_dec_sub23_sv_in3),
    .dec31_dec_sub23_sv_out(dec31_dec_sub23_dec31_dec_sub23_sv_out),
    .dec31_dec_sub23_sv_out2(dec31_dec_sub23_dec31_dec_sub23_sv_out2),
    .dec31_dec_sub23_upd(dec31_dec_sub23_dec31_dec_sub23_upd),
    .opcode_in(dec31_dec_sub23_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87875.19-87910.4" *)
  dec31_dec_sub24 dec31_dec_sub24 (
    .dec31_dec_sub24_SV_Etype(dec31_dec_sub24_dec31_dec_sub24_SV_Etype),
    .dec31_dec_sub24_SV_Ptype(dec31_dec_sub24_dec31_dec_sub24_SV_Ptype),
    .dec31_dec_sub24_asmcode(dec31_dec_sub24_dec31_dec_sub24_asmcode),
    .dec31_dec_sub24_br(dec31_dec_sub24_dec31_dec_sub24_br),
    .dec31_dec_sub24_cr_in(dec31_dec_sub24_dec31_dec_sub24_cr_in),
    .dec31_dec_sub24_cr_out(dec31_dec_sub24_dec31_dec_sub24_cr_out),
    .dec31_dec_sub24_cry_in(dec31_dec_sub24_dec31_dec_sub24_cry_in),
    .dec31_dec_sub24_cry_out(dec31_dec_sub24_dec31_dec_sub24_cry_out),
    .dec31_dec_sub24_form(dec31_dec_sub24_dec31_dec_sub24_form),
    .dec31_dec_sub24_function_unit(dec31_dec_sub24_dec31_dec_sub24_function_unit),
    .dec31_dec_sub24_in1_sel(dec31_dec_sub24_dec31_dec_sub24_in1_sel),
    .dec31_dec_sub24_in2_sel(dec31_dec_sub24_dec31_dec_sub24_in2_sel),
    .dec31_dec_sub24_in3_sel(dec31_dec_sub24_dec31_dec_sub24_in3_sel),
    .dec31_dec_sub24_internal_op(dec31_dec_sub24_dec31_dec_sub24_internal_op),
    .dec31_dec_sub24_inv_a(dec31_dec_sub24_dec31_dec_sub24_inv_a),
    .dec31_dec_sub24_inv_out(dec31_dec_sub24_dec31_dec_sub24_inv_out),
    .dec31_dec_sub24_is_32b(dec31_dec_sub24_dec31_dec_sub24_is_32b),
    .dec31_dec_sub24_ldst_len(dec31_dec_sub24_dec31_dec_sub24_ldst_len),
    .dec31_dec_sub24_lk(dec31_dec_sub24_dec31_dec_sub24_lk),
    .dec31_dec_sub24_out_sel(dec31_dec_sub24_dec31_dec_sub24_out_sel),
    .dec31_dec_sub24_rc_sel(dec31_dec_sub24_dec31_dec_sub24_rc_sel),
    .dec31_dec_sub24_rsrv(dec31_dec_sub24_dec31_dec_sub24_rsrv),
    .dec31_dec_sub24_sgl_pipe(dec31_dec_sub24_dec31_dec_sub24_sgl_pipe),
    .dec31_dec_sub24_sgn(dec31_dec_sub24_dec31_dec_sub24_sgn),
    .dec31_dec_sub24_sgn_ext(dec31_dec_sub24_dec31_dec_sub24_sgn_ext),
    .dec31_dec_sub24_sv_cr_in(dec31_dec_sub24_dec31_dec_sub24_sv_cr_in),
    .dec31_dec_sub24_sv_cr_out(dec31_dec_sub24_dec31_dec_sub24_sv_cr_out),
    .dec31_dec_sub24_sv_in1(dec31_dec_sub24_dec31_dec_sub24_sv_in1),
    .dec31_dec_sub24_sv_in2(dec31_dec_sub24_dec31_dec_sub24_sv_in2),
    .dec31_dec_sub24_sv_in3(dec31_dec_sub24_dec31_dec_sub24_sv_in3),
    .dec31_dec_sub24_sv_out(dec31_dec_sub24_dec31_dec_sub24_sv_out),
    .dec31_dec_sub24_sv_out2(dec31_dec_sub24_dec31_dec_sub24_sv_out2),
    .dec31_dec_sub24_upd(dec31_dec_sub24_dec31_dec_sub24_upd),
    .opcode_in(dec31_dec_sub24_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87911.19-87946.4" *)
  dec31_dec_sub26 dec31_dec_sub26 (
    .dec31_dec_sub26_SV_Etype(dec31_dec_sub26_dec31_dec_sub26_SV_Etype),
    .dec31_dec_sub26_SV_Ptype(dec31_dec_sub26_dec31_dec_sub26_SV_Ptype),
    .dec31_dec_sub26_asmcode(dec31_dec_sub26_dec31_dec_sub26_asmcode),
    .dec31_dec_sub26_br(dec31_dec_sub26_dec31_dec_sub26_br),
    .dec31_dec_sub26_cr_in(dec31_dec_sub26_dec31_dec_sub26_cr_in),
    .dec31_dec_sub26_cr_out(dec31_dec_sub26_dec31_dec_sub26_cr_out),
    .dec31_dec_sub26_cry_in(dec31_dec_sub26_dec31_dec_sub26_cry_in),
    .dec31_dec_sub26_cry_out(dec31_dec_sub26_dec31_dec_sub26_cry_out),
    .dec31_dec_sub26_form(dec31_dec_sub26_dec31_dec_sub26_form),
    .dec31_dec_sub26_function_unit(dec31_dec_sub26_dec31_dec_sub26_function_unit),
    .dec31_dec_sub26_in1_sel(dec31_dec_sub26_dec31_dec_sub26_in1_sel),
    .dec31_dec_sub26_in2_sel(dec31_dec_sub26_dec31_dec_sub26_in2_sel),
    .dec31_dec_sub26_in3_sel(dec31_dec_sub26_dec31_dec_sub26_in3_sel),
    .dec31_dec_sub26_internal_op(dec31_dec_sub26_dec31_dec_sub26_internal_op),
    .dec31_dec_sub26_inv_a(dec31_dec_sub26_dec31_dec_sub26_inv_a),
    .dec31_dec_sub26_inv_out(dec31_dec_sub26_dec31_dec_sub26_inv_out),
    .dec31_dec_sub26_is_32b(dec31_dec_sub26_dec31_dec_sub26_is_32b),
    .dec31_dec_sub26_ldst_len(dec31_dec_sub26_dec31_dec_sub26_ldst_len),
    .dec31_dec_sub26_lk(dec31_dec_sub26_dec31_dec_sub26_lk),
    .dec31_dec_sub26_out_sel(dec31_dec_sub26_dec31_dec_sub26_out_sel),
    .dec31_dec_sub26_rc_sel(dec31_dec_sub26_dec31_dec_sub26_rc_sel),
    .dec31_dec_sub26_rsrv(dec31_dec_sub26_dec31_dec_sub26_rsrv),
    .dec31_dec_sub26_sgl_pipe(dec31_dec_sub26_dec31_dec_sub26_sgl_pipe),
    .dec31_dec_sub26_sgn(dec31_dec_sub26_dec31_dec_sub26_sgn),
    .dec31_dec_sub26_sgn_ext(dec31_dec_sub26_dec31_dec_sub26_sgn_ext),
    .dec31_dec_sub26_sv_cr_in(dec31_dec_sub26_dec31_dec_sub26_sv_cr_in),
    .dec31_dec_sub26_sv_cr_out(dec31_dec_sub26_dec31_dec_sub26_sv_cr_out),
    .dec31_dec_sub26_sv_in1(dec31_dec_sub26_dec31_dec_sub26_sv_in1),
    .dec31_dec_sub26_sv_in2(dec31_dec_sub26_dec31_dec_sub26_sv_in2),
    .dec31_dec_sub26_sv_in3(dec31_dec_sub26_dec31_dec_sub26_sv_in3),
    .dec31_dec_sub26_sv_out(dec31_dec_sub26_dec31_dec_sub26_sv_out),
    .dec31_dec_sub26_sv_out2(dec31_dec_sub26_dec31_dec_sub26_sv_out2),
    .dec31_dec_sub26_upd(dec31_dec_sub26_dec31_dec_sub26_upd),
    .opcode_in(dec31_dec_sub26_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87947.19-87982.4" *)
  dec31_dec_sub27 dec31_dec_sub27 (
    .dec31_dec_sub27_SV_Etype(dec31_dec_sub27_dec31_dec_sub27_SV_Etype),
    .dec31_dec_sub27_SV_Ptype(dec31_dec_sub27_dec31_dec_sub27_SV_Ptype),
    .dec31_dec_sub27_asmcode(dec31_dec_sub27_dec31_dec_sub27_asmcode),
    .dec31_dec_sub27_br(dec31_dec_sub27_dec31_dec_sub27_br),
    .dec31_dec_sub27_cr_in(dec31_dec_sub27_dec31_dec_sub27_cr_in),
    .dec31_dec_sub27_cr_out(dec31_dec_sub27_dec31_dec_sub27_cr_out),
    .dec31_dec_sub27_cry_in(dec31_dec_sub27_dec31_dec_sub27_cry_in),
    .dec31_dec_sub27_cry_out(dec31_dec_sub27_dec31_dec_sub27_cry_out),
    .dec31_dec_sub27_form(dec31_dec_sub27_dec31_dec_sub27_form),
    .dec31_dec_sub27_function_unit(dec31_dec_sub27_dec31_dec_sub27_function_unit),
    .dec31_dec_sub27_in1_sel(dec31_dec_sub27_dec31_dec_sub27_in1_sel),
    .dec31_dec_sub27_in2_sel(dec31_dec_sub27_dec31_dec_sub27_in2_sel),
    .dec31_dec_sub27_in3_sel(dec31_dec_sub27_dec31_dec_sub27_in3_sel),
    .dec31_dec_sub27_internal_op(dec31_dec_sub27_dec31_dec_sub27_internal_op),
    .dec31_dec_sub27_inv_a(dec31_dec_sub27_dec31_dec_sub27_inv_a),
    .dec31_dec_sub27_inv_out(dec31_dec_sub27_dec31_dec_sub27_inv_out),
    .dec31_dec_sub27_is_32b(dec31_dec_sub27_dec31_dec_sub27_is_32b),
    .dec31_dec_sub27_ldst_len(dec31_dec_sub27_dec31_dec_sub27_ldst_len),
    .dec31_dec_sub27_lk(dec31_dec_sub27_dec31_dec_sub27_lk),
    .dec31_dec_sub27_out_sel(dec31_dec_sub27_dec31_dec_sub27_out_sel),
    .dec31_dec_sub27_rc_sel(dec31_dec_sub27_dec31_dec_sub27_rc_sel),
    .dec31_dec_sub27_rsrv(dec31_dec_sub27_dec31_dec_sub27_rsrv),
    .dec31_dec_sub27_sgl_pipe(dec31_dec_sub27_dec31_dec_sub27_sgl_pipe),
    .dec31_dec_sub27_sgn(dec31_dec_sub27_dec31_dec_sub27_sgn),
    .dec31_dec_sub27_sgn_ext(dec31_dec_sub27_dec31_dec_sub27_sgn_ext),
    .dec31_dec_sub27_sv_cr_in(dec31_dec_sub27_dec31_dec_sub27_sv_cr_in),
    .dec31_dec_sub27_sv_cr_out(dec31_dec_sub27_dec31_dec_sub27_sv_cr_out),
    .dec31_dec_sub27_sv_in1(dec31_dec_sub27_dec31_dec_sub27_sv_in1),
    .dec31_dec_sub27_sv_in2(dec31_dec_sub27_dec31_dec_sub27_sv_in2),
    .dec31_dec_sub27_sv_in3(dec31_dec_sub27_dec31_dec_sub27_sv_in3),
    .dec31_dec_sub27_sv_out(dec31_dec_sub27_dec31_dec_sub27_sv_out),
    .dec31_dec_sub27_sv_out2(dec31_dec_sub27_dec31_dec_sub27_sv_out2),
    .dec31_dec_sub27_upd(dec31_dec_sub27_dec31_dec_sub27_upd),
    .opcode_in(dec31_dec_sub27_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:87983.19-88018.4" *)
  dec31_dec_sub28 dec31_dec_sub28 (
    .dec31_dec_sub28_SV_Etype(dec31_dec_sub28_dec31_dec_sub28_SV_Etype),
    .dec31_dec_sub28_SV_Ptype(dec31_dec_sub28_dec31_dec_sub28_SV_Ptype),
    .dec31_dec_sub28_asmcode(dec31_dec_sub28_dec31_dec_sub28_asmcode),
    .dec31_dec_sub28_br(dec31_dec_sub28_dec31_dec_sub28_br),
    .dec31_dec_sub28_cr_in(dec31_dec_sub28_dec31_dec_sub28_cr_in),
    .dec31_dec_sub28_cr_out(dec31_dec_sub28_dec31_dec_sub28_cr_out),
    .dec31_dec_sub28_cry_in(dec31_dec_sub28_dec31_dec_sub28_cry_in),
    .dec31_dec_sub28_cry_out(dec31_dec_sub28_dec31_dec_sub28_cry_out),
    .dec31_dec_sub28_form(dec31_dec_sub28_dec31_dec_sub28_form),
    .dec31_dec_sub28_function_unit(dec31_dec_sub28_dec31_dec_sub28_function_unit),
    .dec31_dec_sub28_in1_sel(dec31_dec_sub28_dec31_dec_sub28_in1_sel),
    .dec31_dec_sub28_in2_sel(dec31_dec_sub28_dec31_dec_sub28_in2_sel),
    .dec31_dec_sub28_in3_sel(dec31_dec_sub28_dec31_dec_sub28_in3_sel),
    .dec31_dec_sub28_internal_op(dec31_dec_sub28_dec31_dec_sub28_internal_op),
    .dec31_dec_sub28_inv_a(dec31_dec_sub28_dec31_dec_sub28_inv_a),
    .dec31_dec_sub28_inv_out(dec31_dec_sub28_dec31_dec_sub28_inv_out),
    .dec31_dec_sub28_is_32b(dec31_dec_sub28_dec31_dec_sub28_is_32b),
    .dec31_dec_sub28_ldst_len(dec31_dec_sub28_dec31_dec_sub28_ldst_len),
    .dec31_dec_sub28_lk(dec31_dec_sub28_dec31_dec_sub28_lk),
    .dec31_dec_sub28_out_sel(dec31_dec_sub28_dec31_dec_sub28_out_sel),
    .dec31_dec_sub28_rc_sel(dec31_dec_sub28_dec31_dec_sub28_rc_sel),
    .dec31_dec_sub28_rsrv(dec31_dec_sub28_dec31_dec_sub28_rsrv),
    .dec31_dec_sub28_sgl_pipe(dec31_dec_sub28_dec31_dec_sub28_sgl_pipe),
    .dec31_dec_sub28_sgn(dec31_dec_sub28_dec31_dec_sub28_sgn),
    .dec31_dec_sub28_sgn_ext(dec31_dec_sub28_dec31_dec_sub28_sgn_ext),
    .dec31_dec_sub28_sv_cr_in(dec31_dec_sub28_dec31_dec_sub28_sv_cr_in),
    .dec31_dec_sub28_sv_cr_out(dec31_dec_sub28_dec31_dec_sub28_sv_cr_out),
    .dec31_dec_sub28_sv_in1(dec31_dec_sub28_dec31_dec_sub28_sv_in1),
    .dec31_dec_sub28_sv_in2(dec31_dec_sub28_dec31_dec_sub28_sv_in2),
    .dec31_dec_sub28_sv_in3(dec31_dec_sub28_dec31_dec_sub28_sv_in3),
    .dec31_dec_sub28_sv_out(dec31_dec_sub28_dec31_dec_sub28_sv_out),
    .dec31_dec_sub28_sv_out2(dec31_dec_sub28_dec31_dec_sub28_sv_out2),
    .dec31_dec_sub28_upd(dec31_dec_sub28_dec31_dec_sub28_upd),
    .opcode_in(dec31_dec_sub28_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:88019.18-88054.4" *)
  dec31_dec_sub4 dec31_dec_sub4 (
    .dec31_dec_sub4_SV_Etype(dec31_dec_sub4_dec31_dec_sub4_SV_Etype),
    .dec31_dec_sub4_SV_Ptype(dec31_dec_sub4_dec31_dec_sub4_SV_Ptype),
    .dec31_dec_sub4_asmcode(dec31_dec_sub4_dec31_dec_sub4_asmcode),
    .dec31_dec_sub4_br(dec31_dec_sub4_dec31_dec_sub4_br),
    .dec31_dec_sub4_cr_in(dec31_dec_sub4_dec31_dec_sub4_cr_in),
    .dec31_dec_sub4_cr_out(dec31_dec_sub4_dec31_dec_sub4_cr_out),
    .dec31_dec_sub4_cry_in(dec31_dec_sub4_dec31_dec_sub4_cry_in),
    .dec31_dec_sub4_cry_out(dec31_dec_sub4_dec31_dec_sub4_cry_out),
    .dec31_dec_sub4_form(dec31_dec_sub4_dec31_dec_sub4_form),
    .dec31_dec_sub4_function_unit(dec31_dec_sub4_dec31_dec_sub4_function_unit),
    .dec31_dec_sub4_in1_sel(dec31_dec_sub4_dec31_dec_sub4_in1_sel),
    .dec31_dec_sub4_in2_sel(dec31_dec_sub4_dec31_dec_sub4_in2_sel),
    .dec31_dec_sub4_in3_sel(dec31_dec_sub4_dec31_dec_sub4_in3_sel),
    .dec31_dec_sub4_internal_op(dec31_dec_sub4_dec31_dec_sub4_internal_op),
    .dec31_dec_sub4_inv_a(dec31_dec_sub4_dec31_dec_sub4_inv_a),
    .dec31_dec_sub4_inv_out(dec31_dec_sub4_dec31_dec_sub4_inv_out),
    .dec31_dec_sub4_is_32b(dec31_dec_sub4_dec31_dec_sub4_is_32b),
    .dec31_dec_sub4_ldst_len(dec31_dec_sub4_dec31_dec_sub4_ldst_len),
    .dec31_dec_sub4_lk(dec31_dec_sub4_dec31_dec_sub4_lk),
    .dec31_dec_sub4_out_sel(dec31_dec_sub4_dec31_dec_sub4_out_sel),
    .dec31_dec_sub4_rc_sel(dec31_dec_sub4_dec31_dec_sub4_rc_sel),
    .dec31_dec_sub4_rsrv(dec31_dec_sub4_dec31_dec_sub4_rsrv),
    .dec31_dec_sub4_sgl_pipe(dec31_dec_sub4_dec31_dec_sub4_sgl_pipe),
    .dec31_dec_sub4_sgn(dec31_dec_sub4_dec31_dec_sub4_sgn),
    .dec31_dec_sub4_sgn_ext(dec31_dec_sub4_dec31_dec_sub4_sgn_ext),
    .dec31_dec_sub4_sv_cr_in(dec31_dec_sub4_dec31_dec_sub4_sv_cr_in),
    .dec31_dec_sub4_sv_cr_out(dec31_dec_sub4_dec31_dec_sub4_sv_cr_out),
    .dec31_dec_sub4_sv_in1(dec31_dec_sub4_dec31_dec_sub4_sv_in1),
    .dec31_dec_sub4_sv_in2(dec31_dec_sub4_dec31_dec_sub4_sv_in2),
    .dec31_dec_sub4_sv_in3(dec31_dec_sub4_dec31_dec_sub4_sv_in3),
    .dec31_dec_sub4_sv_out(dec31_dec_sub4_dec31_dec_sub4_sv_out),
    .dec31_dec_sub4_sv_out2(dec31_dec_sub4_dec31_dec_sub4_sv_out2),
    .dec31_dec_sub4_upd(dec31_dec_sub4_dec31_dec_sub4_upd),
    .opcode_in(dec31_dec_sub4_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:88055.18-88090.4" *)
  dec31_dec_sub8 dec31_dec_sub8 (
    .dec31_dec_sub8_SV_Etype(dec31_dec_sub8_dec31_dec_sub8_SV_Etype),
    .dec31_dec_sub8_SV_Ptype(dec31_dec_sub8_dec31_dec_sub8_SV_Ptype),
    .dec31_dec_sub8_asmcode(dec31_dec_sub8_dec31_dec_sub8_asmcode),
    .dec31_dec_sub8_br(dec31_dec_sub8_dec31_dec_sub8_br),
    .dec31_dec_sub8_cr_in(dec31_dec_sub8_dec31_dec_sub8_cr_in),
    .dec31_dec_sub8_cr_out(dec31_dec_sub8_dec31_dec_sub8_cr_out),
    .dec31_dec_sub8_cry_in(dec31_dec_sub8_dec31_dec_sub8_cry_in),
    .dec31_dec_sub8_cry_out(dec31_dec_sub8_dec31_dec_sub8_cry_out),
    .dec31_dec_sub8_form(dec31_dec_sub8_dec31_dec_sub8_form),
    .dec31_dec_sub8_function_unit(dec31_dec_sub8_dec31_dec_sub8_function_unit),
    .dec31_dec_sub8_in1_sel(dec31_dec_sub8_dec31_dec_sub8_in1_sel),
    .dec31_dec_sub8_in2_sel(dec31_dec_sub8_dec31_dec_sub8_in2_sel),
    .dec31_dec_sub8_in3_sel(dec31_dec_sub8_dec31_dec_sub8_in3_sel),
    .dec31_dec_sub8_internal_op(dec31_dec_sub8_dec31_dec_sub8_internal_op),
    .dec31_dec_sub8_inv_a(dec31_dec_sub8_dec31_dec_sub8_inv_a),
    .dec31_dec_sub8_inv_out(dec31_dec_sub8_dec31_dec_sub8_inv_out),
    .dec31_dec_sub8_is_32b(dec31_dec_sub8_dec31_dec_sub8_is_32b),
    .dec31_dec_sub8_ldst_len(dec31_dec_sub8_dec31_dec_sub8_ldst_len),
    .dec31_dec_sub8_lk(dec31_dec_sub8_dec31_dec_sub8_lk),
    .dec31_dec_sub8_out_sel(dec31_dec_sub8_dec31_dec_sub8_out_sel),
    .dec31_dec_sub8_rc_sel(dec31_dec_sub8_dec31_dec_sub8_rc_sel),
    .dec31_dec_sub8_rsrv(dec31_dec_sub8_dec31_dec_sub8_rsrv),
    .dec31_dec_sub8_sgl_pipe(dec31_dec_sub8_dec31_dec_sub8_sgl_pipe),
    .dec31_dec_sub8_sgn(dec31_dec_sub8_dec31_dec_sub8_sgn),
    .dec31_dec_sub8_sgn_ext(dec31_dec_sub8_dec31_dec_sub8_sgn_ext),
    .dec31_dec_sub8_sv_cr_in(dec31_dec_sub8_dec31_dec_sub8_sv_cr_in),
    .dec31_dec_sub8_sv_cr_out(dec31_dec_sub8_dec31_dec_sub8_sv_cr_out),
    .dec31_dec_sub8_sv_in1(dec31_dec_sub8_dec31_dec_sub8_sv_in1),
    .dec31_dec_sub8_sv_in2(dec31_dec_sub8_dec31_dec_sub8_sv_in2),
    .dec31_dec_sub8_sv_in3(dec31_dec_sub8_dec31_dec_sub8_sv_in3),
    .dec31_dec_sub8_sv_out(dec31_dec_sub8_dec31_dec_sub8_sv_out),
    .dec31_dec_sub8_sv_out2(dec31_dec_sub8_dec31_dec_sub8_sv_out2),
    .dec31_dec_sub8_upd(dec31_dec_sub8_dec31_dec_sub8_upd),
    .opcode_in(dec31_dec_sub8_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:88091.18-88126.4" *)
  dec31_dec_sub9 dec31_dec_sub9 (
    .dec31_dec_sub9_SV_Etype(dec31_dec_sub9_dec31_dec_sub9_SV_Etype),
    .dec31_dec_sub9_SV_Ptype(dec31_dec_sub9_dec31_dec_sub9_SV_Ptype),
    .dec31_dec_sub9_asmcode(dec31_dec_sub9_dec31_dec_sub9_asmcode),
    .dec31_dec_sub9_br(dec31_dec_sub9_dec31_dec_sub9_br),
    .dec31_dec_sub9_cr_in(dec31_dec_sub9_dec31_dec_sub9_cr_in),
    .dec31_dec_sub9_cr_out(dec31_dec_sub9_dec31_dec_sub9_cr_out),
    .dec31_dec_sub9_cry_in(dec31_dec_sub9_dec31_dec_sub9_cry_in),
    .dec31_dec_sub9_cry_out(dec31_dec_sub9_dec31_dec_sub9_cry_out),
    .dec31_dec_sub9_form(dec31_dec_sub9_dec31_dec_sub9_form),
    .dec31_dec_sub9_function_unit(dec31_dec_sub9_dec31_dec_sub9_function_unit),
    .dec31_dec_sub9_in1_sel(dec31_dec_sub9_dec31_dec_sub9_in1_sel),
    .dec31_dec_sub9_in2_sel(dec31_dec_sub9_dec31_dec_sub9_in2_sel),
    .dec31_dec_sub9_in3_sel(dec31_dec_sub9_dec31_dec_sub9_in3_sel),
    .dec31_dec_sub9_internal_op(dec31_dec_sub9_dec31_dec_sub9_internal_op),
    .dec31_dec_sub9_inv_a(dec31_dec_sub9_dec31_dec_sub9_inv_a),
    .dec31_dec_sub9_inv_out(dec31_dec_sub9_dec31_dec_sub9_inv_out),
    .dec31_dec_sub9_is_32b(dec31_dec_sub9_dec31_dec_sub9_is_32b),
    .dec31_dec_sub9_ldst_len(dec31_dec_sub9_dec31_dec_sub9_ldst_len),
    .dec31_dec_sub9_lk(dec31_dec_sub9_dec31_dec_sub9_lk),
    .dec31_dec_sub9_out_sel(dec31_dec_sub9_dec31_dec_sub9_out_sel),
    .dec31_dec_sub9_rc_sel(dec31_dec_sub9_dec31_dec_sub9_rc_sel),
    .dec31_dec_sub9_rsrv(dec31_dec_sub9_dec31_dec_sub9_rsrv),
    .dec31_dec_sub9_sgl_pipe(dec31_dec_sub9_dec31_dec_sub9_sgl_pipe),
    .dec31_dec_sub9_sgn(dec31_dec_sub9_dec31_dec_sub9_sgn),
    .dec31_dec_sub9_sgn_ext(dec31_dec_sub9_dec31_dec_sub9_sgn_ext),
    .dec31_dec_sub9_sv_cr_in(dec31_dec_sub9_dec31_dec_sub9_sv_cr_in),
    .dec31_dec_sub9_sv_cr_out(dec31_dec_sub9_dec31_dec_sub9_sv_cr_out),
    .dec31_dec_sub9_sv_in1(dec31_dec_sub9_dec31_dec_sub9_sv_in1),
    .dec31_dec_sub9_sv_in2(dec31_dec_sub9_dec31_dec_sub9_sv_in2),
    .dec31_dec_sub9_sv_in3(dec31_dec_sub9_dec31_dec_sub9_sv_in3),
    .dec31_dec_sub9_sv_out(dec31_dec_sub9_dec31_dec_sub9_sv_out),
    .dec31_dec_sub9_sv_out2(dec31_dec_sub9_dec31_dec_sub9_sv_out2),
    .dec31_dec_sub9_upd(dec31_dec_sub9_dec31_dec_sub9_upd),
    .opcode_in(dec31_dec_sub9_opcode_in)
  );
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:88128.5-88128.29" *)
    casez (\initial )
      /* src = "libresoc.v:88128.9-88128.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _43_ = dec31_dec_sub10_dec31_dec_sub10_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = dec31_dec_sub28_dec31_dec_sub28_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = dec31_dec_sub0_dec31_dec_sub0_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _43_ = dec31_dec_sub26_dec31_dec_sub26_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _43_ = dec31_dec_sub19_dec31_dec_sub19_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _43_ = dec31_dec_sub22_dec31_dec_sub22_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _43_ = dec31_dec_sub9_dec31_dec_sub9_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _43_ = dec31_dec_sub11_dec31_dec_sub11_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _43_ = dec31_dec_sub27_dec31_dec_sub27_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = dec31_dec_sub15_dec31_dec_sub15_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = dec31_dec_sub20_dec31_dec_sub20_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _43_ = dec31_dec_sub21_dec31_dec_sub21_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = dec31_dec_sub23_dec31_dec_sub23_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = dec31_dec_sub16_dec31_dec_sub16_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _43_ = dec31_dec_sub18_dec31_dec_sub18_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = dec31_dec_sub8_dec31_dec_sub8_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = dec31_dec_sub24_dec31_dec_sub24_function_unit;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = dec31_dec_sub4_dec31_dec_sub4_function_unit;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:88189.5-88189.29" *)
    casez (\initial )
      /* src = "libresoc.v:88189.9-88189.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _47_ = dec31_dec_sub10_dec31_dec_sub10_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = dec31_dec_sub28_dec31_dec_sub28_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = dec31_dec_sub0_dec31_dec_sub0_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _47_ = dec31_dec_sub26_dec31_dec_sub26_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _47_ = dec31_dec_sub19_dec31_dec_sub19_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _47_ = dec31_dec_sub22_dec31_dec_sub22_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _47_ = dec31_dec_sub9_dec31_dec_sub9_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _47_ = dec31_dec_sub11_dec31_dec_sub11_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _47_ = dec31_dec_sub27_dec31_dec_sub27_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = dec31_dec_sub15_dec31_dec_sub15_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = dec31_dec_sub20_dec31_dec_sub20_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _47_ = dec31_dec_sub21_dec31_dec_sub21_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = dec31_dec_sub23_dec31_dec_sub23_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = dec31_dec_sub16_dec31_dec_sub16_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _47_ = dec31_dec_sub18_dec31_dec_sub18_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = dec31_dec_sub8_dec31_dec_sub8_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = dec31_dec_sub24_dec31_dec_sub24_internal_op;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = dec31_dec_sub4_dec31_dec_sub4_internal_op;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:88250.5-88250.29" *)
    casez (\initial )
      /* src = "libresoc.v:88250.9-88250.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _42_ = dec31_dec_sub10_dec31_dec_sub10_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = dec31_dec_sub28_dec31_dec_sub28_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = dec31_dec_sub0_dec31_dec_sub0_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _42_ = dec31_dec_sub26_dec31_dec_sub26_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _42_ = dec31_dec_sub19_dec31_dec_sub19_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _42_ = dec31_dec_sub22_dec31_dec_sub22_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _42_ = dec31_dec_sub9_dec31_dec_sub9_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _42_ = dec31_dec_sub11_dec31_dec_sub11_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _42_ = dec31_dec_sub27_dec31_dec_sub27_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = dec31_dec_sub15_dec31_dec_sub15_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = dec31_dec_sub20_dec31_dec_sub20_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _42_ = dec31_dec_sub21_dec31_dec_sub21_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = dec31_dec_sub23_dec31_dec_sub23_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = dec31_dec_sub16_dec31_dec_sub16_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _42_ = dec31_dec_sub18_dec31_dec_sub18_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = dec31_dec_sub8_dec31_dec_sub8_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = dec31_dec_sub24_dec31_dec_sub24_form;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = dec31_dec_sub4_dec31_dec_sub4_form;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:88311.5-88311.29" *)
    casez (\initial )
      /* src = "libresoc.v:88311.9-88311.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _36_ = dec31_dec_sub10_dec31_dec_sub10_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = dec31_dec_sub28_dec31_dec_sub28_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = dec31_dec_sub0_dec31_dec_sub0_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _36_ = dec31_dec_sub26_dec31_dec_sub26_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _36_ = dec31_dec_sub19_dec31_dec_sub19_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _36_ = dec31_dec_sub22_dec31_dec_sub22_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _36_ = dec31_dec_sub9_dec31_dec_sub9_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _36_ = dec31_dec_sub11_dec31_dec_sub11_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _36_ = dec31_dec_sub27_dec31_dec_sub27_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = dec31_dec_sub15_dec31_dec_sub15_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = dec31_dec_sub20_dec31_dec_sub20_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _36_ = dec31_dec_sub21_dec31_dec_sub21_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = dec31_dec_sub23_dec31_dec_sub23_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = dec31_dec_sub16_dec31_dec_sub16_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _36_ = dec31_dec_sub18_dec31_dec_sub18_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = dec31_dec_sub8_dec31_dec_sub8_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = dec31_dec_sub24_dec31_dec_sub24_asmcode;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = dec31_dec_sub4_dec31_dec_sub4_asmcode;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:88372.5-88372.29" *)
    casez (\initial )
      /* src = "libresoc.v:88372.9-88372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _34_ = dec31_dec_sub10_dec31_dec_sub10_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = dec31_dec_sub28_dec31_dec_sub28_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = dec31_dec_sub0_dec31_dec_sub0_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _34_ = dec31_dec_sub26_dec31_dec_sub26_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _34_ = dec31_dec_sub19_dec31_dec_sub19_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _34_ = dec31_dec_sub22_dec31_dec_sub22_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _34_ = dec31_dec_sub9_dec31_dec_sub9_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _34_ = dec31_dec_sub11_dec31_dec_sub11_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _34_ = dec31_dec_sub27_dec31_dec_sub27_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = dec31_dec_sub15_dec31_dec_sub15_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = dec31_dec_sub20_dec31_dec_sub20_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _34_ = dec31_dec_sub21_dec31_dec_sub21_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = dec31_dec_sub23_dec31_dec_sub23_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = dec31_dec_sub16_dec31_dec_sub16_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _34_ = dec31_dec_sub18_dec31_dec_sub18_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = dec31_dec_sub8_dec31_dec_sub8_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = dec31_dec_sub24_dec31_dec_sub24_SV_Etype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = dec31_dec_sub4_dec31_dec_sub4_SV_Etype;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:88433.5-88433.29" *)
    casez (\initial )
      /* src = "libresoc.v:88433.9-88433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _35_ = dec31_dec_sub10_dec31_dec_sub10_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = dec31_dec_sub28_dec31_dec_sub28_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = dec31_dec_sub0_dec31_dec_sub0_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _35_ = dec31_dec_sub26_dec31_dec_sub26_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _35_ = dec31_dec_sub19_dec31_dec_sub19_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _35_ = dec31_dec_sub22_dec31_dec_sub22_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _35_ = dec31_dec_sub9_dec31_dec_sub9_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _35_ = dec31_dec_sub11_dec31_dec_sub11_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _35_ = dec31_dec_sub27_dec31_dec_sub27_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = dec31_dec_sub15_dec31_dec_sub15_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = dec31_dec_sub20_dec31_dec_sub20_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _35_ = dec31_dec_sub21_dec31_dec_sub21_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = dec31_dec_sub23_dec31_dec_sub23_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = dec31_dec_sub16_dec31_dec_sub16_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _35_ = dec31_dec_sub18_dec31_dec_sub18_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = dec31_dec_sub8_dec31_dec_sub8_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = dec31_dec_sub24_dec31_dec_sub24_SV_Ptype;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = dec31_dec_sub4_dec31_dec_sub4_SV_Ptype;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:88494.5-88494.29" *)
    casez (\initial )
      /* src = "libresoc.v:88494.9-88494.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _44_ = dec31_dec_sub10_dec31_dec_sub10_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = dec31_dec_sub28_dec31_dec_sub28_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = dec31_dec_sub0_dec31_dec_sub0_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _44_ = dec31_dec_sub26_dec31_dec_sub26_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _44_ = dec31_dec_sub19_dec31_dec_sub19_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _44_ = dec31_dec_sub22_dec31_dec_sub22_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _44_ = dec31_dec_sub9_dec31_dec_sub9_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _44_ = dec31_dec_sub11_dec31_dec_sub11_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _44_ = dec31_dec_sub27_dec31_dec_sub27_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = dec31_dec_sub15_dec31_dec_sub15_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = dec31_dec_sub20_dec31_dec_sub20_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _44_ = dec31_dec_sub21_dec31_dec_sub21_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = dec31_dec_sub23_dec31_dec_sub23_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = dec31_dec_sub16_dec31_dec_sub16_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _44_ = dec31_dec_sub18_dec31_dec_sub18_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = dec31_dec_sub8_dec31_dec_sub8_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = dec31_dec_sub24_dec31_dec_sub24_in1_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = dec31_dec_sub4_dec31_dec_sub4_in1_sel;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:88555.5-88555.29" *)
    casez (\initial )
      /* src = "libresoc.v:88555.9-88555.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _45_ = dec31_dec_sub10_dec31_dec_sub10_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = dec31_dec_sub28_dec31_dec_sub28_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = dec31_dec_sub0_dec31_dec_sub0_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _45_ = dec31_dec_sub26_dec31_dec_sub26_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _45_ = dec31_dec_sub19_dec31_dec_sub19_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _45_ = dec31_dec_sub22_dec31_dec_sub22_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _45_ = dec31_dec_sub9_dec31_dec_sub9_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _45_ = dec31_dec_sub11_dec31_dec_sub11_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _45_ = dec31_dec_sub27_dec31_dec_sub27_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = dec31_dec_sub15_dec31_dec_sub15_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = dec31_dec_sub20_dec31_dec_sub20_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _45_ = dec31_dec_sub21_dec31_dec_sub21_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = dec31_dec_sub23_dec31_dec_sub23_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = dec31_dec_sub16_dec31_dec_sub16_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _45_ = dec31_dec_sub18_dec31_dec_sub18_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = dec31_dec_sub8_dec31_dec_sub8_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = dec31_dec_sub24_dec31_dec_sub24_in2_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = dec31_dec_sub4_dec31_dec_sub4_in2_sel;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:88616.5-88616.29" *)
    casez (\initial )
      /* src = "libresoc.v:88616.9-88616.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _46_ = dec31_dec_sub10_dec31_dec_sub10_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = dec31_dec_sub28_dec31_dec_sub28_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = dec31_dec_sub0_dec31_dec_sub0_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _46_ = dec31_dec_sub26_dec31_dec_sub26_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _46_ = dec31_dec_sub19_dec31_dec_sub19_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _46_ = dec31_dec_sub22_dec31_dec_sub22_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _46_ = dec31_dec_sub9_dec31_dec_sub9_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _46_ = dec31_dec_sub11_dec31_dec_sub11_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _46_ = dec31_dec_sub27_dec31_dec_sub27_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = dec31_dec_sub15_dec31_dec_sub15_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = dec31_dec_sub20_dec31_dec_sub20_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _46_ = dec31_dec_sub21_dec31_dec_sub21_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = dec31_dec_sub23_dec31_dec_sub23_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = dec31_dec_sub16_dec31_dec_sub16_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _46_ = dec31_dec_sub18_dec31_dec_sub18_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = dec31_dec_sub8_dec31_dec_sub8_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = dec31_dec_sub24_dec31_dec_sub24_in3_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = dec31_dec_sub4_dec31_dec_sub4_in3_sel;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:88677.5-88677.29" *)
    casez (\initial )
      /* src = "libresoc.v:88677.9-88677.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _53_ = dec31_dec_sub10_dec31_dec_sub10_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = dec31_dec_sub28_dec31_dec_sub28_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = dec31_dec_sub0_dec31_dec_sub0_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _53_ = dec31_dec_sub26_dec31_dec_sub26_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _53_ = dec31_dec_sub19_dec31_dec_sub19_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _53_ = dec31_dec_sub22_dec31_dec_sub22_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _53_ = dec31_dec_sub9_dec31_dec_sub9_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _53_ = dec31_dec_sub11_dec31_dec_sub11_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _53_ = dec31_dec_sub27_dec31_dec_sub27_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = dec31_dec_sub15_dec31_dec_sub15_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = dec31_dec_sub20_dec31_dec_sub20_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _53_ = dec31_dec_sub21_dec31_dec_sub21_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = dec31_dec_sub23_dec31_dec_sub23_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = dec31_dec_sub16_dec31_dec_sub16_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _53_ = dec31_dec_sub18_dec31_dec_sub18_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = dec31_dec_sub8_dec31_dec_sub8_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = dec31_dec_sub24_dec31_dec_sub24_out_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = dec31_dec_sub4_dec31_dec_sub4_out_sel;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_out_sel <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:88738.5-88738.29" *)
    casez (\initial )
      /* src = "libresoc.v:88738.9-88738.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _38_ = dec31_dec_sub10_dec31_dec_sub10_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = dec31_dec_sub28_dec31_dec_sub28_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = dec31_dec_sub0_dec31_dec_sub0_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _38_ = dec31_dec_sub26_dec31_dec_sub26_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _38_ = dec31_dec_sub19_dec31_dec_sub19_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _38_ = dec31_dec_sub22_dec31_dec_sub22_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _38_ = dec31_dec_sub9_dec31_dec_sub9_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _38_ = dec31_dec_sub11_dec31_dec_sub11_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _38_ = dec31_dec_sub27_dec31_dec_sub27_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = dec31_dec_sub15_dec31_dec_sub15_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = dec31_dec_sub20_dec31_dec_sub20_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _38_ = dec31_dec_sub21_dec31_dec_sub21_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = dec31_dec_sub23_dec31_dec_sub23_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = dec31_dec_sub16_dec31_dec_sub16_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _38_ = dec31_dec_sub18_dec31_dec_sub18_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = dec31_dec_sub8_dec31_dec_sub8_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = dec31_dec_sub24_dec31_dec_sub24_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = dec31_dec_sub4_dec31_dec_sub4_cr_in;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:88799.5-88799.29" *)
    casez (\initial )
      /* src = "libresoc.v:88799.9-88799.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _39_ = dec31_dec_sub10_dec31_dec_sub10_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = dec31_dec_sub28_dec31_dec_sub28_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = dec31_dec_sub0_dec31_dec_sub0_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _39_ = dec31_dec_sub26_dec31_dec_sub26_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _39_ = dec31_dec_sub19_dec31_dec_sub19_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _39_ = dec31_dec_sub22_dec31_dec_sub22_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _39_ = dec31_dec_sub9_dec31_dec_sub9_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _39_ = dec31_dec_sub11_dec31_dec_sub11_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _39_ = dec31_dec_sub27_dec31_dec_sub27_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = dec31_dec_sub15_dec31_dec_sub15_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = dec31_dec_sub20_dec31_dec_sub20_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _39_ = dec31_dec_sub21_dec31_dec_sub21_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = dec31_dec_sub23_dec31_dec_sub23_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = dec31_dec_sub16_dec31_dec_sub16_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _39_ = dec31_dec_sub18_dec31_dec_sub18_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = dec31_dec_sub8_dec31_dec_sub8_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = dec31_dec_sub24_dec31_dec_sub24_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = dec31_dec_sub4_dec31_dec_sub4_cr_out;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:88860.5-88860.29" *)
    casez (\initial )
      /* src = "libresoc.v:88860.9-88860.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _61_ = dec31_dec_sub10_dec31_dec_sub10_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = dec31_dec_sub28_dec31_dec_sub28_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = dec31_dec_sub0_dec31_dec_sub0_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _61_ = dec31_dec_sub26_dec31_dec_sub26_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _61_ = dec31_dec_sub19_dec31_dec_sub19_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _61_ = dec31_dec_sub22_dec31_dec_sub22_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _61_ = dec31_dec_sub9_dec31_dec_sub9_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _61_ = dec31_dec_sub11_dec31_dec_sub11_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _61_ = dec31_dec_sub27_dec31_dec_sub27_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = dec31_dec_sub15_dec31_dec_sub15_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = dec31_dec_sub20_dec31_dec_sub20_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _61_ = dec31_dec_sub21_dec31_dec_sub21_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = dec31_dec_sub23_dec31_dec_sub23_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = dec31_dec_sub16_dec31_dec_sub16_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _61_ = dec31_dec_sub18_dec31_dec_sub18_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = dec31_dec_sub8_dec31_dec_sub8_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = dec31_dec_sub24_dec31_dec_sub24_sv_in1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = dec31_dec_sub4_dec31_dec_sub4_sv_in1;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:88921.5-88921.29" *)
    casez (\initial )
      /* src = "libresoc.v:88921.9-88921.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _62_ = dec31_dec_sub10_dec31_dec_sub10_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = dec31_dec_sub28_dec31_dec_sub28_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = dec31_dec_sub0_dec31_dec_sub0_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _62_ = dec31_dec_sub26_dec31_dec_sub26_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _62_ = dec31_dec_sub19_dec31_dec_sub19_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _62_ = dec31_dec_sub22_dec31_dec_sub22_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _62_ = dec31_dec_sub9_dec31_dec_sub9_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _62_ = dec31_dec_sub11_dec31_dec_sub11_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _62_ = dec31_dec_sub27_dec31_dec_sub27_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = dec31_dec_sub15_dec31_dec_sub15_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = dec31_dec_sub20_dec31_dec_sub20_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _62_ = dec31_dec_sub21_dec31_dec_sub21_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = dec31_dec_sub23_dec31_dec_sub23_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = dec31_dec_sub16_dec31_dec_sub16_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _62_ = dec31_dec_sub18_dec31_dec_sub18_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = dec31_dec_sub8_dec31_dec_sub8_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = dec31_dec_sub24_dec31_dec_sub24_sv_in2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = dec31_dec_sub4_dec31_dec_sub4_sv_in2;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:88982.5-88982.29" *)
    casez (\initial )
      /* src = "libresoc.v:88982.9-88982.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _63_ = dec31_dec_sub10_dec31_dec_sub10_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = dec31_dec_sub28_dec31_dec_sub28_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = dec31_dec_sub0_dec31_dec_sub0_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _63_ = dec31_dec_sub26_dec31_dec_sub26_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _63_ = dec31_dec_sub19_dec31_dec_sub19_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _63_ = dec31_dec_sub22_dec31_dec_sub22_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _63_ = dec31_dec_sub9_dec31_dec_sub9_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _63_ = dec31_dec_sub11_dec31_dec_sub11_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _63_ = dec31_dec_sub27_dec31_dec_sub27_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = dec31_dec_sub15_dec31_dec_sub15_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = dec31_dec_sub20_dec31_dec_sub20_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _63_ = dec31_dec_sub21_dec31_dec_sub21_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = dec31_dec_sub23_dec31_dec_sub23_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = dec31_dec_sub16_dec31_dec_sub16_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _63_ = dec31_dec_sub18_dec31_dec_sub18_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = dec31_dec_sub8_dec31_dec_sub8_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = dec31_dec_sub24_dec31_dec_sub24_sv_in3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = dec31_dec_sub4_dec31_dec_sub4_sv_in3;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:89043.5-89043.29" *)
    casez (\initial )
      /* src = "libresoc.v:89043.9-89043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _65_ = dec31_dec_sub10_dec31_dec_sub10_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = dec31_dec_sub28_dec31_dec_sub28_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = dec31_dec_sub0_dec31_dec_sub0_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _65_ = dec31_dec_sub26_dec31_dec_sub26_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _65_ = dec31_dec_sub19_dec31_dec_sub19_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _65_ = dec31_dec_sub22_dec31_dec_sub22_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _65_ = dec31_dec_sub9_dec31_dec_sub9_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _65_ = dec31_dec_sub11_dec31_dec_sub11_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _65_ = dec31_dec_sub27_dec31_dec_sub27_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = dec31_dec_sub15_dec31_dec_sub15_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = dec31_dec_sub20_dec31_dec_sub20_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _65_ = dec31_dec_sub21_dec31_dec_sub21_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = dec31_dec_sub23_dec31_dec_sub23_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = dec31_dec_sub16_dec31_dec_sub16_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _65_ = dec31_dec_sub18_dec31_dec_sub18_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = dec31_dec_sub8_dec31_dec_sub8_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = dec31_dec_sub24_dec31_dec_sub24_sv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = dec31_dec_sub4_dec31_dec_sub4_sv_out;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:89104.5-89104.29" *)
    casez (\initial )
      /* src = "libresoc.v:89104.9-89104.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _64_ = dec31_dec_sub10_dec31_dec_sub10_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = dec31_dec_sub28_dec31_dec_sub28_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = dec31_dec_sub0_dec31_dec_sub0_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _64_ = dec31_dec_sub26_dec31_dec_sub26_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _64_ = dec31_dec_sub19_dec31_dec_sub19_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _64_ = dec31_dec_sub22_dec31_dec_sub22_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _64_ = dec31_dec_sub9_dec31_dec_sub9_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _64_ = dec31_dec_sub11_dec31_dec_sub11_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _64_ = dec31_dec_sub27_dec31_dec_sub27_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = dec31_dec_sub15_dec31_dec_sub15_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = dec31_dec_sub20_dec31_dec_sub20_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _64_ = dec31_dec_sub21_dec31_dec_sub21_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = dec31_dec_sub23_dec31_dec_sub23_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = dec31_dec_sub16_dec31_dec_sub16_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _64_ = dec31_dec_sub18_dec31_dec_sub18_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = dec31_dec_sub8_dec31_dec_sub8_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = dec31_dec_sub24_dec31_dec_sub24_sv_out2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = dec31_dec_sub4_dec31_dec_sub4_sv_out2;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:89165.5-89165.29" *)
    casez (\initial )
      /* src = "libresoc.v:89165.9-89165.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _59_ = dec31_dec_sub10_dec31_dec_sub10_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = dec31_dec_sub28_dec31_dec_sub28_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = dec31_dec_sub0_dec31_dec_sub0_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _59_ = dec31_dec_sub26_dec31_dec_sub26_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _59_ = dec31_dec_sub19_dec31_dec_sub19_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _59_ = dec31_dec_sub22_dec31_dec_sub22_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _59_ = dec31_dec_sub9_dec31_dec_sub9_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _59_ = dec31_dec_sub11_dec31_dec_sub11_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _59_ = dec31_dec_sub27_dec31_dec_sub27_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = dec31_dec_sub15_dec31_dec_sub15_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = dec31_dec_sub20_dec31_dec_sub20_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _59_ = dec31_dec_sub21_dec31_dec_sub21_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = dec31_dec_sub23_dec31_dec_sub23_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = dec31_dec_sub16_dec31_dec_sub16_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _59_ = dec31_dec_sub18_dec31_dec_sub18_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = dec31_dec_sub8_dec31_dec_sub8_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = dec31_dec_sub24_dec31_dec_sub24_sv_cr_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = dec31_dec_sub4_dec31_dec_sub4_sv_cr_in;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:89226.5-89226.29" *)
    casez (\initial )
      /* src = "libresoc.v:89226.9-89226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _60_ = dec31_dec_sub10_dec31_dec_sub10_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = dec31_dec_sub28_dec31_dec_sub28_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = dec31_dec_sub0_dec31_dec_sub0_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _60_ = dec31_dec_sub26_dec31_dec_sub26_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _60_ = dec31_dec_sub19_dec31_dec_sub19_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _60_ = dec31_dec_sub22_dec31_dec_sub22_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _60_ = dec31_dec_sub9_dec31_dec_sub9_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _60_ = dec31_dec_sub11_dec31_dec_sub11_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _60_ = dec31_dec_sub27_dec31_dec_sub27_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = dec31_dec_sub15_dec31_dec_sub15_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = dec31_dec_sub20_dec31_dec_sub20_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _60_ = dec31_dec_sub21_dec31_dec_sub21_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = dec31_dec_sub23_dec31_dec_sub23_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = dec31_dec_sub16_dec31_dec_sub16_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _60_ = dec31_dec_sub18_dec31_dec_sub18_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = dec31_dec_sub8_dec31_dec_sub8_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = dec31_dec_sub24_dec31_dec_sub24_sv_cr_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = dec31_dec_sub4_dec31_dec_sub4_sv_cr_out;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:89287.5-89287.29" *)
    casez (\initial )
      /* src = "libresoc.v:89287.9-89287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _51_ = dec31_dec_sub10_dec31_dec_sub10_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = dec31_dec_sub28_dec31_dec_sub28_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = dec31_dec_sub0_dec31_dec_sub0_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _51_ = dec31_dec_sub26_dec31_dec_sub26_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _51_ = dec31_dec_sub19_dec31_dec_sub19_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _51_ = dec31_dec_sub22_dec31_dec_sub22_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _51_ = dec31_dec_sub9_dec31_dec_sub9_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _51_ = dec31_dec_sub11_dec31_dec_sub11_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _51_ = dec31_dec_sub27_dec31_dec_sub27_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = dec31_dec_sub15_dec31_dec_sub15_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = dec31_dec_sub20_dec31_dec_sub20_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _51_ = dec31_dec_sub21_dec31_dec_sub21_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = dec31_dec_sub23_dec31_dec_sub23_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = dec31_dec_sub16_dec31_dec_sub16_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _51_ = dec31_dec_sub18_dec31_dec_sub18_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = dec31_dec_sub8_dec31_dec_sub8_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = dec31_dec_sub24_dec31_dec_sub24_ldst_len;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = dec31_dec_sub4_dec31_dec_sub4_ldst_len;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:89348.5-89348.29" *)
    casez (\initial )
      /* src = "libresoc.v:89348.9-89348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _66_ = dec31_dec_sub10_dec31_dec_sub10_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = dec31_dec_sub28_dec31_dec_sub28_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = dec31_dec_sub0_dec31_dec_sub0_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _66_ = dec31_dec_sub26_dec31_dec_sub26_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _66_ = dec31_dec_sub19_dec31_dec_sub19_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _66_ = dec31_dec_sub22_dec31_dec_sub22_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _66_ = dec31_dec_sub9_dec31_dec_sub9_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _66_ = dec31_dec_sub11_dec31_dec_sub11_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _66_ = dec31_dec_sub27_dec31_dec_sub27_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = dec31_dec_sub15_dec31_dec_sub15_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = dec31_dec_sub20_dec31_dec_sub20_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _66_ = dec31_dec_sub21_dec31_dec_sub21_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = dec31_dec_sub23_dec31_dec_sub23_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = dec31_dec_sub16_dec31_dec_sub16_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _66_ = dec31_dec_sub18_dec31_dec_sub18_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = dec31_dec_sub8_dec31_dec_sub8_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = dec31_dec_sub24_dec31_dec_sub24_upd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = dec31_dec_sub4_dec31_dec_sub4_upd;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:89409.5-89409.29" *)
    casez (\initial )
      /* src = "libresoc.v:89409.9-89409.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _54_ = dec31_dec_sub10_dec31_dec_sub10_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = dec31_dec_sub28_dec31_dec_sub28_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = dec31_dec_sub0_dec31_dec_sub0_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _54_ = dec31_dec_sub26_dec31_dec_sub26_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _54_ = dec31_dec_sub19_dec31_dec_sub19_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _54_ = dec31_dec_sub22_dec31_dec_sub22_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _54_ = dec31_dec_sub9_dec31_dec_sub9_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _54_ = dec31_dec_sub11_dec31_dec_sub11_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _54_ = dec31_dec_sub27_dec31_dec_sub27_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = dec31_dec_sub15_dec31_dec_sub15_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = dec31_dec_sub20_dec31_dec_sub20_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _54_ = dec31_dec_sub21_dec31_dec_sub21_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = dec31_dec_sub23_dec31_dec_sub23_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = dec31_dec_sub16_dec31_dec_sub16_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _54_ = dec31_dec_sub18_dec31_dec_sub18_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = dec31_dec_sub8_dec31_dec_sub8_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = dec31_dec_sub24_dec31_dec_sub24_rc_sel;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = dec31_dec_sub4_dec31_dec_sub4_rc_sel;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:89470.5-89470.29" *)
    casez (\initial )
      /* src = "libresoc.v:89470.9-89470.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _40_ = dec31_dec_sub10_dec31_dec_sub10_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = dec31_dec_sub28_dec31_dec_sub28_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = dec31_dec_sub0_dec31_dec_sub0_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _40_ = dec31_dec_sub26_dec31_dec_sub26_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _40_ = dec31_dec_sub19_dec31_dec_sub19_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _40_ = dec31_dec_sub22_dec31_dec_sub22_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _40_ = dec31_dec_sub9_dec31_dec_sub9_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _40_ = dec31_dec_sub11_dec31_dec_sub11_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _40_ = dec31_dec_sub27_dec31_dec_sub27_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = dec31_dec_sub15_dec31_dec_sub15_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = dec31_dec_sub20_dec31_dec_sub20_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _40_ = dec31_dec_sub21_dec31_dec_sub21_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = dec31_dec_sub23_dec31_dec_sub23_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = dec31_dec_sub16_dec31_dec_sub16_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _40_ = dec31_dec_sub18_dec31_dec_sub18_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = dec31_dec_sub8_dec31_dec_sub8_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = dec31_dec_sub24_dec31_dec_sub24_cry_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = dec31_dec_sub4_dec31_dec_sub4_cry_in;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:89531.5-89531.29" *)
    casez (\initial )
      /* src = "libresoc.v:89531.9-89531.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _48_ = dec31_dec_sub10_dec31_dec_sub10_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = dec31_dec_sub28_dec31_dec_sub28_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = dec31_dec_sub0_dec31_dec_sub0_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _48_ = dec31_dec_sub26_dec31_dec_sub26_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _48_ = dec31_dec_sub19_dec31_dec_sub19_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _48_ = dec31_dec_sub22_dec31_dec_sub22_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _48_ = dec31_dec_sub9_dec31_dec_sub9_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _48_ = dec31_dec_sub11_dec31_dec_sub11_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _48_ = dec31_dec_sub27_dec31_dec_sub27_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = dec31_dec_sub15_dec31_dec_sub15_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = dec31_dec_sub20_dec31_dec_sub20_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _48_ = dec31_dec_sub21_dec31_dec_sub21_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = dec31_dec_sub23_dec31_dec_sub23_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = dec31_dec_sub16_dec31_dec_sub16_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _48_ = dec31_dec_sub18_dec31_dec_sub18_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = dec31_dec_sub8_dec31_dec_sub8_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = dec31_dec_sub24_dec31_dec_sub24_inv_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = dec31_dec_sub4_dec31_dec_sub4_inv_a;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:89592.5-89592.29" *)
    casez (\initial )
      /* src = "libresoc.v:89592.9-89592.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _49_ = dec31_dec_sub10_dec31_dec_sub10_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = dec31_dec_sub28_dec31_dec_sub28_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = dec31_dec_sub0_dec31_dec_sub0_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _49_ = dec31_dec_sub26_dec31_dec_sub26_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _49_ = dec31_dec_sub19_dec31_dec_sub19_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _49_ = dec31_dec_sub22_dec31_dec_sub22_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _49_ = dec31_dec_sub9_dec31_dec_sub9_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _49_ = dec31_dec_sub11_dec31_dec_sub11_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _49_ = dec31_dec_sub27_dec31_dec_sub27_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = dec31_dec_sub15_dec31_dec_sub15_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = dec31_dec_sub20_dec31_dec_sub20_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _49_ = dec31_dec_sub21_dec31_dec_sub21_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = dec31_dec_sub23_dec31_dec_sub23_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = dec31_dec_sub16_dec31_dec_sub16_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _49_ = dec31_dec_sub18_dec31_dec_sub18_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = dec31_dec_sub8_dec31_dec_sub8_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = dec31_dec_sub24_dec31_dec_sub24_inv_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = dec31_dec_sub4_dec31_dec_sub4_inv_out;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:89653.5-89653.29" *)
    casez (\initial )
      /* src = "libresoc.v:89653.9-89653.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _41_ = dec31_dec_sub10_dec31_dec_sub10_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = dec31_dec_sub28_dec31_dec_sub28_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = dec31_dec_sub0_dec31_dec_sub0_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _41_ = dec31_dec_sub26_dec31_dec_sub26_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _41_ = dec31_dec_sub19_dec31_dec_sub19_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _41_ = dec31_dec_sub22_dec31_dec_sub22_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _41_ = dec31_dec_sub9_dec31_dec_sub9_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _41_ = dec31_dec_sub11_dec31_dec_sub11_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _41_ = dec31_dec_sub27_dec31_dec_sub27_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = dec31_dec_sub15_dec31_dec_sub15_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = dec31_dec_sub20_dec31_dec_sub20_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _41_ = dec31_dec_sub21_dec31_dec_sub21_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = dec31_dec_sub23_dec31_dec_sub23_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = dec31_dec_sub16_dec31_dec_sub16_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _41_ = dec31_dec_sub18_dec31_dec_sub18_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = dec31_dec_sub8_dec31_dec_sub8_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = dec31_dec_sub24_dec31_dec_sub24_cry_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = dec31_dec_sub4_dec31_dec_sub4_cry_out;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:89714.5-89714.29" *)
    casez (\initial )
      /* src = "libresoc.v:89714.9-89714.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _37_ = dec31_dec_sub10_dec31_dec_sub10_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = dec31_dec_sub28_dec31_dec_sub28_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = dec31_dec_sub0_dec31_dec_sub0_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _37_ = dec31_dec_sub26_dec31_dec_sub26_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _37_ = dec31_dec_sub19_dec31_dec_sub19_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _37_ = dec31_dec_sub22_dec31_dec_sub22_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _37_ = dec31_dec_sub9_dec31_dec_sub9_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _37_ = dec31_dec_sub11_dec31_dec_sub11_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _37_ = dec31_dec_sub27_dec31_dec_sub27_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = dec31_dec_sub15_dec31_dec_sub15_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = dec31_dec_sub20_dec31_dec_sub20_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _37_ = dec31_dec_sub21_dec31_dec_sub21_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = dec31_dec_sub23_dec31_dec_sub23_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = dec31_dec_sub16_dec31_dec_sub16_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _37_ = dec31_dec_sub18_dec31_dec_sub18_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = dec31_dec_sub8_dec31_dec_sub8_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = dec31_dec_sub24_dec31_dec_sub24_br;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = dec31_dec_sub4_dec31_dec_sub4_br;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:89775.5-89775.29" *)
    casez (\initial )
      /* src = "libresoc.v:89775.9-89775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _58_ = dec31_dec_sub10_dec31_dec_sub10_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = dec31_dec_sub28_dec31_dec_sub28_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = dec31_dec_sub0_dec31_dec_sub0_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _58_ = dec31_dec_sub26_dec31_dec_sub26_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _58_ = dec31_dec_sub19_dec31_dec_sub19_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _58_ = dec31_dec_sub22_dec31_dec_sub22_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _58_ = dec31_dec_sub9_dec31_dec_sub9_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _58_ = dec31_dec_sub11_dec31_dec_sub11_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _58_ = dec31_dec_sub27_dec31_dec_sub27_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = dec31_dec_sub15_dec31_dec_sub15_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = dec31_dec_sub20_dec31_dec_sub20_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _58_ = dec31_dec_sub21_dec31_dec_sub21_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = dec31_dec_sub23_dec31_dec_sub23_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = dec31_dec_sub16_dec31_dec_sub16_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _58_ = dec31_dec_sub18_dec31_dec_sub18_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = dec31_dec_sub8_dec31_dec_sub8_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = dec31_dec_sub24_dec31_dec_sub24_sgn_ext;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = dec31_dec_sub4_dec31_dec_sub4_sgn_ext;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:89836.5-89836.29" *)
    casez (\initial )
      /* src = "libresoc.v:89836.9-89836.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _55_ = dec31_dec_sub10_dec31_dec_sub10_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = dec31_dec_sub28_dec31_dec_sub28_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = dec31_dec_sub0_dec31_dec_sub0_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _55_ = dec31_dec_sub26_dec31_dec_sub26_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _55_ = dec31_dec_sub19_dec31_dec_sub19_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _55_ = dec31_dec_sub22_dec31_dec_sub22_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _55_ = dec31_dec_sub9_dec31_dec_sub9_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _55_ = dec31_dec_sub11_dec31_dec_sub11_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _55_ = dec31_dec_sub27_dec31_dec_sub27_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = dec31_dec_sub15_dec31_dec_sub15_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = dec31_dec_sub20_dec31_dec_sub20_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _55_ = dec31_dec_sub21_dec31_dec_sub21_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = dec31_dec_sub23_dec31_dec_sub23_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = dec31_dec_sub16_dec31_dec_sub16_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _55_ = dec31_dec_sub18_dec31_dec_sub18_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = dec31_dec_sub8_dec31_dec_sub8_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = dec31_dec_sub24_dec31_dec_sub24_rsrv;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = dec31_dec_sub4_dec31_dec_sub4_rsrv;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:89897.5-89897.29" *)
    casez (\initial )
      /* src = "libresoc.v:89897.9-89897.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _50_ = dec31_dec_sub10_dec31_dec_sub10_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = dec31_dec_sub28_dec31_dec_sub28_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = dec31_dec_sub0_dec31_dec_sub0_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _50_ = dec31_dec_sub26_dec31_dec_sub26_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _50_ = dec31_dec_sub19_dec31_dec_sub19_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _50_ = dec31_dec_sub22_dec31_dec_sub22_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _50_ = dec31_dec_sub9_dec31_dec_sub9_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _50_ = dec31_dec_sub11_dec31_dec_sub11_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _50_ = dec31_dec_sub27_dec31_dec_sub27_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = dec31_dec_sub15_dec31_dec_sub15_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = dec31_dec_sub20_dec31_dec_sub20_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _50_ = dec31_dec_sub21_dec31_dec_sub21_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = dec31_dec_sub23_dec31_dec_sub23_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = dec31_dec_sub16_dec31_dec_sub16_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _50_ = dec31_dec_sub18_dec31_dec_sub18_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = dec31_dec_sub8_dec31_dec_sub8_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = dec31_dec_sub24_dec31_dec_sub24_is_32b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = dec31_dec_sub4_dec31_dec_sub4_is_32b;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:89958.5-89958.29" *)
    casez (\initial )
      /* src = "libresoc.v:89958.9-89958.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _57_ = dec31_dec_sub10_dec31_dec_sub10_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = dec31_dec_sub28_dec31_dec_sub28_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = dec31_dec_sub0_dec31_dec_sub0_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _57_ = dec31_dec_sub26_dec31_dec_sub26_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _57_ = dec31_dec_sub19_dec31_dec_sub19_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _57_ = dec31_dec_sub22_dec31_dec_sub22_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _57_ = dec31_dec_sub9_dec31_dec_sub9_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _57_ = dec31_dec_sub11_dec31_dec_sub11_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _57_ = dec31_dec_sub27_dec31_dec_sub27_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = dec31_dec_sub15_dec31_dec_sub15_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = dec31_dec_sub20_dec31_dec_sub20_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _57_ = dec31_dec_sub21_dec31_dec_sub21_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = dec31_dec_sub23_dec31_dec_sub23_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = dec31_dec_sub16_dec31_dec_sub16_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _57_ = dec31_dec_sub18_dec31_dec_sub18_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = dec31_dec_sub8_dec31_dec_sub8_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = dec31_dec_sub24_dec31_dec_sub24_sgn;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = dec31_dec_sub4_dec31_dec_sub4_sgn;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:90019.5-90019.29" *)
    casez (\initial )
      /* src = "libresoc.v:90019.9-90019.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _52_ = dec31_dec_sub10_dec31_dec_sub10_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = dec31_dec_sub28_dec31_dec_sub28_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = dec31_dec_sub0_dec31_dec_sub0_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _52_ = dec31_dec_sub26_dec31_dec_sub26_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _52_ = dec31_dec_sub19_dec31_dec_sub19_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _52_ = dec31_dec_sub22_dec31_dec_sub22_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _52_ = dec31_dec_sub9_dec31_dec_sub9_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _52_ = dec31_dec_sub11_dec31_dec_sub11_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _52_ = dec31_dec_sub27_dec31_dec_sub27_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = dec31_dec_sub15_dec31_dec_sub15_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = dec31_dec_sub20_dec31_dec_sub20_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _52_ = dec31_dec_sub21_dec31_dec_sub21_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = dec31_dec_sub23_dec31_dec_sub23_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = dec31_dec_sub16_dec31_dec_sub16_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _52_ = dec31_dec_sub18_dec31_dec_sub18_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = dec31_dec_sub8_dec31_dec_sub8_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = dec31_dec_sub24_dec31_dec_sub24_lk;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = dec31_dec_sub4_dec31_dec_sub4_lk;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:90080.5-90080.29" *)
    casez (\initial )
      /* src = "libresoc.v:90080.9-90080.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opc_in)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _56_ = dec31_dec_sub10_dec31_dec_sub10_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = dec31_dec_sub28_dec31_dec_sub28_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = dec31_dec_sub0_dec31_dec_sub0_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _56_ = dec31_dec_sub26_dec31_dec_sub26_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _56_ = dec31_dec_sub19_dec31_dec_sub19_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _56_ = dec31_dec_sub22_dec31_dec_sub22_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _56_ = dec31_dec_sub9_dec31_dec_sub9_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _56_ = dec31_dec_sub11_dec31_dec_sub11_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _56_ = dec31_dec_sub27_dec31_dec_sub27_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = dec31_dec_sub15_dec31_dec_sub15_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = dec31_dec_sub20_dec31_dec_sub20_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _56_ = dec31_dec_sub21_dec31_dec_sub21_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = dec31_dec_sub23_dec31_dec_sub23_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = dec31_dec_sub16_dec31_dec_sub16_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _56_ = dec31_dec_sub18_dec31_dec_sub18_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = dec31_dec_sub8_dec31_dec_sub8_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = dec31_dec_sub24_dec31_dec_sub24_sgl_pipe;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = dec31_dec_sub4_dec31_dec_sub4_sgl_pipe;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_sgl_pipe <= _22_;
  end
  assign dec31_dec_sub4_opcode_in = opcode_in;
  assign dec31_dec_sub24_opcode_in = opcode_in;
  assign dec31_dec_sub8_opcode_in = opcode_in;
  assign dec31_dec_sub18_opcode_in = opcode_in;
  assign dec31_dec_sub16_opcode_in = opcode_in;
  assign dec31_dec_sub23_opcode_in = opcode_in;
  assign dec31_dec_sub21_opcode_in = opcode_in;
  assign dec31_dec_sub20_opcode_in = opcode_in;
  assign dec31_dec_sub15_opcode_in = opcode_in;
  assign dec31_dec_sub27_opcode_in = opcode_in;
  assign dec31_dec_sub11_opcode_in = opcode_in;
  assign dec31_dec_sub9_opcode_in = opcode_in;
  assign dec31_dec_sub22_opcode_in = opcode_in;
  assign dec31_dec_sub19_opcode_in = opcode_in;
  assign dec31_dec_sub26_opcode_in = opcode_in;
  assign dec31_dec_sub0_opcode_in = opcode_in;
  assign dec31_dec_sub28_opcode_in = opcode_in;
  assign dec31_dec_sub10_opcode_in = opcode_in;
  assign opc_in = opcode_switch[4:0];
  assign opcode_switch = opcode_in[10:1];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:90164.1-91141.10" *)
module dec31_dec_sub0(dec31_dec_sub0_function_unit, dec31_dec_sub0_internal_op, dec31_dec_sub0_form, dec31_dec_sub0_asmcode, dec31_dec_sub0_SV_Etype, dec31_dec_sub0_SV_Ptype, dec31_dec_sub0_in1_sel, dec31_dec_sub0_in2_sel, dec31_dec_sub0_in3_sel, dec31_dec_sub0_out_sel, dec31_dec_sub0_cr_in, dec31_dec_sub0_cr_out, dec31_dec_sub0_sv_in1, dec31_dec_sub0_sv_in2, dec31_dec_sub0_sv_in3, dec31_dec_sub0_sv_out, dec31_dec_sub0_sv_out2, dec31_dec_sub0_sv_cr_in, dec31_dec_sub0_sv_cr_out, dec31_dec_sub0_ldst_len, dec31_dec_sub0_upd, dec31_dec_sub0_rc_sel, dec31_dec_sub0_cry_in, dec31_dec_sub0_inv_a, dec31_dec_sub0_inv_out, dec31_dec_sub0_cry_out, dec31_dec_sub0_br, dec31_dec_sub0_sgn_ext, dec31_dec_sub0_rsrv, dec31_dec_sub0_is_32b, dec31_dec_sub0_sgn, dec31_dec_sub0_lk, dec31_dec_sub0_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:91026.3-91044.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:91045.3-91063.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:90798.3-90816.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:90874.3-90892.6" *)
  reg _03_;
  (* src = "libresoc.v:90532.3-90550.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:90551.3-90569.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:90779.3-90797.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:90855.3-90873.6" *)
  reg _07_;
  (* src = "libresoc.v:90931.3-90949.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:90513.3-90531.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:91064.3-91082.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:91083.3-91101.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:91102.3-91120.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:90722.3-90740.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:90817.3-90835.6" *)
  reg _14_;
  (* src = "libresoc.v:90836.3-90854.6" *)
  reg _15_;
  (* src = "libresoc.v:90950.3-90968.6" *)
  reg _16_;
  (* src = "libresoc.v:90703.3-90721.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:90988.3-91006.6" *)
  reg _18_;
  (* src = "libresoc.v:91121.3-91139.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:90760.3-90778.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:90912.3-90930.6" *)
  reg _21_;
  (* src = "libresoc.v:91007.3-91025.6" *)
  reg _22_;
  (* src = "libresoc.v:90969.3-90987.6" *)
  reg _23_;
  (* src = "libresoc.v:90893.3-90911.6" *)
  reg _24_;
  (* src = "libresoc.v:90665.3-90683.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:90684.3-90702.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:90570.3-90588.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:90589.3-90607.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:90608.3-90626.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:90646.3-90664.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:90627.3-90645.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:90741.3-90759.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:90165.7-90165.20" *)
  reg _33_;
  (* src = "libresoc.v:91026.3-91044.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:91045.3-91063.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:90798.3-90816.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:90874.3-90892.6" *)
  reg _37_;
  (* src = "libresoc.v:90532.3-90550.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:90551.3-90569.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:90779.3-90797.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:90855.3-90873.6" *)
  reg _41_;
  (* src = "libresoc.v:90931.3-90949.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:90513.3-90531.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:91064.3-91082.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:91083.3-91101.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:91102.3-91120.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:90722.3-90740.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:90817.3-90835.6" *)
  reg _48_;
  (* src = "libresoc.v:90836.3-90854.6" *)
  reg _49_;
  (* src = "libresoc.v:90950.3-90968.6" *)
  reg _50_;
  (* src = "libresoc.v:90703.3-90721.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:90988.3-91006.6" *)
  reg _52_;
  (* src = "libresoc.v:91121.3-91139.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:90760.3-90778.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:90912.3-90930.6" *)
  reg _55_;
  (* src = "libresoc.v:91007.3-91025.6" *)
  reg _56_;
  (* src = "libresoc.v:90969.3-90987.6" *)
  reg _57_;
  (* src = "libresoc.v:90893.3-90911.6" *)
  reg _58_;
  (* src = "libresoc.v:90665.3-90683.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:90684.3-90702.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:90570.3-90588.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:90589.3-90607.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:90608.3-90626.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:90646.3-90664.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:90627.3-90645.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:90741.3-90759.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_SV_Etype;
  reg [1:0] dec31_dec_sub0_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_SV_Ptype;
  reg [1:0] dec31_dec_sub0_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub0_asmcode;
  reg [7:0] dec31_dec_sub0_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_br;
  reg dec31_dec_sub0_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_cr_in;
  reg [2:0] dec31_dec_sub0_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_cr_out;
  reg [2:0] dec31_dec_sub0_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_cry_in;
  reg [1:0] dec31_dec_sub0_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_cry_out;
  reg dec31_dec_sub0_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub0_form;
  reg [4:0] dec31_dec_sub0_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub0_function_unit;
  reg [13:0] dec31_dec_sub0_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_in1_sel;
  reg [2:0] dec31_dec_sub0_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub0_in2_sel;
  reg [3:0] dec31_dec_sub0_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_in3_sel;
  reg [1:0] dec31_dec_sub0_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub0_internal_op;
  reg [6:0] dec31_dec_sub0_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_inv_a;
  reg dec31_dec_sub0_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_inv_out;
  reg dec31_dec_sub0_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_is_32b;
  reg dec31_dec_sub0_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub0_ldst_len;
  reg [3:0] dec31_dec_sub0_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_lk;
  reg dec31_dec_sub0_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_out_sel;
  reg [2:0] dec31_dec_sub0_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_rc_sel;
  reg [1:0] dec31_dec_sub0_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_rsrv;
  reg dec31_dec_sub0_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_sgl_pipe;
  reg dec31_dec_sub0_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_sgn;
  reg dec31_dec_sub0_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub0_sgn_ext;
  reg dec31_dec_sub0_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_cr_in;
  reg [2:0] dec31_dec_sub0_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_cr_out;
  reg [2:0] dec31_dec_sub0_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_in1;
  reg [2:0] dec31_dec_sub0_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_in2;
  reg [2:0] dec31_dec_sub0_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_in3;
  reg [2:0] dec31_dec_sub0_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_out;
  reg [2:0] dec31_dec_sub0_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub0_sv_out2;
  reg [2:0] dec31_dec_sub0_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub0_upd;
  reg [1:0] dec31_dec_sub0_upd;
  (* src = "libresoc.v:90165.7-90165.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:90514.5-90514.29" *)
    casez (\initial )
      /* src = "libresoc.v:90514.9-90514.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0040;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub0_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:90533.5-90533.29" *)
    casez (\initial )
      /* src = "libresoc.v:90533.9-90533.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h3;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:90552.5-90552.29" *)
    casez (\initial )
      /* src = "libresoc.v:90552.9-90552.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:90571.5-90571.29" *)
    casez (\initial )
      /* src = "libresoc.v:90571.9-90571.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:90590.5-90590.29" *)
    casez (\initial )
      /* src = "libresoc.v:90590.9-90590.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:90609.5-90609.29" *)
    casez (\initial )
      /* src = "libresoc.v:90609.9-90609.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:90628.5-90628.29" *)
    casez (\initial )
      /* src = "libresoc.v:90628.9-90628.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:90647.5-90647.29" *)
    casez (\initial )
      /* src = "libresoc.v:90647.9-90647.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:90666.5-90666.29" *)
    casez (\initial )
      /* src = "libresoc.v:90666.9-90666.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h2;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:90685.5-90685.29" *)
    casez (\initial )
      /* src = "libresoc.v:90685.9-90685.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:90704.5-90704.29" *)
    casez (\initial )
      /* src = "libresoc.v:90704.9-90704.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:90723.5-90723.29" *)
    casez (\initial )
      /* src = "libresoc.v:90723.9-90723.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h0c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h3b;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub0_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:90742.5-90742.29" *)
    casez (\initial )
      /* src = "libresoc.v:90742.9-90742.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:90761.5-90761.29" *)
    casez (\initial )
      /* src = "libresoc.v:90761.9-90761.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:90780.5-90780.29" *)
    casez (\initial )
      /* src = "libresoc.v:90780.9-90780.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:90799.5-90799.29" *)
    casez (\initial )
      /* src = "libresoc.v:90799.9-90799.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h1a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h1c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h9b;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub0_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:90818.5-90818.29" *)
    casez (\initial )
      /* src = "libresoc.v:90818.9-90818.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:90837.5-90837.29" *)
    casez (\initial )
      /* src = "libresoc.v:90837.9-90837.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:90856.5-90856.29" *)
    casez (\initial )
      /* src = "libresoc.v:90856.9-90856.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:90875.5-90875.29" *)
    casez (\initial )
      /* src = "libresoc.v:90875.9-90875.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:90894.5-90894.29" *)
    casez (\initial )
      /* src = "libresoc.v:90894.9-90894.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:90913.5-90913.29" *)
    casez (\initial )
      /* src = "libresoc.v:90913.9-90913.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:90932.5-90932.29" *)
    casez (\initial )
      /* src = "libresoc.v:90932.9-90932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h18;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub0_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:90951.5-90951.29" *)
    casez (\initial )
      /* src = "libresoc.v:90951.9-90951.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:90970.5-90970.29" *)
    casez (\initial )
      /* src = "libresoc.v:90970.9-90970.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:90989.5-90989.29" *)
    casez (\initial )
      /* src = "libresoc.v:90989.9-90989.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:91008.5-91008.29" *)
    casez (\initial )
      /* src = "libresoc.v:91008.9-91008.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:91027.5-91027.29" *)
    casez (\initial )
      /* src = "libresoc.v:91027.9-91027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:91046.5-91046.29" *)
    casez (\initial )
      /* src = "libresoc.v:91046.9-91046.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:91065.5-91065.29" *)
    casez (\initial )
      /* src = "libresoc.v:91065.9-91065.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:91084.5-91084.29" *)
    casez (\initial )
      /* src = "libresoc.v:91084.9-91084.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:91103.5-91103.29" *)
    casez (\initial )
      /* src = "libresoc.v:91103.9-91103.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:91122.5-91122.29" *)
    casez (\initial )
      /* src = "libresoc.v:91122.9-91122.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub0_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:91145.1-92716.10" *)
module dec31_dec_sub10(dec31_dec_sub10_function_unit, dec31_dec_sub10_internal_op, dec31_dec_sub10_form, dec31_dec_sub10_asmcode, dec31_dec_sub10_SV_Etype, dec31_dec_sub10_SV_Ptype, dec31_dec_sub10_in1_sel, dec31_dec_sub10_in2_sel, dec31_dec_sub10_in3_sel, dec31_dec_sub10_out_sel, dec31_dec_sub10_cr_in, dec31_dec_sub10_cr_out, dec31_dec_sub10_sv_in1, dec31_dec_sub10_sv_in2, dec31_dec_sub10_sv_in3, dec31_dec_sub10_sv_out, dec31_dec_sub10_sv_out2, dec31_dec_sub10_sv_cr_in, dec31_dec_sub10_sv_cr_out, dec31_dec_sub10_ldst_len, dec31_dec_sub10_upd, dec31_dec_sub10_rc_sel, dec31_dec_sub10_cry_in, dec31_dec_sub10_inv_a, dec31_dec_sub10_inv_out, dec31_dec_sub10_cry_out, dec31_dec_sub10_br, dec31_dec_sub10_sgn_ext, dec31_dec_sub10_rsrv, dec31_dec_sub10_is_32b, dec31_dec_sub10_sgn, dec31_dec_sub10_lk, dec31_dec_sub10_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:92493.3-92529.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:92530.3-92566.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:92049.3-92085.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:92197.3-92233.6" *)
  reg _03_;
  (* src = "libresoc.v:91531.3-91567.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:91568.3-91604.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:92012.3-92048.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:92160.3-92196.6" *)
  reg _07_;
  (* src = "libresoc.v:92308.3-92344.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:91494.3-91530.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:92567.3-92603.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:92604.3-92640.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:92641.3-92677.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:91901.3-91937.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:92086.3-92122.6" *)
  reg _14_;
  (* src = "libresoc.v:92123.3-92159.6" *)
  reg _15_;
  (* src = "libresoc.v:92345.3-92381.6" *)
  reg _16_;
  (* src = "libresoc.v:91864.3-91900.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:92419.3-92455.6" *)
  reg _18_;
  (* src = "libresoc.v:92678.3-92714.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:91975.3-92011.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:92271.3-92307.6" *)
  reg _21_;
  (* src = "libresoc.v:92456.3-92492.6" *)
  reg _22_;
  (* src = "libresoc.v:92382.3-92418.6" *)
  reg _23_;
  (* src = "libresoc.v:92234.3-92270.6" *)
  reg _24_;
  (* src = "libresoc.v:91790.3-91826.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:91827.3-91863.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:91605.3-91641.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:91642.3-91678.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:91679.3-91715.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:91753.3-91789.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:91716.3-91752.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:91938.3-91974.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:91146.7-91146.20" *)
  reg _33_;
  (* src = "libresoc.v:92493.3-92529.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:92530.3-92566.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:92049.3-92085.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:92197.3-92233.6" *)
  reg _37_;
  (* src = "libresoc.v:91531.3-91567.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:91568.3-91604.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:92012.3-92048.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:92160.3-92196.6" *)
  reg _41_;
  (* src = "libresoc.v:92308.3-92344.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:91494.3-91530.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:92567.3-92603.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:92604.3-92640.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:92641.3-92677.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:91901.3-91937.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:92086.3-92122.6" *)
  reg _48_;
  (* src = "libresoc.v:92123.3-92159.6" *)
  reg _49_;
  (* src = "libresoc.v:92345.3-92381.6" *)
  reg _50_;
  (* src = "libresoc.v:91864.3-91900.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:92419.3-92455.6" *)
  reg _52_;
  (* src = "libresoc.v:92678.3-92714.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:91975.3-92011.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:92271.3-92307.6" *)
  reg _55_;
  (* src = "libresoc.v:92456.3-92492.6" *)
  reg _56_;
  (* src = "libresoc.v:92382.3-92418.6" *)
  reg _57_;
  (* src = "libresoc.v:92234.3-92270.6" *)
  reg _58_;
  (* src = "libresoc.v:91790.3-91826.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:91827.3-91863.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:91605.3-91641.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:91642.3-91678.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:91679.3-91715.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:91753.3-91789.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:91716.3-91752.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:91938.3-91974.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_SV_Etype;
  reg [1:0] dec31_dec_sub10_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_SV_Ptype;
  reg [1:0] dec31_dec_sub10_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub10_asmcode;
  reg [7:0] dec31_dec_sub10_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_br;
  reg dec31_dec_sub10_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_cr_in;
  reg [2:0] dec31_dec_sub10_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_cr_out;
  reg [2:0] dec31_dec_sub10_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_cry_in;
  reg [1:0] dec31_dec_sub10_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_cry_out;
  reg dec31_dec_sub10_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub10_form;
  reg [4:0] dec31_dec_sub10_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub10_function_unit;
  reg [13:0] dec31_dec_sub10_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_in1_sel;
  reg [2:0] dec31_dec_sub10_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub10_in2_sel;
  reg [3:0] dec31_dec_sub10_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_in3_sel;
  reg [1:0] dec31_dec_sub10_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub10_internal_op;
  reg [6:0] dec31_dec_sub10_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_inv_a;
  reg dec31_dec_sub10_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_inv_out;
  reg dec31_dec_sub10_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_is_32b;
  reg dec31_dec_sub10_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub10_ldst_len;
  reg [3:0] dec31_dec_sub10_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_lk;
  reg dec31_dec_sub10_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_out_sel;
  reg [2:0] dec31_dec_sub10_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_rc_sel;
  reg [1:0] dec31_dec_sub10_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_rsrv;
  reg dec31_dec_sub10_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_sgl_pipe;
  reg dec31_dec_sub10_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_sgn;
  reg dec31_dec_sub10_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub10_sgn_ext;
  reg dec31_dec_sub10_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_cr_in;
  reg [2:0] dec31_dec_sub10_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_cr_out;
  reg [2:0] dec31_dec_sub10_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_in1;
  reg [2:0] dec31_dec_sub10_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_in2;
  reg [2:0] dec31_dec_sub10_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_in3;
  reg [2:0] dec31_dec_sub10_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_out;
  reg [2:0] dec31_dec_sub10_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub10_sv_out2;
  reg [2:0] dec31_dec_sub10_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub10_upd;
  reg [1:0] dec31_dec_sub10_upd;
  (* src = "libresoc.v:91146.7-91146.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:91495.5-91495.29" *)
    casez (\initial )
      /* src = "libresoc.v:91495.9-91495.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _43_ = 14'h0002;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub10_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:91532.5-91532.29" *)
    casez (\initial )
      /* src = "libresoc.v:91532.9-91532.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:91569.5-91569.29" *)
    casez (\initial )
      /* src = "libresoc.v:91569.9-91569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:91606.5-91606.29" *)
    casez (\initial )
      /* src = "libresoc.v:91606.9-91606.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:91643.5-91643.29" *)
    casez (\initial )
      /* src = "libresoc.v:91643.9-91643.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:91680.5-91680.29" *)
    casez (\initial )
      /* src = "libresoc.v:91680.9-91680.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:91717.5-91717.29" *)
    casez (\initial )
      /* src = "libresoc.v:91717.9-91717.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:91754.5-91754.29" *)
    casez (\initial )
      /* src = "libresoc.v:91754.9-91754.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:91791.5-91791.29" *)
    casez (\initial )
      /* src = "libresoc.v:91791.9-91791.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:91828.5-91828.29" *)
    casez (\initial )
      /* src = "libresoc.v:91828.9-91828.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:91865.5-91865.29" *)
    casez (\initial )
      /* src = "libresoc.v:91865.9-91865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:91902.5-91902.29" *)
    casez (\initial )
      /* src = "libresoc.v:91902.9-91902.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _47_ = 7'h02;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub10_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:91939.5-91939.29" *)
    casez (\initial )
      /* src = "libresoc.v:91939.9-91939.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:91976.5-91976.29" *)
    casez (\initial )
      /* src = "libresoc.v:91976.9-91976.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:92013.5-92013.29" *)
    casez (\initial )
      /* src = "libresoc.v:92013.9-92013.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _40_ = 2'h2;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:92050.5-92050.29" *)
    casez (\initial )
      /* src = "libresoc.v:92050.9-92050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h0c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h03;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = 8'h05;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = 8'h0b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _36_ = 8'h0d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _36_ = 8'h0e;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub10_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:92087.5-92087.29" *)
    casez (\initial )
      /* src = "libresoc.v:92087.9-92087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:92124.5-92124.29" *)
    casez (\initial )
      /* src = "libresoc.v:92124.9-92124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:92161.5-92161.29" *)
    casez (\initial )
      /* src = "libresoc.v:92161.9-92161.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _41_ = 1'h1;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:92198.5-92198.29" *)
    casez (\initial )
      /* src = "libresoc.v:92198.9-92198.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:92235.5-92235.29" *)
    casez (\initial )
      /* src = "libresoc.v:92235.9-92235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:92272.5-92272.29" *)
    casez (\initial )
      /* src = "libresoc.v:92272.9-92272.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:92309.5-92309.29" *)
    casez (\initial )
      /* src = "libresoc.v:92309.9-92309.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _42_ = 5'h11;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub10_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:92346.5-92346.29" *)
    casez (\initial )
      /* src = "libresoc.v:92346.9-92346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:92383.5-92383.29" *)
    casez (\initial )
      /* src = "libresoc.v:92383.9-92383.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:92420.5-92420.29" *)
    casez (\initial )
      /* src = "libresoc.v:92420.9-92420.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:92457.5-92457.29" *)
    casez (\initial )
      /* src = "libresoc.v:92457.9-92457.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:92494.5-92494.29" *)
    casez (\initial )
      /* src = "libresoc.v:92494.9-92494.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:92531.5-92531.29" *)
    casez (\initial )
      /* src = "libresoc.v:92531.9-92531.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:92568.5-92568.29" *)
    casez (\initial )
      /* src = "libresoc.v:92568.9-92568.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _44_ = 3'h1;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:92605.5-92605.29" *)
    casez (\initial )
      /* src = "libresoc.v:92605.9-92605.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:92642.5-92642.29" *)
    casez (\initial )
      /* src = "libresoc.v:92642.9-92642.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:92679.5-92679.29" *)
    casez (\initial )
      /* src = "libresoc.v:92679.9-92679.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub10_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:92720.1-94885.10" *)
module dec31_dec_sub11(dec31_dec_sub11_function_unit, dec31_dec_sub11_internal_op, dec31_dec_sub11_form, dec31_dec_sub11_asmcode, dec31_dec_sub11_SV_Etype, dec31_dec_sub11_SV_Ptype, dec31_dec_sub11_in1_sel, dec31_dec_sub11_in2_sel, dec31_dec_sub11_in3_sel, dec31_dec_sub11_out_sel, dec31_dec_sub11_cr_in, dec31_dec_sub11_cr_out, dec31_dec_sub11_sv_in1, dec31_dec_sub11_sv_in2, dec31_dec_sub11_sv_in3, dec31_dec_sub11_sv_out, dec31_dec_sub11_sv_out2, dec31_dec_sub11_sv_cr_in, dec31_dec_sub11_sv_cr_out, dec31_dec_sub11_ldst_len, dec31_dec_sub11_upd, dec31_dec_sub11_rc_sel, dec31_dec_sub11_cry_in, dec31_dec_sub11_inv_a, dec31_dec_sub11_inv_out, dec31_dec_sub11_cry_out, dec31_dec_sub11_br, dec31_dec_sub11_sgn_ext, dec31_dec_sub11_rsrv, dec31_dec_sub11_is_32b, dec31_dec_sub11_sgn, dec31_dec_sub11_lk, dec31_dec_sub11_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:94554.3-94608.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:94609.3-94663.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:93894.3-93948.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:94114.3-94168.6" *)
  reg _03_;
  (* src = "libresoc.v:93124.3-93178.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:93179.3-93233.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:93839.3-93893.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:94059.3-94113.6" *)
  reg _07_;
  (* src = "libresoc.v:94279.3-94333.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:93069.3-93123.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:94664.3-94718.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:94719.3-94773.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:94774.3-94828.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:93674.3-93728.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:93949.3-94003.6" *)
  reg _14_;
  (* src = "libresoc.v:94004.3-94058.6" *)
  reg _15_;
  (* src = "libresoc.v:94334.3-94388.6" *)
  reg _16_;
  (* src = "libresoc.v:93619.3-93673.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:94444.3-94498.6" *)
  reg _18_;
  (* src = "libresoc.v:94829.3-94883.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:93784.3-93838.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:94224.3-94278.6" *)
  reg _21_;
  (* src = "libresoc.v:94499.3-94553.6" *)
  reg _22_;
  (* src = "libresoc.v:94389.3-94443.6" *)
  reg _23_;
  (* src = "libresoc.v:94169.3-94223.6" *)
  reg _24_;
  (* src = "libresoc.v:93509.3-93563.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:93564.3-93618.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:93234.3-93288.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:93289.3-93343.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:93344.3-93398.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:93454.3-93508.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:93399.3-93453.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:93729.3-93783.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:92721.7-92721.20" *)
  reg _33_;
  (* src = "libresoc.v:94554.3-94608.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:94609.3-94663.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:93894.3-93948.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:94114.3-94168.6" *)
  reg _37_;
  (* src = "libresoc.v:93124.3-93178.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:93179.3-93233.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:93839.3-93893.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:94059.3-94113.6" *)
  reg _41_;
  (* src = "libresoc.v:94279.3-94333.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:93069.3-93123.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:94664.3-94718.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:94719.3-94773.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:94774.3-94828.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:93674.3-93728.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:93949.3-94003.6" *)
  reg _48_;
  (* src = "libresoc.v:94004.3-94058.6" *)
  reg _49_;
  (* src = "libresoc.v:94334.3-94388.6" *)
  reg _50_;
  (* src = "libresoc.v:93619.3-93673.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:94444.3-94498.6" *)
  reg _52_;
  (* src = "libresoc.v:94829.3-94883.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:93784.3-93838.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:94224.3-94278.6" *)
  reg _55_;
  (* src = "libresoc.v:94499.3-94553.6" *)
  reg _56_;
  (* src = "libresoc.v:94389.3-94443.6" *)
  reg _57_;
  (* src = "libresoc.v:94169.3-94223.6" *)
  reg _58_;
  (* src = "libresoc.v:93509.3-93563.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:93564.3-93618.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:93234.3-93288.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:93289.3-93343.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:93344.3-93398.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:93454.3-93508.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:93399.3-93453.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:93729.3-93783.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_SV_Etype;
  reg [1:0] dec31_dec_sub11_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_SV_Ptype;
  reg [1:0] dec31_dec_sub11_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub11_asmcode;
  reg [7:0] dec31_dec_sub11_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_br;
  reg dec31_dec_sub11_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_cr_in;
  reg [2:0] dec31_dec_sub11_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_cr_out;
  reg [2:0] dec31_dec_sub11_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_cry_in;
  reg [1:0] dec31_dec_sub11_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_cry_out;
  reg dec31_dec_sub11_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub11_form;
  reg [4:0] dec31_dec_sub11_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub11_function_unit;
  reg [13:0] dec31_dec_sub11_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_in1_sel;
  reg [2:0] dec31_dec_sub11_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub11_in2_sel;
  reg [3:0] dec31_dec_sub11_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_in3_sel;
  reg [1:0] dec31_dec_sub11_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub11_internal_op;
  reg [6:0] dec31_dec_sub11_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_inv_a;
  reg dec31_dec_sub11_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_inv_out;
  reg dec31_dec_sub11_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_is_32b;
  reg dec31_dec_sub11_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub11_ldst_len;
  reg [3:0] dec31_dec_sub11_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_lk;
  reg dec31_dec_sub11_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_out_sel;
  reg [2:0] dec31_dec_sub11_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_rc_sel;
  reg [1:0] dec31_dec_sub11_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_rsrv;
  reg dec31_dec_sub11_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_sgl_pipe;
  reg dec31_dec_sub11_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_sgn;
  reg dec31_dec_sub11_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub11_sgn_ext;
  reg dec31_dec_sub11_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_cr_in;
  reg [2:0] dec31_dec_sub11_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_cr_out;
  reg [2:0] dec31_dec_sub11_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_in1;
  reg [2:0] dec31_dec_sub11_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_in2;
  reg [2:0] dec31_dec_sub11_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_in3;
  reg [2:0] dec31_dec_sub11_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_out;
  reg [2:0] dec31_dec_sub11_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub11_sv_out2;
  reg [2:0] dec31_dec_sub11_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub11_upd;
  reg [1:0] dec31_dec_sub11_upd;
  (* src = "libresoc.v:92721.7-92721.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:93070.5-93070.29" *)
    casez (\initial )
      /* src = "libresoc.v:93070.9-93070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = 14'h0100;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub11_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:93125.5-93125.29" *)
    casez (\initial )
      /* src = "libresoc.v:93125.9-93125.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:93180.5-93180.29" *)
    casez (\initial )
      /* src = "libresoc.v:93180.9-93180.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:93235.5-93235.29" *)
    casez (\initial )
      /* src = "libresoc.v:93235.9-93235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:93290.5-93290.29" *)
    casez (\initial )
      /* src = "libresoc.v:93290.9-93290.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:93345.5-93345.29" *)
    casez (\initial )
      /* src = "libresoc.v:93345.9-93345.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:93400.5-93400.29" *)
    casez (\initial )
      /* src = "libresoc.v:93400.9-93400.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:93455.5-93455.29" *)
    casez (\initial )
      /* src = "libresoc.v:93455.9-93455.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:93510.5-93510.29" *)
    casez (\initial )
      /* src = "libresoc.v:93510.9-93510.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:93565.5-93565.29" *)
    casez (\initial )
      /* src = "libresoc.v:93565.9-93565.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:93620.5-93620.29" *)
    casez (\initial )
      /* src = "libresoc.v:93620.9-93620.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:93675.5-93675.29" *)
    casez (\initial )
      /* src = "libresoc.v:93675.9-93675.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _47_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = 7'h32;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub11_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:93730.5-93730.29" *)
    casez (\initial )
      /* src = "libresoc.v:93730.9-93730.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:93785.5-93785.29" *)
    casez (\initial )
      /* src = "libresoc.v:93785.9-93785.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:93840.5-93840.29" *)
    casez (\initial )
      /* src = "libresoc.v:93840.9-93840.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:93895.5-93895.29" *)
    casez (\initial )
      /* src = "libresoc.v:93895.9-93895.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _36_ = 8'h3e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = 8'h3f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _36_ = 8'h3c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _36_ = 8'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _36_ = 8'h41;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'h42;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h3b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _36_ = 8'h40;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h75;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h73;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h7c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h7d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _36_ = 8'h7c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h7d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h81;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = 8'h82;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub11_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:93950.5-93950.29" *)
    casez (\initial )
      /* src = "libresoc.v:93950.9-93950.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:94005.5-94005.29" *)
    casez (\initial )
      /* src = "libresoc.v:94005.9-94005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:94060.5-94060.29" *)
    casez (\initial )
      /* src = "libresoc.v:94060.9-94060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:94115.5-94115.29" *)
    casez (\initial )
      /* src = "libresoc.v:94115.9-94115.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:94170.5-94170.29" *)
    casez (\initial )
      /* src = "libresoc.v:94170.9-94170.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:94225.5-94225.29" *)
    casez (\initial )
      /* src = "libresoc.v:94225.9-94225.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:94280.5-94280.29" *)
    casez (\initial )
      /* src = "libresoc.v:94280.9-94280.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = 5'h11;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub11_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:94335.5-94335.29" *)
    casez (\initial )
      /* src = "libresoc.v:94335.9-94335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = 1'h1;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:94390.5-94390.29" *)
    casez (\initial )
      /* src = "libresoc.v:94390.9-94390.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = 1'h1;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:94445.5-94445.29" *)
    casez (\initial )
      /* src = "libresoc.v:94445.9-94445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:94500.5-94500.29" *)
    casez (\initial )
      /* src = "libresoc.v:94500.9-94500.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:94555.5-94555.29" *)
    casez (\initial )
      /* src = "libresoc.v:94555.9-94555.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:94610.5-94610.29" *)
    casez (\initial )
      /* src = "libresoc.v:94610.9-94610.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:94665.5-94665.29" *)
    casez (\initial )
      /* src = "libresoc.v:94665.9-94665.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = 3'h1;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:94720.5-94720.29" *)
    casez (\initial )
      /* src = "libresoc.v:94720.9-94720.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:94775.5-94775.29" *)
    casez (\initial )
      /* src = "libresoc.v:94775.9-94775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:94830.5-94830.29" *)
    casez (\initial )
      /* src = "libresoc.v:94830.9-94830.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub11_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:94889.1-98638.10" *)
module dec31_dec_sub15(dec31_dec_sub15_function_unit, dec31_dec_sub15_internal_op, dec31_dec_sub15_form, dec31_dec_sub15_asmcode, dec31_dec_sub15_SV_Etype, dec31_dec_sub15_SV_Ptype, dec31_dec_sub15_in1_sel, dec31_dec_sub15_in2_sel, dec31_dec_sub15_in3_sel, dec31_dec_sub15_out_sel, dec31_dec_sub15_cr_in, dec31_dec_sub15_cr_out, dec31_dec_sub15_sv_in1, dec31_dec_sub15_sv_in2, dec31_dec_sub15_sv_in3, dec31_dec_sub15_sv_out, dec31_dec_sub15_sv_out2, dec31_dec_sub15_sv_cr_in, dec31_dec_sub15_sv_cr_out, dec31_dec_sub15_ldst_len, dec31_dec_sub15_upd, dec31_dec_sub15_rc_sel, dec31_dec_sub15_cry_in, dec31_dec_sub15_inv_a, dec31_dec_sub15_inv_out, dec31_dec_sub15_cry_out, dec31_dec_sub15_br, dec31_dec_sub15_sgn_ext, dec31_dec_sub15_rsrv, dec31_dec_sub15_is_32b, dec31_dec_sub15_sgn, dec31_dec_sub15_lk, dec31_dec_sub15_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:98019.3-98121.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:98122.3-98224.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:96783.3-96885.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:97195.3-97297.6" *)
  reg _03_;
  (* src = "libresoc.v:95341.3-95443.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:95444.3-95546.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:96680.3-96782.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:97092.3-97194.6" *)
  reg _07_;
  (* src = "libresoc.v:97504.3-97606.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:95238.3-95340.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:98225.3-98327.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:98328.3-98430.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:98431.3-98533.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:96371.3-96473.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:96886.3-96988.6" *)
  reg _14_;
  (* src = "libresoc.v:96989.3-97091.6" *)
  reg _15_;
  (* src = "libresoc.v:97607.3-97709.6" *)
  reg _16_;
  (* src = "libresoc.v:96268.3-96370.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:97813.3-97915.6" *)
  reg _18_;
  (* src = "libresoc.v:98534.3-98636.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:96577.3-96679.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:97401.3-97503.6" *)
  reg _21_;
  (* src = "libresoc.v:97916.3-98018.6" *)
  reg _22_;
  (* src = "libresoc.v:97710.3-97812.6" *)
  reg _23_;
  (* src = "libresoc.v:97298.3-97400.6" *)
  reg _24_;
  (* src = "libresoc.v:96062.3-96164.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:96165.3-96267.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:95547.3-95649.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:95650.3-95752.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:95753.3-95855.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:95959.3-96061.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:95856.3-95958.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:96474.3-96576.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:94890.7-94890.20" *)
  reg _33_;
  (* src = "libresoc.v:98019.3-98121.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:98122.3-98224.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:96783.3-96885.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:97195.3-97297.6" *)
  reg _37_;
  (* src = "libresoc.v:95341.3-95443.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:95444.3-95546.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:96680.3-96782.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:97092.3-97194.6" *)
  reg _41_;
  (* src = "libresoc.v:97504.3-97606.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:95238.3-95340.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:98225.3-98327.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:98328.3-98430.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:98431.3-98533.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:96371.3-96473.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:96886.3-96988.6" *)
  reg _48_;
  (* src = "libresoc.v:96989.3-97091.6" *)
  reg _49_;
  (* src = "libresoc.v:97607.3-97709.6" *)
  reg _50_;
  (* src = "libresoc.v:96268.3-96370.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:97813.3-97915.6" *)
  reg _52_;
  (* src = "libresoc.v:98534.3-98636.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:96577.3-96679.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:97401.3-97503.6" *)
  reg _55_;
  (* src = "libresoc.v:97916.3-98018.6" *)
  reg _56_;
  (* src = "libresoc.v:97710.3-97812.6" *)
  reg _57_;
  (* src = "libresoc.v:97298.3-97400.6" *)
  reg _58_;
  (* src = "libresoc.v:96062.3-96164.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:96165.3-96267.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:95547.3-95649.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:95650.3-95752.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:95753.3-95855.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:95959.3-96061.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:95856.3-95958.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:96474.3-96576.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_SV_Etype;
  reg [1:0] dec31_dec_sub15_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_SV_Ptype;
  reg [1:0] dec31_dec_sub15_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub15_asmcode;
  reg [7:0] dec31_dec_sub15_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_br;
  reg dec31_dec_sub15_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_cr_in;
  reg [2:0] dec31_dec_sub15_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_cr_out;
  reg [2:0] dec31_dec_sub15_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_cry_in;
  reg [1:0] dec31_dec_sub15_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_cry_out;
  reg dec31_dec_sub15_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub15_form;
  reg [4:0] dec31_dec_sub15_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub15_function_unit;
  reg [13:0] dec31_dec_sub15_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_in1_sel;
  reg [2:0] dec31_dec_sub15_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub15_in2_sel;
  reg [3:0] dec31_dec_sub15_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_in3_sel;
  reg [1:0] dec31_dec_sub15_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub15_internal_op;
  reg [6:0] dec31_dec_sub15_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_inv_a;
  reg dec31_dec_sub15_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_inv_out;
  reg dec31_dec_sub15_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_is_32b;
  reg dec31_dec_sub15_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub15_ldst_len;
  reg [3:0] dec31_dec_sub15_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_lk;
  reg dec31_dec_sub15_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_out_sel;
  reg [2:0] dec31_dec_sub15_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_rc_sel;
  reg [1:0] dec31_dec_sub15_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_rsrv;
  reg dec31_dec_sub15_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_sgl_pipe;
  reg dec31_dec_sub15_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_sgn;
  reg dec31_dec_sub15_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub15_sgn_ext;
  reg dec31_dec_sub15_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_cr_in;
  reg [2:0] dec31_dec_sub15_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_cr_out;
  reg [2:0] dec31_dec_sub15_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_in1;
  reg [2:0] dec31_dec_sub15_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_in2;
  reg [2:0] dec31_dec_sub15_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_in3;
  reg [2:0] dec31_dec_sub15_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_out;
  reg [2:0] dec31_dec_sub15_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub15_sv_out2;
  reg [2:0] dec31_dec_sub15_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub15_upd;
  reg [1:0] dec31_dec_sub15_upd;
  (* src = "libresoc.v:94890.7-94890.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:95239.5-95239.29" *)
    casez (\initial )
      /* src = "libresoc.v:95239.9-95239.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _43_ = 14'h0040;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub15_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:95342.5-95342.29" *)
    casez (\initial )
      /* src = "libresoc.v:95342.9-95342.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _38_ = 3'h5;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:95445.5-95445.29" *)
    casez (\initial )
      /* src = "libresoc.v:95445.9-95445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:95548.5-95548.29" *)
    casez (\initial )
      /* src = "libresoc.v:95548.9-95548.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:95651.5-95651.29" *)
    casez (\initial )
      /* src = "libresoc.v:95651.9-95651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:95754.5-95754.29" *)
    casez (\initial )
      /* src = "libresoc.v:95754.9-95754.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:95857.5-95857.29" *)
    casez (\initial )
      /* src = "libresoc.v:95857.9-95857.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:95960.5-95960.29" *)
    casez (\initial )
      /* src = "libresoc.v:95960.9-95960.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:96063.5-96063.29" *)
    casez (\initial )
      /* src = "libresoc.v:96063.9-96063.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _59_ = 3'h4;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:96166.5-96166.29" *)
    casez (\initial )
      /* src = "libresoc.v:96166.9-96166.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:96269.5-96269.29" *)
    casez (\initial )
      /* src = "libresoc.v:96269.9-96269.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:96372.5-96372.29" *)
    casez (\initial )
      /* src = "libresoc.v:96372.9-96372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _47_ = 7'h23;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub15_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:96475.5-96475.29" *)
    casez (\initial )
      /* src = "libresoc.v:96475.9-96475.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:96578.5-96578.29" *)
    casez (\initial )
      /* src = "libresoc.v:96578.9-96578.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:96681.5-96681.29" *)
    casez (\initial )
      /* src = "libresoc.v:96681.9-96681.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:96784.5-96784.29" *)
    casez (\initial )
      /* src = "libresoc.v:96784.9-96784.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _36_ = 8'h4b;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub15_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:96887.5-96887.29" *)
    casez (\initial )
      /* src = "libresoc.v:96887.9-96887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:96990.5-96990.29" *)
    casez (\initial )
      /* src = "libresoc.v:96990.9-96990.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:97093.5-97093.29" *)
    casez (\initial )
      /* src = "libresoc.v:97093.9-97093.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:97196.5-97196.29" *)
    casez (\initial )
      /* src = "libresoc.v:97196.9-97196.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:97299.5-97299.29" *)
    casez (\initial )
      /* src = "libresoc.v:97299.9-97299.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:97402.5-97402.29" *)
    casez (\initial )
      /* src = "libresoc.v:97402.9-97402.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:97505.5-97505.29" *)
    casez (\initial )
      /* src = "libresoc.v:97505.9-97505.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h12;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _42_ = 5'h12;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub15_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:97608.5-97608.29" *)
    casez (\initial )
      /* src = "libresoc.v:97608.9-97608.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:97711.5-97711.29" *)
    casez (\initial )
      /* src = "libresoc.v:97711.9-97711.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:97814.5-97814.29" *)
    casez (\initial )
      /* src = "libresoc.v:97814.9-97814.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:97917.5-97917.29" *)
    casez (\initial )
      /* src = "libresoc.v:97917.9-97917.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:98020.5-98020.29" *)
    casez (\initial )
      /* src = "libresoc.v:98020.9-98020.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:98123.5-98123.29" *)
    casez (\initial )
      /* src = "libresoc.v:98123.9-98123.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:98226.5-98226.29" *)
    casez (\initial )
      /* src = "libresoc.v:98226.9-98226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:98329.5-98329.29" *)
    casez (\initial )
      /* src = "libresoc.v:98329.9-98329.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:98432.5-98432.29" *)
    casez (\initial )
      /* src = "libresoc.v:98432.9-98432.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:98535.5-98535.29" *)
    casez (\initial )
      /* src = "libresoc.v:98535.9-98535.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub15_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:98642.1-99322.10" *)
module dec31_dec_sub16(dec31_dec_sub16_function_unit, dec31_dec_sub16_internal_op, dec31_dec_sub16_form, dec31_dec_sub16_asmcode, dec31_dec_sub16_SV_Etype, dec31_dec_sub16_SV_Ptype, dec31_dec_sub16_in1_sel, dec31_dec_sub16_in2_sel, dec31_dec_sub16_in3_sel, dec31_dec_sub16_out_sel, dec31_dec_sub16_cr_in, dec31_dec_sub16_cr_out, dec31_dec_sub16_sv_in1, dec31_dec_sub16_sv_in2, dec31_dec_sub16_sv_in3, dec31_dec_sub16_sv_out, dec31_dec_sub16_sv_out2, dec31_dec_sub16_sv_cr_in, dec31_dec_sub16_sv_cr_out, dec31_dec_sub16_ldst_len, dec31_dec_sub16_upd, dec31_dec_sub16_rc_sel, dec31_dec_sub16_cry_in, dec31_dec_sub16_inv_a, dec31_dec_sub16_inv_out, dec31_dec_sub16_cry_out, dec31_dec_sub16_br, dec31_dec_sub16_sgn_ext, dec31_dec_sub16_rsrv, dec31_dec_sub16_is_32b, dec31_dec_sub16_sgn, dec31_dec_sub16_lk, dec31_dec_sub16_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:99261.3-99270.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:99271.3-99280.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:99141.3-99150.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:99181.3-99190.6" *)
  reg _03_;
  (* src = "libresoc.v:99001.3-99010.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:99011.3-99020.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:99131.3-99140.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:99171.3-99180.6" *)
  reg _07_;
  (* src = "libresoc.v:99211.3-99220.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:98991.3-99000.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:99281.3-99290.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:99291.3-99300.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:99301.3-99310.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:99101.3-99110.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:99151.3-99160.6" *)
  reg _14_;
  (* src = "libresoc.v:99161.3-99170.6" *)
  reg _15_;
  (* src = "libresoc.v:99221.3-99230.6" *)
  reg _16_;
  (* src = "libresoc.v:99091.3-99100.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:99241.3-99250.6" *)
  reg _18_;
  (* src = "libresoc.v:99311.3-99320.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:99121.3-99130.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:99201.3-99210.6" *)
  reg _21_;
  (* src = "libresoc.v:99251.3-99260.6" *)
  reg _22_;
  (* src = "libresoc.v:99231.3-99240.6" *)
  reg _23_;
  (* src = "libresoc.v:99191.3-99200.6" *)
  reg _24_;
  (* src = "libresoc.v:99071.3-99080.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:99081.3-99090.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:99021.3-99030.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:99031.3-99040.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:99041.3-99050.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:99061.3-99070.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:99051.3-99060.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:99111.3-99120.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:98643.7-98643.20" *)
  reg _33_;
  (* src = "libresoc.v:99261.3-99270.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:99271.3-99280.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:99141.3-99150.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:99181.3-99190.6" *)
  reg _37_;
  (* src = "libresoc.v:99001.3-99010.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:99011.3-99020.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:99131.3-99140.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:99171.3-99180.6" *)
  reg _41_;
  (* src = "libresoc.v:99211.3-99220.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:98991.3-99000.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:99281.3-99290.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:99291.3-99300.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:99301.3-99310.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:99101.3-99110.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:99151.3-99160.6" *)
  reg _48_;
  (* src = "libresoc.v:99161.3-99170.6" *)
  reg _49_;
  (* src = "libresoc.v:99221.3-99230.6" *)
  reg _50_;
  (* src = "libresoc.v:99091.3-99100.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:99241.3-99250.6" *)
  reg _52_;
  (* src = "libresoc.v:99311.3-99320.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:99121.3-99130.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:99201.3-99210.6" *)
  reg _55_;
  (* src = "libresoc.v:99251.3-99260.6" *)
  reg _56_;
  (* src = "libresoc.v:99231.3-99240.6" *)
  reg _57_;
  (* src = "libresoc.v:99191.3-99200.6" *)
  reg _58_;
  (* src = "libresoc.v:99071.3-99080.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:99081.3-99090.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:99021.3-99030.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:99031.3-99040.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:99041.3-99050.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:99061.3-99070.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:99051.3-99060.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:99111.3-99120.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_SV_Etype;
  reg [1:0] dec31_dec_sub16_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_SV_Ptype;
  reg [1:0] dec31_dec_sub16_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub16_asmcode;
  reg [7:0] dec31_dec_sub16_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_br;
  reg dec31_dec_sub16_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_cr_in;
  reg [2:0] dec31_dec_sub16_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_cr_out;
  reg [2:0] dec31_dec_sub16_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_cry_in;
  reg [1:0] dec31_dec_sub16_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_cry_out;
  reg dec31_dec_sub16_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub16_form;
  reg [4:0] dec31_dec_sub16_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub16_function_unit;
  reg [13:0] dec31_dec_sub16_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_in1_sel;
  reg [2:0] dec31_dec_sub16_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub16_in2_sel;
  reg [3:0] dec31_dec_sub16_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_in3_sel;
  reg [1:0] dec31_dec_sub16_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub16_internal_op;
  reg [6:0] dec31_dec_sub16_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_inv_a;
  reg dec31_dec_sub16_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_inv_out;
  reg dec31_dec_sub16_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_is_32b;
  reg dec31_dec_sub16_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub16_ldst_len;
  reg [3:0] dec31_dec_sub16_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_lk;
  reg dec31_dec_sub16_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_out_sel;
  reg [2:0] dec31_dec_sub16_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_rc_sel;
  reg [1:0] dec31_dec_sub16_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_rsrv;
  reg dec31_dec_sub16_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_sgl_pipe;
  reg dec31_dec_sub16_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_sgn;
  reg dec31_dec_sub16_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub16_sgn_ext;
  reg dec31_dec_sub16_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_cr_in;
  reg [2:0] dec31_dec_sub16_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_cr_out;
  reg [2:0] dec31_dec_sub16_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_in1;
  reg [2:0] dec31_dec_sub16_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_in2;
  reg [2:0] dec31_dec_sub16_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_in3;
  reg [2:0] dec31_dec_sub16_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_out;
  reg [2:0] dec31_dec_sub16_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub16_sv_out2;
  reg [2:0] dec31_dec_sub16_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub16_upd;
  reg [1:0] dec31_dec_sub16_upd;
  (* src = "libresoc.v:98643.7-98643.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:98992.5-98992.29" *)
    casez (\initial )
      /* src = "libresoc.v:98992.9-98992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0040;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub16_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:99002.5-99002.29" *)
    casez (\initial )
      /* src = "libresoc.v:99002.9-99002.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h6;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:99012.5-99012.29" *)
    casez (\initial )
      /* src = "libresoc.v:99012.9-99012.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h4;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:99022.5-99022.29" *)
    casez (\initial )
      /* src = "libresoc.v:99022.9-99022.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:99032.5-99032.29" *)
    casez (\initial )
      /* src = "libresoc.v:99032.9-99032.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:99042.5-99042.29" *)
    casez (\initial )
      /* src = "libresoc.v:99042.9-99042.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:99052.5-99052.29" *)
    casez (\initial )
      /* src = "libresoc.v:99052.9-99052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:99062.5-99062.29" *)
    casez (\initial )
      /* src = "libresoc.v:99062.9-99062.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:99072.5-99072.29" *)
    casez (\initial )
      /* src = "libresoc.v:99072.9-99072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:99082.5-99082.29" *)
    casez (\initial )
      /* src = "libresoc.v:99082.9-99082.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:99092.5-99092.29" *)
    casez (\initial )
      /* src = "libresoc.v:99092.9-99092.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:99102.5-99102.29" *)
    casez (\initial )
      /* src = "libresoc.v:99102.9-99102.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h30;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub16_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:99112.5-99112.29" *)
    casez (\initial )
      /* src = "libresoc.v:99112.9-99112.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:99122.5-99122.29" *)
    casez (\initial )
      /* src = "libresoc.v:99122.9-99122.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:99132.5-99132.29" *)
    casez (\initial )
      /* src = "libresoc.v:99132.9-99132.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:99142.5-99142.29" *)
    casez (\initial )
      /* src = "libresoc.v:99142.9-99142.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h76;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub16_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:99152.5-99152.29" *)
    casez (\initial )
      /* src = "libresoc.v:99152.9-99152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:99162.5-99162.29" *)
    casez (\initial )
      /* src = "libresoc.v:99162.9-99162.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:99172.5-99172.29" *)
    casez (\initial )
      /* src = "libresoc.v:99172.9-99172.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:99182.5-99182.29" *)
    casez (\initial )
      /* src = "libresoc.v:99182.9-99182.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:99192.5-99192.29" *)
    casez (\initial )
      /* src = "libresoc.v:99192.9-99192.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:99202.5-99202.29" *)
    casez (\initial )
      /* src = "libresoc.v:99202.9-99202.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:99212.5-99212.29" *)
    casez (\initial )
      /* src = "libresoc.v:99212.9-99212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h0a;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub16_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:99222.5-99222.29" *)
    casez (\initial )
      /* src = "libresoc.v:99222.9-99222.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:99232.5-99232.29" *)
    casez (\initial )
      /* src = "libresoc.v:99232.9-99232.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:99242.5-99242.29" *)
    casez (\initial )
      /* src = "libresoc.v:99242.9-99242.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:99252.5-99252.29" *)
    casez (\initial )
      /* src = "libresoc.v:99252.9-99252.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:99262.5-99262.29" *)
    casez (\initial )
      /* src = "libresoc.v:99262.9-99262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:99272.5-99272.29" *)
    casez (\initial )
      /* src = "libresoc.v:99272.9-99272.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:99282.5-99282.29" *)
    casez (\initial )
      /* src = "libresoc.v:99282.9-99282.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h4;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:99292.5-99292.29" *)
    casez (\initial )
      /* src = "libresoc.v:99292.9-99292.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:99302.5-99302.29" *)
    casez (\initial )
      /* src = "libresoc.v:99302.9-99302.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:99312.5-99312.29" *)
    casez (\initial )
      /* src = "libresoc.v:99312.9-99312.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub16_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:99326.1-100402.10" *)
module dec31_dec_sub18(dec31_dec_sub18_function_unit, dec31_dec_sub18_internal_op, dec31_dec_sub18_form, dec31_dec_sub18_asmcode, dec31_dec_sub18_SV_Etype, dec31_dec_sub18_SV_Ptype, dec31_dec_sub18_in1_sel, dec31_dec_sub18_in2_sel, dec31_dec_sub18_in3_sel, dec31_dec_sub18_out_sel, dec31_dec_sub18_cr_in, dec31_dec_sub18_cr_out, dec31_dec_sub18_sv_in1, dec31_dec_sub18_sv_in2, dec31_dec_sub18_sv_in3, dec31_dec_sub18_sv_out, dec31_dec_sub18_sv_out2, dec31_dec_sub18_sv_cr_in, dec31_dec_sub18_sv_cr_out, dec31_dec_sub18_ldst_len, dec31_dec_sub18_upd, dec31_dec_sub18_rc_sel, dec31_dec_sub18_cry_in, dec31_dec_sub18_inv_a, dec31_dec_sub18_inv_out, dec31_dec_sub18_cry_out, dec31_dec_sub18_br, dec31_dec_sub18_sgn_ext, dec31_dec_sub18_rsrv, dec31_dec_sub18_is_32b, dec31_dec_sub18_sgn, dec31_dec_sub18_lk, dec31_dec_sub18_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:100269.3-100290.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:100291.3-100312.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:100005.3-100026.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:100093.3-100114.6" *)
  reg _03_;
  (* src = "libresoc.v:99697.3-99718.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:99719.3-99740.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:99983.3-100004.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:100071.3-100092.6" *)
  reg _07_;
  (* src = "libresoc.v:100159.3-100180.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:99675.3-99696.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:100313.3-100334.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:100335.3-100356.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:100357.3-100378.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:99917.3-99938.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:100027.3-100048.6" *)
  reg _14_;
  (* src = "libresoc.v:100049.3-100070.6" *)
  reg _15_;
  (* src = "libresoc.v:100181.3-100202.6" *)
  reg _16_;
  (* src = "libresoc.v:99895.3-99916.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:100225.3-100246.6" *)
  reg _18_;
  (* src = "libresoc.v:100379.3-100400.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:99961.3-99982.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:100137.3-100158.6" *)
  reg _21_;
  (* src = "libresoc.v:100247.3-100268.6" *)
  reg _22_;
  (* src = "libresoc.v:100203.3-100224.6" *)
  reg _23_;
  (* src = "libresoc.v:100115.3-100136.6" *)
  reg _24_;
  (* src = "libresoc.v:99851.3-99872.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:99873.3-99894.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:99741.3-99762.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:99763.3-99784.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:99785.3-99806.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:99829.3-99850.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:99807.3-99828.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:99939.3-99960.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:99327.7-99327.20" *)
  reg _33_;
  (* src = "libresoc.v:100269.3-100290.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:100291.3-100312.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:100005.3-100026.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:100093.3-100114.6" *)
  reg _37_;
  (* src = "libresoc.v:99697.3-99718.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:99719.3-99740.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:99983.3-100004.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:100071.3-100092.6" *)
  reg _41_;
  (* src = "libresoc.v:100159.3-100180.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:99675.3-99696.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:100313.3-100334.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:100335.3-100356.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:100357.3-100378.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:99917.3-99938.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:100027.3-100048.6" *)
  reg _48_;
  (* src = "libresoc.v:100049.3-100070.6" *)
  reg _49_;
  (* src = "libresoc.v:100181.3-100202.6" *)
  reg _50_;
  (* src = "libresoc.v:99895.3-99916.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:100225.3-100246.6" *)
  reg _52_;
  (* src = "libresoc.v:100379.3-100400.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:99961.3-99982.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:100137.3-100158.6" *)
  reg _55_;
  (* src = "libresoc.v:100247.3-100268.6" *)
  reg _56_;
  (* src = "libresoc.v:100203.3-100224.6" *)
  reg _57_;
  (* src = "libresoc.v:100115.3-100136.6" *)
  reg _58_;
  (* src = "libresoc.v:99851.3-99872.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:99873.3-99894.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:99741.3-99762.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:99763.3-99784.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:99785.3-99806.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:99829.3-99850.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:99807.3-99828.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:99939.3-99960.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_SV_Etype;
  reg [1:0] dec31_dec_sub18_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_SV_Ptype;
  reg [1:0] dec31_dec_sub18_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub18_asmcode;
  reg [7:0] dec31_dec_sub18_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_br;
  reg dec31_dec_sub18_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_cr_in;
  reg [2:0] dec31_dec_sub18_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_cr_out;
  reg [2:0] dec31_dec_sub18_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_cry_in;
  reg [1:0] dec31_dec_sub18_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_cry_out;
  reg dec31_dec_sub18_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub18_form;
  reg [4:0] dec31_dec_sub18_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub18_function_unit;
  reg [13:0] dec31_dec_sub18_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_in1_sel;
  reg [2:0] dec31_dec_sub18_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub18_in2_sel;
  reg [3:0] dec31_dec_sub18_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_in3_sel;
  reg [1:0] dec31_dec_sub18_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub18_internal_op;
  reg [6:0] dec31_dec_sub18_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_inv_a;
  reg dec31_dec_sub18_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_inv_out;
  reg dec31_dec_sub18_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_is_32b;
  reg dec31_dec_sub18_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub18_ldst_len;
  reg [3:0] dec31_dec_sub18_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_lk;
  reg dec31_dec_sub18_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_out_sel;
  reg [2:0] dec31_dec_sub18_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_rc_sel;
  reg [1:0] dec31_dec_sub18_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_rsrv;
  reg dec31_dec_sub18_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_sgl_pipe;
  reg dec31_dec_sub18_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_sgn;
  reg dec31_dec_sub18_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub18_sgn_ext;
  reg dec31_dec_sub18_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_cr_in;
  reg [2:0] dec31_dec_sub18_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_cr_out;
  reg [2:0] dec31_dec_sub18_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_in1;
  reg [2:0] dec31_dec_sub18_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_in2;
  reg [2:0] dec31_dec_sub18_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_in3;
  reg [2:0] dec31_dec_sub18_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_out;
  reg [2:0] dec31_dec_sub18_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub18_sv_out2;
  reg [2:0] dec31_dec_sub18_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub18_upd;
  reg [1:0] dec31_dec_sub18_upd;
  (* src = "libresoc.v:99327.7-99327.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:100006.5-100006.29" *)
    casez (\initial )
      /* src = "libresoc.v:100006.9-100006.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _36_ = 8'h78;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h77;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h9e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _36_ = 8'hcd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'hce;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub18_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:100028.5-100028.29" *)
    casez (\initial )
      /* src = "libresoc.v:100028.9-100028.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:100050.5-100050.29" *)
    casez (\initial )
      /* src = "libresoc.v:100050.9-100050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:100072.5-100072.29" *)
    casez (\initial )
      /* src = "libresoc.v:100072.9-100072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:100094.5-100094.29" *)
    casez (\initial )
      /* src = "libresoc.v:100094.9-100094.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:100116.5-100116.29" *)
    casez (\initial )
      /* src = "libresoc.v:100116.9-100116.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:100138.5-100138.29" *)
    casez (\initial )
      /* src = "libresoc.v:100138.9-100138.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:100160.5-100160.29" *)
    casez (\initial )
      /* src = "libresoc.v:100160.9-100160.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub18_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:100182.5-100182.29" *)
    casez (\initial )
      /* src = "libresoc.v:100182.9-100182.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:100204.5-100204.29" *)
    casez (\initial )
      /* src = "libresoc.v:100204.9-100204.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:100226.5-100226.29" *)
    casez (\initial )
      /* src = "libresoc.v:100226.9-100226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:100248.5-100248.29" *)
    casez (\initial )
      /* src = "libresoc.v:100248.9-100248.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:100270.5-100270.29" *)
    casez (\initial )
      /* src = "libresoc.v:100270.9-100270.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h0;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:100292.5-100292.29" *)
    casez (\initial )
      /* src = "libresoc.v:100292.9-100292.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h0;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:100314.5-100314.29" *)
    casez (\initial )
      /* src = "libresoc.v:100314.9-100314.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:100336.5-100336.29" *)
    casez (\initial )
      /* src = "libresoc.v:100336.9-100336.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:100358.5-100358.29" *)
    casez (\initial )
      /* src = "libresoc.v:100358.9-100358.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:100380.5-100380.29" *)
    casez (\initial )
      /* src = "libresoc.v:100380.9-100380.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_out_sel <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:99676.5-99676.29" *)
    casez (\initial )
      /* src = "libresoc.v:99676.9-99676.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _43_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0800;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _43_ = 14'h0800;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0800;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub18_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:99698.5-99698.29" *)
    casez (\initial )
      /* src = "libresoc.v:99698.9-99698.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:99720.5-99720.29" *)
    casez (\initial )
      /* src = "libresoc.v:99720.9-99720.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:99742.5-99742.29" *)
    casez (\initial )
      /* src = "libresoc.v:99742.9-99742.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:99764.5-99764.29" *)
    casez (\initial )
      /* src = "libresoc.v:99764.9-99764.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:99786.5-99786.29" *)
    casez (\initial )
      /* src = "libresoc.v:99786.9-99786.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:99808.5-99808.29" *)
    casez (\initial )
      /* src = "libresoc.v:99808.9-99808.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:99830.5-99830.29" *)
    casez (\initial )
      /* src = "libresoc.v:99830.9-99830.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:99852.5-99852.29" *)
    casez (\initial )
      /* src = "libresoc.v:99852.9-99852.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:99874.5-99874.29" *)
    casez (\initial )
      /* src = "libresoc.v:99874.9-99874.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:99896.5-99896.29" *)
    casez (\initial )
      /* src = "libresoc.v:99896.9-99896.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:99918.5-99918.29" *)
    casez (\initial )
      /* src = "libresoc.v:99918.9-99918.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _47_ = 7'h48;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h4a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _47_ = 7'h4b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h4b;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub18_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:99940.5-99940.29" *)
    casez (\initial )
      /* src = "libresoc.v:99940.9-99940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:99962.5-99962.29" *)
    casez (\initial )
      /* src = "libresoc.v:99962.9-99962.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:99984.5-99984.29" *)
    casez (\initial )
      /* src = "libresoc.v:99984.9-99984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub18_cry_in <= _06_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:100406.1-101383.10" *)
module dec31_dec_sub19(dec31_dec_sub19_function_unit, dec31_dec_sub19_internal_op, dec31_dec_sub19_form, dec31_dec_sub19_asmcode, dec31_dec_sub19_SV_Etype, dec31_dec_sub19_SV_Ptype, dec31_dec_sub19_in1_sel, dec31_dec_sub19_in2_sel, dec31_dec_sub19_in3_sel, dec31_dec_sub19_out_sel, dec31_dec_sub19_cr_in, dec31_dec_sub19_cr_out, dec31_dec_sub19_sv_in1, dec31_dec_sub19_sv_in2, dec31_dec_sub19_sv_in3, dec31_dec_sub19_sv_out, dec31_dec_sub19_sv_out2, dec31_dec_sub19_sv_cr_in, dec31_dec_sub19_sv_cr_out, dec31_dec_sub19_ldst_len, dec31_dec_sub19_upd, dec31_dec_sub19_rc_sel, dec31_dec_sub19_cry_in, dec31_dec_sub19_inv_a, dec31_dec_sub19_inv_out, dec31_dec_sub19_cry_out, dec31_dec_sub19_br, dec31_dec_sub19_sgn_ext, dec31_dec_sub19_rsrv, dec31_dec_sub19_is_32b, dec31_dec_sub19_sgn, dec31_dec_sub19_lk, dec31_dec_sub19_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:101268.3-101286.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:101287.3-101305.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:101040.3-101058.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:101116.3-101134.6" *)
  reg _03_;
  (* src = "libresoc.v:100774.3-100792.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:100793.3-100811.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:101021.3-101039.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:101097.3-101115.6" *)
  reg _07_;
  (* src = "libresoc.v:101173.3-101191.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:100755.3-100773.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:101306.3-101324.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:101325.3-101343.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:101344.3-101362.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:100964.3-100982.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:101059.3-101077.6" *)
  reg _14_;
  (* src = "libresoc.v:101078.3-101096.6" *)
  reg _15_;
  (* src = "libresoc.v:101192.3-101210.6" *)
  reg _16_;
  (* src = "libresoc.v:100945.3-100963.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:101230.3-101248.6" *)
  reg _18_;
  (* src = "libresoc.v:101363.3-101381.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:101002.3-101020.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:101154.3-101172.6" *)
  reg _21_;
  (* src = "libresoc.v:101249.3-101267.6" *)
  reg _22_;
  (* src = "libresoc.v:101211.3-101229.6" *)
  reg _23_;
  (* src = "libresoc.v:101135.3-101153.6" *)
  reg _24_;
  (* src = "libresoc.v:100907.3-100925.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:100926.3-100944.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:100812.3-100830.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:100831.3-100849.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:100850.3-100868.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:100888.3-100906.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:100869.3-100887.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:100983.3-101001.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:100407.7-100407.20" *)
  reg _33_;
  (* src = "libresoc.v:101268.3-101286.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:101287.3-101305.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:101040.3-101058.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:101116.3-101134.6" *)
  reg _37_;
  (* src = "libresoc.v:100774.3-100792.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:100793.3-100811.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:101021.3-101039.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:101097.3-101115.6" *)
  reg _41_;
  (* src = "libresoc.v:101173.3-101191.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:100755.3-100773.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:101306.3-101324.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:101325.3-101343.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:101344.3-101362.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:100964.3-100982.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:101059.3-101077.6" *)
  reg _48_;
  (* src = "libresoc.v:101078.3-101096.6" *)
  reg _49_;
  (* src = "libresoc.v:101192.3-101210.6" *)
  reg _50_;
  (* src = "libresoc.v:100945.3-100963.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:101230.3-101248.6" *)
  reg _52_;
  (* src = "libresoc.v:101363.3-101381.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:101002.3-101020.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:101154.3-101172.6" *)
  reg _55_;
  (* src = "libresoc.v:101249.3-101267.6" *)
  reg _56_;
  (* src = "libresoc.v:101211.3-101229.6" *)
  reg _57_;
  (* src = "libresoc.v:101135.3-101153.6" *)
  reg _58_;
  (* src = "libresoc.v:100907.3-100925.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:100926.3-100944.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:100812.3-100830.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:100831.3-100849.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:100850.3-100868.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:100888.3-100906.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:100869.3-100887.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:100983.3-101001.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_SV_Etype;
  reg [1:0] dec31_dec_sub19_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_SV_Ptype;
  reg [1:0] dec31_dec_sub19_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub19_asmcode;
  reg [7:0] dec31_dec_sub19_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_br;
  reg dec31_dec_sub19_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_cr_in;
  reg [2:0] dec31_dec_sub19_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_cr_out;
  reg [2:0] dec31_dec_sub19_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_cry_in;
  reg [1:0] dec31_dec_sub19_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_cry_out;
  reg dec31_dec_sub19_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub19_form;
  reg [4:0] dec31_dec_sub19_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub19_function_unit;
  reg [13:0] dec31_dec_sub19_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_in1_sel;
  reg [2:0] dec31_dec_sub19_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub19_in2_sel;
  reg [3:0] dec31_dec_sub19_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_in3_sel;
  reg [1:0] dec31_dec_sub19_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub19_internal_op;
  reg [6:0] dec31_dec_sub19_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_inv_a;
  reg dec31_dec_sub19_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_inv_out;
  reg dec31_dec_sub19_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_is_32b;
  reg dec31_dec_sub19_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub19_ldst_len;
  reg [3:0] dec31_dec_sub19_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_lk;
  reg dec31_dec_sub19_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_out_sel;
  reg [2:0] dec31_dec_sub19_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_rc_sel;
  reg [1:0] dec31_dec_sub19_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_rsrv;
  reg dec31_dec_sub19_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_sgl_pipe;
  reg dec31_dec_sub19_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_sgn;
  reg dec31_dec_sub19_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub19_sgn_ext;
  reg dec31_dec_sub19_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_cr_in;
  reg [2:0] dec31_dec_sub19_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_cr_out;
  reg [2:0] dec31_dec_sub19_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_in1;
  reg [2:0] dec31_dec_sub19_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_in2;
  reg [2:0] dec31_dec_sub19_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_in3;
  reg [2:0] dec31_dec_sub19_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_out;
  reg [2:0] dec31_dec_sub19_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub19_sv_out2;
  reg [2:0] dec31_dec_sub19_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub19_upd;
  reg [1:0] dec31_dec_sub19_upd;
  (* src = "libresoc.v:100407.7-100407.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:100756.5-100756.29" *)
    casez (\initial )
      /* src = "libresoc.v:100756.9-100756.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _43_ = 14'h0400;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _43_ = 14'h0400;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub19_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:100775.5-100775.29" *)
    casez (\initial )
      /* src = "libresoc.v:100775.9-100775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:100794.5-100794.29" *)
    casez (\initial )
      /* src = "libresoc.v:100794.9-100794.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:100813.5-100813.29" *)
    casez (\initial )
      /* src = "libresoc.v:100813.9-100813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:100832.5-100832.29" *)
    casez (\initial )
      /* src = "libresoc.v:100832.9-100832.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:100851.5-100851.29" *)
    casez (\initial )
      /* src = "libresoc.v:100851.9-100851.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:100870.5-100870.29" *)
    casez (\initial )
      /* src = "libresoc.v:100870.9-100870.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:100889.5-100889.29" *)
    casez (\initial )
      /* src = "libresoc.v:100889.9-100889.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:100908.5-100908.29" *)
    casez (\initial )
      /* src = "libresoc.v:100908.9-100908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:100927.5-100927.29" *)
    casez (\initial )
      /* src = "libresoc.v:100927.9-100927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:100946.5-100946.29" *)
    casez (\initial )
      /* src = "libresoc.v:100946.9-100946.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:100965.5-100965.29" *)
    casez (\initial )
      /* src = "libresoc.v:100965.9-100965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h2d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h47;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _47_ = 7'h2e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _47_ = 7'h31;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub19_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:100984.5-100984.29" *)
    casez (\initial )
      /* src = "libresoc.v:100984.9-100984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:101003.5-101003.29" *)
    casez (\initial )
      /* src = "libresoc.v:101003.9-101003.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:101022.5-101022.29" *)
    casez (\initial )
      /* src = "libresoc.v:101022.9-101022.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:101041.5-101041.29" *)
    casez (\initial )
      /* src = "libresoc.v:101041.9-101041.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h6f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h70;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _36_ = 8'h71;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _36_ = 8'h79;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub19_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:101060.5-101060.29" *)
    casez (\initial )
      /* src = "libresoc.v:101060.9-101060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:101079.5-101079.29" *)
    casez (\initial )
      /* src = "libresoc.v:101079.9-101079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:101098.5-101098.29" *)
    casez (\initial )
      /* src = "libresoc.v:101098.9-101098.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:101117.5-101117.29" *)
    casez (\initial )
      /* src = "libresoc.v:101117.9-101117.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:101136.5-101136.29" *)
    casez (\initial )
      /* src = "libresoc.v:101136.9-101136.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:101155.5-101155.29" *)
    casez (\initial )
      /* src = "libresoc.v:101155.9-101155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:101174.5-101174.29" *)
    casez (\initial )
      /* src = "libresoc.v:101174.9-101174.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _42_ = 5'h0a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _42_ = 5'h0a;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub19_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:101193.5-101193.29" *)
    casez (\initial )
      /* src = "libresoc.v:101193.9-101193.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:101212.5-101212.29" *)
    casez (\initial )
      /* src = "libresoc.v:101212.9-101212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:101231.5-101231.29" *)
    casez (\initial )
      /* src = "libresoc.v:101231.9-101231.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:101250.5-101250.29" *)
    casez (\initial )
      /* src = "libresoc.v:101250.9-101250.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:101269.5-101269.29" *)
    casez (\initial )
      /* src = "libresoc.v:101269.9-101269.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:101288.5-101288.29" *)
    casez (\initial )
      /* src = "libresoc.v:101288.9-101288.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:101307.5-101307.29" *)
    casez (\initial )
      /* src = "libresoc.v:101307.9-101307.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _44_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _44_ = 3'h4;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:101326.5-101326.29" *)
    casez (\initial )
      /* src = "libresoc.v:101326.9-101326.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:101345.5-101345.29" *)
    casez (\initial )
      /* src = "libresoc.v:101345.9-101345.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:101364.5-101364.29" *)
    casez (\initial )
      /* src = "libresoc.v:101364.9-101364.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _53_ = 3'h3;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub19_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:101387.1-102562.10" *)
module dec31_dec_sub20(dec31_dec_sub20_function_unit, dec31_dec_sub20_internal_op, dec31_dec_sub20_form, dec31_dec_sub20_asmcode, dec31_dec_sub20_SV_Etype, dec31_dec_sub20_SV_Ptype, dec31_dec_sub20_in1_sel, dec31_dec_sub20_in2_sel, dec31_dec_sub20_in3_sel, dec31_dec_sub20_out_sel, dec31_dec_sub20_cr_in, dec31_dec_sub20_cr_out, dec31_dec_sub20_sv_in1, dec31_dec_sub20_sv_in2, dec31_dec_sub20_sv_in3, dec31_dec_sub20_sv_out, dec31_dec_sub20_sv_out2, dec31_dec_sub20_sv_cr_in, dec31_dec_sub20_sv_cr_out, dec31_dec_sub20_ldst_len, dec31_dec_sub20_upd, dec31_dec_sub20_rc_sel, dec31_dec_sub20_cry_in, dec31_dec_sub20_inv_a, dec31_dec_sub20_inv_out, dec31_dec_sub20_cry_out, dec31_dec_sub20_br, dec31_dec_sub20_sgn_ext, dec31_dec_sub20_rsrv, dec31_dec_sub20_is_32b, dec31_dec_sub20_sgn, dec31_dec_sub20_lk, dec31_dec_sub20_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:102411.3-102435.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:102436.3-102460.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:102111.3-102135.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:102211.3-102235.6" *)
  reg _03_;
  (* src = "libresoc.v:101761.3-101785.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:101786.3-101810.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:102086.3-102110.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:102186.3-102210.6" *)
  reg _07_;
  (* src = "libresoc.v:102286.3-102310.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:101736.3-101760.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:102461.3-102485.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:102486.3-102510.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:102511.3-102535.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:102011.3-102035.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:102136.3-102160.6" *)
  reg _14_;
  (* src = "libresoc.v:102161.3-102185.6" *)
  reg _15_;
  (* src = "libresoc.v:102311.3-102335.6" *)
  reg _16_;
  (* src = "libresoc.v:101986.3-102010.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:102361.3-102385.6" *)
  reg _18_;
  (* src = "libresoc.v:102536.3-102560.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:102061.3-102085.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:102261.3-102285.6" *)
  reg _21_;
  (* src = "libresoc.v:102386.3-102410.6" *)
  reg _22_;
  (* src = "libresoc.v:102336.3-102360.6" *)
  reg _23_;
  (* src = "libresoc.v:102236.3-102260.6" *)
  reg _24_;
  (* src = "libresoc.v:101936.3-101960.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:101961.3-101985.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:101811.3-101835.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:101836.3-101860.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:101861.3-101885.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:101911.3-101935.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:101886.3-101910.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:102036.3-102060.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:101388.7-101388.20" *)
  reg _33_;
  (* src = "libresoc.v:102411.3-102435.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:102436.3-102460.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:102111.3-102135.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:102211.3-102235.6" *)
  reg _37_;
  (* src = "libresoc.v:101761.3-101785.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:101786.3-101810.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:102086.3-102110.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:102186.3-102210.6" *)
  reg _41_;
  (* src = "libresoc.v:102286.3-102310.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:101736.3-101760.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:102461.3-102485.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:102486.3-102510.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:102511.3-102535.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:102011.3-102035.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:102136.3-102160.6" *)
  reg _48_;
  (* src = "libresoc.v:102161.3-102185.6" *)
  reg _49_;
  (* src = "libresoc.v:102311.3-102335.6" *)
  reg _50_;
  (* src = "libresoc.v:101986.3-102010.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:102361.3-102385.6" *)
  reg _52_;
  (* src = "libresoc.v:102536.3-102560.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:102061.3-102085.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:102261.3-102285.6" *)
  reg _55_;
  (* src = "libresoc.v:102386.3-102410.6" *)
  reg _56_;
  (* src = "libresoc.v:102336.3-102360.6" *)
  reg _57_;
  (* src = "libresoc.v:102236.3-102260.6" *)
  reg _58_;
  (* src = "libresoc.v:101936.3-101960.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:101961.3-101985.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:101811.3-101835.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:101836.3-101860.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:101861.3-101885.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:101911.3-101935.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:101886.3-101910.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:102036.3-102060.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_SV_Etype;
  reg [1:0] dec31_dec_sub20_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_SV_Ptype;
  reg [1:0] dec31_dec_sub20_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub20_asmcode;
  reg [7:0] dec31_dec_sub20_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_br;
  reg dec31_dec_sub20_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_cr_in;
  reg [2:0] dec31_dec_sub20_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_cr_out;
  reg [2:0] dec31_dec_sub20_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_cry_in;
  reg [1:0] dec31_dec_sub20_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_cry_out;
  reg dec31_dec_sub20_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub20_form;
  reg [4:0] dec31_dec_sub20_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub20_function_unit;
  reg [13:0] dec31_dec_sub20_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_in1_sel;
  reg [2:0] dec31_dec_sub20_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub20_in2_sel;
  reg [3:0] dec31_dec_sub20_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_in3_sel;
  reg [1:0] dec31_dec_sub20_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub20_internal_op;
  reg [6:0] dec31_dec_sub20_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_inv_a;
  reg dec31_dec_sub20_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_inv_out;
  reg dec31_dec_sub20_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_is_32b;
  reg dec31_dec_sub20_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub20_ldst_len;
  reg [3:0] dec31_dec_sub20_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_lk;
  reg dec31_dec_sub20_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_out_sel;
  reg [2:0] dec31_dec_sub20_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_rc_sel;
  reg [1:0] dec31_dec_sub20_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_rsrv;
  reg dec31_dec_sub20_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_sgl_pipe;
  reg dec31_dec_sub20_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_sgn;
  reg dec31_dec_sub20_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub20_sgn_ext;
  reg dec31_dec_sub20_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_cr_in;
  reg [2:0] dec31_dec_sub20_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_cr_out;
  reg [2:0] dec31_dec_sub20_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_in1;
  reg [2:0] dec31_dec_sub20_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_in2;
  reg [2:0] dec31_dec_sub20_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_in3;
  reg [2:0] dec31_dec_sub20_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_out;
  reg [2:0] dec31_dec_sub20_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub20_sv_out2;
  reg [2:0] dec31_dec_sub20_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub20_upd;
  reg [1:0] dec31_dec_sub20_upd;
  (* src = "libresoc.v:101388.7-101388.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:101737.5-101737.29" *)
    casez (\initial )
      /* src = "libresoc.v:101737.9-101737.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = 14'h0004;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub20_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:101762.5-101762.29" *)
    casez (\initial )
      /* src = "libresoc.v:101762.9-101762.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:101787.5-101787.29" *)
    casez (\initial )
      /* src = "libresoc.v:101787.9-101787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:101812.5-101812.29" *)
    casez (\initial )
      /* src = "libresoc.v:101812.9-101812.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:101837.5-101837.29" *)
    casez (\initial )
      /* src = "libresoc.v:101837.9-101837.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:101862.5-101862.29" *)
    casez (\initial )
      /* src = "libresoc.v:101862.9-101862.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = 3'h1;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:101887.5-101887.29" *)
    casez (\initial )
      /* src = "libresoc.v:101887.9-101887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:101912.5-101912.29" *)
    casez (\initial )
      /* src = "libresoc.v:101912.9-101912.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:101937.5-101937.29" *)
    casez (\initial )
      /* src = "libresoc.v:101937.9-101937.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:101962.5-101962.29" *)
    casez (\initial )
      /* src = "libresoc.v:101962.9-101962.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:101987.5-101987.29" *)
    casez (\initial )
      /* src = "libresoc.v:101987.9-101987.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = 4'h8;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:102012.5-102012.29" *)
    casez (\initial )
      /* src = "libresoc.v:102012.9-102012.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = 7'h26;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub20_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:102037.5-102037.29" *)
    casez (\initial )
      /* src = "libresoc.v:102037.9-102037.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:102062.5-102062.29" *)
    casez (\initial )
      /* src = "libresoc.v:102062.9-102062.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:102087.5-102087.29" *)
    casez (\initial )
      /* src = "libresoc.v:102087.9-102087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:102112.5-102112.29" *)
    casez (\initial )
      /* src = "libresoc.v:102112.9-102112.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h4d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h53;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h54;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h59;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h63;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = 8'hae;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub20_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:102137.5-102137.29" *)
    casez (\initial )
      /* src = "libresoc.v:102137.9-102137.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:102162.5-102162.29" *)
    casez (\initial )
      /* src = "libresoc.v:102162.9-102162.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:102187.5-102187.29" *)
    casez (\initial )
      /* src = "libresoc.v:102187.9-102187.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:102212.5-102212.29" *)
    casez (\initial )
      /* src = "libresoc.v:102212.9-102212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = 1'h1;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:102237.5-102237.29" *)
    casez (\initial )
      /* src = "libresoc.v:102237.9-102237.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:102262.5-102262.29" *)
    casez (\initial )
      /* src = "libresoc.v:102262.9-102262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:102287.5-102287.29" *)
    casez (\initial )
      /* src = "libresoc.v:102287.9-102287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub20_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:102312.5-102312.29" *)
    casez (\initial )
      /* src = "libresoc.v:102312.9-102312.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:102337.5-102337.29" *)
    casez (\initial )
      /* src = "libresoc.v:102337.9-102337.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:102362.5-102362.29" *)
    casez (\initial )
      /* src = "libresoc.v:102362.9-102362.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:102387.5-102387.29" *)
    casez (\initial )
      /* src = "libresoc.v:102387.9-102387.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:102412.5-102412.29" *)
    casez (\initial )
      /* src = "libresoc.v:102412.9-102412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:102437.5-102437.29" *)
    casez (\initial )
      /* src = "libresoc.v:102437.9-102437.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:102462.5-102462.29" *)
    casez (\initial )
      /* src = "libresoc.v:102462.9-102462.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:102487.5-102487.29" *)
    casez (\initial )
      /* src = "libresoc.v:102487.9-102487.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:102512.5-102512.29" *)
    casez (\initial )
      /* src = "libresoc.v:102512.9-102512.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:102537.5-102537.29" *)
    casez (\initial )
      /* src = "libresoc.v:102537.9-102537.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub20_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:102566.1-104527.10" *)
module dec31_dec_sub21(dec31_dec_sub21_function_unit, dec31_dec_sub21_internal_op, dec31_dec_sub21_form, dec31_dec_sub21_asmcode, dec31_dec_sub21_SV_Etype, dec31_dec_sub21_SV_Ptype, dec31_dec_sub21_in1_sel, dec31_dec_sub21_in2_sel, dec31_dec_sub21_in3_sel, dec31_dec_sub21_out_sel, dec31_dec_sub21_cr_in, dec31_dec_sub21_cr_out, dec31_dec_sub21_sv_in1, dec31_dec_sub21_sv_in2, dec31_dec_sub21_sv_in3, dec31_dec_sub21_sv_out, dec31_dec_sub21_sv_out2, dec31_dec_sub21_sv_cr_in, dec31_dec_sub21_sv_cr_out, dec31_dec_sub21_ldst_len, dec31_dec_sub21_upd, dec31_dec_sub21_rc_sel, dec31_dec_sub21_cry_in, dec31_dec_sub21_inv_a, dec31_dec_sub21_inv_out, dec31_dec_sub21_cry_out, dec31_dec_sub21_br, dec31_dec_sub21_sgn_ext, dec31_dec_sub21_rsrv, dec31_dec_sub21_is_32b, dec31_dec_sub21_sgn, dec31_dec_sub21_lk, dec31_dec_sub21_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:104232.3-104280.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:104281.3-104329.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:104189.3-104231.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:103797.3-103845.6" *)
  reg _03_;
  (* src = "libresoc.v:102964.3-103012.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:103013.3-103061.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:103601.3-103649.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:103748.3-103796.6" *)
  reg _07_;
  (* src = "libresoc.v:103993.3-104041.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:102915.3-102963.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:104330.3-104378.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:104379.3-104427.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:104428.3-104476.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:103454.3-103502.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:103650.3-103698.6" *)
  reg _14_;
  (* src = "libresoc.v:103699.3-103747.6" *)
  reg _15_;
  (* src = "libresoc.v:103944.3-103992.6" *)
  reg _16_;
  (* src = "libresoc.v:103405.3-103453.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:104091.3-104139.6" *)
  reg _18_;
  (* src = "libresoc.v:104477.3-104525.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:103552.3-103600.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:103895.3-103943.6" *)
  reg _21_;
  (* src = "libresoc.v:104140.3-104188.6" *)
  reg _22_;
  (* src = "libresoc.v:104042.3-104090.6" *)
  reg _23_;
  (* src = "libresoc.v:103846.3-103894.6" *)
  reg _24_;
  (* src = "libresoc.v:103307.3-103355.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:103356.3-103404.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:103062.3-103110.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:103111.3-103159.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:103160.3-103208.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:103258.3-103306.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:103209.3-103257.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:103503.3-103551.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:102567.7-102567.20" *)
  reg _33_;
  (* src = "libresoc.v:104232.3-104280.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:104281.3-104329.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:104189.3-104231.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:103797.3-103845.6" *)
  reg _37_;
  (* src = "libresoc.v:102964.3-103012.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:103013.3-103061.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:103601.3-103649.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:103748.3-103796.6" *)
  reg _41_;
  (* src = "libresoc.v:103993.3-104041.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:102915.3-102963.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:104330.3-104378.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:104379.3-104427.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:104428.3-104476.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:103454.3-103502.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:103650.3-103698.6" *)
  reg _48_;
  (* src = "libresoc.v:103699.3-103747.6" *)
  reg _49_;
  (* src = "libresoc.v:103944.3-103992.6" *)
  reg _50_;
  (* src = "libresoc.v:103405.3-103453.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:104091.3-104139.6" *)
  reg _52_;
  (* src = "libresoc.v:104477.3-104525.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:103552.3-103600.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:103895.3-103943.6" *)
  reg _55_;
  (* src = "libresoc.v:104140.3-104188.6" *)
  reg _56_;
  (* src = "libresoc.v:104042.3-104090.6" *)
  reg _57_;
  (* src = "libresoc.v:103846.3-103894.6" *)
  reg _58_;
  (* src = "libresoc.v:103307.3-103355.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:103356.3-103404.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:103062.3-103110.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:103111.3-103159.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:103160.3-103208.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:103258.3-103306.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:103209.3-103257.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:103503.3-103551.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_SV_Etype;
  reg [1:0] dec31_dec_sub21_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_SV_Ptype;
  reg [1:0] dec31_dec_sub21_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub21_asmcode;
  reg [7:0] dec31_dec_sub21_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_br;
  reg dec31_dec_sub21_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_cr_in;
  reg [2:0] dec31_dec_sub21_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_cr_out;
  reg [2:0] dec31_dec_sub21_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_cry_in;
  reg [1:0] dec31_dec_sub21_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_cry_out;
  reg dec31_dec_sub21_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub21_form;
  reg [4:0] dec31_dec_sub21_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub21_function_unit;
  reg [13:0] dec31_dec_sub21_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_in1_sel;
  reg [2:0] dec31_dec_sub21_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub21_in2_sel;
  reg [3:0] dec31_dec_sub21_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_in3_sel;
  reg [1:0] dec31_dec_sub21_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub21_internal_op;
  reg [6:0] dec31_dec_sub21_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_inv_a;
  reg dec31_dec_sub21_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_inv_out;
  reg dec31_dec_sub21_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_is_32b;
  reg dec31_dec_sub21_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub21_ldst_len;
  reg [3:0] dec31_dec_sub21_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_lk;
  reg dec31_dec_sub21_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_out_sel;
  reg [2:0] dec31_dec_sub21_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_rc_sel;
  reg [1:0] dec31_dec_sub21_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_rsrv;
  reg dec31_dec_sub21_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_sgl_pipe;
  reg dec31_dec_sub21_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_sgn;
  reg dec31_dec_sub21_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub21_sgn_ext;
  reg dec31_dec_sub21_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_cr_in;
  reg [2:0] dec31_dec_sub21_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_cr_out;
  reg [2:0] dec31_dec_sub21_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_in1;
  reg [2:0] dec31_dec_sub21_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_in2;
  reg [2:0] dec31_dec_sub21_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_in3;
  reg [2:0] dec31_dec_sub21_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_out;
  reg [2:0] dec31_dec_sub21_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub21_sv_out2;
  reg [2:0] dec31_dec_sub21_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub21_upd;
  reg [1:0] dec31_dec_sub21_upd;
  (* src = "libresoc.v:102567.7-102567.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:102916.5-102916.29" *)
    casez (\initial )
      /* src = "libresoc.v:102916.9-102916.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0004;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub21_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:102965.5-102965.29" *)
    casez (\initial )
      /* src = "libresoc.v:102965.9-102965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:103014.5-103014.29" *)
    casez (\initial )
      /* src = "libresoc.v:103014.9-103014.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:103063.5-103063.29" *)
    casez (\initial )
      /* src = "libresoc.v:103063.9-103063.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:103112.5-103112.29" *)
    casez (\initial )
      /* src = "libresoc.v:103112.9-103112.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:103161.5-103161.29" *)
    casez (\initial )
      /* src = "libresoc.v:103161.9-103161.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h1;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:103210.5-103210.29" *)
    casez (\initial )
      /* src = "libresoc.v:103210.9-103210.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:103259.5-103259.29" *)
    casez (\initial )
      /* src = "libresoc.v:103259.9-103259.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _64_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:103308.5-103308.29" *)
    casez (\initial )
      /* src = "libresoc.v:103308.9-103308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:103357.5-103357.29" *)
    casez (\initial )
      /* src = "libresoc.v:103357.9-103357.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:103406.5-103406.29" *)
    casez (\initial )
      /* src = "libresoc.v:103406.9-103406.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h4;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:103455.5-103455.29" *)
    casez (\initial )
      /* src = "libresoc.v:103455.9-103455.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h26;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub21_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:103504.5-103504.29" *)
    casez (\initial )
      /* src = "libresoc.v:103504.9-103504.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _66_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h2;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:103553.5-103553.29" *)
    casez (\initial )
      /* src = "libresoc.v:103553.9-103553.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:103602.5-103602.29" *)
    casez (\initial )
      /* src = "libresoc.v:103602.9-103602.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:103651.5-103651.29" *)
    casez (\initial )
      /* src = "libresoc.v:103651.9-103651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:103700.5-103700.29" *)
    casez (\initial )
      /* src = "libresoc.v:103700.9-103700.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:103749.5-103749.29" *)
    casez (\initial )
      /* src = "libresoc.v:103749.9-103749.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:103798.5-103798.29" *)
    casez (\initial )
      /* src = "libresoc.v:103798.9-103798.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:103847.5-103847.29" *)
    casez (\initial )
      /* src = "libresoc.v:103847.9-103847.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _58_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _58_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:103896.5-103896.29" *)
    casez (\initial )
      /* src = "libresoc.v:103896.9-103896.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:103945.5-103945.29" *)
    casez (\initial )
      /* src = "libresoc.v:103945.9-103945.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:103994.5-103994.29" *)
    casez (\initial )
      /* src = "libresoc.v:103994.9-103994.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub21_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:104043.5-104043.29" *)
    casez (\initial )
      /* src = "libresoc.v:104043.9-104043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:104092.5-104092.29" *)
    casez (\initial )
      /* src = "libresoc.v:104092.9-104092.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:104141.5-104141.29" *)
    casez (\initial )
      /* src = "libresoc.v:104141.9-104141.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:104190.5-104190.29" *)
    casez (\initial )
      /* src = "libresoc.v:104190.9-104190.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
          _36_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
          _36_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h56;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h57;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
          _36_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _36_ = 8'h64;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _36_ = 8'h65;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h68;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'ha8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
          _36_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _36_ = 8'hb1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'hb2;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub21_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:104233.5-104233.29" *)
    casez (\initial )
      /* src = "libresoc.v:104233.9-104233.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:104282.5-104282.29" *)
    casez (\initial )
      /* src = "libresoc.v:104282.9-104282.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:104331.5-104331.29" *)
    casez (\initial )
      /* src = "libresoc.v:104331.9-104331.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:104380.5-104380.29" *)
    casez (\initial )
      /* src = "libresoc.v:104380.9-104380.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:104429.5-104429.29" *)
    casez (\initial )
      /* src = "libresoc.v:104429.9-104429.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:104478.5-104478.29" *)
    casez (\initial )
      /* src = "libresoc.v:104478.9-104478.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub21_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:104531.1-106696.10" *)
module dec31_dec_sub22(dec31_dec_sub22_function_unit, dec31_dec_sub22_internal_op, dec31_dec_sub22_form, dec31_dec_sub22_asmcode, dec31_dec_sub22_SV_Etype, dec31_dec_sub22_SV_Ptype, dec31_dec_sub22_in1_sel, dec31_dec_sub22_in2_sel, dec31_dec_sub22_in3_sel, dec31_dec_sub22_out_sel, dec31_dec_sub22_cr_in, dec31_dec_sub22_cr_out, dec31_dec_sub22_sv_in1, dec31_dec_sub22_sv_in2, dec31_dec_sub22_sv_in3, dec31_dec_sub22_sv_out, dec31_dec_sub22_sv_out2, dec31_dec_sub22_sv_cr_in, dec31_dec_sub22_sv_cr_out, dec31_dec_sub22_ldst_len, dec31_dec_sub22_upd, dec31_dec_sub22_rc_sel, dec31_dec_sub22_cry_in, dec31_dec_sub22_inv_a, dec31_dec_sub22_inv_out, dec31_dec_sub22_cry_out, dec31_dec_sub22_br, dec31_dec_sub22_sgn_ext, dec31_dec_sub22_rsrv, dec31_dec_sub22_is_32b, dec31_dec_sub22_sgn, dec31_dec_sub22_lk, dec31_dec_sub22_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:106365.3-106419.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:106420.3-106474.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:105705.3-105759.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:105925.3-105979.6" *)
  reg _03_;
  (* src = "libresoc.v:104935.3-104989.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:104990.3-105044.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:105650.3-105704.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:105870.3-105924.6" *)
  reg _07_;
  (* src = "libresoc.v:106090.3-106144.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:104880.3-104934.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:106475.3-106529.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:106530.3-106584.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:106585.3-106639.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:105485.3-105539.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:105760.3-105814.6" *)
  reg _14_;
  (* src = "libresoc.v:105815.3-105869.6" *)
  reg _15_;
  (* src = "libresoc.v:106145.3-106199.6" *)
  reg _16_;
  (* src = "libresoc.v:105430.3-105484.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:106255.3-106309.6" *)
  reg _18_;
  (* src = "libresoc.v:106640.3-106694.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:105595.3-105649.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:106035.3-106089.6" *)
  reg _21_;
  (* src = "libresoc.v:106310.3-106364.6" *)
  reg _22_;
  (* src = "libresoc.v:106200.3-106254.6" *)
  reg _23_;
  (* src = "libresoc.v:105980.3-106034.6" *)
  reg _24_;
  (* src = "libresoc.v:105320.3-105374.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:105375.3-105429.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:105045.3-105099.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:105100.3-105154.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:105155.3-105209.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:105265.3-105319.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:105210.3-105264.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:105540.3-105594.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:104532.7-104532.20" *)
  reg _33_;
  (* src = "libresoc.v:106365.3-106419.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:106420.3-106474.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:105705.3-105759.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:105925.3-105979.6" *)
  reg _37_;
  (* src = "libresoc.v:104935.3-104989.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:104990.3-105044.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:105650.3-105704.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:105870.3-105924.6" *)
  reg _41_;
  (* src = "libresoc.v:106090.3-106144.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:104880.3-104934.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:106475.3-106529.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:106530.3-106584.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:106585.3-106639.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:105485.3-105539.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:105760.3-105814.6" *)
  reg _48_;
  (* src = "libresoc.v:105815.3-105869.6" *)
  reg _49_;
  (* src = "libresoc.v:106145.3-106199.6" *)
  reg _50_;
  (* src = "libresoc.v:105430.3-105484.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:106255.3-106309.6" *)
  reg _52_;
  (* src = "libresoc.v:106640.3-106694.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:105595.3-105649.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:106035.3-106089.6" *)
  reg _55_;
  (* src = "libresoc.v:106310.3-106364.6" *)
  reg _56_;
  (* src = "libresoc.v:106200.3-106254.6" *)
  reg _57_;
  (* src = "libresoc.v:105980.3-106034.6" *)
  reg _58_;
  (* src = "libresoc.v:105320.3-105374.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:105375.3-105429.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:105045.3-105099.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:105100.3-105154.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:105155.3-105209.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:105265.3-105319.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:105210.3-105264.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:105540.3-105594.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_SV_Etype;
  reg [1:0] dec31_dec_sub22_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_SV_Ptype;
  reg [1:0] dec31_dec_sub22_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub22_asmcode;
  reg [7:0] dec31_dec_sub22_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_br;
  reg dec31_dec_sub22_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_cr_in;
  reg [2:0] dec31_dec_sub22_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_cr_out;
  reg [2:0] dec31_dec_sub22_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_cry_in;
  reg [1:0] dec31_dec_sub22_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_cry_out;
  reg dec31_dec_sub22_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub22_form;
  reg [4:0] dec31_dec_sub22_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub22_function_unit;
  reg [13:0] dec31_dec_sub22_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_in1_sel;
  reg [2:0] dec31_dec_sub22_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub22_in2_sel;
  reg [3:0] dec31_dec_sub22_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_in3_sel;
  reg [1:0] dec31_dec_sub22_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub22_internal_op;
  reg [6:0] dec31_dec_sub22_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_inv_a;
  reg dec31_dec_sub22_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_inv_out;
  reg dec31_dec_sub22_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_is_32b;
  reg dec31_dec_sub22_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub22_ldst_len;
  reg [3:0] dec31_dec_sub22_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_lk;
  reg dec31_dec_sub22_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_out_sel;
  reg [2:0] dec31_dec_sub22_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_rc_sel;
  reg [1:0] dec31_dec_sub22_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_rsrv;
  reg dec31_dec_sub22_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_sgl_pipe;
  reg dec31_dec_sub22_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_sgn;
  reg dec31_dec_sub22_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub22_sgn_ext;
  reg dec31_dec_sub22_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_cr_in;
  reg [2:0] dec31_dec_sub22_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_cr_out;
  reg [2:0] dec31_dec_sub22_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_in1;
  reg [2:0] dec31_dec_sub22_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_in2;
  reg [2:0] dec31_dec_sub22_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_in3;
  reg [2:0] dec31_dec_sub22_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_out;
  reg [2:0] dec31_dec_sub22_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub22_sv_out2;
  reg [2:0] dec31_dec_sub22_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub22_upd;
  reg [1:0] dec31_dec_sub22_upd;
  (* src = "libresoc.v:104532.7-104532.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:104881.5-104881.29" *)
    casez (\initial )
      /* src = "libresoc.v:104881.9-104881.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _43_ = 14'h0800;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _43_ = 14'h0002;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub22_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:104936.5-104936.29" *)
    casez (\initial )
      /* src = "libresoc.v:104936.9-104936.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:104991.5-104991.29" *)
    casez (\initial )
      /* src = "libresoc.v:104991.9-104991.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:105046.5-105046.29" *)
    casez (\initial )
      /* src = "libresoc.v:105046.9-105046.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:105101.5-105101.29" *)
    casez (\initial )
      /* src = "libresoc.v:105101.9-105101.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:105156.5-105156.29" *)
    casez (\initial )
      /* src = "libresoc.v:105156.9-105156.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:105211.5-105211.29" *)
    casez (\initial )
      /* src = "libresoc.v:105211.9-105211.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:105266.5-105266.29" *)
    casez (\initial )
      /* src = "libresoc.v:105266.9-105266.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:105321.5-105321.29" *)
    casez (\initial )
      /* src = "libresoc.v:105321.9-105321.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:105376.5-105376.29" *)
    casez (\initial )
      /* src = "libresoc.v:105376.9-105376.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:105431.5-105431.29" *)
    casez (\initial )
      /* src = "libresoc.v:105431.9-105431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:105486.5-105486.29" *)
    casez (\initial )
      /* src = "libresoc.v:105486.9-105486.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _47_ = 7'h1c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h21;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h01;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _47_ = 7'h01;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub22_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:105541.5-105541.29" *)
    casez (\initial )
      /* src = "libresoc.v:105541.9-105541.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:105596.5-105596.29" *)
    casez (\initial )
      /* src = "libresoc.v:105596.9-105596.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _54_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _54_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _54_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:105651.5-105651.29" *)
    casez (\initial )
      /* src = "libresoc.v:105651.9-105651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:105706.5-105706.29" *)
    casez (\initial )
      /* src = "libresoc.v:105706.9-105706.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h2e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h30;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h31;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _36_ = 8'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'h49;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h4a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h5d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h66;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _36_ = 8'ha9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _36_ = 8'haf;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = 8'hb4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _36_ = 8'hb5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = 8'hba;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'hbb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _36_ = 8'hca;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub22_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:105761.5-105761.29" *)
    casez (\initial )
      /* src = "libresoc.v:105761.9-105761.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:105816.5-105816.29" *)
    casez (\initial )
      /* src = "libresoc.v:105816.9-105816.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:105871.5-105871.29" *)
    casez (\initial )
      /* src = "libresoc.v:105871.9-105871.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:105926.5-105926.29" *)
    casez (\initial )
      /* src = "libresoc.v:105926.9-105926.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:105981.5-105981.29" *)
    casez (\initial )
      /* src = "libresoc.v:105981.9-105981.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:106036.5-106036.29" *)
    casez (\initial )
      /* src = "libresoc.v:106036.9-106036.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:106091.5-106091.29" *)
    casez (\initial )
      /* src = "libresoc.v:106091.9-106091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub22_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:106146.5-106146.29" *)
    casez (\initial )
      /* src = "libresoc.v:106146.9-106146.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:106201.5-106201.29" *)
    casez (\initial )
      /* src = "libresoc.v:106201.9-106201.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:106256.5-106256.29" *)
    casez (\initial )
      /* src = "libresoc.v:106256.9-106256.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:106311.5-106311.29" *)
    casez (\initial )
      /* src = "libresoc.v:106311.9-106311.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:106366.5-106366.29" *)
    casez (\initial )
      /* src = "libresoc.v:106366.9-106366.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _34_ = 2'h0;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:106421.5-106421.29" *)
    casez (\initial )
      /* src = "libresoc.v:106421.9-106421.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _35_ = 2'h0;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:106476.5-106476.29" *)
    casez (\initial )
      /* src = "libresoc.v:106476.9-106476.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:106531.5-106531.29" *)
    casez (\initial )
      /* src = "libresoc.v:106531.9-106531.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:106586.5-106586.29" *)
    casez (\initial )
      /* src = "libresoc.v:106586.9-106586.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:106641.5-106641.29" *)
    casez (\initial )
      /* src = "libresoc.v:106641.9-106641.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h15:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub22_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:106700.1-108667.10" *)
module dec31_dec_sub23(dec31_dec_sub23_function_unit, dec31_dec_sub23_internal_op, dec31_dec_sub23_form, dec31_dec_sub23_asmcode, dec31_dec_sub23_SV_Etype, dec31_dec_sub23_SV_Ptype, dec31_dec_sub23_in1_sel, dec31_dec_sub23_in2_sel, dec31_dec_sub23_in3_sel, dec31_dec_sub23_out_sel, dec31_dec_sub23_cr_in, dec31_dec_sub23_cr_out, dec31_dec_sub23_sv_in1, dec31_dec_sub23_sv_in2, dec31_dec_sub23_sv_in3, dec31_dec_sub23_sv_out, dec31_dec_sub23_sv_out2, dec31_dec_sub23_sv_cr_in, dec31_dec_sub23_sv_cr_out, dec31_dec_sub23_ldst_len, dec31_dec_sub23_upd, dec31_dec_sub23_rc_sel, dec31_dec_sub23_cry_in, dec31_dec_sub23_inv_a, dec31_dec_sub23_inv_out, dec31_dec_sub23_cry_out, dec31_dec_sub23_br, dec31_dec_sub23_sgn_ext, dec31_dec_sub23_rsrv, dec31_dec_sub23_is_32b, dec31_dec_sub23_sgn, dec31_dec_sub23_lk, dec31_dec_sub23_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:108372.3-108420.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:108421.3-108469.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:107784.3-107832.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:107980.3-108028.6" *)
  reg _03_;
  (* src = "libresoc.v:107098.3-107146.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:107147.3-107195.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:107735.3-107783.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:107931.3-107979.6" *)
  reg _07_;
  (* src = "libresoc.v:108127.3-108175.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:107049.3-107097.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:108470.3-108518.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:108519.3-108567.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:108568.3-108616.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:107588.3-107636.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:107833.3-107881.6" *)
  reg _14_;
  (* src = "libresoc.v:107882.3-107930.6" *)
  reg _15_;
  (* src = "libresoc.v:108176.3-108224.6" *)
  reg _16_;
  (* src = "libresoc.v:107539.3-107587.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:108274.3-108322.6" *)
  reg _18_;
  (* src = "libresoc.v:108617.3-108665.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:107686.3-107734.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:108078.3-108126.6" *)
  reg _21_;
  (* src = "libresoc.v:108323.3-108371.6" *)
  reg _22_;
  (* src = "libresoc.v:108225.3-108273.6" *)
  reg _23_;
  (* src = "libresoc.v:108029.3-108077.6" *)
  reg _24_;
  (* src = "libresoc.v:107441.3-107489.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:107490.3-107538.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:107196.3-107244.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:107245.3-107293.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:107294.3-107342.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:107392.3-107440.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:107343.3-107391.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:107637.3-107685.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:106701.7-106701.20" *)
  reg _33_;
  (* src = "libresoc.v:108372.3-108420.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:108421.3-108469.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:107784.3-107832.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:107980.3-108028.6" *)
  reg _37_;
  (* src = "libresoc.v:107098.3-107146.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:107147.3-107195.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:107735.3-107783.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:107931.3-107979.6" *)
  reg _41_;
  (* src = "libresoc.v:108127.3-108175.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:107049.3-107097.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:108470.3-108518.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:108519.3-108567.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:108568.3-108616.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:107588.3-107636.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:107833.3-107881.6" *)
  reg _48_;
  (* src = "libresoc.v:107882.3-107930.6" *)
  reg _49_;
  (* src = "libresoc.v:108176.3-108224.6" *)
  reg _50_;
  (* src = "libresoc.v:107539.3-107587.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:108274.3-108322.6" *)
  reg _52_;
  (* src = "libresoc.v:108617.3-108665.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:107686.3-107734.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:108078.3-108126.6" *)
  reg _55_;
  (* src = "libresoc.v:108323.3-108371.6" *)
  reg _56_;
  (* src = "libresoc.v:108225.3-108273.6" *)
  reg _57_;
  (* src = "libresoc.v:108029.3-108077.6" *)
  reg _58_;
  (* src = "libresoc.v:107441.3-107489.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:107490.3-107538.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:107196.3-107244.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:107245.3-107293.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:107294.3-107342.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:107392.3-107440.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:107343.3-107391.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:107637.3-107685.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_SV_Etype;
  reg [1:0] dec31_dec_sub23_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_SV_Ptype;
  reg [1:0] dec31_dec_sub23_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub23_asmcode;
  reg [7:0] dec31_dec_sub23_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_br;
  reg dec31_dec_sub23_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_cr_in;
  reg [2:0] dec31_dec_sub23_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_cr_out;
  reg [2:0] dec31_dec_sub23_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_cry_in;
  reg [1:0] dec31_dec_sub23_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_cry_out;
  reg dec31_dec_sub23_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub23_form;
  reg [4:0] dec31_dec_sub23_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub23_function_unit;
  reg [13:0] dec31_dec_sub23_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_in1_sel;
  reg [2:0] dec31_dec_sub23_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub23_in2_sel;
  reg [3:0] dec31_dec_sub23_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_in3_sel;
  reg [1:0] dec31_dec_sub23_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub23_internal_op;
  reg [6:0] dec31_dec_sub23_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_inv_a;
  reg dec31_dec_sub23_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_inv_out;
  reg dec31_dec_sub23_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_is_32b;
  reg dec31_dec_sub23_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub23_ldst_len;
  reg [3:0] dec31_dec_sub23_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_lk;
  reg dec31_dec_sub23_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_out_sel;
  reg [2:0] dec31_dec_sub23_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_rc_sel;
  reg [1:0] dec31_dec_sub23_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_rsrv;
  reg dec31_dec_sub23_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_sgl_pipe;
  reg dec31_dec_sub23_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_sgn;
  reg dec31_dec_sub23_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub23_sgn_ext;
  reg dec31_dec_sub23_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_cr_in;
  reg [2:0] dec31_dec_sub23_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_cr_out;
  reg [2:0] dec31_dec_sub23_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_in1;
  reg [2:0] dec31_dec_sub23_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_in2;
  reg [2:0] dec31_dec_sub23_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_in3;
  reg [2:0] dec31_dec_sub23_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_out;
  reg [2:0] dec31_dec_sub23_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub23_sv_out2;
  reg [2:0] dec31_dec_sub23_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub23_upd;
  reg [1:0] dec31_dec_sub23_upd;
  (* src = "libresoc.v:106701.7-106701.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:107050.5-107050.29" *)
    casez (\initial )
      /* src = "libresoc.v:107050.9-107050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0004;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub23_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:107099.5-107099.29" *)
    casez (\initial )
      /* src = "libresoc.v:107099.9-107099.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:107148.5-107148.29" *)
    casez (\initial )
      /* src = "libresoc.v:107148.9-107148.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:107197.5-107197.29" *)
    casez (\initial )
      /* src = "libresoc.v:107197.9-107197.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:107246.5-107246.29" *)
    casez (\initial )
      /* src = "libresoc.v:107246.9-107246.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:107295.5-107295.29" *)
    casez (\initial )
      /* src = "libresoc.v:107295.9-107295.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h1;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:107344.5-107344.29" *)
    casez (\initial )
      /* src = "libresoc.v:107344.9-107344.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:107393.5-107393.29" *)
    casez (\initial )
      /* src = "libresoc.v:107393.9-107393.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _64_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _64_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:107442.5-107442.29" *)
    casez (\initial )
      /* src = "libresoc.v:107442.9-107442.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:107491.5-107491.29" *)
    casez (\initial )
      /* src = "libresoc.v:107491.9-107491.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:107540.5-107540.29" *)
    casez (\initial )
      /* src = "libresoc.v:107540.9-107540.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h4;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:107589.5-107589.29" *)
    casez (\initial )
      /* src = "libresoc.v:107589.9-107589.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h26;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub23_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:107638.5-107638.29" *)
    casez (\initial )
      /* src = "libresoc.v:107638.9-107638.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:107687.5-107687.29" *)
    casez (\initial )
      /* src = "libresoc.v:107687.9-107687.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:107736.5-107736.29" *)
    casez (\initial )
      /* src = "libresoc.v:107736.9-107736.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:107785.5-107785.29" *)
    casez (\initial )
      /* src = "libresoc.v:107785.9-107785.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h50;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h51;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _36_ = 8'h5b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _36_ = 8'h5c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _36_ = 8'h60;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h61;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h6a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h6b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'hab;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _36_ = 8'hac;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _36_ = 8'hb7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _36_ = 8'hb8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _36_ = 8'hbd;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'hbe;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub23_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:107834.5-107834.29" *)
    casez (\initial )
      /* src = "libresoc.v:107834.9-107834.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:107883.5-107883.29" *)
    casez (\initial )
      /* src = "libresoc.v:107883.9-107883.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:107932.5-107932.29" *)
    casez (\initial )
      /* src = "libresoc.v:107932.9-107932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:107981.5-107981.29" *)
    casez (\initial )
      /* src = "libresoc.v:107981.9-107981.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:108030.5-108030.29" *)
    casez (\initial )
      /* src = "libresoc.v:108030.9-108030.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _58_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _58_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:108079.5-108079.29" *)
    casez (\initial )
      /* src = "libresoc.v:108079.9-108079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:108128.5-108128.29" *)
    casez (\initial )
      /* src = "libresoc.v:108128.9-108128.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub23_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:108177.5-108177.29" *)
    casez (\initial )
      /* src = "libresoc.v:108177.9-108177.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:108226.5-108226.29" *)
    casez (\initial )
      /* src = "libresoc.v:108226.9-108226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:108275.5-108275.29" *)
    casez (\initial )
      /* src = "libresoc.v:108275.9-108275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:108324.5-108324.29" *)
    casez (\initial )
      /* src = "libresoc.v:108324.9-108324.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:108373.5-108373.29" *)
    casez (\initial )
      /* src = "libresoc.v:108373.9-108373.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:108422.5-108422.29" *)
    casez (\initial )
      /* src = "libresoc.v:108422.9-108422.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:108471.5-108471.29" *)
    casez (\initial )
      /* src = "libresoc.v:108471.9-108471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:108520.5-108520.29" *)
    casez (\initial )
      /* src = "libresoc.v:108520.9-108520.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:108569.5-108569.29" *)
    casez (\initial )
      /* src = "libresoc.v:108569.9-108569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:108618.5-108618.29" *)
    casez (\initial )
      /* src = "libresoc.v:108618.9-108618.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0a:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub23_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:108671.1-109648.10" *)
module dec31_dec_sub24(dec31_dec_sub24_function_unit, dec31_dec_sub24_internal_op, dec31_dec_sub24_form, dec31_dec_sub24_asmcode, dec31_dec_sub24_SV_Etype, dec31_dec_sub24_SV_Ptype, dec31_dec_sub24_in1_sel, dec31_dec_sub24_in2_sel, dec31_dec_sub24_in3_sel, dec31_dec_sub24_out_sel, dec31_dec_sub24_cr_in, dec31_dec_sub24_cr_out, dec31_dec_sub24_sv_in1, dec31_dec_sub24_sv_in2, dec31_dec_sub24_sv_in3, dec31_dec_sub24_sv_out, dec31_dec_sub24_sv_out2, dec31_dec_sub24_sv_cr_in, dec31_dec_sub24_sv_cr_out, dec31_dec_sub24_ldst_len, dec31_dec_sub24_upd, dec31_dec_sub24_rc_sel, dec31_dec_sub24_cry_in, dec31_dec_sub24_inv_a, dec31_dec_sub24_inv_out, dec31_dec_sub24_cry_out, dec31_dec_sub24_br, dec31_dec_sub24_sgn_ext, dec31_dec_sub24_rsrv, dec31_dec_sub24_is_32b, dec31_dec_sub24_sgn, dec31_dec_sub24_lk, dec31_dec_sub24_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:109533.3-109551.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:109552.3-109570.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:109305.3-109323.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:109381.3-109399.6" *)
  reg _03_;
  (* src = "libresoc.v:109039.3-109057.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:109058.3-109076.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:109286.3-109304.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:109362.3-109380.6" *)
  reg _07_;
  (* src = "libresoc.v:109438.3-109456.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:109020.3-109038.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:109571.3-109589.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:109590.3-109608.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:109609.3-109627.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:109229.3-109247.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:109324.3-109342.6" *)
  reg _14_;
  (* src = "libresoc.v:109343.3-109361.6" *)
  reg _15_;
  (* src = "libresoc.v:109457.3-109475.6" *)
  reg _16_;
  (* src = "libresoc.v:109210.3-109228.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:109495.3-109513.6" *)
  reg _18_;
  (* src = "libresoc.v:109628.3-109646.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:109267.3-109285.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:109419.3-109437.6" *)
  reg _21_;
  (* src = "libresoc.v:109514.3-109532.6" *)
  reg _22_;
  (* src = "libresoc.v:109476.3-109494.6" *)
  reg _23_;
  (* src = "libresoc.v:109400.3-109418.6" *)
  reg _24_;
  (* src = "libresoc.v:109172.3-109190.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:109191.3-109209.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:109077.3-109095.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:109096.3-109114.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:109115.3-109133.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:109153.3-109171.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:109134.3-109152.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:109248.3-109266.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:108672.7-108672.20" *)
  reg _33_;
  (* src = "libresoc.v:109533.3-109551.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:109552.3-109570.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:109305.3-109323.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:109381.3-109399.6" *)
  reg _37_;
  (* src = "libresoc.v:109039.3-109057.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:109058.3-109076.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:109286.3-109304.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:109362.3-109380.6" *)
  reg _41_;
  (* src = "libresoc.v:109438.3-109456.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:109020.3-109038.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:109571.3-109589.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:109590.3-109608.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:109609.3-109627.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:109229.3-109247.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:109324.3-109342.6" *)
  reg _48_;
  (* src = "libresoc.v:109343.3-109361.6" *)
  reg _49_;
  (* src = "libresoc.v:109457.3-109475.6" *)
  reg _50_;
  (* src = "libresoc.v:109210.3-109228.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:109495.3-109513.6" *)
  reg _52_;
  (* src = "libresoc.v:109628.3-109646.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:109267.3-109285.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:109419.3-109437.6" *)
  reg _55_;
  (* src = "libresoc.v:109514.3-109532.6" *)
  reg _56_;
  (* src = "libresoc.v:109476.3-109494.6" *)
  reg _57_;
  (* src = "libresoc.v:109400.3-109418.6" *)
  reg _58_;
  (* src = "libresoc.v:109172.3-109190.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:109191.3-109209.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:109077.3-109095.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:109096.3-109114.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:109115.3-109133.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:109153.3-109171.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:109134.3-109152.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:109248.3-109266.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_SV_Etype;
  reg [1:0] dec31_dec_sub24_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_SV_Ptype;
  reg [1:0] dec31_dec_sub24_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub24_asmcode;
  reg [7:0] dec31_dec_sub24_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_br;
  reg dec31_dec_sub24_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_cr_in;
  reg [2:0] dec31_dec_sub24_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_cr_out;
  reg [2:0] dec31_dec_sub24_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_cry_in;
  reg [1:0] dec31_dec_sub24_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_cry_out;
  reg dec31_dec_sub24_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub24_form;
  reg [4:0] dec31_dec_sub24_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub24_function_unit;
  reg [13:0] dec31_dec_sub24_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_in1_sel;
  reg [2:0] dec31_dec_sub24_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub24_in2_sel;
  reg [3:0] dec31_dec_sub24_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_in3_sel;
  reg [1:0] dec31_dec_sub24_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub24_internal_op;
  reg [6:0] dec31_dec_sub24_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_inv_a;
  reg dec31_dec_sub24_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_inv_out;
  reg dec31_dec_sub24_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_is_32b;
  reg dec31_dec_sub24_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub24_ldst_len;
  reg [3:0] dec31_dec_sub24_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_lk;
  reg dec31_dec_sub24_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_out_sel;
  reg [2:0] dec31_dec_sub24_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_rc_sel;
  reg [1:0] dec31_dec_sub24_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_rsrv;
  reg dec31_dec_sub24_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_sgl_pipe;
  reg dec31_dec_sub24_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_sgn;
  reg dec31_dec_sub24_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub24_sgn_ext;
  reg dec31_dec_sub24_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_cr_in;
  reg [2:0] dec31_dec_sub24_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_cr_out;
  reg [2:0] dec31_dec_sub24_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_in1;
  reg [2:0] dec31_dec_sub24_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_in2;
  reg [2:0] dec31_dec_sub24_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_in3;
  reg [2:0] dec31_dec_sub24_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_out;
  reg [2:0] dec31_dec_sub24_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub24_sv_out2;
  reg [2:0] dec31_dec_sub24_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub24_upd;
  reg [1:0] dec31_dec_sub24_upd;
  (* src = "libresoc.v:108672.7-108672.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:109021.5-109021.29" *)
    casez (\initial )
      /* src = "libresoc.v:109021.9-109021.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0008;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub24_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:109040.5-109040.29" *)
    casez (\initial )
      /* src = "libresoc.v:109040.9-109040.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:109059.5-109059.29" *)
    casez (\initial )
      /* src = "libresoc.v:109059.9-109059.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:109078.5-109078.29" *)
    casez (\initial )
      /* src = "libresoc.v:109078.9-109078.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:109097.5-109097.29" *)
    casez (\initial )
      /* src = "libresoc.v:109097.9-109097.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h2;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:109116.5-109116.29" *)
    casez (\initial )
      /* src = "libresoc.v:109116.9-109116.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h3;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:109135.5-109135.29" *)
    casez (\initial )
      /* src = "libresoc.v:109135.9-109135.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:109154.5-109154.29" *)
    casez (\initial )
      /* src = "libresoc.v:109154.9-109154.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:109173.5-109173.29" *)
    casez (\initial )
      /* src = "libresoc.v:109173.9-109173.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:109192.5-109192.29" *)
    casez (\initial )
      /* src = "libresoc.v:109192.9-109192.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:109211.5-109211.29" *)
    casez (\initial )
      /* src = "libresoc.v:109211.9-109211.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:109230.5-109230.29" *)
    casez (\initial )
      /* src = "libresoc.v:109230.9-109230.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h3c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _47_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h3d;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub24_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:109249.5-109249.29" *)
    casez (\initial )
      /* src = "libresoc.v:109249.9-109249.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:109268.5-109268.29" *)
    casez (\initial )
      /* src = "libresoc.v:109268.9-109268.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:109287.5-109287.29" *)
    casez (\initial )
      /* src = "libresoc.v:109287.9-109287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:109306.5-109306.29" *)
    casez (\initial )
      /* src = "libresoc.v:109306.9-109306.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'ha0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'ha3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _36_ = 8'ha4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'ha6;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub24_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:109325.5-109325.29" *)
    casez (\initial )
      /* src = "libresoc.v:109325.9-109325.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:109344.5-109344.29" *)
    casez (\initial )
      /* src = "libresoc.v:109344.9-109344.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:109363.5-109363.29" *)
    casez (\initial )
      /* src = "libresoc.v:109363.9-109363.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:109382.5-109382.29" *)
    casez (\initial )
      /* src = "libresoc.v:109382.9-109382.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:109401.5-109401.29" *)
    casez (\initial )
      /* src = "libresoc.v:109401.9-109401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:109420.5-109420.29" *)
    casez (\initial )
      /* src = "libresoc.v:109420.9-109420.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:109439.5-109439.29" *)
    casez (\initial )
      /* src = "libresoc.v:109439.9-109439.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub24_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:109458.5-109458.29" *)
    casez (\initial )
      /* src = "libresoc.v:109458.9-109458.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h1;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:109477.5-109477.29" *)
    casez (\initial )
      /* src = "libresoc.v:109477.9-109477.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:109496.5-109496.29" *)
    casez (\initial )
      /* src = "libresoc.v:109496.9-109496.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:109515.5-109515.29" *)
    casez (\initial )
      /* src = "libresoc.v:109515.9-109515.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:109534.5-109534.29" *)
    casez (\initial )
      /* src = "libresoc.v:109534.9-109534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:109553.5-109553.29" *)
    casez (\initial )
      /* src = "libresoc.v:109553.9-109553.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:109572.5-109572.29" *)
    casez (\initial )
      /* src = "libresoc.v:109572.9-109572.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:109591.5-109591.29" *)
    casez (\initial )
      /* src = "libresoc.v:109591.9-109591.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _45_ = 4'hb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:109610.5-109610.29" *)
    casez (\initial )
      /* src = "libresoc.v:109610.9-109610.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:109629.5-109629.29" *)
    casez (\initial )
      /* src = "libresoc.v:109629.9-109629.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h2;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub24_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:109652.1-111718.10" *)
module dec31_dec_sub26(dec31_dec_sub26_function_unit, dec31_dec_sub26_internal_op, dec31_dec_sub26_form, dec31_dec_sub26_asmcode, dec31_dec_sub26_SV_Etype, dec31_dec_sub26_SV_Ptype, dec31_dec_sub26_in1_sel, dec31_dec_sub26_in2_sel, dec31_dec_sub26_in3_sel, dec31_dec_sub26_out_sel, dec31_dec_sub26_cr_in, dec31_dec_sub26_cr_out, dec31_dec_sub26_sv_in1, dec31_dec_sub26_sv_in2, dec31_dec_sub26_sv_in3, dec31_dec_sub26_sv_out, dec31_dec_sub26_sv_out2, dec31_dec_sub26_sv_cr_in, dec31_dec_sub26_sv_cr_out, dec31_dec_sub26_ldst_len, dec31_dec_sub26_upd, dec31_dec_sub26_rc_sel, dec31_dec_sub26_cry_in, dec31_dec_sub26_inv_a, dec31_dec_sub26_inv_out, dec31_dec_sub26_cry_out, dec31_dec_sub26_br, dec31_dec_sub26_sgn_ext, dec31_dec_sub26_rsrv, dec31_dec_sub26_is_32b, dec31_dec_sub26_sgn, dec31_dec_sub26_lk, dec31_dec_sub26_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:111405.3-111456.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:111457.3-111508.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:110781.3-110832.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:110989.3-111040.6" *)
  reg _03_;
  (* src = "libresoc.v:110053.3-110104.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:110105.3-110156.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:110729.3-110780.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:110937.3-110988.6" *)
  reg _07_;
  (* src = "libresoc.v:111145.3-111196.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:110001.3-110052.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:111509.3-111560.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:111561.3-111612.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:111613.3-111664.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:110573.3-110624.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:110833.3-110884.6" *)
  reg _14_;
  (* src = "libresoc.v:110885.3-110936.6" *)
  reg _15_;
  (* src = "libresoc.v:111197.3-111248.6" *)
  reg _16_;
  (* src = "libresoc.v:110521.3-110572.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:111301.3-111352.6" *)
  reg _18_;
  (* src = "libresoc.v:111665.3-111716.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:110677.3-110728.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:111093.3-111144.6" *)
  reg _21_;
  (* src = "libresoc.v:111353.3-111404.6" *)
  reg _22_;
  (* src = "libresoc.v:111249.3-111300.6" *)
  reg _23_;
  (* src = "libresoc.v:111041.3-111092.6" *)
  reg _24_;
  (* src = "libresoc.v:110417.3-110468.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:110469.3-110520.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:110157.3-110208.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:110209.3-110260.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:110261.3-110312.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:110365.3-110416.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:110313.3-110364.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:110625.3-110676.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:109653.7-109653.20" *)
  reg _33_;
  (* src = "libresoc.v:111405.3-111456.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:111457.3-111508.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:110781.3-110832.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:110989.3-111040.6" *)
  reg _37_;
  (* src = "libresoc.v:110053.3-110104.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:110105.3-110156.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:110729.3-110780.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:110937.3-110988.6" *)
  reg _41_;
  (* src = "libresoc.v:111145.3-111196.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:110001.3-110052.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:111509.3-111560.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:111561.3-111612.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:111613.3-111664.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:110573.3-110624.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:110833.3-110884.6" *)
  reg _48_;
  (* src = "libresoc.v:110885.3-110936.6" *)
  reg _49_;
  (* src = "libresoc.v:111197.3-111248.6" *)
  reg _50_;
  (* src = "libresoc.v:110521.3-110572.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:111301.3-111352.6" *)
  reg _52_;
  (* src = "libresoc.v:111665.3-111716.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:110677.3-110728.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:111093.3-111144.6" *)
  reg _55_;
  (* src = "libresoc.v:111353.3-111404.6" *)
  reg _56_;
  (* src = "libresoc.v:111249.3-111300.6" *)
  reg _57_;
  (* src = "libresoc.v:111041.3-111092.6" *)
  reg _58_;
  (* src = "libresoc.v:110417.3-110468.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:110469.3-110520.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:110157.3-110208.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:110209.3-110260.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:110261.3-110312.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:110365.3-110416.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:110313.3-110364.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:110625.3-110676.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_SV_Etype;
  reg [1:0] dec31_dec_sub26_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_SV_Ptype;
  reg [1:0] dec31_dec_sub26_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub26_asmcode;
  reg [7:0] dec31_dec_sub26_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_br;
  reg dec31_dec_sub26_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_cr_in;
  reg [2:0] dec31_dec_sub26_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_cr_out;
  reg [2:0] dec31_dec_sub26_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_cry_in;
  reg [1:0] dec31_dec_sub26_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_cry_out;
  reg dec31_dec_sub26_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub26_form;
  reg [4:0] dec31_dec_sub26_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub26_function_unit;
  reg [13:0] dec31_dec_sub26_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_in1_sel;
  reg [2:0] dec31_dec_sub26_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub26_in2_sel;
  reg [3:0] dec31_dec_sub26_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_in3_sel;
  reg [1:0] dec31_dec_sub26_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub26_internal_op;
  reg [6:0] dec31_dec_sub26_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_inv_a;
  reg dec31_dec_sub26_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_inv_out;
  reg dec31_dec_sub26_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_is_32b;
  reg dec31_dec_sub26_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub26_ldst_len;
  reg [3:0] dec31_dec_sub26_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_lk;
  reg dec31_dec_sub26_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_out_sel;
  reg [2:0] dec31_dec_sub26_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_rc_sel;
  reg [1:0] dec31_dec_sub26_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_rsrv;
  reg dec31_dec_sub26_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_sgl_pipe;
  reg dec31_dec_sub26_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_sgn;
  reg dec31_dec_sub26_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub26_sgn_ext;
  reg dec31_dec_sub26_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_cr_in;
  reg [2:0] dec31_dec_sub26_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_cr_out;
  reg [2:0] dec31_dec_sub26_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_in1;
  reg [2:0] dec31_dec_sub26_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_in2;
  reg [2:0] dec31_dec_sub26_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_in3;
  reg [2:0] dec31_dec_sub26_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_out;
  reg [2:0] dec31_dec_sub26_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub26_sv_out2;
  reg [2:0] dec31_dec_sub26_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub26_upd;
  reg [1:0] dec31_dec_sub26_upd;
  (* src = "libresoc.v:109653.7-109653.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:110002.5-110002.29" *)
    casez (\initial )
      /* src = "libresoc.v:110002.9-110002.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _43_ = 14'h0008;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub26_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:110054.5-110054.29" *)
    casez (\initial )
      /* src = "libresoc.v:110054.9-110054.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:110106.5-110106.29" *)
    casez (\initial )
      /* src = "libresoc.v:110106.9-110106.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:110158.5-110158.29" *)
    casez (\initial )
      /* src = "libresoc.v:110158.9-110158.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:110210.5-110210.29" *)
    casez (\initial )
      /* src = "libresoc.v:110210.9-110210.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:110262.5-110262.29" *)
    casez (\initial )
      /* src = "libresoc.v:110262.9-110262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _63_ = 3'h2;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:110314.5-110314.29" *)
    casez (\initial )
      /* src = "libresoc.v:110314.9-110314.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:110366.5-110366.29" *)
    casez (\initial )
      /* src = "libresoc.v:110366.9-110366.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:110418.5-110418.29" *)
    casez (\initial )
      /* src = "libresoc.v:110418.9-110418.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:110470.5-110470.29" *)
    casez (\initial )
      /* src = "libresoc.v:110470.9-110470.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:110522.5-110522.29" *)
    casez (\initial )
      /* src = "libresoc.v:110522.9-110522.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:110574.5-110574.29" *)
    casez (\initial )
      /* src = "libresoc.v:110574.9-110574.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _47_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h0e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _47_ = 7'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h1f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _47_ = 7'h20;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _47_ = 7'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _47_ = 7'h37;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h37;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _47_ = 7'h3d;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub26_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:110626.5-110626.29" *)
    casez (\initial )
      /* src = "libresoc.v:110626.9-110626.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:110678.5-110678.29" *)
    casez (\initial )
      /* src = "libresoc.v:110678.9-110678.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:110730.5-110730.29" *)
    casez (\initial )
      /* src = "libresoc.v:110730.9-110730.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:110782.5-110782.29" *)
    casez (\initial )
      /* src = "libresoc.v:110782.9-110782.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h21;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h22;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _36_ = 8'h23;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h24;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _36_ = 8'h44;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = 8'h45;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'h46;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _36_ = 8'h47;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h8c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h8d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _36_ = 8'h8e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _36_ = 8'h8f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'h90;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'ha1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _36_ = 8'ha2;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub26_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:110834.5-110834.29" *)
    casez (\initial )
      /* src = "libresoc.v:110834.9-110834.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:110886.5-110886.29" *)
    casez (\initial )
      /* src = "libresoc.v:110886.9-110886.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:110938.5-110938.29" *)
    casez (\initial )
      /* src = "libresoc.v:110938.9-110938.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _41_ = 1'h1;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:110990.5-110990.29" *)
    casez (\initial )
      /* src = "libresoc.v:110990.9-110990.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:111042.5-111042.29" *)
    casez (\initial )
      /* src = "libresoc.v:111042.9-111042.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:111094.5-111094.29" *)
    casez (\initial )
      /* src = "libresoc.v:111094.9-111094.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:111146.5-111146.29" *)
    casez (\initial )
      /* src = "libresoc.v:111146.9-111146.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _42_ = 5'h10;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _42_ = 5'h10;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub26_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:111198.5-111198.29" *)
    casez (\initial )
      /* src = "libresoc.v:111198.9-111198.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:111250.5-111250.29" *)
    casez (\initial )
      /* src = "libresoc.v:111250.9-111250.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _57_ = 1'h1;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:111302.5-111302.29" *)
    casez (\initial )
      /* src = "libresoc.v:111302.9-111302.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:111354.5-111354.29" *)
    casez (\initial )
      /* src = "libresoc.v:111354.9-111354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:111406.5-111406.29" *)
    casez (\initial )
      /* src = "libresoc.v:111406.9-111406.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:111458.5-111458.29" *)
    casez (\initial )
      /* src = "libresoc.v:111458.9-111458.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:111510.5-111510.29" *)
    casez (\initial )
      /* src = "libresoc.v:111510.9-111510.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:111562.5-111562.29" *)
    casez (\initial )
      /* src = "libresoc.v:111562.9-111562.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _45_ = 4'ha;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:111614.5-111614.29" *)
    casez (\initial )
      /* src = "libresoc.v:111614.9-111614.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:111666.5-111666.29" *)
    casez (\initial )
      /* src = "libresoc.v:111666.9-111666.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0b:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h05:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _53_ = 3'h2;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub26_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:111722.1-112699.10" *)
module dec31_dec_sub27(dec31_dec_sub27_function_unit, dec31_dec_sub27_internal_op, dec31_dec_sub27_form, dec31_dec_sub27_asmcode, dec31_dec_sub27_SV_Etype, dec31_dec_sub27_SV_Ptype, dec31_dec_sub27_in1_sel, dec31_dec_sub27_in2_sel, dec31_dec_sub27_in3_sel, dec31_dec_sub27_out_sel, dec31_dec_sub27_cr_in, dec31_dec_sub27_cr_out, dec31_dec_sub27_sv_in1, dec31_dec_sub27_sv_in2, dec31_dec_sub27_sv_in3, dec31_dec_sub27_sv_out, dec31_dec_sub27_sv_out2, dec31_dec_sub27_sv_cr_in, dec31_dec_sub27_sv_cr_out, dec31_dec_sub27_ldst_len, dec31_dec_sub27_upd, dec31_dec_sub27_rc_sel, dec31_dec_sub27_cry_in, dec31_dec_sub27_inv_a, dec31_dec_sub27_inv_out, dec31_dec_sub27_cry_out, dec31_dec_sub27_br, dec31_dec_sub27_sgn_ext, dec31_dec_sub27_rsrv, dec31_dec_sub27_is_32b, dec31_dec_sub27_sgn, dec31_dec_sub27_lk, dec31_dec_sub27_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:112584.3-112602.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:112603.3-112621.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:112356.3-112374.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:112432.3-112450.6" *)
  reg _03_;
  (* src = "libresoc.v:112090.3-112108.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:112109.3-112127.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:112337.3-112355.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:112413.3-112431.6" *)
  reg _07_;
  (* src = "libresoc.v:112489.3-112507.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:112071.3-112089.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:112622.3-112640.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:112641.3-112659.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:112660.3-112678.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:112280.3-112298.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:112375.3-112393.6" *)
  reg _14_;
  (* src = "libresoc.v:112394.3-112412.6" *)
  reg _15_;
  (* src = "libresoc.v:112508.3-112526.6" *)
  reg _16_;
  (* src = "libresoc.v:112261.3-112279.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:112546.3-112564.6" *)
  reg _18_;
  (* src = "libresoc.v:112679.3-112697.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:112318.3-112336.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:112470.3-112488.6" *)
  reg _21_;
  (* src = "libresoc.v:112565.3-112583.6" *)
  reg _22_;
  (* src = "libresoc.v:112527.3-112545.6" *)
  reg _23_;
  (* src = "libresoc.v:112451.3-112469.6" *)
  reg _24_;
  (* src = "libresoc.v:112223.3-112241.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:112242.3-112260.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:112128.3-112146.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:112147.3-112165.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:112166.3-112184.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:112204.3-112222.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:112185.3-112203.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:112299.3-112317.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:111723.7-111723.20" *)
  reg _33_;
  (* src = "libresoc.v:112584.3-112602.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:112603.3-112621.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:112356.3-112374.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:112432.3-112450.6" *)
  reg _37_;
  (* src = "libresoc.v:112090.3-112108.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:112109.3-112127.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:112337.3-112355.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:112413.3-112431.6" *)
  reg _41_;
  (* src = "libresoc.v:112489.3-112507.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:112071.3-112089.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:112622.3-112640.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:112641.3-112659.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:112660.3-112678.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:112280.3-112298.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:112375.3-112393.6" *)
  reg _48_;
  (* src = "libresoc.v:112394.3-112412.6" *)
  reg _49_;
  (* src = "libresoc.v:112508.3-112526.6" *)
  reg _50_;
  (* src = "libresoc.v:112261.3-112279.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:112546.3-112564.6" *)
  reg _52_;
  (* src = "libresoc.v:112679.3-112697.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:112318.3-112336.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:112470.3-112488.6" *)
  reg _55_;
  (* src = "libresoc.v:112565.3-112583.6" *)
  reg _56_;
  (* src = "libresoc.v:112527.3-112545.6" *)
  reg _57_;
  (* src = "libresoc.v:112451.3-112469.6" *)
  reg _58_;
  (* src = "libresoc.v:112223.3-112241.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:112242.3-112260.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:112128.3-112146.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:112147.3-112165.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:112166.3-112184.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:112204.3-112222.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:112185.3-112203.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:112299.3-112317.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_SV_Etype;
  reg [1:0] dec31_dec_sub27_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_SV_Ptype;
  reg [1:0] dec31_dec_sub27_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub27_asmcode;
  reg [7:0] dec31_dec_sub27_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_br;
  reg dec31_dec_sub27_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_cr_in;
  reg [2:0] dec31_dec_sub27_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_cr_out;
  reg [2:0] dec31_dec_sub27_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_cry_in;
  reg [1:0] dec31_dec_sub27_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_cry_out;
  reg dec31_dec_sub27_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub27_form;
  reg [4:0] dec31_dec_sub27_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub27_function_unit;
  reg [13:0] dec31_dec_sub27_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_in1_sel;
  reg [2:0] dec31_dec_sub27_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub27_in2_sel;
  reg [3:0] dec31_dec_sub27_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_in3_sel;
  reg [1:0] dec31_dec_sub27_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub27_internal_op;
  reg [6:0] dec31_dec_sub27_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_inv_a;
  reg dec31_dec_sub27_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_inv_out;
  reg dec31_dec_sub27_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_is_32b;
  reg dec31_dec_sub27_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub27_ldst_len;
  reg [3:0] dec31_dec_sub27_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_lk;
  reg dec31_dec_sub27_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_out_sel;
  reg [2:0] dec31_dec_sub27_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_rc_sel;
  reg [1:0] dec31_dec_sub27_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_rsrv;
  reg dec31_dec_sub27_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_sgl_pipe;
  reg dec31_dec_sub27_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_sgn;
  reg dec31_dec_sub27_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub27_sgn_ext;
  reg dec31_dec_sub27_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_cr_in;
  reg [2:0] dec31_dec_sub27_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_cr_out;
  reg [2:0] dec31_dec_sub27_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_in1;
  reg [2:0] dec31_dec_sub27_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_in2;
  reg [2:0] dec31_dec_sub27_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_in3;
  reg [2:0] dec31_dec_sub27_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_out;
  reg [2:0] dec31_dec_sub27_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub27_sv_out2;
  reg [2:0] dec31_dec_sub27_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub27_upd;
  reg [1:0] dec31_dec_sub27_upd;
  (* src = "libresoc.v:111723.7-111723.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:112072.5-112072.29" *)
    casez (\initial )
      /* src = "libresoc.v:112072.9-112072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _43_ = 14'h0008;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0008;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub27_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:112091.5-112091.29" *)
    casez (\initial )
      /* src = "libresoc.v:112091.9-112091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:112110.5-112110.29" *)
    casez (\initial )
      /* src = "libresoc.v:112110.9-112110.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:112129.5-112129.29" *)
    casez (\initial )
      /* src = "libresoc.v:112129.9-112129.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:112148.5-112148.29" *)
    casez (\initial )
      /* src = "libresoc.v:112148.9-112148.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h2;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:112167.5-112167.29" *)
    casez (\initial )
      /* src = "libresoc.v:112167.9-112167.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _63_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h3;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:112186.5-112186.29" *)
    casez (\initial )
      /* src = "libresoc.v:112186.9-112186.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:112205.5-112205.29" *)
    casez (\initial )
      /* src = "libresoc.v:112205.9-112205.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:112224.5-112224.29" *)
    casez (\initial )
      /* src = "libresoc.v:112224.9-112224.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:112243.5-112243.29" *)
    casez (\initial )
      /* src = "libresoc.v:112243.9-112243.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:112262.5-112262.29" *)
    casez (\initial )
      /* src = "libresoc.v:112262.9-112262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:112281.5-112281.29" *)
    casez (\initial )
      /* src = "libresoc.v:112281.9-112281.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _47_ = 7'h20;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h3c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _47_ = 7'h3d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h3d;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub27_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:112300.5-112300.29" *)
    casez (\initial )
      /* src = "libresoc.v:112300.9-112300.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:112319.5-112319.29" *)
    casez (\initial )
      /* src = "libresoc.v:112319.9-112319.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:112338.5-112338.29" *)
    casez (\initial )
      /* src = "libresoc.v:112338.9-112338.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:112357.5-112357.29" *)
    casez (\initial )
      /* src = "libresoc.v:112357.9-112357.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _36_ = 8'h47;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h9f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _36_ = 8'ha2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'ha5;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub27_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:112376.5-112376.29" *)
    casez (\initial )
      /* src = "libresoc.v:112376.9-112376.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:112395.5-112395.29" *)
    casez (\initial )
      /* src = "libresoc.v:112395.9-112395.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:112414.5-112414.29" *)
    casez (\initial )
      /* src = "libresoc.v:112414.9-112414.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:112433.5-112433.29" *)
    casez (\initial )
      /* src = "libresoc.v:112433.9-112433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:112452.5-112452.29" *)
    casez (\initial )
      /* src = "libresoc.v:112452.9-112452.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:112471.5-112471.29" *)
    casez (\initial )
      /* src = "libresoc.v:112471.9-112471.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:112490.5-112490.29" *)
    casez (\initial )
      /* src = "libresoc.v:112490.9-112490.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _42_ = 5'h10;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _42_ = 5'h10;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub27_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:112509.5-112509.29" *)
    casez (\initial )
      /* src = "libresoc.v:112509.9-112509.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:112528.5-112528.29" *)
    casez (\initial )
      /* src = "libresoc.v:112528.9-112528.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:112547.5-112547.29" *)
    casez (\initial )
      /* src = "libresoc.v:112547.9-112547.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:112566.5-112566.29" *)
    casez (\initial )
      /* src = "libresoc.v:112566.9-112566.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:112585.5-112585.29" *)
    casez (\initial )
      /* src = "libresoc.v:112585.9-112585.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:112604.5-112604.29" *)
    casez (\initial )
      /* src = "libresoc.v:112604.9-112604.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:112623.5-112623.29" *)
    casez (\initial )
      /* src = "libresoc.v:112623.9-112623.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _44_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h0;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:112642.5-112642.29" *)
    casez (\initial )
      /* src = "libresoc.v:112642.9-112642.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _45_ = 4'ha;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:112661.5-112661.29" *)
    casez (\initial )
      /* src = "libresoc.v:112661.9-112661.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:112680.5-112680.29" *)
    casez (\initial )
      /* src = "libresoc.v:112680.9-112680.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h1b:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h19:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h2;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub27_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:112703.1-114274.10" *)
module dec31_dec_sub28(dec31_dec_sub28_function_unit, dec31_dec_sub28_internal_op, dec31_dec_sub28_form, dec31_dec_sub28_asmcode, dec31_dec_sub28_SV_Etype, dec31_dec_sub28_SV_Ptype, dec31_dec_sub28_in1_sel, dec31_dec_sub28_in2_sel, dec31_dec_sub28_in3_sel, dec31_dec_sub28_out_sel, dec31_dec_sub28_cr_in, dec31_dec_sub28_cr_out, dec31_dec_sub28_sv_in1, dec31_dec_sub28_sv_in2, dec31_dec_sub28_sv_in3, dec31_dec_sub28_sv_out, dec31_dec_sub28_sv_out2, dec31_dec_sub28_sv_cr_in, dec31_dec_sub28_sv_cr_out, dec31_dec_sub28_ldst_len, dec31_dec_sub28_upd, dec31_dec_sub28_rc_sel, dec31_dec_sub28_cry_in, dec31_dec_sub28_inv_a, dec31_dec_sub28_inv_out, dec31_dec_sub28_cry_out, dec31_dec_sub28_br, dec31_dec_sub28_sgn_ext, dec31_dec_sub28_rsrv, dec31_dec_sub28_is_32b, dec31_dec_sub28_sgn, dec31_dec_sub28_lk, dec31_dec_sub28_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:114051.3-114087.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:114088.3-114124.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:113607.3-113643.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:113755.3-113791.6" *)
  reg _03_;
  (* src = "libresoc.v:113089.3-113125.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:113126.3-113162.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:113570.3-113606.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:113718.3-113754.6" *)
  reg _07_;
  (* src = "libresoc.v:113866.3-113902.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:113052.3-113088.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:114125.3-114161.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:114162.3-114198.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:114199.3-114235.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:113459.3-113495.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:113644.3-113680.6" *)
  reg _14_;
  (* src = "libresoc.v:113681.3-113717.6" *)
  reg _15_;
  (* src = "libresoc.v:113903.3-113939.6" *)
  reg _16_;
  (* src = "libresoc.v:113422.3-113458.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:113977.3-114013.6" *)
  reg _18_;
  (* src = "libresoc.v:114236.3-114272.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:113533.3-113569.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:113829.3-113865.6" *)
  reg _21_;
  (* src = "libresoc.v:114014.3-114050.6" *)
  reg _22_;
  (* src = "libresoc.v:113940.3-113976.6" *)
  reg _23_;
  (* src = "libresoc.v:113792.3-113828.6" *)
  reg _24_;
  (* src = "libresoc.v:113348.3-113384.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:113385.3-113421.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:113163.3-113199.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:113200.3-113236.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:113237.3-113273.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:113311.3-113347.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:113274.3-113310.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:113496.3-113532.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:112704.7-112704.20" *)
  reg _33_;
  (* src = "libresoc.v:114051.3-114087.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:114088.3-114124.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:113607.3-113643.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:113755.3-113791.6" *)
  reg _37_;
  (* src = "libresoc.v:113089.3-113125.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:113126.3-113162.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:113570.3-113606.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:113718.3-113754.6" *)
  reg _41_;
  (* src = "libresoc.v:113866.3-113902.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:113052.3-113088.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:114125.3-114161.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:114162.3-114198.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:114199.3-114235.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:113459.3-113495.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:113644.3-113680.6" *)
  reg _48_;
  (* src = "libresoc.v:113681.3-113717.6" *)
  reg _49_;
  (* src = "libresoc.v:113903.3-113939.6" *)
  reg _50_;
  (* src = "libresoc.v:113422.3-113458.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:113977.3-114013.6" *)
  reg _52_;
  (* src = "libresoc.v:114236.3-114272.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:113533.3-113569.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:113829.3-113865.6" *)
  reg _55_;
  (* src = "libresoc.v:114014.3-114050.6" *)
  reg _56_;
  (* src = "libresoc.v:113940.3-113976.6" *)
  reg _57_;
  (* src = "libresoc.v:113792.3-113828.6" *)
  reg _58_;
  (* src = "libresoc.v:113348.3-113384.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:113385.3-113421.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:113163.3-113199.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:113200.3-113236.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:113237.3-113273.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:113311.3-113347.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:113274.3-113310.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:113496.3-113532.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_SV_Etype;
  reg [1:0] dec31_dec_sub28_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_SV_Ptype;
  reg [1:0] dec31_dec_sub28_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub28_asmcode;
  reg [7:0] dec31_dec_sub28_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_br;
  reg dec31_dec_sub28_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_cr_in;
  reg [2:0] dec31_dec_sub28_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_cr_out;
  reg [2:0] dec31_dec_sub28_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_cry_in;
  reg [1:0] dec31_dec_sub28_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_cry_out;
  reg dec31_dec_sub28_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub28_form;
  reg [4:0] dec31_dec_sub28_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub28_function_unit;
  reg [13:0] dec31_dec_sub28_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_in1_sel;
  reg [2:0] dec31_dec_sub28_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub28_in2_sel;
  reg [3:0] dec31_dec_sub28_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_in3_sel;
  reg [1:0] dec31_dec_sub28_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub28_internal_op;
  reg [6:0] dec31_dec_sub28_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_inv_a;
  reg dec31_dec_sub28_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_inv_out;
  reg dec31_dec_sub28_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_is_32b;
  reg dec31_dec_sub28_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub28_ldst_len;
  reg [3:0] dec31_dec_sub28_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_lk;
  reg dec31_dec_sub28_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_out_sel;
  reg [2:0] dec31_dec_sub28_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_rc_sel;
  reg [1:0] dec31_dec_sub28_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_rsrv;
  reg dec31_dec_sub28_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_sgl_pipe;
  reg dec31_dec_sub28_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_sgn;
  reg dec31_dec_sub28_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub28_sgn_ext;
  reg dec31_dec_sub28_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_cr_in;
  reg [2:0] dec31_dec_sub28_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_cr_out;
  reg [2:0] dec31_dec_sub28_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_in1;
  reg [2:0] dec31_dec_sub28_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_in2;
  reg [2:0] dec31_dec_sub28_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_in3;
  reg [2:0] dec31_dec_sub28_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_out;
  reg [2:0] dec31_dec_sub28_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub28_sv_out2;
  reg [2:0] dec31_dec_sub28_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub28_upd;
  reg [1:0] dec31_dec_sub28_upd;
  (* src = "libresoc.v:112704.7-112704.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:113053.5-113053.29" *)
    casez (\initial )
      /* src = "libresoc.v:113053.9-113053.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _43_ = 14'h0010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _43_ = 14'h0010;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub28_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:113090.5-113090.29" *)
    casez (\initial )
      /* src = "libresoc.v:113090.9-113090.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:113127.5-113127.29" *)
    casez (\initial )
      /* src = "libresoc.v:113127.9-113127.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:113164.5-113164.29" *)
    casez (\initial )
      /* src = "libresoc.v:113164.9-113164.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _61_ = 3'h3;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:113201.5-113201.29" *)
    casez (\initial )
      /* src = "libresoc.v:113201.9-113201.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _62_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _62_ = 3'h2;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:113238.5-113238.29" *)
    casez (\initial )
      /* src = "libresoc.v:113238.9-113238.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:113275.5-113275.29" *)
    casez (\initial )
      /* src = "libresoc.v:113275.9-113275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:113312.5-113312.29" *)
    casez (\initial )
      /* src = "libresoc.v:113312.9-113312.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:113349.5-113349.29" *)
    casez (\initial )
      /* src = "libresoc.v:113349.9-113349.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:113386.5-113386.29" *)
    casez (\initial )
      /* src = "libresoc.v:113386.9-113386.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:113423.5-113423.29" *)
    casez (\initial )
      /* src = "libresoc.v:113423.9-113423.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:113460.5-113460.29" *)
    casez (\initial )
      /* src = "libresoc.v:113460.9-113460.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h09;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h0b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h43;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _47_ = 7'h04;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _47_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _47_ = 7'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _47_ = 7'h43;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub28_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:113497.5-113497.29" *)
    casez (\initial )
      /* src = "libresoc.v:113497.9-113497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:113534.5-113534.29" *)
    casez (\initial )
      /* src = "libresoc.v:113534.9-113534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:113571.5-113571.29" *)
    casez (\initial )
      /* src = "libresoc.v:113571.9-113571.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:113608.5-113608.29" *)
    casez (\initial )
      /* src = "libresoc.v:113608.9-113608.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h0f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'h10;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h19;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h1b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h43;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _36_ = 8'h83;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h87;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _36_ = 8'h88;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _36_ = 8'h89;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _36_ = 8'hd1;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub28_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:113645.5-113645.29" *)
    casez (\initial )
      /* src = "libresoc.v:113645.9-113645.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:113682.5-113682.29" *)
    casez (\initial )
      /* src = "libresoc.v:113682.9-113682.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _49_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:113719.5-113719.29" *)
    casez (\initial )
      /* src = "libresoc.v:113719.9-113719.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:113756.5-113756.29" *)
    casez (\initial )
      /* src = "libresoc.v:113756.9-113756.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:113793.5-113793.29" *)
    casez (\initial )
      /* src = "libresoc.v:113793.9-113793.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:113830.5-113830.29" *)
    casez (\initial )
      /* src = "libresoc.v:113830.9-113830.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:113867.5-113867.29" *)
    casez (\initial )
      /* src = "libresoc.v:113867.9-113867.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub28_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:113904.5-113904.29" *)
    casez (\initial )
      /* src = "libresoc.v:113904.9-113904.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:113941.5-113941.29" *)
    casez (\initial )
      /* src = "libresoc.v:113941.9-113941.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:113978.5-113978.29" *)
    casez (\initial )
      /* src = "libresoc.v:113978.9-113978.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:114015.5-114015.29" *)
    casez (\initial )
      /* src = "libresoc.v:114015.9-114015.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:114052.5-114052.29" *)
    casez (\initial )
      /* src = "libresoc.v:114052.9-114052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:114089.5-114089.29" *)
    casez (\initial )
      /* src = "libresoc.v:114089.9-114089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:114126.5-114126.29" *)
    casez (\initial )
      /* src = "libresoc.v:114126.9-114126.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _44_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _44_ = 3'h4;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:114163.5-114163.29" *)
    casez (\initial )
      /* src = "libresoc.v:114163.9-114163.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:114200.5-114200.29" *)
    casez (\initial )
      /* src = "libresoc.v:114200.9-114200.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:114237.5-114237.29" *)
    casez (\initial )
      /* src = "libresoc.v:114237.9-114237.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _53_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h09:
        begin
          _53_ = 3'h2;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub28_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:114278.1-115057.10" *)
module dec31_dec_sub4(dec31_dec_sub4_function_unit, dec31_dec_sub4_internal_op, dec31_dec_sub4_form, dec31_dec_sub4_asmcode, dec31_dec_sub4_SV_Etype, dec31_dec_sub4_SV_Ptype, dec31_dec_sub4_in1_sel, dec31_dec_sub4_in2_sel, dec31_dec_sub4_in3_sel, dec31_dec_sub4_out_sel, dec31_dec_sub4_cr_in, dec31_dec_sub4_cr_out, dec31_dec_sub4_sv_in1, dec31_dec_sub4_sv_in2, dec31_dec_sub4_sv_in3, dec31_dec_sub4_sv_out, dec31_dec_sub4_sv_out2, dec31_dec_sub4_sv_cr_in, dec31_dec_sub4_sv_cr_out, dec31_dec_sub4_ldst_len, dec31_dec_sub4_upd, dec31_dec_sub4_rc_sel, dec31_dec_sub4_cry_in, dec31_dec_sub4_inv_a, dec31_dec_sub4_inv_out, dec31_dec_sub4_cry_out, dec31_dec_sub4_br, dec31_dec_sub4_sgn_ext, dec31_dec_sub4_rsrv, dec31_dec_sub4_is_32b, dec31_dec_sub4_sgn, dec31_dec_sub4_lk, dec31_dec_sub4_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:114978.3-114990.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:114991.3-115003.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:114822.3-114834.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:114874.3-114886.6" *)
  reg _03_;
  (* src = "libresoc.v:114640.3-114652.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:114653.3-114665.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:114809.3-114821.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:114861.3-114873.6" *)
  reg _07_;
  (* src = "libresoc.v:114913.3-114925.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:114627.3-114639.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:115004.3-115016.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:115017.3-115029.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:115030.3-115042.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:114770.3-114782.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:114835.3-114847.6" *)
  reg _14_;
  (* src = "libresoc.v:114848.3-114860.6" *)
  reg _15_;
  (* src = "libresoc.v:114926.3-114938.6" *)
  reg _16_;
  (* src = "libresoc.v:114757.3-114769.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:114952.3-114964.6" *)
  reg _18_;
  (* src = "libresoc.v:115043.3-115055.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:114796.3-114808.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:114900.3-114912.6" *)
  reg _21_;
  (* src = "libresoc.v:114965.3-114977.6" *)
  reg _22_;
  (* src = "libresoc.v:114939.3-114951.6" *)
  reg _23_;
  (* src = "libresoc.v:114887.3-114899.6" *)
  reg _24_;
  (* src = "libresoc.v:114731.3-114743.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:114744.3-114756.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:114666.3-114678.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:114679.3-114691.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:114692.3-114704.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:114718.3-114730.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:114705.3-114717.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:114783.3-114795.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:114279.7-114279.20" *)
  reg _33_;
  (* src = "libresoc.v:114978.3-114990.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:114991.3-115003.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:114822.3-114834.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:114874.3-114886.6" *)
  reg _37_;
  (* src = "libresoc.v:114640.3-114652.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:114653.3-114665.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:114809.3-114821.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:114861.3-114873.6" *)
  reg _41_;
  (* src = "libresoc.v:114913.3-114925.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:114627.3-114639.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:115004.3-115016.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:115017.3-115029.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:115030.3-115042.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:114770.3-114782.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:114835.3-114847.6" *)
  reg _48_;
  (* src = "libresoc.v:114848.3-114860.6" *)
  reg _49_;
  (* src = "libresoc.v:114926.3-114938.6" *)
  reg _50_;
  (* src = "libresoc.v:114757.3-114769.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:114952.3-114964.6" *)
  reg _52_;
  (* src = "libresoc.v:115043.3-115055.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:114796.3-114808.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:114900.3-114912.6" *)
  reg _55_;
  (* src = "libresoc.v:114965.3-114977.6" *)
  reg _56_;
  (* src = "libresoc.v:114939.3-114951.6" *)
  reg _57_;
  (* src = "libresoc.v:114887.3-114899.6" *)
  reg _58_;
  (* src = "libresoc.v:114731.3-114743.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:114744.3-114756.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:114666.3-114678.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:114679.3-114691.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:114692.3-114704.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:114718.3-114730.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:114705.3-114717.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:114783.3-114795.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_SV_Etype;
  reg [1:0] dec31_dec_sub4_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_SV_Ptype;
  reg [1:0] dec31_dec_sub4_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub4_asmcode;
  reg [7:0] dec31_dec_sub4_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_br;
  reg dec31_dec_sub4_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_cr_in;
  reg [2:0] dec31_dec_sub4_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_cr_out;
  reg [2:0] dec31_dec_sub4_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_cry_in;
  reg [1:0] dec31_dec_sub4_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_cry_out;
  reg dec31_dec_sub4_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub4_form;
  reg [4:0] dec31_dec_sub4_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub4_function_unit;
  reg [13:0] dec31_dec_sub4_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_in1_sel;
  reg [2:0] dec31_dec_sub4_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub4_in2_sel;
  reg [3:0] dec31_dec_sub4_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_in3_sel;
  reg [1:0] dec31_dec_sub4_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub4_internal_op;
  reg [6:0] dec31_dec_sub4_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_inv_a;
  reg dec31_dec_sub4_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_inv_out;
  reg dec31_dec_sub4_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_is_32b;
  reg dec31_dec_sub4_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub4_ldst_len;
  reg [3:0] dec31_dec_sub4_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_lk;
  reg dec31_dec_sub4_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_out_sel;
  reg [2:0] dec31_dec_sub4_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_rc_sel;
  reg [1:0] dec31_dec_sub4_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_rsrv;
  reg dec31_dec_sub4_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_sgl_pipe;
  reg dec31_dec_sub4_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_sgn;
  reg dec31_dec_sub4_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub4_sgn_ext;
  reg dec31_dec_sub4_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_cr_in;
  reg [2:0] dec31_dec_sub4_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_cr_out;
  reg [2:0] dec31_dec_sub4_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_in1;
  reg [2:0] dec31_dec_sub4_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_in2;
  reg [2:0] dec31_dec_sub4_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_in3;
  reg [2:0] dec31_dec_sub4_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_out;
  reg [2:0] dec31_dec_sub4_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub4_sv_out2;
  reg [2:0] dec31_dec_sub4_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub4_upd;
  reg [1:0] dec31_dec_sub4_upd;
  (* src = "libresoc.v:114279.7-114279.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:114628.5-114628.29" *)
    casez (\initial )
      /* src = "libresoc.v:114628.9-114628.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0080;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0080;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub4_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:114641.5-114641.29" *)
    casez (\initial )
      /* src = "libresoc.v:114641.9-114641.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:114654.5-114654.29" *)
    casez (\initial )
      /* src = "libresoc.v:114654.9-114654.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:114667.5-114667.29" *)
    casez (\initial )
      /* src = "libresoc.v:114667.9-114667.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h0;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:114680.5-114680.29" *)
    casez (\initial )
      /* src = "libresoc.v:114680.9-114680.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:114693.5-114693.29" *)
    casez (\initial )
      /* src = "libresoc.v:114693.9-114693.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:114706.5-114706.29" *)
    casez (\initial )
      /* src = "libresoc.v:114706.9-114706.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:114719.5-114719.29" *)
    casez (\initial )
      /* src = "libresoc.v:114719.9-114719.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:114732.5-114732.29" *)
    casez (\initial )
      /* src = "libresoc.v:114732.9-114732.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:114745.5-114745.29" *)
    casez (\initial )
      /* src = "libresoc.v:114745.9-114745.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:114758.5-114758.29" *)
    casez (\initial )
      /* src = "libresoc.v:114758.9-114758.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:114771.5-114771.29" *)
    casez (\initial )
      /* src = "libresoc.v:114771.9-114771.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h3f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h3f;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub4_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:114784.5-114784.29" *)
    casez (\initial )
      /* src = "libresoc.v:114784.9-114784.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:114797.5-114797.29" *)
    casez (\initial )
      /* src = "libresoc.v:114797.9-114797.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:114810.5-114810.29" *)
    casez (\initial )
      /* src = "libresoc.v:114810.9-114810.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:114823.5-114823.29" *)
    casez (\initial )
      /* src = "libresoc.v:114823.9-114823.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'hcb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'hcf;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub4_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:114836.5-114836.29" *)
    casez (\initial )
      /* src = "libresoc.v:114836.9-114836.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:114849.5-114849.29" *)
    casez (\initial )
      /* src = "libresoc.v:114849.9-114849.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:114862.5-114862.29" *)
    casez (\initial )
      /* src = "libresoc.v:114862.9-114862.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:114875.5-114875.29" *)
    casez (\initial )
      /* src = "libresoc.v:114875.9-114875.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:114888.5-114888.29" *)
    casez (\initial )
      /* src = "libresoc.v:114888.9-114888.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:114901.5-114901.29" *)
    casez (\initial )
      /* src = "libresoc.v:114901.9-114901.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:114914.5-114914.29" *)
    casez (\initial )
      /* src = "libresoc.v:114914.9-114914.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h08;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub4_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:114927.5-114927.29" *)
    casez (\initial )
      /* src = "libresoc.v:114927.9-114927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h1;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:114940.5-114940.29" *)
    casez (\initial )
      /* src = "libresoc.v:114940.9-114940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:114953.5-114953.29" *)
    casez (\initial )
      /* src = "libresoc.v:114953.9-114953.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:114966.5-114966.29" *)
    casez (\initial )
      /* src = "libresoc.v:114966.9-114966.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:114979.5-114979.29" *)
    casez (\initial )
      /* src = "libresoc.v:114979.9-114979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h0;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:114992.5-114992.29" *)
    casez (\initial )
      /* src = "libresoc.v:114992.9-114992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h0;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:115005.5-115005.29" *)
    casez (\initial )
      /* src = "libresoc.v:115005.9-115005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:115018.5-115018.29" *)
    casez (\initial )
      /* src = "libresoc.v:115018.9-115018.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:115031.5-115031.29" *)
    casez (\initial )
      /* src = "libresoc.v:115031.9-115031.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:115044.5-115044.29" *)
    casez (\initial )
      /* src = "libresoc.v:115044.9-115044.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub4_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:115061.1-116830.10" *)
module dec31_dec_sub8(dec31_dec_sub8_function_unit, dec31_dec_sub8_internal_op, dec31_dec_sub8_form, dec31_dec_sub8_asmcode, dec31_dec_sub8_SV_Etype, dec31_dec_sub8_SV_Ptype, dec31_dec_sub8_in1_sel, dec31_dec_sub8_in2_sel, dec31_dec_sub8_in3_sel, dec31_dec_sub8_out_sel, dec31_dec_sub8_cr_in, dec31_dec_sub8_cr_out, dec31_dec_sub8_sv_in1, dec31_dec_sub8_sv_in2, dec31_dec_sub8_sv_in3, dec31_dec_sub8_sv_out, dec31_dec_sub8_sv_out2, dec31_dec_sub8_sv_cr_in, dec31_dec_sub8_sv_cr_out, dec31_dec_sub8_ldst_len, dec31_dec_sub8_upd, dec31_dec_sub8_rc_sel, dec31_dec_sub8_cry_in, dec31_dec_sub8_inv_a, dec31_dec_sub8_inv_out, dec31_dec_sub8_cry_out, dec31_dec_sub8_br, dec31_dec_sub8_sgn_ext, dec31_dec_sub8_rsrv, dec31_dec_sub8_is_32b, dec31_dec_sub8_sgn, dec31_dec_sub8_lk, dec31_dec_sub8_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:116571.3-116613.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:116614.3-116656.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:116055.3-116097.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:116227.3-116269.6" *)
  reg _03_;
  (* src = "libresoc.v:115453.3-115495.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:115496.3-115538.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:116012.3-116054.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:116184.3-116226.6" *)
  reg _07_;
  (* src = "libresoc.v:116356.3-116398.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:115410.3-115452.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:116657.3-116699.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:116700.3-116742.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:116743.3-116785.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:115883.3-115925.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:116098.3-116140.6" *)
  reg _14_;
  (* src = "libresoc.v:116141.3-116183.6" *)
  reg _15_;
  (* src = "libresoc.v:116399.3-116441.6" *)
  reg _16_;
  (* src = "libresoc.v:115840.3-115882.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:116485.3-116527.6" *)
  reg _18_;
  (* src = "libresoc.v:116786.3-116828.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:115969.3-116011.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:116313.3-116355.6" *)
  reg _21_;
  (* src = "libresoc.v:116528.3-116570.6" *)
  reg _22_;
  (* src = "libresoc.v:116442.3-116484.6" *)
  reg _23_;
  (* src = "libresoc.v:116270.3-116312.6" *)
  reg _24_;
  (* src = "libresoc.v:115754.3-115796.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:115797.3-115839.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:115539.3-115581.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:115582.3-115624.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:115625.3-115667.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:115711.3-115753.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:115668.3-115710.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:115926.3-115968.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:115062.7-115062.20" *)
  reg _33_;
  (* src = "libresoc.v:116571.3-116613.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:116614.3-116656.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:116055.3-116097.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:116227.3-116269.6" *)
  reg _37_;
  (* src = "libresoc.v:115453.3-115495.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:115496.3-115538.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:116012.3-116054.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:116184.3-116226.6" *)
  reg _41_;
  (* src = "libresoc.v:116356.3-116398.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:115410.3-115452.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:116657.3-116699.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:116700.3-116742.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:116743.3-116785.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:115883.3-115925.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:116098.3-116140.6" *)
  reg _48_;
  (* src = "libresoc.v:116141.3-116183.6" *)
  reg _49_;
  (* src = "libresoc.v:116399.3-116441.6" *)
  reg _50_;
  (* src = "libresoc.v:115840.3-115882.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:116485.3-116527.6" *)
  reg _52_;
  (* src = "libresoc.v:116786.3-116828.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:115969.3-116011.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:116313.3-116355.6" *)
  reg _55_;
  (* src = "libresoc.v:116528.3-116570.6" *)
  reg _56_;
  (* src = "libresoc.v:116442.3-116484.6" *)
  reg _57_;
  (* src = "libresoc.v:116270.3-116312.6" *)
  reg _58_;
  (* src = "libresoc.v:115754.3-115796.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:115797.3-115839.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:115539.3-115581.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:115582.3-115624.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:115625.3-115667.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:115711.3-115753.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:115668.3-115710.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:115926.3-115968.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_SV_Etype;
  reg [1:0] dec31_dec_sub8_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_SV_Ptype;
  reg [1:0] dec31_dec_sub8_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub8_asmcode;
  reg [7:0] dec31_dec_sub8_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_br;
  reg dec31_dec_sub8_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_cr_in;
  reg [2:0] dec31_dec_sub8_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_cr_out;
  reg [2:0] dec31_dec_sub8_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_cry_in;
  reg [1:0] dec31_dec_sub8_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_cry_out;
  reg dec31_dec_sub8_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub8_form;
  reg [4:0] dec31_dec_sub8_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub8_function_unit;
  reg [13:0] dec31_dec_sub8_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_in1_sel;
  reg [2:0] dec31_dec_sub8_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub8_in2_sel;
  reg [3:0] dec31_dec_sub8_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_in3_sel;
  reg [1:0] dec31_dec_sub8_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub8_internal_op;
  reg [6:0] dec31_dec_sub8_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_inv_a;
  reg dec31_dec_sub8_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_inv_out;
  reg dec31_dec_sub8_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_is_32b;
  reg dec31_dec_sub8_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub8_ldst_len;
  reg [3:0] dec31_dec_sub8_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_lk;
  reg dec31_dec_sub8_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_out_sel;
  reg [2:0] dec31_dec_sub8_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_rc_sel;
  reg [1:0] dec31_dec_sub8_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_rsrv;
  reg dec31_dec_sub8_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_sgl_pipe;
  reg dec31_dec_sub8_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_sgn;
  reg dec31_dec_sub8_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub8_sgn_ext;
  reg dec31_dec_sub8_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_cr_in;
  reg [2:0] dec31_dec_sub8_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_cr_out;
  reg [2:0] dec31_dec_sub8_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_in1;
  reg [2:0] dec31_dec_sub8_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_in2;
  reg [2:0] dec31_dec_sub8_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_in3;
  reg [2:0] dec31_dec_sub8_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_out;
  reg [2:0] dec31_dec_sub8_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub8_sv_out2;
  reg [2:0] dec31_dec_sub8_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub8_upd;
  reg [1:0] dec31_dec_sub8_upd;
  (* src = "libresoc.v:115062.7-115062.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:115411.5-115411.29" *)
    casez (\initial )
      /* src = "libresoc.v:115411.9-115411.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _43_ = 14'h0002;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _43_ = 14'h0002;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub8_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:115454.5-115454.29" *)
    casez (\initial )
      /* src = "libresoc.v:115454.9-115454.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:115497.5-115497.29" *)
    casez (\initial )
      /* src = "libresoc.v:115497.9-115497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:115540.5-115540.29" *)
    casez (\initial )
      /* src = "libresoc.v:115540.9-115540.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:115583.5-115583.29" *)
    casez (\initial )
      /* src = "libresoc.v:115583.9-115583.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:115626.5-115626.29" *)
    casez (\initial )
      /* src = "libresoc.v:115626.9-115626.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:115669.5-115669.29" *)
    casez (\initial )
      /* src = "libresoc.v:115669.9-115669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:115712.5-115712.29" *)
    casez (\initial )
      /* src = "libresoc.v:115712.9-115712.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:115755.5-115755.29" *)
    casez (\initial )
      /* src = "libresoc.v:115755.9-115755.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:115798.5-115798.29" *)
    casez (\initial )
      /* src = "libresoc.v:115798.9-115798.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:115841.5-115841.29" *)
    casez (\initial )
      /* src = "libresoc.v:115841.9-115841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:115884.5-115884.29" *)
    casez (\initial )
      /* src = "libresoc.v:115884.9-115884.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _47_ = 7'h02;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _47_ = 7'h02;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub8_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:115927.5-115927.29" *)
    casez (\initial )
      /* src = "libresoc.v:115927.9-115927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:115970.5-115970.29" *)
    casez (\initial )
      /* src = "libresoc.v:115970.9-115970.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:116013.5-116013.29" *)
    casez (\initial )
      /* src = "libresoc.v:116013.9-116013.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _40_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _40_ = 2'h2;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:116056.5-116056.29" *)
    casez (\initial )
      /* src = "libresoc.v:116056.9-116056.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _36_ = 8'h84;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _36_ = 8'h85;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _36_ = 8'hbf;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _36_ = 8'hc7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'hc0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'hc1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _36_ = 8'hc2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _36_ = 8'hc3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'hc5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = 8'hc6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _36_ = 8'hc8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _36_ = 8'hc9;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub8_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:116099.5-116099.29" *)
    casez (\initial )
      /* src = "libresoc.v:116099.9-116099.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _48_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _48_ = 1'h1;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:116142.5-116142.29" *)
    casez (\initial )
      /* src = "libresoc.v:116142.9-116142.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:116185.5-116185.29" *)
    casez (\initial )
      /* src = "libresoc.v:116185.9-116185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _41_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _41_ = 1'h1;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:116228.5-116228.29" *)
    casez (\initial )
      /* src = "libresoc.v:116228.9-116228.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:116271.5-116271.29" *)
    casez (\initial )
      /* src = "libresoc.v:116271.9-116271.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:116314.5-116314.29" *)
    casez (\initial )
      /* src = "libresoc.v:116314.9-116314.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:116357.5-116357.29" *)
    casez (\initial )
      /* src = "libresoc.v:116357.9-116357.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _42_ = 5'h11;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub8_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:116400.5-116400.29" *)
    casez (\initial )
      /* src = "libresoc.v:116400.9-116400.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:116443.5-116443.29" *)
    casez (\initial )
      /* src = "libresoc.v:116443.9-116443.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:116486.5-116486.29" *)
    casez (\initial )
      /* src = "libresoc.v:116486.9-116486.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:116529.5-116529.29" *)
    casez (\initial )
      /* src = "libresoc.v:116529.9-116529.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:116572.5-116572.29" *)
    casez (\initial )
      /* src = "libresoc.v:116572.9-116572.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:116615.5-116615.29" *)
    casez (\initial )
      /* src = "libresoc.v:116615.9-116615.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:116658.5-116658.29" *)
    casez (\initial )
      /* src = "libresoc.v:116658.9-116658.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _44_ = 3'h1;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:116701.5-116701.29" *)
    casez (\initial )
      /* src = "libresoc.v:116701.9-116701.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = 4'h9;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _45_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _45_ = 4'h0;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:116744.5-116744.29" *)
    casez (\initial )
      /* src = "libresoc.v:116744.9-116744.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:116787.5-116787.29" *)
    casez (\initial )
      /* src = "libresoc.v:116787.9-116787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h03:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h13:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h01:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h11:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h04:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h14:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h06:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h16:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub8_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:116834.1-118999.10" *)
module dec31_dec_sub9(dec31_dec_sub9_function_unit, dec31_dec_sub9_internal_op, dec31_dec_sub9_form, dec31_dec_sub9_asmcode, dec31_dec_sub9_SV_Etype, dec31_dec_sub9_SV_Ptype, dec31_dec_sub9_in1_sel, dec31_dec_sub9_in2_sel, dec31_dec_sub9_in3_sel, dec31_dec_sub9_out_sel, dec31_dec_sub9_cr_in, dec31_dec_sub9_cr_out, dec31_dec_sub9_sv_in1, dec31_dec_sub9_sv_in2, dec31_dec_sub9_sv_in3, dec31_dec_sub9_sv_out, dec31_dec_sub9_sv_out2, dec31_dec_sub9_sv_cr_in, dec31_dec_sub9_sv_cr_out, dec31_dec_sub9_ldst_len, dec31_dec_sub9_upd, dec31_dec_sub9_rc_sel, dec31_dec_sub9_cry_in, dec31_dec_sub9_inv_a, dec31_dec_sub9_inv_out, dec31_dec_sub9_cry_out, dec31_dec_sub9_br, dec31_dec_sub9_sgn_ext, dec31_dec_sub9_rsrv, dec31_dec_sub9_is_32b, dec31_dec_sub9_sgn, dec31_dec_sub9_lk, dec31_dec_sub9_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:118668.3-118722.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:118723.3-118777.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:118008.3-118062.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:118228.3-118282.6" *)
  reg _03_;
  (* src = "libresoc.v:117238.3-117292.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:117293.3-117347.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:117953.3-118007.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:118173.3-118227.6" *)
  reg _07_;
  (* src = "libresoc.v:118393.3-118447.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:117183.3-117237.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:118778.3-118832.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:118833.3-118887.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:118888.3-118942.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:117788.3-117842.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:118063.3-118117.6" *)
  reg _14_;
  (* src = "libresoc.v:118118.3-118172.6" *)
  reg _15_;
  (* src = "libresoc.v:118448.3-118502.6" *)
  reg _16_;
  (* src = "libresoc.v:117733.3-117787.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:118558.3-118612.6" *)
  reg _18_;
  (* src = "libresoc.v:118943.3-118997.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:117898.3-117952.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:118338.3-118392.6" *)
  reg _21_;
  (* src = "libresoc.v:118613.3-118667.6" *)
  reg _22_;
  (* src = "libresoc.v:118503.3-118557.6" *)
  reg _23_;
  (* src = "libresoc.v:118283.3-118337.6" *)
  reg _24_;
  (* src = "libresoc.v:117623.3-117677.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:117678.3-117732.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:117348.3-117402.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:117403.3-117457.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:117458.3-117512.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:117568.3-117622.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:117513.3-117567.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:117843.3-117897.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:116835.7-116835.20" *)
  reg _33_;
  (* src = "libresoc.v:118668.3-118722.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:118723.3-118777.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:118008.3-118062.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:118228.3-118282.6" *)
  reg _37_;
  (* src = "libresoc.v:117238.3-117292.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:117293.3-117347.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:117953.3-118007.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:118173.3-118227.6" *)
  reg _41_;
  (* src = "libresoc.v:118393.3-118447.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:117183.3-117237.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:118778.3-118832.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:118833.3-118887.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:118888.3-118942.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:117788.3-117842.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:118063.3-118117.6" *)
  reg _48_;
  (* src = "libresoc.v:118118.3-118172.6" *)
  reg _49_;
  (* src = "libresoc.v:118448.3-118502.6" *)
  reg _50_;
  (* src = "libresoc.v:117733.3-117787.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:118558.3-118612.6" *)
  reg _52_;
  (* src = "libresoc.v:118943.3-118997.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:117898.3-117952.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:118338.3-118392.6" *)
  reg _55_;
  (* src = "libresoc.v:118613.3-118667.6" *)
  reg _56_;
  (* src = "libresoc.v:118503.3-118557.6" *)
  reg _57_;
  (* src = "libresoc.v:118283.3-118337.6" *)
  reg _58_;
  (* src = "libresoc.v:117623.3-117677.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:117678.3-117732.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:117348.3-117402.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:117403.3-117457.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:117458.3-117512.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:117568.3-117622.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:117513.3-117567.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:117843.3-117897.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_SV_Etype;
  reg [1:0] dec31_dec_sub9_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_SV_Ptype;
  reg [1:0] dec31_dec_sub9_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec31_dec_sub9_asmcode;
  reg [7:0] dec31_dec_sub9_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_br;
  reg dec31_dec_sub9_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_cr_in;
  reg [2:0] dec31_dec_sub9_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_cr_out;
  reg [2:0] dec31_dec_sub9_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_cry_in;
  reg [1:0] dec31_dec_sub9_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_cry_out;
  reg dec31_dec_sub9_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec31_dec_sub9_form;
  reg [4:0] dec31_dec_sub9_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec31_dec_sub9_function_unit;
  reg [13:0] dec31_dec_sub9_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_in1_sel;
  reg [2:0] dec31_dec_sub9_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub9_in2_sel;
  reg [3:0] dec31_dec_sub9_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_in3_sel;
  reg [1:0] dec31_dec_sub9_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec31_dec_sub9_internal_op;
  reg [6:0] dec31_dec_sub9_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_inv_a;
  reg dec31_dec_sub9_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_inv_out;
  reg dec31_dec_sub9_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_is_32b;
  reg dec31_dec_sub9_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec31_dec_sub9_ldst_len;
  reg [3:0] dec31_dec_sub9_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_lk;
  reg dec31_dec_sub9_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_out_sel;
  reg [2:0] dec31_dec_sub9_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_rc_sel;
  reg [1:0] dec31_dec_sub9_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_rsrv;
  reg dec31_dec_sub9_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_sgl_pipe;
  reg dec31_dec_sub9_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_sgn;
  reg dec31_dec_sub9_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec31_dec_sub9_sgn_ext;
  reg dec31_dec_sub9_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_cr_in;
  reg [2:0] dec31_dec_sub9_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_cr_out;
  reg [2:0] dec31_dec_sub9_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_in1;
  reg [2:0] dec31_dec_sub9_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_in2;
  reg [2:0] dec31_dec_sub9_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_in3;
  reg [2:0] dec31_dec_sub9_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_out;
  reg [2:0] dec31_dec_sub9_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec31_dec_sub9_sv_out2;
  reg [2:0] dec31_dec_sub9_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec31_dec_sub9_upd;
  reg [1:0] dec31_dec_sub9_upd;
  (* src = "libresoc.v:116835.7-116835.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [4:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:117184.5-117184.29" *)
    casez (\initial )
      /* src = "libresoc.v:117184.9-117184.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _43_ = 14'h0200;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _43_ = 14'h0100;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _43_ = 14'h0100;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec31_dec_sub9_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:117239.5-117239.29" *)
    casez (\initial )
      /* src = "libresoc.v:117239.9-117239.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:117294.5-117294.29" *)
    casez (\initial )
      /* src = "libresoc.v:117294.9-117294.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _39_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _39_ = 3'h1;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:117349.5-117349.29" *)
    casez (\initial )
      /* src = "libresoc.v:117349.9-117349.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:117404.5-117404.29" *)
    casez (\initial )
      /* src = "libresoc.v:117404.9-117404.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _62_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _62_ = 3'h3;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:117459.5-117459.29" *)
    casez (\initial )
      /* src = "libresoc.v:117459.9-117459.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:117514.5-117514.29" *)
    casez (\initial )
      /* src = "libresoc.v:117514.9-117514.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:117569.5-117569.29" *)
    casez (\initial )
      /* src = "libresoc.v:117569.9-117569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:117624.5-117624.29" *)
    casez (\initial )
      /* src = "libresoc.v:117624.9-117624.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:117679.5-117679.29" *)
    casez (\initial )
      /* src = "libresoc.v:117679.9-117679.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _60_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _60_ = 3'h1;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:117734.5-117734.29" *)
    casez (\initial )
      /* src = "libresoc.v:117734.9-117734.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _51_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _51_ = 4'h0;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:117789.5-117789.29" *)
    casez (\initial )
      /* src = "libresoc.v:117789.9-117789.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _47_ = 7'h1e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _47_ = 7'h1d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _47_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _47_ = 7'h2f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _47_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _47_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _47_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _47_ = 7'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _47_ = 7'h32;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _47_ = 7'h32;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub9_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:117844.5-117844.29" *)
    casez (\initial )
      /* src = "libresoc.v:117844.9-117844.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:117899.5-117899.29" *)
    casez (\initial )
      /* src = "libresoc.v:117899.9-117899.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _54_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _54_ = 2'h2;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:117954.5-117954.29" *)
    casez (\initial )
      /* src = "libresoc.v:117954.9-117954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:118009.5-118009.29" *)
    casez (\initial )
      /* src = "libresoc.v:118009.9-118009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _36_ = 8'h36;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _36_ = 8'h37;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _36_ = 8'h34;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _36_ = 8'h35;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _36_ = 8'h39;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _36_ = 8'h3a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _36_ = 8'h33;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _36_ = 8'h38;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _36_ = 8'h74;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _36_ = 8'h72;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _36_ = 8'h7a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _36_ = 8'h7b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _36_ = 8'h7a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _36_ = 8'h7b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _36_ = 8'h7e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _36_ = 8'h7f;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub9_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:118064.5-118064.29" *)
    casez (\initial )
      /* src = "libresoc.v:118064.9-118064.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:118119.5-118119.29" *)
    casez (\initial )
      /* src = "libresoc.v:118119.9-118119.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:118174.5-118174.29" *)
    casez (\initial )
      /* src = "libresoc.v:118174.9-118174.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:118229.5-118229.29" *)
    casez (\initial )
      /* src = "libresoc.v:118229.9-118229.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:118284.5-118284.29" *)
    casez (\initial )
      /* src = "libresoc.v:118284.9-118284.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:118339.5-118339.29" *)
    casez (\initial )
      /* src = "libresoc.v:118339.9-118339.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:118394.5-118394.29" *)
    casez (\initial )
      /* src = "libresoc.v:118394.9-118394.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _42_ = 5'h08;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _42_ = 5'h11;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _42_ = 5'h11;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec31_dec_sub9_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:118449.5-118449.29" *)
    casez (\initial )
      /* src = "libresoc.v:118449.9-118449.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:118504.5-118504.29" *)
    casez (\initial )
      /* src = "libresoc.v:118504.9-118504.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _57_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _57_ = 1'h1;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:118559.5-118559.29" *)
    casez (\initial )
      /* src = "libresoc.v:118559.9-118559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:118614.5-118614.29" *)
    casez (\initial )
      /* src = "libresoc.v:118614.9-118614.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _56_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _56_ = 1'h0;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:118669.5-118669.29" *)
    casez (\initial )
      /* src = "libresoc.v:118669.9-118669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:118724.5-118724.29" *)
    casez (\initial )
      /* src = "libresoc.v:118724.9-118724.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _35_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _35_ = 2'h1;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:118779.5-118779.29" *)
    casez (\initial )
      /* src = "libresoc.v:118779.9-118779.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _44_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _44_ = 3'h1;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:118834.5-118834.29" *)
    casez (\initial )
      /* src = "libresoc.v:118834.9-118834.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _45_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _45_ = 4'h1;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:118889.5-118889.29" *)
    casez (\initial )
      /* src = "libresoc.v:118889.9-118889.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:118944.5-118944.29" *)
    casez (\initial )
      /* src = "libresoc.v:118944.9-118944.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      5'h0c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1c:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1d:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1e:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h0f:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h1f:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h08:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h18:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h02:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h00:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h12:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h10:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h07:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      5'h17:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec31_dec_sub9_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec58" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:119003.1-119881.10" *)
module dec58(dec58_function_unit, dec58_internal_op, dec58_form, dec58_asmcode, dec58_SV_Etype, dec58_SV_Ptype, dec58_in1_sel, dec58_in2_sel, dec58_in3_sel, dec58_out_sel, dec58_cr_in, dec58_cr_out, dec58_sv_in1, dec58_sv_in2, dec58_sv_in3, dec58_sv_out, dec58_sv_out2, dec58_sv_cr_in, dec58_sv_cr_out, dec58_ldst_len, dec58_upd, dec58_rc_sel, dec58_cry_in, dec58_inv_a, dec58_inv_out, dec58_cry_out, dec58_br, dec58_sgn_ext, dec58_rsrv, dec58_is_32b, dec58_sgn, dec58_lk, dec58_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:119784.3-119799.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:119800.3-119815.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:119592.3-119607.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:119656.3-119671.6" *)
  reg _03_;
  (* src = "libresoc.v:119368.3-119383.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:119384.3-119399.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:119576.3-119591.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:119640.3-119655.6" *)
  reg _07_;
  (* src = "libresoc.v:119704.3-119719.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:119352.3-119367.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:119816.3-119831.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:119832.3-119847.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:119848.3-119863.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:119528.3-119543.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:119608.3-119623.6" *)
  reg _14_;
  (* src = "libresoc.v:119624.3-119639.6" *)
  reg _15_;
  (* src = "libresoc.v:119720.3-119735.6" *)
  reg _16_;
  (* src = "libresoc.v:119512.3-119527.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:119752.3-119767.6" *)
  reg _18_;
  (* src = "libresoc.v:119864.3-119879.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:119560.3-119575.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:119688.3-119703.6" *)
  reg _21_;
  (* src = "libresoc.v:119768.3-119783.6" *)
  reg _22_;
  (* src = "libresoc.v:119736.3-119751.6" *)
  reg _23_;
  (* src = "libresoc.v:119672.3-119687.6" *)
  reg _24_;
  (* src = "libresoc.v:119480.3-119495.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:119496.3-119511.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:119400.3-119415.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:119416.3-119431.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:119432.3-119447.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:119464.3-119479.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:119448.3-119463.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:119544.3-119559.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:119004.7-119004.20" *)
  reg _33_;
  (* src = "libresoc.v:119784.3-119799.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:119800.3-119815.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:119592.3-119607.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:119656.3-119671.6" *)
  reg _37_;
  (* src = "libresoc.v:119368.3-119383.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:119384.3-119399.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:119576.3-119591.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:119640.3-119655.6" *)
  reg _41_;
  (* src = "libresoc.v:119704.3-119719.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:119352.3-119367.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:119816.3-119831.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:119832.3-119847.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:119848.3-119863.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:119528.3-119543.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:119608.3-119623.6" *)
  reg _48_;
  (* src = "libresoc.v:119624.3-119639.6" *)
  reg _49_;
  (* src = "libresoc.v:119720.3-119735.6" *)
  reg _50_;
  (* src = "libresoc.v:119512.3-119527.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:119752.3-119767.6" *)
  reg _52_;
  (* src = "libresoc.v:119864.3-119879.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:119560.3-119575.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:119688.3-119703.6" *)
  reg _55_;
  (* src = "libresoc.v:119768.3-119783.6" *)
  reg _56_;
  (* src = "libresoc.v:119736.3-119751.6" *)
  reg _57_;
  (* src = "libresoc.v:119672.3-119687.6" *)
  reg _58_;
  (* src = "libresoc.v:119480.3-119495.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:119496.3-119511.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:119400.3-119415.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:119416.3-119431.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:119432.3-119447.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:119464.3-119479.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:119448.3-119463.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:119544.3-119559.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_SV_Etype;
  reg [1:0] dec58_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_SV_Ptype;
  reg [1:0] dec58_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec58_asmcode;
  reg [7:0] dec58_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_br;
  reg dec58_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_cr_in;
  reg [2:0] dec58_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_cr_out;
  reg [2:0] dec58_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_cry_in;
  reg [1:0] dec58_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_cry_out;
  reg dec58_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec58_form;
  reg [4:0] dec58_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec58_function_unit;
  reg [13:0] dec58_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_in1_sel;
  reg [2:0] dec58_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec58_in2_sel;
  reg [3:0] dec58_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_in3_sel;
  reg [1:0] dec58_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec58_internal_op;
  reg [6:0] dec58_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_inv_a;
  reg dec58_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_inv_out;
  reg dec58_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_is_32b;
  reg dec58_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec58_ldst_len;
  reg [3:0] dec58_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_lk;
  reg dec58_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_out_sel;
  reg [2:0] dec58_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_rc_sel;
  reg [1:0] dec58_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_rsrv;
  reg dec58_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_sgl_pipe;
  reg dec58_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_sgn;
  reg dec58_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec58_sgn_ext;
  reg dec58_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_cr_in;
  reg [2:0] dec58_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_cr_out;
  reg [2:0] dec58_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_in1;
  reg [2:0] dec58_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_in2;
  reg [2:0] dec58_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_in3;
  reg [2:0] dec58_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_out;
  reg [2:0] dec58_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec58_sv_out2;
  reg [2:0] dec58_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec58_upd;
  reg [1:0] dec58_upd;
  (* src = "libresoc.v:119004.7-119004.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [1:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:119353.5-119353.29" *)
    casez (\initial )
      /* src = "libresoc.v:119353.9-119353.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _43_ = 14'h0004;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec58_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:119369.5-119369.29" *)
    casez (\initial )
      /* src = "libresoc.v:119369.9-119369.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:119385.5-119385.29" *)
    casez (\initial )
      /* src = "libresoc.v:119385.9-119385.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:119401.5-119401.29" *)
    casez (\initial )
      /* src = "libresoc.v:119401.9-119401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _61_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _61_ = 3'h2;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:119417.5-119417.29" *)
    casez (\initial )
      /* src = "libresoc.v:119417.9-119417.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:119433.5-119433.29" *)
    casez (\initial )
      /* src = "libresoc.v:119433.9-119433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _63_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _63_ = 3'h0;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:119449.5-119449.29" *)
    casez (\initial )
      /* src = "libresoc.v:119449.9-119449.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _65_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _65_ = 3'h1;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:119465.5-119465.29" *)
    casez (\initial )
      /* src = "libresoc.v:119465.9-119465.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _64_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _64_ = 3'h0;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:119481.5-119481.29" *)
    casez (\initial )
      /* src = "libresoc.v:119481.9-119481.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:119497.5-119497.29" *)
    casez (\initial )
      /* src = "libresoc.v:119497.9-119497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:119513.5-119513.29" *)
    casez (\initial )
      /* src = "libresoc.v:119513.9-119513.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _51_ = 4'h4;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec58_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:119529.5-119529.29" *)
    casez (\initial )
      /* src = "libresoc.v:119529.9-119529.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _47_ = 7'h25;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _47_ = 7'h25;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec58_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:119545.5-119545.29" *)
    casez (\initial )
      /* src = "libresoc.v:119545.9-119545.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _66_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _66_ = 2'h0;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:119561.5-119561.29" *)
    casez (\initial )
      /* src = "libresoc.v:119561.9-119561.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:119577.5-119577.29" *)
    casez (\initial )
      /* src = "libresoc.v:119577.9-119577.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:119593.5-119593.29" *)
    casez (\initial )
      /* src = "libresoc.v:119593.9-119593.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _36_ = 8'h52;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _36_ = 8'h55;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _36_ = 8'h62;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec58_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:119609.5-119609.29" *)
    casez (\initial )
      /* src = "libresoc.v:119609.9-119609.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:119625.5-119625.29" *)
    casez (\initial )
      /* src = "libresoc.v:119625.9-119625.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:119641.5-119641.29" *)
    casez (\initial )
      /* src = "libresoc.v:119641.9-119641.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:119657.5-119657.29" *)
    casez (\initial )
      /* src = "libresoc.v:119657.9-119657.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:119673.5-119673.29" *)
    casez (\initial )
      /* src = "libresoc.v:119673.9-119673.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _58_ = 1'h1;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:119689.5-119689.29" *)
    casez (\initial )
      /* src = "libresoc.v:119689.9-119689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:119705.5-119705.29" *)
    casez (\initial )
      /* src = "libresoc.v:119705.9-119705.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _42_ = 5'h05;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _42_ = 5'h05;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _42_ = 5'h05;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec58_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:119721.5-119721.29" *)
    casez (\initial )
      /* src = "libresoc.v:119721.9-119721.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:119737.5-119737.29" *)
    casez (\initial )
      /* src = "libresoc.v:119737.9-119737.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:119753.5-119753.29" *)
    casez (\initial )
      /* src = "libresoc.v:119753.9-119753.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:119769.5-119769.29" *)
    casez (\initial )
      /* src = "libresoc.v:119769.9-119769.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec58_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:119785.5-119785.29" *)
    casez (\initial )
      /* src = "libresoc.v:119785.9-119785.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _34_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _34_ = 2'h2;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:119801.5-119801.29" *)
    casez (\initial )
      /* src = "libresoc.v:119801.9-119801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:119817.5-119817.29" *)
    casez (\initial )
      /* src = "libresoc.v:119817.9-119817.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:119833.5-119833.29" *)
    casez (\initial )
      /* src = "libresoc.v:119833.9-119833.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _45_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _45_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _45_ = 4'h8;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec58_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:119849.5-119849.29" *)
    casez (\initial )
      /* src = "libresoc.v:119849.9-119849.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _46_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _46_ = 2'h0;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec58_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:119865.5-119865.29" *)
    casez (\initial )
      /* src = "libresoc.v:119865.9-119865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _53_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _53_ = 3'h1;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec58_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec.dec62" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:119885.1-120664.10" *)
module dec62(dec62_function_unit, dec62_internal_op, dec62_form, dec62_asmcode, dec62_SV_Etype, dec62_SV_Ptype, dec62_in1_sel, dec62_in2_sel, dec62_in3_sel, dec62_out_sel, dec62_cr_in, dec62_cr_out, dec62_sv_in1, dec62_sv_in2, dec62_sv_in3, dec62_sv_out, dec62_sv_out2, dec62_sv_cr_in, dec62_sv_cr_out, dec62_ldst_len, dec62_upd, dec62_rc_sel, dec62_cry_in, dec62_inv_a, dec62_inv_out, dec62_cry_out, dec62_br, dec62_sgn_ext, dec62_rsrv, dec62_is_32b, dec62_sgn, dec62_lk, dec62_sgl_pipe, opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:120585.3-120597.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:120598.3-120610.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:120429.3-120441.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:120481.3-120493.6" *)
  reg _03_;
  (* src = "libresoc.v:120247.3-120259.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:120260.3-120272.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:120416.3-120428.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:120468.3-120480.6" *)
  reg _07_;
  (* src = "libresoc.v:120520.3-120532.6" *)
  reg [4:0] _08_;
  (* src = "libresoc.v:120234.3-120246.6" *)
  reg [13:0] _09_;
  (* src = "libresoc.v:120611.3-120623.6" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:120624.3-120636.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:120637.3-120649.6" *)
  reg [1:0] _12_;
  (* src = "libresoc.v:120377.3-120389.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:120442.3-120454.6" *)
  reg _14_;
  (* src = "libresoc.v:120455.3-120467.6" *)
  reg _15_;
  (* src = "libresoc.v:120533.3-120545.6" *)
  reg _16_;
  (* src = "libresoc.v:120364.3-120376.6" *)
  reg [3:0] _17_;
  (* src = "libresoc.v:120559.3-120571.6" *)
  reg _18_;
  (* src = "libresoc.v:120650.3-120662.6" *)
  reg [2:0] _19_;
  (* src = "libresoc.v:120403.3-120415.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:120507.3-120519.6" *)
  reg _21_;
  (* src = "libresoc.v:120572.3-120584.6" *)
  reg _22_;
  (* src = "libresoc.v:120546.3-120558.6" *)
  reg _23_;
  (* src = "libresoc.v:120494.3-120506.6" *)
  reg _24_;
  (* src = "libresoc.v:120338.3-120350.6" *)
  reg [2:0] _25_;
  (* src = "libresoc.v:120351.3-120363.6" *)
  reg [2:0] _26_;
  (* src = "libresoc.v:120273.3-120285.6" *)
  reg [2:0] _27_;
  (* src = "libresoc.v:120286.3-120298.6" *)
  reg [2:0] _28_;
  (* src = "libresoc.v:120299.3-120311.6" *)
  reg [2:0] _29_;
  (* src = "libresoc.v:120325.3-120337.6" *)
  reg [2:0] _30_;
  (* src = "libresoc.v:120312.3-120324.6" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:120390.3-120402.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:119886.7-119886.20" *)
  reg _33_;
  (* src = "libresoc.v:120585.3-120597.6" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:120598.3-120610.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:120429.3-120441.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:120481.3-120493.6" *)
  reg _37_;
  (* src = "libresoc.v:120247.3-120259.6" *)
  reg [2:0] _38_;
  (* src = "libresoc.v:120260.3-120272.6" *)
  reg [2:0] _39_;
  (* src = "libresoc.v:120416.3-120428.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:120468.3-120480.6" *)
  reg _41_;
  (* src = "libresoc.v:120520.3-120532.6" *)
  reg [4:0] _42_;
  (* src = "libresoc.v:120234.3-120246.6" *)
  reg [13:0] _43_;
  (* src = "libresoc.v:120611.3-120623.6" *)
  reg [2:0] _44_;
  (* src = "libresoc.v:120624.3-120636.6" *)
  reg [3:0] _45_;
  (* src = "libresoc.v:120637.3-120649.6" *)
  reg [1:0] _46_;
  (* src = "libresoc.v:120377.3-120389.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:120442.3-120454.6" *)
  reg _48_;
  (* src = "libresoc.v:120455.3-120467.6" *)
  reg _49_;
  (* src = "libresoc.v:120533.3-120545.6" *)
  reg _50_;
  (* src = "libresoc.v:120364.3-120376.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:120559.3-120571.6" *)
  reg _52_;
  (* src = "libresoc.v:120650.3-120662.6" *)
  reg [2:0] _53_;
  (* src = "libresoc.v:120403.3-120415.6" *)
  reg [1:0] _54_;
  (* src = "libresoc.v:120507.3-120519.6" *)
  reg _55_;
  (* src = "libresoc.v:120572.3-120584.6" *)
  reg _56_;
  (* src = "libresoc.v:120546.3-120558.6" *)
  reg _57_;
  (* src = "libresoc.v:120494.3-120506.6" *)
  reg _58_;
  (* src = "libresoc.v:120338.3-120350.6" *)
  reg [2:0] _59_;
  (* src = "libresoc.v:120351.3-120363.6" *)
  reg [2:0] _60_;
  (* src = "libresoc.v:120273.3-120285.6" *)
  reg [2:0] _61_;
  (* src = "libresoc.v:120286.3-120298.6" *)
  reg [2:0] _62_;
  (* src = "libresoc.v:120299.3-120311.6" *)
  reg [2:0] _63_;
  (* src = "libresoc.v:120325.3-120337.6" *)
  reg [2:0] _64_;
  (* src = "libresoc.v:120312.3-120324.6" *)
  reg [2:0] _65_;
  (* src = "libresoc.v:120390.3-120402.6" *)
  reg [1:0] _66_;
  (* enum_base_type = "SVEtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "EXTRA2" *)
  (* enum_value_10 = "EXTRA3" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_SV_Etype;
  reg [1:0] dec62_SV_Etype;
  (* enum_base_type = "SVPtype" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "P1" *)
  (* enum_value_10 = "P2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_SV_Ptype;
  reg [1:0] dec62_SV_Ptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [7:0] dec62_asmcode;
  reg [7:0] dec62_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_br;
  reg dec62_br;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_cr_in;
  reg [2:0] dec62_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_cr_out;
  reg [2:0] dec62_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_cry_in;
  reg [1:0] dec62_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_cry_out;
  reg dec62_cry_out;
  (* enum_base_type = "Form" *)
  (* enum_value_00000 = "NONE" *)
  (* enum_value_00001 = "I" *)
  (* enum_value_00010 = "B" *)
  (* enum_value_00011 = "SC" *)
  (* enum_value_00100 = "D" *)
  (* enum_value_00101 = "DS" *)
  (* enum_value_00110 = "DQ" *)
  (* enum_value_00111 = "DX" *)
  (* enum_value_01000 = "X" *)
  (* enum_value_01001 = "XL" *)
  (* enum_value_01010 = "XFX" *)
  (* enum_value_01011 = "XFL" *)
  (* enum_value_01100 = "XX1" *)
  (* enum_value_01101 = "XX2" *)
  (* enum_value_01110 = "XX3" *)
  (* enum_value_01111 = "XX4" *)
  (* enum_value_10000 = "XS" *)
  (* enum_value_10001 = "XO" *)
  (* enum_value_10010 = "A" *)
  (* enum_value_10011 = "M" *)
  (* enum_value_10100 = "MD" *)
  (* enum_value_10101 = "MDS" *)
  (* enum_value_10110 = "VA" *)
  (* enum_value_10111 = "VC" *)
  (* enum_value_11000 = "VX" *)
  (* enum_value_11001 = "EVX" *)
  (* enum_value_11010 = "EVS" *)
  (* enum_value_11011 = "Z22" *)
  (* enum_value_11100 = "Z23" *)
  (* enum_value_11101 = "SVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [4:0] dec62_form;
  reg [4:0] dec62_form;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [13:0] dec62_function_unit;
  reg [13:0] dec62_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_in1_sel;
  reg [2:0] dec62_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec62_in2_sel;
  reg [3:0] dec62_in2_sel;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_in3_sel;
  reg [1:0] dec62_in3_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [6:0] dec62_internal_op;
  reg [6:0] dec62_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_inv_a;
  reg dec62_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_inv_out;
  reg dec62_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_is_32b;
  reg dec62_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [3:0] dec62_ldst_len;
  reg [3:0] dec62_ldst_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_lk;
  reg dec62_lk;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_out_sel;
  reg [2:0] dec62_out_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_rc_sel;
  reg [1:0] dec62_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_rsrv;
  reg dec62_rsrv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_sgl_pipe;
  reg dec62_sgl_pipe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_sgn;
  reg dec62_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  output dec62_sgn_ext;
  reg dec62_sgn_ext;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_cr_in;
  reg [2:0] dec62_sv_cr_in;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_cr_out;
  reg [2:0] dec62_sv_cr_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_in1;
  reg [2:0] dec62_sv_in1;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_in2;
  reg [2:0] dec62_sv_in2;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_in3;
  reg [2:0] dec62_sv_in3;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_out;
  reg [2:0] dec62_sv_out;
  (* enum_base_type = "SVEXTRA" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "Idx0" *)
  (* enum_value_010 = "Idx1" *)
  (* enum_value_011 = "Idx2" *)
  (* enum_value_100 = "Idx3" *)
  (* enum_value_101 = "Idx_1_2" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [2:0] dec62_sv_out2;
  reg [2:0] dec62_sv_out2;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  output [1:0] dec62_upd;
  reg [1:0] dec62_upd;
  (* src = "libresoc.v:119886.7-119886.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  input [31:0] opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" *)
  wire [1:0] opcode_switch;
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
      \initial  <= _33_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _43_;
    (* src = "libresoc.v:120235.5-120235.29" *)
    casez (\initial )
      /* src = "libresoc.v:120235.9-120235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _43_ = 14'h0004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _43_ = 14'h0004;
        end
      default:
          _43_ = 14'h0000;
    endcase
  end
  always @* begin
      dec62_function_unit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _38_;
    (* src = "libresoc.v:120248.5-120248.29" *)
    casez (\initial )
      /* src = "libresoc.v:120248.9-120248.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _38_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _38_ = 3'h0;
        end
      default:
          _38_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_cr_in <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _39_;
    (* src = "libresoc.v:120261.5-120261.29" *)
    casez (\initial )
      /* src = "libresoc.v:120261.9-120261.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _39_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _39_ = 3'h0;
        end
      default:
          _39_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_cr_out <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _61_;
    (* src = "libresoc.v:120274.5-120274.29" *)
    casez (\initial )
      /* src = "libresoc.v:120274.9-120274.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _61_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _61_ = 3'h3;
        end
      default:
          _61_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_in1 <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _62_;
    (* src = "libresoc.v:120287.5-120287.29" *)
    casez (\initial )
      /* src = "libresoc.v:120287.9-120287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _62_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _62_ = 3'h0;
        end
      default:
          _62_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_in2 <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _63_;
    (* src = "libresoc.v:120300.5-120300.29" *)
    casez (\initial )
      /* src = "libresoc.v:120300.9-120300.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _63_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _63_ = 3'h2;
        end
      default:
          _63_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_in3 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _65_;
    (* src = "libresoc.v:120313.5-120313.29" *)
    casez (\initial )
      /* src = "libresoc.v:120313.9-120313.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _65_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _65_ = 3'h0;
        end
      default:
          _65_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_out <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _64_;
    (* src = "libresoc.v:120326.5-120326.29" *)
    casez (\initial )
      /* src = "libresoc.v:120326.9-120326.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _64_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _64_ = 3'h1;
        end
      default:
          _64_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_out2 <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _59_;
    (* src = "libresoc.v:120339.5-120339.29" *)
    casez (\initial )
      /* src = "libresoc.v:120339.9-120339.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _59_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _59_ = 3'h0;
        end
      default:
          _59_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_cr_in <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _60_;
    (* src = "libresoc.v:120352.5-120352.29" *)
    casez (\initial )
      /* src = "libresoc.v:120352.9-120352.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _60_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _60_ = 3'h0;
        end
      default:
          _60_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_sv_cr_out <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _51_;
    (* src = "libresoc.v:120365.5-120365.29" *)
    casez (\initial )
      /* src = "libresoc.v:120365.9-120365.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _51_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _51_ = 4'h8;
        end
      default:
          _51_ = 4'h0;
    endcase
  end
  always @* begin
      dec62_ldst_len <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _47_;
    (* src = "libresoc.v:120378.5-120378.29" *)
    casez (\initial )
      /* src = "libresoc.v:120378.9-120378.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _47_ = 7'h26;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _47_ = 7'h26;
        end
      default:
          _47_ = 7'h00;
    endcase
  end
  always @* begin
      dec62_internal_op <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _66_;
    (* src = "libresoc.v:120391.5-120391.29" *)
    casez (\initial )
      /* src = "libresoc.v:120391.9-120391.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _66_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _66_ = 2'h1;
        end
      default:
          _66_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_upd <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _54_;
    (* src = "libresoc.v:120404.5-120404.29" *)
    casez (\initial )
      /* src = "libresoc.v:120404.9-120404.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _54_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _54_ = 2'h0;
        end
      default:
          _54_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_rc_sel <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _40_;
    (* src = "libresoc.v:120417.5-120417.29" *)
    casez (\initial )
      /* src = "libresoc.v:120417.9-120417.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _40_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _40_ = 2'h0;
        end
      default:
          _40_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_cry_in <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _36_;
    (* src = "libresoc.v:120430.5-120430.29" *)
    casez (\initial )
      /* src = "libresoc.v:120430.9-120430.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _36_ = 8'had;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _36_ = 8'hb0;
        end
      default:
          _36_ = 8'h00;
    endcase
  end
  always @* begin
      dec62_asmcode <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _48_;
    (* src = "libresoc.v:120443.5-120443.29" *)
    casez (\initial )
      /* src = "libresoc.v:120443.9-120443.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _48_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_inv_a <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _49_;
    (* src = "libresoc.v:120456.5-120456.29" *)
    casez (\initial )
      /* src = "libresoc.v:120456.9-120456.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _49_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _49_ = 1'h0;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_inv_out <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _41_;
    (* src = "libresoc.v:120469.5-120469.29" *)
    casez (\initial )
      /* src = "libresoc.v:120469.9-120469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _41_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _41_ = 1'h0;
        end
      default:
          _41_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_cry_out <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _37_;
    (* src = "libresoc.v:120482.5-120482.29" *)
    casez (\initial )
      /* src = "libresoc.v:120482.9-120482.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _37_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_br <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _58_;
    (* src = "libresoc.v:120495.5-120495.29" *)
    casez (\initial )
      /* src = "libresoc.v:120495.9-120495.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _58_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _58_ = 1'h0;
        end
      default:
          _58_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_sgn_ext <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _55_;
    (* src = "libresoc.v:120508.5-120508.29" *)
    casez (\initial )
      /* src = "libresoc.v:120508.9-120508.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _55_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_rsrv <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _42_;
    (* src = "libresoc.v:120521.5-120521.29" *)
    casez (\initial )
      /* src = "libresoc.v:120521.9-120521.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _42_ = 5'h05;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _42_ = 5'h05;
        end
      default:
          _42_ = 5'h00;
    endcase
  end
  always @* begin
      dec62_form <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _50_;
    (* src = "libresoc.v:120534.5-120534.29" *)
    casez (\initial )
      /* src = "libresoc.v:120534.9-120534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _50_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _50_ = 1'h0;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_is_32b <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _57_;
    (* src = "libresoc.v:120547.5-120547.29" *)
    casez (\initial )
      /* src = "libresoc.v:120547.9-120547.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _57_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _57_ = 1'h0;
        end
      default:
          _57_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_sgn <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _52_;
    (* src = "libresoc.v:120560.5-120560.29" *)
    casez (\initial )
      /* src = "libresoc.v:120560.9-120560.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _52_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _52_ = 1'h0;
        end
      default:
          _52_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_lk <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _56_;
    (* src = "libresoc.v:120573.5-120573.29" *)
    casez (\initial )
      /* src = "libresoc.v:120573.9-120573.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _56_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _56_ = 1'h1;
        end
      default:
          _56_ = 1'h0;
    endcase
  end
  always @* begin
      dec62_sgl_pipe <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _34_;
    (* src = "libresoc.v:120586.5-120586.29" *)
    casez (\initial )
      /* src = "libresoc.v:120586.9-120586.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _34_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _34_ = 2'h1;
        end
      default:
          _34_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_SV_Etype <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _35_;
    (* src = "libresoc.v:120599.5-120599.29" *)
    casez (\initial )
      /* src = "libresoc.v:120599.9-120599.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _35_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _35_ = 2'h2;
        end
      default:
          _35_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_SV_Ptype <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _44_;
    (* src = "libresoc.v:120612.5-120612.29" *)
    casez (\initial )
      /* src = "libresoc.v:120612.9-120612.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _44_ = 3'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _44_ = 3'h2;
        end
      default:
          _44_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_in1_sel <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _45_;
    (* src = "libresoc.v:120625.5-120625.29" *)
    casez (\initial )
      /* src = "libresoc.v:120625.9-120625.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _45_ = 4'h8;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _45_ = 4'h8;
        end
      default:
          _45_ = 4'h0;
    endcase
  end
  always @* begin
      dec62_in2_sel <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _46_;
    (* src = "libresoc.v:120638.5-120638.29" *)
    casez (\initial )
      /* src = "libresoc.v:120638.9-120638.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _46_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _46_ = 2'h1;
        end
      default:
          _46_ = 2'h0;
    endcase
  end
  always @* begin
      dec62_in3_sel <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _53_;
    (* src = "libresoc.v:120651.5-120651.29" *)
    casez (\initial )
      /* src = "libresoc.v:120651.9-120651.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" *)
    casez (opcode_switch)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _53_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _53_ = 3'h0;
        end
      default:
          _53_ = 3'h0;
    endcase
  end
  always @* begin
      dec62_out_sel <= _19_;
  end
  assign opcode_switch = opcode_in[1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:120668.1-121251.10" *)
module dec_ALU(bigendian, sv_a_nz, ALU__insn_type, ALU__fn_unit, ALU__imm_data__data, ALU__imm_data__ok, ALU__rc__rc, ALU__rc__ok, ALU__oe__oe, ALU__oe__ok, ALU__invert_in, ALU__zero_a, ALU__invert_out, ALU__write_cr0, ALU__input_carry, ALU__output_carry, ALU__is_32bit, ALU__is_signed, ALU__data_len, ALU__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:121214.3-121228.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:121201.3-121213.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:121186.3-121200.6" *)
  reg _02_;
  (* src = "libresoc.v:120669.7-120669.20" *)
  reg _03_;
  (* src = "libresoc.v:121214.3-121228.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:121201.3-121213.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:121186.3-121200.6" *)
  reg _06_;
  (* src = "libresoc.v:121102.18-121102.113" *)
  wire _07_;
  (* src = "libresoc.v:121104.18-121104.110" *)
  wire _08_;
  (* src = "libresoc.v:121117.18-121117.114" *)
  wire _09_;
  (* src = "libresoc.v:121118.18-121118.116" *)
  wire _10_;
  (* src = "libresoc.v:121120.18-121120.114" *)
  wire _11_;
  (* src = "libresoc.v:121122.18-121122.110" *)
  wire _12_;
  (* src = "libresoc.v:121123.17-121123.112" *)
  wire _13_;
  (* src = "libresoc.v:121124.17-121124.114" *)
  wire _14_;
  (* src = "libresoc.v:121105.18-121105.126" *)
  wire _15_;
  (* src = "libresoc.v:121106.18-121106.126" *)
  wire _16_;
  (* src = "libresoc.v:121108.18-121108.110" *)
  wire _17_;
  (* src = "libresoc.v:121109.18-121109.110" *)
  wire _18_;
  (* src = "libresoc.v:121111.18-121111.112" *)
  wire _19_;
  (* src = "libresoc.v:121112.17-121112.130" *)
  wire _20_;
  (* src = "libresoc.v:121114.18-121114.110" *)
  wire _21_;
  (* src = "libresoc.v:121116.18-121116.131" *)
  wire _22_;
  (* src = "libresoc.v:121119.18-121119.131" *)
  wire _23_;
  (* src = "libresoc.v:121125.17-121125.130" *)
  wire _24_;
  (* src = "libresoc.v:121103.18-121103.110" *)
  wire _25_;
  (* src = "libresoc.v:121121.18-121121.110" *)
  wire _26_;
  (* src = "libresoc.v:121107.18-121107.110" *)
  wire _27_;
  (* src = "libresoc.v:121110.18-121110.110" *)
  wire _28_;
  (* src = "libresoc.v:121113.18-121113.110" *)
  wire _29_;
  (* src = "libresoc.v:121115.18-121115.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] ALU__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] ALU__fn_unit;
  reg [13:0] ALU__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] ALU__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] ALU__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] ALU__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] ALU__insn_type;
  reg [6:0] ALU__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__write_cr0;
  reg ALU__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output ALU__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_ALU_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_ALU_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_ALU_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_ALU_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_ALU_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_ALU_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_ALU_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_ALU_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_ALU_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_ALU_UI;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_ALU_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_ALU_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_ALU_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_ALU_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_ALU_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_ALU_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_ALU_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_ALU_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_ALU_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_ALU_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_ALU_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_ALU_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_ALU_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_ALU_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  wire dec_ai_immz_out;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  wire [2:0] dec_ai_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  wire dec_ai_sv_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:120669.7-120669.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  input sv_a_nz;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_ALU_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_ALU_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121126.7-121154.4" *)
  dec dec (
    .ALU_BD(dec_ALU_BD),
    .ALU_DS(dec_ALU_DS),
    .ALU_LI(dec_ALU_LI),
    .ALU_OE(dec_ALU_OE),
    .ALU_RA(dec_ALU_RA),
    .ALU_Rc(dec_ALU_Rc),
    .ALU_SH32(dec_ALU_SH32),
    .ALU_SI(dec_ALU_SI),
    .ALU_SPR(dec_ALU_SPR),
    .ALU_UI(dec_ALU_UI),
    .ALU_cr_out(dec_ALU_cr_out),
    .ALU_cry_in(dec_ALU_cry_in),
    .ALU_cry_out(dec_ALU_cry_out),
    .ALU_function_unit(dec_ALU_function_unit),
    .ALU_in1_sel(dec_ALU_in1_sel),
    .ALU_in2_sel(dec_ALU_in2_sel),
    .ALU_internal_op(dec_ALU_internal_op),
    .ALU_inv_a(dec_ALU_inv_a),
    .ALU_inv_out(dec_ALU_inv_out),
    .ALU_is_32b(dec_ALU_is_32b),
    .ALU_ldst_len(dec_ALU_ldst_len),
    .ALU_rc_sel(dec_ALU_rc_sel),
    .ALU_sgn(dec_ALU_sgn),
    .ALU_sh(dec_ALU_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121155.10-121160.4" *)
  dec_ai dec_ai (
    .ALU_RA(dec_ALU_RA),
    .immz_out(dec_ai_immz_out),
    .sel_in(dec_ai_sel_in),
    .sv_nz(dec_ai_sv_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121161.10-121172.4" *)
  dec_bi dec_bi (
    .ALU_BD(dec_ALU_BD),
    .ALU_DS(dec_ALU_DS),
    .ALU_LI(dec_ALU_LI),
    .ALU_SH32(dec_ALU_SH32),
    .ALU_SI(dec_ALU_SI),
    .ALU_UI(dec_ALU_UI),
    .ALU_sh(dec_ALU_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121173.10-121179.4" *)
  dec_oe dec_oe (
    .ALU_OE(dec_ALU_OE),
    .ALU_internal_op(dec_ALU_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121180.10-121185.4" *)
  dec_rc dec_rc (
    .ALU_Rc(dec_ALU_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:121187.5-121187.29" *)
    casez (\initial )
      /* src = "libresoc.v:121187.9-121187.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *)
    casez (dec_ALU_cr_out)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1, 3'h5:
        begin
          _06_ = dec_rc_rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2, 3'h3:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      ALU__write_cr0 <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:121202.5-121202.29" *)
    casez (\initial )
      /* src = "libresoc.v:121202.9-121202.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_ALU_internal_op;
    endcase
  end
  always @* begin
      ALU__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:121215.5-121215.29" *)
    casez (\initial )
      /* src = "libresoc.v:121215.9-121215.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_ALU_function_unit;
        end
    endcase
  end
  always @* begin
      ALU__fn_unit <= _00_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign ALU__is_signed = dec_ALU_sgn;
  assign ALU__is_32bit = dec_ALU_is_32b;
  assign ALU__output_carry = dec_ALU_cry_out;
  assign ALU__input_carry = dec_ALU_cry_in;
  assign ALU__invert_out = dec_ALU_inv_out;
  assign ALU__invert_in = dec_ALU_inv_a;
  assign ALU__data_len = dec_ALU_ldst_len;
  assign { ALU__oe__ok, ALU__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { ALU__rc__ok, ALU__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { ALU__imm_data__ok, ALU__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_ALU_in2_sel;
  assign ALU__zero_a = dec_ai_immz_out;
  assign dec_ai_sel_in = dec_ALU_in1_sel;
  assign dec_ai_sv_nz = sv_a_nz;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_ALU_SPR[4:0], dec_ALU_SPR[9:5] };
  assign dec_oe_sel_in = dec_ALU_rc_sel;
  assign dec_rc_sel_in = dec_ALU_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign ALU__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:121255.1-121735.10" *)
module dec_BRANCH(raw_opcode_in, bigendian, BRANCH__cia, BRANCH__insn_type, BRANCH__fn_unit, BRANCH__insn, BRANCH__imm_data__data, BRANCH__imm_data__ok, BRANCH__lk, BRANCH__is_32bit, core_pc);
  reg \initial  = 0;
  (* src = "libresoc.v:121685.3-121699.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:121710.3-121722.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:121700.3-121709.6" *)
  reg _02_;
  (* src = "libresoc.v:121256.7-121256.20" *)
  reg _03_;
  (* src = "libresoc.v:121685.3-121699.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:121710.3-121722.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:121700.3-121709.6" *)
  reg _06_;
  (* src = "libresoc.v:121617.18-121617.113" *)
  wire _07_;
  (* src = "libresoc.v:121619.18-121619.110" *)
  wire _08_;
  (* src = "libresoc.v:121632.18-121632.114" *)
  wire _09_;
  (* src = "libresoc.v:121633.18-121633.116" *)
  wire _10_;
  (* src = "libresoc.v:121635.18-121635.114" *)
  wire _11_;
  (* src = "libresoc.v:121637.18-121637.110" *)
  wire _12_;
  (* src = "libresoc.v:121638.17-121638.112" *)
  wire _13_;
  (* src = "libresoc.v:121639.17-121639.114" *)
  wire _14_;
  (* src = "libresoc.v:121620.18-121620.129" *)
  wire _15_;
  (* src = "libresoc.v:121621.18-121621.129" *)
  wire _16_;
  (* src = "libresoc.v:121623.18-121623.110" *)
  wire _17_;
  (* src = "libresoc.v:121624.18-121624.110" *)
  wire _18_;
  (* src = "libresoc.v:121626.18-121626.112" *)
  wire _19_;
  (* src = "libresoc.v:121627.17-121627.133" *)
  wire _20_;
  (* src = "libresoc.v:121629.18-121629.110" *)
  wire _21_;
  (* src = "libresoc.v:121631.18-121631.134" *)
  wire _22_;
  (* src = "libresoc.v:121634.18-121634.134" *)
  wire _23_;
  (* src = "libresoc.v:121640.17-121640.133" *)
  wire _24_;
  (* src = "libresoc.v:121618.18-121618.110" *)
  wire _25_;
  (* src = "libresoc.v:121636.18-121636.110" *)
  wire _26_;
  (* src = "libresoc.v:121622.18-121622.110" *)
  wire _27_;
  (* src = "libresoc.v:121625.18-121625.110" *)
  wire _28_;
  (* src = "libresoc.v:121628.18-121628.110" *)
  wire _29_;
  (* src = "libresoc.v:121630.18-121630.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] BRANCH__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] BRANCH__fn_unit;
  reg [13:0] BRANCH__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] BRANCH__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output BRANCH__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] BRANCH__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] BRANCH__insn_type;
  reg [6:0] BRANCH__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output BRANCH__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output BRANCH__lk;
  reg BRANCH__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  input [63:0] core_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_BRANCH_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_BRANCH_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_BRANCH_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_BRANCH_LK;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_BRANCH_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_BRANCH_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_BRANCH_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_BRANCH_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_BRANCH_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_BRANCH_UI;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_BRANCH_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_BRANCH_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_BRANCH_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_BRANCH_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_BRANCH_is_32b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_BRANCH_lk;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_BRANCH_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_BRANCH_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:121256.7-121256.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_BRANCH_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_BRANCH_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121641.13-121663.4" *)
  \dec$141  dec (
    .BRANCH_BD(dec_BRANCH_BD),
    .BRANCH_DS(dec_BRANCH_DS),
    .BRANCH_LI(dec_BRANCH_LI),
    .BRANCH_LK(dec_BRANCH_LK),
    .BRANCH_OE(dec_BRANCH_OE),
    .BRANCH_Rc(dec_BRANCH_Rc),
    .BRANCH_SH32(dec_BRANCH_SH32),
    .BRANCH_SI(dec_BRANCH_SI),
    .BRANCH_SPR(dec_BRANCH_SPR),
    .BRANCH_UI(dec_BRANCH_UI),
    .BRANCH_cr_out(dec_BRANCH_cr_out),
    .BRANCH_function_unit(dec_BRANCH_function_unit),
    .BRANCH_in2_sel(dec_BRANCH_in2_sel),
    .BRANCH_internal_op(dec_BRANCH_internal_op),
    .BRANCH_is_32b(dec_BRANCH_is_32b),
    .BRANCH_lk(dec_BRANCH_lk),
    .BRANCH_rc_sel(dec_BRANCH_rc_sel),
    .BRANCH_sh(dec_BRANCH_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121664.16-121675.4" *)
  \dec_bi$144  dec_bi (
    .BRANCH_BD(dec_BRANCH_BD),
    .BRANCH_DS(dec_BRANCH_DS),
    .BRANCH_LI(dec_BRANCH_LI),
    .BRANCH_SH32(dec_BRANCH_SH32),
    .BRANCH_SI(dec_BRANCH_SI),
    .BRANCH_UI(dec_BRANCH_UI),
    .BRANCH_sh(dec_BRANCH_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121676.16-121680.4" *)
  \dec_oe$143  dec_oe (
    .BRANCH_OE(dec_BRANCH_OE),
    .BRANCH_internal_op(dec_BRANCH_internal_op),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:121681.16-121684.4" *)
  \dec_rc$142  dec_rc (
    .BRANCH_Rc(dec_BRANCH_Rc),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:121686.5-121686.29" *)
    casez (\initial )
      /* src = "libresoc.v:121686.9-121686.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_BRANCH_function_unit;
        end
    endcase
  end
  always @* begin
      BRANCH__fn_unit <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:121701.5-121701.29" *)
    casez (\initial )
      /* src = "libresoc.v:121701.9-121701.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:898" *)
    casez (dec_BRANCH_lk)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _06_ = dec_BRANCH_LK;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      BRANCH__lk <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:121711.5-121711.29" *)
    casez (\initial )
      /* src = "libresoc.v:121711.9-121711.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_BRANCH_internal_op;
    endcase
  end
  always @* begin
      BRANCH__insn_type <= _01_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign BRANCH__is_32bit = dec_BRANCH_is_32b;
  assign { BRANCH__imm_data__ok, BRANCH__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_BRANCH_in2_sel;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_BRANCH_SPR[4:0], dec_BRANCH_SPR[9:5] };
  assign BRANCH__cia = core_pc;
  assign dec_oe_sel_in = dec_BRANCH_rc_sel;
  assign dec_rc_sel_in = dec_BRANCH_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign BRANCH__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:121739.1-122111.10" *)
module dec_CR(bigendian, CR__insn_type, CR__fn_unit, CR__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:122088.3-122102.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:122075.3-122087.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:121740.7-121740.20" *)
  reg _02_;
  (* src = "libresoc.v:122088.3-122102.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:122075.3-122087.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:122030.18-122030.113" *)
  wire _05_;
  (* src = "libresoc.v:122032.18-122032.110" *)
  wire _06_;
  (* src = "libresoc.v:122045.18-122045.114" *)
  wire _07_;
  (* src = "libresoc.v:122046.18-122046.116" *)
  wire _08_;
  (* src = "libresoc.v:122048.18-122048.114" *)
  wire _09_;
  (* src = "libresoc.v:122050.18-122050.110" *)
  wire _10_;
  (* src = "libresoc.v:122051.17-122051.112" *)
  wire _11_;
  (* src = "libresoc.v:122052.17-122052.114" *)
  wire _12_;
  (* src = "libresoc.v:122033.18-122033.125" *)
  wire _13_;
  (* src = "libresoc.v:122034.18-122034.125" *)
  wire _14_;
  (* src = "libresoc.v:122036.18-122036.110" *)
  wire _15_;
  (* src = "libresoc.v:122037.18-122037.110" *)
  wire _16_;
  (* src = "libresoc.v:122039.18-122039.112" *)
  wire _17_;
  (* src = "libresoc.v:122040.17-122040.129" *)
  wire _18_;
  (* src = "libresoc.v:122042.18-122042.110" *)
  wire _19_;
  (* src = "libresoc.v:122044.18-122044.130" *)
  wire _20_;
  (* src = "libresoc.v:122047.18-122047.130" *)
  wire _21_;
  (* src = "libresoc.v:122053.17-122053.129" *)
  wire _22_;
  (* src = "libresoc.v:122031.18-122031.110" *)
  wire _23_;
  (* src = "libresoc.v:122049.18-122049.110" *)
  wire _24_;
  (* src = "libresoc.v:122035.18-122035.110" *)
  wire _25_;
  (* src = "libresoc.v:122038.18-122038.110" *)
  wire _26_;
  (* src = "libresoc.v:122041.18-122041.110" *)
  wire _27_;
  (* src = "libresoc.v:122043.18-122043.110" *)
  wire _28_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] CR__fn_unit;
  reg [13:0] CR__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] CR__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] CR__insn_type;
  reg [6:0] CR__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_CR_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_CR_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_CR_SPR;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_CR_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_CR_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_CR_internal_op;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_CR_rc_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:121740.7-121740.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  assign _05_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _06_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _08_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _10_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _12_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _13_ = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _14_ = dec_CR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _15_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _16_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _18_ = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _20_ = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _22_ = dec_CR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _23_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _24_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _25_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _26_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _27_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _28_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122054.13-122065.4" *)
  \dec$138  dec (
    .CR_OE(dec_CR_OE),
    .CR_Rc(dec_CR_Rc),
    .CR_SPR(dec_CR_SPR),
    .CR_cr_out(dec_CR_cr_out),
    .CR_function_unit(dec_CR_function_unit),
    .CR_internal_op(dec_CR_internal_op),
    .CR_rc_sel(dec_CR_rc_sel),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122066.16-122070.4" *)
  \dec_oe$140  dec_oe (
    .CR_OE(dec_CR_OE),
    .CR_internal_op(dec_CR_internal_op),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122071.16-122074.4" *)
  \dec_rc$139  dec_rc (
    .CR_Rc(dec_CR_Rc),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _04_;
    (* src = "libresoc.v:122076.5-122076.29" *)
    casez (\initial )
      /* src = "libresoc.v:122076.9-122076.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 7'h00;
        end
      default:
          _04_ = dec_CR_internal_op;
    endcase
  end
  always @* begin
      CR__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _03_;
    (* src = "libresoc.v:122089.5-122089.29" *)
    casez (\initial )
      /* src = "libresoc.v:122089.9-122089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _03_ = dec_CR_function_unit;
        end
    endcase
  end
  always @* begin
      CR__fn_unit <= _00_;
  end
  assign \$10  = _05_;
  assign \$12  = _23_;
  assign \$14  = _06_;
  assign \$16  = _13_;
  assign \$18  = _14_;
  assign \$20  = _25_;
  assign \$22  = _15_;
  assign \$24  = _16_;
  assign \$26  = _26_;
  assign \$28  = _17_;
  assign \$2  = _18_;
  assign \$30  = _27_;
  assign \$32  = _19_;
  assign \$34  = _28_;
  assign \$36  = _20_;
  assign \$38  = _07_;
  assign \$40  = _08_;
  assign \$42  = _21_;
  assign \$44  = _09_;
  assign \$46  = _24_;
  assign \$48  = _10_;
  assign \$4  = _11_;
  assign \$6  = _12_;
  assign \$8  = _22_;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_CR_SPR[4:0], dec_CR_SPR[9:5] };
  assign dec_oe_sel_in = dec_CR_rc_sel;
  assign dec_rc_sel_in = dec_CR_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign CR__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:122115.1-122698.10" *)
module dec_DIV(bigendian, sv_a_nz, DIV__insn_type, DIV__fn_unit, DIV__imm_data__data, DIV__imm_data__ok, DIV__rc__rc, DIV__rc__ok, DIV__oe__oe, DIV__oe__ok, DIV__invert_in, DIV__zero_a, DIV__input_carry, DIV__invert_out, DIV__write_cr0, DIV__output_carry, DIV__is_32bit, DIV__is_signed, DIV__data_len, DIV__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:122661.3-122675.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:122648.3-122660.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:122633.3-122647.6" *)
  reg _02_;
  (* src = "libresoc.v:122116.7-122116.20" *)
  reg _03_;
  (* src = "libresoc.v:122661.3-122675.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:122648.3-122660.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:122633.3-122647.6" *)
  reg _06_;
  (* src = "libresoc.v:122549.18-122549.113" *)
  wire _07_;
  (* src = "libresoc.v:122551.18-122551.110" *)
  wire _08_;
  (* src = "libresoc.v:122564.18-122564.114" *)
  wire _09_;
  (* src = "libresoc.v:122565.18-122565.116" *)
  wire _10_;
  (* src = "libresoc.v:122567.18-122567.114" *)
  wire _11_;
  (* src = "libresoc.v:122569.18-122569.110" *)
  wire _12_;
  (* src = "libresoc.v:122570.17-122570.112" *)
  wire _13_;
  (* src = "libresoc.v:122571.17-122571.114" *)
  wire _14_;
  (* src = "libresoc.v:122552.18-122552.126" *)
  wire _15_;
  (* src = "libresoc.v:122553.18-122553.126" *)
  wire _16_;
  (* src = "libresoc.v:122555.18-122555.110" *)
  wire _17_;
  (* src = "libresoc.v:122556.18-122556.110" *)
  wire _18_;
  (* src = "libresoc.v:122558.18-122558.112" *)
  wire _19_;
  (* src = "libresoc.v:122559.17-122559.130" *)
  wire _20_;
  (* src = "libresoc.v:122561.18-122561.110" *)
  wire _21_;
  (* src = "libresoc.v:122563.18-122563.131" *)
  wire _22_;
  (* src = "libresoc.v:122566.18-122566.131" *)
  wire _23_;
  (* src = "libresoc.v:122572.17-122572.130" *)
  wire _24_;
  (* src = "libresoc.v:122550.18-122550.110" *)
  wire _25_;
  (* src = "libresoc.v:122568.18-122568.110" *)
  wire _26_;
  (* src = "libresoc.v:122554.18-122554.110" *)
  wire _27_;
  (* src = "libresoc.v:122557.18-122557.110" *)
  wire _28_;
  (* src = "libresoc.v:122560.18-122560.110" *)
  wire _29_;
  (* src = "libresoc.v:122562.18-122562.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] DIV__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] DIV__fn_unit;
  reg [13:0] DIV__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] DIV__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] DIV__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] DIV__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] DIV__insn_type;
  reg [6:0] DIV__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__write_cr0;
  reg DIV__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output DIV__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_DIV_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_DIV_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_DIV_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_DIV_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_DIV_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_DIV_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_DIV_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_DIV_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_DIV_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_DIV_UI;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_DIV_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_DIV_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_DIV_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_DIV_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_DIV_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_DIV_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_DIV_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_DIV_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_DIV_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_DIV_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_DIV_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_DIV_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_DIV_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_DIV_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  wire dec_ai_immz_out;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  wire [2:0] dec_ai_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  wire dec_ai_sv_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:122116.7-122116.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  input sv_a_nz;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_DIV_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_DIV_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122573.13-122601.4" *)
  \dec$153  dec (
    .DIV_BD(dec_DIV_BD),
    .DIV_DS(dec_DIV_DS),
    .DIV_LI(dec_DIV_LI),
    .DIV_OE(dec_DIV_OE),
    .DIV_RA(dec_DIV_RA),
    .DIV_Rc(dec_DIV_Rc),
    .DIV_SH32(dec_DIV_SH32),
    .DIV_SI(dec_DIV_SI),
    .DIV_SPR(dec_DIV_SPR),
    .DIV_UI(dec_DIV_UI),
    .DIV_cr_out(dec_DIV_cr_out),
    .DIV_cry_in(dec_DIV_cry_in),
    .DIV_cry_out(dec_DIV_cry_out),
    .DIV_function_unit(dec_DIV_function_unit),
    .DIV_in1_sel(dec_DIV_in1_sel),
    .DIV_in2_sel(dec_DIV_in2_sel),
    .DIV_internal_op(dec_DIV_internal_op),
    .DIV_inv_a(dec_DIV_inv_a),
    .DIV_inv_out(dec_DIV_inv_out),
    .DIV_is_32b(dec_DIV_is_32b),
    .DIV_ldst_len(dec_DIV_ldst_len),
    .DIV_rc_sel(dec_DIV_rc_sel),
    .DIV_sgn(dec_DIV_sgn),
    .DIV_sh(dec_DIV_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122602.16-122607.4" *)
  \dec_ai$156  dec_ai (
    .DIV_RA(dec_DIV_RA),
    .immz_out(dec_ai_immz_out),
    .sel_in(dec_ai_sel_in),
    .sv_nz(dec_ai_sv_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122608.16-122619.4" *)
  \dec_bi$157  dec_bi (
    .DIV_BD(dec_DIV_BD),
    .DIV_DS(dec_DIV_DS),
    .DIV_LI(dec_DIV_LI),
    .DIV_SH32(dec_DIV_SH32),
    .DIV_SI(dec_DIV_SI),
    .DIV_UI(dec_DIV_UI),
    .DIV_sh(dec_DIV_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122620.16-122626.4" *)
  \dec_oe$155  dec_oe (
    .DIV_OE(dec_DIV_OE),
    .DIV_internal_op(dec_DIV_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:122627.16-122632.4" *)
  \dec_rc$154  dec_rc (
    .DIV_Rc(dec_DIV_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:122634.5-122634.29" *)
    casez (\initial )
      /* src = "libresoc.v:122634.9-122634.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *)
    casez (dec_DIV_cr_out)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1, 3'h5:
        begin
          _06_ = dec_rc_rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2, 3'h3:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      DIV__write_cr0 <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:122649.5-122649.29" *)
    casez (\initial )
      /* src = "libresoc.v:122649.9-122649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_DIV_internal_op;
    endcase
  end
  always @* begin
      DIV__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:122662.5-122662.29" *)
    casez (\initial )
      /* src = "libresoc.v:122662.9-122662.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_DIV_function_unit;
        end
    endcase
  end
  always @* begin
      DIV__fn_unit <= _00_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign DIV__is_signed = dec_DIV_sgn;
  assign DIV__is_32bit = dec_DIV_is_32b;
  assign DIV__output_carry = dec_DIV_cry_out;
  assign DIV__input_carry = dec_DIV_cry_in;
  assign DIV__invert_out = dec_DIV_inv_out;
  assign DIV__invert_in = dec_DIV_inv_a;
  assign DIV__data_len = dec_DIV_ldst_len;
  assign { DIV__oe__ok, DIV__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { DIV__rc__ok, DIV__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { DIV__imm_data__ok, DIV__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_DIV_in2_sel;
  assign DIV__zero_a = dec_ai_immz_out;
  assign dec_ai_sel_in = dec_DIV_in1_sel;
  assign dec_ai_sv_nz = sv_a_nz;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_DIV_SPR[4:0], dec_DIV_SPR[9:5] };
  assign dec_oe_sel_in = dec_DIV_rc_sel;
  assign dec_rc_sel_in = dec_DIV_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign DIV__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:122702.1-123263.10" *)
module dec_LDST(bigendian, sv_a_nz, LDST__insn_type, LDST__fn_unit, LDST__imm_data__data, LDST__imm_data__ok, LDST__zero_a, LDST__rc__rc, LDST__rc__ok, LDST__oe__oe, LDST__oe__ok, LDST__is_32bit, LDST__is_signed, LDST__data_len, LDST__byte_reverse, LDST__sign_extend, LDST__ldst_mode, LDST__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:123227.3-123241.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:123214.3-123226.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:122703.7-122703.20" *)
  reg _02_;
  (* src = "libresoc.v:123227.3-123241.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:123214.3-123226.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:123131.18-123131.113" *)
  wire _05_;
  (* src = "libresoc.v:123133.18-123133.110" *)
  wire _06_;
  (* src = "libresoc.v:123146.18-123146.114" *)
  wire _07_;
  (* src = "libresoc.v:123147.18-123147.116" *)
  wire _08_;
  (* src = "libresoc.v:123149.18-123149.114" *)
  wire _09_;
  (* src = "libresoc.v:123151.18-123151.110" *)
  wire _10_;
  (* src = "libresoc.v:123152.17-123152.112" *)
  wire _11_;
  (* src = "libresoc.v:123153.17-123153.114" *)
  wire _12_;
  (* src = "libresoc.v:123134.18-123134.127" *)
  wire _13_;
  (* src = "libresoc.v:123135.18-123135.127" *)
  wire _14_;
  (* src = "libresoc.v:123137.18-123137.110" *)
  wire _15_;
  (* src = "libresoc.v:123138.18-123138.110" *)
  wire _16_;
  (* src = "libresoc.v:123140.18-123140.112" *)
  wire _17_;
  (* src = "libresoc.v:123141.17-123141.131" *)
  wire _18_;
  (* src = "libresoc.v:123143.18-123143.110" *)
  wire _19_;
  (* src = "libresoc.v:123145.18-123145.132" *)
  wire _20_;
  (* src = "libresoc.v:123148.18-123148.132" *)
  wire _21_;
  (* src = "libresoc.v:123154.17-123154.131" *)
  wire _22_;
  (* src = "libresoc.v:123132.18-123132.110" *)
  wire _23_;
  (* src = "libresoc.v:123150.18-123150.110" *)
  wire _24_;
  (* src = "libresoc.v:123136.18-123136.110" *)
  wire _25_;
  (* src = "libresoc.v:123139.18-123139.110" *)
  wire _26_;
  (* src = "libresoc.v:123142.18-123142.110" *)
  wire _27_;
  (* src = "libresoc.v:123144.18-123144.110" *)
  wire _28_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] LDST__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] LDST__fn_unit;
  reg [13:0] LDST__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] LDST__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] LDST__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] LDST__insn_type;
  reg [6:0] LDST__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__is_signed;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] LDST__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LDST__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_LDST_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_LDST_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_LDST_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_LDST_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_LDST_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_LDST_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_LDST_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_LDST_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_LDST_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_LDST_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LDST_br;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_LDST_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_LDST_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_LDST_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_LDST_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_LDST_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LDST_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_LDST_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_LDST_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LDST_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LDST_sgn_ext;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_LDST_sh;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_LDST_upd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  wire dec_ai_immz_out;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  wire [2:0] dec_ai_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  wire dec_ai_sv_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:122703.7-122703.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  input sv_a_nz;
  assign _05_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _06_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _08_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _10_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _12_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _13_ = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _14_ = dec_LDST_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _15_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _16_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _18_ = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _20_ = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _22_ = dec_LDST_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _23_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _24_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _25_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _26_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _27_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _28_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123155.13-123182.4" *)
  \dec$166  dec (
    .LDST_BD(dec_LDST_BD),
    .LDST_DS(dec_LDST_DS),
    .LDST_LI(dec_LDST_LI),
    .LDST_OE(dec_LDST_OE),
    .LDST_RA(dec_LDST_RA),
    .LDST_Rc(dec_LDST_Rc),
    .LDST_SH32(dec_LDST_SH32),
    .LDST_SI(dec_LDST_SI),
    .LDST_SPR(dec_LDST_SPR),
    .LDST_UI(dec_LDST_UI),
    .LDST_br(dec_LDST_br),
    .LDST_cr_out(dec_LDST_cr_out),
    .LDST_function_unit(dec_LDST_function_unit),
    .LDST_in1_sel(dec_LDST_in1_sel),
    .LDST_in2_sel(dec_LDST_in2_sel),
    .LDST_internal_op(dec_LDST_internal_op),
    .LDST_is_32b(dec_LDST_is_32b),
    .LDST_ldst_len(dec_LDST_ldst_len),
    .LDST_rc_sel(dec_LDST_rc_sel),
    .LDST_sgn(dec_LDST_sgn),
    .LDST_sgn_ext(dec_LDST_sgn_ext),
    .LDST_sh(dec_LDST_sh),
    .LDST_upd(dec_LDST_upd),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123183.16-123188.4" *)
  \dec_ai$169  dec_ai (
    .LDST_RA(dec_LDST_RA),
    .immz_out(dec_ai_immz_out),
    .sel_in(dec_ai_sel_in),
    .sv_nz(dec_ai_sv_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123189.16-123200.4" *)
  \dec_bi$170  dec_bi (
    .LDST_BD(dec_LDST_BD),
    .LDST_DS(dec_LDST_DS),
    .LDST_LI(dec_LDST_LI),
    .LDST_SH32(dec_LDST_SH32),
    .LDST_SI(dec_LDST_SI),
    .LDST_UI(dec_LDST_UI),
    .LDST_sh(dec_LDST_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123201.16-123207.4" *)
  \dec_oe$168  dec_oe (
    .LDST_OE(dec_LDST_OE),
    .LDST_internal_op(dec_LDST_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123208.16-123213.4" *)
  \dec_rc$167  dec_rc (
    .LDST_Rc(dec_LDST_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _04_;
    (* src = "libresoc.v:123215.5-123215.29" *)
    casez (\initial )
      /* src = "libresoc.v:123215.9-123215.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 7'h00;
        end
      default:
          _04_ = dec_LDST_internal_op;
    endcase
  end
  always @* begin
      LDST__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _03_;
    (* src = "libresoc.v:123228.5-123228.29" *)
    casez (\initial )
      /* src = "libresoc.v:123228.9-123228.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _03_ = dec_LDST_function_unit;
        end
    endcase
  end
  always @* begin
      LDST__fn_unit <= _00_;
  end
  assign \$10  = _05_;
  assign \$12  = _23_;
  assign \$14  = _06_;
  assign \$16  = _13_;
  assign \$18  = _14_;
  assign \$20  = _25_;
  assign \$22  = _15_;
  assign \$24  = _16_;
  assign \$26  = _26_;
  assign \$28  = _17_;
  assign \$2  = _18_;
  assign \$30  = _27_;
  assign \$32  = _19_;
  assign \$34  = _28_;
  assign \$36  = _20_;
  assign \$38  = _07_;
  assign \$40  = _08_;
  assign \$42  = _21_;
  assign \$44  = _09_;
  assign \$46  = _24_;
  assign \$48  = _10_;
  assign \$4  = _11_;
  assign \$6  = _12_;
  assign \$8  = _22_;
  assign LDST__ldst_mode = dec_LDST_upd;
  assign LDST__sign_extend = dec_LDST_sgn_ext;
  assign LDST__byte_reverse = dec_LDST_br;
  assign LDST__is_signed = dec_LDST_sgn;
  assign LDST__is_32bit = dec_LDST_is_32b;
  assign LDST__data_len = dec_LDST_ldst_len;
  assign { LDST__oe__ok, LDST__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { LDST__rc__ok, LDST__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { LDST__imm_data__ok, LDST__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_LDST_in2_sel;
  assign LDST__zero_a = dec_ai_immz_out;
  assign dec_ai_sel_in = dec_LDST_in1_sel;
  assign dec_ai_sv_nz = sv_a_nz;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_LDST_SPR[4:0], dec_LDST_SPR[9:5] };
  assign dec_oe_sel_in = dec_LDST_rc_sel;
  assign dec_rc_sel_in = dec_LDST_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign LDST__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:123267.1-123850.10" *)
module dec_LOGICAL(bigendian, sv_a_nz, LOGICAL__insn_type, LOGICAL__fn_unit, LOGICAL__imm_data__data, LOGICAL__imm_data__ok, LOGICAL__rc__rc, LOGICAL__rc__ok, LOGICAL__oe__oe, LOGICAL__oe__ok, LOGICAL__invert_in, LOGICAL__zero_a, LOGICAL__input_carry, LOGICAL__invert_out, LOGICAL__write_cr0, LOGICAL__output_carry, LOGICAL__is_32bit, LOGICAL__is_signed, LOGICAL__data_len, LOGICAL__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:123813.3-123827.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:123800.3-123812.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:123785.3-123799.6" *)
  reg _02_;
  (* src = "libresoc.v:123268.7-123268.20" *)
  reg _03_;
  (* src = "libresoc.v:123813.3-123827.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:123800.3-123812.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:123785.3-123799.6" *)
  reg _06_;
  (* src = "libresoc.v:123701.18-123701.113" *)
  wire _07_;
  (* src = "libresoc.v:123703.18-123703.110" *)
  wire _08_;
  (* src = "libresoc.v:123716.18-123716.114" *)
  wire _09_;
  (* src = "libresoc.v:123717.18-123717.116" *)
  wire _10_;
  (* src = "libresoc.v:123719.18-123719.114" *)
  wire _11_;
  (* src = "libresoc.v:123721.18-123721.110" *)
  wire _12_;
  (* src = "libresoc.v:123722.17-123722.112" *)
  wire _13_;
  (* src = "libresoc.v:123723.17-123723.114" *)
  wire _14_;
  (* src = "libresoc.v:123704.18-123704.130" *)
  wire _15_;
  (* src = "libresoc.v:123705.18-123705.130" *)
  wire _16_;
  (* src = "libresoc.v:123707.18-123707.110" *)
  wire _17_;
  (* src = "libresoc.v:123708.18-123708.110" *)
  wire _18_;
  (* src = "libresoc.v:123710.18-123710.112" *)
  wire _19_;
  (* src = "libresoc.v:123711.17-123711.134" *)
  wire _20_;
  (* src = "libresoc.v:123713.18-123713.110" *)
  wire _21_;
  (* src = "libresoc.v:123715.18-123715.135" *)
  wire _22_;
  (* src = "libresoc.v:123718.18-123718.135" *)
  wire _23_;
  (* src = "libresoc.v:123724.17-123724.134" *)
  wire _24_;
  (* src = "libresoc.v:123702.18-123702.110" *)
  wire _25_;
  (* src = "libresoc.v:123720.18-123720.110" *)
  wire _26_;
  (* src = "libresoc.v:123706.18-123706.110" *)
  wire _27_;
  (* src = "libresoc.v:123709.18-123709.110" *)
  wire _28_;
  (* src = "libresoc.v:123712.18-123712.110" *)
  wire _29_;
  (* src = "libresoc.v:123714.18-123714.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] LOGICAL__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] LOGICAL__fn_unit;
  reg [13:0] LOGICAL__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] LOGICAL__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] LOGICAL__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] LOGICAL__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] LOGICAL__insn_type;
  reg [6:0] LOGICAL__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__write_cr0;
  reg LOGICAL__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output LOGICAL__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_LOGICAL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_LOGICAL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_LOGICAL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_LOGICAL_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_LOGICAL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_LOGICAL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_LOGICAL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_LOGICAL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_LOGICAL_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_LOGICAL_UI;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_LOGICAL_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_LOGICAL_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LOGICAL_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_LOGICAL_function_unit;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_LOGICAL_in1_sel;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_LOGICAL_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_LOGICAL_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LOGICAL_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LOGICAL_inv_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LOGICAL_is_32b;
  (* enum_base_type = "LdstLen" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "is1B" *)
  (* enum_value_0010 = "is2B" *)
  (* enum_value_0100 = "is4B" *)
  (* enum_value_1000 = "is8B" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_LOGICAL_ldst_len;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_LOGICAL_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_LOGICAL_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_LOGICAL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  wire dec_ai_immz_out;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  wire [2:0] dec_ai_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  wire dec_ai_sv_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:123268.7-123268.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  input sv_a_nz;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_LOGICAL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_LOGICAL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123725.13-123753.4" *)
  \dec$145  dec (
    .LOGICAL_BD(dec_LOGICAL_BD),
    .LOGICAL_DS(dec_LOGICAL_DS),
    .LOGICAL_LI(dec_LOGICAL_LI),
    .LOGICAL_OE(dec_LOGICAL_OE),
    .LOGICAL_RA(dec_LOGICAL_RA),
    .LOGICAL_Rc(dec_LOGICAL_Rc),
    .LOGICAL_SH32(dec_LOGICAL_SH32),
    .LOGICAL_SI(dec_LOGICAL_SI),
    .LOGICAL_SPR(dec_LOGICAL_SPR),
    .LOGICAL_UI(dec_LOGICAL_UI),
    .LOGICAL_cr_out(dec_LOGICAL_cr_out),
    .LOGICAL_cry_in(dec_LOGICAL_cry_in),
    .LOGICAL_cry_out(dec_LOGICAL_cry_out),
    .LOGICAL_function_unit(dec_LOGICAL_function_unit),
    .LOGICAL_in1_sel(dec_LOGICAL_in1_sel),
    .LOGICAL_in2_sel(dec_LOGICAL_in2_sel),
    .LOGICAL_internal_op(dec_LOGICAL_internal_op),
    .LOGICAL_inv_a(dec_LOGICAL_inv_a),
    .LOGICAL_inv_out(dec_LOGICAL_inv_out),
    .LOGICAL_is_32b(dec_LOGICAL_is_32b),
    .LOGICAL_ldst_len(dec_LOGICAL_ldst_len),
    .LOGICAL_rc_sel(dec_LOGICAL_rc_sel),
    .LOGICAL_sgn(dec_LOGICAL_sgn),
    .LOGICAL_sh(dec_LOGICAL_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123754.16-123759.4" *)
  \dec_ai$148  dec_ai (
    .LOGICAL_RA(dec_LOGICAL_RA),
    .immz_out(dec_ai_immz_out),
    .sel_in(dec_ai_sel_in),
    .sv_nz(dec_ai_sv_nz)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123760.16-123771.4" *)
  \dec_bi$149  dec_bi (
    .LOGICAL_BD(dec_LOGICAL_BD),
    .LOGICAL_DS(dec_LOGICAL_DS),
    .LOGICAL_LI(dec_LOGICAL_LI),
    .LOGICAL_SH32(dec_LOGICAL_SH32),
    .LOGICAL_SI(dec_LOGICAL_SI),
    .LOGICAL_UI(dec_LOGICAL_UI),
    .LOGICAL_sh(dec_LOGICAL_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123772.16-123778.4" *)
  \dec_oe$147  dec_oe (
    .LOGICAL_OE(dec_LOGICAL_OE),
    .LOGICAL_internal_op(dec_LOGICAL_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:123779.16-123784.4" *)
  \dec_rc$146  dec_rc (
    .LOGICAL_Rc(dec_LOGICAL_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:123786.5-123786.29" *)
    casez (\initial )
      /* src = "libresoc.v:123786.9-123786.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *)
    casez (dec_LOGICAL_cr_out)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1, 3'h5:
        begin
          _06_ = dec_rc_rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2, 3'h3:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      LOGICAL__write_cr0 <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:123801.5-123801.29" *)
    casez (\initial )
      /* src = "libresoc.v:123801.9-123801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_LOGICAL_internal_op;
    endcase
  end
  always @* begin
      LOGICAL__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:123814.5-123814.29" *)
    casez (\initial )
      /* src = "libresoc.v:123814.9-123814.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_LOGICAL_function_unit;
        end
    endcase
  end
  always @* begin
      LOGICAL__fn_unit <= _00_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign LOGICAL__is_signed = dec_LOGICAL_sgn;
  assign LOGICAL__is_32bit = dec_LOGICAL_is_32b;
  assign LOGICAL__output_carry = dec_LOGICAL_cry_out;
  assign LOGICAL__input_carry = dec_LOGICAL_cry_in;
  assign LOGICAL__invert_out = dec_LOGICAL_inv_out;
  assign LOGICAL__invert_in = dec_LOGICAL_inv_a;
  assign LOGICAL__data_len = dec_LOGICAL_ldst_len;
  assign { LOGICAL__oe__ok, LOGICAL__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { LOGICAL__rc__ok, LOGICAL__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { LOGICAL__imm_data__ok, LOGICAL__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_LOGICAL_in2_sel;
  assign LOGICAL__zero_a = dec_ai_immz_out;
  assign dec_ai_sel_in = dec_LOGICAL_in1_sel;
  assign dec_ai_sv_nz = sv_a_nz;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_LOGICAL_SPR[4:0], dec_LOGICAL_SPR[9:5] };
  assign dec_oe_sel_in = dec_LOGICAL_rc_sel;
  assign dec_rc_sel_in = dec_LOGICAL_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign LOGICAL__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:123854.1-124356.10" *)
module dec_MUL(bigendian, MUL__insn_type, MUL__fn_unit, MUL__imm_data__data, MUL__imm_data__ok, MUL__rc__rc, MUL__rc__ok, MUL__oe__oe, MUL__oe__ok, MUL__write_cr0, MUL__is_32bit, MUL__is_signed, MUL__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:124327.3-124341.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:124314.3-124326.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:124299.3-124313.6" *)
  reg _02_;
  (* src = "libresoc.v:123855.7-123855.20" *)
  reg _03_;
  (* src = "libresoc.v:124327.3-124341.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:124314.3-124326.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:124299.3-124313.6" *)
  reg _06_;
  (* src = "libresoc.v:124228.18-124228.113" *)
  wire _07_;
  (* src = "libresoc.v:124230.18-124230.110" *)
  wire _08_;
  (* src = "libresoc.v:124243.18-124243.114" *)
  wire _09_;
  (* src = "libresoc.v:124244.18-124244.116" *)
  wire _10_;
  (* src = "libresoc.v:124246.18-124246.114" *)
  wire _11_;
  (* src = "libresoc.v:124248.18-124248.110" *)
  wire _12_;
  (* src = "libresoc.v:124249.17-124249.112" *)
  wire _13_;
  (* src = "libresoc.v:124250.17-124250.114" *)
  wire _14_;
  (* src = "libresoc.v:124231.18-124231.126" *)
  wire _15_;
  (* src = "libresoc.v:124232.18-124232.126" *)
  wire _16_;
  (* src = "libresoc.v:124234.18-124234.110" *)
  wire _17_;
  (* src = "libresoc.v:124235.18-124235.110" *)
  wire _18_;
  (* src = "libresoc.v:124237.18-124237.112" *)
  wire _19_;
  (* src = "libresoc.v:124238.17-124238.130" *)
  wire _20_;
  (* src = "libresoc.v:124240.18-124240.110" *)
  wire _21_;
  (* src = "libresoc.v:124242.18-124242.131" *)
  wire _22_;
  (* src = "libresoc.v:124245.18-124245.131" *)
  wire _23_;
  (* src = "libresoc.v:124251.17-124251.130" *)
  wire _24_;
  (* src = "libresoc.v:124229.18-124229.110" *)
  wire _25_;
  (* src = "libresoc.v:124247.18-124247.110" *)
  wire _26_;
  (* src = "libresoc.v:124233.18-124233.110" *)
  wire _27_;
  (* src = "libresoc.v:124236.18-124236.110" *)
  wire _28_;
  (* src = "libresoc.v:124239.18-124239.110" *)
  wire _29_;
  (* src = "libresoc.v:124241.18-124241.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] MUL__fn_unit;
  reg [13:0] MUL__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] MUL__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] MUL__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] MUL__insn_type;
  reg [6:0] MUL__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output MUL__write_cr0;
  reg MUL__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_MUL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_MUL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_MUL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_MUL_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_MUL_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_MUL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_MUL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_MUL_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_MUL_UI;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_MUL_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_MUL_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_MUL_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_MUL_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_MUL_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_MUL_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_MUL_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_MUL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:123855.7-123855.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_MUL_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_MUL_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124252.13-124273.4" *)
  \dec$158  dec (
    .MUL_BD(dec_MUL_BD),
    .MUL_DS(dec_MUL_DS),
    .MUL_LI(dec_MUL_LI),
    .MUL_OE(dec_MUL_OE),
    .MUL_Rc(dec_MUL_Rc),
    .MUL_SH32(dec_MUL_SH32),
    .MUL_SI(dec_MUL_SI),
    .MUL_SPR(dec_MUL_SPR),
    .MUL_UI(dec_MUL_UI),
    .MUL_cr_out(dec_MUL_cr_out),
    .MUL_function_unit(dec_MUL_function_unit),
    .MUL_in2_sel(dec_MUL_in2_sel),
    .MUL_internal_op(dec_MUL_internal_op),
    .MUL_is_32b(dec_MUL_is_32b),
    .MUL_rc_sel(dec_MUL_rc_sel),
    .MUL_sgn(dec_MUL_sgn),
    .MUL_sh(dec_MUL_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124274.16-124285.4" *)
  \dec_bi$161  dec_bi (
    .MUL_BD(dec_MUL_BD),
    .MUL_DS(dec_MUL_DS),
    .MUL_LI(dec_MUL_LI),
    .MUL_SH32(dec_MUL_SH32),
    .MUL_SI(dec_MUL_SI),
    .MUL_UI(dec_MUL_UI),
    .MUL_sh(dec_MUL_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124286.16-124292.4" *)
  \dec_oe$160  dec_oe (
    .MUL_OE(dec_MUL_OE),
    .MUL_internal_op(dec_MUL_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124293.16-124298.4" *)
  \dec_rc$159  dec_rc (
    .MUL_Rc(dec_MUL_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:124300.5-124300.29" *)
    casez (\initial )
      /* src = "libresoc.v:124300.9-124300.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *)
    casez (dec_MUL_cr_out)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1, 3'h5:
        begin
          _06_ = dec_rc_rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2, 3'h3:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      MUL__write_cr0 <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:124315.5-124315.29" *)
    casez (\initial )
      /* src = "libresoc.v:124315.9-124315.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_MUL_internal_op;
    endcase
  end
  always @* begin
      MUL__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:124328.5-124328.29" *)
    casez (\initial )
      /* src = "libresoc.v:124328.9-124328.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_MUL_function_unit;
        end
    endcase
  end
  always @* begin
      MUL__fn_unit <= _00_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign MUL__is_signed = dec_MUL_sgn;
  assign MUL__is_32bit = dec_MUL_is_32b;
  assign { MUL__oe__ok, MUL__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { MUL__rc__ok, MUL__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { MUL__imm_data__ok, MUL__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_MUL_in2_sel;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_MUL_SPR[4:0], dec_MUL_SPR[9:5] };
  assign dec_oe_sel_in = dec_MUL_rc_sel;
  assign dec_rc_sel_in = dec_MUL_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign MUL__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:124360.1-124906.10" *)
module dec_SHIFT_ROT(bigendian, SHIFT_ROT__insn_type, SHIFT_ROT__fn_unit, SHIFT_ROT__imm_data__data, SHIFT_ROT__imm_data__ok, SHIFT_ROT__rc__rc, SHIFT_ROT__rc__ok, SHIFT_ROT__oe__oe, SHIFT_ROT__oe__ok, SHIFT_ROT__write_cr0, SHIFT_ROT__invert_in, SHIFT_ROT__input_carry, SHIFT_ROT__output_carry, SHIFT_ROT__input_cr, SHIFT_ROT__output_cr, SHIFT_ROT__is_32bit, SHIFT_ROT__is_signed, SHIFT_ROT__insn, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:124872.3-124886.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:124859.3-124871.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:124844.3-124858.6" *)
  reg _02_;
  (* src = "libresoc.v:124361.7-124361.20" *)
  reg _03_;
  (* src = "libresoc.v:124872.3-124886.6" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:124859.3-124871.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:124844.3-124858.6" *)
  reg _06_;
  (* src = "libresoc.v:124769.18-124769.113" *)
  wire _07_;
  (* src = "libresoc.v:124771.18-124771.110" *)
  wire _08_;
  (* src = "libresoc.v:124784.18-124784.114" *)
  wire _09_;
  (* src = "libresoc.v:124785.18-124785.116" *)
  wire _10_;
  (* src = "libresoc.v:124787.18-124787.114" *)
  wire _11_;
  (* src = "libresoc.v:124789.18-124789.110" *)
  wire _12_;
  (* src = "libresoc.v:124790.17-124790.112" *)
  wire _13_;
  (* src = "libresoc.v:124791.17-124791.114" *)
  wire _14_;
  (* src = "libresoc.v:124772.18-124772.132" *)
  wire _15_;
  (* src = "libresoc.v:124773.18-124773.132" *)
  wire _16_;
  (* src = "libresoc.v:124775.18-124775.110" *)
  wire _17_;
  (* src = "libresoc.v:124776.18-124776.110" *)
  wire _18_;
  (* src = "libresoc.v:124778.18-124778.112" *)
  wire _19_;
  (* src = "libresoc.v:124779.17-124779.136" *)
  wire _20_;
  (* src = "libresoc.v:124781.18-124781.110" *)
  wire _21_;
  (* src = "libresoc.v:124783.18-124783.137" *)
  wire _22_;
  (* src = "libresoc.v:124786.18-124786.137" *)
  wire _23_;
  (* src = "libresoc.v:124792.17-124792.136" *)
  wire _24_;
  (* src = "libresoc.v:124770.18-124770.110" *)
  wire _25_;
  (* src = "libresoc.v:124788.18-124788.110" *)
  wire _26_;
  (* src = "libresoc.v:124774.18-124774.110" *)
  wire _27_;
  (* src = "libresoc.v:124777.18-124777.110" *)
  wire _28_;
  (* src = "libresoc.v:124780.18-124780.110" *)
  wire _29_;
  (* src = "libresoc.v:124782.18-124782.110" *)
  wire _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] SHIFT_ROT__fn_unit;
  reg [13:0] SHIFT_ROT__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] SHIFT_ROT__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] SHIFT_ROT__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] SHIFT_ROT__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] SHIFT_ROT__insn_type;
  reg [6:0] SHIFT_ROT__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SHIFT_ROT__write_cr0;
  reg SHIFT_ROT__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_SHIFT_ROT_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [13:0] dec_SHIFT_ROT_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [23:0] dec_SHIFT_ROT_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_SHIFT_ROT_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_SHIFT_ROT_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [4:0] dec_SHIFT_ROT_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_SHIFT_ROT_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_SHIFT_ROT_SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [15:0] dec_SHIFT_ROT_UI;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_SHIFT_ROT_cr_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_SHIFT_ROT_cr_out;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_SHIFT_ROT_cry_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_SHIFT_ROT_cry_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_SHIFT_ROT_function_unit;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [3:0] dec_SHIFT_ROT_in2_sel;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_SHIFT_ROT_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_SHIFT_ROT_inv_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_SHIFT_ROT_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_SHIFT_ROT_rc_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_SHIFT_ROT_sgn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [5:0] dec_SHIFT_ROT_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] dec_bi_imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_bi_imm_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  wire [3:0] dec_bi_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_oe_oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec_rc_rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:124361.7-124361.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _08_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _10_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _12_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _13_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _14_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _15_ = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _16_ = dec_SHIFT_ROT_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _18_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _20_ = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _22_ = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _23_ = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _24_ = dec_SHIFT_ROT_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _25_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _26_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _27_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _28_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _29_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _30_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124793.13-124818.4" *)
  \dec$162  dec (
    .SHIFT_ROT_BD(dec_SHIFT_ROT_BD),
    .SHIFT_ROT_DS(dec_SHIFT_ROT_DS),
    .SHIFT_ROT_LI(dec_SHIFT_ROT_LI),
    .SHIFT_ROT_OE(dec_SHIFT_ROT_OE),
    .SHIFT_ROT_Rc(dec_SHIFT_ROT_Rc),
    .SHIFT_ROT_SH32(dec_SHIFT_ROT_SH32),
    .SHIFT_ROT_SI(dec_SHIFT_ROT_SI),
    .SHIFT_ROT_SPR(dec_SHIFT_ROT_SPR),
    .SHIFT_ROT_UI(dec_SHIFT_ROT_UI),
    .SHIFT_ROT_cr_in(dec_SHIFT_ROT_cr_in),
    .SHIFT_ROT_cr_out(dec_SHIFT_ROT_cr_out),
    .SHIFT_ROT_cry_in(dec_SHIFT_ROT_cry_in),
    .SHIFT_ROT_cry_out(dec_SHIFT_ROT_cry_out),
    .SHIFT_ROT_function_unit(dec_SHIFT_ROT_function_unit),
    .SHIFT_ROT_in2_sel(dec_SHIFT_ROT_in2_sel),
    .SHIFT_ROT_internal_op(dec_SHIFT_ROT_internal_op),
    .SHIFT_ROT_inv_a(dec_SHIFT_ROT_inv_a),
    .SHIFT_ROT_is_32b(dec_SHIFT_ROT_is_32b),
    .SHIFT_ROT_rc_sel(dec_SHIFT_ROT_rc_sel),
    .SHIFT_ROT_sgn(dec_SHIFT_ROT_sgn),
    .SHIFT_ROT_sh(dec_SHIFT_ROT_sh),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124819.16-124830.4" *)
  \dec_bi$165  dec_bi (
    .SHIFT_ROT_BD(dec_SHIFT_ROT_BD),
    .SHIFT_ROT_DS(dec_SHIFT_ROT_DS),
    .SHIFT_ROT_LI(dec_SHIFT_ROT_LI),
    .SHIFT_ROT_SH32(dec_SHIFT_ROT_SH32),
    .SHIFT_ROT_SI(dec_SHIFT_ROT_SI),
    .SHIFT_ROT_UI(dec_SHIFT_ROT_UI),
    .SHIFT_ROT_sh(dec_SHIFT_ROT_sh),
    .imm_b(dec_bi_imm_b),
    .imm_b_ok(dec_bi_imm_b_ok),
    .sel_in(dec_bi_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124831.16-124837.4" *)
  \dec_oe$164  dec_oe (
    .SHIFT_ROT_OE(dec_SHIFT_ROT_OE),
    .SHIFT_ROT_internal_op(dec_SHIFT_ROT_internal_op),
    .oe(dec_oe_oe),
    .oe_ok(dec_oe_oe_ok),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:124838.16-124843.4" *)
  \dec_rc$163  dec_rc (
    .SHIFT_ROT_Rc(dec_SHIFT_ROT_Rc),
    .rc(dec_rc_rc),
    .rc_ok(dec_rc_rc_ok),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _03_ = 1'h0;
  end
  always @* begin
      \initial  <= _03_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _06_;
    (* src = "libresoc.v:124845.5-124845.29" *)
    casez (\initial )
      /* src = "libresoc.v:124845.9-124845.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:879" *)
    casez (dec_SHIFT_ROT_cr_out)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1, 3'h5:
        begin
          _06_ = dec_rc_rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2, 3'h3:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      SHIFT_ROT__write_cr0 <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _05_;
    (* src = "libresoc.v:124860.5-124860.29" *)
    casez (\initial )
      /* src = "libresoc.v:124860.9-124860.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _05_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _05_ = 7'h00;
        end
      default:
          _05_ = dec_SHIFT_ROT_internal_op;
    endcase
  end
  always @* begin
      SHIFT_ROT__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _04_;
    (* src = "libresoc.v:124873.5-124873.29" *)
    casez (\initial )
      /* src = "libresoc.v:124873.9-124873.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dec_SHIFT_ROT_function_unit;
        end
    endcase
  end
  always @* begin
      SHIFT_ROT__fn_unit <= _00_;
  end
  assign \$10  = _07_;
  assign \$12  = _25_;
  assign \$14  = _08_;
  assign \$16  = _15_;
  assign \$18  = _16_;
  assign \$20  = _27_;
  assign \$22  = _17_;
  assign \$24  = _18_;
  assign \$26  = _28_;
  assign \$28  = _19_;
  assign \$2  = _20_;
  assign \$30  = _29_;
  assign \$32  = _21_;
  assign \$34  = _30_;
  assign \$36  = _22_;
  assign \$38  = _09_;
  assign \$40  = _10_;
  assign \$42  = _23_;
  assign \$44  = _11_;
  assign \$46  = _26_;
  assign \$48  = _12_;
  assign \$4  = _13_;
  assign \$6  = _14_;
  assign \$8  = _24_;
  assign SHIFT_ROT__is_signed = dec_SHIFT_ROT_sgn;
  assign SHIFT_ROT__is_32bit = dec_SHIFT_ROT_is_32b;
  assign SHIFT_ROT__output_carry = dec_SHIFT_ROT_cry_out;
  assign SHIFT_ROT__input_carry = dec_SHIFT_ROT_cry_in;
  assign SHIFT_ROT__invert_in = dec_SHIFT_ROT_inv_a;
  assign SHIFT_ROT__output_cr = dec_SHIFT_ROT_cr_out[0];
  assign SHIFT_ROT__input_cr = dec_SHIFT_ROT_cr_in[0];
  assign { SHIFT_ROT__oe__ok, SHIFT_ROT__oe__oe } = { dec_oe_oe_ok, dec_oe_oe };
  assign { SHIFT_ROT__rc__ok, SHIFT_ROT__rc__rc } = { dec_rc_rc_ok, dec_rc_rc };
  assign { SHIFT_ROT__imm_data__ok, SHIFT_ROT__imm_data__data } = { dec_bi_imm_b_ok, dec_bi_imm_b };
  assign dec_bi_sel_in = dec_SHIFT_ROT_in2_sel;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_SHIFT_ROT_SPR[4:0], dec_SHIFT_ROT_SPR[9:5] };
  assign dec_oe_sel_in = dec_SHIFT_ROT_rc_sel;
  assign dec_rc_sel_in = dec_SHIFT_ROT_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign SHIFT_ROT__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:124910.1-125288.10" *)
module dec_SPR(bigendian, SPR__insn_type, SPR__fn_unit, SPR__insn, SPR__is_32bit, raw_opcode_in);
  reg \initial  = 0;
  (* src = "libresoc.v:125264.3-125278.6" *)
  reg [13:0] _00_;
  (* src = "libresoc.v:125251.3-125263.6" *)
  reg [6:0] _01_;
  (* src = "libresoc.v:124911.7-124911.20" *)
  reg _02_;
  (* src = "libresoc.v:125264.3-125278.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:125251.3-125263.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:125205.18-125205.113" *)
  wire _05_;
  (* src = "libresoc.v:125207.18-125207.110" *)
  wire _06_;
  (* src = "libresoc.v:125220.18-125220.114" *)
  wire _07_;
  (* src = "libresoc.v:125221.18-125221.116" *)
  wire _08_;
  (* src = "libresoc.v:125223.18-125223.114" *)
  wire _09_;
  (* src = "libresoc.v:125225.18-125225.110" *)
  wire _10_;
  (* src = "libresoc.v:125226.17-125226.112" *)
  wire _11_;
  (* src = "libresoc.v:125227.17-125227.114" *)
  wire _12_;
  (* src = "libresoc.v:125208.18-125208.126" *)
  wire _13_;
  (* src = "libresoc.v:125209.18-125209.126" *)
  wire _14_;
  (* src = "libresoc.v:125211.18-125211.110" *)
  wire _15_;
  (* src = "libresoc.v:125212.18-125212.110" *)
  wire _16_;
  (* src = "libresoc.v:125214.18-125214.112" *)
  wire _17_;
  (* src = "libresoc.v:125215.17-125215.130" *)
  wire _18_;
  (* src = "libresoc.v:125217.18-125217.110" *)
  wire _19_;
  (* src = "libresoc.v:125219.18-125219.131" *)
  wire _20_;
  (* src = "libresoc.v:125222.18-125222.131" *)
  wire _21_;
  (* src = "libresoc.v:125228.17-125228.130" *)
  wire _22_;
  (* src = "libresoc.v:125206.18-125206.110" *)
  wire _23_;
  (* src = "libresoc.v:125224.18-125224.110" *)
  wire _24_;
  (* src = "libresoc.v:125210.18-125210.110" *)
  wire _25_;
  (* src = "libresoc.v:125213.18-125213.110" *)
  wire _26_;
  (* src = "libresoc.v:125216.18-125216.110" *)
  wire _27_;
  (* src = "libresoc.v:125218.18-125218.110" *)
  wire _28_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *)
  wire \$8 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] SPR__fn_unit;
  reg [13:0] SPR__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] SPR__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] SPR__insn_type;
  reg [6:0] SPR__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output SPR__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  input bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_SPR_OE;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire dec_SPR_Rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [9:0] dec_SPR_SPR;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [2:0] dec_SPR_cr_out;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [13:0] dec_SPR_function_unit;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [6:0] dec_SPR_internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:198" *)
  wire dec_SPR_is_32b;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  wire [1:0] dec_SPR_rc_sel;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  wire [1:0] dec_oe_sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" *)
  wire [31:0] dec_opcode_in;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  wire [1:0] dec_rc_sel_in;
  (* src = "libresoc.v:124911.7-124911.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463" *)
  wire [31:0] insn_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500" *)
  wire [31:0] \insn_in$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:842" *)
  wire is_mmu_spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:841" *)
  wire is_spr_mv;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  input [31:0] raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:836" *)
  wire [9:0] spr;
  assign _05_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$8 ;
  assign _06_ = \$10  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$12 ;
  assign _07_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$36 ;
  assign _08_ = \$38  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _09_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$42 ;
  assign _10_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) \$46 ;
  assign _11_ = is_spr_mv & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) \$2 ;
  assign _12_ = \$4  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) is_mmu_spr;
  assign _13_ = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:843" *) 7'h31;
  assign _14_ = dec_SPR_internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) 7'h2e;
  assign _15_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h12;
  assign _16_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 5'h13;
  assign _17_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) 10'h2d0;
  assign _18_ = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _19_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) 6'h30;
  assign _20_ = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *) 14'h0400;
  assign _21_ = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _22_ = dec_SPR_function_unit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) 14'h0800;
  assign _23_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _24_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:854" *) is_mmu_spr;
  assign _25_ = \$16  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:844" *) \$18 ;
  assign _26_ = \$22  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$24 ;
  assign _27_ = \$26  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:847" *) \$28 ;
  assign _28_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:848" *) \$32 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:125229.13-125241.4" *)
  \dec$150  dec (
    .SPR_OE(dec_SPR_OE),
    .SPR_Rc(dec_SPR_Rc),
    .SPR_SPR(dec_SPR_SPR),
    .SPR_cr_out(dec_SPR_cr_out),
    .SPR_function_unit(dec_SPR_function_unit),
    .SPR_internal_op(dec_SPR_internal_op),
    .SPR_is_32b(dec_SPR_is_32b),
    .SPR_rc_sel(dec_SPR_rc_sel),
    .bigendian(bigendian),
    .opcode_in(dec_opcode_in),
    .raw_opcode_in(raw_opcode_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:125242.16-125246.4" *)
  \dec_oe$152  dec_oe (
    .SPR_OE(dec_SPR_OE),
    .SPR_internal_op(dec_SPR_internal_op),
    .sel_in(dec_oe_sel_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:125247.16-125250.4" *)
  \dec_rc$151  dec_rc (
    .SPR_Rc(dec_SPR_Rc),
    .sel_in(dec_rc_sel_in)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _04_;
    (* src = "libresoc.v:125252.5-125252.29" *)
    casez (\initial )
      /* src = "libresoc.v:125252.9-125252.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$14 , \$6  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _04_ = 7'h00;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _04_ = 7'h00;
        end
      default:
          _04_ = dec_SPR_internal_op;
    endcase
  end
  always @* begin
      SPR__insn_type <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _03_;
    (* src = "libresoc.v:125265.5-125265.29" *)
    casez (\initial )
      /* src = "libresoc.v:125265.9-125265.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:850" *)
    casez ({ \$48 , \$40  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _03_ = 14'h0000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _03_ = dec_SPR_function_unit;
        end
    endcase
  end
  always @* begin
      SPR__fn_unit <= _00_;
  end
  assign \$10  = _05_;
  assign \$12  = _23_;
  assign \$14  = _06_;
  assign \$16  = _13_;
  assign \$18  = _14_;
  assign \$20  = _25_;
  assign \$22  = _15_;
  assign \$24  = _16_;
  assign \$26  = _26_;
  assign \$28  = _17_;
  assign \$2  = _18_;
  assign \$30  = _27_;
  assign \$32  = _19_;
  assign \$34  = _28_;
  assign \$36  = _20_;
  assign \$38  = _07_;
  assign \$40  = _08_;
  assign \$42  = _21_;
  assign \$44  = _09_;
  assign \$46  = _24_;
  assign \$48  = _10_;
  assign \$4  = _11_;
  assign \$6  = _12_;
  assign \$8  = _22_;
  assign SPR__is_32bit = dec_SPR_is_32b;
  assign is_mmu_spr = \$34 ;
  assign is_spr_mv = \$20 ;
  assign spr = { dec_SPR_SPR[4:0], dec_SPR_SPR[9:5] };
  assign dec_oe_sel_in = dec_SPR_rc_sel;
  assign dec_rc_sel_in = dec_SPR_rc_sel;
  assign \insn_in$1  = dec_opcode_in;
  assign insn_in = dec_opcode_in;
  assign SPR__insn = dec_opcode_in;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_a" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:125292.1-125845.10" *)
module dec_a(SPR, sv_nz, sel_in, reg_a, reg_a_ok, spr_a, spr_a_ok, fast_a, fast_a_ok, RS, RA, BO, XL_XO, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg _01_;
  (* src = "libresoc.v:125293.7-125293.20" *)
  reg _02_;
  (* src = "libresoc.v:125717.3-125732.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:125733.3-125748.6" *)
  reg _04_;
  (* src = "libresoc.v:125785.3-125803.6" *)
  reg [9:0] _05_;
  (* src = "libresoc.v:125823.3-125842.6" *)
  reg [9:0] _06_;
  (* src = "libresoc.v:125823.3-125842.6" *)
  reg _07_;
  (* src = "libresoc.v:125804.3-125822.6" *)
  reg [9:0] _08_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg _10_;
  (* src = "libresoc.v:125717.3-125732.6" *)
  reg [4:0] _11_;
  (* src = "libresoc.v:125733.3-125748.6" *)
  reg _12_;
  (* src = "libresoc.v:125785.3-125803.6" *)
  reg [9:0] _13_;
  (* src = "libresoc.v:125823.3-125842.6" *)
  reg [9:0] _14_;
  (* src = "libresoc.v:125823.3-125842.6" *)
  reg _15_;
  (* src = "libresoc.v:125804.3-125822.6" *)
  reg [9:0] _16_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg [2:0] _17_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg _18_;
  (* src = "libresoc.v:125717.3-125732.6" *)
  reg [4:0] _19_;
  (* src = "libresoc.v:125733.3-125748.6" *)
  reg _20_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg [2:0] _21_;
  (* src = "libresoc.v:125749.3-125784.6" *)
  reg _22_;
  (* src = "libresoc.v:125692.18-125692.108" *)
  wire _23_;
  (* src = "libresoc.v:125701.18-125701.110" *)
  wire _24_;
  (* src = "libresoc.v:125706.18-125706.113" *)
  wire _25_;
  (* src = "libresoc.v:125694.18-125694.112" *)
  wire _26_;
  (* src = "libresoc.v:125695.18-125695.112" *)
  wire _27_;
  (* src = "libresoc.v:125696.17-125696.111" *)
  wire _28_;
  (* src = "libresoc.v:125697.18-125697.112" *)
  wire _29_;
  (* src = "libresoc.v:125703.18-125703.112" *)
  wire _30_;
  (* src = "libresoc.v:125707.17-125707.111" *)
  wire _31_;
  (* src = "libresoc.v:125698.18-125698.109" *)
  wire _32_;
  (* src = "libresoc.v:125699.18-125699.111" *)
  wire _33_;
  (* src = "libresoc.v:125708.17-125708.108" *)
  wire _34_;
  (* src = "libresoc.v:125709.17-125709.110" *)
  wire _35_;
  (* src = "libresoc.v:125704.18-125704.105" *)
  wire _36_;
  (* src = "libresoc.v:125705.18-125705.108" *)
  wire _37_;
  (* src = "libresoc.v:125691.17-125691.107" *)
  wire _38_;
  (* src = "libresoc.v:125693.18-125693.109" *)
  wire _39_;
  (* src = "libresoc.v:125700.18-125700.110" *)
  wire _40_;
  (* src = "libresoc.v:125702.18-125702.110" *)
  wire _41_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [9:0] SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  input [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_a;
  reg [2:0] fast_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_a_ok;
  reg fast_a_ok;
  (* src = "libresoc.v:125293.7-125293.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126" *)
  wire [4:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [4:0] reg_a;
  reg [4:0] reg_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg_a_ok;
  reg reg_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:136" *)
  wire [4:0] rs;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:161" *)
  reg [9:0] spr;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spr_a;
  reg [9:0] spr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr_a_ok;
  reg spr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] sprmap_fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire sprmap_fast_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *)
  reg [9:0] sprmap_spr_i;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] sprmap_spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire sprmap_spr_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" *)
  input sv_nz;
  assign _23_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$9 ;
  assign _24_ = \$19  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$25 ;
  assign _25_ = XL_XO[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) \$35 ;
  assign _26_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4;
  assign _27_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1;
  assign _28_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128" *) 3'h1;
  assign _29_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2;
  assign _30_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *) 3'h4;
  assign _31_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" *) 3'h2;
  assign _32_ = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00;
  assign _33_ = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0;
  assign _34_ = ra != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 5'h00;
  assign _35_ = sv_nz != (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) 1'h0;
  assign _36_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *) BO[2];
  assign _37_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *) XL_XO[5];
  assign _38_ = \$5  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$7 ;
  assign _39_ = \$1  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$11 ;
  assign _40_ = \$21  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$23 ;
  assign _41_ = \$17  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *) \$27 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:125710.10-125716.4" *)
  sprmap sprmap (
    .fast_o(sprmap_fast_o),
    .fast_o_ok(sprmap_fast_o_ok),
    .spr_i(sprmap_spr_i),
    .spr_o(sprmap_spr_o),
    .spr_o_ok(sprmap_spr_o_ok)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _19_;
    (* src = "libresoc.v:125718.5-125718.29" *)
    casez (\initial )
      /* src = "libresoc.v:125718.9-125718.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _11_ = ra;
        end
      default:
          _11_ = 5'h00;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *)
    casez (\$15 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _19_ = rs;
        end
      default:
          _19_ = _11_;
    endcase
  end
  always @* begin
      reg_a <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _20_;
    (* src = "libresoc.v:125734.5-125734.29" *)
    casez (\initial )
      /* src = "libresoc.v:125734.9-125734.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" *)
    casez (\$29 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" *)
    casez (\$31 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = 1'h1;
        end
      default:
          _20_ = _12_;
    endcase
  end
  always @* begin
      reg_a_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    _01_ = _10_;
    (* src = "libresoc.v:125750.5-125750.29" *)
    casez (\initial )
      /* src = "libresoc.v:125750.9-125750.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
        begin
          _09_ = _17_;
          _10_ = _18_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147" *)
          casez (\$33 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _17_ = 3'h0;
                _18_ = 1'h1;
              end
            default:
              begin
                _17_ = 3'h0;
                _18_ = 1'h0;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
        begin
          _09_ = _21_;
          _10_ = _22_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:154" *)
          casez (\$37 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _21_ = 3'h0;
                _22_ = 1'h1;
              end
            default:
              begin
                _21_ = 3'h0;
                _22_ = 1'h0;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e:
        begin
          { _10_, _09_ } = { sprmap_fast_o_ok, sprmap_fast_o };
        end
      default:
        begin
          _09_ = 3'h0;
          _10_ = 1'h0;
        end
    endcase
  end
  always @* begin
      fast_a <= _00_;
      fast_a_ok <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:125786.5-125786.29" *)
    casez (\initial )
      /* src = "libresoc.v:125786.9-125786.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
          _13_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
          _13_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e:
        begin
          _13_ = { SPR[4:0], SPR[9:5] };
        end
      default:
          _13_ = 10'h000;
    endcase
  end
  always @* begin
      spr <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:125805.5-125805.29" *)
    casez (\initial )
      /* src = "libresoc.v:125805.9-125805.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
          _16_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
          _16_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e:
        begin
          _16_ = spr;
        end
      default:
          _16_ = 10'h000;
    endcase
  end
  always @* begin
      sprmap_spr_i <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    _07_ = _15_;
    (* src = "libresoc.v:125824.5-125824.29" *)
    casez (\initial )
      /* src = "libresoc.v:125824.9-125824.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e:
        begin
          { _15_, _14_ } = { sprmap_spr_o_ok, sprmap_spr_o };
        end
      default:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
    endcase
  end
  always @* begin
      spr_a <= _06_;
      spr_a_ok <= _07_;
  end
  assign \$9  = _38_;
  assign \$11  = _23_;
  assign \$13  = _39_;
  assign \$15  = _26_;
  assign \$17  = _27_;
  assign \$1  = _28_;
  assign \$19  = _29_;
  assign \$21  = _32_;
  assign \$23  = _33_;
  assign \$25  = _40_;
  assign \$27  = _24_;
  assign \$29  = _41_;
  assign \$31  = _30_;
  assign \$33  = _36_;
  assign \$35  = _37_;
  assign \$37  = _25_;
  assign \$3  = _31_;
  assign \$5  = _34_;
  assign \$7  = _35_;
  assign rs = RS;
  assign ra = RA;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec_ai" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:125849.1-125894.10" *)
module dec_ai(sel_in, immz_out, ALU_RA, sv_nz);
  reg \initial  = 0;
  (* src = "libresoc.v:125883.3-125892.6" *)
  reg _00_;
  (* src = "libresoc.v:125850.7-125850.20" *)
  reg _01_;
  (* src = "libresoc.v:125883.3-125892.6" *)
  reg _02_;
  (* src = "libresoc.v:125878.17-125878.107" *)
  wire _03_;
  (* src = "libresoc.v:125881.17-125881.107" *)
  wire _04_;
  (* src = "libresoc.v:125879.17-125879.111" *)
  wire _05_;
  (* src = "libresoc.v:125880.17-125880.108" *)
  wire _06_;
  (* src = "libresoc.v:125882.17-125882.110" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] ALU_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  output immz_out;
  reg immz_out;
  (* src = "libresoc.v:125850.7-125850.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *)
  wire [4:0] ra;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  input sv_nz;
  assign _03_ = \$5  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ;
  assign _04_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ;
  assign _05_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2;
  assign _06_ = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00;
  assign _07_ = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:125884.5-125884.29" *)
    casez (\initial )
      /* src = "libresoc.v:125884.9-125884.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _02_ = 1'h1;
        end
      default:
          _02_ = 1'h0;
    endcase
  end
  always @* begin
      immz_out <= _00_;
  end
  assign \$9  = _03_;
  assign \$1  = _05_;
  assign \$3  = _06_;
  assign \$5  = _04_;
  assign \$7  = _07_;
  assign ra = ALU_RA;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec_ai" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:125898.1-125943.10" *)
module \dec_ai$148 (sel_in, immz_out, LOGICAL_RA, sv_nz);
  reg \initial  = 0;
  (* src = "libresoc.v:125932.3-125941.6" *)
  reg _00_;
  (* src = "libresoc.v:125899.7-125899.20" *)
  reg _01_;
  (* src = "libresoc.v:125932.3-125941.6" *)
  reg _02_;
  (* src = "libresoc.v:125927.17-125927.107" *)
  wire _03_;
  (* src = "libresoc.v:125930.17-125930.107" *)
  wire _04_;
  (* src = "libresoc.v:125928.17-125928.111" *)
  wire _05_;
  (* src = "libresoc.v:125929.17-125929.108" *)
  wire _06_;
  (* src = "libresoc.v:125931.17-125931.110" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] LOGICAL_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  output immz_out;
  reg immz_out;
  (* src = "libresoc.v:125899.7-125899.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *)
  wire [4:0] ra;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  input sv_nz;
  assign _03_ = \$5  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ;
  assign _04_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ;
  assign _05_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2;
  assign _06_ = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00;
  assign _07_ = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:125933.5-125933.29" *)
    casez (\initial )
      /* src = "libresoc.v:125933.9-125933.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _02_ = 1'h1;
        end
      default:
          _02_ = 1'h0;
    endcase
  end
  always @* begin
      immz_out <= _00_;
  end
  assign \$9  = _03_;
  assign \$1  = _05_;
  assign \$3  = _06_;
  assign \$5  = _04_;
  assign \$7  = _07_;
  assign ra = LOGICAL_RA;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec_ai" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:125947.1-125992.10" *)
module \dec_ai$156 (sel_in, immz_out, DIV_RA, sv_nz);
  reg \initial  = 0;
  (* src = "libresoc.v:125981.3-125990.6" *)
  reg _00_;
  (* src = "libresoc.v:125948.7-125948.20" *)
  reg _01_;
  (* src = "libresoc.v:125981.3-125990.6" *)
  reg _02_;
  (* src = "libresoc.v:125976.17-125976.107" *)
  wire _03_;
  (* src = "libresoc.v:125979.17-125979.107" *)
  wire _04_;
  (* src = "libresoc.v:125977.17-125977.111" *)
  wire _05_;
  (* src = "libresoc.v:125978.17-125978.108" *)
  wire _06_;
  (* src = "libresoc.v:125980.17-125980.110" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] DIV_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  output immz_out;
  reg immz_out;
  (* src = "libresoc.v:125948.7-125948.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *)
  wire [4:0] ra;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  input sv_nz;
  assign _03_ = \$5  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ;
  assign _04_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ;
  assign _05_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2;
  assign _06_ = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00;
  assign _07_ = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:125982.5-125982.29" *)
    casez (\initial )
      /* src = "libresoc.v:125982.9-125982.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _02_ = 1'h1;
        end
      default:
          _02_ = 1'h0;
    endcase
  end
  always @* begin
      immz_out <= _00_;
  end
  assign \$9  = _03_;
  assign \$1  = _05_;
  assign \$3  = _06_;
  assign \$5  = _04_;
  assign \$7  = _07_;
  assign ra = DIV_RA;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec_ai" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:125996.1-126041.10" *)
module \dec_ai$169 (sel_in, immz_out, LDST_RA, sv_nz);
  reg \initial  = 0;
  (* src = "libresoc.v:126030.3-126039.6" *)
  reg _00_;
  (* src = "libresoc.v:125997.7-125997.20" *)
  reg _01_;
  (* src = "libresoc.v:126030.3-126039.6" *)
  reg _02_;
  (* src = "libresoc.v:126025.17-126025.107" *)
  wire _03_;
  (* src = "libresoc.v:126028.17-126028.107" *)
  wire _04_;
  (* src = "libresoc.v:126026.17-126026.111" *)
  wire _05_;
  (* src = "libresoc.v:126027.17-126027.108" *)
  wire _06_;
  (* src = "libresoc.v:126029.17-126029.110" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] LDST_RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180" *)
  output immz_out;
  reg immz_out;
  (* src = "libresoc.v:125997.7-125997.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188" *)
  wire [4:0] ra;
  (* enum_base_type = "In1Sel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RA" *)
  (* enum_value_010 = "RA_OR_ZERO" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:179" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181" *)
  input sv_nz;
  assign _03_ = \$5  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) \$7 ;
  assign _04_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) \$3 ;
  assign _05_ = sel_in == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 3'h2;
  assign _06_ = ra == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191" *) 5'h00;
  assign _07_ = sv_nz == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *) 1'h0;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:126031.5-126031.29" *)
    casez (\initial )
      /* src = "libresoc.v:126031.9-126031.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _02_ = 1'h1;
        end
      default:
          _02_ = 1'h0;
    endcase
  end
  always @* begin
      immz_out <= _00_;
  end
  assign \$9  = _03_;
  assign \$1  = _05_;
  assign \$3  = _06_;
  assign \$5  = _04_;
  assign \$7  = _07_;
  assign ra = LDST_RA;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_b" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:126045.1-126243.10" *)
module dec_b(sel_in, reg_b, reg_b_ok, fast_b, fast_b_ok, RS, RB, XL_XO, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:126207.3-126224.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:126225.3-126242.6" *)
  reg _01_;
  (* src = "libresoc.v:126046.7-126046.20" *)
  reg _02_;
  (* src = "libresoc.v:126177.3-126191.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:126192.3-126206.6" *)
  reg _04_;
  (* src = "libresoc.v:126207.3-126224.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:126225.3-126242.6" *)
  reg _06_;
  (* src = "libresoc.v:126177.3-126191.6" *)
  reg [6:0] _07_;
  (* src = "libresoc.v:126192.3-126206.6" *)
  reg _08_;
  (* src = "libresoc.v:126207.3-126224.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:126225.3-126242.6" *)
  reg _10_;
  (* src = "libresoc.v:126171.17-126171.117" *)
  wire _11_;
  (* src = "libresoc.v:126175.17-126175.117" *)
  wire _12_;
  (* src = "libresoc.v:126173.17-126173.100" *)
  wire [6:0] _13_;
  (* src = "libresoc.v:126174.17-126174.100" *)
  wire [6:0] _14_;
  (* src = "libresoc.v:126172.18-126172.108" *)
  wire _15_;
  (* src = "libresoc.v:126176.17-126176.107" *)
  wire _16_;
  (* src = "libresoc.v:126173.17-126173.100" *)
  wire [6:0] _17_;
  (* src = "libresoc.v:126174.17-126174.100" *)
  wire [6:0] _18_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [6:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [6:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  input [9:0] XL_XO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_b;
  reg [2:0] fast_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_b_ok;
  reg fast_b_ok;
  (* src = "libresoc.v:126046.7-126046.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [6:0] reg_b;
  reg [6:0] reg_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg_b_ok;
  reg reg_b_ok;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209" *)
  input [3:0] sel_in;
  assign _11_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08;
  assign _12_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *) 7'h08;
  assign _13_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RB;
  assign _14_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) RS;
  assign _15_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9];
  assign _16_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *) XL_XO[9];
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _13_;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _14_;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _07_;
    (* src = "libresoc.v:126178.5-126178.29" *)
    casez (\initial )
      /* src = "libresoc.v:126178.9-126178.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _07_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hd:
        begin
          _07_ = \$3 ;
        end
      default:
          _07_ = 7'h00;
    endcase
  end
  always @* begin
      reg_b <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _08_;
    (* src = "libresoc.v:126193.5-126193.29" *)
    casez (\initial )
      /* src = "libresoc.v:126193.9-126193.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h1:
        begin
          _08_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hd:
        begin
          _08_ = 1'h1;
        end
      default:
          _08_ = 1'h0;
    endcase
  end
  always @* begin
      reg_b_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _05_;
    (* src = "libresoc.v:126208.5-126208.29" *)
    casez (\initial )
      /* src = "libresoc.v:126208.9-126208.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *)
    casez (\$5 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _05_ = _09_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *)
          casez ({ XL_XO[5], \$7  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _09_ = 3'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _09_ = 3'h2;
              end
            default:
                _09_ = 3'h0;
          endcase
        end
      default:
          _05_ = 3'h0;
    endcase
  end
  always @* begin
      fast_b <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _06_;
    (* src = "libresoc.v:126226.5-126226.29" *)
    casez (\initial )
      /* src = "libresoc.v:126226.9-126226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _06_ = _10_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:237" *)
          casez ({ XL_XO[5], \$11  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _10_ = 1'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _10_ = 1'h1;
              end
            default:
                _10_ = 1'h0;
          endcase
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      fast_b_ok <= _01_;
  end
  assign \$9  = _11_;
  assign \$11  = _15_;
  assign \$1  = _17_;
  assign \$3  = _18_;
  assign \$5  = _12_;
  assign \$7  = _16_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:126247.1-126584.10" *)
module dec_bi(imm_b, imm_b_ok, ALU_SI, ALU_UI, ALU_SH32, ALU_sh, ALU_LI, ALU_BD, ALU_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:126514.3-126544.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:126545.3-126579.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:126336.3-126382.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:126383.3-126429.6" *)
  reg _03_;
  (* src = "libresoc.v:126248.7-126248.20" *)
  reg _04_;
  (* src = "libresoc.v:126487.3-126513.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:126430.3-126444.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:126445.3-126463.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:126464.3-126486.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:126514.3-126544.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:126545.3-126579.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:126336.3-126382.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:126383.3-126429.6" *)
  reg _12_;
  (* src = "libresoc.v:126487.3-126513.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:126430.3-126444.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:126445.3-126463.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:126464.3-126486.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:126326.17-126326.104" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:126327.18-126327.107" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:126330.17-126330.104" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:126334.17-126334.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:126326.17-126326.104" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:126327.18-126327.107" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:126330.17-126330.104" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:126334.17-126334.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:126328.18-126328.114" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:126329.18-126329.113" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:126331.18-126331.113" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:126332.18-126332.113" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:126333.17-126333.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] ALU_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] ALU_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] ALU_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] ALU_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] ALU_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] ALU_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] ALU_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:126248.7-126248.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) ALU_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = ALU_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = ALU_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = ALU_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = ALU_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:126337.5-126337.29" *)
    casez (\initial )
      /* src = "libresoc.v:126337.9-126337.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:126384.5-126384.29" *)
    casez (\initial )
      /* src = "libresoc.v:126384.9-126384.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:126431.5-126431.29" *)
    casez (\initial )
      /* src = "libresoc.v:126431.9-126431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = ALU_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:126446.5-126446.29" *)
    casez (\initial )
      /* src = "libresoc.v:126446.9-126446.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:126465.5-126465.29" *)
    casez (\initial )
      /* src = "libresoc.v:126465.9-126465.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = ALU_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:126488.5-126488.29" *)
    casez (\initial )
      /* src = "libresoc.v:126488.9-126488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:126515.5-126515.29" *)
    casez (\initial )
      /* src = "libresoc.v:126515.9-126515.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:126546.5-126546.29" *)
    casez (\initial )
      /* src = "libresoc.v:126546.9-126546.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:126588.1-126925.10" *)
module \dec_bi$144 (imm_b, imm_b_ok, BRANCH_SI, BRANCH_UI, BRANCH_SH32, BRANCH_sh, BRANCH_LI, BRANCH_BD, BRANCH_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:126855.3-126885.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:126886.3-126920.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:126677.3-126723.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:126724.3-126770.6" *)
  reg _03_;
  (* src = "libresoc.v:126589.7-126589.20" *)
  reg _04_;
  (* src = "libresoc.v:126828.3-126854.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:126771.3-126785.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:126786.3-126804.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:126805.3-126827.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:126855.3-126885.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:126886.3-126920.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:126677.3-126723.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:126724.3-126770.6" *)
  reg _12_;
  (* src = "libresoc.v:126828.3-126854.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:126771.3-126785.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:126786.3-126804.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:126805.3-126827.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:126667.17-126667.107" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:126668.18-126668.110" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:126671.17-126671.107" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:126675.17-126675.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:126667.17-126667.107" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:126668.18-126668.110" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:126671.17-126671.107" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:126675.17-126675.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:126669.18-126669.117" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:126670.18-126670.116" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:126672.18-126672.116" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:126673.18-126673.116" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:126674.17-126674.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] BRANCH_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] BRANCH_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] BRANCH_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BRANCH_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] BRANCH_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] BRANCH_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] BRANCH_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:126589.7-126589.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) BRANCH_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = BRANCH_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = BRANCH_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = BRANCH_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = BRANCH_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:126678.5-126678.29" *)
    casez (\initial )
      /* src = "libresoc.v:126678.9-126678.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:126725.5-126725.29" *)
    casez (\initial )
      /* src = "libresoc.v:126725.9-126725.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:126772.5-126772.29" *)
    casez (\initial )
      /* src = "libresoc.v:126772.9-126772.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = BRANCH_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:126787.5-126787.29" *)
    casez (\initial )
      /* src = "libresoc.v:126787.9-126787.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:126806.5-126806.29" *)
    casez (\initial )
      /* src = "libresoc.v:126806.9-126806.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = BRANCH_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:126829.5-126829.29" *)
    casez (\initial )
      /* src = "libresoc.v:126829.9-126829.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:126856.5-126856.29" *)
    casez (\initial )
      /* src = "libresoc.v:126856.9-126856.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:126887.5-126887.29" *)
    casez (\initial )
      /* src = "libresoc.v:126887.9-126887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:126929.1-127266.10" *)
module \dec_bi$149 (imm_b, imm_b_ok, LOGICAL_SI, LOGICAL_UI, LOGICAL_SH32, LOGICAL_sh, LOGICAL_LI, LOGICAL_BD, LOGICAL_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:127196.3-127226.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:127227.3-127261.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:127018.3-127064.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:127065.3-127111.6" *)
  reg _03_;
  (* src = "libresoc.v:126930.7-126930.20" *)
  reg _04_;
  (* src = "libresoc.v:127169.3-127195.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:127112.3-127126.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:127127.3-127145.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:127146.3-127168.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:127196.3-127226.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:127227.3-127261.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:127018.3-127064.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:127065.3-127111.6" *)
  reg _12_;
  (* src = "libresoc.v:127169.3-127195.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:127112.3-127126.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:127127.3-127145.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:127146.3-127168.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:127008.17-127008.108" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:127009.18-127009.111" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:127012.17-127012.108" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:127016.17-127016.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:127008.17-127008.108" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:127009.18-127009.111" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:127012.17-127012.108" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:127016.17-127016.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:127010.18-127010.118" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:127011.18-127011.117" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:127013.18-127013.117" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:127014.18-127014.117" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:127015.17-127015.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] LOGICAL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] LOGICAL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] LOGICAL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] LOGICAL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] LOGICAL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] LOGICAL_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] LOGICAL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:126930.7-126930.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LOGICAL_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = LOGICAL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = LOGICAL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = LOGICAL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = LOGICAL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:127019.5-127019.29" *)
    casez (\initial )
      /* src = "libresoc.v:127019.9-127019.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:127066.5-127066.29" *)
    casez (\initial )
      /* src = "libresoc.v:127066.9-127066.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:127113.5-127113.29" *)
    casez (\initial )
      /* src = "libresoc.v:127113.9-127113.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = LOGICAL_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:127128.5-127128.29" *)
    casez (\initial )
      /* src = "libresoc.v:127128.9-127128.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:127147.5-127147.29" *)
    casez (\initial )
      /* src = "libresoc.v:127147.9-127147.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = LOGICAL_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:127170.5-127170.29" *)
    casez (\initial )
      /* src = "libresoc.v:127170.9-127170.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:127197.5-127197.29" *)
    casez (\initial )
      /* src = "libresoc.v:127197.9-127197.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:127228.5-127228.29" *)
    casez (\initial )
      /* src = "libresoc.v:127228.9-127228.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:127270.1-127607.10" *)
module \dec_bi$157 (imm_b, imm_b_ok, DIV_SI, DIV_UI, DIV_SH32, DIV_sh, DIV_LI, DIV_BD, DIV_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:127537.3-127567.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:127568.3-127602.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:127359.3-127405.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:127406.3-127452.6" *)
  reg _03_;
  (* src = "libresoc.v:127271.7-127271.20" *)
  reg _04_;
  (* src = "libresoc.v:127510.3-127536.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:127453.3-127467.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:127468.3-127486.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:127487.3-127509.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:127537.3-127567.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:127568.3-127602.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:127359.3-127405.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:127406.3-127452.6" *)
  reg _12_;
  (* src = "libresoc.v:127510.3-127536.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:127453.3-127467.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:127468.3-127486.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:127487.3-127509.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:127349.17-127349.104" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:127350.18-127350.107" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:127353.17-127353.104" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:127357.17-127357.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:127349.17-127349.104" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:127350.18-127350.107" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:127353.17-127353.104" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:127357.17-127357.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:127351.18-127351.114" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:127352.18-127352.113" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:127354.18-127354.113" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:127355.18-127355.113" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:127356.17-127356.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] DIV_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] DIV_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] DIV_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] DIV_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] DIV_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] DIV_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] DIV_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:127271.7-127271.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) DIV_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = DIV_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = DIV_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = DIV_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = DIV_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:127360.5-127360.29" *)
    casez (\initial )
      /* src = "libresoc.v:127360.9-127360.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:127407.5-127407.29" *)
    casez (\initial )
      /* src = "libresoc.v:127407.9-127407.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:127454.5-127454.29" *)
    casez (\initial )
      /* src = "libresoc.v:127454.9-127454.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = DIV_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:127469.5-127469.29" *)
    casez (\initial )
      /* src = "libresoc.v:127469.9-127469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:127488.5-127488.29" *)
    casez (\initial )
      /* src = "libresoc.v:127488.9-127488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = DIV_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:127511.5-127511.29" *)
    casez (\initial )
      /* src = "libresoc.v:127511.9-127511.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:127538.5-127538.29" *)
    casez (\initial )
      /* src = "libresoc.v:127538.9-127538.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:127569.5-127569.29" *)
    casez (\initial )
      /* src = "libresoc.v:127569.9-127569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:127611.1-127948.10" *)
module \dec_bi$161 (imm_b, imm_b_ok, MUL_SI, MUL_UI, MUL_SH32, MUL_sh, MUL_LI, MUL_BD, MUL_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:127878.3-127908.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:127909.3-127943.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:127700.3-127746.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:127747.3-127793.6" *)
  reg _03_;
  (* src = "libresoc.v:127612.7-127612.20" *)
  reg _04_;
  (* src = "libresoc.v:127851.3-127877.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:127794.3-127808.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:127809.3-127827.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:127828.3-127850.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:127878.3-127908.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:127909.3-127943.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:127700.3-127746.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:127747.3-127793.6" *)
  reg _12_;
  (* src = "libresoc.v:127851.3-127877.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:127794.3-127808.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:127809.3-127827.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:127828.3-127850.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:127690.17-127690.104" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:127691.18-127691.107" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:127694.17-127694.104" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:127698.17-127698.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:127690.17-127690.104" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:127691.18-127691.107" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:127694.17-127694.104" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:127698.17-127698.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:127692.18-127692.114" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:127693.18-127693.113" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:127695.18-127695.113" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:127696.18-127696.113" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:127697.17-127697.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] MUL_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] MUL_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] MUL_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] MUL_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] MUL_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] MUL_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] MUL_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:127612.7-127612.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) MUL_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = MUL_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = MUL_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = MUL_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = MUL_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:127701.5-127701.29" *)
    casez (\initial )
      /* src = "libresoc.v:127701.9-127701.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:127748.5-127748.29" *)
    casez (\initial )
      /* src = "libresoc.v:127748.9-127748.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:127795.5-127795.29" *)
    casez (\initial )
      /* src = "libresoc.v:127795.9-127795.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = MUL_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:127810.5-127810.29" *)
    casez (\initial )
      /* src = "libresoc.v:127810.9-127810.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:127829.5-127829.29" *)
    casez (\initial )
      /* src = "libresoc.v:127829.9-127829.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = MUL_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:127852.5-127852.29" *)
    casez (\initial )
      /* src = "libresoc.v:127852.9-127852.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:127879.5-127879.29" *)
    casez (\initial )
      /* src = "libresoc.v:127879.9-127879.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:127910.5-127910.29" *)
    casez (\initial )
      /* src = "libresoc.v:127910.9-127910.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:127952.1-128289.10" *)
module \dec_bi$165 (imm_b, imm_b_ok, SHIFT_ROT_SI, SHIFT_ROT_UI, SHIFT_ROT_SH32, SHIFT_ROT_sh, SHIFT_ROT_LI, SHIFT_ROT_BD, SHIFT_ROT_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:128219.3-128249.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:128250.3-128284.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:128041.3-128087.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:128088.3-128134.6" *)
  reg _03_;
  (* src = "libresoc.v:127953.7-127953.20" *)
  reg _04_;
  (* src = "libresoc.v:128192.3-128218.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:128135.3-128149.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:128150.3-128168.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:128169.3-128191.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:128219.3-128249.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:128250.3-128284.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:128041.3-128087.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:128088.3-128134.6" *)
  reg _12_;
  (* src = "libresoc.v:128192.3-128218.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:128135.3-128149.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:128150.3-128168.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:128169.3-128191.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:128031.17-128031.110" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:128032.18-128032.113" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:128035.17-128035.110" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:128039.17-128039.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:128031.17-128031.110" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:128032.18-128032.113" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:128035.17-128035.110" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:128039.17-128039.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:128033.18-128033.120" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:128034.18-128034.119" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:128036.18-128036.119" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:128037.18-128037.119" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:128038.17-128038.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] SHIFT_ROT_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] SHIFT_ROT_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] SHIFT_ROT_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] SHIFT_ROT_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] SHIFT_ROT_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] SHIFT_ROT_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] SHIFT_ROT_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:127953.7-127953.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) SHIFT_ROT_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = SHIFT_ROT_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = SHIFT_ROT_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = SHIFT_ROT_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = SHIFT_ROT_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:128042.5-128042.29" *)
    casez (\initial )
      /* src = "libresoc.v:128042.9-128042.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:128089.5-128089.29" *)
    casez (\initial )
      /* src = "libresoc.v:128089.9-128089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:128136.5-128136.29" *)
    casez (\initial )
      /* src = "libresoc.v:128136.9-128136.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = SHIFT_ROT_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:128151.5-128151.29" *)
    casez (\initial )
      /* src = "libresoc.v:128151.9-128151.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:128170.5-128170.29" *)
    casez (\initial )
      /* src = "libresoc.v:128170.9-128170.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = SHIFT_ROT_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:128193.5-128193.29" *)
    casez (\initial )
      /* src = "libresoc.v:128193.9-128193.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:128220.5-128220.29" *)
    casez (\initial )
      /* src = "libresoc.v:128220.9-128220.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:128251.5-128251.29" *)
    casez (\initial )
      /* src = "libresoc.v:128251.9-128251.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec_bi" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:128293.1-128630.10" *)
module \dec_bi$170 (imm_b, imm_b_ok, LDST_SI, LDST_UI, LDST_SH32, LDST_sh, LDST_LI, LDST_BD, LDST_DS, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:128560.3-128590.6" *)
  reg [15:0] _00_;
  (* src = "libresoc.v:128591.3-128625.6" *)
  reg [15:0] _01_;
  (* src = "libresoc.v:128382.3-128428.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:128429.3-128475.6" *)
  reg _03_;
  (* src = "libresoc.v:128294.7-128294.20" *)
  reg _04_;
  (* src = "libresoc.v:128533.3-128559.6" *)
  reg [25:0] _05_;
  (* src = "libresoc.v:128476.3-128490.6" *)
  reg [15:0] _06_;
  (* src = "libresoc.v:128491.3-128509.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:128510.3-128532.6" *)
  reg [15:0] _08_;
  (* src = "libresoc.v:128560.3-128590.6" *)
  reg [15:0] _09_;
  (* src = "libresoc.v:128591.3-128625.6" *)
  reg [15:0] _10_;
  (* src = "libresoc.v:128382.3-128428.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:128429.3-128475.6" *)
  reg _12_;
  (* src = "libresoc.v:128533.3-128559.6" *)
  reg [25:0] _13_;
  (* src = "libresoc.v:128476.3-128490.6" *)
  reg [15:0] _14_;
  (* src = "libresoc.v:128491.3-128509.6" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:128510.3-128532.6" *)
  reg [15:0] _16_;
  (* src = "libresoc.v:128372.17-128372.105" *)
  wire [63:0] _17_;
  (* src = "libresoc.v:128373.18-128373.108" *)
  wire [63:0] _18_;
  (* src = "libresoc.v:128376.17-128376.105" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:128380.17-128380.102" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:128372.17-128372.105" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:128373.18-128373.108" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:128376.17-128376.105" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:128380.17-128380.102" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:128374.18-128374.115" *)
  wire [46:0] _25_;
  (* src = "libresoc.v:128375.18-128375.114" *)
  wire [26:0] _26_;
  (* src = "libresoc.v:128377.18-128377.114" *)
  wire [16:0] _27_;
  (* src = "libresoc.v:128378.18-128378.114" *)
  wire [16:0] _28_;
  (* src = "libresoc.v:128379.17-128379.109" *)
  wire [46:0] _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *)
  wire [46:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *)
  wire [26:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *)
  wire [16:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *)
  wire [16:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [63:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *)
  wire [46:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295" *)
  wire [63:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  wire [63:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] LDST_BD;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [13:0] LDST_DS;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [23:0] LDST_LI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] LDST_SH32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] LDST_SI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [15:0] LDST_UI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [5:0] LDST_sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285" *)
  reg [15:0] bd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290" *)
  reg [15:0] ds;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] imm_b;
  reg [63:0] imm_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output imm_b_ok;
  reg imm_b_ok;
  (* src = "libresoc.v:128294.7-128294.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" *)
  reg [25:0] li;
  (* enum_base_type = "In2Sel" *)
  (* enum_value_0000 = "NONE" *)
  (* enum_value_0001 = "RB" *)
  (* enum_value_0010 = "CONST_UI" *)
  (* enum_value_0011 = "CONST_SI" *)
  (* enum_value_0100 = "CONST_UI_HI" *)
  (* enum_value_0101 = "CONST_SI_HI" *)
  (* enum_value_0110 = "CONST_LI" *)
  (* enum_value_0111 = "CONST_BD" *)
  (* enum_value_1000 = "CONST_DS" *)
  (* enum_value_1001 = "CONST_M1" *)
  (* enum_value_1010 = "CONST_SH" *)
  (* enum_value_1011 = "CONST_SH32" *)
  (* enum_value_1100 = "SPR" *)
  (* enum_value_1101 = "RS" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252" *)
  input [3:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" *)
  reg [15:0] si;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" *)
  reg [31:0] si_hi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" *)
  reg [15:0] ui;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_sh;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_SH32;
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) LDST_UI;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) \$4 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _17_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _18_;
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *) _19_;
  assign _24_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) _20_;
  assign _25_ = LDST_SI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271" *) 5'h10;
  assign _26_ = LDST_LI <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:281" *) 2'h2;
  assign _27_ = LDST_BD <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286" *) 2'h2;
  assign _28_ = LDST_DS <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291" *) 2'h2;
  assign _29_ = ui <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277" *) 5'h10;
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _11_;
    (* src = "libresoc.v:128383.5-128383.29" *)
    casez (\initial )
      /* src = "libresoc.v:128383.9-128383.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _11_ = \$1 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _11_ = { si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si[15], si };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _11_ = { si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi[31], si_hi };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _11_ = \$3 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _11_ = { li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li[25], li };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _11_ = { bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd[15], bd };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _11_ = { ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds[15], ds };
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _11_ = \$7 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _11_ = \$9 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _11_ = \$11 ;
        end
      default:
          _11_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      imm_b <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:128430.5-128430.29" *)
    casez (\initial )
      /* src = "libresoc.v:128430.9-128430.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'h9:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'ha:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      4'hb:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      imm_b_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    (* src = "libresoc.v:128477.5-128477.29" *)
    casez (\initial )
      /* src = "libresoc.v:128477.9-128477.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _14_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
        begin
          _14_ = LDST_SI;
        end
      default:
          _14_ = 16'h0000;
    endcase
  end
  always @* begin
      si <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _15_;
    (* src = "libresoc.v:128492.5-128492.29" *)
    casez (\initial )
      /* src = "libresoc.v:128492.9-128492.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _15_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
        begin
          _15_ = \$13 [31:0];
        end
      default:
          _15_ = 32'd0;
    endcase
  end
  always @* begin
      si_hi <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:128511.5-128511.29" *)
    casez (\initial )
      /* src = "libresoc.v:128511.9-128511.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _16_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
        begin
          _16_ = LDST_UI;
        end
      default:
          _16_ = 16'h0000;
    endcase
  end
  always @* begin
      ui <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:128534.5-128534.29" *)
    casez (\initial )
      /* src = "libresoc.v:128534.9-128534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _13_ = 26'h0000000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
        begin
          _13_ = \$16 [25:0];
        end
      default:
          _13_ = 26'h0000000;
    endcase
  end
  always @* begin
      li <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _09_;
    (* src = "libresoc.v:128561.5-128561.29" *)
    casez (\initial )
      /* src = "libresoc.v:128561.9-128561.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _09_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
        begin
          _09_ = \$19 [15:0];
        end
      default:
          _09_ = 16'h0000;
    endcase
  end
  always @* begin
      bd <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _10_;
    (* src = "libresoc.v:128592.5-128592.29" *)
    casez (\initial )
      /* src = "libresoc.v:128592.9-128592.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      4'h2:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h3:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h5:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h4:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h6:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h7:
          _10_ = 16'h0000;
      /* src = "libresoc.v:0.0-0.0" */
      4'h8:
        begin
          _10_ = \$22 [15:0];
        end
      default:
          _10_ = 16'h0000;
    endcase
  end
  always @* begin
      ds <= _01_;
  end
  assign \$9  = _21_;
  assign \$11  = _22_;
  assign \$14  = _25_;
  assign \$17  = _26_;
  assign \$1  = _23_;
  assign \$20  = _27_;
  assign \$23  = _28_;
  assign \$4  = _29_;
  assign \$3  = _24_;
  assign \$7  = 64'hffffffffffffffff;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_c" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:128634.1-128682.10" *)
module dec_c(reg_c, reg_c_ok, RS, RB, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:128635.7-128635.20" *)
  reg _0_;
  (* src = "libresoc.v:128652.3-128666.6" *)
  reg [4:0] _1_;
  (* src = "libresoc.v:128667.3-128681.6" *)
  reg _2_;
  (* src = "libresoc.v:128652.3-128666.6" *)
  reg [4:0] _3_;
  (* src = "libresoc.v:128667.3-128681.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RS;
  (* src = "libresoc.v:128635.7-128635.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [4:0] reg_c;
  reg [4:0] reg_c;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg_c_ok;
  reg reg_c_ok;
  (* enum_base_type = "In3Sel" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "RS" *)
  (* enum_value_10 = "RB" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:128653.5-128653.29" *)
    casez (\initial )
      /* src = "libresoc.v:128653.9-128653.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = RB;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = RS;
        end
      default:
          _3_ = 5'h00;
    endcase
  end
  always @* begin
      reg_c <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:128668.5-128668.29" *)
    casez (\initial )
      /* src = "libresoc.v:128668.9-128668.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      reg_c_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_cr_in" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:128686.1-129222.10" *)
module dec_cr_in(insn_in, sel_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, cr_bitfield_b, cr_bitfield_b_ok, cr_bitfield_o, cr_bitfield_o_ok, BB, BA, BT, FXM, BI, BC, X_BFA, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:129042.3-129076.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:129077.3-129107.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:128875.3-128905.6" *)
  reg _02_;
  (* src = "libresoc.v:129108.3-129138.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:128953.3-128983.6" *)
  reg _04_;
  (* src = "libresoc.v:128840.3-128874.6" *)
  reg _05_;
  (* src = "libresoc.v:128906.3-128952.6" *)
  reg [7:0] _06_;
  (* src = "libresoc.v:128984.3-129022.6" *)
  reg _07_;
  (* src = "libresoc.v:128687.7-128687.20" *)
  reg _08_;
  (* src = "libresoc.v:129139.3-129177.6" *)
  reg _09_;
  (* src = "libresoc.v:129178.3-129221.6" *)
  reg [7:0] _10_;
  (* src = "libresoc.v:129023.3-129041.6" *)
  reg [1:0] _11_;
  (* src = "libresoc.v:129042.3-129076.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:129077.3-129107.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:128875.3-128905.6" *)
  reg _14_;
  (* src = "libresoc.v:129108.3-129138.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:128953.3-128983.6" *)
  reg _16_;
  (* src = "libresoc.v:128840.3-128874.6" *)
  reg _17_;
  (* src = "libresoc.v:128906.3-128952.6" *)
  reg [7:0] _18_;
  (* src = "libresoc.v:128984.3-129022.6" *)
  reg _19_;
  (* src = "libresoc.v:129139.3-129177.6" *)
  reg _20_;
  (* src = "libresoc.v:129178.3-129221.6" *)
  reg [7:0] _21_;
  (* src = "libresoc.v:129023.3-129041.6" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:128906.3-128952.6" *)
  reg [7:0] _23_;
  (* src = "libresoc.v:129178.3-129221.6" *)
  reg [7:0] _24_;
  (* src = "libresoc.v:128833.17-128833.112" *)
  wire _25_;
  (* src = "libresoc.v:128835.17-128835.112" *)
  wire _26_;
  (* src = "libresoc.v:128832.17-128832.117" *)
  wire _27_;
  (* src = "libresoc.v:128834.17-128834.117" *)
  wire _28_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BB;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BI;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [7:0] FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  input [2:0] X_BFA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] cr_bitfield;
  reg [2:0] cr_bitfield;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] cr_bitfield_b;
  reg [2:0] cr_bitfield_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_bitfield_b_ok;
  reg cr_bitfield_b_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] cr_bitfield_o;
  reg [2:0] cr_bitfield_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_bitfield_o_ok;
  reg cr_bitfield_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_bitfield_ok;
  reg cr_bitfield_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [7:0] cr_fxm;
  reg [7:0] cr_fxm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_fxm_ok;
  reg cr_fxm_ok;
  (* src = "libresoc.v:128687.7-128687.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:543" *)
  input [31:0] insn_in;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:594" *)
  reg move_one;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  reg [7:0] ppick_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [7:0] ppick_o;
  (* enum_base_type = "CRInSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BI" *)
  (* enum_value_011 = "BFA" *)
  (* enum_value_100 = "BA_BB" *)
  (* enum_value_101 = "BC" *)
  (* enum_value_110 = "WHOLE_REG" *)
  (* enum_value_111 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" *)
  reg [1:0] sv_override;
  assign _25_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one;
  assign _26_ = \$5  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) move_one;
  assign _27_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d;
  assign _28_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *) 7'h2d;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:128836.9-128839.4" *)
  ppick ppick (
    .i(ppick_i),
    .o(ppick_o)
  );
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:128841.5-128841.29" *)
    casez (\initial )
      /* src = "libresoc.v:128841.9-128841.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _17_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _17_ = 1'h1;
        end
      default:
          _17_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bitfield_ok <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _14_;
    (* src = "libresoc.v:128876.5-128876.29" *)
    casez (\initial )
      /* src = "libresoc.v:128876.9-128876.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _14_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _14_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _14_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _14_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _14_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _14_ = 1'h1;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bitfield_b_ok <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:128907.5-128907.29" *)
    casez (\initial )
      /* src = "libresoc.v:128907.9-128907.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _18_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _18_ = _23_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
          casez (\$7 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _23_ = ppick_o;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _23_ = 8'hff;
              end
          endcase
        end
      default:
          _18_ = 8'h00;
    endcase
  end
  always @* begin
      cr_fxm <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    (* src = "libresoc.v:128954.5-128954.29" *)
    casez (\initial )
      /* src = "libresoc.v:128954.9-128954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _16_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _16_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _16_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _16_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _16_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _16_ = 1'h1;
        end
      default:
          _16_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bitfield_o_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:128985.5-128985.29" *)
    casez (\initial )
      /* src = "libresoc.v:128985.9-128985.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _19_ = 1'h1;
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      cr_fxm_ok <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _22_;
    (* src = "libresoc.v:129024.5-129024.29" *)
    casez (\initial )
      /* src = "libresoc.v:129024.9-129024.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _22_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _22_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _22_ = 2'h2;
        end
      default:
          _22_ = 2'h0;
    endcase
  end
  always @* begin
      sv_override <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:129043.5-129043.29" *)
    casez (\initial )
      /* src = "libresoc.v:129043.9-129043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _12_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _12_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _12_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _12_ = BI[4:2];
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _12_ = X_BFA;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _12_ = BA[4:2];
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _12_ = BC[4:2];
        end
      default:
          _12_ = 3'h0;
    endcase
  end
  always @* begin
      cr_bitfield <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _13_;
    (* src = "libresoc.v:129078.5-129078.29" *)
    casez (\initial )
      /* src = "libresoc.v:129078.9-129078.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _13_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _13_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _13_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _13_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _13_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _13_ = BB[4:2];
        end
      default:
          _13_ = 3'h0;
    endcase
  end
  always @* begin
      cr_bitfield_b <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _15_;
    (* src = "libresoc.v:129109.5-129109.29" *)
    casez (\initial )
      /* src = "libresoc.v:129109.9-129109.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _15_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _15_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _15_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _15_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _15_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _15_ = BT[4:2];
        end
      default:
          _15_ = 3'h0;
    endcase
  end
  always @* begin
      cr_bitfield_o <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _20_;
    (* src = "libresoc.v:129140.5-129140.29" *)
    casez (\initial )
      /* src = "libresoc.v:129140.9-129140.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _20_ = insn_in[20];
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      move_one <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _21_;
    (* src = "libresoc.v:129179.5-129179.29" *)
    casez (\initial )
      /* src = "libresoc.v:129179.9-129179.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _21_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _21_ = _24_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:596" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = FXM;
              end
            default:
                _24_ = 8'h00;
          endcase
        end
      default:
          _21_ = 8'h00;
    endcase
  end
  always @* begin
      ppick_i <= _10_;
  end
  assign \$1  = _27_;
  assign \$3  = _25_;
  assign \$5  = _28_;
  assign \$7  = _26_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_cr_out" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:129226.1-129588.10" *)
module dec_cr_out(insn_in, sel_in, rc_in, cr_fxm, cr_fxm_ok, cr_bitfield, cr_bitfield_ok, FXM, X_BF, XL_BT, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:129434.3-129460.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:129357.3-129383.6" *)
  reg _01_;
  (* src = "libresoc.v:129533.3-129587.6" *)
  reg [7:0] _02_;
  (* src = "libresoc.v:129384.3-129414.6" *)
  reg _03_;
  (* src = "libresoc.v:129227.7-129227.20" *)
  reg _04_;
  (* src = "libresoc.v:129461.3-129491.6" *)
  reg _05_;
  (* src = "libresoc.v:129492.3-129532.6" *)
  reg [7:0] _06_;
  (* src = "libresoc.v:129415.3-129433.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:129434.3-129460.6" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:129357.3-129383.6" *)
  reg _09_;
  (* src = "libresoc.v:129533.3-129587.6" *)
  reg [7:0] _10_;
  (* src = "libresoc.v:129384.3-129414.6" *)
  reg _11_;
  (* src = "libresoc.v:129461.3-129491.6" *)
  reg _12_;
  (* src = "libresoc.v:129492.3-129532.6" *)
  reg [7:0] _13_;
  (* src = "libresoc.v:129415.3-129433.6" *)
  reg [1:0] _14_;
  (* src = "libresoc.v:129533.3-129587.6" *)
  reg [7:0] _15_;
  (* src = "libresoc.v:129492.3-129532.6" *)
  reg [7:0] _16_;
  (* src = "libresoc.v:129533.3-129587.6" *)
  reg [7:0] _17_;
  (* src = "libresoc.v:129492.3-129532.6" *)
  reg [7:0] _18_;
  (* src = "libresoc.v:129533.3-129587.6" *)
  reg [7:0] _19_;
  (* src = "libresoc.v:129350.17-129350.117" *)
  wire _20_;
  (* src = "libresoc.v:129351.17-129351.117" *)
  wire _21_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [7:0] FXM;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  input [4:0] XL_BT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" *)
  input [2:0] X_BF;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] cr_bitfield;
  reg [2:0] cr_bitfield;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_bitfield_ok;
  reg cr_bitfield_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [7:0] cr_fxm;
  reg [7:0] cr_fxm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_fxm_ok;
  reg cr_fxm_ok;
  (* src = "libresoc.v:129227.7-129227.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:618" *)
  input [31:0] insn_in;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:659" *)
  reg move_one;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire ppick_en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  reg [7:0] ppick_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  wire [7:0] ppick_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:616" *)
  input rc_in;
  (* enum_base_type = "CROutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "CR0" *)
  (* enum_value_010 = "BF" *)
  (* enum_value_011 = "BT" *)
  (* enum_value_100 = "WHOLE_REG" *)
  (* enum_value_101 = "CR1" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:617" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:621" *)
  reg [1:0] sv_override;
  assign _20_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30;
  assign _21_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *) 7'h30;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:129352.15-129356.4" *)
  \ppick$175  ppick (
    .en_o(ppick_en_o),
    .i(ppick_i),
    .o(ppick_o)
  );
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _09_;
    (* src = "libresoc.v:129358.5-129358.29" *)
    casez (\initial )
      /* src = "libresoc.v:129358.9-129358.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _09_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _09_ = rc_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _09_ = rc_in;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _09_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _09_ = 1'h1;
        end
      default:
          _09_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bitfield_ok <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _11_;
    (* src = "libresoc.v:129385.5-129385.29" *)
    casez (\initial )
      /* src = "libresoc.v:129385.9-129385.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _11_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _11_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _11_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _11_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _11_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _11_ = 1'h1;
        end
      default:
          _11_ = 1'h0;
    endcase
  end
  always @* begin
      cr_fxm_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _14_;
    (* src = "libresoc.v:129416.5-129416.29" *)
    casez (\initial )
      /* src = "libresoc.v:129416.9-129416.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _14_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _14_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _14_ = 2'h2;
        end
      default:
          _14_ = 2'h0;
    endcase
  end
  always @* begin
      sv_override <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _08_;
    (* src = "libresoc.v:129435.5-129435.29" *)
    casez (\initial )
      /* src = "libresoc.v:129435.9-129435.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _08_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _08_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _08_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _08_ = X_BF;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _08_ = XL_BT[4:2];
        end
      default:
          _08_ = 3'h0;
    endcase
  end
  always @* begin
      cr_bitfield <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:129462.5-129462.29" *)
    casez (\initial )
      /* src = "libresoc.v:129462.9-129462.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _12_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _12_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _12_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _12_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _12_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _12_ = insn_in[20];
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      move_one <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _13_;
    (* src = "libresoc.v:129493.5-129493.29" *)
    casez (\initial )
      /* src = "libresoc.v:129493.9-129493.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _13_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _13_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _13_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _13_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _13_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _13_ = _16_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _16_ = _18_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *)
                casez (move_one)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _18_ = FXM;
                    end
                  default:
                      _18_ = 8'h00;
                endcase
              end
            default:
                _16_ = 8'h00;
          endcase
        end
      default:
          _13_ = 8'h00;
    endcase
  end
  always @* begin
      ppick_i <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _10_;
    (* src = "libresoc.v:129534.5-129534.29" *)
    casez (\initial )
      /* src = "libresoc.v:129534.9-129534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _10_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _10_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _10_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _10_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _10_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _10_ = _15_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:661" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _15_ = _17_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:662" *)
                casez (move_one)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _17_ = _19_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665" *)
                      casez (ppick_en_o)
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _19_ = ppick_o;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _19_ = 8'h01;
                          end
                      endcase
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _17_ = FXM;
                    end
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _15_ = 8'hff;
              end
          endcase
        end
      default:
          _10_ = 8'h00;
    endcase
  end
  always @* begin
      cr_fxm <= _02_;
  end
  assign \$1  = _20_;
  assign \$3  = _21_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_o" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:129592.1-130109.10" *)
module dec_o(SPR, sel_in, reg_o, reg_o_ok, spr_o, spr_o_ok, fast_o, fast_o_ok, RT, RA, BO, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg _01_;
  (* src = "libresoc.v:129593.7-129593.20" *)
  reg _02_;
  (* src = "libresoc.v:129964.3-129978.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:129979.3-129993.6" *)
  reg _04_;
  (* src = "libresoc.v:129994.3-130012.6" *)
  reg [9:0] _05_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg [9:0] _06_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg _07_;
  (* src = "libresoc.v:130013.3-130036.6" *)
  reg [9:0] _08_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg _10_;
  (* src = "libresoc.v:129964.3-129978.6" *)
  reg [4:0] _11_;
  (* src = "libresoc.v:129979.3-129993.6" *)
  reg _12_;
  (* src = "libresoc.v:129994.3-130012.6" *)
  reg [9:0] _13_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg [9:0] _14_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg _15_;
  (* src = "libresoc.v:130013.3-130036.6" *)
  reg [9:0] _16_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg [2:0] _17_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg _18_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg [9:0] _19_;
  (* src = "libresoc.v:130037.3-130061.6" *)
  reg _20_;
  (* src = "libresoc.v:130013.3-130036.6" *)
  reg [9:0] _21_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg [2:0] _22_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg _23_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg [2:0] _24_;
  (* src = "libresoc.v:130062.3-130108.6" *)
  reg _25_;
  (* src = "libresoc.v:129953.17-129953.117" *)
  wire _26_;
  (* src = "libresoc.v:129954.17-129954.117" *)
  wire _27_;
  (* src = "libresoc.v:129955.17-129955.117" *)
  wire _28_;
  (* src = "libresoc.v:129956.17-129956.104" *)
  wire _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] BO;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RT;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [9:0] SPR;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_o;
  reg [2:0] fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_o_ok;
  reg fast_o_ok;
  (* src = "libresoc.v:129593.7-129593.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [4:0] reg_o;
  reg [4:0] reg_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg_o_ok;
  reg reg_o_ok;
  (* enum_base_type = "OutSel" *)
  (* enum_value_000 = "NONE" *)
  (* enum_value_001 = "RT" *)
  (* enum_value_010 = "RA" *)
  (* enum_value_011 = "SPR" *)
  (* enum_value_100 = "RT_OR_ZERO" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351" *)
  input [2:0] sel_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" *)
  reg [9:0] spr;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spr_o;
  reg [9:0] spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr_o_ok;
  reg spr_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] sprmap_fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire sprmap_fast_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *)
  reg [9:0] sprmap_spr_i;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] sprmap_spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire sprmap_spr_o_ok;
  assign _26_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31;
  assign _27_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31;
  assign _28_ = internal_op == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *) 7'h31;
  assign _29_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *) BO[2];
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:129957.16-129963.4" *)
  \sprmap$174  sprmap (
    .fast_o(sprmap_fast_o),
    .fast_o_ok(sprmap_fast_o_ok),
    .spr_i(sprmap_spr_i),
    .spr_o(sprmap_spr_o),
    .spr_o_ok(sprmap_spr_o_ok)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _11_;
    (* src = "libresoc.v:129965.5-129965.29" *)
    casez (\initial )
      /* src = "libresoc.v:129965.9-129965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _11_ = RT;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _11_ = RA;
        end
      default:
          _11_ = 5'h00;
    endcase
  end
  always @* begin
      reg_o <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _12_;
    (* src = "libresoc.v:129980.5-129980.29" *)
    casez (\initial )
      /* src = "libresoc.v:129980.9-129980.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _12_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      reg_o_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _13_;
    (* src = "libresoc.v:129995.5-129995.29" *)
    casez (\initial )
      /* src = "libresoc.v:129995.9-129995.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _13_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _13_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _13_ = { SPR[4:0], SPR[9:5] };
        end
      default:
          _13_ = 10'h000;
    endcase
  end
  always @* begin
      spr <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _16_;
    (* src = "libresoc.v:130014.5-130014.29" *)
    casez (\initial )
      /* src = "libresoc.v:130014.9-130014.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _16_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _16_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _16_ = _21_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _21_ = spr;
              end
            default:
                _21_ = 10'h000;
          endcase
        end
      default:
          _16_ = 10'h000;
    endcase
  end
  always @* begin
      sprmap_spr_i <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _14_;
    _07_ = _15_;
    (* src = "libresoc.v:130038.5-130038.29" *)
    casez (\initial )
      /* src = "libresoc.v:130038.9-130038.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _14_ = _19_;
          _15_ = _20_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _20_, _19_ } = { sprmap_spr_o_ok, sprmap_spr_o };
              end
            default:
              begin
                _19_ = 10'h000;
                _20_ = 1'h0;
              end
          endcase
        end
      default:
        begin
          _14_ = 10'h000;
          _15_ = 1'h0;
        end
    endcase
  end
  always @* begin
      spr_o <= _06_;
      spr_o_ok <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _22_;
    _01_ = _23_;
    (* src = "libresoc.v:130063.5-130063.29" *)
    casez (\initial )
      /* src = "libresoc.v:130063.9-130063.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _09_ = 3'h0;
          _10_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _09_ = 3'h0;
          _10_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _09_ = _17_;
          _10_ = _18_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:376" *)
          casez (\$5 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _18_, _17_ } = { sprmap_fast_o_ok, sprmap_fast_o };
              end
            default:
              begin
                _17_ = 3'h0;
                _18_ = 1'h0;
              end
          endcase
        end
      default:
        begin
          _09_ = 3'h0;
          _10_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:382" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07, 7'h08:
        begin
          _22_ = _24_;
          _23_ = _25_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:386" *)
          casez (\$7 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = 3'h0;
                _25_ = 1'h1;
              end
            default:
              begin
                _24_ = _09_;
                _25_ = _10_;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          _22_ = 3'h3;
          _23_ = 1'h1;
        end
      default:
        begin
          _22_ = _09_;
          _23_ = _10_;
        end
    endcase
  end
  always @* begin
      fast_o <= _00_;
      fast_o_ok <= _01_;
  end
  assign \$1  = _26_;
  assign \$3  = _27_;
  assign \$5  = _28_;
  assign \$7  = _29_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_o2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130113.1-130281.10" *)
module dec_o2(lk, reg_o2, reg_o2_ok, fast_o2, fast_o2_ok, upd, RA, internal_op);
  reg \initial  = 0;
  (* src = "libresoc.v:130241.3-130260.6" *)
  reg [2:0] _00_;
  (* src = "libresoc.v:130261.3-130280.6" *)
  reg _01_;
  (* src = "libresoc.v:130114.7-130114.20" *)
  reg _02_;
  (* src = "libresoc.v:130221.3-130230.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:130231.3-130240.6" *)
  reg _04_;
  (* src = "libresoc.v:130241.3-130260.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:130261.3-130280.6" *)
  reg _06_;
  (* src = "libresoc.v:130221.3-130230.6" *)
  reg [4:0] _07_;
  (* src = "libresoc.v:130231.3-130240.6" *)
  reg _08_;
  (* src = "libresoc.v:130241.3-130260.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:130261.3-130280.6" *)
  reg _10_;
  (* src = "libresoc.v:130219.17-130219.108" *)
  wire _11_;
  (* src = "libresoc.v:130220.17-130220.108" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input [4:0] RA;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_o2;
  reg [2:0] fast_o2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_o2_ok;
  reg fast_o2_ok;
  (* src = "libresoc.v:130114.7-130114.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:416" *)
  input lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [4:0] reg_o2;
  reg [4:0] reg_o2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output reg_o2_ok;
  reg reg_o2_ok;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [1:0] upd;
  assign _11_ = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1;
  assign _12_ = upd == (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *) 2'h1;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _07_;
    (* src = "libresoc.v:130222.5-130222.29" *)
    casez (\initial )
      /* src = "libresoc.v:130222.9-130222.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _07_ = RA;
        end
      default:
          _07_ = 5'h00;
    endcase
  end
  always @* begin
      reg_o2 <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _08_;
    (* src = "libresoc.v:130232.5-130232.29" *)
    casez (\initial )
      /* src = "libresoc.v:130232.9-130232.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432" *)
    casez (\$3 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _08_ = 1'h1;
        end
      default:
          _08_ = 1'h0;
    endcase
  end
  always @* begin
      reg_o2_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _05_;
    (* src = "libresoc.v:130242.5-130242.29" *)
    casez (\initial )
      /* src = "libresoc.v:130242.9-130242.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07, 7'h06, 7'h08:
        begin
          _05_ = _09_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *)
          casez (lk)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _09_ = 3'h1;
              end
            default:
                _09_ = 3'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          _05_ = 3'h4;
        end
      default:
          _05_ = 3'h0;
    endcase
  end
  always @* begin
      fast_o2 <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _06_;
    (* src = "libresoc.v:130262.5-130262.29" *)
    casez (\initial )
      /* src = "libresoc.v:130262.9-130262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:438" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h07, 7'h06, 7'h08:
        begin
          _06_ = _10_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" *)
          casez (lk)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _10_ = 1'h1;
              end
            default:
                _10_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          _06_ = 1'h1;
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      fast_o2_ok <= _01_;
  end
  assign \$1  = _11_;
  assign \$3  = _12_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130285.1-130420.10" *)
module dec_oe(ALU_internal_op, oe, oe_ok, ALU_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130286.7-130286.20" *)
  reg _0_;
  (* src = "libresoc.v:130378.3-130398.6" *)
  reg _1_;
  (* src = "libresoc.v:130399.3-130419.6" *)
  reg _2_;
  (* src = "libresoc.v:130378.3-130398.6" *)
  reg _3_;
  (* src = "libresoc.v:130399.3-130419.6" *)
  reg _4_;
  (* src = "libresoc.v:130378.3-130398.6" *)
  reg _5_;
  (* src = "libresoc.v:130399.3-130419.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input ALU_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] ALU_internal_op;
  (* src = "libresoc.v:130286.7-130286.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:130379.5-130379.29" *)
    casez (\initial )
      /* src = "libresoc.v:130379.9-130379.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (ALU_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = ALU_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:130400.5-130400.29" *)
    casez (\initial )
      /* src = "libresoc.v:130400.9-130400.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (ALU_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130424.1-130557.10" *)
module \dec_oe$140 (CR_internal_op, CR_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130425.7-130425.20" *)
  reg _0_;
  (* src = "libresoc.v:130515.3-130535.6" *)
  reg _1_;
  (* src = "libresoc.v:130536.3-130556.6" *)
  reg _2_;
  (* src = "libresoc.v:130515.3-130535.6" *)
  reg _3_;
  (* src = "libresoc.v:130536.3-130556.6" *)
  reg _4_;
  (* src = "libresoc.v:130515.3-130535.6" *)
  reg _5_;
  (* src = "libresoc.v:130536.3-130556.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input CR_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] CR_internal_op;
  (* src = "libresoc.v:130425.7-130425.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:130516.5-130516.29" *)
    casez (\initial )
      /* src = "libresoc.v:130516.9-130516.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (CR_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = CR_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:130537.5-130537.29" *)
    casez (\initial )
      /* src = "libresoc.v:130537.9-130537.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (CR_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130561.1-130694.10" *)
module \dec_oe$143 (BRANCH_internal_op, BRANCH_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130562.7-130562.20" *)
  reg _0_;
  (* src = "libresoc.v:130652.3-130672.6" *)
  reg _1_;
  (* src = "libresoc.v:130673.3-130693.6" *)
  reg _2_;
  (* src = "libresoc.v:130652.3-130672.6" *)
  reg _3_;
  (* src = "libresoc.v:130673.3-130693.6" *)
  reg _4_;
  (* src = "libresoc.v:130652.3-130672.6" *)
  reg _5_;
  (* src = "libresoc.v:130673.3-130693.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input BRANCH_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] BRANCH_internal_op;
  (* src = "libresoc.v:130562.7-130562.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:130653.5-130653.29" *)
    casez (\initial )
      /* src = "libresoc.v:130653.9-130653.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (BRANCH_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = BRANCH_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:130674.5-130674.29" *)
    casez (\initial )
      /* src = "libresoc.v:130674.9-130674.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (BRANCH_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130698.1-130833.10" *)
module \dec_oe$147 (LOGICAL_internal_op, oe, oe_ok, LOGICAL_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130699.7-130699.20" *)
  reg _0_;
  (* src = "libresoc.v:130791.3-130811.6" *)
  reg _1_;
  (* src = "libresoc.v:130812.3-130832.6" *)
  reg _2_;
  (* src = "libresoc.v:130791.3-130811.6" *)
  reg _3_;
  (* src = "libresoc.v:130812.3-130832.6" *)
  reg _4_;
  (* src = "libresoc.v:130791.3-130811.6" *)
  reg _5_;
  (* src = "libresoc.v:130812.3-130832.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input LOGICAL_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] LOGICAL_internal_op;
  (* src = "libresoc.v:130699.7-130699.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:130792.5-130792.29" *)
    casez (\initial )
      /* src = "libresoc.v:130792.9-130792.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (LOGICAL_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = LOGICAL_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:130813.5-130813.29" *)
    casez (\initial )
      /* src = "libresoc.v:130813.9-130813.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (LOGICAL_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130837.1-130970.10" *)
module \dec_oe$152 (SPR_internal_op, SPR_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130838.7-130838.20" *)
  reg _0_;
  (* src = "libresoc.v:130928.3-130948.6" *)
  reg _1_;
  (* src = "libresoc.v:130949.3-130969.6" *)
  reg _2_;
  (* src = "libresoc.v:130928.3-130948.6" *)
  reg _3_;
  (* src = "libresoc.v:130949.3-130969.6" *)
  reg _4_;
  (* src = "libresoc.v:130928.3-130948.6" *)
  reg _5_;
  (* src = "libresoc.v:130949.3-130969.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input SPR_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] SPR_internal_op;
  (* src = "libresoc.v:130838.7-130838.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:130929.5-130929.29" *)
    casez (\initial )
      /* src = "libresoc.v:130929.9-130929.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (SPR_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = SPR_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:130950.5-130950.29" *)
    casez (\initial )
      /* src = "libresoc.v:130950.9-130950.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (SPR_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:130974.1-131109.10" *)
module \dec_oe$155 (DIV_internal_op, oe, oe_ok, DIV_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:130975.7-130975.20" *)
  reg _0_;
  (* src = "libresoc.v:131067.3-131087.6" *)
  reg _1_;
  (* src = "libresoc.v:131088.3-131108.6" *)
  reg _2_;
  (* src = "libresoc.v:131067.3-131087.6" *)
  reg _3_;
  (* src = "libresoc.v:131088.3-131108.6" *)
  reg _4_;
  (* src = "libresoc.v:131067.3-131087.6" *)
  reg _5_;
  (* src = "libresoc.v:131088.3-131108.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input DIV_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] DIV_internal_op;
  (* src = "libresoc.v:130975.7-130975.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131068.5-131068.29" *)
    casez (\initial )
      /* src = "libresoc.v:131068.9-131068.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (DIV_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = DIV_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131089.5-131089.29" *)
    casez (\initial )
      /* src = "libresoc.v:131089.9-131089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (DIV_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131113.1-131248.10" *)
module \dec_oe$160 (MUL_internal_op, oe, oe_ok, MUL_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131114.7-131114.20" *)
  reg _0_;
  (* src = "libresoc.v:131206.3-131226.6" *)
  reg _1_;
  (* src = "libresoc.v:131227.3-131247.6" *)
  reg _2_;
  (* src = "libresoc.v:131206.3-131226.6" *)
  reg _3_;
  (* src = "libresoc.v:131227.3-131247.6" *)
  reg _4_;
  (* src = "libresoc.v:131206.3-131226.6" *)
  reg _5_;
  (* src = "libresoc.v:131227.3-131247.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input MUL_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] MUL_internal_op;
  (* src = "libresoc.v:131114.7-131114.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131207.5-131207.29" *)
    casez (\initial )
      /* src = "libresoc.v:131207.9-131207.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (MUL_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = MUL_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131228.5-131228.29" *)
    casez (\initial )
      /* src = "libresoc.v:131228.9-131228.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (MUL_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131252.1-131387.10" *)
module \dec_oe$164 (SHIFT_ROT_internal_op, oe, oe_ok, SHIFT_ROT_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131253.7-131253.20" *)
  reg _0_;
  (* src = "libresoc.v:131345.3-131365.6" *)
  reg _1_;
  (* src = "libresoc.v:131366.3-131386.6" *)
  reg _2_;
  (* src = "libresoc.v:131345.3-131365.6" *)
  reg _3_;
  (* src = "libresoc.v:131366.3-131386.6" *)
  reg _4_;
  (* src = "libresoc.v:131345.3-131365.6" *)
  reg _5_;
  (* src = "libresoc.v:131366.3-131386.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input SHIFT_ROT_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] SHIFT_ROT_internal_op;
  (* src = "libresoc.v:131253.7-131253.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131346.5-131346.29" *)
    casez (\initial )
      /* src = "libresoc.v:131346.9-131346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (SHIFT_ROT_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = SHIFT_ROT_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131367.5-131367.29" *)
    casez (\initial )
      /* src = "libresoc.v:131367.9-131367.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (SHIFT_ROT_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131391.1-131526.10" *)
module \dec_oe$168 (LDST_internal_op, oe, oe_ok, LDST_OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131392.7-131392.20" *)
  reg _0_;
  (* src = "libresoc.v:131484.3-131504.6" *)
  reg _1_;
  (* src = "libresoc.v:131505.3-131525.6" *)
  reg _2_;
  (* src = "libresoc.v:131484.3-131504.6" *)
  reg _3_;
  (* src = "libresoc.v:131505.3-131525.6" *)
  reg _4_;
  (* src = "libresoc.v:131484.3-131504.6" *)
  reg _5_;
  (* src = "libresoc.v:131505.3-131525.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input LDST_OE;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] LDST_internal_op;
  (* src = "libresoc.v:131392.7-131392.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131485.5-131485.29" *)
    casez (\initial )
      /* src = "libresoc.v:131485.9-131485.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (LDST_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = LDST_OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131506.5-131506.29" *)
    casez (\initial )
      /* src = "libresoc.v:131506.9-131506.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (LDST_internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_oe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131530.1-131665.10" *)
module \dec_oe$173 (internal_op, oe, oe_ok, OE, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131531.7-131531.20" *)
  reg _0_;
  (* src = "libresoc.v:131623.3-131643.6" *)
  reg _1_;
  (* src = "libresoc.v:131644.3-131664.6" *)
  reg _2_;
  (* src = "libresoc.v:131623.3-131643.6" *)
  reg _3_;
  (* src = "libresoc.v:131644.3-131664.6" *)
  reg _4_;
  (* src = "libresoc.v:131623.3-131643.6" *)
  reg _5_;
  (* src = "libresoc.v:131644.3-131664.6" *)
  reg _6_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input OE;
  (* src = "libresoc.v:131531.7-131531.15" *)
  reg \initial ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" *)
  input [6:0] internal_op;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe;
  reg oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output oe_ok;
  reg oe_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131624.5-131624.29" *)
    casez (\initial )
      /* src = "libresoc.v:131624.9-131624.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _3_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = _5_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _5_ = OE;
              end
            default:
                _5_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131645.5-131645.29" *)
    casez (\initial )
      /* src = "libresoc.v:131645.9-131645.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" *)
    casez (internal_op)
      /* src = "libresoc.v:0.0-0.0" */
      7'h33, 7'h34, 7'h1f, 7'h0e, 7'h3c, 7'h3d, 7'h38, 7'h25, 7'h26, 7'h39, 7'h3a, 7'h20:
          _4_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = _6_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:525" *)
          casez (sel_in)
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _6_ = 1'h1;
              end
            default:
                _6_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      oe_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_ALU.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131669.1-131723.10" *)
module dec_rc(rc, rc_ok, ALU_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131670.7-131670.20" *)
  reg _0_;
  (* src = "libresoc.v:131685.3-131703.6" *)
  reg _1_;
  (* src = "libresoc.v:131704.3-131722.6" *)
  reg _2_;
  (* src = "libresoc.v:131685.3-131703.6" *)
  reg _3_;
  (* src = "libresoc.v:131704.3-131722.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input ALU_Rc;
  (* src = "libresoc.v:131670.7-131670.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131686.5-131686.29" *)
    casez (\initial )
      /* src = "libresoc.v:131686.9-131686.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = ALU_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131705.5-131705.29" *)
    casez (\initial )
      /* src = "libresoc.v:131705.9-131705.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_CR.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131727.1-131779.10" *)
module \dec_rc$139 (CR_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131728.7-131728.20" *)
  reg _0_;
  (* src = "libresoc.v:131741.3-131759.6" *)
  reg _1_;
  (* src = "libresoc.v:131760.3-131778.6" *)
  reg _2_;
  (* src = "libresoc.v:131741.3-131759.6" *)
  reg _3_;
  (* src = "libresoc.v:131760.3-131778.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input CR_Rc;
  (* src = "libresoc.v:131728.7-131728.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131742.5-131742.29" *)
    casez (\initial )
      /* src = "libresoc.v:131742.9-131742.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = CR_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131761.5-131761.29" *)
    casez (\initial )
      /* src = "libresoc.v:131761.9-131761.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_BRANCH.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131783.1-131835.10" *)
module \dec_rc$142 (BRANCH_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131784.7-131784.20" *)
  reg _0_;
  (* src = "libresoc.v:131797.3-131815.6" *)
  reg _1_;
  (* src = "libresoc.v:131816.3-131834.6" *)
  reg _2_;
  (* src = "libresoc.v:131797.3-131815.6" *)
  reg _3_;
  (* src = "libresoc.v:131816.3-131834.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input BRANCH_Rc;
  (* src = "libresoc.v:131784.7-131784.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131798.5-131798.29" *)
    casez (\initial )
      /* src = "libresoc.v:131798.9-131798.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = BRANCH_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131817.5-131817.29" *)
    casez (\initial )
      /* src = "libresoc.v:131817.9-131817.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LOGICAL.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131839.1-131893.10" *)
module \dec_rc$146 (rc, rc_ok, LOGICAL_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131840.7-131840.20" *)
  reg _0_;
  (* src = "libresoc.v:131855.3-131873.6" *)
  reg _1_;
  (* src = "libresoc.v:131874.3-131892.6" *)
  reg _2_;
  (* src = "libresoc.v:131855.3-131873.6" *)
  reg _3_;
  (* src = "libresoc.v:131874.3-131892.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input LOGICAL_Rc;
  (* src = "libresoc.v:131840.7-131840.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131856.5-131856.29" *)
    casez (\initial )
      /* src = "libresoc.v:131856.9-131856.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = LOGICAL_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131875.5-131875.29" *)
    casez (\initial )
      /* src = "libresoc.v:131875.9-131875.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SPR.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131897.1-131949.10" *)
module \dec_rc$151 (SPR_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131898.7-131898.20" *)
  reg _0_;
  (* src = "libresoc.v:131911.3-131929.6" *)
  reg _1_;
  (* src = "libresoc.v:131930.3-131948.6" *)
  reg _2_;
  (* src = "libresoc.v:131911.3-131929.6" *)
  reg _3_;
  (* src = "libresoc.v:131930.3-131948.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input SPR_Rc;
  (* src = "libresoc.v:131898.7-131898.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131912.5-131912.29" *)
    casez (\initial )
      /* src = "libresoc.v:131912.9-131912.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = SPR_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131931.5-131931.29" *)
    casez (\initial )
      /* src = "libresoc.v:131931.9-131931.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_DIV.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:131953.1-132007.10" *)
module \dec_rc$154 (rc, rc_ok, DIV_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:131954.7-131954.20" *)
  reg _0_;
  (* src = "libresoc.v:131969.3-131987.6" *)
  reg _1_;
  (* src = "libresoc.v:131988.3-132006.6" *)
  reg _2_;
  (* src = "libresoc.v:131969.3-131987.6" *)
  reg _3_;
  (* src = "libresoc.v:131988.3-132006.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input DIV_Rc;
  (* src = "libresoc.v:131954.7-131954.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:131970.5-131970.29" *)
    casez (\initial )
      /* src = "libresoc.v:131970.9-131970.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = DIV_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:131989.5-131989.29" *)
    casez (\initial )
      /* src = "libresoc.v:131989.9-131989.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_MUL.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:132011.1-132065.10" *)
module \dec_rc$159 (rc, rc_ok, MUL_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:132012.7-132012.20" *)
  reg _0_;
  (* src = "libresoc.v:132027.3-132045.6" *)
  reg _1_;
  (* src = "libresoc.v:132046.3-132064.6" *)
  reg _2_;
  (* src = "libresoc.v:132027.3-132045.6" *)
  reg _3_;
  (* src = "libresoc.v:132046.3-132064.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input MUL_Rc;
  (* src = "libresoc.v:132012.7-132012.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:132028.5-132028.29" *)
    casez (\initial )
      /* src = "libresoc.v:132028.9-132028.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = MUL_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:132047.5-132047.29" *)
    casez (\initial )
      /* src = "libresoc.v:132047.9-132047.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:132069.1-132123.10" *)
module \dec_rc$163 (rc, rc_ok, SHIFT_ROT_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:132070.7-132070.20" *)
  reg _0_;
  (* src = "libresoc.v:132085.3-132103.6" *)
  reg _1_;
  (* src = "libresoc.v:132104.3-132122.6" *)
  reg _2_;
  (* src = "libresoc.v:132085.3-132103.6" *)
  reg _3_;
  (* src = "libresoc.v:132104.3-132122.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input SHIFT_ROT_Rc;
  (* src = "libresoc.v:132070.7-132070.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:132086.5-132086.29" *)
    casez (\initial )
      /* src = "libresoc.v:132086.9-132086.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = SHIFT_ROT_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:132105.5-132105.29" *)
    casez (\initial )
      /* src = "libresoc.v:132105.9-132105.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.dec_LDST.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:132127.1-132181.10" *)
module \dec_rc$167 (rc, rc_ok, LDST_Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:132128.7-132128.20" *)
  reg _0_;
  (* src = "libresoc.v:132143.3-132161.6" *)
  reg _1_;
  (* src = "libresoc.v:132162.3-132180.6" *)
  reg _2_;
  (* src = "libresoc.v:132143.3-132161.6" *)
  reg _3_;
  (* src = "libresoc.v:132162.3-132180.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input LDST_Rc;
  (* src = "libresoc.v:132128.7-132128.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:132144.5-132144.29" *)
    casez (\initial )
      /* src = "libresoc.v:132144.9-132144.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = LDST_Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:132163.5-132163.29" *)
    casez (\initial )
      /* src = "libresoc.v:132163.9-132163.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_rc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:132185.1-132239.10" *)
module \dec_rc$172 (rc, rc_ok, Rc, sel_in);
  reg \initial  = 0;
  (* src = "libresoc.v:132186.7-132186.20" *)
  reg _0_;
  (* src = "libresoc.v:132201.3-132219.6" *)
  reg _1_;
  (* src = "libresoc.v:132220.3-132238.6" *)
  reg _2_;
  (* src = "libresoc.v:132201.3-132219.6" *)
  reg _3_;
  (* src = "libresoc.v:132220.3-132238.6" *)
  reg _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" *)
  input Rc;
  (* src = "libresoc.v:132186.7-132186.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc;
  reg rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output rc_ok;
  reg rc_ok;
  (* enum_base_type = "RC" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "RC" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462" *)
  input [1:0] sel_in;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:132202.5-132202.29" *)
    casez (\initial )
      /* src = "libresoc.v:132202.9-132202.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _3_ = Rc;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _3_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _3_ = 1'h0;
        end
      default:
          _3_ = 1'h0;
    endcase
  end
  always @* begin
      rc <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:132221.5-132221.29" *)
    casez (\initial )
      /* src = "libresoc.v:132221.9-132221.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471" *)
    casez (sel_in)
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 1'h1;
        end
      default:
          _4_ = 1'h0;
    endcase
  end
  always @* begin
      rc_ok <= _2_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:132243.1-133487.10" *)
module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:133044.3-133045.25" *)
  reg _000_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:133016.3-133017.75" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [13:0] _003_;
  (* src = "libresoc.v:132986.3-132987.73" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:132988.3-132989.87" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _007_;
  (* src = "libresoc.v:132990.3-132991.83" *)
  reg _008_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:133004.3-133005.81" *)
  reg [1:0] _010_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [31:0] _011_;
  (* src = "libresoc.v:133018.3-133019.67" *)
  reg [31:0] _012_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [6:0] _013_;
  (* src = "libresoc.v:132984.3-132985.77" *)
  reg [6:0] _014_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _015_;
  (* src = "libresoc.v:133000.3-133001.77" *)
  reg _016_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _017_;
  (* src = "libresoc.v:133006.3-133007.79" *)
  reg _018_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _019_;
  (* src = "libresoc.v:133012.3-133013.75" *)
  reg _020_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _021_;
  (* src = "libresoc.v:133014.3-133015.77" *)
  reg _022_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _023_;
  (* src = "libresoc.v:132996.3-132997.71" *)
  reg _024_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _025_;
  (* src = "libresoc.v:132998.3-132999.71" *)
  reg _026_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _027_;
  (* src = "libresoc.v:133010.3-133011.83" *)
  reg _028_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _029_;
  (* src = "libresoc.v:132994.3-132995.71" *)
  reg _030_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _031_;
  (* src = "libresoc.v:132992.3-132993.71" *)
  reg _032_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _033_;
  (* src = "libresoc.v:133008.3-133009.77" *)
  reg _034_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _035_;
  (* src = "libresoc.v:133002.3-133003.71" *)
  reg _036_;
  (* src = "libresoc.v:133042.3-133043.40" *)
  reg _037_;
  (* src = "libresoc.v:133397.3-133405.6" *)
  reg _038_;
  (* src = "libresoc.v:132958.3-132959.39" *)
  reg _039_;
  (* src = "libresoc.v:133388.3-133396.6" *)
  reg _040_;
  (* src = "libresoc.v:132960.3-132961.43" *)
  reg _041_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg [63:0] _042_;
  (* src = "libresoc.v:132980.3-132981.37" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg _044_;
  (* src = "libresoc.v:132982.3-132983.43" *)
  reg _045_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg [3:0] _046_;
  (* src = "libresoc.v:132976.3-132977.43" *)
  reg [3:0] _047_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg _048_;
  (* src = "libresoc.v:132978.3-132979.49" *)
  reg _049_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg [1:0] _050_;
  (* src = "libresoc.v:132972.3-132973.47" *)
  reg [1:0] _051_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg _052_;
  (* src = "libresoc.v:132974.3-132975.53" *)
  reg _053_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _054_;
  (* src = "libresoc.v:132968.3-132969.47" *)
  reg _055_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _056_;
  (* src = "libresoc.v:132970.3-132971.53" *)
  reg _057_;
  (* src = "libresoc.v:133406.3-133415.6" *)
  reg [63:0] _058_;
  (* src = "libresoc.v:133416.3-133425.6" *)
  reg [3:0] _059_;
  (* src = "libresoc.v:133426.3-133435.6" *)
  reg [1:0] _060_;
  (* src = "libresoc.v:133436.3-133445.6" *)
  reg _061_;
  (* src = "libresoc.v:132244.7-132244.20" *)
  reg _062_;
  (* src = "libresoc.v:133186.3-133194.6" *)
  reg _063_;
  (* src = "libresoc.v:133028.3-133029.39" *)
  reg _064_;
  (* src = "libresoc.v:133177.3-133185.6" *)
  reg _065_;
  (* src = "libresoc.v:133030.3-133031.39" *)
  reg _066_;
  (* src = "libresoc.v:133446.3-133454.6" *)
  reg [3:0] _067_;
  (* src = "libresoc.v:133040.3-133041.37" *)
  reg [3:0] _068_;
  (* src = "libresoc.v:133131.3-133140.6" *)
  reg _069_;
  (* src = "libresoc.v:133222.3-133230.6" *)
  reg [3:0] _070_;
  (* src = "libresoc.v:133020.3-133021.39" *)
  reg [3:0] _071_;
  (* src = "libresoc.v:133213.3-133221.6" *)
  reg [3:0] _072_;
  (* src = "libresoc.v:133022.3-133023.39" *)
  reg [3:0] _073_;
  (* src = "libresoc.v:133150.3-133158.6" *)
  reg _074_;
  (* src = "libresoc.v:133036.3-133037.41" *)
  reg _075_;
  (* src = "libresoc.v:133141.3-133149.6" *)
  reg _076_;
  (* src = "libresoc.v:133038.3-133039.41" *)
  reg _077_;
  (* src = "libresoc.v:133168.3-133176.6" *)
  reg _078_;
  (* src = "libresoc.v:133032.3-133033.39" *)
  reg _079_;
  (* src = "libresoc.v:133159.3-133167.6" *)
  reg _080_;
  (* src = "libresoc.v:133034.3-133035.39" *)
  reg _081_;
  (* src = "libresoc.v:133204.3-133212.6" *)
  reg [2:0] _082_;
  (* src = "libresoc.v:133024.3-133025.39" *)
  reg [2:0] _083_;
  (* src = "libresoc.v:133195.3-133203.6" *)
  reg [2:0] _084_;
  (* src = "libresoc.v:133026.3-133027.39" *)
  reg [2:0] _085_;
  (* src = "libresoc.v:133358.3-133367.6" *)
  reg [63:0] _086_;
  (* src = "libresoc.v:132966.3-132967.29" *)
  reg [63:0] _087_;
  (* src = "libresoc.v:133368.3-133377.6" *)
  reg [63:0] _088_;
  (* src = "libresoc.v:132964.3-132965.29" *)
  reg [63:0] _089_;
  (* src = "libresoc.v:133378.3-133387.6" *)
  reg _090_;
  (* src = "libresoc.v:132962.3-132963.29" *)
  reg _091_;
  (* src = "libresoc.v:132374.7-132374.24" *)
  reg _092_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [3:0] _093_;
  (* src = "libresoc.v:132384.13-132384.49" *)
  reg [3:0] _094_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [13:0] _095_;
  (* src = "libresoc.v:132403.14-132403.53" *)
  reg [13:0] _096_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [63:0] _097_;
  (* src = "libresoc.v:132407.14-132407.72" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _099_;
  (* src = "libresoc.v:132411.7-132411.47" *)
  reg _100_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [1:0] _101_;
  (* src = "libresoc.v:132419.13-132419.52" *)
  reg [1:0] _102_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [31:0] _103_;
  (* src = "libresoc.v:132423.14-132423.47" *)
  reg [31:0] _104_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [6:0] _105_;
  (* src = "libresoc.v:132502.13-132502.51" *)
  reg [6:0] _106_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _107_;
  (* src = "libresoc.v:132506.7-132506.44" *)
  reg _108_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _109_;
  (* src = "libresoc.v:132510.7-132510.45" *)
  reg _110_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _111_;
  (* src = "libresoc.v:132514.7-132514.43" *)
  reg _112_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _113_;
  (* src = "libresoc.v:132518.7-132518.44" *)
  reg _114_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _115_;
  (* src = "libresoc.v:132522.7-132522.41" *)
  reg _116_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _117_;
  (* src = "libresoc.v:132526.7-132526.41" *)
  reg _118_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _119_;
  (* src = "libresoc.v:132530.7-132530.47" *)
  reg _120_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _121_;
  (* src = "libresoc.v:132534.7-132534.41" *)
  reg _122_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _123_;
  (* src = "libresoc.v:132538.7-132538.41" *)
  reg _124_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _125_;
  (* src = "libresoc.v:132542.7-132542.44" *)
  reg _126_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _127_;
  (* src = "libresoc.v:132546.7-132546.41" *)
  reg _128_;
  (* src = "libresoc.v:132572.7-132572.26" *)
  reg _129_;
  (* src = "libresoc.v:133397.3-133405.6" *)
  reg _130_;
  (* src = "libresoc.v:132580.7-132580.25" *)
  reg _131_;
  (* src = "libresoc.v:133388.3-133396.6" *)
  reg _132_;
  (* src = "libresoc.v:132592.7-132592.27" *)
  reg _133_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg [63:0] _134_;
  (* src = "libresoc.v:132626.14-132626.47" *)
  reg [63:0] _135_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg _136_;
  (* src = "libresoc.v:132630.7-132630.27" *)
  reg _137_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg [3:0] _138_;
  (* src = "libresoc.v:132634.13-132634.33" *)
  reg [3:0] _139_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg _140_;
  (* src = "libresoc.v:132638.7-132638.30" *)
  reg _141_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg [1:0] _142_;
  (* src = "libresoc.v:132642.13-132642.35" *)
  reg [1:0] _143_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg _144_;
  (* src = "libresoc.v:132646.7-132646.32" *)
  reg _145_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _146_;
  (* src = "libresoc.v:132650.7-132650.29" *)
  reg _147_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _148_;
  (* src = "libresoc.v:132654.7-132654.32" *)
  reg _149_;
  (* src = "libresoc.v:133406.3-133415.6" *)
  reg [63:0] _150_;
  (* src = "libresoc.v:133416.3-133425.6" *)
  reg [3:0] _151_;
  (* src = "libresoc.v:133426.3-133435.6" *)
  reg [1:0] _152_;
  (* src = "libresoc.v:133436.3-133445.6" *)
  reg _153_;
  (* src = "libresoc.v:133186.3-133194.6" *)
  reg _154_;
  (* src = "libresoc.v:132674.7-132674.25" *)
  reg _155_;
  (* src = "libresoc.v:133177.3-133185.6" *)
  reg _156_;
  (* src = "libresoc.v:132678.7-132678.25" *)
  reg _157_;
  (* src = "libresoc.v:133446.3-133454.6" *)
  reg [3:0] _158_;
  (* src = "libresoc.v:132812.13-132812.30" *)
  reg [3:0] _159_;
  (* src = "libresoc.v:133131.3-133140.6" *)
  reg _160_;
  (* src = "libresoc.v:133222.3-133230.6" *)
  reg [3:0] _161_;
  (* src = "libresoc.v:132820.13-132820.31" *)
  reg [3:0] _162_;
  (* src = "libresoc.v:133213.3-133221.6" *)
  reg [3:0] _163_;
  (* src = "libresoc.v:132824.13-132824.31" *)
  reg [3:0] _164_;
  (* src = "libresoc.v:133150.3-133158.6" *)
  reg _165_;
  (* src = "libresoc.v:132836.7-132836.26" *)
  reg _166_;
  (* src = "libresoc.v:133141.3-133149.6" *)
  reg _167_;
  (* src = "libresoc.v:132840.7-132840.26" *)
  reg _168_;
  (* src = "libresoc.v:133168.3-133176.6" *)
  reg _169_;
  (* src = "libresoc.v:132844.7-132844.25" *)
  reg _170_;
  (* src = "libresoc.v:133159.3-133167.6" *)
  reg _171_;
  (* src = "libresoc.v:132848.7-132848.25" *)
  reg _172_;
  (* src = "libresoc.v:133204.3-133212.6" *)
  reg [2:0] _173_;
  (* src = "libresoc.v:132862.13-132862.31" *)
  reg [2:0] _174_;
  (* src = "libresoc.v:133195.3-133203.6" *)
  reg [2:0] _175_;
  (* src = "libresoc.v:132866.13-132866.31" *)
  reg [2:0] _176_;
  (* src = "libresoc.v:133358.3-133367.6" *)
  reg [63:0] _177_;
  (* src = "libresoc.v:132874.14-132874.43" *)
  reg [63:0] _178_;
  (* src = "libresoc.v:133368.3-133377.6" *)
  reg [63:0] _179_;
  (* src = "libresoc.v:132878.14-132878.43" *)
  reg [63:0] _180_;
  (* src = "libresoc.v:133378.3-133387.6" *)
  reg _181_;
  (* src = "libresoc.v:132882.7-132882.20" *)
  reg _182_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg [63:0] _183_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _184_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _185_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _186_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _187_;
  (* src = "libresoc.v:133231.3-133269.6" *)
  reg _188_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg [63:0] _189_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg _190_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg [3:0] _191_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg _192_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg [1:0] _193_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg _194_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _195_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _196_;
  (* src = "libresoc.v:133270.3-133291.6" *)
  reg _197_;
  (* src = "libresoc.v:133292.3-133313.6" *)
  reg _198_;
  (* src = "libresoc.v:133314.3-133335.6" *)
  reg _199_;
  (* src = "libresoc.v:133336.3-133357.6" *)
  reg _200_;
  (* src = "libresoc.v:132897.19-132897.133" *)
  wire [2:0] _201_;
  (* src = "libresoc.v:132899.19-132899.115" *)
  wire [2:0] _202_;
  (* src = "libresoc.v:132900.18-132900.110" *)
  wire _203_;
  (* src = "libresoc.v:132901.19-132901.125" *)
  wire _204_;
  (* src = "libresoc.v:132902.19-132902.125" *)
  wire _205_;
  (* src = "libresoc.v:132903.19-132903.125" *)
  wire _206_;
  (* src = "libresoc.v:132904.19-132904.125" *)
  wire _207_;
  (* src = "libresoc.v:132905.19-132905.149" *)
  wire [3:0] _208_;
  (* src = "libresoc.v:132906.19-132906.121" *)
  wire [3:0] _209_;
  (* src = "libresoc.v:132907.19-132907.127" *)
  wire _210_;
  (* src = "libresoc.v:132908.19-132908.127" *)
  wire _211_;
  (* src = "libresoc.v:132909.19-132909.127" *)
  wire _212_;
  (* src = "libresoc.v:132910.19-132910.127" *)
  wire _213_;
  (* src = "libresoc.v:132912.18-132912.98" *)
  wire _214_;
  (* src = "libresoc.v:132914.18-132914.100" *)
  wire _215_;
  (* src = "libresoc.v:132915.18-132915.160" *)
  wire [3:0] _216_;
  (* src = "libresoc.v:132917.18-132917.119" *)
  wire [3:0] _217_;
  (* src = "libresoc.v:132920.17-132920.123" *)
  wire _218_;
  (* src = "libresoc.v:132921.18-132921.116" *)
  wire _219_;
  (* src = "libresoc.v:132926.18-132926.113" *)
  wire _220_;
  (* src = "libresoc.v:132927.18-132927.125" *)
  wire [3:0] _221_;
  (* src = "libresoc.v:132929.18-132929.112" *)
  wire _222_;
  (* src = "libresoc.v:132931.18-132931.126" *)
  wire _223_;
  (* src = "libresoc.v:132932.18-132932.126" *)
  wire _224_;
  (* src = "libresoc.v:132933.18-132933.117" *)
  wire _225_;
  (* src = "libresoc.v:132939.18-132939.130" *)
  wire _226_;
  (* src = "libresoc.v:132940.18-132940.124" *)
  wire [3:0] _227_;
  (* src = "libresoc.v:132942.18-132942.116" *)
  wire _228_;
  (* src = "libresoc.v:132943.18-132943.119" *)
  wire _229_;
  (* src = "libresoc.v:132944.18-132944.121" *)
  wire _230_;
  (* src = "libresoc.v:132945.18-132945.121" *)
  wire _231_;
  (* src = "libresoc.v:132955.18-132955.134" *)
  wire _232_;
  (* src = "libresoc.v:132956.18-132956.132" *)
  wire _233_;
  (* src = "libresoc.v:132957.18-132957.149" *)
  wire [2:0] _234_;
  (* src = "libresoc.v:132928.18-132928.113" *)
  wire _235_;
  (* src = "libresoc.v:132930.18-132930.119" *)
  wire _236_;
  (* src = "libresoc.v:132895.19-132895.130" *)
  wire _237_;
  (* src = "libresoc.v:132896.19-132896.136" *)
  wire _238_;
  (* src = "libresoc.v:132898.19-132898.115" *)
  wire [2:0] _239_;
  (* src = "libresoc.v:132911.18-132911.97" *)
  wire _240_;
  (* src = "libresoc.v:132913.18-132913.99" *)
  wire _241_;
  (* src = "libresoc.v:132916.18-132916.113" *)
  wire [3:0] _242_;
  (* src = "libresoc.v:132919.18-132919.106" *)
  wire _243_;
  (* src = "libresoc.v:132925.18-132925.120" *)
  wire _244_;
  (* src = "libresoc.v:132936.17-132936.113" *)
  wire [2:0] _245_;
  (* src = "libresoc.v:132924.18-132924.112" *)
  wire _246_;
  (* src = "libresoc.v:132934.18-132934.122" *)
  wire _247_;
  (* src = "libresoc.v:132935.18-132935.124" *)
  wire _248_;
  (* src = "libresoc.v:132937.18-132937.168" *)
  wire [3:0] _249_;
  (* src = "libresoc.v:132938.18-132938.155" *)
  wire [2:0] _250_;
  (* src = "libresoc.v:132941.18-132941.120" *)
  wire [3:0] _251_;
  (* src = "libresoc.v:132947.17-132947.117" *)
  wire [2:0] _252_;
  (* src = "libresoc.v:132952.17-132952.104" *)
  wire _253_;
  (* src = "libresoc.v:132918.18-132918.106" *)
  wire _254_;
  (* src = "libresoc.v:132922.18-132922.113" *)
  wire _255_;
  (* src = "libresoc.v:132923.18-132923.112" *)
  wire _256_;
  (* src = "libresoc.v:132946.18-132946.158" *)
  wire _257_;
  (* src = "libresoc.v:132948.18-132948.159" *)
  wire [63:0] _258_;
  (* src = "libresoc.v:132949.18-132949.164" *)
  wire _259_;
  (* src = "libresoc.v:132950.18-132950.180" *)
  wire [63:0] _260_;
  (* src = "libresoc.v:132951.18-132951.115" *)
  wire [63:0] _261_;
  (* src = "libresoc.v:132953.18-132953.125" *)
  wire [63:0] _262_;
  (* src = "libresoc.v:132954.18-132954.118" *)
  wire _263_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [3:0] \$118 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [3:0] \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$128 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [3:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [3:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [3:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [3:0] \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [3:0] \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [2:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [3:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [3:0] \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$86 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$88 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$90 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_div0_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] alu_div0_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \alu_div0_logical_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_div0_logical_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_div0_logical_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_div0_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_div0_logical_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] alu_div0_logical_op__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_div0_logical_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_div0_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_div0_logical_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_div0_logical_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_div0_logical_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_div0_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_div0_logical_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_div0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_div0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_div0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_div0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_div0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_div0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_div0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_div0_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire alu_div0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \alu_div0_xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [3:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [3:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r1__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r1__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r2__xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r2__xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest2_o;
  reg [3:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest3_o;
  reg [1:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output dest4_o;
  reg dest4_o;
  (* src = "libresoc.v:132244.7-132244.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_div0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_div0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_div0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_div0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_div0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_div0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [3:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [3:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [3:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [2:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [3:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src3_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] \src_or_imm$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire \src_sel$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  assign _201_ = \$98  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$102 , \$100  };
  assign _202_ = \$104  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$106 ;
  assign _203_ = \$2  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ;
  assign _204_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _205_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _206_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _207_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _208_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$110 , \$112 , \$114 , \$116  };
  assign _209_ = \$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _210_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _211_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _212_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _213_ = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _214_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ;
  assign _215_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ;
  assign _216_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _217_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _218_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _219_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ;
  assign _220_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ;
  assign _221_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _222_ = \$40  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ;
  assign _223_ = \$48  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_div0_n_ready_i;
  assign _224_ = \$50  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_div0_n_valid_o;
  assign _225_ = \$52  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _226_ = alu_div0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _227_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _228_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _229_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _230_ = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _231_ = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _232_ = alu_div0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _233_ = alu_div0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _234_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _235_ = \$42  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _236_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _237_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__zero_a;
  assign _238_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_div0_logical_op__imm_data__ok;
  assign _239_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _240_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _241_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _242_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _243_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _244_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_div0_n_ready_i;
  assign _245_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _246_ = \$32  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ;
  assign _247_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _248_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _249_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _250_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _251_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _252_ = \$5  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _253_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ;
  assign _254_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ;
  assign _255_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _256_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _257_ = alu_div0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0];
  assign _258_ = alu_div0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i;
  assign _259_ = alu_div0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _260_ = alu_div0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_div0_logical_op__imm_data__data : src2_i;
  assign _261_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0;
  assign _262_ = \src_sel$82  ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$85  : src_r1;
  assign _263_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133046.12-133082.4" *)
  alu_div0 alu_div0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_div0_cr_a),
    .cr_a_ok(cr_a_ok),
    .logical_op__data_len(alu_div0_logical_op__data_len),
    .logical_op__fn_unit(alu_div0_logical_op__fn_unit),
    .logical_op__imm_data__data(alu_div0_logical_op__imm_data__data),
    .logical_op__imm_data__ok(alu_div0_logical_op__imm_data__ok),
    .logical_op__input_carry(alu_div0_logical_op__input_carry),
    .logical_op__insn(alu_div0_logical_op__insn),
    .logical_op__insn_type(alu_div0_logical_op__insn_type),
    .logical_op__invert_in(alu_div0_logical_op__invert_in),
    .logical_op__invert_out(alu_div0_logical_op__invert_out),
    .logical_op__is_32bit(alu_div0_logical_op__is_32bit),
    .logical_op__is_signed(alu_div0_logical_op__is_signed),
    .logical_op__oe__oe(alu_div0_logical_op__oe__oe),
    .logical_op__oe__ok(alu_div0_logical_op__oe__ok),
    .logical_op__output_carry(alu_div0_logical_op__output_carry),
    .logical_op__rc__ok(alu_div0_logical_op__rc__ok),
    .logical_op__rc__rc(alu_div0_logical_op__rc__rc),
    .logical_op__write_cr0(alu_div0_logical_op__write_cr0),
    .logical_op__zero_a(alu_div0_logical_op__zero_a),
    .n_ready_i(alu_div0_n_ready_i),
    .n_valid_o(alu_div0_n_valid_o),
    .o(alu_div0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_div0_p_ready_o),
    .p_valid_i(alu_div0_p_valid_i),
    .ra(alu_div0_ra),
    .rb(alu_div0_rb),
    .xer_ov(alu_div0_xer_ov),
    .xer_ov_ok(xer_ov_ok),
    .xer_so(alu_div0_xer_so),
    .\xer_so$1 (\alu_div0_xer_so$1 ),
    .xer_so_ok(xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133083.14-133089.4" *)
  \alu_l$90  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133090.15-133096.4" *)
  \alui_l$89  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133097.14-133103.4" *)
  \opc_l$85  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133104.14-133110.4" *)
  \req_l$86  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133111.14-133117.4" *)
  \rok_l$88  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133118.14-133123.4" *)
  \rst_l$87  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:133124.14-133130.4" *)
  \src_l$84  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _062_ = 1'h0;
  end
  always @* begin
      \initial  <= _062_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__data_len <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__fn_unit <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__imm_data__data <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__imm_data__ok <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__input_carry <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__insn <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__insn_type <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__invert_in <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__invert_out <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__is_32bit <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__is_signed <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__oe__oe <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__oe__ok <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__output_carry <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__rc__ok <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__rc__rc <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _126_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__write_cr0 <= _126_;
  end
  always @* begin
    if (\initial ) begin end
    _128_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_div0_logical_op__zero_a <= _128_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _139_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a <= _139_;
  end
  always @* begin
    if (\initial ) begin end
    _141_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a_ok <= _141_;
  end
  always @* begin
    if (\initial ) begin end
    _143_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ov <= _143_;
  end
  always @* begin
    if (\initial ) begin end
    _145_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ov_ok <= _145_;
  end
  always @* begin
    if (\initial ) begin end
    _147_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so <= _147_;
  end
  always @* begin
    if (\initial ) begin end
    _149_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so_ok <= _149_;
  end
  always @* begin
    if (\initial ) begin end
    _155_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _155_;
  end
  always @* begin
    if (\initial ) begin end
    _157_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _157_;
  end
  always @* begin
    if (\initial ) begin end
    _159_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _159_;
  end
  always @* begin
    if (\initial ) begin end
    _162_ = 4'hf;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _162_;
  end
  always @* begin
    if (\initial ) begin end
    _164_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _164_;
  end
  always @* begin
    if (\initial ) begin end
    _166_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _166_;
  end
  always @* begin
    if (\initial ) begin end
    _168_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _168_;
  end
  always @* begin
    if (\initial ) begin end
    _170_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _170_;
  end
  always @* begin
    if (\initial ) begin end
    _172_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _172_;
  end
  always @* begin
    if (\initial ) begin end
    _174_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _174_;
  end
  always @* begin
    if (\initial ) begin end
    _176_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _176_;
  end
  always @* begin
    if (\initial ) begin end
    _178_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _178_;
  end
  always @* begin
    if (\initial ) begin end
    _180_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _180_;
  end
  always @* begin
    if (\initial ) begin end
    _182_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _182_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \data_r3__xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \data_r3__xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so_ok <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \data_r2__xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ov <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \data_r2__xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ov_ok <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \data_r1__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \data_r1__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a_ok <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \alu_div0_logical_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__insn_type <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \alu_div0_logical_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__fn_unit <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \alu_div0_logical_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__imm_data__data <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \alu_div0_logical_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__imm_data__ok <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \alu_div0_logical_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__rc__rc <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \alu_div0_logical_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__rc__ok <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \alu_div0_logical_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__oe__oe <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \alu_div0_logical_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__oe__ok <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \alu_div0_logical_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__invert_in <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \alu_div0_logical_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__zero_a <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \alu_div0_logical_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__input_carry <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \alu_div0_logical_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__invert_out <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \alu_div0_logical_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__write_cr0 <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \alu_div0_logical_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__output_carry <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \alu_div0_logical_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__is_32bit <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \alu_div0_logical_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__is_signed <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \alu_div0_logical_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__data_len <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \alu_div0_logical_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_div0_logical_op__insn <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = alu_div0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$10 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _160_;
    (* src = "libresoc.v:133132.5-133132.29" *)
    casez (\initial )
      /* src = "libresoc.v:133132.9-133132.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$54 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _160_ = 1'h1;
        end
      default:
          _160_ = \$46 ;
    endcase
  end
  always @* begin
      req_done <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = _167_;
    (* src = "libresoc.v:133142.5-133142.29" *)
    casez (\initial )
      /* src = "libresoc.v:133142.9-133142.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _167_ = 1'h0;
        end
      default:
          _167_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = _165_;
    (* src = "libresoc.v:133151.5-133151.29" *)
    casez (\initial )
      /* src = "libresoc.v:133151.9-133151.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _165_ = 1'h1;
        end
      default:
          _165_ = \$64 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = _171_;
    (* src = "libresoc.v:133160.5-133160.29" *)
    casez (\initial )
      /* src = "libresoc.v:133160.9-133160.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 1'h0;
        end
      default:
          _171_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = _169_;
    (* src = "libresoc.v:133169.5-133169.29" *)
    casez (\initial )
      /* src = "libresoc.v:133169.9-133169.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _169_ = 1'h1;
        end
      default:
          _169_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _156_;
    (* src = "libresoc.v:133178.5-133178.29" *)
    casez (\initial )
      /* src = "libresoc.v:133178.9-133178.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _156_ = 1'h0;
        end
      default:
          _156_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = _154_;
    (* src = "libresoc.v:133187.5-133187.29" *)
    casez (\initial )
      /* src = "libresoc.v:133187.9-133187.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _154_ = 1'h1;
        end
      default:
          _154_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = _175_;
    (* src = "libresoc.v:133196.5-133196.29" *)
    casez (\initial )
      /* src = "libresoc.v:133196.9-133196.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 3'h0;
        end
      default:
          _175_ = { cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = _173_;
    (* src = "libresoc.v:133205.5-133205.29" *)
    casez (\initial )
      /* src = "libresoc.v:133205.9-133205.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 3'h7;
        end
      default:
          _173_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _163_;
    (* src = "libresoc.v:133214.5-133214.29" *)
    casez (\initial )
      /* src = "libresoc.v:133214.9-133214.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _163_ = 4'h0;
        end
      default:
          _163_ = \$66 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _161_;
    (* src = "libresoc.v:133223.5-133223.29" *)
    casez (\initial )
      /* src = "libresoc.v:133223.9-133223.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _161_ = 4'hf;
        end
      default:
          _161_ = \$68 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _093_;
    _003_ = _095_;
    _009_ = _101_;
    _011_ = _103_;
    _013_ = _105_;
    _015_ = _107_;
    _017_ = _109_;
    _019_ = _111_;
    _021_ = _113_;
    _027_ = _119_;
    _033_ = _125_;
    _035_ = _127_;
    _005_ = _183_;
    _007_ = _184_;
    _023_ = _185_;
    _025_ = _186_;
    _029_ = _187_;
    _031_ = _188_;
    (* src = "libresoc.v:133232.5-133232.29" *)
    casez (\initial )
      /* src = "libresoc.v:133232.9-133232.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _103_, _093_, _113_, _111_, _119_, _125_, _109_, _101_, _127_, _107_, _117_, _115_, _121_, _123_, _099_, _097_, _095_, _105_ } = { oper_i_alu_div0__insn, oper_i_alu_div0__data_len, oper_i_alu_div0__is_signed, oper_i_alu_div0__is_32bit, oper_i_alu_div0__output_carry, oper_i_alu_div0__write_cr0, oper_i_alu_div0__invert_out, oper_i_alu_div0__input_carry, oper_i_alu_div0__zero_a, oper_i_alu_div0__invert_in, oper_i_alu_div0__oe__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__rc__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__fn_unit, oper_i_alu_div0__insn_type };
        end
      default:
        begin
          _093_ = alu_div0_logical_op__data_len;
          _095_ = alu_div0_logical_op__fn_unit;
          _097_ = alu_div0_logical_op__imm_data__data;
          _099_ = alu_div0_logical_op__imm_data__ok;
          _101_ = alu_div0_logical_op__input_carry;
          _103_ = alu_div0_logical_op__insn;
          _105_ = alu_div0_logical_op__insn_type;
          _107_ = alu_div0_logical_op__invert_in;
          _109_ = alu_div0_logical_op__invert_out;
          _111_ = alu_div0_logical_op__is_32bit;
          _113_ = alu_div0_logical_op__is_signed;
          _115_ = alu_div0_logical_op__oe__oe;
          _117_ = alu_div0_logical_op__oe__ok;
          _119_ = alu_div0_logical_op__output_carry;
          _121_ = alu_div0_logical_op__rc__ok;
          _123_ = alu_div0_logical_op__rc__rc;
          _125_ = alu_div0_logical_op__write_cr0;
          _127_ = alu_div0_logical_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _183_ = 64'h0000000000000000;
          _184_ = 1'h0;
          _188_ = 1'h0;
          _187_ = 1'h0;
          _185_ = 1'h0;
          _186_ = 1'h0;
        end
      default:
        begin
          _183_ = _097_;
          _184_ = _099_;
          _185_ = _115_;
          _186_ = _117_;
          _187_ = _121_;
          _188_ = _123_;
        end
    endcase
  end
  always @* begin
      \alu_div0_logical_op__data_len$next  <= _001_;
      \alu_div0_logical_op__fn_unit$next  <= _003_;
      \alu_div0_logical_op__imm_data__data$next  <= _005_;
      \alu_div0_logical_op__imm_data__ok$next  <= _007_;
      \alu_div0_logical_op__input_carry$next  <= _009_;
      \alu_div0_logical_op__insn$next  <= _011_;
      \alu_div0_logical_op__insn_type$next  <= _013_;
      \alu_div0_logical_op__invert_in$next  <= _015_;
      \alu_div0_logical_op__invert_out$next  <= _017_;
      \alu_div0_logical_op__is_32bit$next  <= _019_;
      \alu_div0_logical_op__is_signed$next  <= _021_;
      \alu_div0_logical_op__oe__oe$next  <= _023_;
      \alu_div0_logical_op__oe__ok$next  <= _025_;
      \alu_div0_logical_op__output_carry$next  <= _027_;
      \alu_div0_logical_op__rc__ok$next  <= _029_;
      \alu_div0_logical_op__rc__rc$next  <= _031_;
      \alu_div0_logical_op__write_cr0$next  <= _033_;
      \alu_div0_logical_op__zero_a$next  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _189_;
    _044_ = _197_;
    (* src = "libresoc.v:133271.5-133271.29" *)
    casez (\initial )
      /* src = "libresoc.v:133271.9-133271.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _136_, _134_ } = { o_ok, alu_div0_o };
        end
      default:
        begin
          _134_ = data_r0__o;
          _136_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _190_, _189_ } = 65'h00000000000000000;
        end
      default:
        begin
          _189_ = _134_;
          _190_ = _136_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _197_ = 1'h0;
        end
      default:
          _197_ = _190_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _042_;
      \data_r0__o_ok$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _191_;
    _048_ = _198_;
    (* src = "libresoc.v:133293.5-133293.29" *)
    casez (\initial )
      /* src = "libresoc.v:133293.9-133293.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _140_, _138_ } = { cr_a_ok, alu_div0_cr_a };
        end
      default:
        begin
          _138_ = data_r1__cr_a;
          _140_ = data_r1__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _192_, _191_ } = 5'h00;
        end
      default:
        begin
          _191_ = _138_;
          _192_ = _140_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _198_ = 1'h0;
        end
      default:
          _198_ = _192_;
    endcase
  end
  always @* begin
      \data_r1__cr_a$next  <= _046_;
      \data_r1__cr_a_ok$next  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _193_;
    _052_ = _199_;
    (* src = "libresoc.v:133315.5-133315.29" *)
    casez (\initial )
      /* src = "libresoc.v:133315.9-133315.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _144_, _142_ } = { xer_ov_ok, alu_div0_xer_ov };
        end
      default:
        begin
          _142_ = data_r2__xer_ov;
          _144_ = data_r2__xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _194_, _193_ } = 3'h0;
        end
      default:
        begin
          _193_ = _142_;
          _194_ = _144_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _199_ = 1'h0;
        end
      default:
          _199_ = _194_;
    endcase
  end
  always @* begin
      \data_r2__xer_ov$next  <= _050_;
      \data_r2__xer_ov_ok$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _195_;
    _056_ = _200_;
    (* src = "libresoc.v:133337.5-133337.29" *)
    casez (\initial )
      /* src = "libresoc.v:133337.9-133337.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _148_, _146_ } = { xer_so_ok, alu_div0_xer_so };
        end
      default:
        begin
          _146_ = data_r3__xer_so;
          _148_ = data_r3__xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _196_, _195_ } = 2'h0;
        end
      default:
        begin
          _195_ = _146_;
          _196_ = _148_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _200_ = 1'h0;
        end
      default:
          _200_ = _196_;
    endcase
  end
  always @* begin
      \data_r3__xer_so$next  <= _054_;
      \data_r3__xer_so_ok$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = _177_;
    (* src = "libresoc.v:133359.5-133359.29" *)
    casez (\initial )
      /* src = "libresoc.v:133359.9-133359.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _177_ = src_or_imm;
        end
      default:
          _177_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = _179_;
    (* src = "libresoc.v:133369.5-133369.29" *)
    casez (\initial )
      /* src = "libresoc.v:133369.9-133369.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (\src_sel$82 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _179_ = \src_or_imm$85 ;
        end
      default:
          _179_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = _181_;
    (* src = "libresoc.v:133379.5-133379.29" *)
    casez (\initial )
      /* src = "libresoc.v:133379.9-133379.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _181_ = src3_i;
        end
      default:
          _181_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _132_;
    (* src = "libresoc.v:133389.5-133389.29" *)
    casez (\initial )
      /* src = "libresoc.v:133389.9-133389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h1;
        end
      default:
          _132_ = \$94 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _130_;
    (* src = "libresoc.v:133398.5-133398.29" *)
    casez (\initial )
      /* src = "libresoc.v:133398.9-133398.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h1;
        end
      default:
          _130_ = \$96 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _150_;
    (* src = "libresoc.v:133407.5-133407.29" *)
    casez (\initial )
      /* src = "libresoc.v:133407.9-133407.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$122 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _150_ = data_r0__o;
        end
      default:
          _150_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _151_;
    (* src = "libresoc.v:133417.5-133417.29" *)
    casez (\initial )
      /* src = "libresoc.v:133417.9-133417.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$124 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = data_r1__cr_a;
        end
      default:
          _151_ = 4'h0;
    endcase
  end
  always @* begin
      dest2_o <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _152_;
    (* src = "libresoc.v:133427.5-133427.29" *)
    casez (\initial )
      /* src = "libresoc.v:133427.9-133427.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$126 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _152_ = data_r2__xer_ov;
        end
      default:
          _152_ = 2'h0;
    endcase
  end
  always @* begin
      dest3_o <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _153_;
    (* src = "libresoc.v:133437.5-133437.29" *)
    casez (\initial )
      /* src = "libresoc.v:133437.9-133437.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$128 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = data_r3__xer_so;
        end
      default:
          _153_ = 1'h0;
    endcase
  end
  always @* begin
      dest4_o <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = _158_;
    (* src = "libresoc.v:133447.5-133447.29" *)
    casez (\initial )
      /* src = "libresoc.v:133447.9-133447.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _158_ = 4'h0;
        end
      default:
          _158_ = \$20 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _067_;
  end
  assign \$100  = _237_;
  assign \$102  = _238_;
  assign \$104  = _201_;
  assign \$106  = _239_;
  assign \$108  = _202_;
  assign \$10  = _203_;
  assign \$110  = _204_;
  assign \$112  = _205_;
  assign \$114  = _206_;
  assign \$116  = _207_;
  assign \$118  = _208_;
  assign \$120  = _209_;
  assign \$122  = _210_;
  assign \$124  = _211_;
  assign \$126  = _212_;
  assign \$128  = _213_;
  assign \$12  = _240_;
  assign \$14  = _214_;
  assign \$16  = _241_;
  assign \$18  = _215_;
  assign \$20  = _216_;
  assign \$24  = _242_;
  assign \$26  = _217_;
  assign \$23  = _254_;
  assign \$22  = _243_;
  assign \$2  = _218_;
  assign \$30  = _219_;
  assign \$32  = _255_;
  assign \$34  = _256_;
  assign \$36  = _246_;
  assign \$38  = _244_;
  assign \$40  = _220_;
  assign \$42  = _221_;
  assign \$44  = _235_;
  assign \$46  = _222_;
  assign \$48  = _236_;
  assign \$50  = _223_;
  assign \$52  = _224_;
  assign \$54  = _225_;
  assign \$56  = _247_;
  assign \$58  = _248_;
  assign \$5  = _245_;
  assign \$60  = _249_;
  assign \$62  = _250_;
  assign \$64  = _226_;
  assign \$66  = _227_;
  assign \$68  = _251_;
  assign \$70  = _228_;
  assign \$72  = _229_;
  assign \$74  = _230_;
  assign \$76  = _231_;
  assign \$78  = _257_;
  assign \$7  = _252_;
  assign \$80  = _258_;
  assign \$83  = _259_;
  assign \$86  = _260_;
  assign \$88  = _261_;
  assign \$4  = _253_;
  assign \$90  = _262_;
  assign \$92  = _263_;
  assign \$94  = _232_;
  assign \$96  = _233_;
  assign \$98  = _234_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$120 ;
  assign cu_rd__rel_o = \$108 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_div0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_div0_p_valid_i = alui_l_q_alui;
  assign \alu_div0_xer_so$1  = \$92 ;
  assign alu_div0_rb = \$90 ;
  assign alu_div0_ra = \$88 ;
  assign \src_or_imm$85  = \$86 ;
  assign \src_sel$82  = \$83 ;
  assign src_or_imm = \$80 ;
  assign src_sel = \$78 ;
  assign cu_wrmask_o = { \$76 , \$74 , \$72 , \$70  };
  assign reset_r = \$62 ;
  assign reset_w = \$60 ;
  assign rst_r = \$58 ;
  assign reset = \$56 ;
  assign wr_any = \$36 ;
  assign cu_done_o = \$30 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$18 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_div0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$14 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$10 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:133491.1-133500.10" *)
module div_state_init(o_q_bits_known, o_dividend_quotient, dividend);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *)
  input [127:0] dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  output [127:0] o_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  output [6:0] o_q_bits_known;
  assign o_dividend_quotient = dividend;
  assign o_q_bits_known = 7'h00;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:133504.1-133586.10" *)
module div_state_next(o_q_bits_known, i_q_bits_known, i_dividend_quotient, divisor, o_dividend_quotient);
  reg \initial  = 0;
  (* src = "libresoc.v:133505.7-133505.20" *)
  reg _00_;
  (* src = "libresoc.v:133570.3-133581.6" *)
  reg [127:0] _01_;
  (* src = "libresoc.v:133558.3-133569.6" *)
  reg [6:0] _02_;
  (* src = "libresoc.v:133546.3-133557.6" *)
  reg [127:0] _03_;
  (* src = "libresoc.v:133570.3-133581.6" *)
  reg [127:0] _04_;
  (* src = "libresoc.v:133558.3-133569.6" *)
  reg [6:0] _05_;
  (* src = "libresoc.v:133546.3-133557.6" *)
  reg [127:0] _06_;
  (* src = "libresoc.v:133540.18-133540.106" *)
  wire [7:0] _07_;
  (* src = "libresoc.v:133541.18-133541.109" *)
  wire _08_;
  (* src = "libresoc.v:133545.17-133545.108" *)
  wire _09_;
  (* src = "libresoc.v:133544.17-133544.101" *)
  wire _10_;
  (* src = "libresoc.v:133542.17-133542.101" *)
  wire [126:0] _11_;
  (* src = "libresoc.v:133543.17-133543.109" *)
  wire [128:0] _12_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *)
  wire [128:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *)
  wire [7:0] \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *)
  wire [7:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *)
  wire [126:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *)
  wire [128:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" *)
  wire [127:0] difference;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" *)
  input [63:0] divisor;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  input [127:0] i_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  input [6:0] i_q_bits_known;
  (* src = "libresoc.v:133505.7-133505.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" *)
  wire next_quotient_bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  output [127:0] o_dividend_quotient;
  reg [127:0] o_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  output [6:0] o_q_bits_known;
  reg [6:0] o_q_bits_known;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" *)
  reg [127:0] value;
  assign _07_ = i_q_bits_known + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" *) 1'h1;
  assign _08_ = i_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 7'h40;
  assign _09_ = i_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 7'h40;
  assign _10_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" *) difference[127];
  assign _11_ = divisor <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) 6'h3f;
  assign _12_ = i_dividend_quotient - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" *) \$2 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _06_;
    (* src = "libresoc.v:133547.5-133547.29" *)
    casez (\initial )
      /* src = "libresoc.v:133547.9-133547.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" *)
    casez (next_quotient_bit)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _06_ = difference;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _06_ = i_dividend_quotient;
        end
    endcase
  end
  always @* begin
      value <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _05_;
    (* src = "libresoc.v:133559.5-133559.29" *)
    casez (\initial )
      /* src = "libresoc.v:133559.9-133559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *)
    casez (\$8 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _05_ = i_q_bits_known;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _05_ = \$10 [6:0];
        end
    endcase
  end
  always @* begin
      o_q_bits_known <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _04_;
    (* src = "libresoc.v:133571.5-133571.29" *)
    casez (\initial )
      /* src = "libresoc.v:133571.9-133571.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _04_ = i_dividend_quotient;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = { value[126:0], next_quotient_bit };
        end
    endcase
  end
  always @* begin
      o_dividend_quotient <= _01_;
  end
  assign \$11  = _07_;
  assign \$13  = _08_;
  assign \$2  = _11_;
  assign \$4  = _12_;
  assign \$6  = _10_;
  assign \$8  = _09_;
  assign \$1  = \$4 ;
  assign \$10  = \$11 ;
  assign next_quotient_bit = \$6 ;
  assign difference = \$4 [127:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:133590.1-133833.10" *)
module dummy(trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , muxid);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \fast1$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \fast2$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__cia$6 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \trap_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \trap_op__insn$4 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \trap_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \trap_op__is_32bit$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__ldst_exc$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__msr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [12:0] \trap_op__trapaddr$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__traptype$8 ;
  assign \fast2$14  = fast2;
  assign \fast1$13  = fast1;
  assign \rb$12  = rb;
  assign \ra$11  = ra;
  assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2  } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
  assign \muxid$1  = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fast" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:133837.1-133968.10" *)
module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:133838.7-133838.20" *)
  reg _10_;
  (* src = "libresoc.v:133950.3-133959.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:133941.3-133949.6" *)
  reg _12_;
  (* src = "libresoc.v:133918.3-133919.41" *)
  reg _13_;
  (* src = "libresoc.v:133885.7-133885.27" *)
  reg _14_;
  (* src = "libresoc.v:133922.3-133930.6" *)
  reg _15_;
  (* src = "libresoc.v:133920.3-133921.35" *)
  reg _16_;
  (* src = "libresoc.v:133931.3-133940.6" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _18_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _20_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [2:0] _21_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _22_;
  (* src = "libresoc.v:133910.3-133915.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:133950.3-133959.6" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:133941.3-133949.6" *)
  reg _25_;
  (* src = "libresoc.v:133922.3-133930.6" *)
  reg _26_;
  (* src = "libresoc.v:133883.7-133883.23" *)
  reg _27_;
  (* src = "libresoc.v:133931.3-133940.6" *)
  reg [63:0] _28_;
  (* src = "libresoc.v:133916.26-133916.32" *)
  wire [63:0] _29_;
  (* src = "libresoc.v:133917.30-133917.36" *)
  wire [63:0] _30_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [2:0] _31_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _32_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [2:0] _34_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _35_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _36_;
  (* src = "libresoc.v:133908.13-133908.16" *)
  reg [2:0] _0_;
  (* src = "libresoc.v:133909.13-133909.16" *)
  reg [2:0] _1_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] dest1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] dest1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest1__wen;
  (* src = "libresoc.v:133838.7-133838.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] issue__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \issue__addr$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] issue__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] issue__data_o;
  reg [63:0] issue__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input issue__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input issue__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [2:0] memory_r_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [2:0] \memory_r_addr$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [63:0] memory_r_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [63:0] \memory_r_data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [2:0] memory_w_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [2:0] \memory_w_addr$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [63:0] memory_w_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [63:0] \memory_w_data$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire memory_w_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire \memory_w_en$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] src1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] src1__data_o;
  reg [63:0] src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src1__ren;
  (* src = "libresoc.v:133897.14-133897.20" *)
  reg [63:0] memory [7:0];
  initial begin
    memory[0] = 64'h0000000000000000;
    memory[1] = 64'h0000000000000000;
    memory[2] = 64'h0000000000000000;
    memory[3] = 64'h0000000000000000;
    memory[4] = 64'h0000000000000000;
    memory[5] = 64'h0000000000000000;
    memory[6] = 64'h0000000000000000;
    memory[7] = 64'h0000000000000000;
  end
  assign _30_ = memory[_1_];
  assign _29_ = memory[_0_];
  always @* begin
    if (\initial ) begin end
  end
  always @* begin
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _10_ = 1'h0;
  end
  always @* begin
      \initial  <= _10_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$8  <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = memory_r_addr;
    _09_ = \memory_r_addr$3 ;
    _02_ = _18_;
    _03_ = _19_;
    _04_ = _20_;
    _05_ = _21_;
    _06_ = _22_;
    _07_ = _23_;
    (* src = "libresoc.v:133913.5-133913.61" *)
    casez (memory_w_en)
      /* src = "libresoc.v:133913.9-133913.20" */
      1'h1:
        begin
          _18_ = memory_w_addr;
          _19_ = memory_w_data;
          _20_ = 64'hffffffffffffffff;
        end
      default:
        begin
          _18_ = 3'hx;
          _19_ = 64'hxxxxxxxxxxxxxxxx;
          _20_ = 64'h0000000000000000;
        end
    endcase
    (* src = "libresoc.v:133914.5-133914.73" *)
    casez (\memory_w_en$5 )
      /* src = "libresoc.v:133914.9-133914.23" */
      1'h1:
        begin
          _21_ = \memory_w_addr$6 ;
          _22_ = \memory_w_data$7 ;
          _23_ = 64'hffffffffffffffff;
        end
      default:
        begin
          _21_ = 3'hx;
          _22_ = 64'hxxxxxxxxxxxxxxxx;
          _23_ = 64'h0000000000000000;
        end
    endcase
  end
  always @(posedge coresync_clk) begin
      _0_ <= _08_;
      _1_ <= _09_;
      _31_ <= _02_;
      _32_ <= _03_;
      _33_ <= _04_;
      _34_ <= _05_;
      _35_ <= _06_;
      _36_ <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = \ren_delay$8$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$8  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _26_;
    (* src = "libresoc.v:133923.5-133923.29" *)
    casez (\initial )
      /* src = "libresoc.v:133923.9-133923.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = 1'h0;
        end
      default:
          _26_ = src1__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _28_;
    (* src = "libresoc.v:133932.5-133932.29" *)
    casez (\initial )
      /* src = "libresoc.v:133932.9-133932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *)
    casez (ren_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = memory_r_data;
        end
      default:
          _28_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      src1__data_o <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _25_;
    (* src = "libresoc.v:133942.5-133942.29" *)
    casez (\initial )
      /* src = "libresoc.v:133942.9-133942.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = 1'h0;
        end
      default:
          _25_ = issue__ren;
    endcase
  end
  always @* begin
      \ren_delay$8$next  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _24_;
    (* src = "libresoc.v:133951.5-133951.29" *)
    casez (\initial )
      /* src = "libresoc.v:133951.9-133951.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *)
    casez (\ren_delay$8 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = \memory_r_data$4 ;
        end
      default:
          _24_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      issue__data_o <= _11_;
  end
  assign memory_r_data = _29_;
  assign \memory_r_data$4  = _30_;
  assign \memory_w_data$7  = issue__data_i;
  assign \memory_w_en$5  = issue__wen;
  assign \memory_w_addr$6  = \issue__addr$1 ;
  assign memory_w_data = dest1__data_i;
  assign memory_w_en = dest1__wen;
  assign memory_w_addr = dest1__addr;
  assign \memory_r_addr$3  = issue__addr;
  assign memory_r_addr = src1__addr;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:133972.1-135922.10" *)
module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src2_i$79 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$80 , \cu_wr__rel_o$81 , \cu_wr__go_i$82 , \o_ok$83 , \cu_wr__rel_o$84 , \cu_wr__go_i$85 , \o_ok$86 , \cu_wr__rel_o$87 , \cu_wr__go_i$88 , \o_ok$89 , \cu_wr__rel_o$90 , \cu_wr__go_i$91 , \o_ok$92 , \cu_wr__rel_o$93 , \cu_wr__go_i$94 , \o_ok$95 , \cu_wr__rel_o$96 , \cu_wr__go_i$97 , \o_ok$98 , \cu_wr__rel_o$99 , \cu_wr__go_i$100 , \cu_wr__rel_o$101 , \cu_wr__go_i$102 , dest1_o, \dest1_o$103 , \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$110 , \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \dest2_o$115 , dest3_o, \dest2_o$116 , \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , xer_ca_ok, \xer_ca_ok$120 , \xer_ca_ok$121 , \dest3_o$122 , dest6_o, \dest3_o$123 , xer_ov_ok, \xer_ov_ok$124 , \xer_ov_ok$125 , \xer_ov_ok$126 , dest4_o, dest5_o, \dest3_o$127 , \dest3_o$128 , xer_so_ok, \xer_so_ok$129 , \xer_so_ok$130 , \xer_so_ok$131 , \dest5_o$132 , \dest4_o$133 , \dest4_o$134 , \dest4_o$135 , fast1_ok, \cu_wr__rel_o$136 , \cu_wr__go_i$137 , \fast1_ok$138 , \fast1_ok$139 , fast2_ok, \fast2_ok$140 , \dest1_o$141 , \dest2_o$142 , \dest3_o$143 , \dest2_o$144 , \dest3_o$145 , nia_ok, \nia_ok$146 , \dest3_o$147 , \dest4_o$148 , msr_ok, \dest5_o$149 , spr1_ok, \dest2_o$150 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$151 , \ldst_port0_exc_$signal$152 , \ldst_port0_exc_$signal$153 , \ldst_port0_exc_$signal$154 , \ldst_port0_exc_$signal$155 , \ldst_port0_exc_$signal$156 , \ldst_port0_exc_$signal$157 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_ad__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_ad__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output \cu_busy_o$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input \cu_issue_i$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] \cu_rd__go_i$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] \cu_rd__go_i$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_rd__go_i$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_rd__go_i$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_rd__go_i$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] \cu_rd__go_i$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_rd__go_i$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] \cu_rd__go_i$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_rd__go_i$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] \cu_rd__rel_o$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] \cu_rd__rel_o$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_rd__rel_o$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_rd__rel_o$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_rd__rel_o$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] \cu_rd__rel_o$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_rd__rel_o$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] \cu_rd__rel_o$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_rd__rel_o$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [3:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] \cu_rdmaskn_i$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [5:0] \cu_rdmaskn_i$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] \cu_rdmaskn_i$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] \cu_rdmaskn_i$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [4:0] \cu_rdmaskn_i$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] \cu_rdmaskn_i$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [5:0] \cu_rdmaskn_i$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] \cu_rdmaskn_i$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [3:0] \cu_rdmaskn_i$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_st__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_st__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_wr__go_i$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [1:0] \cu_wr__go_i$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_wr__go_i$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] \cu_wr__go_i$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] \cu_wr__go_i$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [1:0] \cu_wr__go_i$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] \cu_wr__go_i$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] \cu_wr__go_i$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] \cu_wr__go_i$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [1:0] \cu_wr__rel_o$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_wr__rel_o$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_wr__rel_o$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] \cu_wr__rel_o$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [1:0] \cu_wr__rel_o$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] \cu_wr__rel_o$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] \cu_wr__rel_o$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] \cu_wr__rel_o$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] \cu_wr__rel_o$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest1_o$141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [31:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] \dest2_o$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] \dest2_o$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] \dest2_o$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] \dest2_o$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] \dest2_o$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest2_o$142 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest2_o$144 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest2_o$150 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] \dest3_o$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] \dest3_o$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] \dest3_o$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] \dest3_o$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest3_o$143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest3_o$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest3_o$147 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest4_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output \dest4_o$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output \dest4_o$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output \dest4_o$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest4_o$148 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest5_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output \dest5_o$132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] \dest5_o$149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest6_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \fast1_ok$138 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \fast1_ok$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \fast2_ok$140 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [95:0] ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  input ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  input ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  output [3:0] ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$153 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$155 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$156 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$157 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  output ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  output ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output msr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \nia_ok$146 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_alu0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_alu0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_alu0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_alu0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_alu0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_alu0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_alu0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_branch0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_branch0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_branch0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_branch0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_branch0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_branch0__lk;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_cr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_cr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_cr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_div0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_div0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_div0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_div0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_div0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_div0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_div0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_logical0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_logical0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_logical0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_logical0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_logical0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_logical0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__zero_a;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_mul0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_mul0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_mul0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_mul0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__write_cr0;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_shift_rot0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_shift_rot0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_shift_rot0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_shift_rot0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_shift_rot0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__write_cr0;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_spr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_spr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_spr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_spr0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_trap0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_trap0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_trap0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_trap0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_trap0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] oper_i_alu_trap0__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_trap0__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] oper_i_alu_trap0__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] oper_i_alu_trap0__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_ldst_ldst0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_ldst_ldst0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_ldst_ldst0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_ldst_ldst0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_ldst_ldst0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__is_signed;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_ldst_ldst0__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src1_i$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src2_i$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src3_i$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input \src3_i$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input \src3_i$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input \src3_i$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input \src3_i$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [31:0] \src3_i$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] \src3_i$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src3_i$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src3_i$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src4_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input \src4_i$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] \src4_i$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] \src4_i$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] \src4_i$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src5_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] \src5_i$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] \src5_i$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src6_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [3:0] \src6_i$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ca_ok$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ca_ok$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ov_ok$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ov_ok$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ov_ok$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so_ok$129 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so_ok$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so_ok$131 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135554.8-135596.4" *)
  alu0 alu0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(cr_a_ok),
    .cu_busy_o(cu_busy_o),
    .cu_issue_i(cu_issue_i),
    .cu_rd__go_i(cu_rd__go_i),
    .cu_rd__rel_o(cu_rd__rel_o),
    .cu_rdmaskn_i(cu_rdmaskn_i),
    .cu_wr__go_i(cu_wr__go_i),
    .cu_wr__rel_o(cu_wr__rel_o),
    .dest1_o(dest1_o),
    .dest2_o(\dest2_o$115 ),
    .dest3_o(\dest3_o$122 ),
    .dest4_o(dest4_o),
    .dest5_o(\dest5_o$132 ),
    .o_ok(o_ok),
    .oper_i_alu_alu0__data_len(oper_i_alu_alu0__data_len),
    .oper_i_alu_alu0__fn_unit(oper_i_alu_alu0__fn_unit),
    .oper_i_alu_alu0__imm_data__data(oper_i_alu_alu0__imm_data__data),
    .oper_i_alu_alu0__imm_data__ok(oper_i_alu_alu0__imm_data__ok),
    .oper_i_alu_alu0__input_carry(oper_i_alu_alu0__input_carry),
    .oper_i_alu_alu0__insn(oper_i_alu_alu0__insn),
    .oper_i_alu_alu0__insn_type(oper_i_alu_alu0__insn_type),
    .oper_i_alu_alu0__invert_in(oper_i_alu_alu0__invert_in),
    .oper_i_alu_alu0__invert_out(oper_i_alu_alu0__invert_out),
    .oper_i_alu_alu0__is_32bit(oper_i_alu_alu0__is_32bit),
    .oper_i_alu_alu0__is_signed(oper_i_alu_alu0__is_signed),
    .oper_i_alu_alu0__oe__oe(oper_i_alu_alu0__oe__oe),
    .oper_i_alu_alu0__oe__ok(oper_i_alu_alu0__oe__ok),
    .oper_i_alu_alu0__output_carry(oper_i_alu_alu0__output_carry),
    .oper_i_alu_alu0__rc__ok(oper_i_alu_alu0__rc__ok),
    .oper_i_alu_alu0__rc__rc(oper_i_alu_alu0__rc__rc),
    .oper_i_alu_alu0__write_cr0(oper_i_alu_alu0__write_cr0),
    .oper_i_alu_alu0__zero_a(oper_i_alu_alu0__zero_a),
    .src1_i(src1_i),
    .src2_i(src2_i),
    .src3_i(\src3_i$60 ),
    .src4_i(\src4_i$65 ),
    .xer_ca_ok(xer_ca_ok),
    .xer_ov_ok(xer_ov_ok),
    .xer_so_ok(xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135597.11-135624.4" *)
  branch0 branch0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cu_busy_o(\cu_busy_o$5 ),
    .cu_issue_i(\cu_issue_i$4 ),
    .cu_rd__go_i(\cu_rd__go_i$70 ),
    .cu_rd__rel_o(\cu_rd__rel_o$69 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$6 ),
    .cu_wr__go_i(\cu_wr__go_i$137 ),
    .cu_wr__rel_o(\cu_wr__rel_o$136 ),
    .dest1_o(\dest1_o$141 ),
    .dest2_o(\dest2_o$144 ),
    .dest3_o(\dest3_o$147 ),
    .fast1_ok(fast1_ok),
    .fast2_ok(fast2_ok),
    .nia_ok(nia_ok),
    .oper_i_alu_branch0__cia(oper_i_alu_branch0__cia),
    .oper_i_alu_branch0__fn_unit(oper_i_alu_branch0__fn_unit),
    .oper_i_alu_branch0__imm_data__data(oper_i_alu_branch0__imm_data__data),
    .oper_i_alu_branch0__imm_data__ok(oper_i_alu_branch0__imm_data__ok),
    .oper_i_alu_branch0__insn(oper_i_alu_branch0__insn),
    .oper_i_alu_branch0__insn_type(oper_i_alu_branch0__insn_type),
    .oper_i_alu_branch0__is_32bit(oper_i_alu_branch0__is_32bit),
    .oper_i_alu_branch0__lk(oper_i_alu_branch0__lk),
    .src1_i(\src1_i$74 ),
    .src2_i(\src2_i$77 ),
    .src3_i(\src3_i$71 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135625.7-135650.4" *)
  cr0 cr0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(\cr_a_ok$110 ),
    .cu_busy_o(\cu_busy_o$2 ),
    .cu_issue_i(\cu_issue_i$1 ),
    .cu_rd__go_i(\cu_rd__go_i$29 ),
    .cu_rd__rel_o(\cu_rd__rel_o$28 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$3 ),
    .cu_wr__go_i(\cu_wr__go_i$82 ),
    .cu_wr__rel_o(\cu_wr__rel_o$81 ),
    .dest1_o(\dest1_o$103 ),
    .dest2_o(dest2_o),
    .dest3_o(dest3_o),
    .full_cr_ok(full_cr_ok),
    .o_ok(\o_ok$80 ),
    .oper_i_alu_cr0__fn_unit(oper_i_alu_cr0__fn_unit),
    .oper_i_alu_cr0__insn(oper_i_alu_cr0__insn),
    .oper_i_alu_cr0__insn_type(oper_i_alu_cr0__insn_type),
    .src1_i(\src1_i$50 ),
    .src2_i(\src2_i$30 ),
    .src3_i(\src3_i$67 ),
    .src4_i(\src4_i$68 ),
    .src5_i(\src5_i$72 ),
    .src6_i(\src6_i$73 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135651.8-135690.4" *)
  div0 div0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(\cr_a_ok$112 ),
    .cu_busy_o(\cu_busy_o$17 ),
    .cu_issue_i(\cu_issue_i$16 ),
    .cu_rd__go_i(\cu_rd__go_i$38 ),
    .cu_rd__rel_o(\cu_rd__rel_o$37 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$18 ),
    .cu_wr__go_i(\cu_wr__go_i$94 ),
    .cu_wr__rel_o(\cu_wr__rel_o$93 ),
    .dest1_o(\dest1_o$107 ),
    .dest2_o(\dest2_o$117 ),
    .dest3_o(\dest3_o$127 ),
    .dest4_o(\dest4_o$134 ),
    .o_ok(\o_ok$92 ),
    .oper_i_alu_div0__data_len(oper_i_alu_div0__data_len),
    .oper_i_alu_div0__fn_unit(oper_i_alu_div0__fn_unit),
    .oper_i_alu_div0__imm_data__data(oper_i_alu_div0__imm_data__data),
    .oper_i_alu_div0__imm_data__ok(oper_i_alu_div0__imm_data__ok),
    .oper_i_alu_div0__input_carry(oper_i_alu_div0__input_carry),
    .oper_i_alu_div0__insn(oper_i_alu_div0__insn),
    .oper_i_alu_div0__insn_type(oper_i_alu_div0__insn_type),
    .oper_i_alu_div0__invert_in(oper_i_alu_div0__invert_in),
    .oper_i_alu_div0__invert_out(oper_i_alu_div0__invert_out),
    .oper_i_alu_div0__is_32bit(oper_i_alu_div0__is_32bit),
    .oper_i_alu_div0__is_signed(oper_i_alu_div0__is_signed),
    .oper_i_alu_div0__oe__oe(oper_i_alu_div0__oe__oe),
    .oper_i_alu_div0__oe__ok(oper_i_alu_div0__oe__ok),
    .oper_i_alu_div0__output_carry(oper_i_alu_div0__output_carry),
    .oper_i_alu_div0__rc__ok(oper_i_alu_div0__rc__ok),
    .oper_i_alu_div0__rc__rc(oper_i_alu_div0__rc__rc),
    .oper_i_alu_div0__write_cr0(oper_i_alu_div0__write_cr0),
    .oper_i_alu_div0__zero_a(oper_i_alu_div0__zero_a),
    .src1_i(\src1_i$56 ),
    .src2_i(\src2_i$39 ),
    .src3_i(\src3_i$62 ),
    .xer_ov_ok(\xer_ov_ok$125 ),
    .xer_so_ok(\xer_so_ok$130 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135691.9-135745.4" *)
  ldst0 ldst0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cu_ad__go_i(cu_ad__go_i),
    .cu_ad__rel_o(cu_ad__rel_o),
    .cu_busy_o(\cu_busy_o$26 ),
    .cu_issue_i(\cu_issue_i$25 ),
    .cu_rd__go_i(\cu_rd__go_i$47 ),
    .cu_rd__rel_o(\cu_rd__rel_o$46 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$27 ),
    .cu_st__go_i(cu_st__go_i),
    .cu_st__rel_o(cu_st__rel_o),
    .cu_wr__go_i(\cu_wr__go_i$102 ),
    .cu_wr__rel_o(\cu_wr__rel_o$101 ),
    .ea(ea),
    .ldst_port0_addr_i(ldst_port0_addr_i),
    .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok),
    .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o),
    .ldst_port0_busy_o(ldst_port0_busy_o),
    .ldst_port0_data_len(ldst_port0_data_len),
    .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ),
    .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$151 ),
    .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$152 ),
    .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$153 ),
    .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$154 ),
    .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$155 ),
    .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$156 ),
    .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$157 ),
    .ldst_port0_is_ld_i(ldst_port0_is_ld_i),
    .ldst_port0_is_st_i(ldst_port0_is_st_i),
    .ldst_port0_ld_data_o(ldst_port0_ld_data_o),
    .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok),
    .ldst_port0_st_data_i(ldst_port0_st_data_i),
    .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok),
    .o(o),
    .oper_i_ldst_ldst0__byte_reverse(oper_i_ldst_ldst0__byte_reverse),
    .oper_i_ldst_ldst0__data_len(oper_i_ldst_ldst0__data_len),
    .oper_i_ldst_ldst0__fn_unit(oper_i_ldst_ldst0__fn_unit),
    .oper_i_ldst_ldst0__imm_data__data(oper_i_ldst_ldst0__imm_data__data),
    .oper_i_ldst_ldst0__imm_data__ok(oper_i_ldst_ldst0__imm_data__ok),
    .oper_i_ldst_ldst0__insn(oper_i_ldst_ldst0__insn),
    .oper_i_ldst_ldst0__insn_type(oper_i_ldst_ldst0__insn_type),
    .oper_i_ldst_ldst0__is_32bit(oper_i_ldst_ldst0__is_32bit),
    .oper_i_ldst_ldst0__is_signed(oper_i_ldst_ldst0__is_signed),
    .oper_i_ldst_ldst0__ldst_mode(oper_i_ldst_ldst0__ldst_mode),
    .oper_i_ldst_ldst0__oe__oe(oper_i_ldst_ldst0__oe__oe),
    .oper_i_ldst_ldst0__oe__ok(oper_i_ldst_ldst0__oe__ok),
    .oper_i_ldst_ldst0__rc__ok(oper_i_ldst_ldst0__rc__ok),
    .oper_i_ldst_ldst0__rc__rc(oper_i_ldst_ldst0__rc__rc),
    .oper_i_ldst_ldst0__sign_extend(oper_i_ldst_ldst0__sign_extend),
    .oper_i_ldst_ldst0__zero_a(oper_i_ldst_ldst0__zero_a),
    .src1_i(\src1_i$59 ),
    .src2_i(\src2_i$48 ),
    .src3_i(\src3_i$49 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135746.12-135781.4" *)
  logical0 logical0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(\cr_a_ok$111 ),
    .cu_busy_o(\cu_busy_o$11 ),
    .cu_issue_i(\cu_issue_i$10 ),
    .cu_rd__go_i(\cu_rd__go_i$35 ),
    .cu_rd__rel_o(\cu_rd__rel_o$34 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$12 ),
    .cu_wr__go_i(\cu_wr__go_i$88 ),
    .cu_wr__rel_o(\cu_wr__rel_o$87 ),
    .dest1_o(\dest1_o$105 ),
    .dest2_o(\dest2_o$116 ),
    .o_ok(\o_ok$86 ),
    .oper_i_alu_logical0__data_len(oper_i_alu_logical0__data_len),
    .oper_i_alu_logical0__fn_unit(oper_i_alu_logical0__fn_unit),
    .oper_i_alu_logical0__imm_data__data(oper_i_alu_logical0__imm_data__data),
    .oper_i_alu_logical0__imm_data__ok(oper_i_alu_logical0__imm_data__ok),
    .oper_i_alu_logical0__input_carry(oper_i_alu_logical0__input_carry),
    .oper_i_alu_logical0__insn(oper_i_alu_logical0__insn),
    .oper_i_alu_logical0__insn_type(oper_i_alu_logical0__insn_type),
    .oper_i_alu_logical0__invert_in(oper_i_alu_logical0__invert_in),
    .oper_i_alu_logical0__invert_out(oper_i_alu_logical0__invert_out),
    .oper_i_alu_logical0__is_32bit(oper_i_alu_logical0__is_32bit),
    .oper_i_alu_logical0__is_signed(oper_i_alu_logical0__is_signed),
    .oper_i_alu_logical0__oe__oe(oper_i_alu_logical0__oe__oe),
    .oper_i_alu_logical0__oe__ok(oper_i_alu_logical0__oe__ok),
    .oper_i_alu_logical0__output_carry(oper_i_alu_logical0__output_carry),
    .oper_i_alu_logical0__rc__ok(oper_i_alu_logical0__rc__ok),
    .oper_i_alu_logical0__rc__rc(oper_i_alu_logical0__rc__rc),
    .oper_i_alu_logical0__write_cr0(oper_i_alu_logical0__write_cr0),
    .oper_i_alu_logical0__zero_a(oper_i_alu_logical0__zero_a),
    .src1_i(\src1_i$52 ),
    .src2_i(\src2_i$36 ),
    .src3_i(\src3_i$61 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135782.8-135815.4" *)
  mul0 mul0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(\cr_a_ok$113 ),
    .cu_busy_o(\cu_busy_o$20 ),
    .cu_issue_i(\cu_issue_i$19 ),
    .cu_rd__go_i(\cu_rd__go_i$41 ),
    .cu_rd__rel_o(\cu_rd__rel_o$40 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$21 ),
    .cu_wr__go_i(\cu_wr__go_i$97 ),
    .cu_wr__rel_o(\cu_wr__rel_o$96 ),
    .dest1_o(\dest1_o$108 ),
    .dest2_o(\dest2_o$118 ),
    .dest3_o(\dest3_o$128 ),
    .dest4_o(\dest4_o$135 ),
    .o_ok(\o_ok$95 ),
    .oper_i_alu_mul0__fn_unit(oper_i_alu_mul0__fn_unit),
    .oper_i_alu_mul0__imm_data__data(oper_i_alu_mul0__imm_data__data),
    .oper_i_alu_mul0__imm_data__ok(oper_i_alu_mul0__imm_data__ok),
    .oper_i_alu_mul0__insn(oper_i_alu_mul0__insn),
    .oper_i_alu_mul0__insn_type(oper_i_alu_mul0__insn_type),
    .oper_i_alu_mul0__is_32bit(oper_i_alu_mul0__is_32bit),
    .oper_i_alu_mul0__is_signed(oper_i_alu_mul0__is_signed),
    .oper_i_alu_mul0__oe__oe(oper_i_alu_mul0__oe__oe),
    .oper_i_alu_mul0__oe__ok(oper_i_alu_mul0__oe__ok),
    .oper_i_alu_mul0__rc__ok(oper_i_alu_mul0__rc__ok),
    .oper_i_alu_mul0__rc__rc(oper_i_alu_mul0__rc__rc),
    .oper_i_alu_mul0__write_cr0(oper_i_alu_mul0__write_cr0),
    .src1_i(\src1_i$57 ),
    .src2_i(\src2_i$42 ),
    .src3_i(\src3_i$63 ),
    .xer_ov_ok(\xer_ov_ok$126 ),
    .xer_so_ok(\xer_so_ok$131 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135816.13-135854.4" *)
  shiftrot0 shiftrot0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a_ok(\cr_a_ok$114 ),
    .cu_busy_o(\cu_busy_o$23 ),
    .cu_issue_i(\cu_issue_i$22 ),
    .cu_rd__go_i(\cu_rd__go_i$44 ),
    .cu_rd__rel_o(\cu_rd__rel_o$43 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$24 ),
    .cu_wr__go_i(\cu_wr__go_i$100 ),
    .cu_wr__rel_o(\cu_wr__rel_o$99 ),
    .dest1_o(\dest1_o$109 ),
    .dest2_o(\dest2_o$119 ),
    .dest3_o(\dest3_o$123 ),
    .o_ok(\o_ok$98 ),
    .oper_i_alu_shift_rot0__fn_unit(oper_i_alu_shift_rot0__fn_unit),
    .oper_i_alu_shift_rot0__imm_data__data(oper_i_alu_shift_rot0__imm_data__data),
    .oper_i_alu_shift_rot0__imm_data__ok(oper_i_alu_shift_rot0__imm_data__ok),
    .oper_i_alu_shift_rot0__input_carry(oper_i_alu_shift_rot0__input_carry),
    .oper_i_alu_shift_rot0__input_cr(oper_i_alu_shift_rot0__input_cr),
    .oper_i_alu_shift_rot0__insn(oper_i_alu_shift_rot0__insn),
    .oper_i_alu_shift_rot0__insn_type(oper_i_alu_shift_rot0__insn_type),
    .oper_i_alu_shift_rot0__invert_in(oper_i_alu_shift_rot0__invert_in),
    .oper_i_alu_shift_rot0__is_32bit(oper_i_alu_shift_rot0__is_32bit),
    .oper_i_alu_shift_rot0__is_signed(oper_i_alu_shift_rot0__is_signed),
    .oper_i_alu_shift_rot0__oe__oe(oper_i_alu_shift_rot0__oe__oe),
    .oper_i_alu_shift_rot0__oe__ok(oper_i_alu_shift_rot0__oe__ok),
    .oper_i_alu_shift_rot0__output_carry(oper_i_alu_shift_rot0__output_carry),
    .oper_i_alu_shift_rot0__output_cr(oper_i_alu_shift_rot0__output_cr),
    .oper_i_alu_shift_rot0__rc__ok(oper_i_alu_shift_rot0__rc__ok),
    .oper_i_alu_shift_rot0__rc__rc(oper_i_alu_shift_rot0__rc__rc),
    .oper_i_alu_shift_rot0__write_cr0(oper_i_alu_shift_rot0__write_cr0),
    .src1_i(\src1_i$58 ),
    .src2_i(\src2_i$45 ),
    .src3_i(src3_i),
    .src4_i(\src4_i$64 ),
    .src5_i(src5_i),
    .xer_ca_ok(\xer_ca_ok$121 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135855.8-135887.4" *)
  spr0 spr0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cu_busy_o(\cu_busy_o$14 ),
    .cu_issue_i(\cu_issue_i$13 ),
    .cu_rd__go_i(\cu_rd__go_i$54 ),
    .cu_rd__rel_o(\cu_rd__rel_o$53 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$15 ),
    .cu_wr__go_i(\cu_wr__go_i$91 ),
    .cu_wr__rel_o(\cu_wr__rel_o$90 ),
    .dest1_o(\dest1_o$106 ),
    .dest2_o(\dest2_o$150 ),
    .dest3_o(\dest3_o$143 ),
    .dest4_o(\dest4_o$133 ),
    .dest5_o(dest5_o),
    .dest6_o(dest6_o),
    .fast1_ok(\fast1_ok$139 ),
    .o_ok(\o_ok$89 ),
    .oper_i_alu_spr0__fn_unit(oper_i_alu_spr0__fn_unit),
    .oper_i_alu_spr0__insn(oper_i_alu_spr0__insn),
    .oper_i_alu_spr0__insn_type(oper_i_alu_spr0__insn_type),
    .oper_i_alu_spr0__is_32bit(oper_i_alu_spr0__is_32bit),
    .spr1_ok(spr1_ok),
    .src1_i(\src1_i$55 ),
    .src2_i(\src2_i$79 ),
    .src3_i(\src3_i$76 ),
    .src4_i(src4_i),
    .src5_i(\src5_i$66 ),
    .src6_i(src6_i),
    .xer_ca_ok(\xer_ca_ok$120 ),
    .xer_ov_ok(\xer_ov_ok$124 ),
    .xer_so_ok(\xer_so_ok$129 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:135888.9-135921.4" *)
  trap0 trap0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cu_busy_o(\cu_busy_o$8 ),
    .cu_issue_i(\cu_issue_i$7 ),
    .cu_rd__go_i(\cu_rd__go_i$32 ),
    .cu_rd__rel_o(\cu_rd__rel_o$31 ),
    .cu_rdmaskn_i(\cu_rdmaskn_i$9 ),
    .cu_wr__go_i(\cu_wr__go_i$85 ),
    .cu_wr__rel_o(\cu_wr__rel_o$84 ),
    .dest1_o(\dest1_o$104 ),
    .dest2_o(\dest2_o$142 ),
    .dest3_o(\dest3_o$145 ),
    .dest4_o(\dest4_o$148 ),
    .dest5_o(\dest5_o$149 ),
    .fast1_ok(\fast1_ok$138 ),
    .fast2_ok(\fast2_ok$140 ),
    .msr_ok(msr_ok),
    .nia_ok(\nia_ok$146 ),
    .o_ok(\o_ok$83 ),
    .oper_i_alu_trap0__cia(oper_i_alu_trap0__cia),
    .oper_i_alu_trap0__fn_unit(oper_i_alu_trap0__fn_unit),
    .oper_i_alu_trap0__insn(oper_i_alu_trap0__insn),
    .oper_i_alu_trap0__insn_type(oper_i_alu_trap0__insn_type),
    .oper_i_alu_trap0__is_32bit(oper_i_alu_trap0__is_32bit),
    .oper_i_alu_trap0__ldst_exc(oper_i_alu_trap0__ldst_exc),
    .oper_i_alu_trap0__msr(oper_i_alu_trap0__msr),
    .oper_i_alu_trap0__trapaddr(oper_i_alu_trap0__trapaddr),
    .oper_i_alu_trap0__traptype(oper_i_alu_trap0__traptype),
    .src1_i(\src1_i$51 ),
    .src2_i(\src2_i$33 ),
    .src3_i(\src3_i$75 ),
    .src4_i(\src4_i$78 )
  );
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.l0.idx_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:135926.1-135984.10" *)
module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:135927.7-135927.20" *)
  reg _00_;
  (* src = "libresoc.v:135972.3-135980.6" *)
  reg _01_;
  (* src = "libresoc.v:135970.3-135971.27" *)
  reg _02_;
  (* src = "libresoc.v:135972.3-135980.6" *)
  reg _03_;
  (* src = "libresoc.v:135951.7-135951.19" *)
  reg _04_;
  (* src = "libresoc.v:135962.17-135962.96" *)
  wire _05_;
  (* src = "libresoc.v:135967.17-135967.96" *)
  wire _06_;
  (* src = "libresoc.v:135964.18-135964.95" *)
  wire _07_;
  (* src = "libresoc.v:135966.17-135966.94" *)
  wire _08_;
  (* src = "libresoc.v:135969.17-135969.94" *)
  wire _09_;
  (* src = "libresoc.v:135963.18-135963.100" *)
  wire _10_;
  (* src = "libresoc.v:135965.18-135965.101" *)
  wire _11_;
  (* src = "libresoc.v:135968.17-135968.99" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:135927.7-135927.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_idx_l;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_idx_l;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_idx_l;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_idx_l;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_idx_l;
  assign _11_ = q_idx_l | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_idx_l;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:135973.5-135973.29" *)
    casez (\initial )
      /* src = "libresoc.v:135973.9-135973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_idx_l = \$15 ;
  assign qn_idx_l = \$13 ;
  assign q_idx_l = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.imem" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:135988.1-136367.10" *)
module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, clk);
  reg \initial  = 0;
  (* src = "libresoc.v:136319.3-136328.6" *)
  reg _000_;
  (* src = "libresoc.v:136299.3-136318.6" *)
  reg [44:0] _001_;
  (* src = "libresoc.v:136130.3-136131.39" *)
  reg [44:0] _002_;
  (* src = "libresoc.v:136329.3-136346.6" *)
  reg _003_;
  (* src = "libresoc.v:136276.3-136298.6" *)
  reg _004_;
  (* src = "libresoc.v:136132.3-136133.43" *)
  reg _005_;
  (* src = "libresoc.v:136347.3-136364.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:136253.3-136275.6" *)
  reg [44:0] _007_;
  (* src = "libresoc.v:136134.3-136135.35" *)
  reg [44:0] _008_;
  (* src = "libresoc.v:136144.3-136171.6" *)
  reg _009_;
  (* src = "libresoc.v:136142.3-136143.35" *)
  reg _010_;
  (* src = "libresoc.v:136200.3-136227.6" *)
  reg [7:0] _011_;
  (* src = "libresoc.v:136138.3-136139.35" *)
  reg [7:0] _012_;
  (* src = "libresoc.v:136172.3-136199.6" *)
  reg _013_;
  (* src = "libresoc.v:136140.3-136141.35" *)
  reg _014_;
  (* src = "libresoc.v:136228.3-136252.6" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:136136.3-136137.37" *)
  reg [63:0] _016_;
  (* src = "libresoc.v:135989.7-135989.20" *)
  reg _017_;
  (* src = "libresoc.v:136319.3-136328.6" *)
  reg _018_;
  (* src = "libresoc.v:136299.3-136318.6" *)
  reg [44:0] _019_;
  (* src = "libresoc.v:136053.14-136053.44" *)
  reg [44:0] _020_;
  (* src = "libresoc.v:136329.3-136346.6" *)
  reg _021_;
  (* src = "libresoc.v:136276.3-136298.6" *)
  reg _022_;
  (* src = "libresoc.v:136060.7-136060.27" *)
  reg _023_;
  (* src = "libresoc.v:136347.3-136364.6" *)
  reg [63:0] _024_;
  (* src = "libresoc.v:136253.3-136275.6" *)
  reg [44:0] _025_;
  (* src = "libresoc.v:136074.14-136074.42" *)
  reg [44:0] _026_;
  (* src = "libresoc.v:136144.3-136171.6" *)
  reg _027_;
  (* src = "libresoc.v:136079.7-136079.23" *)
  reg _028_;
  (* src = "libresoc.v:136200.3-136227.6" *)
  reg [7:0] _029_;
  (* src = "libresoc.v:136088.13-136088.30" *)
  reg [7:0] _030_;
  (* src = "libresoc.v:136172.3-136199.6" *)
  reg _031_;
  (* src = "libresoc.v:136093.7-136093.23" *)
  reg _032_;
  (* src = "libresoc.v:136228.3-136252.6" *)
  reg [63:0] _033_;
  (* src = "libresoc.v:136097.14-136097.47" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:136299.3-136318.6" *)
  reg [44:0] _035_;
  (* src = "libresoc.v:136329.3-136346.6" *)
  reg _036_;
  (* src = "libresoc.v:136276.3-136298.6" *)
  reg _037_;
  (* src = "libresoc.v:136347.3-136364.6" *)
  reg [63:0] _038_;
  (* src = "libresoc.v:136253.3-136275.6" *)
  reg [44:0] _039_;
  (* src = "libresoc.v:136144.3-136171.6" *)
  reg _040_;
  (* src = "libresoc.v:136200.3-136227.6" *)
  reg [7:0] _041_;
  (* src = "libresoc.v:136172.3-136199.6" *)
  reg _042_;
  (* src = "libresoc.v:136228.3-136252.6" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:136299.3-136318.6" *)
  reg [44:0] _044_;
  (* src = "libresoc.v:136276.3-136298.6" *)
  reg _045_;
  (* src = "libresoc.v:136253.3-136275.6" *)
  reg [44:0] _046_;
  (* src = "libresoc.v:136144.3-136171.6" *)
  reg _047_;
  (* src = "libresoc.v:136200.3-136227.6" *)
  reg [7:0] _048_;
  (* src = "libresoc.v:136172.3-136199.6" *)
  reg _049_;
  (* src = "libresoc.v:136228.3-136252.6" *)
  reg [63:0] _050_;
  (* src = "libresoc.v:136144.3-136171.6" *)
  reg _051_;
  (* src = "libresoc.v:136200.3-136227.6" *)
  reg [7:0] _052_;
  (* src = "libresoc.v:136172.3-136199.6" *)
  reg _053_;
  (* src = "libresoc.v:136228.3-136252.6" *)
  reg [63:0] _054_;
  (* src = "libresoc.v:136106.18-136106.110" *)
  wire _055_;
  (* src = "libresoc.v:136112.18-136112.110" *)
  wire _056_;
  (* src = "libresoc.v:136117.18-136117.110" *)
  wire _057_;
  (* src = "libresoc.v:136120.17-136120.108" *)
  wire _058_;
  (* src = "libresoc.v:136123.18-136123.110" *)
  wire _059_;
  (* src = "libresoc.v:136124.18-136124.115" *)
  wire _060_;
  (* src = "libresoc.v:136126.18-136126.115" *)
  wire _061_;
  (* src = "libresoc.v:136105.18-136105.105" *)
  wire _062_;
  (* src = "libresoc.v:136108.18-136108.105" *)
  wire _063_;
  (* src = "libresoc.v:136109.17-136109.104" *)
  wire _064_;
  (* src = "libresoc.v:136111.18-136111.105" *)
  wire _065_;
  (* src = "libresoc.v:136114.18-136114.105" *)
  wire _066_;
  (* src = "libresoc.v:136116.18-136116.105" *)
  wire _067_;
  (* src = "libresoc.v:136119.18-136119.105" *)
  wire _068_;
  (* src = "libresoc.v:136122.18-136122.105" *)
  wire _069_;
  (* src = "libresoc.v:136125.18-136125.105" *)
  wire _070_;
  (* src = "libresoc.v:136127.18-136127.105" *)
  wire _071_;
  (* src = "libresoc.v:136129.17-136129.104" *)
  wire _072_;
  (* src = "libresoc.v:136104.17-136104.103" *)
  wire _073_;
  (* src = "libresoc.v:136107.18-136107.115" *)
  wire _074_;
  (* src = "libresoc.v:136110.18-136110.106" *)
  wire _075_;
  (* src = "libresoc.v:136113.18-136113.115" *)
  wire _076_;
  (* src = "libresoc.v:136115.18-136115.106" *)
  wire _077_;
  (* src = "libresoc.v:136118.18-136118.115" *)
  wire _078_;
  (* src = "libresoc.v:136121.18-136121.106" *)
  wire _079_;
  (* src = "libresoc.v:136128.17-136128.114" *)
  wire _080_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" *)
  reg a_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" *)
  input [47:0] a_pc_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" *)
  wire a_stall_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *)
  input a_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
  reg [44:0] f_badaddr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *)
  reg [44:0] \f_badaddr_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" *)
  output f_busy_o;
  reg f_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" *)
  reg f_fetch_err_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" *)
  reg \f_fetch_err_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" *)
  output [63:0] f_instr_o;
  reg [63:0] f_instr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" *)
  wire f_stall_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *)
  input f_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [44:0] ibus__adr;
  reg [44:0] ibus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  reg [44:0] \ibus__adr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__cyc;
  reg ibus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  reg \ibus__cyc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [63:0] ibus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [7:0] ibus__sel;
  reg [7:0] ibus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  reg [7:0] \ibus__sel$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__stb;
  reg ibus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  reg \ibus__stb$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *)
  reg [63:0] ibus_rdata;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *)
  reg [63:0] \ibus_rdata$next ;
  (* src = "libresoc.v:135989.7-135989.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
  input wb_icache_en;
  assign _055_ = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$11 ;
  assign _056_ = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$21 ;
  assign _057_ = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$31 ;
  assign _058_ = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$1 ;
  assign _059_ = a_valid_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) \$41 ;
  assign _060_ = ibus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) ibus__err;
  assign _061_ = ibus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *) ibus__err;
  assign _062_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
  assign _063_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i;
  assign _064_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
  assign _065_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
  assign _066_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i;
  assign _067_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
  assign _068_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i;
  assign _069_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" *) a_stall_i;
  assign _070_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) f_stall_i;
  assign _071_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" *) f_stall_i;
  assign _072_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) f_valid_i;
  assign _073_ = \$5  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$7 ;
  assign _074_ = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err;
  assign _075_ = \$15  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$17 ;
  assign _076_ = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err;
  assign _077_ = \$25  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$27 ;
  assign _078_ = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err;
  assign _079_ = \$35  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) \$37 ;
  assign _080_ = ibus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *) ibus__err;
  always @* begin
    if (\initial ) begin end
    _017_ = 1'h0;
  end
  always @* begin
      \initial  <= _017_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _020_ = 45'h000000000000;
  end
  always @* begin
  end
  initial begin
      f_badaddr_o <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      f_fetch_err_o <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = 45'h000000000000;
  end
  always @* begin
  end
  initial begin
      ibus__adr <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ibus__cyc <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      ibus__sel <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ibus__stb <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ibus_rdata <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \f_badaddr_o$next ;
  end
  always @(posedge clk) begin
      f_badaddr_o <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \f_fetch_err_o$next ;
  end
  always @(posedge clk) begin
      f_fetch_err_o <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \ibus__adr$next ;
  end
  always @(posedge clk) begin
      ibus__adr <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \ibus_rdata$next ;
  end
  always @(posedge clk) begin
      ibus_rdata <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \ibus__sel$next ;
  end
  always @(posedge clk) begin
      ibus__sel <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \ibus__stb$next ;
  end
  always @(posedge clk) begin
      ibus__stb <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \ibus__cyc$next ;
  end
  always @(posedge clk) begin
      ibus__cyc <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _051_;
    (* src = "libresoc.v:136145.5-136145.29" *)
    casez (\initial )
      /* src = "libresoc.v:136145.9-136145.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _027_ = _040_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *)
          casez ({ \$3 , ibus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _040_ = _047_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
                casez (\$9 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _047_ = 1'h0;
                    end
                  default:
                      _047_ = ibus__cyc;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _040_ = 1'h1;
              end
            default:
                _040_ = ibus__cyc;
          endcase
        end
      default:
          _027_ = ibus__cyc;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _051_ = 1'h0;
        end
      default:
          _051_ = _027_;
    endcase
  end
  always @* begin
      \ibus__cyc$next  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _053_;
    (* src = "libresoc.v:136173.5-136173.29" *)
    casez (\initial )
      /* src = "libresoc.v:136173.9-136173.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _031_ = _042_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *)
          casez ({ \$13 , ibus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _042_ = _049_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
                casez (\$19 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _049_ = 1'h0;
                    end
                  default:
                      _049_ = ibus__stb;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _042_ = 1'h1;
              end
            default:
                _042_ = ibus__stb;
          endcase
        end
      default:
          _031_ = ibus__stb;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _053_ = 1'h0;
        end
      default:
          _053_ = _031_;
    endcase
  end
  always @* begin
      \ibus__stb$next  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _052_;
    (* src = "libresoc.v:136201.5-136201.29" *)
    casez (\initial )
      /* src = "libresoc.v:136201.9-136201.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _029_ = _041_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *)
          casez ({ \$23 , ibus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _041_ = _048_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
                casez (\$29 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _048_ = 8'h00;
                    end
                  default:
                      _048_ = ibus__sel;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _041_ = 8'hff;
              end
            default:
                _041_ = ibus__sel;
          endcase
        end
      default:
          _029_ = ibus__sel;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _052_ = 8'h00;
        end
      default:
          _052_ = _029_;
    endcase
  end
  always @* begin
      \ibus__sel$next  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _054_;
    (* src = "libresoc.v:136229.5-136229.29" *)
    casez (\initial )
      /* src = "libresoc.v:136229.9-136229.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = _043_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *)
          casez ({ \$33 , ibus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _043_ = _050_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" *)
                casez (\$39 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _050_ = ibus__dat_r;
                    end
                  default:
                      _050_ = ibus_rdata;
                endcase
              end
            default:
                _043_ = ibus_rdata;
          endcase
        end
      default:
          _033_ = ibus_rdata;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _054_ = 64'h0000000000000000;
        end
      default:
          _054_ = _033_;
    endcase
  end
  always @* begin
      \ibus_rdata$next  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _046_;
    (* src = "libresoc.v:136254.5-136254.29" *)
    casez (\initial )
      /* src = "libresoc.v:136254.9-136254.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _025_ = _039_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" *)
          casez ({ \$43 , ibus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
                _039_ = ibus__adr;
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _039_ = a_pc_i[47:3];
              end
            default:
                _039_ = ibus__adr;
          endcase
        end
      default:
          _025_ = ibus__adr;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _046_ = 45'h000000000000;
        end
      default:
          _046_ = _025_;
    endcase
  end
  always @* begin
      \ibus__adr$next  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _045_;
    (* src = "libresoc.v:136277.5-136277.29" *)
    casez (\initial )
      /* src = "libresoc.v:136277.9-136277.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _022_ = _037_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *)
          casez ({ \$47 , \$45  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _037_ = 1'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _037_ = 1'h0;
              end
            default:
                _037_ = f_fetch_err_o;
          endcase
        end
      default:
          _022_ = f_fetch_err_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _045_ = 1'h0;
        end
      default:
          _045_ = _022_;
    endcase
  end
  always @* begin
      \f_fetch_err_o$next  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _044_;
    (* src = "libresoc.v:136300.5-136300.29" *)
    casez (\initial )
      /* src = "libresoc.v:136300.9-136300.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _019_ = _035_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" *)
          casez ({ \$51 , \$49  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _035_ = ibus__adr;
              end
            default:
                _035_ = f_badaddr_o;
          endcase
        end
      default:
          _019_ = f_badaddr_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _044_ = 45'h000000000000;
        end
      default:
          _044_ = _019_;
    endcase
  end
  always @* begin
      \f_badaddr_o$next  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _018_;
    (* src = "libresoc.v:136320.5-136320.29" *)
    casez (\initial )
      /* src = "libresoc.v:136320.9-136320.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _018_ = ibus__cyc;
        end
      default:
          _018_ = 1'h0;
    endcase
  end
  always @* begin
      a_busy_o <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _021_;
    (* src = "libresoc.v:136330.5-136330.29" *)
    casez (\initial )
      /* src = "libresoc.v:136330.9-136330.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _021_ = _036_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *)
          casez (f_fetch_err_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _036_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _036_ = ibus__cyc;
              end
          endcase
        end
      default:
          _021_ = 1'h0;
    endcase
  end
  always @* begin
      f_busy_o <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _024_;
    (* src = "libresoc.v:136348.5-136348.29" *)
    casez (\initial )
      /* src = "libresoc.v:136348.9-136348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:67" *)
    casez (wb_icache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _024_ = _038_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:96" *)
          casez (f_fetch_err_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _038_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _038_ = ibus_rdata;
              end
          endcase
        end
      default:
          _024_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      f_instr_o <= _006_;
  end
  assign \$9  = _073_;
  assign \$11  = _062_;
  assign \$13  = _055_;
  assign \$15  = _074_;
  assign \$17  = _063_;
  assign \$1  = _064_;
  assign \$19  = _075_;
  assign \$21  = _065_;
  assign \$23  = _056_;
  assign \$25  = _076_;
  assign \$27  = _066_;
  assign \$29  = _077_;
  assign \$31  = _067_;
  assign \$33  = _057_;
  assign \$35  = _078_;
  assign \$37  = _068_;
  assign \$3  = _058_;
  assign \$39  = _079_;
  assign \$41  = _069_;
  assign \$43  = _059_;
  assign \$45  = _060_;
  assign \$47  = _070_;
  assign \$49  = _061_;
  assign \$51  = _071_;
  assign \$5  = _080_;
  assign \$7  = _072_;
  assign a_stall_i = 1'h0;
  assign f_stall_i = 1'h0;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:136371.1-136698.10" *)
module \input (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \xer_ca$23 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:136661.3-136672.6" *)
  reg [63:0] _0_;
  (* src = "libresoc.v:136372.7-136372.20" *)
  reg _1_;
  (* src = "libresoc.v:136673.3-136691.6" *)
  reg [1:0] _2_;
  (* src = "libresoc.v:136661.3-136672.6" *)
  reg [63:0] _3_;
  (* src = "libresoc.v:136673.3-136691.6" *)
  reg [1:0] _4_;
  (* src = "libresoc.v:136660.18-136660.100" *)
  wire [63:0] _5_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
  wire [63:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
  reg [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \alu_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \alu_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \alu_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \alu_op__input_carry$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \alu_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \alu_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_out$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__write_cr0$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *)
  wire [63:0] b;
  (* src = "libresoc.v:136372.7-136372.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [1:0] \xer_ca$23 ;
  reg [1:0] \xer_ca$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$22 ;
  assign _5_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
  always @* begin
    if (\initial ) begin end
    _1_ = 1'h0;
  end
  always @* begin
      \initial  <= _1_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _3_;
    (* src = "libresoc.v:136662.5-136662.29" *)
    casez (\initial )
      /* src = "libresoc.v:136662.9-136662.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *)
    casez (alu_op__invert_in)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _3_ = \$24 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = ra;
        end
    endcase
  end
  always @* begin
      a <= _0_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:136674.5-136674.29" *)
    casez (\initial )
      /* src = "libresoc.v:136674.9-136674.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *)
    casez (alu_op__input_carry)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 2'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = xer_ca;
        end
      default:
          _4_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ca$23  <= _2_;
  end
  assign \$24  = _5_;
  assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2  } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$22  = xer_so;
  assign \rb$21  = rb;
  assign b = rb;
  assign \ra$20  = a;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:136702.1-137030.10" *)
module \input$113 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \ra$19 , \rb$20 , \rc$21 , \xer_so$22 , \xer_ca$23 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:136992.3-137003.6" *)
  reg [63:0] _0_;
  (* src = "libresoc.v:136703.7-136703.20" *)
  reg _1_;
  (* src = "libresoc.v:137004.3-137022.6" *)
  reg [1:0] _2_;
  (* src = "libresoc.v:136992.3-137003.6" *)
  reg [63:0] _3_;
  (* src = "libresoc.v:137004.3-137022.6" *)
  reg [1:0] _4_;
  (* src = "libresoc.v:136991.18-136991.100" *)
  wire [63:0] _5_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
  wire [63:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
  reg [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *)
  wire [63:0] b;
  (* src = "libresoc.v:136703.7-136703.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rc$21 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \sr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \sr_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \sr_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__input_cr$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \sr_op__insn$18 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \sr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [1:0] \xer_ca$23 ;
  reg [1:0] \xer_ca$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$22 ;
  assign _5_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
  always @* begin
    if (\initial ) begin end
    _1_ = 1'h0;
  end
  always @* begin
      \initial  <= _1_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _3_;
    (* src = "libresoc.v:136993.5-136993.29" *)
    casez (\initial )
      /* src = "libresoc.v:136993.9-136993.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *)
    casez (sr_op__invert_in)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _3_ = \$24 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _3_ = ra;
        end
    endcase
  end
  always @* begin
      a <= _0_;
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:137005.5-137005.29" *)
    casez (\initial )
      /* src = "libresoc.v:137005.9-137005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" *)
    casez (sr_op__input_carry)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _4_ = 2'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _4_ = 2'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _4_ = xer_ca;
        end
      default:
          _4_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ca$23  <= _2_;
  end
  assign \$24  = _5_;
  assign \rc$21  = rc;
  assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2  } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$22  = xer_so;
  assign \rb$20  = b;
  assign b = rb;
  assign \ra$19  = a;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:137034.1-137337.10" *)
module \input$50 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:137319.3-137330.6" *)
  reg [63:0] _0_;
  (* src = "libresoc.v:137035.7-137035.20" *)
  reg _1_;
  (* src = "libresoc.v:137319.3-137330.6" *)
  reg [63:0] _2_;
  (* src = "libresoc.v:137318.18-137318.100" *)
  wire [63:0] _3_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *)
  wire [63:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
  wire [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *)
  reg [63:0] b;
  (* src = "libresoc.v:137035.7-137035.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$22 ;
  assign _3_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" *) rb;
  always @* begin
    if (\initial ) begin end
    _1_ = 1'h0;
  end
  always @* begin
      \initial  <= _1_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _2_;
    (* src = "libresoc.v:137320.5-137320.29" *)
    casez (\initial )
      /* src = "libresoc.v:137320.9-137320.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" *)
    casez (logical_op__invert_in)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _2_ = \$23 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _2_ = rb;
        end
    endcase
  end
  always @* begin
      b <= _0_;
  end
  assign \$23  = _3_;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$22  = xer_so;
  assign \rb$21  = b;
  assign \ra$20  = a;
  assign a = ra;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:137341.1-137644.10" *)
module \input$78 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:137626.3-137637.6" *)
  reg [63:0] _0_;
  (* src = "libresoc.v:137342.7-137342.20" *)
  reg _1_;
  (* src = "libresoc.v:137626.3-137637.6" *)
  reg [63:0] _2_;
  (* src = "libresoc.v:137625.18-137625.100" *)
  wire [63:0] _3_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *)
  wire [63:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
  reg [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *)
  wire [63:0] b;
  (* src = "libresoc.v:137342.7-137342.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$22 ;
  assign _3_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" *) ra;
  always @* begin
    if (\initial ) begin end
    _1_ = 1'h0;
  end
  always @* begin
      \initial  <= _1_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _2_;
    (* src = "libresoc.v:137627.5-137627.29" *)
    casez (\initial )
      /* src = "libresoc.v:137627.9-137627.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" *)
    casez (logical_op__invert_in)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _2_ = \$23 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _2_ = ra;
        end
    endcase
  end
  always @* begin
      a <= _0_;
  end
  assign \$23  = _3_;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$22  = xer_so;
  assign \rb$21  = rb;
  assign b = rb;
  assign \ra$20  = a;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:137648.1-137904.10" *)
module \input$95 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , muxid);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" *)
  wire [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" *)
  wire [63:0] b;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$16 ;
  assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$16  = xer_so;
  assign \rb$15  = rb;
  assign b = rb;
  assign \ra$14  = a;
  assign a = ra;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.int" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:137908.1-138047.10" *)
module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [4:0] _02_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [4:0] _05_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [4:0] _06_;
  (* src = "libresoc.v:138013.3-138022.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:137909.7-137909.20" *)
  reg _08_;
  (* src = "libresoc.v:138023.3-138031.6" *)
  reg _09_;
  (* src = "libresoc.v:138000.3-138001.41" *)
  reg _10_;
  (* src = "libresoc.v:137944.7-137944.27" *)
  reg _11_;
  (* src = "libresoc.v:138004.3-138012.6" *)
  reg _12_;
  (* src = "libresoc.v:138002.3-138003.35" *)
  reg _13_;
  (* src = "libresoc.v:138032.3-138041.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [4:0] _15_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:137993.3-137997.6" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:138013.3-138022.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:138023.3-138031.6" *)
  reg _19_;
  (* src = "libresoc.v:138004.3-138012.6" *)
  reg _20_;
  (* src = "libresoc.v:137942.7-137942.23" *)
  reg _21_;
  (* src = "libresoc.v:138032.3-138041.6" *)
  reg [63:0] _22_;
  (* src = "libresoc.v:137998.26-137998.32" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:137999.30-137999.36" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [4:0] _25_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _27_;
  (* src = "libresoc.v:137991.13-137991.16" *)
  reg [4:0] _0_;
  (* src = "libresoc.v:137992.13-137992.16" *)
  reg [4:0] _1_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [4:0] dest1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] dest1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [4:0] dmi__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] dmi__data_o;
  reg [63:0] dmi__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dmi__ren;
  (* src = "libresoc.v:137909.7-137909.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [4:0] memory_r_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [4:0] \memory_r_addr$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [63:0] memory_r_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [63:0] \memory_r_data$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [4:0] memory_w_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [63:0] memory_w_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire memory_w_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [4:0] src1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] src1__data_o;
  reg [63:0] src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src1__ren;
  (* src = "libresoc.v:137956.14-137956.20" *)
  reg [63:0] memory [31:0];
  initial begin
    memory[0] = 64'h0000000000000000;
    memory[1] = 64'h0000000000000000;
    memory[2] = 64'h0000000000000000;
    memory[3] = 64'h0000000000000000;
    memory[4] = 64'h0000000000000000;
    memory[5] = 64'h0000000000000000;
    memory[6] = 64'h0000000000000000;
    memory[7] = 64'h0000000000000000;
    memory[8] = 64'h0000000000000000;
    memory[9] = 64'h0000000000000000;
    memory[10] = 64'h0000000000000000;
    memory[11] = 64'h0000000000000000;
    memory[12] = 64'h0000000000000000;
    memory[13] = 64'h0000000000000000;
    memory[14] = 64'h0000000000000000;
    memory[15] = 64'h0000000000000000;
    memory[16] = 64'h0000000000000000;
    memory[17] = 64'h0000000000000000;
    memory[18] = 64'h0000000000000000;
    memory[19] = 64'h0000000000000000;
    memory[20] = 64'h0000000000000000;
    memory[21] = 64'h0000000000000000;
    memory[22] = 64'h0000000000000000;
    memory[23] = 64'h0000000000000000;
    memory[24] = 64'h0000000000000000;
    memory[25] = 64'h0000000000000000;
    memory[26] = 64'h0000000000000000;
    memory[27] = 64'h0000000000000000;
    memory[28] = 64'h0000000000000000;
    memory[29] = 64'h0000000000000000;
    memory[30] = 64'h0000000000000000;
    memory[31] = 64'h0000000000000000;
  end
  assign _24_ = memory[_1_];
  assign _23_ = memory[_0_];
  always @* begin
    if (\initial ) begin end
  end
  always @* begin
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _08_ = 1'h0;
  end
  always @* begin
      \initial  <= _08_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$4  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = memory_r_addr;
    _06_ = \memory_r_addr$2 ;
    _02_ = _15_;
    _03_ = _16_;
    _04_ = _17_;
    (* src = "libresoc.v:137996.5-137996.61" *)
    casez (memory_w_en)
      /* src = "libresoc.v:137996.9-137996.20" */
      1'h1:
        begin
          _15_ = memory_w_addr;
          _16_ = memory_w_data;
          _17_ = 64'hffffffffffffffff;
        end
      default:
        begin
          _15_ = 5'hxx;
          _16_ = 64'hxxxxxxxxxxxxxxxx;
          _17_ = 64'h0000000000000000;
        end
    endcase
  end
  always @(posedge coresync_clk) begin
      _0_ <= _05_;
      _1_ <= _06_;
      _25_ <= _02_;
      _26_ <= _03_;
      _27_ <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \ren_delay$4$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$4  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _20_;
    (* src = "libresoc.v:138005.5-138005.29" *)
    casez (\initial )
      /* src = "libresoc.v:138005.9-138005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = 1'h0;
        end
      default:
          _20_ = dmi__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _18_;
    (* src = "libresoc.v:138014.5-138014.29" *)
    casez (\initial )
      /* src = "libresoc.v:138014.9-138014.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *)
    casez (ren_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = memory_r_data;
        end
      default:
          _18_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dmi__data_o <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _19_;
    (* src = "libresoc.v:138024.5-138024.29" *)
    casez (\initial )
      /* src = "libresoc.v:138024.9-138024.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _19_ = 1'h0;
        end
      default:
          _19_ = src1__ren;
    endcase
  end
  always @* begin
      \ren_delay$4$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _22_;
    (* src = "libresoc.v:138033.5-138033.29" *)
    casez (\initial )
      /* src = "libresoc.v:138033.9-138033.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *)
    casez (\ren_delay$4 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = \memory_r_data$3 ;
        end
      default:
          _22_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      src1__data_o <= _14_;
  end
  assign memory_r_data = _23_;
  assign \memory_r_data$3  = _24_;
  assign memory_w_data = dest1__data_i;
  assign memory_w_en = dest1__wen;
  assign memory_w_addr = dest1__addr;
  assign \memory_r_addr$2  = src1__addr;
  assign memory_r_addr = dmi__addr;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.jtag" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:138051.1-140636.10" *)
module jtag(dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, dmi0__dout, rst, wb_dcache_en, wb_icache_en, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, clk);
  reg \initial  = 0;
  (* src = "libresoc.v:140047.3-140073.6" *)
  reg _000_;
  (* src = "libresoc.v:139695.3-139710.6" *)
  reg _001_;
  (* src = "libresoc.v:140228.3-140272.6" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:139598.3-139599.41" *)
  reg [3:0] _003_;
  (* src = "libresoc.v:140326.3-140352.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:139594.3-139595.35" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:139897.3-139913.6" *)
  reg _006_;
  (* src = "libresoc.v:139626.3-139627.47" *)
  reg _007_;
  (* src = "libresoc.v:139914.3-139934.6" *)
  reg [7:0] _008_;
  (* src = "libresoc.v:139624.3-139625.47" *)
  reg [7:0] _009_;
  (* src = "libresoc.v:139879.3-139887.6" *)
  reg _010_;
  (* src = "libresoc.v:139630.3-139631.63" *)
  reg _011_;
  (* src = "libresoc.v:139888.3-139896.6" *)
  reg _012_;
  (* src = "libresoc.v:139628.3-139629.73" *)
  reg _013_;
  (* src = "libresoc.v:140353.3-140381.6" *)
  reg [63:0] _014_;
  (* src = "libresoc.v:139592.3-139593.45" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:139953.3-139969.6" *)
  reg [1:0] _016_;
  (* src = "libresoc.v:139618.3-139619.47" *)
  reg [1:0] _017_;
  (* src = "libresoc.v:139970.3-139990.6" *)
  reg [63:0] _018_;
  (* src = "libresoc.v:139616.3-139617.47" *)
  reg [63:0] _019_;
  (* src = "libresoc.v:139935.3-139943.6" *)
  reg _020_;
  (* src = "libresoc.v:139622.3-139623.63" *)
  reg _021_;
  (* src = "libresoc.v:139944.3-139952.6" *)
  reg _022_;
  (* src = "libresoc.v:139620.3-139621.73" *)
  reg _023_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _024_;
  (* src = "libresoc.v:139596.3-139597.45" *)
  reg [2:0] _025_;
  (* src = "libresoc.v:138657.13-138657.35" *)
  reg [2:0] _026_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _027_;
  (* src = "libresoc.v:139604.3-139605.35" *)
  reg [2:0] _028_;
  (* src = "libresoc.v:138052.7-138052.20" *)
  reg _029_;
  (* src = "libresoc.v:140431.3-140451.6" *)
  reg [129:0] _030_;
  (* src = "libresoc.v:139656.3-139657.27" *)
  reg [129:0] _031_;
  (* src = "libresoc.v:140413.3-140430.6" *)
  reg [129:0] _032_;
  (* src = "libresoc.v:139658.3-139659.27" *)
  reg [129:0] _033_;
  (* src = "libresoc.v:140074.3-140118.6" *)
  reg [29:0] _034_;
  (* src = "libresoc.v:139606.3-139607.41" *)
  reg [29:0] _035_;
  (* src = "libresoc.v:140172.3-140198.6" *)
  reg [31:0] _036_;
  (* src = "libresoc.v:139602.3-139603.45" *)
  reg [31:0] _037_;
  (* src = "libresoc.v:139785.3-139801.6" *)
  reg _038_;
  (* src = "libresoc.v:139642.3-139643.53" *)
  reg _039_;
  (* src = "libresoc.v:139802.3-139822.6" *)
  reg [29:0] _040_;
  (* src = "libresoc.v:139640.3-139641.53" *)
  reg [29:0] _041_;
  (* src = "libresoc.v:139767.3-139775.6" *)
  reg _042_;
  (* src = "libresoc.v:139646.3-139647.69" *)
  reg _043_;
  (* src = "libresoc.v:139776.3-139784.6" *)
  reg _044_;
  (* src = "libresoc.v:139644.3-139645.79" *)
  reg _045_;
  (* src = "libresoc.v:140199.3-140227.6" *)
  reg [31:0] _046_;
  (* src = "libresoc.v:139600.3-139601.51" *)
  reg [31:0] _047_;
  (* src = "libresoc.v:139841.3-139857.6" *)
  reg [1:0] _048_;
  (* src = "libresoc.v:139634.3-139635.53" *)
  reg [1:0] _049_;
  (* src = "libresoc.v:139858.3-139878.6" *)
  reg [31:0] _050_;
  (* src = "libresoc.v:139632.3-139633.53" *)
  reg [31:0] _051_;
  (* src = "libresoc.v:139823.3-139831.6" *)
  reg _052_;
  (* src = "libresoc.v:139638.3-139639.69" *)
  reg _053_;
  (* src = "libresoc.v:139832.3-139840.6" *)
  reg _054_;
  (* src = "libresoc.v:139636.3-139637.79" *)
  reg _055_;
  (* src = "libresoc.v:139729.3-139745.6" *)
  reg _056_;
  (* src = "libresoc.v:139650.3-139651.31" *)
  reg _057_;
  (* src = "libresoc.v:139746.3-139766.6" *)
  reg [2:0] _058_;
  (* src = "libresoc.v:139648.3-139649.31" *)
  reg [2:0] _059_;
  (* src = "libresoc.v:139711.3-139719.6" *)
  reg _060_;
  (* src = "libresoc.v:139654.3-139655.47" *)
  reg _061_;
  (* src = "libresoc.v:139720.3-139728.6" *)
  reg _062_;
  (* src = "libresoc.v:139652.3-139653.57" *)
  reg _063_;
  (* src = "libresoc.v:140403.3-140412.6" *)
  reg [2:0] _064_;
  (* src = "libresoc.v:140009.3-140025.6" *)
  reg _065_;
  (* src = "libresoc.v:139610.3-139611.31" *)
  reg _066_;
  (* src = "libresoc.v:140026.3-140046.6" *)
  reg [2:0] _067_;
  (* src = "libresoc.v:139608.3-139609.31" *)
  reg [2:0] _068_;
  (* src = "libresoc.v:139991.3-139999.6" *)
  reg _069_;
  (* src = "libresoc.v:139614.3-139615.47" *)
  reg _070_;
  (* src = "libresoc.v:140000.3-140008.6" *)
  reg _071_;
  (* src = "libresoc.v:139612.3-139613.57" *)
  reg _072_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _073_;
  (* src = "libresoc.v:139588.3-139589.41" *)
  reg _074_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _075_;
  (* src = "libresoc.v:139586.3-139587.41" *)
  reg _076_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _077_;
  (* src = "libresoc.v:139590.3-139591.37" *)
  reg _078_;
  (* src = "libresoc.v:140047.3-140073.6" *)
  reg _079_;
  (* src = "libresoc.v:139695.3-139710.6" *)
  reg _080_;
  (* src = "libresoc.v:140228.3-140272.6" *)
  reg [3:0] _081_;
  (* src = "libresoc.v:138570.13-138570.32" *)
  reg [3:0] _082_;
  (* src = "libresoc.v:140326.3-140352.6" *)
  reg [63:0] _083_;
  (* src = "libresoc.v:138575.14-138575.46" *)
  reg [63:0] _084_;
  (* src = "libresoc.v:139897.3-139913.6" *)
  reg _085_;
  (* src = "libresoc.v:138589.7-138589.29" *)
  reg _086_;
  (* src = "libresoc.v:139914.3-139934.6" *)
  reg [7:0] _087_;
  (* src = "libresoc.v:138597.13-138597.36" *)
  reg [7:0] _088_;
  (* src = "libresoc.v:139879.3-139887.6" *)
  reg _089_;
  (* src = "libresoc.v:138605.7-138605.37" *)
  reg _090_;
  (* src = "libresoc.v:139888.3-139896.6" *)
  reg _091_;
  (* src = "libresoc.v:138609.7-138609.42" *)
  reg _092_;
  (* src = "libresoc.v:140353.3-140381.6" *)
  reg [63:0] _093_;
  (* src = "libresoc.v:138613.14-138613.51" *)
  reg [63:0] _094_;
  (* src = "libresoc.v:139953.3-139969.6" *)
  reg [1:0] _095_;
  (* src = "libresoc.v:138619.13-138619.35" *)
  reg [1:0] _096_;
  (* src = "libresoc.v:139970.3-139990.6" *)
  reg [63:0] _097_;
  (* src = "libresoc.v:138627.14-138627.52" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:139935.3-139943.6" *)
  reg _099_;
  (* src = "libresoc.v:138635.7-138635.37" *)
  reg _100_;
  (* src = "libresoc.v:139944.3-139952.6" *)
  reg _101_;
  (* src = "libresoc.v:138639.7-138639.42" *)
  reg _102_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _103_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _104_;
  (* src = "libresoc.v:138655.13-138655.29" *)
  reg [2:0] _105_;
  (* src = "libresoc.v:140431.3-140451.6" *)
  reg [129:0] _106_;
  (* src = "libresoc.v:138855.15-138855.61" *)
  reg [129:0] _107_;
  (* src = "libresoc.v:140413.3-140430.6" *)
  reg [129:0] _108_;
  (* src = "libresoc.v:138867.15-138867.61" *)
  reg [129:0] _109_;
  (* src = "libresoc.v:140074.3-140118.6" *)
  reg [29:0] _110_;
  (* src = "libresoc.v:138876.14-138876.41" *)
  reg [29:0] _111_;
  (* src = "libresoc.v:140172.3-140198.6" *)
  reg [31:0] _112_;
  (* src = "libresoc.v:138885.14-138885.36" *)
  reg [31:0] _113_;
  (* src = "libresoc.v:139785.3-139801.6" *)
  reg _114_;
  (* src = "libresoc.v:138899.7-138899.32" *)
  reg _115_;
  (* src = "libresoc.v:139802.3-139822.6" *)
  reg [29:0] _116_;
  (* src = "libresoc.v:138907.14-138907.47" *)
  reg [29:0] _117_;
  (* src = "libresoc.v:139767.3-139775.6" *)
  reg _118_;
  (* src = "libresoc.v:138915.7-138915.40" *)
  reg _119_;
  (* src = "libresoc.v:139776.3-139784.6" *)
  reg _120_;
  (* src = "libresoc.v:138919.7-138919.45" *)
  reg _121_;
  (* src = "libresoc.v:140199.3-140227.6" *)
  reg [31:0] _122_;
  (* src = "libresoc.v:138923.14-138923.39" *)
  reg [31:0] _123_;
  (* src = "libresoc.v:139841.3-139857.6" *)
  reg [1:0] _124_;
  (* src = "libresoc.v:138929.13-138929.38" *)
  reg [1:0] _125_;
  (* src = "libresoc.v:139858.3-139878.6" *)
  reg [31:0] _126_;
  (* src = "libresoc.v:138937.14-138937.40" *)
  reg [31:0] _127_;
  (* src = "libresoc.v:139823.3-139831.6" *)
  reg _128_;
  (* src = "libresoc.v:138945.7-138945.40" *)
  reg _129_;
  (* src = "libresoc.v:139832.3-139840.6" *)
  reg _130_;
  (* src = "libresoc.v:138949.7-138949.45" *)
  reg _131_;
  (* src = "libresoc.v:139729.3-139745.6" *)
  reg _132_;
  (* src = "libresoc.v:139283.7-139283.21" *)
  reg _133_;
  (* src = "libresoc.v:139746.3-139766.6" *)
  reg [2:0] _134_;
  (* src = "libresoc.v:139291.13-139291.27" *)
  reg [2:0] _135_;
  (* src = "libresoc.v:139711.3-139719.6" *)
  reg _136_;
  (* src = "libresoc.v:139299.7-139299.29" *)
  reg _137_;
  (* src = "libresoc.v:139720.3-139728.6" *)
  reg _138_;
  (* src = "libresoc.v:139303.7-139303.34" *)
  reg _139_;
  (* src = "libresoc.v:140403.3-140412.6" *)
  reg [2:0] _140_;
  (* src = "libresoc.v:140009.3-140025.6" *)
  reg _141_;
  (* src = "libresoc.v:139313.7-139313.21" *)
  reg _142_;
  (* src = "libresoc.v:140026.3-140046.6" *)
  reg [2:0] _143_;
  (* src = "libresoc.v:139321.13-139321.27" *)
  reg [2:0] _144_;
  (* src = "libresoc.v:139991.3-139999.6" *)
  reg _145_;
  (* src = "libresoc.v:139329.7-139329.29" *)
  reg _146_;
  (* src = "libresoc.v:140000.3-140008.6" *)
  reg _147_;
  (* src = "libresoc.v:139333.7-139333.34" *)
  reg _148_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _149_;
  (* src = "libresoc.v:139338.7-139338.26" *)
  reg _150_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _151_;
  (* src = "libresoc.v:139343.7-139343.26" *)
  reg _152_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _153_;
  (* src = "libresoc.v:139347.7-139347.24" *)
  reg _154_;
  (* src = "libresoc.v:140228.3-140272.6" *)
  reg [3:0] _155_;
  (* src = "libresoc.v:140326.3-140352.6" *)
  reg [63:0] _156_;
  (* src = "libresoc.v:139897.3-139913.6" *)
  reg _157_;
  (* src = "libresoc.v:139914.3-139934.6" *)
  reg [7:0] _158_;
  (* src = "libresoc.v:140353.3-140381.6" *)
  reg [63:0] _159_;
  (* src = "libresoc.v:139953.3-139969.6" *)
  reg [1:0] _160_;
  (* src = "libresoc.v:139970.3-139990.6" *)
  reg [63:0] _161_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _162_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _163_;
  (* src = "libresoc.v:140431.3-140451.6" *)
  reg [129:0] _164_;
  (* src = "libresoc.v:140413.3-140430.6" *)
  reg [129:0] _165_;
  (* src = "libresoc.v:140074.3-140118.6" *)
  reg [29:0] _166_;
  (* src = "libresoc.v:140172.3-140198.6" *)
  reg [31:0] _167_;
  (* src = "libresoc.v:139785.3-139801.6" *)
  reg _168_;
  (* src = "libresoc.v:139802.3-139822.6" *)
  reg [29:0] _169_;
  (* src = "libresoc.v:140199.3-140227.6" *)
  reg [31:0] _170_;
  (* src = "libresoc.v:139841.3-139857.6" *)
  reg [1:0] _171_;
  (* src = "libresoc.v:139858.3-139878.6" *)
  reg [31:0] _172_;
  (* src = "libresoc.v:139729.3-139745.6" *)
  reg _173_;
  (* src = "libresoc.v:139746.3-139766.6" *)
  reg [2:0] _174_;
  (* src = "libresoc.v:140009.3-140025.6" *)
  reg _175_;
  (* src = "libresoc.v:140026.3-140046.6" *)
  reg [2:0] _176_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _177_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _178_;
  (* src = "libresoc.v:140382.3-140402.6" *)
  reg _179_;
  (* src = "libresoc.v:140228.3-140272.6" *)
  reg [3:0] _180_;
  (* src = "libresoc.v:140326.3-140352.6" *)
  reg [63:0] _181_;
  (* src = "libresoc.v:139914.3-139934.6" *)
  reg [7:0] _182_;
  (* src = "libresoc.v:140353.3-140381.6" *)
  reg [63:0] _183_;
  (* src = "libresoc.v:139970.3-139990.6" *)
  reg [63:0] _184_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _185_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _186_;
  (* src = "libresoc.v:140074.3-140118.6" *)
  reg [29:0] _187_;
  (* src = "libresoc.v:140172.3-140198.6" *)
  reg [31:0] _188_;
  (* src = "libresoc.v:139802.3-139822.6" *)
  reg [29:0] _189_;
  (* src = "libresoc.v:140199.3-140227.6" *)
  reg [31:0] _190_;
  (* src = "libresoc.v:139858.3-139878.6" *)
  reg [31:0] _191_;
  (* src = "libresoc.v:139746.3-139766.6" *)
  reg [2:0] _192_;
  (* src = "libresoc.v:140026.3-140046.6" *)
  reg [2:0] _193_;
  (* src = "libresoc.v:140228.3-140272.6" *)
  reg [3:0] _194_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _195_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _196_;
  (* src = "libresoc.v:140074.3-140118.6" *)
  reg [29:0] _197_;
  (* src = "libresoc.v:140273.3-140325.6" *)
  reg [2:0] _198_;
  (* src = "libresoc.v:140119.3-140171.6" *)
  reg [2:0] _199_;
  (* src = "libresoc.v:139548.19-139548.112" *)
  wire [30:0] _200_;
  (* src = "libresoc.v:139550.19-139550.112" *)
  wire [30:0] _201_;
  (* src = "libresoc.v:139556.19-139556.112" *)
  wire [4:0] _202_;
  (* src = "libresoc.v:139557.19-139557.112" *)
  wire [4:0] _203_;
  (* src = "libresoc.v:139394.18-139394.112" *)
  wire _204_;
  (* src = "libresoc.v:139461.18-139461.108" *)
  wire _205_;
  (* src = "libresoc.v:139472.18-139472.110" *)
  wire _206_;
  (* src = "libresoc.v:139474.19-139474.110" *)
  wire _207_;
  (* src = "libresoc.v:139477.19-139477.114" *)
  wire _208_;
  (* src = "libresoc.v:139479.19-139479.112" *)
  wire _209_;
  (* src = "libresoc.v:139481.19-139481.113" *)
  wire _210_;
  (* src = "libresoc.v:139484.19-139484.121" *)
  wire _211_;
  (* src = "libresoc.v:139487.19-139487.114" *)
  wire _212_;
  (* src = "libresoc.v:139489.19-139489.112" *)
  wire _213_;
  (* src = "libresoc.v:139491.19-139491.113" *)
  wire _214_;
  (* src = "libresoc.v:139493.19-139493.132" *)
  wire _215_;
  (* src = "libresoc.v:139498.19-139498.114" *)
  wire _216_;
  (* src = "libresoc.v:139500.19-139500.112" *)
  wire _217_;
  (* src = "libresoc.v:139502.19-139502.113" *)
  wire _218_;
  (* src = "libresoc.v:139504.19-139504.132" *)
  wire _219_;
  (* src = "libresoc.v:139508.19-139508.114" *)
  wire _220_;
  (* src = "libresoc.v:139510.19-139510.112" *)
  wire _221_;
  (* src = "libresoc.v:139512.19-139512.113" *)
  wire _222_;
  (* src = "libresoc.v:139514.19-139514.129" *)
  wire _223_;
  (* src = "libresoc.v:139520.19-139520.114" *)
  wire _224_;
  (* src = "libresoc.v:139522.19-139522.112" *)
  wire _225_;
  (* src = "libresoc.v:139524.19-139524.113" *)
  wire _226_;
  (* src = "libresoc.v:139526.19-139526.129" *)
  wire _227_;
  (* src = "libresoc.v:139530.19-139530.114" *)
  wire _228_;
  (* src = "libresoc.v:139532.19-139532.112" *)
  wire _229_;
  (* src = "libresoc.v:139534.19-139534.113" *)
  wire _230_;
  (* src = "libresoc.v:139536.19-139536.121" *)
  wire _231_;
  (* src = "libresoc.v:139539.18-139539.108" *)
  wire _232_;
  (* src = "libresoc.v:139549.18-139549.111" *)
  wire _233_;
  (* src = "libresoc.v:139575.17-139575.106" *)
  wire _234_;
  (* src = "libresoc.v:139350.17-139350.110" *)
  wire _235_;
  (* src = "libresoc.v:139361.18-139361.111" *)
  wire _236_;
  (* src = "libresoc.v:139372.18-139372.111" *)
  wire _237_;
  (* src = "libresoc.v:139405.17-139405.110" *)
  wire _238_;
  (* src = "libresoc.v:139406.18-139406.111" *)
  wire _239_;
  (* src = "libresoc.v:139417.18-139417.111" *)
  wire _240_;
  (* src = "libresoc.v:139439.18-139439.111" *)
  wire _241_;
  (* src = "libresoc.v:139468.19-139468.112" *)
  wire _242_;
  (* src = "libresoc.v:139469.19-139469.112" *)
  wire _243_;
  (* src = "libresoc.v:139471.19-139471.112" *)
  wire _244_;
  (* src = "libresoc.v:139475.19-139475.112" *)
  wire _245_;
  (* src = "libresoc.v:139483.18-139483.111" *)
  wire _246_;
  (* src = "libresoc.v:139485.19-139485.112" *)
  wire _247_;
  (* src = "libresoc.v:139494.18-139494.111" *)
  wire _248_;
  (* src = "libresoc.v:139495.19-139495.112" *)
  wire _249_;
  (* src = "libresoc.v:139496.19-139496.112" *)
  wire _250_;
  (* src = "libresoc.v:139506.19-139506.112" *)
  wire _251_;
  (* src = "libresoc.v:139515.19-139515.112" *)
  wire _252_;
  (* src = "libresoc.v:139516.17-139516.110" *)
  wire _253_;
  (* src = "libresoc.v:139517.18-139517.111" *)
  wire _254_;
  (* src = "libresoc.v:139518.19-139518.112" *)
  wire _255_;
  (* src = "libresoc.v:139527.19-139527.112" *)
  wire _256_;
  (* src = "libresoc.v:139537.19-139537.110" *)
  wire _257_;
  (* src = "libresoc.v:139538.19-139538.110" *)
  wire _258_;
  (* src = "libresoc.v:139541.19-139541.110" *)
  wire _259_;
  (* src = "libresoc.v:139543.19-139543.110" *)
  wire _260_;
  (* src = "libresoc.v:139545.19-139545.110" *)
  wire _261_;
  (* src = "libresoc.v:139547.19-139547.110" *)
  wire _262_;
  (* src = "libresoc.v:139552.19-139552.116" *)
  wire _263_;
  (* src = "libresoc.v:139553.19-139553.116" *)
  wire _264_;
  (* src = "libresoc.v:139555.19-139555.116" *)
  wire _265_;
  (* src = "libresoc.v:139558.18-139558.111" *)
  wire _266_;
  (* src = "libresoc.v:139559.18-139559.111" *)
  wire _267_;
  (* src = "libresoc.v:139551.19-139551.106" *)
  wire [7:0] _268_;
  (* src = "libresoc.v:139476.19-139476.109" *)
  wire _269_;
  (* src = "libresoc.v:139478.19-139478.109" *)
  wire _270_;
  (* src = "libresoc.v:139480.19-139480.109" *)
  wire _271_;
  (* src = "libresoc.v:139486.19-139486.120" *)
  wire _272_;
  (* src = "libresoc.v:139488.19-139488.120" *)
  wire _273_;
  (* src = "libresoc.v:139490.19-139490.120" *)
  wire _274_;
  (* src = "libresoc.v:139497.19-139497.120" *)
  wire _275_;
  (* src = "libresoc.v:139499.19-139499.120" *)
  wire _276_;
  (* src = "libresoc.v:139501.19-139501.120" *)
  wire _277_;
  (* src = "libresoc.v:139507.19-139507.117" *)
  wire _278_;
  (* src = "libresoc.v:139509.19-139509.117" *)
  wire _279_;
  (* src = "libresoc.v:139511.19-139511.117" *)
  wire _280_;
  (* src = "libresoc.v:139519.19-139519.117" *)
  wire _281_;
  (* src = "libresoc.v:139521.19-139521.117" *)
  wire _282_;
  (* src = "libresoc.v:139523.19-139523.117" *)
  wire _283_;
  (* src = "libresoc.v:139529.19-139529.109" *)
  wire _284_;
  (* src = "libresoc.v:139531.19-139531.109" *)
  wire _285_;
  (* src = "libresoc.v:139533.19-139533.109" *)
  wire _286_;
  (* src = "libresoc.v:139482.19-139482.110" *)
  wire _287_;
  (* src = "libresoc.v:139492.19-139492.121" *)
  wire _288_;
  (* src = "libresoc.v:139503.19-139503.121" *)
  wire _289_;
  (* src = "libresoc.v:139513.19-139513.118" *)
  wire _290_;
  (* src = "libresoc.v:139525.19-139525.118" *)
  wire _291_;
  (* src = "libresoc.v:139535.19-139535.110" *)
  wire _292_;
  (* src = "libresoc.v:139546.19-139546.100" *)
  wire _293_;
  (* src = "libresoc.v:139383.18-139383.104" *)
  wire _294_;
  (* src = "libresoc.v:139428.18-139428.104" *)
  wire _295_;
  (* src = "libresoc.v:139450.18-139450.104" *)
  wire _296_;
  (* src = "libresoc.v:139470.19-139470.107" *)
  wire _297_;
  (* src = "libresoc.v:139473.19-139473.107" *)
  wire _298_;
  (* src = "libresoc.v:139505.18-139505.104" *)
  wire _299_;
  (* src = "libresoc.v:139528.18-139528.104" *)
  wire _300_;
  (* src = "libresoc.v:139540.19-139540.107" *)
  wire _301_;
  (* src = "libresoc.v:139542.19-139542.107" *)
  wire _302_;
  (* src = "libresoc.v:139544.19-139544.107" *)
  wire _303_;
  (* src = "libresoc.v:139554.19-139554.107" *)
  wire _304_;
  (* src = "libresoc.v:139564.17-139564.101" *)
  wire _305_;
  (* src = "libresoc.v:139551.19-139551.106" *)
  wire [7:0] _306_;
  (* src = "libresoc.v:139351.18-139351.132" *)
  wire _307_;
  (* src = "libresoc.v:139352.19-139352.134" *)
  wire _308_;
  (* src = "libresoc.v:139353.19-139353.134" *)
  wire _309_;
  (* src = "libresoc.v:139354.19-139354.133" *)
  wire _310_;
  (* src = "libresoc.v:139355.19-139355.134" *)
  wire _311_;
  (* src = "libresoc.v:139356.19-139356.132" *)
  wire _312_;
  (* src = "libresoc.v:139357.19-139357.132" *)
  wire _313_;
  (* src = "libresoc.v:139358.19-139358.132" *)
  wire _314_;
  (* src = "libresoc.v:139359.19-139359.132" *)
  wire _315_;
  (* src = "libresoc.v:139360.19-139360.132" *)
  wire _316_;
  (* src = "libresoc.v:139362.19-139362.132" *)
  wire _317_;
  (* src = "libresoc.v:139363.19-139363.132" *)
  wire _318_;
  (* src = "libresoc.v:139364.19-139364.132" *)
  wire _319_;
  (* src = "libresoc.v:139365.19-139365.132" *)
  wire _320_;
  (* src = "libresoc.v:139366.19-139366.132" *)
  wire _321_;
  (* src = "libresoc.v:139367.19-139367.133" *)
  wire _322_;
  (* src = "libresoc.v:139368.19-139368.133" *)
  wire _323_;
  (* src = "libresoc.v:139369.19-139369.134" *)
  wire _324_;
  (* src = "libresoc.v:139370.19-139370.132" *)
  wire _325_;
  (* src = "libresoc.v:139371.19-139371.134" *)
  wire _326_;
  (* src = "libresoc.v:139373.19-139373.134" *)
  wire _327_;
  (* src = "libresoc.v:139374.19-139374.133" *)
  wire _328_;
  (* src = "libresoc.v:139375.19-139375.133" *)
  wire _329_;
  (* src = "libresoc.v:139376.19-139376.133" *)
  wire _330_;
  (* src = "libresoc.v:139377.19-139377.133" *)
  wire _331_;
  (* src = "libresoc.v:139378.19-139378.133" *)
  wire _332_;
  (* src = "libresoc.v:139379.19-139379.133" *)
  wire _333_;
  (* src = "libresoc.v:139380.19-139380.134" *)
  wire _334_;
  (* src = "libresoc.v:139381.19-139381.133" *)
  wire _335_;
  (* src = "libresoc.v:139382.19-139382.134" *)
  wire _336_;
  (* src = "libresoc.v:139384.19-139384.134" *)
  wire _337_;
  (* src = "libresoc.v:139385.19-139385.133" *)
  wire _338_;
  (* src = "libresoc.v:139386.19-139386.134" *)
  wire _339_;
  (* src = "libresoc.v:139387.19-139387.135" *)
  wire _340_;
  (* src = "libresoc.v:139388.19-139388.134" *)
  wire _341_;
  (* src = "libresoc.v:139389.19-139389.135" *)
  wire _342_;
  (* src = "libresoc.v:139390.19-139390.135" *)
  wire _343_;
  (* src = "libresoc.v:139391.19-139391.134" *)
  wire _344_;
  (* src = "libresoc.v:139392.19-139392.135" *)
  wire _345_;
  (* src = "libresoc.v:139393.19-139393.135" *)
  wire _346_;
  (* src = "libresoc.v:139395.19-139395.134" *)
  wire _347_;
  (* src = "libresoc.v:139396.19-139396.135" *)
  wire _348_;
  (* src = "libresoc.v:139397.19-139397.135" *)
  wire _349_;
  (* src = "libresoc.v:139398.19-139398.134" *)
  wire _350_;
  (* src = "libresoc.v:139399.19-139399.135" *)
  wire _351_;
  (* src = "libresoc.v:139400.19-139400.135" *)
  wire _352_;
  (* src = "libresoc.v:139401.19-139401.134" *)
  wire _353_;
  (* src = "libresoc.v:139402.19-139402.135" *)
  wire _354_;
  (* src = "libresoc.v:139403.19-139403.135" *)
  wire _355_;
  (* src = "libresoc.v:139404.19-139404.134" *)
  wire _356_;
  (* src = "libresoc.v:139407.19-139407.135" *)
  wire _357_;
  (* src = "libresoc.v:139408.19-139408.133" *)
  wire _358_;
  (* src = "libresoc.v:139409.19-139409.132" *)
  wire _359_;
  (* src = "libresoc.v:139410.19-139410.133" *)
  wire _360_;
  (* src = "libresoc.v:139411.19-139411.133" *)
  wire _361_;
  (* src = "libresoc.v:139412.19-139412.132" *)
  wire _362_;
  (* src = "libresoc.v:139413.19-139413.133" *)
  wire _363_;
  (* src = "libresoc.v:139414.19-139414.134" *)
  wire _364_;
  (* src = "libresoc.v:139415.19-139415.133" *)
  wire _365_;
  (* src = "libresoc.v:139416.19-139416.134" *)
  wire _366_;
  (* src = "libresoc.v:139418.19-139418.134" *)
  wire _367_;
  (* src = "libresoc.v:139419.19-139419.133" *)
  wire _368_;
  (* src = "libresoc.v:139420.19-139420.134" *)
  wire _369_;
  (* src = "libresoc.v:139421.19-139421.134" *)
  wire _370_;
  (* src = "libresoc.v:139422.19-139422.133" *)
  wire _371_;
  (* src = "libresoc.v:139423.19-139423.134" *)
  wire _372_;
  (* src = "libresoc.v:139424.19-139424.134" *)
  wire _373_;
  (* src = "libresoc.v:139425.19-139425.133" *)
  wire _374_;
  (* src = "libresoc.v:139426.19-139426.134" *)
  wire _375_;
  (* src = "libresoc.v:139427.19-139427.134" *)
  wire _376_;
  (* src = "libresoc.v:139429.19-139429.133" *)
  wire _377_;
  (* src = "libresoc.v:139430.19-139430.134" *)
  wire _378_;
  (* src = "libresoc.v:139431.19-139431.134" *)
  wire _379_;
  (* src = "libresoc.v:139432.19-139432.133" *)
  wire _380_;
  (* src = "libresoc.v:139433.19-139433.134" *)
  wire _381_;
  (* src = "libresoc.v:139434.19-139434.133" *)
  wire _382_;
  (* src = "libresoc.v:139435.19-139435.133" *)
  wire _383_;
  (* src = "libresoc.v:139436.19-139436.134" *)
  wire _384_;
  (* src = "libresoc.v:139437.19-139437.134" *)
  wire _385_;
  (* src = "libresoc.v:139438.19-139438.133" *)
  wire _386_;
  (* src = "libresoc.v:139440.19-139440.134" *)
  wire _387_;
  (* src = "libresoc.v:139441.19-139441.134" *)
  wire _388_;
  (* src = "libresoc.v:139442.19-139442.133" *)
  wire _389_;
  (* src = "libresoc.v:139443.19-139443.134" *)
  wire _390_;
  (* src = "libresoc.v:139444.19-139444.134" *)
  wire _391_;
  (* src = "libresoc.v:139445.19-139445.133" *)
  wire _392_;
  (* src = "libresoc.v:139446.19-139446.134" *)
  wire _393_;
  (* src = "libresoc.v:139447.19-139447.134" *)
  wire _394_;
  (* src = "libresoc.v:139448.19-139448.133" *)
  wire _395_;
  (* src = "libresoc.v:139449.19-139449.134" *)
  wire _396_;
  (* src = "libresoc.v:139451.19-139451.134" *)
  wire _397_;
  (* src = "libresoc.v:139452.19-139452.133" *)
  wire _398_;
  (* src = "libresoc.v:139453.19-139453.134" *)
  wire _399_;
  (* src = "libresoc.v:139454.19-139454.134" *)
  wire _400_;
  (* src = "libresoc.v:139455.19-139455.133" *)
  wire _401_;
  (* src = "libresoc.v:139456.19-139456.134" *)
  wire _402_;
  (* src = "libresoc.v:139457.19-139457.134" *)
  wire _403_;
  (* src = "libresoc.v:139458.19-139458.133" *)
  wire _404_;
  (* src = "libresoc.v:139459.19-139459.134" *)
  wire _405_;
  (* src = "libresoc.v:139460.19-139460.135" *)
  wire _406_;
  (* src = "libresoc.v:139462.19-139462.134" *)
  wire _407_;
  (* src = "libresoc.v:139463.19-139463.135" *)
  wire _408_;
  (* src = "libresoc.v:139464.19-139464.134" *)
  wire _409_;
  (* src = "libresoc.v:139465.19-139465.133" *)
  wire _410_;
  (* src = "libresoc.v:139466.19-139466.133" *)
  wire _411_;
  (* src = "libresoc.v:139467.19-139467.133" *)
  wire _412_;
  (* src = "libresoc.v:139560.18-139560.132" *)
  wire _413_;
  (* src = "libresoc.v:139561.18-139561.133" *)
  wire _414_;
  (* src = "libresoc.v:139562.18-139562.133" *)
  wire _415_;
  (* src = "libresoc.v:139563.18-139563.134" *)
  wire _416_;
  (* src = "libresoc.v:139565.18-139565.131" *)
  wire _417_;
  (* src = "libresoc.v:139566.18-139566.132" *)
  wire _418_;
  (* src = "libresoc.v:139567.18-139567.131" *)
  wire _419_;
  (* src = "libresoc.v:139568.18-139568.132" *)
  wire _420_;
  (* src = "libresoc.v:139569.18-139569.132" *)
  wire _421_;
  (* src = "libresoc.v:139570.18-139570.131" *)
  wire _422_;
  (* src = "libresoc.v:139571.18-139571.133" *)
  wire _423_;
  (* src = "libresoc.v:139572.18-139572.133" *)
  wire _424_;
  (* src = "libresoc.v:139573.18-139573.132" *)
  wire _425_;
  (* src = "libresoc.v:139574.18-139574.133" *)
  wire _426_;
  (* src = "libresoc.v:139576.18-139576.133" *)
  wire _427_;
  (* src = "libresoc.v:139577.18-139577.132" *)
  wire _428_;
  (* src = "libresoc.v:139578.18-139578.133" *)
  wire _429_;
  (* src = "libresoc.v:139579.18-139579.133" *)
  wire _430_;
  (* src = "libresoc.v:139580.18-139580.132" *)
  wire _431_;
  (* src = "libresoc.v:139581.18-139581.133" *)
  wire _432_;
  (* src = "libresoc.v:139582.18-139582.133" *)
  wire _433_;
  (* src = "libresoc.v:139583.18-139583.132" *)
  wire _434_;
  (* src = "libresoc.v:139584.18-139584.133" *)
  wire _435_;
  (* src = "libresoc.v:139585.18-139585.133" *)
  wire _436_;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$125 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$131 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$137 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$139 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$141 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$143 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$145 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$147 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$149 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$151 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$153 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$155 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$157 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$159 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$161 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$163 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$165 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$167 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$169 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$171 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$173 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$175 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$177 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$179 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$181 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$183 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$185 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$187 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$189 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$191 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$193 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$195 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$197 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$199 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$201 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$203 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$205 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$207 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$209 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$211 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$213 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$215 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$217 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$219 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$221 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$223 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$225 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$227 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$229 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$231 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$233 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$235 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$237 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$239 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$241 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$243 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$245 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$247 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$249 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$251 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$253 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$255 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$257 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$259 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$261 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$263 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$265 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$267 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$269 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$271 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$273 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$275 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$277 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$279 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$281 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$283 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$285 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$287 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$289 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$291 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$293 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$295 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$297 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$299 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$301 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$303 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *)
  wire \$305 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *)
  wire \$307 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *)
  wire \$309 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$311 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$313 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$315 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *)
  wire \$317 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$319 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$321 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$323 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$325 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$327 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$329 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$331 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$333 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$335 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$337 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$339 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$341 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$343 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$345 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$347 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$349 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$351 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$353 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$355 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$357 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$359 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$361 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$363 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$365 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$367 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$369 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$371 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$373 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$375 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$377 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$379 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$381 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$383 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$385 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$387 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$389 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$391 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$393 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$395 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$397 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$399 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$401 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$403 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$405 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$407 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$409 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$411 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$413 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$415 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *)
  wire \$417 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$419 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *)
  wire \$421 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$423 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *)
  wire \$425 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$427 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *)
  wire \$429 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$431 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
  wire \$433 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *)
  wire \$435 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *)
  wire \$437 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *)
  wire \$439 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *)
  wire \$441 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *)
  wire \$443 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *)
  wire \$445 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *)
  wire \$447 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *)
  wire \$449 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *)
  wire \$450 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *)
  wire \$453 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *)
  wire [30:0] \$455 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *)
  wire [30:0] \$456 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *)
  wire [30:0] \$458 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *)
  wire [30:0] \$459 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  wire [7:0] \$461 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *)
  wire \$464 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *)
  wire \$466 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *)
  wire \$468 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *)
  wire \$470 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *)
  wire [4:0] \$472 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *)
  wire [4:0] \$473 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *)
  wire [4:0] \$475 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *)
  wire [4:0] \$476 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tck;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tdi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  output TAP_bus__tdo;
  reg TAP_bus__tdo;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tms;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" *)
  reg TAP_tdo;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" *)
  wire _fsm_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:23" *)
  wire _fsm_isdr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:22" *)
  wire _fsm_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:25" *)
  wire _fsm_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" *)
  wire _fsm_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:225" *)
  wire _idblock_TAP_id_tdo;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" *)
  wire _idblock_id_bypass;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:374" *)
  wire _idblock_select_id;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" *)
  wire [3:0] _irblock_ir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" *)
  wire _irblock_tdo;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  input dmi0__ack_o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  output [3:0] dmi0__addr_i;
  reg [3:0] dmi0__addr_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg [3:0] \dmi0__addr_i$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  output [63:0] dmi0__din;
  reg [63:0] dmi0__din;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg [63:0] \dmi0__din$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  input [63:0] dmi0__dout;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  output dmi0__req_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  output dmi0__we_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *)
  wire [7:0] dmi0_addrsr__i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *)
  wire [7:0] dmi0_addrsr__o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *)
  reg dmi0_addrsr__oe;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:471" *)
  reg \dmi0_addrsr__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire dmi0_addrsr_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire dmi0_addrsr_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [7:0] dmi0_addrsr_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [7:0] \dmi0_addrsr_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire dmi0_addrsr_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire dmi0_addrsr_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg dmi0_addrsr_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \dmi0_addrsr_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg dmi0_addrsr_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \dmi0_addrsr_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *)
  reg [63:0] dmi0_datasr__i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *)
  reg [63:0] \dmi0_datasr__i$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *)
  wire [63:0] dmi0_datasr__o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *)
  reg [1:0] dmi0_datasr__oe;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:473" *)
  reg [1:0] \dmi0_datasr__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire dmi0_datasr_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire [1:0] dmi0_datasr_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [63:0] dmi0_datasr_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [63:0] \dmi0_datasr_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire dmi0_datasr_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire dmi0_datasr_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg dmi0_datasr_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \dmi0_datasr_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg dmi0_datasr_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \dmi0_datasr_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
  reg [2:0] fsm_state;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
  reg [2:0] \fsm_state$463 ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
  reg [2:0] \fsm_state$463$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
  reg [2:0] \fsm_state$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__oe;
  (* src = "libresoc.v:138052.7-138052.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *)
  reg [129:0] io_bd;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" *)
  reg [129:0] \io_bd$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" *)
  wire io_bd2core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" *)
  wire io_bd2io;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:391" *)
  wire io_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" *)
  wire io_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" *)
  reg [129:0] io_sr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" *)
  reg [129:0] \io_sr$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" *)
  wire io_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input jtag_wb__ack;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [29:0] jtag_wb__adr;
  reg [29:0] jtag_wb__adr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  reg [29:0] \jtag_wb__adr$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input [31:0] jtag_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [31:0] jtag_wb__dat_w;
  reg [31:0] jtag_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  reg [31:0] \jtag_wb__dat_w$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [3:0] jtag_wb__sel;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__stb;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__we;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *)
  wire [29:0] jtag_wb_addrsr__i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *)
  wire [29:0] jtag_wb_addrsr__o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *)
  reg jtag_wb_addrsr__oe;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" *)
  reg \jtag_wb_addrsr__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire jtag_wb_addrsr_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire jtag_wb_addrsr_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [29:0] jtag_wb_addrsr_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [29:0] \jtag_wb_addrsr_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire jtag_wb_addrsr_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire jtag_wb_addrsr_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg jtag_wb_addrsr_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \jtag_wb_addrsr_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg jtag_wb_addrsr_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \jtag_wb_addrsr_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *)
  reg [31:0] jtag_wb_datasr__i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *)
  reg [31:0] \jtag_wb_datasr__i$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *)
  wire [31:0] jtag_wb_datasr__o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *)
  reg [1:0] jtag_wb_datasr__oe;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:735" *)
  reg [1:0] \jtag_wb_datasr__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire jtag_wb_datasr_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire [1:0] jtag_wb_datasr_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [31:0] jtag_wb_datasr_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [31:0] \jtag_wb_datasr_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire jtag_wb_datasr_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire jtag_wb_datasr_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg jtag_wb_datasr_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \jtag_wb_datasr_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg jtag_wb_datasr_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \jtag_wb_datasr_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_clk__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_clk__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_miso__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_miso__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_mosi__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_mosi__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_scl__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_scl__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__oe;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
  wire negjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *)
  wire negjtag_rst;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  wire posjtag_clk;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" *)
  wire posjtag_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cas_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cas_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cke__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cke__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_clock__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_clock__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ras_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ras_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_we_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_we_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
  wire [2:0] sr0__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
  wire [2:0] sr0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
  reg sr0__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:81" *)
  reg \sr0__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire sr0_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire sr0_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [2:0] sr0_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [2:0] \sr0_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire sr0_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire sr0_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg sr0_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \sr0_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg sr0_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \sr0_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
  reg [2:0] sr5__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
  wire sr5__ie;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
  wire [2:0] sr5__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
  reg sr5__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *)
  reg \sr5__oe$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:646" *)
  wire sr5_capture;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:645" *)
  wire sr5_isir;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [2:0] sr5_reg;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:642" *)
  reg [2:0] \sr5_reg$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:647" *)
  wire sr5_shift;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:648" *)
  wire sr5_update;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg sr5_update_core;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:660" *)
  reg \sr5_update_core$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg sr5_update_core_prev;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" *)
  reg \sr5_update_core_prev$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  output wb_dcache_en;
  reg wb_dcache_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  reg \wb_dcache_en$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
  output wb_icache_en;
  reg wb_icache_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
  reg \wb_icache_en$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:97" *)
  reg wb_sram_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:97" *)
  reg \wb_sram_en$next ;
  assign _200_ = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" *) 1'h1;
  assign _201_ = jtag_wb__adr + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" *) 1'h1;
  assign _202_ = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" *) 1'h1;
  assign _203_ = dmi0__addr_i + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" *) 1'h1;
  assign _204_ = \$15  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" *) _fsm_capture;
  assign _205_ = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$27 ;
  assign _206_ = \$29  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" *) _fsm_shift;
  assign _207_ = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$319 ;
  assign _208_ = \$325  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _209_ = \$329  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _210_ = \$333  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _211_ = sr0_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$337 ;
  assign _212_ = \$343  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _213_ = \$347  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _214_ = \$351  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _215_ = jtag_wb_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$355 ;
  assign _216_ = \$363  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _217_ = \$367  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _218_ = \$371  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _219_ = jtag_wb_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$375 ;
  assign _220_ = \$381  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _221_ = \$385  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _222_ = \$389  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _223_ = dmi0_addrsr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$393 ;
  assign _224_ = \$401  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _225_ = \$405  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _226_ = \$409  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _227_ = dmi0_datasr_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$413 ;
  assign _228_ = \$419  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) _fsm_capture;
  assign _229_ = \$423  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) _fsm_shift;
  assign _230_ = \$427  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) _fsm_update;
  assign _231_ = sr5_update_core_prev & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) \$431 ;
  assign _232_ = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$41 ;
  assign _233_ = \$43  & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" *) _fsm_update;
  assign _234_ = _fsm_isdr & (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$5 ;
  assign _235_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" *) 4'hf;
  assign _236_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0;
  assign _237_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2;
  assign _238_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 1'h1;
  assign _239_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0;
  assign _240_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2;
  assign _241_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2;
  assign _242_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0;
  assign _243_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2;
  assign _244_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2;
  assign _245_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h4;
  assign _246_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 1'h0;
  assign _247_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h5;
  assign _248_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) 2'h2;
  assign _249_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h6;
  assign _250_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 3'h7;
  assign _251_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h8;
  assign _252_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'h9;
  assign _253_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) 4'hf;
  assign _254_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" *) 2'h2;
  assign _255_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'ha;
  assign _256_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" *) 4'hb;
  assign _257_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 1'h1;
  assign _258_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h2;
  assign _259_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) 2'h3;
  assign _260_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) 3'h4;
  assign _261_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) 1'h0;
  assign _262_ = fsm_state == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:801" *) 2'h2;
  assign _263_ = \fsm_state$463  == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 1'h1;
  assign _264_ = \fsm_state$463  == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) 2'h2;
  assign _265_ = \fsm_state$463  == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" *) 2'h2;
  assign _266_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" *) 1'h0;
  assign _267_ = _irblock_ir == (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" *) 1'h0;
  assign _268_ = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) dmi0__addr_i;
  assign _269_ = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _270_ = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _271_ = sr0_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _272_ = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _273_ = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _274_ = jtag_wb_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _275_ = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _276_ = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _277_ = jtag_wb_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _278_ = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _279_ = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _280_ = dmi0_addrsr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _281_ = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _282_ = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _283_ = dmi0_datasr_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _284_ = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" *) 1'h0;
  assign _285_ = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" *) 1'h0;
  assign _286_ = sr5_isir != (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" *) 1'h0;
  assign _287_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr0_update_core;
  assign _288_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_addrsr_update_core;
  assign _289_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) jtag_wb_datasr_update_core;
  assign _290_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_addrsr_update_core;
  assign _291_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) dmi0_datasr_update_core;
  assign _292_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *) sr5_update_core;
  assign _293_ = ~ (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:800" *) \$450 ;
  assign _294_ = \$11  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$13 ;
  assign _295_ = \$19  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$21 ;
  assign _296_ = \$23  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$25 ;
  assign _297_ = \$311  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$313 ;
  assign _298_ = \$315  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$317 ;
  assign _299_ = \$33  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" *) \$35 ;
  assign _300_ = \$37  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" *) \$39 ;
  assign _301_ = \$435  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$437 ;
  assign _302_ = \$439  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:797" *) \$441 ;
  assign _303_ = \$443  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:798" *) \$445 ;
  assign _304_ = \$464  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" *) \$466 ;
  assign _305_ = \$1  | (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" *) \$3 ;
  assign _306_ = + (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) _268_;
  assign _307_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[24] : sdr_dq_6__core__o;
  assign _308_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[25] : sdr_dq_6__core__oe;
  assign _309_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[26] : sdr_dq_7__pad__i;
  assign _310_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[27] : sdr_dq_7__core__o;
  assign _311_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[28] : sdr_dq_7__core__oe;
  assign _312_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[29] : sdr_a_0__core__o;
  assign _313_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[30] : sdr_a_1__core__o;
  assign _314_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[31] : sdr_a_2__core__o;
  assign _315_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[32] : sdr_a_3__core__o;
  assign _316_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[33] : sdr_a_4__core__o;
  assign _317_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[34] : sdr_a_5__core__o;
  assign _318_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[35] : sdr_a_6__core__o;
  assign _319_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[36] : sdr_a_7__core__o;
  assign _320_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[37] : sdr_a_8__core__o;
  assign _321_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[38] : sdr_a_9__core__o;
  assign _322_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[39] : sdr_ba_0__core__o;
  assign _323_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[40] : sdr_ba_1__core__o;
  assign _324_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[41] : sdr_clock__core__o;
  assign _325_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[42] : sdr_cke__core__o;
  assign _326_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[43] : sdr_ras_n__core__o;
  assign _327_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[44] : sdr_cas_n__core__o;
  assign _328_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[45] : sdr_we_n__core__o;
  assign _329_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[46] : sdr_cs_n__core__o;
  assign _330_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[47] : sdr_a_10__core__o;
  assign _331_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[48] : sdr_a_11__core__o;
  assign _332_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[49] : sdr_a_12__core__o;
  assign _333_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[50] : sdr_dm_1__core__o;
  assign _334_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[51] : sdr_dq_8__pad__i;
  assign _335_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[52] : sdr_dq_8__core__o;
  assign _336_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[53] : sdr_dq_8__core__oe;
  assign _337_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[54] : sdr_dq_9__pad__i;
  assign _338_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[55] : sdr_dq_9__core__o;
  assign _339_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[56] : sdr_dq_9__core__oe;
  assign _340_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[57] : sdr_dq_10__pad__i;
  assign _341_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[58] : sdr_dq_10__core__o;
  assign _342_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[59] : sdr_dq_10__core__oe;
  assign _343_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[60] : sdr_dq_11__pad__i;
  assign _344_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[61] : sdr_dq_11__core__o;
  assign _345_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[62] : sdr_dq_11__core__oe;
  assign _346_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[63] : sdr_dq_12__pad__i;
  assign _347_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[64] : sdr_dq_12__core__o;
  assign _348_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[65] : sdr_dq_12__core__oe;
  assign _349_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[66] : sdr_dq_13__pad__i;
  assign _350_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[67] : sdr_dq_13__core__o;
  assign _351_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[68] : sdr_dq_13__core__oe;
  assign _352_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[69] : sdr_dq_14__pad__i;
  assign _353_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[70] : sdr_dq_14__core__o;
  assign _354_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[71] : sdr_dq_14__core__oe;
  assign _355_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[72] : sdr_dq_15__pad__i;
  assign _356_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[73] : sdr_dq_15__core__o;
  assign _357_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[74] : sdr_dq_15__core__oe;
  assign _358_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[75] : gpio_e8__pad__i;
  assign _359_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[76] : gpio_e8__core__o;
  assign _360_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[77] : gpio_e8__core__oe;
  assign _361_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[78] : gpio_e9__pad__i;
  assign _362_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[79] : gpio_e9__core__o;
  assign _363_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[80] : gpio_e9__core__oe;
  assign _364_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[81] : gpio_e10__pad__i;
  assign _365_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[82] : gpio_e10__core__o;
  assign _366_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[83] : gpio_e10__core__oe;
  assign _367_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[84] : gpio_e11__pad__i;
  assign _368_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[85] : gpio_e11__core__o;
  assign _369_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[86] : gpio_e11__core__oe;
  assign _370_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[87] : gpio_e12__pad__i;
  assign _371_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[88] : gpio_e12__core__o;
  assign _372_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[89] : gpio_e12__core__oe;
  assign _373_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[90] : gpio_e13__pad__i;
  assign _374_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[91] : gpio_e13__core__o;
  assign _375_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[92] : gpio_e13__core__oe;
  assign _376_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[93] : gpio_e14__pad__i;
  assign _377_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[94] : gpio_e14__core__o;
  assign _378_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[95] : gpio_e14__core__oe;
  assign _379_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[96] : gpio_e15__pad__i;
  assign _380_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[97] : gpio_e15__core__o;
  assign _381_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[98] : gpio_e15__core__oe;
  assign _382_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[99] : gpio_s0__pad__i;
  assign _383_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[100] : gpio_s0__core__o;
  assign _384_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[101] : gpio_s0__core__oe;
  assign _385_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[102] : gpio_s1__pad__i;
  assign _386_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[103] : gpio_s1__core__o;
  assign _387_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[104] : gpio_s1__core__oe;
  assign _388_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[105] : gpio_s2__pad__i;
  assign _389_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[106] : gpio_s2__core__o;
  assign _390_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[107] : gpio_s2__core__oe;
  assign _391_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[108] : gpio_s3__pad__i;
  assign _392_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[109] : gpio_s3__core__o;
  assign _393_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[110] : gpio_s3__core__oe;
  assign _394_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[111] : gpio_s4__pad__i;
  assign _395_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[112] : gpio_s4__core__o;
  assign _396_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[113] : gpio_s4__core__oe;
  assign _397_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[114] : gpio_s5__pad__i;
  assign _398_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[115] : gpio_s5__core__o;
  assign _399_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[116] : gpio_s5__core__oe;
  assign _400_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[117] : gpio_s6__pad__i;
  assign _401_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[118] : gpio_s6__core__o;
  assign _402_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[119] : gpio_s6__core__oe;
  assign _403_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[120] : gpio_s7__pad__i;
  assign _404_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[121] : gpio_s7__core__o;
  assign _405_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[122] : gpio_s7__core__oe;
  assign _406_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[123] : mtwi_sda__pad__i;
  assign _407_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[124] : mtwi_sda__core__o;
  assign _408_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[125] : mtwi_sda__core__oe;
  assign _409_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[126] : mtwi_scl__core__o;
  assign _410_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[127] : eint_0__pad__i;
  assign _411_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[128] : eint_1__pad__i;
  assign _412_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[129] : eint_2__pad__i;
  assign _413_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[0] : mspi0_clk__core__o;
  assign _414_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[1] : mspi0_cs_n__core__o;
  assign _415_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[2] : mspi0_mosi__core__o;
  assign _416_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" *) io_bd[3] : mspi0_miso__pad__i;
  assign _417_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" *) io_bd[4] : sdr_dm_0__core__o;
  assign _418_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[5] : sdr_dq_0__pad__i;
  assign _419_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[6] : sdr_dq_0__core__o;
  assign _420_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[7] : sdr_dq_0__core__oe;
  assign _421_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[8] : sdr_dq_1__pad__i;
  assign _422_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[9] : sdr_dq_1__core__o;
  assign _423_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[10] : sdr_dq_1__core__oe;
  assign _424_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[11] : sdr_dq_2__pad__i;
  assign _425_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[12] : sdr_dq_2__core__o;
  assign _426_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[13] : sdr_dq_2__core__oe;
  assign _427_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[14] : sdr_dq_3__pad__i;
  assign _428_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[15] : sdr_dq_3__core__o;
  assign _429_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[16] : sdr_dq_3__core__oe;
  assign _430_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[17] : sdr_dq_4__pad__i;
  assign _431_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[18] : sdr_dq_4__core__o;
  assign _432_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[19] : sdr_dq_4__core__oe;
  assign _433_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[20] : sdr_dq_5__pad__i;
  assign _434_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" *) io_bd[21] : sdr_dq_5__core__o;
  assign _435_ = io_bd2io ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" *) io_bd[22] : sdr_dq_5__core__oe;
  assign _436_ = io_bd2core ? (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" *) io_bd[23] : sdr_dq_6__pad__i;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:139660.8-139672.4" *)
  _fsm _fsm (
    .TAP_bus__tck(TAP_bus__tck),
    .TAP_bus__tms(TAP_bus__tms),
    .capture(_fsm_capture),
    .isdr(_fsm_isdr),
    .isir(_fsm_isir),
    .negjtag_clk(negjtag_clk),
    .negjtag_rst(negjtag_rst),
    .posjtag_clk(posjtag_clk),
    .posjtag_rst(posjtag_rst),
    .shift(_fsm_shift),
    .update(_fsm_update)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:139673.12-139683.4" *)
  _idblock _idblock (
    .TAP_bus__tdi(TAP_bus__tdi),
    .TAP_id_tdo(_idblock_TAP_id_tdo),
    .capture(_fsm_capture),
    .id_bypass(_idblock_id_bypass),
    .posjtag_clk(posjtag_clk),
    .posjtag_rst(posjtag_rst),
    .select_id(_idblock_select_id),
    .shift(_fsm_shift),
    .update(_fsm_update)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:139684.12-139694.4" *)
  _irblock _irblock (
    .TAP_bus__tdi(TAP_bus__tdi),
    .capture(_fsm_capture),
    .ir(_irblock_ir),
    .isir(_fsm_isir),
    .posjtag_clk(posjtag_clk),
    .posjtag_rst(posjtag_rst),
    .shift(_fsm_shift),
    .tdo(_irblock_tdo),
    .update(_fsm_update)
  );
  always @* begin
    if (\initial ) begin end
    _029_ = 1'h0;
  end
  always @* begin
      \initial  <= _029_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      dmi0__addr_i <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dmi0__din <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_addrsr__oe <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      dmi0_addrsr_reg <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_addrsr_update_core <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_addrsr_update_core_prev <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dmi0_datasr__i <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_datasr__oe <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dmi0_datasr_reg <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_datasr_update_core <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dmi0_datasr_update_core_prev <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      fsm_state <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      \fsm_state$463  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 130'h000000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      io_bd <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 130'h000000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      io_sr <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      jtag_wb__adr <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      jtag_wb__dat_w <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_addrsr__oe <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      jtag_wb_addrsr_reg <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_addrsr_update_core <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_addrsr_update_core_prev <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_datasr__i <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_datasr__oe <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_datasr_reg <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_datasr_update_core <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_wb_datasr_update_core_prev <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr0__oe <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sr0_reg <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr0_update_core <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _139_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr0_update_core_prev <= _139_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr5__oe <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sr5_reg <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr5_update_core <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr5_update_core_prev <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      wb_dcache_en <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      wb_icache_en <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      wb_sram_en <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \wb_icache_en$next ;
  end
  always @(posedge clk) begin
      wb_icache_en <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \wb_dcache_en$next ;
  end
  always @(posedge clk) begin
      wb_dcache_en <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = \wb_sram_en$next ;
  end
  always @(posedge clk) begin
      wb_sram_en <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \dmi0_datasr__i$next ;
  end
  always @(posedge clk) begin
      dmi0_datasr__i <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \dmi0__din$next ;
  end
  always @(posedge clk) begin
      dmi0__din <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \fsm_state$463$next ;
  end
  always @(posedge clk) begin
      \fsm_state$463  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \dmi0__addr_i$next ;
  end
  always @(posedge clk) begin
      dmi0__addr_i <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \jtag_wb_datasr__i$next ;
  end
  always @(posedge clk) begin
      jtag_wb_datasr__i <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \jtag_wb__dat_w$next ;
  end
  always @(posedge clk) begin
      jtag_wb__dat_w <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \fsm_state$next ;
  end
  always @(posedge clk) begin
      fsm_state <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \jtag_wb__adr$next ;
  end
  always @(posedge clk) begin
      jtag_wb__adr <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \sr5_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      sr5_reg <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \sr5__oe$next ;
  end
  always @(posedge clk) begin
      sr5__oe <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \sr5_update_core_prev$next ;
  end
  always @(posedge clk) begin
      sr5_update_core_prev <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \sr5_update_core$next ;
  end
  always @(posedge clk) begin
      sr5_update_core <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \dmi0_datasr_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      dmi0_datasr_reg <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \dmi0_datasr__oe$next ;
  end
  always @(posedge clk) begin
      dmi0_datasr__oe <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \dmi0_datasr_update_core_prev$next ;
  end
  always @(posedge clk) begin
      dmi0_datasr_update_core_prev <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \dmi0_datasr_update_core$next ;
  end
  always @(posedge clk) begin
      dmi0_datasr_update_core <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \dmi0_addrsr_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      dmi0_addrsr_reg <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \dmi0_addrsr__oe$next ;
  end
  always @(posedge clk) begin
      dmi0_addrsr__oe <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \dmi0_addrsr_update_core_prev$next ;
  end
  always @(posedge clk) begin
      dmi0_addrsr_update_core_prev <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \dmi0_addrsr_update_core$next ;
  end
  always @(posedge clk) begin
      dmi0_addrsr_update_core <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \jtag_wb_datasr_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      jtag_wb_datasr_reg <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \jtag_wb_datasr__oe$next ;
  end
  always @(posedge clk) begin
      jtag_wb_datasr__oe <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \jtag_wb_datasr_update_core_prev$next ;
  end
  always @(posedge clk) begin
      jtag_wb_datasr_update_core_prev <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \jtag_wb_datasr_update_core$next ;
  end
  always @(posedge clk) begin
      jtag_wb_datasr_update_core <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \jtag_wb_addrsr_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      jtag_wb_addrsr_reg <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \jtag_wb_addrsr__oe$next ;
  end
  always @(posedge clk) begin
      jtag_wb_addrsr__oe <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \jtag_wb_addrsr_update_core_prev$next ;
  end
  always @(posedge clk) begin
      jtag_wb_addrsr_update_core_prev <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \jtag_wb_addrsr_update_core$next ;
  end
  always @(posedge clk) begin
      jtag_wb_addrsr_update_core <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \sr0_reg$next ;
  end
  always @(posedge posjtag_clk) begin
      sr0_reg <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \sr0__oe$next ;
  end
  always @(posedge clk) begin
      sr0__oe <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \sr0_update_core_prev$next ;
  end
  always @(posedge clk) begin
      sr0_update_core_prev <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \sr0_update_core$next ;
  end
  always @(posedge clk) begin
      sr0_update_core <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \io_bd$next ;
  end
  always @(negedge negjtag_clk) begin
      io_bd <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \io_sr$next ;
  end
  always @(posedge posjtag_clk) begin
      io_sr <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _080_;
    (* src = "libresoc.v:139696.5-139696.29" *)
    casez (\initial )
      /* src = "libresoc.v:139696.9-139696.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" *)
    casez ({ \$321 , _idblock_select_id, _fsm_isir })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _080_ = _irblock_tdo;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
        begin
          _080_ = _idblock_TAP_id_tdo;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b1??:
        begin
          _080_ = io_sr[129];
        end
      default:
          _080_ = 1'h0;
    endcase
  end
  always @* begin
      TAP_tdo <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _136_;
    (* src = "libresoc.v:139712.5-139712.29" *)
    casez (\initial )
      /* src = "libresoc.v:139712.9-139712.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = 1'h0;
        end
      default:
          _136_ = sr0_update;
    endcase
  end
  always @* begin
      \sr0_update_core$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _138_;
    (* src = "libresoc.v:139721.5-139721.29" *)
    casez (\initial )
      /* src = "libresoc.v:139721.9-139721.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _138_ = 1'h0;
        end
      default:
          _138_ = sr0_update_core;
    endcase
  end
  always @* begin
      \sr0_update_core_prev$next  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _173_;
    (* src = "libresoc.v:139730.5-139730.29" *)
    casez (\initial )
      /* src = "libresoc.v:139730.9-139730.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$339 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = sr0_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _132_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 1'h0;
        end
      default:
          _173_ = _132_;
    endcase
  end
  always @* begin
      \sr0__oe$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _192_;
    (* src = "libresoc.v:139747.5-139747.29" *)
    casez (\initial )
      /* src = "libresoc.v:139747.9-139747.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (sr0_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = { TAP_bus__tdi, sr0_reg[2:1] };
        end
      default:
          _134_ = sr0_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (sr0_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _174_ = sr0__i;
        end
      default:
          _174_ = _134_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _192_ = 3'h0;
        end
      default:
          _192_ = _174_;
    endcase
  end
  always @* begin
      \sr0_reg$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _118_;
    (* src = "libresoc.v:139768.5-139768.29" *)
    casez (\initial )
      /* src = "libresoc.v:139768.9-139768.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _118_ = 1'h0;
        end
      default:
          _118_ = jtag_wb_addrsr_update;
    endcase
  end
  always @* begin
      \jtag_wb_addrsr_update_core$next  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _120_;
    (* src = "libresoc.v:139777.5-139777.29" *)
    casez (\initial )
      /* src = "libresoc.v:139777.9-139777.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _120_ = 1'h0;
        end
      default:
          _120_ = jtag_wb_addrsr_update_core;
    endcase
  end
  always @* begin
      \jtag_wb_addrsr_update_core_prev$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _168_;
    (* src = "libresoc.v:139786.5-139786.29" *)
    casez (\initial )
      /* src = "libresoc.v:139786.9-139786.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$357 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _114_ = jtag_wb_addrsr_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _114_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _168_ = 1'h0;
        end
      default:
          _168_ = _114_;
    endcase
  end
  always @* begin
      \jtag_wb_addrsr__oe$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _189_;
    (* src = "libresoc.v:139803.5-139803.29" *)
    casez (\initial )
      /* src = "libresoc.v:139803.9-139803.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (jtag_wb_addrsr_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _116_ = { TAP_bus__tdi, jtag_wb_addrsr_reg[29:1] };
        end
      default:
          _116_ = jtag_wb_addrsr_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (jtag_wb_addrsr_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _169_ = jtag_wb_addrsr__i;
        end
      default:
          _169_ = _116_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _189_ = 30'h00000000;
        end
      default:
          _189_ = _169_;
    endcase
  end
  always @* begin
      \jtag_wb_addrsr_reg$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = _128_;
    (* src = "libresoc.v:139824.5-139824.29" *)
    casez (\initial )
      /* src = "libresoc.v:139824.9-139824.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = 1'h0;
        end
      default:
          _128_ = jtag_wb_datasr_update;
    endcase
  end
  always @* begin
      \jtag_wb_datasr_update_core$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _130_;
    (* src = "libresoc.v:139833.5-139833.29" *)
    casez (\initial )
      /* src = "libresoc.v:139833.9-139833.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h0;
        end
      default:
          _130_ = jtag_wb_datasr_update_core;
    endcase
  end
  always @* begin
      \jtag_wb_datasr_update_core_prev$next  <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = _171_;
    (* src = "libresoc.v:139842.5-139842.29" *)
    casez (\initial )
      /* src = "libresoc.v:139842.9-139842.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$377 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _124_ = jtag_wb_datasr_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _124_ = 2'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 2'h0;
        end
      default:
          _171_ = _124_;
    endcase
  end
  always @* begin
      \jtag_wb_datasr__oe$next  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _191_;
    (* src = "libresoc.v:139859.5-139859.29" *)
    casez (\initial )
      /* src = "libresoc.v:139859.9-139859.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (jtag_wb_datasr_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = { TAP_bus__tdi, jtag_wb_datasr_reg[31:1] };
        end
      default:
          _126_ = jtag_wb_datasr_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (jtag_wb_datasr_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _172_ = jtag_wb_datasr__i;
        end
      default:
          _172_ = _126_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _191_ = 32'd0;
        end
      default:
          _191_ = _172_;
    endcase
  end
  always @* begin
      \jtag_wb_datasr_reg$next  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _089_;
    (* src = "libresoc.v:139880.5-139880.29" *)
    casez (\initial )
      /* src = "libresoc.v:139880.9-139880.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _089_ = 1'h0;
        end
      default:
          _089_ = dmi0_addrsr_update;
    endcase
  end
  always @* begin
      \dmi0_addrsr_update_core$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _091_;
    (* src = "libresoc.v:139889.5-139889.29" *)
    casez (\initial )
      /* src = "libresoc.v:139889.9-139889.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _091_ = 1'h0;
        end
      default:
          _091_ = dmi0_addrsr_update_core;
    endcase
  end
  always @* begin
      \dmi0_addrsr_update_core_prev$next  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _157_;
    (* src = "libresoc.v:139898.5-139898.29" *)
    casez (\initial )
      /* src = "libresoc.v:139898.9-139898.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$395 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _085_ = dmi0_addrsr_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _085_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = 1'h0;
        end
      default:
          _157_ = _085_;
    endcase
  end
  always @* begin
      \dmi0_addrsr__oe$next  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _182_;
    (* src = "libresoc.v:139915.5-139915.29" *)
    casez (\initial )
      /* src = "libresoc.v:139915.9-139915.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (dmi0_addrsr_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = { TAP_bus__tdi, dmi0_addrsr_reg[7:1] };
        end
      default:
          _087_ = dmi0_addrsr_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (dmi0_addrsr_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _158_ = dmi0_addrsr__i;
        end
      default:
          _158_ = _087_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _182_ = 8'h00;
        end
      default:
          _182_ = _158_;
    endcase
  end
  always @* begin
      \dmi0_addrsr_reg$next  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _099_;
    (* src = "libresoc.v:139936.5-139936.29" *)
    casez (\initial )
      /* src = "libresoc.v:139936.9-139936.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _099_ = 1'h0;
        end
      default:
          _099_ = dmi0_datasr_update;
    endcase
  end
  always @* begin
      \dmi0_datasr_update_core$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _101_;
    (* src = "libresoc.v:139945.5-139945.29" *)
    casez (\initial )
      /* src = "libresoc.v:139945.9-139945.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = 1'h0;
        end
      default:
          _101_ = dmi0_datasr_update_core;
    endcase
  end
  always @* begin
      \dmi0_datasr_update_core_prev$next  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _160_;
    (* src = "libresoc.v:139954.5-139954.29" *)
    casez (\initial )
      /* src = "libresoc.v:139954.9-139954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$415 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _095_ = dmi0_datasr_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _095_ = 2'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _160_ = 2'h0;
        end
      default:
          _160_ = _095_;
    endcase
  end
  always @* begin
      \dmi0_datasr__oe$next  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _184_;
    (* src = "libresoc.v:139971.5-139971.29" *)
    casez (\initial )
      /* src = "libresoc.v:139971.9-139971.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (dmi0_datasr_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = { TAP_bus__tdi, dmi0_datasr_reg[63:1] };
        end
      default:
          _097_ = dmi0_datasr_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (dmi0_datasr_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _161_ = dmi0_datasr__i;
        end
      default:
          _161_ = _097_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _184_ = 64'h0000000000000000;
        end
      default:
          _184_ = _161_;
    endcase
  end
  always @* begin
      \dmi0_datasr_reg$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _145_;
    (* src = "libresoc.v:139992.5-139992.29" *)
    casez (\initial )
      /* src = "libresoc.v:139992.9-139992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 1'h0;
        end
      default:
          _145_ = sr5_update;
    endcase
  end
  always @* begin
      \sr5_update_core$next  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = _147_;
    (* src = "libresoc.v:140001.5-140001.29" *)
    casez (\initial )
      /* src = "libresoc.v:140001.9-140001.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = 1'h0;
        end
      default:
          _147_ = sr5_update_core;
    endcase
  end
  always @* begin
      \sr5_update_core_prev$next  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _175_;
    (* src = "libresoc.v:140010.5-140010.29" *)
    casez (\initial )
      /* src = "libresoc.v:140010.9-140010.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" *)
    casez (\$433 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = sr5_isir;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _141_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 1'h0;
        end
      default:
          _175_ = _141_;
    endcase
  end
  always @* begin
      \sr5__oe$next  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = _193_;
    (* src = "libresoc.v:140027.5-140027.29" *)
    casez (\initial )
      /* src = "libresoc.v:140027.9-140027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:673" *)
    casez (sr5_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = { TAP_bus__tdi, sr5_reg[2:1] };
        end
      default:
          _143_ = sr5_reg;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" *)
    casez (sr5_capture)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _176_ = sr5__i;
        end
      default:
          _176_ = _143_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _193_ = 3'h0;
        end
      default:
          _193_ = _176_;
    endcase
  end
  always @* begin
      \sr5_reg$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _079_;
    (* src = "libresoc.v:140048.5-140048.29" *)
    casez (\initial )
      /* src = "libresoc.v:140048.9-140048.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:685" *)
    casez ({ sr5_shift, dmi0_datasr_shift, dmi0_addrsr_shift, jtag_wb_datasr_shift, jtag_wb_addrsr_shift, sr0_shift })
      /* src = "libresoc.v:0.0-0.0" */
      6'b?????1:
        begin
          _079_ = sr0_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'b????1?:
        begin
          _079_ = jtag_wb_addrsr_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'b???1??:
        begin
          _079_ = jtag_wb_datasr_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'b??1???:
        begin
          _079_ = dmi0_addrsr_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'b?1????:
        begin
          _079_ = dmi0_datasr_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      6'b1?????:
        begin
          _079_ = sr5_reg[0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _079_ = TAP_tdo;
        end
    endcase
  end
  always @* begin
      TAP_bus__tdo <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _197_;
    (* src = "libresoc.v:140075.5-140075.29" *)
    casez (\initial )
      /* src = "libresoc.v:140075.9-140075.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _110_ = _166_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *)
          casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
              begin
                _166_ = jtag_wb_addrsr__o;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
              begin
                _166_ = \$455 [29:0];
              end
            default:
                _166_ = jtag_wb__adr;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _110_ = jtag_wb__adr;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _110_ = jtag_wb__adr;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _110_ = jtag_wb__adr;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _110_ = _187_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" *)
          casez (jtag_wb__ack)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _187_ = \$458 [29:0];
              end
            default:
                _187_ = jtag_wb__adr;
          endcase
        end
      default:
          _110_ = jtag_wb__adr;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _197_ = 30'h00000000;
        end
      default:
          _197_ = _110_;
    endcase
  end
  always @* begin
      \jtag_wb__adr$next  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _199_;
    (* src = "libresoc.v:140120.5-140120.29" *)
    casez (\initial )
      /* src = "libresoc.v:140120.9-140120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _104_ = _163_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *)
          casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
              begin
                _163_ = 3'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
              begin
                _163_ = 3'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b1??:
              begin
                _163_ = 3'h2;
              end
            default:
                _163_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _104_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _104_ = _186_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" *)
          casez (jtag_wb__ack)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _186_ = 3'h0;
              end
            default:
                _186_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _104_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _104_ = _196_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" *)
          casez (jtag_wb__ack)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _196_ = 3'h1;
              end
            default:
                _196_ = fsm_state;
          endcase
        end
      default:
          _104_ = fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _199_ = 3'h0;
        end
      default:
          _199_ = _104_;
    endcase
  end
  always @* begin
      \fsm_state$next  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _188_;
    (* src = "libresoc.v:140173.5-140173.29" *)
    casez (\initial )
      /* src = "libresoc.v:140173.9-140173.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _112_ = _167_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" *)
          casez ({ jtag_wb_datasr__oe, jtag_wb_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
                _167_ = jtag_wb__dat_w;
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
                _167_ = jtag_wb__dat_w;
            /* src = "libresoc.v:0.0-0.0" */
            3'b1??:
              begin
                _167_ = jtag_wb_datasr__o;
              end
            default:
                _167_ = jtag_wb__dat_w;
          endcase
        end
      default:
          _112_ = jtag_wb__dat_w;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _188_ = 32'd0;
        end
      default:
          _188_ = _112_;
    endcase
  end
  always @* begin
      \jtag_wb__dat_w$next  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _190_;
    (* src = "libresoc.v:140200.5-140200.29" *)
    casez (\initial )
      /* src = "libresoc.v:140200.9-140200.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _122_ = jtag_wb_datasr__i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _122_ = jtag_wb_datasr__i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _122_ = _170_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" *)
          casez (jtag_wb__ack)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _170_ = jtag_wb__dat_r;
              end
            default:
                _170_ = jtag_wb_datasr__i;
          endcase
        end
      default:
          _122_ = jtag_wb_datasr__i;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _190_ = 32'd0;
        end
      default:
          _190_ = _122_;
    endcase
  end
  always @* begin
      \jtag_wb_datasr__i$next  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _194_;
    (* src = "libresoc.v:140229.5-140229.29" *)
    casez (\initial )
      /* src = "libresoc.v:140229.9-140229.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
    casez (\fsm_state$463 )
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _081_ = _155_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *)
          casez ({ dmi0_datasr__oe, dmi0_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
              begin
                _155_ = dmi0_addrsr__o[3:0];
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
              begin
                _155_ = \$472 [3:0];
              end
            default:
                _155_ = dmi0__addr_i;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _081_ = dmi0__addr_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _081_ = dmi0__addr_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _081_ = dmi0__addr_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _081_ = _180_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" *)
          casez (dmi0__ack_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _180_ = \$475 [3:0];
              end
            default:
                _180_ = dmi0__addr_i;
          endcase
        end
      default:
          _081_ = dmi0__addr_i;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _194_ = 4'h0;
        end
      default:
          _194_ = _081_;
    endcase
  end
  always @* begin
      \dmi0__addr_i$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _198_;
    (* src = "libresoc.v:140274.5-140274.29" *)
    casez (\initial )
      /* src = "libresoc.v:140274.9-140274.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
    casez (\fsm_state$463 )
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _103_ = _162_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *)
          casez ({ dmi0_datasr__oe, dmi0_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
              begin
                _162_ = 3'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
              begin
                _162_ = 3'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b1??:
              begin
                _162_ = 3'h2;
              end
            default:
                _162_ = \fsm_state$463 ;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _103_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _103_ = _185_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" *)
          casez (dmi0__ack_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _185_ = 3'h0;
              end
            default:
                _185_ = \fsm_state$463 ;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _103_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _103_ = _195_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" *)
          casez (dmi0__ack_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _195_ = 3'h1;
              end
            default:
                _195_ = \fsm_state$463 ;
          endcase
        end
      default:
          _103_ = \fsm_state$463 ;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _198_ = 3'h0;
        end
      default:
          _198_ = _103_;
    endcase
  end
  always @* begin
      \fsm_state$463$next  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _181_;
    (* src = "libresoc.v:140327.5-140327.29" *)
    casez (\initial )
      /* src = "libresoc.v:140327.9-140327.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
    casez (\fsm_state$463 )
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _083_ = _156_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" *)
          casez ({ dmi0_datasr__oe, dmi0_addrsr__oe })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
                _156_ = dmi0__din;
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
                _156_ = dmi0__din;
            /* src = "libresoc.v:0.0-0.0" */
            3'b1??:
              begin
                _156_ = dmi0_datasr__o;
              end
            default:
                _156_ = dmi0__din;
          endcase
        end
      default:
          _083_ = dmi0__din;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _181_ = 64'h0000000000000000;
        end
      default:
          _181_ = _083_;
    endcase
  end
  always @* begin
      \dmi0__din$next  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _183_;
    (* src = "libresoc.v:140354.5-140354.29" *)
    casez (\initial )
      /* src = "libresoc.v:140354.9-140354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" *)
    casez (\fsm_state$463 )
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _093_ = dmi0_datasr__i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _093_ = dmi0_datasr__i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _093_ = _159_;
          (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" *)
          casez (dmi0__ack_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _159_ = dmi0__dout;
              end
            default:
                _159_ = dmi0_datasr__i;
          endcase
        end
      default:
          _093_ = dmi0_datasr__i;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _183_ = 64'h0000000000000000;
        end
      default:
          _183_ = _093_;
    endcase
  end
  always @* begin
      \dmi0_datasr__i$next  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = _177_;
    _075_ = _178_;
    _077_ = _179_;
    (* src = "libresoc.v:140383.5-140383.29" *)
    casez (\initial )
      /* src = "libresoc.v:140383.9-140383.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:108" *)
    casez (sr5__oe)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _153_, _149_, _151_ } = sr5__o;
        end
      default:
        begin
          _149_ = wb_dcache_en;
          _151_ = wb_icache_en;
          _153_ = wb_sram_en;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _178_ = 1'h1;
          _177_ = 1'h1;
          _179_ = 1'h1;
        end
      default:
        begin
          _177_ = _149_;
          _178_ = _151_;
          _179_ = _153_;
        end
    endcase
  end
  always @* begin
      \wb_dcache_en$next  <= _073_;
      \wb_icache_en$next  <= _075_;
      \wb_sram_en$next  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _140_;
    (* src = "libresoc.v:140404.5-140404.29" *)
    casez (\initial )
      /* src = "libresoc.v:140404.9-140404.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:111" *)
    casez (sr5__ie)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _140_ = { wb_sram_en, wb_dcache_en, wb_icache_en };
        end
      default:
          _140_ = 3'h0;
    endcase
  end
  always @* begin
      sr5__i <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _165_;
    (* src = "libresoc.v:140414.5-140414.29" *)
    casez (\initial )
      /* src = "libresoc.v:140414.9-140414.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" *)
    casez ({ io_update, io_shift, io_capture })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _108_ = { eint_2__pad__i, eint_1__pad__i, eint_0__pad__i, mtwi_scl__core__o, mtwi_sda__core__oe, mtwi_sda__core__o, mtwi_sda__pad__i, gpio_s7__core__oe, gpio_s7__core__o, gpio_s7__pad__i, gpio_s6__core__oe, gpio_s6__core__o, gpio_s6__pad__i, gpio_s5__core__oe, gpio_s5__core__o, gpio_s5__pad__i, gpio_s4__core__oe, gpio_s4__core__o, gpio_s4__pad__i, gpio_s3__core__oe, gpio_s3__core__o, gpio_s3__pad__i, gpio_s2__core__oe, gpio_s2__core__o, gpio_s2__pad__i, gpio_s1__core__oe, gpio_s1__core__o, gpio_s1__pad__i, gpio_s0__core__oe, gpio_s0__core__o, gpio_s0__pad__i, gpio_e15__core__oe, gpio_e15__core__o, gpio_e15__pad__i, gpio_e14__core__oe, gpio_e14__core__o, gpio_e14__pad__i, gpio_e13__core__oe, gpio_e13__core__o, gpio_e13__pad__i, gpio_e12__core__oe, gpio_e12__core__o, gpio_e12__pad__i, gpio_e11__core__oe, gpio_e11__core__o, gpio_e11__pad__i, gpio_e10__core__oe, gpio_e10__core__o, gpio_e10__pad__i, gpio_e9__core__oe, gpio_e9__core__o, gpio_e9__pad__i, gpio_e8__core__oe, gpio_e8__core__o, gpio_e8__pad__i, sdr_dq_15__core__oe, sdr_dq_15__core__o, sdr_dq_15__pad__i, sdr_dq_14__core__oe, sdr_dq_14__core__o, sdr_dq_14__pad__i, sdr_dq_13__core__oe, sdr_dq_13__core__o, sdr_dq_13__pad__i, sdr_dq_12__core__oe, sdr_dq_12__core__o, sdr_dq_12__pad__i, sdr_dq_11__core__oe, sdr_dq_11__core__o, sdr_dq_11__pad__i, sdr_dq_10__core__oe, sdr_dq_10__core__o, sdr_dq_10__pad__i, sdr_dq_9__core__oe, sdr_dq_9__core__o, sdr_dq_9__pad__i, sdr_dq_8__core__oe, sdr_dq_8__core__o, sdr_dq_8__pad__i, sdr_dm_1__core__o, sdr_a_12__core__o, sdr_a_11__core__o, sdr_a_10__core__o, sdr_cs_n__core__o, sdr_we_n__core__o, sdr_cas_n__core__o, sdr_ras_n__core__o, sdr_cke__core__o, sdr_clock__core__o, sdr_ba_1__core__o, sdr_ba_0__core__o, sdr_a_9__core__o, sdr_a_8__core__o, sdr_a_7__core__o, sdr_a_6__core__o, sdr_a_5__core__o, sdr_a_4__core__o, sdr_a_3__core__o, sdr_a_2__core__o, sdr_a_1__core__o, sdr_a_0__core__o, sdr_dq_7__core__oe, sdr_dq_7__core__o, sdr_dq_7__pad__i, sdr_dq_6__core__oe, sdr_dq_6__core__o, sdr_dq_6__pad__i, sdr_dq_5__core__oe, sdr_dq_5__core__o, sdr_dq_5__pad__i, sdr_dq_4__core__oe, sdr_dq_4__core__o, sdr_dq_4__pad__i, sdr_dq_3__core__oe, sdr_dq_3__core__o, sdr_dq_3__pad__i, sdr_dq_2__core__oe, sdr_dq_2__core__o, sdr_dq_2__pad__i, sdr_dq_1__core__oe, sdr_dq_1__core__o, sdr_dq_1__pad__i, sdr_dq_0__core__oe, sdr_dq_0__core__o, sdr_dq_0__pad__i, sdr_dm_0__core__o, mspi0_miso__pad__i, mspi0_mosi__core__o, mspi0_cs_n__core__o, mspi0_clk__core__o };
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
        begin
          _108_ = { io_sr[128:0], TAP_bus__tdi };
        end
      default:
          _108_ = io_sr;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (posjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _165_ = 130'h000000000000000000000000000000000;
        end
      default:
          _165_ = _108_;
    endcase
  end
  always @* begin
      \io_sr$next  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _164_;
    (* src = "libresoc.v:140432.5-140432.29" *)
    casez (\initial )
      /* src = "libresoc.v:140432.9-140432.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:552" *)
    casez ({ io_update, io_shift, io_capture })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
          _106_ = io_bd;
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
          _106_ = io_bd;
      /* src = "libresoc.v:0.0-0.0" */
      3'b1??:
        begin
          _106_ = io_sr;
        end
      default:
          _106_ = io_bd;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (negjtag_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _164_ = 130'h000000000000000000000000000000000;
        end
      default:
          _164_ = _106_;
    endcase
  end
  always @* begin
      \io_bd$next  <= _030_;
  end
  assign \$9  = _235_;
  assign \$99  = _307_;
  assign \$101  = _308_;
  assign \$103  = _309_;
  assign \$105  = _310_;
  assign \$107  = _311_;
  assign \$109  = _312_;
  assign \$111  = _313_;
  assign \$113  = _314_;
  assign \$115  = _315_;
  assign \$117  = _316_;
  assign \$11  = _236_;
  assign \$119  = _317_;
  assign \$121  = _318_;
  assign \$123  = _319_;
  assign \$125  = _320_;
  assign \$127  = _321_;
  assign \$129  = _322_;
  assign \$131  = _323_;
  assign \$133  = _324_;
  assign \$135  = _325_;
  assign \$137  = _326_;
  assign \$13  = _237_;
  assign \$139  = _327_;
  assign \$141  = _328_;
  assign \$143  = _329_;
  assign \$145  = _330_;
  assign \$147  = _331_;
  assign \$149  = _332_;
  assign \$151  = _333_;
  assign \$153  = _334_;
  assign \$155  = _335_;
  assign \$157  = _336_;
  assign \$15  = _294_;
  assign \$159  = _337_;
  assign \$161  = _338_;
  assign \$163  = _339_;
  assign \$165  = _340_;
  assign \$167  = _341_;
  assign \$169  = _342_;
  assign \$171  = _343_;
  assign \$173  = _344_;
  assign \$175  = _345_;
  assign \$177  = _346_;
  assign \$17  = _204_;
  assign \$179  = _347_;
  assign \$181  = _348_;
  assign \$183  = _349_;
  assign \$185  = _350_;
  assign \$187  = _351_;
  assign \$189  = _352_;
  assign \$191  = _353_;
  assign \$193  = _354_;
  assign \$195  = _355_;
  assign \$197  = _356_;
  assign \$1  = _238_;
  assign \$19  = _239_;
  assign \$199  = _357_;
  assign \$201  = _358_;
  assign \$203  = _359_;
  assign \$205  = _360_;
  assign \$207  = _361_;
  assign \$209  = _362_;
  assign \$211  = _363_;
  assign \$213  = _364_;
  assign \$215  = _365_;
  assign \$217  = _366_;
  assign \$21  = _240_;
  assign \$219  = _367_;
  assign \$221  = _368_;
  assign \$223  = _369_;
  assign \$225  = _370_;
  assign \$227  = _371_;
  assign \$229  = _372_;
  assign \$231  = _373_;
  assign \$233  = _374_;
  assign \$235  = _375_;
  assign \$237  = _376_;
  assign \$23  = _295_;
  assign \$239  = _377_;
  assign \$241  = _378_;
  assign \$243  = _379_;
  assign \$245  = _380_;
  assign \$247  = _381_;
  assign \$249  = _382_;
  assign \$251  = _383_;
  assign \$253  = _384_;
  assign \$255  = _385_;
  assign \$257  = _386_;
  assign \$25  = _241_;
  assign \$259  = _387_;
  assign \$261  = _388_;
  assign \$263  = _389_;
  assign \$265  = _390_;
  assign \$267  = _391_;
  assign \$269  = _392_;
  assign \$271  = _393_;
  assign \$273  = _394_;
  assign \$275  = _395_;
  assign \$277  = _396_;
  assign \$27  = _296_;
  assign \$279  = _397_;
  assign \$281  = _398_;
  assign \$283  = _399_;
  assign \$285  = _400_;
  assign \$287  = _401_;
  assign \$289  = _402_;
  assign \$291  = _403_;
  assign \$293  = _404_;
  assign \$295  = _405_;
  assign \$297  = _406_;
  assign \$29  = _205_;
  assign \$299  = _407_;
  assign \$301  = _408_;
  assign \$303  = _409_;
  assign \$305  = _410_;
  assign \$307  = _411_;
  assign \$309  = _412_;
  assign \$311  = _242_;
  assign \$313  = _243_;
  assign \$315  = _297_;
  assign \$317  = _244_;
  assign \$31  = _206_;
  assign \$319  = _298_;
  assign \$321  = _207_;
  assign \$323  = _245_;
  assign \$325  = _269_;
  assign \$327  = _208_;
  assign \$329  = _270_;
  assign \$331  = _209_;
  assign \$333  = _271_;
  assign \$335  = _210_;
  assign \$337  = _287_;
  assign \$33  = _246_;
  assign \$339  = _211_;
  assign \$341  = _247_;
  assign \$343  = _272_;
  assign \$345  = _212_;
  assign \$347  = _273_;
  assign \$349  = _213_;
  assign \$351  = _274_;
  assign \$353  = _214_;
  assign \$355  = _288_;
  assign \$357  = _215_;
  assign \$35  = _248_;
  assign \$359  = _249_;
  assign \$361  = _250_;
  assign \$363  = _275_;
  assign \$365  = _216_;
  assign \$367  = _276_;
  assign \$369  = _217_;
  assign \$371  = _277_;
  assign \$373  = _218_;
  assign \$375  = _289_;
  assign \$377  = _219_;
  assign \$37  = _299_;
  assign \$379  = _251_;
  assign \$381  = _278_;
  assign \$383  = _220_;
  assign \$385  = _279_;
  assign \$387  = _221_;
  assign \$389  = _280_;
  assign \$391  = _222_;
  assign \$393  = _290_;
  assign \$395  = _223_;
  assign \$397  = _252_;
  assign \$3  = _253_;
  assign \$39  = _254_;
  assign \$399  = _255_;
  assign \$401  = _281_;
  assign \$403  = _224_;
  assign \$405  = _282_;
  assign \$407  = _225_;
  assign \$409  = _283_;
  assign \$411  = _226_;
  assign \$413  = _291_;
  assign \$415  = _227_;
  assign \$417  = _256_;
  assign \$41  = _300_;
  assign \$419  = _284_;
  assign \$421  = _228_;
  assign \$423  = _285_;
  assign \$425  = _229_;
  assign \$427  = _286_;
  assign \$429  = _230_;
  assign \$431  = _292_;
  assign \$433  = _231_;
  assign \$435  = _257_;
  assign \$437  = _258_;
  assign \$43  = _232_;
  assign \$439  = _301_;
  assign \$441  = _259_;
  assign \$443  = _302_;
  assign \$445  = _260_;
  assign \$447  = _303_;
  assign \$450  = _261_;
  assign \$449  = _293_;
  assign \$453  = _262_;
  assign \$456  = _200_;
  assign \$45  = _233_;
  assign \$459  = _201_;
  assign \$461  = _306_;
  assign \$464  = _263_;
  assign \$466  = _264_;
  assign \$468  = _304_;
  assign \$470  = _265_;
  assign \$473  = _202_;
  assign \$476  = _203_;
  assign \$47  = _266_;
  assign \$49  = _267_;
  assign \$51  = _413_;
  assign \$53  = _414_;
  assign \$55  = _415_;
  assign \$57  = _416_;
  assign \$5  = _305_;
  assign \$59  = _417_;
  assign \$61  = _418_;
  assign \$63  = _419_;
  assign \$65  = _420_;
  assign \$67  = _421_;
  assign \$69  = _422_;
  assign \$71  = _423_;
  assign \$73  = _424_;
  assign \$75  = _425_;
  assign \$77  = _426_;
  assign \$7  = _234_;
  assign \$79  = _427_;
  assign \$81  = _428_;
  assign \$83  = _429_;
  assign \$85  = _430_;
  assign \$87  = _431_;
  assign \$89  = _432_;
  assign \$91  = _433_;
  assign \$93  = _434_;
  assign \$95  = _435_;
  assign \$97  = _436_;
  assign \$455  = \$456 ;
  assign \$458  = \$459 ;
  assign \$472  = \$473 ;
  assign \$475  = \$476 ;
  assign sr5__ie = 1'h0;
  assign sr0__i = sr0__o;
  assign dmi0__we_i = \$470 ;
  assign dmi0__req_i = \$468 ;
  assign dmi0_addrsr__i = \$461 ;
  assign jtag_wb__we = \$453 ;
  assign jtag_wb__cyc = \$449 ;
  assign jtag_wb__stb = \$447 ;
  assign jtag_wb__sel[3] = 1'h1;
  assign jtag_wb__sel[2] = 1'h1;
  assign jtag_wb__sel[1] = 1'h1;
  assign jtag_wb__sel[0] = 1'h1;
  assign jtag_wb_addrsr__i = jtag_wb__adr;
  assign sr5_update = \$429 ;
  assign sr5_shift = \$425 ;
  assign sr5_capture = \$421 ;
  assign sr5_isir = \$417 ;
  assign sr5__o = sr5_reg;
  assign dmi0_datasr_update = \$411 ;
  assign dmi0_datasr_shift = \$407 ;
  assign dmi0_datasr_capture = \$403 ;
  assign dmi0_datasr_isir = { \$399 , \$397  };
  assign dmi0_datasr__o = dmi0_datasr_reg;
  assign dmi0_addrsr_update = \$391 ;
  assign dmi0_addrsr_shift = \$387 ;
  assign dmi0_addrsr_capture = \$383 ;
  assign dmi0_addrsr_isir = \$379 ;
  assign dmi0_addrsr__o = dmi0_addrsr_reg;
  assign jtag_wb_datasr_update = \$373 ;
  assign jtag_wb_datasr_shift = \$369 ;
  assign jtag_wb_datasr_capture = \$365 ;
  assign jtag_wb_datasr_isir = { \$361 , \$359  };
  assign jtag_wb_datasr__o = jtag_wb_datasr_reg;
  assign jtag_wb_addrsr_update = \$353 ;
  assign jtag_wb_addrsr_shift = \$349 ;
  assign jtag_wb_addrsr_capture = \$345 ;
  assign jtag_wb_addrsr_isir = \$341 ;
  assign jtag_wb_addrsr__o = jtag_wb_addrsr_reg;
  assign sr0_update = \$335 ;
  assign sr0_shift = \$331 ;
  assign sr0_capture = \$327 ;
  assign sr0_isir = \$323 ;
  assign sr0__o = sr0_reg;
  assign eint_2__core__i = \$309 ;
  assign eint_1__core__i = \$307 ;
  assign eint_0__core__i = \$305 ;
  assign mtwi_scl__pad__o = \$303 ;
  assign mtwi_sda__pad__oe = \$301 ;
  assign mtwi_sda__pad__o = \$299 ;
  assign mtwi_sda__core__i = \$297 ;
  assign gpio_s7__pad__oe = \$295 ;
  assign gpio_s7__pad__o = \$293 ;
  assign gpio_s7__core__i = \$291 ;
  assign gpio_s6__pad__oe = \$289 ;
  assign gpio_s6__pad__o = \$287 ;
  assign gpio_s6__core__i = \$285 ;
  assign gpio_s5__pad__oe = \$283 ;
  assign gpio_s5__pad__o = \$281 ;
  assign gpio_s5__core__i = \$279 ;
  assign gpio_s4__pad__oe = \$277 ;
  assign gpio_s4__pad__o = \$275 ;
  assign gpio_s4__core__i = \$273 ;
  assign gpio_s3__pad__oe = \$271 ;
  assign gpio_s3__pad__o = \$269 ;
  assign gpio_s3__core__i = \$267 ;
  assign gpio_s2__pad__oe = \$265 ;
  assign gpio_s2__pad__o = \$263 ;
  assign gpio_s2__core__i = \$261 ;
  assign gpio_s1__pad__oe = \$259 ;
  assign gpio_s1__pad__o = \$257 ;
  assign gpio_s1__core__i = \$255 ;
  assign gpio_s0__pad__oe = \$253 ;
  assign gpio_s0__pad__o = \$251 ;
  assign gpio_s0__core__i = \$249 ;
  assign gpio_e15__pad__oe = \$247 ;
  assign gpio_e15__pad__o = \$245 ;
  assign gpio_e15__core__i = \$243 ;
  assign gpio_e14__pad__oe = \$241 ;
  assign gpio_e14__pad__o = \$239 ;
  assign gpio_e14__core__i = \$237 ;
  assign gpio_e13__pad__oe = \$235 ;
  assign gpio_e13__pad__o = \$233 ;
  assign gpio_e13__core__i = \$231 ;
  assign gpio_e12__pad__oe = \$229 ;
  assign gpio_e12__pad__o = \$227 ;
  assign gpio_e12__core__i = \$225 ;
  assign gpio_e11__pad__oe = \$223 ;
  assign gpio_e11__pad__o = \$221 ;
  assign gpio_e11__core__i = \$219 ;
  assign gpio_e10__pad__oe = \$217 ;
  assign gpio_e10__pad__o = \$215 ;
  assign gpio_e10__core__i = \$213 ;
  assign gpio_e9__pad__oe = \$211 ;
  assign gpio_e9__pad__o = \$209 ;
  assign gpio_e9__core__i = \$207 ;
  assign gpio_e8__pad__oe = \$205 ;
  assign gpio_e8__pad__o = \$203 ;
  assign gpio_e8__core__i = \$201 ;
  assign sdr_dq_15__pad__oe = \$199 ;
  assign sdr_dq_15__pad__o = \$197 ;
  assign sdr_dq_15__core__i = \$195 ;
  assign sdr_dq_14__pad__oe = \$193 ;
  assign sdr_dq_14__pad__o = \$191 ;
  assign sdr_dq_14__core__i = \$189 ;
  assign sdr_dq_13__pad__oe = \$187 ;
  assign sdr_dq_13__pad__o = \$185 ;
  assign sdr_dq_13__core__i = \$183 ;
  assign sdr_dq_12__pad__oe = \$181 ;
  assign sdr_dq_12__pad__o = \$179 ;
  assign sdr_dq_12__core__i = \$177 ;
  assign sdr_dq_11__pad__oe = \$175 ;
  assign sdr_dq_11__pad__o = \$173 ;
  assign sdr_dq_11__core__i = \$171 ;
  assign sdr_dq_10__pad__oe = \$169 ;
  assign sdr_dq_10__pad__o = \$167 ;
  assign sdr_dq_10__core__i = \$165 ;
  assign sdr_dq_9__pad__oe = \$163 ;
  assign sdr_dq_9__pad__o = \$161 ;
  assign sdr_dq_9__core__i = \$159 ;
  assign sdr_dq_8__pad__oe = \$157 ;
  assign sdr_dq_8__pad__o = \$155 ;
  assign sdr_dq_8__core__i = \$153 ;
  assign sdr_dm_1__pad__o = \$151 ;
  assign sdr_a_12__pad__o = \$149 ;
  assign sdr_a_11__pad__o = \$147 ;
  assign sdr_a_10__pad__o = \$145 ;
  assign sdr_cs_n__pad__o = \$143 ;
  assign sdr_we_n__pad__o = \$141 ;
  assign sdr_cas_n__pad__o = \$139 ;
  assign sdr_ras_n__pad__o = \$137 ;
  assign sdr_cke__pad__o = \$135 ;
  assign sdr_clock__pad__o = \$133 ;
  assign sdr_ba_1__pad__o = \$131 ;
  assign sdr_ba_0__pad__o = \$129 ;
  assign sdr_a_9__pad__o = \$127 ;
  assign sdr_a_8__pad__o = \$125 ;
  assign sdr_a_7__pad__o = \$123 ;
  assign sdr_a_6__pad__o = \$121 ;
  assign sdr_a_5__pad__o = \$119 ;
  assign sdr_a_4__pad__o = \$117 ;
  assign sdr_a_3__pad__o = \$115 ;
  assign sdr_a_2__pad__o = \$113 ;
  assign sdr_a_1__pad__o = \$111 ;
  assign sdr_a_0__pad__o = \$109 ;
  assign sdr_dq_7__pad__oe = \$107 ;
  assign sdr_dq_7__pad__o = \$105 ;
  assign sdr_dq_7__core__i = \$103 ;
  assign sdr_dq_6__pad__oe = \$101 ;
  assign sdr_dq_6__pad__o = \$99 ;
  assign sdr_dq_6__core__i = \$97 ;
  assign sdr_dq_5__pad__oe = \$95 ;
  assign sdr_dq_5__pad__o = \$93 ;
  assign sdr_dq_5__core__i = \$91 ;
  assign sdr_dq_4__pad__oe = \$89 ;
  assign sdr_dq_4__pad__o = \$87 ;
  assign sdr_dq_4__core__i = \$85 ;
  assign sdr_dq_3__pad__oe = \$83 ;
  assign sdr_dq_3__pad__o = \$81 ;
  assign sdr_dq_3__core__i = \$79 ;
  assign sdr_dq_2__pad__oe = \$77 ;
  assign sdr_dq_2__pad__o = \$75 ;
  assign sdr_dq_2__core__i = \$73 ;
  assign sdr_dq_1__pad__oe = \$71 ;
  assign sdr_dq_1__pad__o = \$69 ;
  assign sdr_dq_1__core__i = \$67 ;
  assign sdr_dq_0__pad__oe = \$65 ;
  assign sdr_dq_0__pad__o = \$63 ;
  assign sdr_dq_0__core__i = \$61 ;
  assign sdr_dm_0__pad__o = \$59 ;
  assign mspi0_miso__core__i = \$57 ;
  assign mspi0_mosi__pad__o = \$55 ;
  assign mspi0_cs_n__pad__o = \$53 ;
  assign mspi0_clk__pad__o = \$51 ;
  assign io_bd2core = \$49 ;
  assign io_bd2io = \$47 ;
  assign io_update = \$45 ;
  assign io_shift = \$31 ;
  assign io_capture = \$17 ;
  assign _idblock_id_bypass = \$9 ;
  assign _idblock_select_id = \$7 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:140640.1-140829.10" *)
module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [44:0] dbus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [63:0] dbus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [63:0] dbus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [7:0] dbus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [95:0] ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  output ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  output ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  input [3:0] ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  input ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  input ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [47:0] pimem_ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pimem_ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  wire pimem_ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  wire pimem_ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  wire [3:0] pimem_ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \pimem_ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  wire pimem_ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  wire pimem_ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pimem_ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pimem_ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] pimem_ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire pimem_ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *)
  wire [63:0] pimem_m_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *)
  wire pimem_m_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *)
  wire [47:0] pimem_x_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *)
  wire pimem_x_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *)
  wire pimem_x_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *)
  wire [7:0] pimem_x_mask_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *)
  wire [63:0] pimem_x_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *)
  wire pimem_x_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *)
  wire pimem_x_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  input wb_dcache_en;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:140745.12-140779.4" *)
  \l0$130  l0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .ldst_port0_addr_i(ldst_port0_addr_i),
    .\ldst_port0_addr_i$12 (pimem_ldst_port0_addr_i),
    .ldst_port0_addr_i_ok(ldst_port0_addr_i_ok),
    .\ldst_port0_addr_i_ok$13 (pimem_ldst_port0_addr_i_ok),
    .ldst_port0_addr_ok_o(ldst_port0_addr_ok_o),
    .\ldst_port0_addr_ok_o$14 (pimem_ldst_port0_addr_ok_o),
    .ldst_port0_busy_o(ldst_port0_busy_o),
    .\ldst_port0_busy_o$10 (pimem_ldst_port0_busy_o),
    .ldst_port0_data_len(ldst_port0_data_len),
    .\ldst_port0_data_len$11 (pimem_ldst_port0_data_len),
    .\ldst_port0_exc_$signal (\ldst_port0_exc_$signal ),
    .\ldst_port0_exc_$signal$1 (\ldst_port0_exc_$signal$1 ),
    .\ldst_port0_exc_$signal$19 (\pimem_ldst_port0_exc_$signal ),
    .\ldst_port0_exc_$signal$2 (\ldst_port0_exc_$signal$2 ),
    .\ldst_port0_exc_$signal$3 (\ldst_port0_exc_$signal$3 ),
    .\ldst_port0_exc_$signal$4 (\ldst_port0_exc_$signal$4 ),
    .\ldst_port0_exc_$signal$5 (\ldst_port0_exc_$signal$5 ),
    .\ldst_port0_exc_$signal$6 (\ldst_port0_exc_$signal$6 ),
    .\ldst_port0_exc_$signal$7 (\ldst_port0_exc_$signal$7 ),
    .ldst_port0_is_ld_i(ldst_port0_is_ld_i),
    .\ldst_port0_is_ld_i$8 (pimem_ldst_port0_is_ld_i),
    .ldst_port0_is_st_i(ldst_port0_is_st_i),
    .\ldst_port0_is_st_i$9 (pimem_ldst_port0_is_st_i),
    .ldst_port0_ld_data_o(ldst_port0_ld_data_o),
    .\ldst_port0_ld_data_o$15 (pimem_ldst_port0_ld_data_o),
    .ldst_port0_ld_data_o_ok(ldst_port0_ld_data_o_ok),
    .\ldst_port0_ld_data_o_ok$16 (pimem_ldst_port0_ld_data_o_ok),
    .ldst_port0_st_data_i(ldst_port0_st_data_i),
    .\ldst_port0_st_data_i$18 (pimem_ldst_port0_st_data_i),
    .ldst_port0_st_data_i_ok(ldst_port0_st_data_i_ok),
    .\ldst_port0_st_data_i_ok$17 (pimem_ldst_port0_st_data_i_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:140780.9-140802.4" *)
  lsmem lsmem (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dbus__ack(dbus__ack),
    .dbus__adr(dbus__adr),
    .dbus__cyc(dbus__cyc),
    .dbus__dat_r(dbus__dat_r),
    .dbus__dat_w(dbus__dat_w),
    .dbus__err(dbus__err),
    .dbus__sel(dbus__sel),
    .dbus__stb(dbus__stb),
    .dbus__we(dbus__we),
    .m_ld_data_o(pimem_m_ld_data_o),
    .m_valid_i(pimem_m_valid_i),
    .wb_dcache_en(wb_dcache_en),
    .x_addr_i(pimem_x_addr_i),
    .x_busy_o(pimem_x_busy_o),
    .x_ld_i(pimem_x_ld_i),
    .x_mask_i(pimem_x_mask_i),
    .x_st_data_i(pimem_x_st_data_i),
    .x_st_i(pimem_x_st_i),
    .x_valid_i(pimem_x_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:140803.9-140827.4" *)
  pimem pimem (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .ldst_port0_addr_i(pimem_ldst_port0_addr_i),
    .ldst_port0_addr_i_ok(pimem_ldst_port0_addr_i_ok),
    .ldst_port0_addr_ok_o(pimem_ldst_port0_addr_ok_o),
    .ldst_port0_busy_o(pimem_ldst_port0_busy_o),
    .ldst_port0_data_len(pimem_ldst_port0_data_len),
    .\ldst_port0_exc_$signal (\pimem_ldst_port0_exc_$signal ),
    .ldst_port0_is_ld_i(pimem_ldst_port0_is_ld_i),
    .ldst_port0_is_st_i(pimem_ldst_port0_is_st_i),
    .ldst_port0_ld_data_o(pimem_ldst_port0_ld_data_o),
    .ldst_port0_ld_data_o_ok(pimem_ldst_port0_ld_data_o_ok),
    .ldst_port0_st_data_i(pimem_ldst_port0_st_data_i),
    .ldst_port0_st_data_i_ok(pimem_ldst_port0_st_data_i_ok),
    .m_ld_data_o(pimem_m_ld_data_o),
    .m_valid_i(pimem_m_valid_i),
    .x_addr_i(pimem_x_addr_i),
    .x_busy_o(pimem_x_busy_o),
    .x_ld_i(pimem_x_ld_i),
    .x_mask_i(pimem_x_mask_i),
    .x_st_data_i(pimem_x_st_data_i),
    .x_st_i(pimem_x_st_i),
    .x_valid_i(pimem_x_valid_i)
  );
  assign \pimem_ldst_port0_exc_$signal  = 1'h0;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.l0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:140833.1-141241.10" *)
module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, \ldst_port0_is_ld_i$8 , \ldst_port0_is_st_i$9 , \ldst_port0_busy_o$10 , \ldst_port0_data_len$11 , \ldst_port0_addr_i$12 , \ldst_port0_addr_i_ok$13 , \ldst_port0_addr_ok_o$14 , \ldst_port0_ld_data_o$15 , \ldst_port0_ld_data_o_ok$16 , \ldst_port0_st_data_i_ok$17 , \ldst_port0_st_data_i$18 , \ldst_port0_exc_$signal$19 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:141096.3-141110.6" *)
  reg _00_;
  (* src = "libresoc.v:140996.3-140997.35" *)
  reg _01_;
  (* src = "libresoc.v:140854.7-140854.24" *)
  reg _02_;
  (* src = "libresoc.v:141151.3-141160.6" *)
  reg _03_;
  (* src = "libresoc.v:141141.3-141150.6" *)
  reg _04_;
  (* src = "libresoc.v:140834.7-140834.20" *)
  reg _05_;
  (* src = "libresoc.v:141017.3-141026.6" *)
  reg [47:0] _06_;
  (* src = "libresoc.v:141027.3-141036.6" *)
  reg _07_;
  (* src = "libresoc.v:141069.3-141078.6" *)
  reg _08_;
  (* src = "libresoc.v:141059.3-141068.6" *)
  reg _09_;
  (* src = "libresoc.v:141131.3-141140.6" *)
  reg _10_;
  (* src = "libresoc.v:141206.3-141215.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _12_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _13_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _14_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _15_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _16_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _17_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _18_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _19_;
  (* src = "libresoc.v:141216.3-141225.6" *)
  reg _20_;
  (* src = "libresoc.v:141186.3-141195.6" *)
  reg _21_;
  (* src = "libresoc.v:141196.3-141205.6" *)
  reg _22_;
  (* src = "libresoc.v:141048.3-141058.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:141048.3-141058.6" *)
  reg _24_;
  (* src = "libresoc.v:141121.3-141130.6" *)
  reg _25_;
  (* src = "libresoc.v:141111.3-141120.6" *)
  reg _26_;
  (* src = "libresoc.v:141037.3-141047.6" *)
  reg [63:0] _27_;
  (* src = "libresoc.v:141037.3-141047.6" *)
  reg _28_;
  (* src = "libresoc.v:140994.3-140995.36" *)
  reg _29_;
  (* src = "libresoc.v:141176.3-141185.6" *)
  reg _30_;
  (* src = "libresoc.v:141161.3-141175.6" *)
  reg _31_;
  (* src = "libresoc.v:141096.3-141110.6" *)
  reg _32_;
  (* src = "libresoc.v:141151.3-141160.6" *)
  reg _33_;
  (* src = "libresoc.v:141141.3-141150.6" *)
  reg _34_;
  (* src = "libresoc.v:141017.3-141026.6" *)
  reg [47:0] _35_;
  (* src = "libresoc.v:141027.3-141036.6" *)
  reg _36_;
  (* src = "libresoc.v:141069.3-141078.6" *)
  reg _37_;
  (* src = "libresoc.v:141059.3-141068.6" *)
  reg _38_;
  (* src = "libresoc.v:141131.3-141140.6" *)
  reg _39_;
  (* src = "libresoc.v:141206.3-141215.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _41_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _42_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _43_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _44_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _45_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _46_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _47_;
  (* src = "libresoc.v:141079.3-141095.6" *)
  reg _48_;
  (* src = "libresoc.v:141216.3-141225.6" *)
  reg _49_;
  (* src = "libresoc.v:141186.3-141195.6" *)
  reg _50_;
  (* src = "libresoc.v:141196.3-141205.6" *)
  reg _51_;
  (* src = "libresoc.v:141048.3-141058.6" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:141048.3-141058.6" *)
  reg _53_;
  (* src = "libresoc.v:141121.3-141130.6" *)
  reg _54_;
  (* src = "libresoc.v:141111.3-141120.6" *)
  reg _55_;
  (* src = "libresoc.v:141037.3-141047.6" *)
  reg [63:0] _56_;
  (* src = "libresoc.v:141037.3-141047.6" *)
  reg _57_;
  (* src = "libresoc.v:140981.7-140981.25" *)
  reg _58_;
  (* src = "libresoc.v:141176.3-141185.6" *)
  reg _59_;
  (* src = "libresoc.v:141161.3-141175.6" *)
  reg _60_;
  (* src = "libresoc.v:141096.3-141110.6" *)
  reg _61_;
  (* src = "libresoc.v:141161.3-141175.6" *)
  reg _62_;
  (* src = "libresoc.v:140992.18-140992.103" *)
  wire _63_;
  (* src = "libresoc.v:140993.18-140993.118" *)
  wire _64_;
  (* src = "libresoc.v:140990.18-140990.134" *)
  wire _65_;
  (* src = "libresoc.v:140991.18-140991.120" *)
  wire _66_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *)
  wire [95:0] \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" *)
  wire [95:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \idx_l$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \idx_l$23$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire idx_l_q_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg idx_l_r_idx_l;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg idx_l_s_idx_l;
  (* src = "libresoc.v:140834.7-140834.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [95:0] ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [47:0] \ldst_port0_addr_i$12 ;
  reg [47:0] \ldst_port0_addr_i$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \ldst_port0_addr_i_ok$13 ;
  reg \ldst_port0_addr_i_ok$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  output ldst_port0_addr_ok_o;
  reg ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  input \ldst_port0_addr_ok_o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  output ldst_port0_busy_o;
  reg ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  input \ldst_port0_busy_o$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *)
  reg ldst_port0_cache_paradox;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" *)
  wire \ldst_port0_cache_paradox$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  input [3:0] ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  output [3:0] \ldst_port0_data_len$11 ;
  reg [3:0] \ldst_port0_data_len$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal ;
  reg \ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$1 ;
  reg \ldst_port0_exc_$signal$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$2 ;
  reg \ldst_port0_exc_$signal$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$3 ;
  reg \ldst_port0_exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \ldst_port0_exc_$signal$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$4 ;
  reg \ldst_port0_exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$5 ;
  reg \ldst_port0_exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$6 ;
  reg \ldst_port0_exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  output \ldst_port0_exc_$signal$7 ;
  reg \ldst_port0_exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *)
  reg ldst_port0_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" *)
  wire \ldst_port0_go_die_i$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  input ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  output \ldst_port0_is_ld_i$8 ;
  reg \ldst_port0_is_ld_i$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  input ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  output \ldst_port0_is_st_i$9 ;
  reg \ldst_port0_is_st_i$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ldst_port0_ld_data_o;
  reg [63:0] ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] \ldst_port0_ld_data_o$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_ld_data_o_ok;
  reg ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input \ldst_port0_ld_data_o_ok$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *)
  reg ldst_port0_ldst_error;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" *)
  wire \ldst_port0_ldst_error$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *)
  reg ldst_port0_mmu_done;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" *)
  wire \ldst_port0_mmu_done$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \ldst_port0_st_data_i$18 ;
  reg [63:0] \ldst_port0_st_data_i$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \ldst_port0_st_data_i_ok$17 ;
  reg \ldst_port0_st_data_i_ok$17 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *)
  wire pick_i;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" *)
  wire pick_n;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" *)
  wire pick_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" *)
  reg reset_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" *)
  wire \reset_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire reset_l_q_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg reset_l_r_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg reset_l_s_reset;
  assign _63_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *) pick_n;
  assign _64_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *) \ldst_port0_busy_o$10 ;
  assign _65_ = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" *) ldst_port0_is_st_i;
  assign _66_ = idx_l_q_idx_l ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) pick_o : \idx_l$23 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:140998.9-141004.4" *)
  idx_l idx_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_idx_l(idx_l_q_idx_l),
    .r_idx_l(idx_l_r_idx_l),
    .s_idx_l(idx_l_s_idx_l)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:141005.8-141009.4" *)
  pick pick (
    .i(pick_i),
    .n(pick_n),
    .o(pick_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:141010.17-141016.4" *)
  \reset_l$131  reset_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_reset(reset_l_q_reset),
    .r_reset(reset_l_r_reset),
    .s_reset(reset_l_s_reset)
  );
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \idx_l$23  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _58_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      reset_delay <= _58_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = reset_l_q_reset;
  end
  always @(posedge coresync_clk) begin
      reset_delay <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \idx_l$23$next ;
  end
  always @(posedge coresync_clk) begin
      \idx_l$23  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _35_;
    (* src = "libresoc.v:141018.5-141018.29" *)
    casez (\initial )
      /* src = "libresoc.v:141018.9-141018.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _35_ = \$32 [47:0];
        end
      default:
          _35_ = 48'h000000000000;
    endcase
  end
  always @* begin
      \ldst_port0_addr_i$12  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _36_;
    (* src = "libresoc.v:141028.5-141028.29" *)
    casez (\initial )
      /* src = "libresoc.v:141028.9-141028.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _36_ = ldst_port0_addr_i_ok;
        end
      default:
          _36_ = 1'h0;
    endcase
  end
  always @* begin
      \ldst_port0_addr_i_ok$13  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _56_;
    _28_ = _57_;
    (* src = "libresoc.v:141038.5-141038.29" *)
    casez (\initial )
      /* src = "libresoc.v:141038.9-141038.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _57_, _56_ } = { ldst_port0_st_data_i_ok, ldst_port0_st_data_i };
        end
      default:
        begin
          _56_ = 64'h0000000000000000;
          _57_ = 1'h0;
        end
    endcase
  end
  always @* begin
      \ldst_port0_st_data_i$18  <= _27_;
      \ldst_port0_st_data_i_ok$17  <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _52_;
    _24_ = _53_;
    (* src = "libresoc.v:141049.5-141049.29" *)
    casez (\initial )
      /* src = "libresoc.v:141049.9-141049.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _53_, _52_ } = { \ldst_port0_ld_data_o_ok$16 , \ldst_port0_ld_data_o$15  };
        end
      default:
        begin
          _52_ = 64'h0000000000000000;
          _53_ = 1'h0;
        end
    endcase
  end
  always @* begin
      ldst_port0_ld_data_o <= _23_;
      ldst_port0_ld_data_o_ok <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _38_;
    (* src = "libresoc.v:141060.5-141060.29" *)
    casez (\initial )
      /* src = "libresoc.v:141060.9-141060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _38_ = \ldst_port0_busy_o$10 ;
        end
      default:
          _38_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_busy_o <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _37_;
    (* src = "libresoc.v:141070.5-141070.29" *)
    casez (\initial )
      /* src = "libresoc.v:141070.9-141070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = \ldst_port0_addr_ok_o$14 ;
        end
      default:
          _37_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_addr_ok_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = _48_;
    _12_ = _41_;
    _13_ = _42_;
    _14_ = _43_;
    _15_ = _44_;
    _16_ = _45_;
    _17_ = _46_;
    _18_ = _47_;
    (* src = "libresoc.v:141080.5-141080.29" *)
    casez (\initial )
      /* src = "libresoc.v:141080.9-141080.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _47_, _46_, _45_, _44_, _43_, _42_, _41_, _48_ } = { \ldst_port0_exc_$signal$39 , \ldst_port0_exc_$signal$38 , \ldst_port0_exc_$signal$37 , \ldst_port0_exc_$signal$36 , \ldst_port0_exc_$signal$35 , \ldst_port0_exc_$signal$34 , \ldst_port0_exc_$signal$33 , \ldst_port0_exc_$signal$19  };
        end
      default:
        begin
          _48_ = 1'h0;
          _41_ = 1'h0;
          _42_ = 1'h0;
          _43_ = 1'h0;
          _44_ = 1'h0;
          _45_ = 1'h0;
          _46_ = 1'h0;
          _47_ = 1'h0;
        end
    endcase
  end
  always @* begin
      \ldst_port0_exc_$signal  <= _19_;
      \ldst_port0_exc_$signal$1  <= _12_;
      \ldst_port0_exc_$signal$2  <= _13_;
      \ldst_port0_exc_$signal$3  <= _14_;
      \ldst_port0_exc_$signal$4  <= _15_;
      \ldst_port0_exc_$signal$5  <= _16_;
      \ldst_port0_exc_$signal$6  <= _17_;
      \ldst_port0_exc_$signal$7  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _61_;
    (* src = "libresoc.v:141097.5-141097.29" *)
    casez (\initial )
      /* src = "libresoc.v:141097.9-141097.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = pick_o;
        end
      default:
          _32_ = \idx_l$23 ;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _61_ = 1'h0;
        end
      default:
          _61_ = _32_;
    endcase
  end
  always @* begin
      \idx_l$23$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _55_;
    (* src = "libresoc.v:141112.5-141112.29" *)
    casez (\initial )
      /* src = "libresoc.v:141112.9-141112.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _55_ = \ldst_port0_mmu_done$40 ;
        end
      default:
          _55_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_mmu_done <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _54_;
    (* src = "libresoc.v:141122.5-141122.29" *)
    casez (\initial )
      /* src = "libresoc.v:141122.9-141122.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _54_ = \ldst_port0_ldst_error$41 ;
        end
      default:
          _54_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_ldst_error <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _39_;
    (* src = "libresoc.v:141132.5-141132.29" *)
    casez (\initial )
      /* src = "libresoc.v:141132.9-141132.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = \ldst_port0_cache_paradox$42 ;
        end
      default:
          _39_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_cache_paradox <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _34_;
    (* src = "libresoc.v:141142.5-141142.29" *)
    casez (\initial )
      /* src = "libresoc.v:141142.9-141142.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" *)
    casez (\$26 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = 1'h1;
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      idx_l_s_idx_l <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _33_;
    (* src = "libresoc.v:141152.5-141152.29" *)
    casez (\initial )
      /* src = "libresoc.v:141152.9-141152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = 1'h1;
        end
      default:
          _33_ = 1'h1;
    endcase
  end
  always @* begin
      idx_l_r_idx_l <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _60_;
    (* src = "libresoc.v:141162.5-141162.29" *)
    casez (\initial )
      /* src = "libresoc.v:141162.9-141162.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _60_ = _62_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" *)
          casez (\$28 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = 1'h1;
              end
            default:
                _62_ = 1'h0;
          endcase
        end
      default:
          _60_ = 1'h0;
    endcase
  end
  always @* begin
      reset_l_s_reset <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = _59_;
    (* src = "libresoc.v:141177.5-141177.29" *)
    casez (\initial )
      /* src = "libresoc.v:141177.9-141177.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 1'h1;
        end
      default:
          _59_ = 1'h0;
    endcase
  end
  always @* begin
      reset_l_r_reset <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = _50_;
    (* src = "libresoc.v:141187.5-141187.29" *)
    casez (\initial )
      /* src = "libresoc.v:141187.9-141187.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _50_ = ldst_port0_is_ld_i;
        end
      default:
          _50_ = 1'h0;
    endcase
  end
  always @* begin
      \ldst_port0_is_ld_i$8  <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _51_;
    (* src = "libresoc.v:141197.5-141197.29" *)
    casez (\initial )
      /* src = "libresoc.v:141197.9-141197.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _51_ = ldst_port0_is_st_i;
        end
      default:
          _51_ = 1'h0;
    endcase
  end
  always @* begin
      \ldst_port0_is_st_i$9  <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _40_;
    (* src = "libresoc.v:141207.5-141207.29" *)
    casez (\initial )
      /* src = "libresoc.v:141207.9-141207.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _40_ = ldst_port0_data_len;
        end
      default:
          _40_ = 4'h0;
    endcase
  end
  always @* begin
      \ldst_port0_data_len$11  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _49_;
    (* src = "libresoc.v:141217.5-141217.29" *)
    casez (\initial )
      /* src = "libresoc.v:141217.9-141217.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" *)
    casez (idx_l_q_idx_l)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _49_ = \ldst_port0_go_die_i$30 ;
        end
      default:
          _49_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_go_die_i <= _20_;
  end
  assign \$20  = _65_;
  assign \$24  = _66_;
  assign \$26  = _63_;
  assign \$28  = _64_;
  assign \$22  = \$24 ;
  assign \$32  = ldst_port0_addr_i;
  assign \ldst_port0_go_die_i$30  = 1'h0;
  assign \ldst_port0_exc_$signal$33  = 1'h0;
  assign \ldst_port0_exc_$signal$34  = 1'h0;
  assign \ldst_port0_exc_$signal$35  = 1'h0;
  assign \ldst_port0_exc_$signal$36  = 1'h0;
  assign \ldst_port0_exc_$signal$37  = 1'h0;
  assign \ldst_port0_exc_$signal$38  = 1'h0;
  assign \ldst_port0_exc_$signal$39  = 1'h0;
  assign \ldst_port0_mmu_done$40  = 1'h0;
  assign \ldst_port0_ldst_error$41  = 1'h0;
  assign \ldst_port0_cache_paradox$42  = 1'h0;
  assign \reset_delay$next  = reset_l_q_reset;
  assign pick_i = \$20 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.ld_active" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:141245.1-141303.10" *)
module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:141246.7-141246.20" *)
  reg _00_;
  (* src = "libresoc.v:141291.3-141299.6" *)
  reg _01_;
  (* src = "libresoc.v:141289.3-141290.27" *)
  reg _02_;
  (* src = "libresoc.v:141291.3-141299.6" *)
  reg _03_;
  (* src = "libresoc.v:141268.7-141268.19" *)
  reg _04_;
  (* src = "libresoc.v:141281.17-141281.96" *)
  wire _05_;
  (* src = "libresoc.v:141286.17-141286.96" *)
  wire _06_;
  (* src = "libresoc.v:141283.18-141283.99" *)
  wire _07_;
  (* src = "libresoc.v:141285.17-141285.98" *)
  wire _08_;
  (* src = "libresoc.v:141288.17-141288.98" *)
  wire _09_;
  (* src = "libresoc.v:141282.18-141282.104" *)
  wire _10_;
  (* src = "libresoc.v:141284.18-141284.105" *)
  wire _11_;
  (* src = "libresoc.v:141287.17-141287.103" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:141246.7-141246.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_ld_active;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_ld_active;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_ld_active;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_ld_active;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_ld_active;
  assign _11_ = q_ld_active | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_ld_active;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:141292.5-141292.29" *)
    casez (\initial )
      /* src = "libresoc.v:141292.9-141292.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_ld_active = \$15 ;
  assign qn_ld_active = \$13 ;
  assign q_ld_active = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:141307.1-142670.10" *)
module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, cu_wr__rel_o, cu_wr__go_i, o, ea, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, \ldst_port0_exc_$signal , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$7 , ldst_port0_addr_ok_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:142325.3-142333.6" *)
  reg _000_;
  (* src = "libresoc.v:142207.3-142208.39" *)
  reg _001_;
  (* src = "libresoc.v:142153.3-142154.21" *)
  reg _002_;
  (* src = "libresoc.v:142490.3-142499.6" *)
  reg [63:0] _003_;
  (* src = "libresoc.v:142500.3-142509.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:142480.3-142489.6" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:142155.3-142156.25" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:141308.7-141308.20" *)
  reg _007_;
  (* src = "libresoc.v:142555.3-142574.6" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:142519.3-142542.6" *)
  reg [63:0] _009_;
  (* src = "libresoc.v:142422.3-142431.6" *)
  reg [63:0] _010_;
  (* src = "libresoc.v:142163.3-142164.27" *)
  reg [63:0] _011_;
  (* src = "libresoc.v:142151.3-142152.33" *)
  reg [95:0] _012_;
  (* src = "libresoc.v:142510.3-142518.6" *)
  reg _013_;
  (* src = "libresoc.v:142149.3-142150.57" *)
  reg _014_;
  (* src = "libresoc.v:142599.3-142610.6" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:142370.3-142378.6" *)
  reg _016_;
  (* src = "libresoc.v:142197.3-142198.39" *)
  reg _017_;
  (* src = "libresoc.v:142298.3-142306.6" *)
  reg _018_;
  (* src = "libresoc.v:142213.3-142214.39" *)
  reg _019_;
  (* src = "libresoc.v:142289.3-142297.6" *)
  reg _020_;
  (* src = "libresoc.v:142215.3-142216.39" *)
  reg _021_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _022_;
  (* src = "libresoc.v:142189.3-142190.57" *)
  reg _023_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [3:0] _024_;
  (* src = "libresoc.v:142187.3-142188.49" *)
  reg [3:0] _025_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [13:0] _026_;
  (* src = "libresoc.v:142167.3-142168.47" *)
  reg [13:0] _027_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [63:0] _028_;
  (* src = "libresoc.v:142169.3-142170.61" *)
  reg [63:0] _029_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _030_;
  (* src = "libresoc.v:142171.3-142172.57" *)
  reg _031_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [31:0] _032_;
  (* src = "libresoc.v:142195.3-142196.41" *)
  reg [31:0] _033_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [6:0] _034_;
  (* src = "libresoc.v:142165.3-142166.51" *)
  reg [6:0] _035_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _036_;
  (* src = "libresoc.v:142183.3-142184.49" *)
  reg _037_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _038_;
  (* src = "libresoc.v:142185.3-142186.51" *)
  reg _039_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [1:0] _040_;
  (* src = "libresoc.v:142193.3-142194.51" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _042_;
  (* src = "libresoc.v:142179.3-142180.45" *)
  reg _043_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _044_;
  (* src = "libresoc.v:142181.3-142182.45" *)
  reg _045_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _046_;
  (* src = "libresoc.v:142177.3-142178.45" *)
  reg _047_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _048_;
  (* src = "libresoc.v:142175.3-142176.45" *)
  reg _049_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _050_;
  (* src = "libresoc.v:142191.3-142192.55" *)
  reg _051_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _052_;
  (* src = "libresoc.v:142173.3-142174.45" *)
  reg _053_;
  (* src = "libresoc.v:142217.3-142218.28" *)
  reg _054_;
  (* src = "libresoc.v:142543.3-142554.6" *)
  reg [63:0] _055_;
  (* src = "libresoc.v:142316.3-142324.6" *)
  reg [2:0] _056_;
  (* src = "libresoc.v:142209.3-142210.39" *)
  reg [2:0] _057_;
  (* src = "libresoc.v:142307.3-142315.6" *)
  reg [2:0] _058_;
  (* src = "libresoc.v:142211.3-142212.39" *)
  reg [2:0] _059_;
  (* src = "libresoc.v:142432.3-142447.6" *)
  reg [63:0] _060_;
  (* src = "libresoc.v:142161.3-142162.29" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:142448.3-142463.6" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:142159.3-142160.29" *)
  reg [63:0] _063_;
  (* src = "libresoc.v:142464.3-142479.6" *)
  reg [63:0] _064_;
  (* src = "libresoc.v:142157.3-142158.29" *)
  reg [63:0] _065_;
  (* src = "libresoc.v:142575.3-142598.6" *)
  reg [63:0] _066_;
  (* src = "libresoc.v:142361.3-142369.6" *)
  reg _067_;
  (* src = "libresoc.v:142199.3-142200.39" *)
  reg _068_;
  (* src = "libresoc.v:142352.3-142360.6" *)
  reg _069_;
  (* src = "libresoc.v:142201.3-142202.39" *)
  reg _070_;
  (* src = "libresoc.v:142343.3-142351.6" *)
  reg _071_;
  (* src = "libresoc.v:142203.3-142204.39" *)
  reg _072_;
  (* src = "libresoc.v:142334.3-142342.6" *)
  reg _073_;
  (* src = "libresoc.v:142205.3-142206.39" *)
  reg _074_;
  (* src = "libresoc.v:142325.3-142333.6" *)
  reg _075_;
  (* src = "libresoc.v:141504.7-141504.25" *)
  reg _076_;
  (* src = "libresoc.v:141518.7-141518.20" *)
  reg _077_;
  (* src = "libresoc.v:142490.3-142499.6" *)
  reg [63:0] _078_;
  (* src = "libresoc.v:142500.3-142509.6" *)
  reg [63:0] _079_;
  (* src = "libresoc.v:142480.3-142489.6" *)
  reg [63:0] _080_;
  (* src = "libresoc.v:141564.14-141564.41" *)
  reg [63:0] _081_;
  (* src = "libresoc.v:142555.3-142574.6" *)
  reg [63:0] _082_;
  (* src = "libresoc.v:142519.3-142542.6" *)
  reg [63:0] _083_;
  (* src = "libresoc.v:142422.3-142431.6" *)
  reg [63:0] _084_;
  (* src = "libresoc.v:141594.14-141594.42" *)
  reg [63:0] _085_;
  (* src = "libresoc.v:141599.14-141599.62" *)
  reg [95:0] _086_;
  (* src = "libresoc.v:142510.3-142518.6" *)
  reg _087_;
  (* src = "libresoc.v:141604.7-141604.34" *)
  reg _088_;
  (* src = "libresoc.v:142599.3-142610.6" *)
  reg [63:0] _089_;
  (* src = "libresoc.v:142370.3-142378.6" *)
  reg _090_;
  (* src = "libresoc.v:141653.7-141653.25" *)
  reg _091_;
  (* src = "libresoc.v:142298.3-142306.6" *)
  reg _092_;
  (* src = "libresoc.v:141667.7-141667.25" *)
  reg _093_;
  (* src = "libresoc.v:142289.3-142297.6" *)
  reg _094_;
  (* src = "libresoc.v:141671.7-141671.25" *)
  reg _095_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _096_;
  (* src = "libresoc.v:141802.7-141802.34" *)
  reg _097_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [3:0] _098_;
  (* src = "libresoc.v:141806.13-141806.36" *)
  reg [3:0] _099_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [13:0] _100_;
  (* src = "libresoc.v:141825.14-141825.40" *)
  reg [13:0] _101_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [63:0] _102_;
  (* src = "libresoc.v:141829.14-141829.59" *)
  reg [63:0] _103_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _104_;
  (* src = "libresoc.v:141833.7-141833.34" *)
  reg _105_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [31:0] _106_;
  (* src = "libresoc.v:141837.14-141837.34" *)
  reg [31:0] _107_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [6:0] _108_;
  (* src = "libresoc.v:141916.13-141916.38" *)
  reg [6:0] _109_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _110_;
  (* src = "libresoc.v:141920.7-141920.30" *)
  reg _111_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _112_;
  (* src = "libresoc.v:141924.7-141924.31" *)
  reg _113_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [1:0] _114_;
  (* src = "libresoc.v:141933.13-141933.37" *)
  reg [1:0] _115_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _116_;
  (* src = "libresoc.v:141937.7-141937.28" *)
  reg _117_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _118_;
  (* src = "libresoc.v:141941.7-141941.28" *)
  reg _119_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _120_;
  (* src = "libresoc.v:141945.7-141945.28" *)
  reg _121_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _122_;
  (* src = "libresoc.v:141949.7-141949.28" *)
  reg _123_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _124_;
  (* src = "libresoc.v:141953.7-141953.33" *)
  reg _125_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _126_;
  (* src = "libresoc.v:141957.7-141957.28" *)
  reg _127_;
  (* src = "libresoc.v:141961.7-141961.21" *)
  reg _128_;
  (* src = "libresoc.v:142543.3-142554.6" *)
  reg [63:0] _129_;
  (* src = "libresoc.v:142316.3-142324.6" *)
  reg [2:0] _130_;
  (* src = "libresoc.v:142003.13-142003.31" *)
  reg [2:0] _131_;
  (* src = "libresoc.v:142307.3-142315.6" *)
  reg [2:0] _132_;
  (* src = "libresoc.v:142007.13-142007.31" *)
  reg [2:0] _133_;
  (* src = "libresoc.v:142432.3-142447.6" *)
  reg [63:0] _134_;
  (* src = "libresoc.v:142011.14-142011.43" *)
  reg [63:0] _135_;
  (* src = "libresoc.v:142448.3-142463.6" *)
  reg [63:0] _136_;
  (* src = "libresoc.v:142015.14-142015.43" *)
  reg [63:0] _137_;
  (* src = "libresoc.v:142464.3-142479.6" *)
  reg [63:0] _138_;
  (* src = "libresoc.v:142019.14-142019.43" *)
  reg [63:0] _139_;
  (* src = "libresoc.v:142575.3-142598.6" *)
  reg [63:0] _140_;
  (* src = "libresoc.v:142361.3-142369.6" *)
  reg _141_;
  (* src = "libresoc.v:142029.7-142029.25" *)
  reg _142_;
  (* src = "libresoc.v:142352.3-142360.6" *)
  reg _143_;
  (* src = "libresoc.v:142039.7-142039.25" *)
  reg _144_;
  (* src = "libresoc.v:142343.3-142351.6" *)
  reg _145_;
  (* src = "libresoc.v:142043.7-142043.25" *)
  reg _146_;
  (* src = "libresoc.v:142334.3-142342.6" *)
  reg _147_;
  (* src = "libresoc.v:142053.7-142053.25" *)
  reg _148_;
  (* src = "libresoc.v:142555.3-142574.6" *)
  reg [63:0] _149_;
  (* src = "libresoc.v:142519.3-142542.6" *)
  reg [63:0] _150_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _151_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [3:0] _152_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [13:0] _153_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [63:0] _154_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _155_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [31:0] _156_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [6:0] _157_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _158_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _159_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [1:0] _160_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _161_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _162_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _163_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _164_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _165_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _166_;
  (* src = "libresoc.v:142432.3-142447.6" *)
  reg [63:0] _167_;
  (* src = "libresoc.v:142448.3-142463.6" *)
  reg [63:0] _168_;
  (* src = "libresoc.v:142464.3-142479.6" *)
  reg [63:0] _169_;
  (* src = "libresoc.v:142575.3-142598.6" *)
  reg [63:0] _170_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg [63:0] _171_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _172_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _173_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _174_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _175_;
  (* src = "libresoc.v:142379.3-142421.6" *)
  reg _176_;
  (* src = "libresoc.v:142135.18-142135.124" *)
  wire [64:0] _177_;
  (* src = "libresoc.v:142058.19-142058.118" *)
  wire _178_;
  (* src = "libresoc.v:142059.19-142059.125" *)
  wire _179_;
  (* src = "libresoc.v:142060.19-142060.120" *)
  wire _180_;
  (* src = "libresoc.v:142061.19-142061.125" *)
  wire _181_;
  (* src = "libresoc.v:142062.19-142062.118" *)
  wire _182_;
  (* src = "libresoc.v:142064.19-142064.119" *)
  wire _183_;
  (* src = "libresoc.v:142065.19-142065.123" *)
  wire _184_;
  (* src = "libresoc.v:142066.19-142066.123" *)
  wire _185_;
  (* src = "libresoc.v:142067.19-142067.120" *)
  wire _186_;
  (* src = "libresoc.v:142068.19-142068.123" *)
  wire _187_;
  (* src = "libresoc.v:142069.19-142069.119" *)
  wire _188_;
  (* src = "libresoc.v:142070.19-142070.123" *)
  wire _189_;
  (* src = "libresoc.v:142071.19-142071.125" *)
  wire _190_;
  (* src = "libresoc.v:142073.19-142073.116" *)
  wire _191_;
  (* src = "libresoc.v:142075.19-142075.120" *)
  wire _192_;
  (* src = "libresoc.v:142076.19-142076.123" *)
  wire _193_;
  (* src = "libresoc.v:142080.19-142080.125" *)
  wire _194_;
  (* src = "libresoc.v:142081.19-142081.123" *)
  wire _195_;
  (* src = "libresoc.v:142086.19-142086.116" *)
  wire _196_;
  (* src = "libresoc.v:142088.19-142088.116" *)
  wire _197_;
  (* src = "libresoc.v:142091.19-142091.118" *)
  wire _198_;
  (* src = "libresoc.v:142093.19-142093.125" *)
  wire _199_;
  (* src = "libresoc.v:142096.19-142096.160" *)
  wire [2:0] _200_;
  (* src = "libresoc.v:142097.19-142097.122" *)
  wire _201_;
  (* src = "libresoc.v:142098.19-142098.122" *)
  wire _202_;
  (* src = "libresoc.v:142100.19-142100.122" *)
  wire _203_;
  (* src = "libresoc.v:142112.18-142112.123" *)
  wire _204_;
  (* src = "libresoc.v:142113.18-142113.123" *)
  wire _205_;
  (* src = "libresoc.v:142115.18-142115.114" *)
  wire _206_;
  (* src = "libresoc.v:142117.18-142117.113" *)
  wire _207_;
  (* src = "libresoc.v:142120.18-142120.113" *)
  wire _208_;
  (* src = "libresoc.v:142124.18-142124.113" *)
  wire _209_;
  (* src = "libresoc.v:142127.18-142127.119" *)
  wire _210_;
  (* src = "libresoc.v:142136.18-142136.150" *)
  wire [2:0] _211_;
  (* src = "libresoc.v:142138.18-142138.113" *)
  wire [2:0] _212_;
  (* src = "libresoc.v:142140.18-142140.113" *)
  wire [2:0] _213_;
  (* src = "libresoc.v:142141.18-142141.127" *)
  wire _214_;
  (* src = "libresoc.v:142142.18-142142.117" *)
  wire _215_;
  (* src = "libresoc.v:142147.18-142147.117" *)
  wire _216_;
  (* src = "libresoc.v:142072.19-142072.127" *)
  wire _217_;
  (* src = "libresoc.v:142092.19-142092.127" *)
  wire _218_;
  (* src = "libresoc.v:142094.19-142094.127" *)
  wire _219_;
  (* src = "libresoc.v:142105.19-142105.126" *)
  wire _220_;
  (* src = "libresoc.v:142110.18-142110.127" *)
  wire _221_;
  (* src = "libresoc.v:142111.18-142111.127" *)
  wire _222_;
  (* src = "libresoc.v:142119.18-142119.126" *)
  wire _223_;
  (* src = "libresoc.v:142123.18-142123.126" *)
  wire _224_;
  (* src = "libresoc.v:142099.19-142099.110" *)
  wire [95:0] _225_;
  (* src = "libresoc.v:142101.19-142101.116" *)
  wire [63:0] _226_;
  (* src = "libresoc.v:142106.19-142106.102" *)
  wire [63:0] _227_;
  (* src = "libresoc.v:142084.19-142084.109" *)
  wire _228_;
  (* src = "libresoc.v:142089.19-142089.121" *)
  wire _229_;
  (* src = "libresoc.v:142114.18-142114.112" *)
  wire _230_;
  (* src = "libresoc.v:142116.18-142116.110" *)
  wire _231_;
  (* src = "libresoc.v:142118.18-142118.120" *)
  wire _232_;
  (* src = "libresoc.v:142122.18-142122.120" *)
  wire _233_;
  (* src = "libresoc.v:142137.18-142137.143" *)
  wire [1:0] _234_;
  (* src = "libresoc.v:142139.18-142139.115" *)
  wire [2:0] _235_;
  (* src = "libresoc.v:142146.18-142146.107" *)
  wire _236_;
  (* src = "libresoc.v:142148.18-142148.118" *)
  wire _237_;
  (* src = "libresoc.v:142063.18-142063.124" *)
  wire _238_;
  (* src = "libresoc.v:142074.18-142074.129" *)
  wire _239_;
  (* src = "libresoc.v:142077.19-142077.123" *)
  wire _240_;
  (* src = "libresoc.v:142078.19-142078.125" *)
  wire _241_;
  (* src = "libresoc.v:142079.19-142079.125" *)
  wire _242_;
  (* src = "libresoc.v:142082.19-142082.132" *)
  wire _243_;
  (* src = "libresoc.v:142083.19-142083.126" *)
  wire _244_;
  (* src = "libresoc.v:142085.18-142085.129" *)
  wire _245_;
  (* src = "libresoc.v:142087.19-142087.125" *)
  wire _246_;
  (* src = "libresoc.v:142090.19-142090.119" *)
  wire _247_;
  (* src = "libresoc.v:142095.18-142095.126" *)
  wire _248_;
  (* src = "libresoc.v:142103.18-142103.156" *)
  wire [2:0] _249_;
  (* src = "libresoc.v:142109.18-142109.126" *)
  wire _250_;
  (* src = "libresoc.v:142121.18-142121.116" *)
  wire _251_;
  (* src = "libresoc.v:142125.18-142125.116" *)
  wire _252_;
  (* src = "libresoc.v:142126.18-142126.127" *)
  wire [1:0] _253_;
  (* src = "libresoc.v:142128.18-142128.118" *)
  wire _254_;
  (* src = "libresoc.v:142129.18-142129.118" *)
  wire _255_;
  (* src = "libresoc.v:142130.18-142130.114" *)
  wire _256_;
  (* src = "libresoc.v:142143.17-142143.124" *)
  wire _257_;
  (* src = "libresoc.v:142144.18-142144.132" *)
  wire _258_;
  (* src = "libresoc.v:142145.18-142145.134" *)
  wire _259_;
  (* src = "libresoc.v:142099.19-142099.110" *)
  wire [95:0] _260_;
  (* src = "libresoc.v:142101.19-142101.116" *)
  wire [63:0] _261_;
  (* src = "libresoc.v:142102.19-142102.148" *)
  wire [63:0] _262_;
  (* src = "libresoc.v:142104.19-142104.206" *)
  wire [63:0] _263_;
  (* src = "libresoc.v:142106.19-142106.102" *)
  wire [63:0] _264_;
  (* src = "libresoc.v:142107.19-142107.120" *)
  wire [63:0] _265_;
  (* src = "libresoc.v:142108.19-142108.150" *)
  wire [63:0] _266_;
  (* src = "libresoc.v:142131.18-142131.107" *)
  wire [63:0] _267_;
  (* src = "libresoc.v:142132.18-142132.112" *)
  wire [63:0] _268_;
  (* src = "libresoc.v:142133.18-142133.147" *)
  wire [63:0] _269_;
  (* src = "libresoc.v:142134.18-142134.155" *)
  wire [63:0] _270_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *)
  wire \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *)
  wire \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *)
  wire \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
  wire \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
  wire \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *)
  wire \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *)
  wire \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *)
  wire \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *)
  wire \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *)
  wire \$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *)
  wire \$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *)
  wire \$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *)
  wire \$132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *)
  wire \$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *)
  wire \$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *)
  wire \$138 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$140 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$142 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$144 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$147 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *)
  wire \$150 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *)
  wire \$152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *)
  wire \$154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
  wire \$156 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
  wire \$158 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *)
  wire \$160 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *)
  wire \$162 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *)
  wire \$164 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *)
  wire [2:0] \$166 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *)
  wire \$167 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *)
  wire [2:0] \$169 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *)
  wire \$171 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *)
  wire \$173 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *)
  wire [95:0] \$175 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *)
  wire \$177 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *)
  wire [2:0] \$18 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$186 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$188 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$190 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *)
  wire \$192 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$194 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$196 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *)
  wire [63:0] \$198 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *)
  wire [1:0] \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *)
  wire [1:0] \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *)
  wire [63:0] \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *)
  wire [63:0] \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *)
  wire [64:0] \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *)
  wire [64:0] \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *)
  wire [2:0] \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *)
  wire [1:0] \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *)
  wire [2:0] \$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *)
  wire [2:0] \$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *)
  wire [2:0] \$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *)
  wire \$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *)
  wire \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *)
  wire \$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
  wire \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *)
  wire \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *)
  wire \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" *)
  wire addr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *)
  wire [63:0] addr_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire adr_l_q_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg adr_l_r_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \adr_l_r_adr$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire adr_l_s_adr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  wire alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" *)
  wire [63:0] alu_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *)
  reg alu_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" *)
  wire \alu_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" *)
  wire alu_valid;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_ad__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_ad__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input cu_st__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output cu_st__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [1:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [1:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [1:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  reg [63:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ea;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] ea_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \ea_r$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$179 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$180 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$181 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$182 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$183 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$184 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \exc_$signal$185 ;
  (* src = "libresoc.v:141308.7-141308.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" *)
  wire ld_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" *)
  wire ld_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:281" *)
  reg [63:0] ldd_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:385" *)
  wire [63:0] ldd_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *)
  reg [63:0] lddata_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] ldo_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \ldo_r$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [95:0] ldst_port0_addr_i;
  reg [95:0] ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [95:0] \ldst_port0_addr_i$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_addr_i_ok;
  reg ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \ldst_port0_addr_i_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  input ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  input ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  output [3:0] ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  output ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  output ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ldst_port0_st_data_i;
  reg [63:0] ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" *)
  wire load_mem_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire lod_l_qn_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  wire lod_l_r_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire lod_l_s_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire lsd_l_q_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg lsd_l_r_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \lsd_l_r_lsd$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire lsd_l_s_lsd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" *)
  wire op_is_ld;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:267" *)
  wire op_is_st;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_ldst_ldst0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_ldst_ldst0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_ldst_ldst0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_ldst_ldst0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_ldst_ldst0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__is_signed;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_ldst_ldst0__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_ldst_ldst0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__byte_reverse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__byte_reverse$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] oper_r__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \oper_r__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] oper_r__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \oper_r__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] oper_r__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \oper_r__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__imm_data__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] oper_r__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \oper_r__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] oper_r__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \oper_r__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__is_signed$next ;
  (* enum_base_type = "LDSTMode" *)
  (* enum_value_00 = "NONE" *)
  (* enum_value_01 = "update" *)
  (* enum_value_10 = "cix" *)
  (* enum_value_11 = "cx" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] oper_r__ldst_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \oper_r__ldst_mode$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__sign_extend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__sign_extend$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg oper_r__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \oper_r__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *)
  reg p_st_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:303" *)
  wire \p_st_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" *)
  wire rd_done;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" *)
  wire rda_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" *)
  wire reset_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" *)
  wire reset_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" *)
  wire reset_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" *)
  wire [2:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293" *)
  wire reset_s;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" *)
  wire reset_u;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" *)
  wire reset_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" *)
  reg [63:0] revnorev;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rst_l_q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  wire rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" *)
  wire [63:0] src1_or_z;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" *)
  wire [63:0] src2_or_imm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" *)
  reg [63:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:111" *)
  wire st_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:17" *)
  reg [63:0] stdata_r;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire sto_l_q_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg sto_l_r_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \sto_l_r_sto$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire sto_l_s_sto;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:115" *)
  wire stwd_mem_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire upd_l_q_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg upd_l_r_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \upd_l_r_upd$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg upd_l_s_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \upd_l_s_upd$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:277" *)
  wire wr_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire wri_l_q_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg wri_l_r_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \wri_l_r_wri$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire wri_l_s_wri;
  assign _177_ = src1_or_z + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" *) src2_or_imm;
  assign _178_ = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) \$98 ;
  assign _179_ = alu_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) adr_l_q_adr;
  assign _180_ = \$102  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" *) cu_busy_o;
  assign _181_ = sto_l_q_sto & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) cu_busy_o;
  assign _182_ = \$106  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) rd_done;
  assign _183_ = \$108  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" *) op_is_st;
  assign _184_ = \$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" *) cu_shadown_i;
  assign _185_ = rd_done & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) wri_l_q_wri;
  assign _186_ = \$114  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_busy_o;
  assign _187_ = \$116  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) lod_l_qn_lod;
  assign _188_ = \$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) op_is_ld;
  assign _189_ = \$120  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" *) cu_shadown_i;
  assign _190_ = upd_l_q_upd & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_busy_o;
  assign _191_ = \$124  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) \$126 ;
  assign _192_ = \$128  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) alu_valid;
  assign _193_ = \$130  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" *) cu_shadown_i;
  assign _194_ = rst_l_q_rst & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_busy_o;
  assign _195_ = \$140  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_shadown_i;
  assign _196_ = \$142  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$144 ;
  assign _197_ = \$150  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) \$152 ;
  assign _198_ = wr_reset & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) \$158 ;
  assign _199_ = \$162  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *) cu_wr__go_i[1];
  assign _200_ = { cu_busy_o, cu_busy_o, cu_busy_o } & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" *) { 1'h0, \$167 , op_is_ld };
  assign _201_ = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" *) cu_busy_o;
  assign _202_ = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" *) cu_busy_o;
  assign _203_ = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" *) lsd_l_q_lsd;
  assign _204_ = op_is_ld & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" *) cu_ad__go_i;
  assign _205_ = op_is_st & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" *) cu_st__go_i;
  assign _206_ = alu_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$30 ;
  assign _207_ = \$32  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) \$34 ;
  assign _208_ = \$39  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$41 ;
  assign _209_ = \$47  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$49 ;
  assign _210_ = addr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" *) op_is_st;
  assign _211_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _212_ = \$76  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$78 ;
  assign _213_ = \$80  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) \$82 ;
  assign _214_ = src_l_q_src[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) cu_busy_o;
  assign _215_ = \$86  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" *) op_is_st;
  assign _216_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$92 ;
  assign _217_ = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1;
  assign _218_ = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1;
  assign _219_ = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1;
  assign _220_ = oper_r__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *) 2'h2;
  assign _221_ = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" *) 7'h26;
  assign _222_ = oper_r__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" *) 7'h25;
  assign _223_ = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1;
  assign _224_ = oper_r__ldst_mode == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" *) 2'h1;
  assign _225_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) addr_r;
  assign _226_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) ldst_port0_ld_data_o[7:0];
  assign _227_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) src_r2[7:0];
  assign _228_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) \$147 ;
  assign _229_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) ldst_port0_busy_o;
  assign _230_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) alu_valid;
  assign _231_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" *) rda_any;
  assign _232_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o;
  assign _233_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) ldst_port0_busy_o;
  assign _234_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) { oper_r__imm_data__ok, oper_r__zero_a };
  assign _235_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" *) cu_rdmaskn_i;
  assign _236_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) \$93 ;
  assign _237_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" *) cu_rd__rel_o[2];
  assign _238_ = cu_done_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" *) cu_go_die_i;
  assign _239_ = cu_wr__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" *) cu_go_die_i;
  assign _240_ = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) p_st_go;
  assign _241_ = \$134  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[0];
  assign _242_ = \$136  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" *) cu_wr__go_i[1];
  assign _243_ = cu_st__rel_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[0];
  assign _244_ = \$145  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" *) cu_wr__rel_o[1];
  assign _245_ = cu_wr__go_i[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" *) cu_go_die_i;
  assign _246_ = lod_l_qn_lod | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" *) op_is_st;
  assign _247_ = \$156  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" *) op_is_ld;
  assign _248_ = cu_st__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" *) cu_go_die_i;
  assign _249_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _250_ = cu_ad__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" *) cu_go_die_i;
  assign _251_ = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$43 ;
  assign _252_ = wr_reset | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" *) \$51 ;
  assign _253_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" *) { \$45 , \$53  };
  assign _254_ = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" *) p_st_go;
  assign _255_ = reset_s | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) p_st_go;
  assign _256_ = \$61  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" *) ld_ok;
  assign _257_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" *) cu_go_die_i;
  assign _258_ = cu_rd__go_i[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" *) cu_rd__go_i[1];
  assign _259_ = cu_rd__rel_o[0] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" *) cu_rd__rel_o[1];
  assign _260_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" *) _225_;
  assign _261_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) _226_;
  assign _262_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { 48'h000000000000, ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8] };
  assign _263_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { 32'h00000000, ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24] };
  assign _264_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) _227_;
  assign _265_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { 48'h000000000000, src_r2[7:0], src_r2[15:8] };
  assign _266_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" *) { 32'h00000000, src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24] };
  assign _267_ = ld_ok ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) ldd_o : ldo_r;
  assign _268_ = alu_l_q_alu ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) alu_o : ea_r;
  assign _269_ = oper_r__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" *) 64'h0000000000000000 : src_r0;
  assign _270_ = oper_r__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" *) oper_r__imm_data__data : src_r1;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142219.9-142225.4" *)
  adr_l adr_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_adr(adr_l_q_adr),
    .r_adr(adr_l_r_adr),
    .s_adr(adr_l_s_adr)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142226.15-142232.4" *)
  \alu_l$128  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142233.9-142239.4" *)
  lod_l lod_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .qn_lod(lod_l_qn_lod),
    .r_lod(lod_l_r_lod),
    .s_lod(lod_l_s_lod)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142240.9-142246.4" *)
  lsd_l lsd_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_lsd(lsd_l_q_lsd),
    .r_lsd(lsd_l_r_lsd),
    .s_lsd(lsd_l_s_lsd)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142247.15-142253.4" *)
  \opc_l$126  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142254.15-142260.4" *)
  \rst_l$129  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rst(rst_l_q_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142261.15-142267.4" *)
  \src_l$127  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142268.9-142274.4" *)
  sto_l sto_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_sto(sto_l_q_sto),
    .r_sto(sto_l_r_sto),
    .s_sto(sto_l_s_sto)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142275.9-142281.4" *)
  upd_l upd_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_upd(upd_l_q_upd),
    .r_upd(upd_l_r_upd),
    .s_upd(upd_l_s_upd)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:142282.9-142288.4" *)
  wri_l wri_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_wri(wri_l_q_wri),
    .r_wri(wri_l_r_wri),
    .s_wri(wri_l_s_wri)
  );
  always @* begin
    if (\initial ) begin end
    _007_ = 1'h0;
  end
  always @* begin
      \initial  <= _007_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      adr_l_r_adr <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_ok <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ea_r <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ldo_r <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 96'h000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      ldst_port0_addr_i <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ldst_port0_addr_i_ok <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      lsd_l_r_lsd <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__byte_reverse <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__data_len <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      oper_r__fn_unit <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      oper_r__imm_data__data <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__imm_data__ok <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      oper_r__insn <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      oper_r__insn_type <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__is_32bit <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__is_signed <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__ldst_mode <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__oe__oe <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__oe__ok <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__rc__ok <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__rc__rc <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__sign_extend <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      oper_r__zero_a <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _128_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      p_st_go <= _128_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _139_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _139_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sto_l_r_sto <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      upd_l_r_upd <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      upd_l_s_upd <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      wri_l_r_wri <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \ldst_port0_addr_i_ok$next ;
  end
  always @(posedge coresync_clk) begin
      ldst_port0_addr_i_ok <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \$175 ;
  end
  always @(posedge coresync_clk) begin
      ldst_port0_addr_i <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \$96 ;
  end
  always @(posedge coresync_clk) begin
      alu_ok <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \ea_r$next ;
  end
  always @(posedge coresync_clk) begin
      ea_r <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \ldo_r$next ;
  end
  always @(posedge coresync_clk) begin
      ldo_r <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \oper_r__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__insn_type <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \oper_r__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__fn_unit <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \oper_r__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__imm_data__data <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \oper_r__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__imm_data__ok <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \oper_r__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__zero_a <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \oper_r__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__rc__rc <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \oper_r__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__rc__ok <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \oper_r__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__oe__oe <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \oper_r__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__oe__ok <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \oper_r__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__is_32bit <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \oper_r__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__is_signed <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \oper_r__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__data_len <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \oper_r__byte_reverse$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__byte_reverse <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \oper_r__sign_extend$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__sign_extend <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \oper_r__ldst_mode$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__ldst_mode <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \oper_r__insn$next ;
  end
  always @(posedge coresync_clk) begin
      oper_r__insn <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \lsd_l_r_lsd$next ;
  end
  always @(posedge coresync_clk) begin
      lsd_l_r_lsd <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \sto_l_r_sto$next ;
  end
  always @(posedge coresync_clk) begin
      sto_l_r_sto <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \upd_l_r_upd$next ;
  end
  always @(posedge coresync_clk) begin
      upd_l_r_upd <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \upd_l_s_upd$next ;
  end
  always @(posedge coresync_clk) begin
      upd_l_s_upd <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \wri_l_r_wri$next ;
  end
  always @(posedge coresync_clk) begin
      wri_l_r_wri <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \adr_l_r_adr$next ;
  end
  always @(posedge coresync_clk) begin
      adr_l_r_adr <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = cu_st__go_i;
  end
  always @(posedge coresync_clk) begin
      p_st_go <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _094_;
    (* src = "libresoc.v:142290.5-142290.29" *)
    casez (\initial )
      /* src = "libresoc.v:142290.9-142290.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _094_ = 1'h0;
        end
      default:
          _094_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _092_;
    (* src = "libresoc.v:142299.5-142299.29" *)
    casez (\initial )
      /* src = "libresoc.v:142299.9-142299.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _092_ = 1'h1;
        end
      default:
          _092_ = reset_o;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _132_;
    (* src = "libresoc.v:142308.5-142308.29" *)
    casez (\initial )
      /* src = "libresoc.v:142308.9-142308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 3'h0;
        end
      default:
          _132_ = { cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _130_;
    (* src = "libresoc.v:142317.5-142317.29" *)
    casez (\initial )
      /* src = "libresoc.v:142317.9-142317.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 3'h7;
        end
      default:
          _130_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _075_;
    (* src = "libresoc.v:142326.5-142326.29" *)
    casez (\initial )
      /* src = "libresoc.v:142326.9-142326.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _075_ = 1'h1;
        end
      default:
          _075_ = reset_a;
    endcase
  end
  always @* begin
      \adr_l_r_adr$next  <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = _147_;
    (* src = "libresoc.v:142335.5-142335.29" *)
    casez (\initial )
      /* src = "libresoc.v:142335.9-142335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = 1'h1;
        end
      default:
          _147_ = \$38 [0];
    endcase
  end
  always @* begin
      \wri_l_r_wri$next  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = _145_;
    (* src = "libresoc.v:142344.5-142344.29" *)
    casez (\initial )
      /* src = "libresoc.v:142344.9-142344.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 1'h0;
        end
      default:
          _145_ = reset_i;
    endcase
  end
  always @* begin
      \upd_l_s_upd$next  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _143_;
    (* src = "libresoc.v:142353.5-142353.29" *)
    casez (\initial )
      /* src = "libresoc.v:142353.9-142353.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 1'h1;
        end
      default:
          _143_ = reset_u;
    endcase
  end
  always @* begin
      \upd_l_r_upd$next  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = _141_;
    (* src = "libresoc.v:142362.5-142362.29" *)
    casez (\initial )
      /* src = "libresoc.v:142362.9-142362.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 1'h1;
        end
      default:
          _141_ = \$59 ;
    endcase
  end
  always @* begin
      \sto_l_r_sto$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _090_;
    (* src = "libresoc.v:142371.5-142371.29" *)
    casez (\initial )
      /* src = "libresoc.v:142371.9-142371.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _090_ = 1'h1;
        end
      default:
          _090_ = \$63 ;
    endcase
  end
  always @* begin
      \lsd_l_r_lsd$next  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _151_;
    _024_ = _152_;
    _026_ = _153_;
    _032_ = _156_;
    _034_ = _157_;
    _036_ = _158_;
    _038_ = _159_;
    _040_ = _160_;
    _050_ = _165_;
    _052_ = _166_;
    _028_ = _171_;
    _030_ = _172_;
    _042_ = _173_;
    _044_ = _174_;
    _046_ = _175_;
    _048_ = _176_;
    (* src = "libresoc.v:142380.5-142380.29" *)
    casez (\initial )
      /* src = "libresoc.v:142380.9-142380.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:379" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _106_, _114_, _124_, _096_, _098_, _112_, _110_, _118_, _116_, _120_, _122_, _126_, _104_, _102_, _100_, _108_ } = { oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__insn_type };
        end
      default:
        begin
          _096_ = oper_r__byte_reverse;
          _098_ = oper_r__data_len;
          _100_ = oper_r__fn_unit;
          _102_ = oper_r__imm_data__data;
          _104_ = oper_r__imm_data__ok;
          _106_ = oper_r__insn;
          _108_ = oper_r__insn_type;
          _110_ = oper_r__is_32bit;
          _112_ = oper_r__is_signed;
          _114_ = oper_r__ldst_mode;
          _116_ = oper_r__oe__oe;
          _118_ = oper_r__oe__ok;
          _120_ = oper_r__rc__ok;
          _122_ = oper_r__rc__rc;
          _124_ = oper_r__sign_extend;
          _126_ = oper_r__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" *)
    casez (cu_done_o)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _156_, _160_, _165_, _151_, _152_, _159_, _158_, _162_, _161_, _163_, _164_, _166_, _155_, _154_, _153_, _157_ } = 133'h0000000000000000000000000000000000;
        end
      default:
        begin
          _151_ = _096_;
          _152_ = _098_;
          _153_ = _100_;
          _154_ = _102_;
          _155_ = _104_;
          _156_ = _106_;
          _157_ = _108_;
          _158_ = _110_;
          _159_ = _112_;
          _160_ = _114_;
          _161_ = _116_;
          _162_ = _118_;
          _163_ = _120_;
          _164_ = _122_;
          _165_ = _124_;
          _166_ = _126_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 64'h0000000000000000;
          _172_ = 1'h0;
          _176_ = 1'h0;
          _175_ = 1'h0;
          _173_ = 1'h0;
          _174_ = 1'h0;
        end
      default:
        begin
          _171_ = _154_;
          _172_ = _155_;
          _173_ = _161_;
          _174_ = _162_;
          _175_ = _163_;
          _176_ = _164_;
        end
    endcase
  end
  always @* begin
      \oper_r__byte_reverse$next  <= _022_;
      \oper_r__data_len$next  <= _024_;
      \oper_r__fn_unit$next  <= _026_;
      \oper_r__imm_data__data$next  <= _028_;
      \oper_r__imm_data__ok$next  <= _030_;
      \oper_r__insn$next  <= _032_;
      \oper_r__insn_type$next  <= _034_;
      \oper_r__is_32bit$next  <= _036_;
      \oper_r__is_signed$next  <= _038_;
      \oper_r__ldst_mode$next  <= _040_;
      \oper_r__oe__oe$next  <= _042_;
      \oper_r__oe__ok$next  <= _044_;
      \oper_r__rc__ok$next  <= _046_;
      \oper_r__rc__rc$next  <= _048_;
      \oper_r__sign_extend$next  <= _050_;
      \oper_r__zero_a$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _084_;
    (* src = "libresoc.v:142423.5-142423.29" *)
    casez (\initial )
      /* src = "libresoc.v:142423.9-142423.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (ld_ok)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _084_ = ldd_o;
        end
      default:
          _084_ = ldo_r;
    endcase
  end
  always @* begin
      \ldo_r$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _167_;
    (* src = "libresoc.v:142433.5-142433.29" *)
    casez (\initial )
      /* src = "libresoc.v:142433.9-142433.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *)
    casez (cu_rd__go_i[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = src1_i;
        end
      default:
          _134_ = src_r0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _167_ = 64'h0000000000000000;
        end
      default:
          _167_ = _134_;
    endcase
  end
  always @* begin
      \src_r0$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _168_;
    (* src = "libresoc.v:142449.5-142449.29" *)
    casez (\initial )
      /* src = "libresoc.v:142449.9-142449.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *)
    casez (cu_rd__go_i[1])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = src2_i;
        end
      default:
          _136_ = src_r1;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _168_ = 64'h0000000000000000;
        end
      default:
          _168_ = _136_;
    endcase
  end
  always @* begin
      \src_r1$next  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _169_;
    (* src = "libresoc.v:142465.5-142465.29" *)
    casez (\initial )
      /* src = "libresoc.v:142465.9-142465.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393" *)
    casez (cu_rd__go_i[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _138_ = src3_i;
        end
      default:
          _138_ = src_r2;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _169_ = 64'h0000000000000000;
        end
      default:
          _169_ = _138_;
    endcase
  end
  always @* begin
      \src_r2$next  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _080_;
    (* src = "libresoc.v:142481.5-142481.29" *)
    casez (\initial )
      /* src = "libresoc.v:142481.9-142481.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (alu_l_q_alu)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _080_ = alu_o;
        end
      default:
          _080_ = ea_r;
    endcase
  end
  always @* begin
      \ea_r$next  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _078_;
    (* src = "libresoc.v:142491.5-142491.29" *)
    casez (\initial )
      /* src = "libresoc.v:142491.9-142491.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:472" *)
    casez (cu_wr__go_i[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _078_ = ldd_r;
        end
      default:
          _078_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _079_;
    (* src = "libresoc.v:142501.5-142501.29" *)
    casez (\initial )
      /* src = "libresoc.v:142501.9-142501.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" *)
    casez (\$164 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _079_ = addr_r;
        end
      default:
          _079_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest2_o <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _087_;
    (* src = "libresoc.v:142511.5-142511.29" *)
    casez (\initial )
      /* src = "libresoc.v:142511.9-142511.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = 1'h0;
        end
      default:
          _087_ = \$177 ;
    endcase
  end
  always @* begin
      \ldst_port0_addr_i_ok$next  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _083_;
    (* src = "libresoc.v:142520.5-142520.29" *)
    casez (\initial )
      /* src = "libresoc.v:142520.9-142520.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *)
    casez (oper_r__byte_reverse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _083_ = _150_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *)
          casez (oper_r__data_len)
            /* src = "libresoc.v:0.0-0.0" */
            4'h1:
              begin
                _150_ = \$186 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h2:
              begin
                _150_ = \$188 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h4:
              begin
                _150_ = \$190 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h8:
              begin
                _150_ = { ldst_port0_ld_data_o[7:0], ldst_port0_ld_data_o[15:8], ldst_port0_ld_data_o[23:16], ldst_port0_ld_data_o[31:24], ldst_port0_ld_data_o[39:32], ldst_port0_ld_data_o[47:40], ldst_port0_ld_data_o[55:48], ldst_port0_ld_data_o[63:56] };
              end
            default:
                _150_ = 64'h0000000000000000;
          endcase
        end
      default:
          _083_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      lddata_r <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _129_;
    (* src = "libresoc.v:142544.5-142544.29" *)
    casez (\initial )
      /* src = "libresoc.v:142544.9-142544.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:500" *)
    casez (oper_r__byte_reverse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = lddata_r;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _129_ = ldst_port0_ld_data_o;
        end
    endcase
  end
  always @* begin
      revnorev <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _082_;
    (* src = "libresoc.v:142556.5-142556.29" *)
    casez (\initial )
      /* src = "libresoc.v:142556.9-142556.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:509" *)
    casez (oper_r__sign_extend)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _082_ = _149_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" *)
          casez (\$192 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _149_ = { revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15], revnorev[15:0] };
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _149_ = { revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31], revnorev[31:0] };
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _082_ = revnorev;
        end
    endcase
  end
  always @* begin
      ldd_o <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _140_;
    (* src = "libresoc.v:142576.5-142576.29" *)
    casez (\initial )
      /* src = "libresoc.v:142576.9-142576.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *)
    casez (oper_r__byte_reverse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _140_ = _170_;
          (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:30" *)
          casez (oper_r__data_len)
            /* src = "libresoc.v:0.0-0.0" */
            4'h1:
              begin
                _170_ = \$194 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h2:
              begin
                _170_ = \$196 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h4:
              begin
                _170_ = \$198 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h8:
              begin
                _170_ = { src_r2[7:0], src_r2[15:8], src_r2[23:16], src_r2[31:24], src_r2[39:32], src_r2[47:40], src_r2[55:48], src_r2[63:56] };
              end
            default:
                _170_ = 64'h0000000000000000;
          endcase
        end
      default:
          _140_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      stdata_r <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _089_;
    (* src = "libresoc.v:142600.5-142600.29" *)
    casez (\initial )
      /* src = "libresoc.v:142600.9-142600.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:523" *)
    casez (oper_r__byte_reverse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _089_ = stdata_r;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _089_ = src_r2;
        end
    endcase
  end
  always @* begin
      ldst_port0_st_data_i <= _015_;
  end
  assign \$100  = _178_;
  assign \$102  = _179_;
  assign \$104  = _180_;
  assign \$106  = _181_;
  assign \$108  = _182_;
  assign \$10  = _238_;
  assign \$110  = _183_;
  assign \$112  = _184_;
  assign \$114  = _185_;
  assign \$116  = _186_;
  assign \$118  = _187_;
  assign \$120  = _188_;
  assign \$122  = _189_;
  assign \$124  = _190_;
  assign \$126  = _217_;
  assign \$128  = _191_;
  assign \$12  = _239_;
  assign \$130  = _192_;
  assign \$132  = _193_;
  assign \$134  = _240_;
  assign \$136  = _241_;
  assign \$138  = _242_;
  assign \$140  = _194_;
  assign \$142  = _195_;
  assign \$145  = _243_;
  assign \$147  = _244_;
  assign \$144  = _228_;
  assign \$14  = _245_;
  assign \$150  = _196_;
  assign \$152  = _246_;
  assign \$154  = _197_;
  assign \$156  = _229_;
  assign \$158  = _247_;
  assign \$160  = _198_;
  assign \$162  = _218_;
  assign \$164  = _199_;
  assign \$167  = _219_;
  assign \$16  = _248_;
  assign \$169  = _200_;
  assign \$171  = _201_;
  assign \$173  = _202_;
  assign \$175  = _260_;
  assign \$177  = _203_;
  assign \$186  = _261_;
  assign \$188  = _262_;
  assign \$18  = _249_;
  assign \$190  = _263_;
  assign \$192  = _220_;
  assign \$194  = _264_;
  assign \$196  = _265_;
  assign \$198  = _266_;
  assign \$20  = _250_;
  assign \$22  = _221_;
  assign \$24  = _222_;
  assign \$26  = _204_;
  assign \$28  = _205_;
  assign \$30  = _230_;
  assign \$32  = _206_;
  assign \$34  = _231_;
  assign \$36  = _207_;
  assign \$39  = _232_;
  assign \$41  = _223_;
  assign \$43  = _208_;
  assign \$45  = _251_;
  assign \$47  = _233_;
  assign \$49  = _224_;
  assign \$51  = _209_;
  assign \$53  = _252_;
  assign \$55  = _253_;
  assign \$57  = _210_;
  assign \$59  = _254_;
  assign \$61  = _255_;
  assign \$63  = _256_;
  assign \$65  = _267_;
  assign \$67  = _268_;
  assign \$69  = _269_;
  assign \$71  = _270_;
  assign \$74  = _177_;
  assign \$76  = _211_;
  assign \$78  = _234_;
  assign \$80  = _212_;
  assign \$82  = _235_;
  assign \$84  = _213_;
  assign \$86  = _214_;
  assign \$88  = _215_;
  assign \$8  = _257_;
  assign \$90  = _258_;
  assign \$93  = _259_;
  assign \$92  = _236_;
  assign \$96  = _216_;
  assign \$98  = _237_;
  assign \$38  = \$55 ;
  assign \$73  = \$74 ;
  assign \$166  = \$169 ;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign ldst_port0_st_data_i_ok = cu_st__go_i;
  assign ld_ok = ldst_port0_ld_data_o_ok;
  assign addr_ok = ldst_port0_addr_ok_o;
  assign { \exc_$signal$185 , \exc_$signal$184 , \exc_$signal$183 , \exc_$signal$182 , \exc_$signal$181 , \exc_$signal$180 , \exc_$signal$179 , \exc_$signal  } = { \ldst_port0_exc_$signal$7 , \ldst_port0_exc_$signal$6 , \ldst_port0_exc_$signal$5 , \ldst_port0_exc_$signal$4 , \ldst_port0_exc_$signal$3 , \ldst_port0_exc_$signal$2 , \ldst_port0_exc_$signal$1 , \ldst_port0_exc_$signal  };
  assign \ldst_port0_addr_i$next  = \$175 ;
  assign ldst_port0_data_len = oper_r__data_len;
  assign ldst_port0_is_st_i = \$173 ;
  assign ldst_port0_is_ld_i = \$171 ;
  assign cu_wrmask_o = \$169 [1:0];
  assign ea = dest2_o;
  assign o = dest1_o;
  assign cu_done_o = \$160 ;
  assign wr_reset = \$154 ;
  assign wr_any = \$138 ;
  assign cu_wr__rel_o[1] = \$132 ;
  assign cu_wr__rel_o[0] = \$122 ;
  assign cu_st__rel_o = \$112 ;
  assign cu_ad__rel_o = \$104 ;
  assign rd_done = \$100 ;
  assign alu_valid = \$96 ;
  assign rda_any = \$90 ;
  assign cu_rd__rel_o[2] = \$88 ;
  assign cu_rd__rel_o[1:0] = \$84 [1:0];
  assign cu_busy_o = opc_l_q_opc;
  assign \alu_ok$next  = alu_valid;
  assign alu_o = \$74 [63:0];
  assign src2_or_imm = \$71 ;
  assign src1_or_z = \$69 ;
  assign addr_r = \$67 ;
  assign ldd_r = \$65 ;
  assign rst_l_r_rst = cu_issue_i;
  assign rst_l_s_rst = addr_ok;
  assign lsd_l_s_lsd = cu_issue_i;
  assign sto_l_s_sto = \$57 ;
  assign wri_l_s_wri = cu_issue_i;
  assign lod_l_r_lod = ld_ok;
  assign lod_l_s_lod = reset_i;
  assign adr_l_s_adr = reset_i;
  assign alu_l_r_alu = \$36 ;
  assign alu_l_s_alu = reset_i;
  assign st_o = op_is_st;
  assign ld_o = op_is_ld;
  assign stwd_mem_o = \$28 ;
  assign load_mem_o = \$26 ;
  assign op_is_ld = \$24 ;
  assign op_is_st = \$22 ;
  assign \p_st_go$next  = cu_st__go_i;
  assign reset_a = \$20 ;
  assign reset_r = \$18 ;
  assign reset_s = \$16 ;
  assign reset_u = \$14 ;
  assign reset_w = \$12 ;
  assign reset_o = \$10 ;
  assign reset_i = \$8 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:142674.1-143261.10" *)
module left_mask(mask, shift);
  reg \initial  = 0;
  (* src = "libresoc.v:142675.7-142675.20" *)
  reg _000_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _002_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _003_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _004_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _005_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _006_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _007_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _008_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _009_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _010_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _011_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _012_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _013_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _014_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _015_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _016_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _017_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _018_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _019_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _020_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _021_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _022_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _023_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _024_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _025_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _026_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _027_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _028_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _029_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _030_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _031_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _032_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _033_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _034_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _035_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _036_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _037_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _038_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _039_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _040_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _041_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _042_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _043_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _044_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _045_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _046_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _047_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _048_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _049_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _050_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _051_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _052_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _053_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _054_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _055_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _056_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _057_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _058_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _059_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _060_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _061_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _062_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _063_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _064_;
  (* src = "libresoc.v:142873.3-143260.6" *)
  reg _065_;
  (* src = "libresoc.v:142809.17-142809.96" *)
  wire _066_;
  (* src = "libresoc.v:142810.18-142810.98" *)
  wire _067_;
  (* src = "libresoc.v:142811.19-142811.99" *)
  wire _068_;
  (* src = "libresoc.v:142812.19-142812.99" *)
  wire _069_;
  (* src = "libresoc.v:142813.19-142813.99" *)
  wire _070_;
  (* src = "libresoc.v:142814.19-142814.99" *)
  wire _071_;
  (* src = "libresoc.v:142815.19-142815.99" *)
  wire _072_;
  (* src = "libresoc.v:142816.19-142816.99" *)
  wire _073_;
  (* src = "libresoc.v:142817.19-142817.99" *)
  wire _074_;
  (* src = "libresoc.v:142818.19-142818.99" *)
  wire _075_;
  (* src = "libresoc.v:142819.19-142819.99" *)
  wire _076_;
  (* src = "libresoc.v:142820.18-142820.97" *)
  wire _077_;
  (* src = "libresoc.v:142821.19-142821.99" *)
  wire _078_;
  (* src = "libresoc.v:142822.19-142822.99" *)
  wire _079_;
  (* src = "libresoc.v:142823.19-142823.99" *)
  wire _080_;
  (* src = "libresoc.v:142824.19-142824.99" *)
  wire _081_;
  (* src = "libresoc.v:142825.19-142825.99" *)
  wire _082_;
  (* src = "libresoc.v:142826.18-142826.97" *)
  wire _083_;
  (* src = "libresoc.v:142827.18-142827.97" *)
  wire _084_;
  (* src = "libresoc.v:142828.18-142828.97" *)
  wire _085_;
  (* src = "libresoc.v:142829.17-142829.96" *)
  wire _086_;
  (* src = "libresoc.v:142830.18-142830.97" *)
  wire _087_;
  (* src = "libresoc.v:142831.18-142831.97" *)
  wire _088_;
  (* src = "libresoc.v:142832.18-142832.97" *)
  wire _089_;
  (* src = "libresoc.v:142833.18-142833.97" *)
  wire _090_;
  (* src = "libresoc.v:142834.18-142834.97" *)
  wire _091_;
  (* src = "libresoc.v:142835.18-142835.97" *)
  wire _092_;
  (* src = "libresoc.v:142836.18-142836.97" *)
  wire _093_;
  (* src = "libresoc.v:142837.18-142837.98" *)
  wire _094_;
  (* src = "libresoc.v:142838.18-142838.98" *)
  wire _095_;
  (* src = "libresoc.v:142839.18-142839.98" *)
  wire _096_;
  (* src = "libresoc.v:142840.17-142840.96" *)
  wire _097_;
  (* src = "libresoc.v:142841.18-142841.98" *)
  wire _098_;
  (* src = "libresoc.v:142842.18-142842.98" *)
  wire _099_;
  (* src = "libresoc.v:142843.18-142843.98" *)
  wire _100_;
  (* src = "libresoc.v:142844.18-142844.98" *)
  wire _101_;
  (* src = "libresoc.v:142845.18-142845.98" *)
  wire _102_;
  (* src = "libresoc.v:142846.18-142846.98" *)
  wire _103_;
  (* src = "libresoc.v:142847.18-142847.98" *)
  wire _104_;
  (* src = "libresoc.v:142848.18-142848.98" *)
  wire _105_;
  (* src = "libresoc.v:142849.18-142849.98" *)
  wire _106_;
  (* src = "libresoc.v:142850.18-142850.98" *)
  wire _107_;
  (* src = "libresoc.v:142851.17-142851.96" *)
  wire _108_;
  (* src = "libresoc.v:142852.18-142852.98" *)
  wire _109_;
  (* src = "libresoc.v:142853.18-142853.98" *)
  wire _110_;
  (* src = "libresoc.v:142854.18-142854.98" *)
  wire _111_;
  (* src = "libresoc.v:142855.18-142855.98" *)
  wire _112_;
  (* src = "libresoc.v:142856.18-142856.98" *)
  wire _113_;
  (* src = "libresoc.v:142857.18-142857.98" *)
  wire _114_;
  (* src = "libresoc.v:142858.18-142858.98" *)
  wire _115_;
  (* src = "libresoc.v:142859.18-142859.98" *)
  wire _116_;
  (* src = "libresoc.v:142860.18-142860.98" *)
  wire _117_;
  (* src = "libresoc.v:142861.18-142861.98" *)
  wire _118_;
  (* src = "libresoc.v:142862.17-142862.96" *)
  wire _119_;
  (* src = "libresoc.v:142863.18-142863.98" *)
  wire _120_;
  (* src = "libresoc.v:142864.18-142864.98" *)
  wire _121_;
  (* src = "libresoc.v:142865.18-142865.98" *)
  wire _122_;
  (* src = "libresoc.v:142866.18-142866.98" *)
  wire _123_;
  (* src = "libresoc.v:142867.18-142867.98" *)
  wire _124_;
  (* src = "libresoc.v:142868.18-142868.98" *)
  wire _125_;
  (* src = "libresoc.v:142869.18-142869.98" *)
  wire _126_;
  (* src = "libresoc.v:142870.18-142870.98" *)
  wire _127_;
  (* src = "libresoc.v:142871.18-142871.98" *)
  wire _128_;
  (* src = "libresoc.v:142872.18-142872.98" *)
  wire _129_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$125 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$99 ;
  (* src = "libresoc.v:142675.7-142675.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *)
  output [63:0] mask;
  reg [63:0] mask;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *)
  input [6:0] shift;
  assign _066_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h4;
  assign _067_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h31;
  assign _068_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h32;
  assign _069_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h33;
  assign _070_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h34;
  assign _071_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h35;
  assign _072_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h36;
  assign _073_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h37;
  assign _074_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h38;
  assign _075_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h39;
  assign _076_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3a;
  assign _077_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h5;
  assign _078_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3b;
  assign _079_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3c;
  assign _080_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3d;
  assign _081_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3e;
  assign _082_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3f;
  assign _083_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h6;
  assign _084_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h7;
  assign _085_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h8;
  assign _086_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h0;
  assign _087_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h9;
  assign _088_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'ha;
  assign _089_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hb;
  assign _090_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hc;
  assign _091_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hd;
  assign _092_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'he;
  assign _093_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hf;
  assign _094_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h10;
  assign _095_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h11;
  assign _096_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h12;
  assign _097_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h1;
  assign _098_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h13;
  assign _099_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h14;
  assign _100_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h15;
  assign _101_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h16;
  assign _102_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h17;
  assign _103_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h18;
  assign _104_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h19;
  assign _105_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1a;
  assign _106_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1b;
  assign _107_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1c;
  assign _108_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h2;
  assign _109_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1d;
  assign _110_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1e;
  assign _111_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1f;
  assign _112_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h20;
  assign _113_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h21;
  assign _114_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h22;
  assign _115_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h23;
  assign _116_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h24;
  assign _117_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h25;
  assign _118_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h26;
  assign _119_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h3;
  assign _120_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h27;
  assign _121_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h28;
  assign _122_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h29;
  assign _123_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2a;
  assign _124_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2b;
  assign _125_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2c;
  assign _126_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2d;
  assign _127_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2e;
  assign _128_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2f;
  assign _129_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h30;
  always @* begin
    if (\initial ) begin end
    _000_ = 1'h0;
  end
  always @* begin
      \initial  <= _000_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _001_[0] = _012_;
    _001_[1] = _023_;
    _001_[2] = _034_;
    _001_[3] = _045_;
    _001_[4] = _056_;
    _001_[5] = _062_;
    _001_[6] = _063_;
    _001_[7] = _064_;
    _001_[8] = _065_;
    _001_[9] = _002_;
    _001_[10] = _003_;
    _001_[11] = _004_;
    _001_[12] = _005_;
    _001_[13] = _006_;
    _001_[14] = _007_;
    _001_[15] = _008_;
    _001_[16] = _009_;
    _001_[17] = _010_;
    _001_[18] = _011_;
    _001_[19] = _013_;
    _001_[20] = _014_;
    _001_[21] = _015_;
    _001_[22] = _016_;
    _001_[23] = _017_;
    _001_[24] = _018_;
    _001_[25] = _019_;
    _001_[26] = _020_;
    _001_[27] = _021_;
    _001_[28] = _022_;
    _001_[29] = _024_;
    _001_[30] = _025_;
    _001_[31] = _026_;
    _001_[32] = _027_;
    _001_[33] = _028_;
    _001_[34] = _029_;
    _001_[35] = _030_;
    _001_[36] = _031_;
    _001_[37] = _032_;
    _001_[38] = _033_;
    _001_[39] = _035_;
    _001_[40] = _036_;
    _001_[41] = _037_;
    _001_[42] = _038_;
    _001_[43] = _039_;
    _001_[44] = _040_;
    _001_[45] = _041_;
    _001_[46] = _042_;
    _001_[47] = _043_;
    _001_[48] = _044_;
    _001_[49] = _046_;
    _001_[50] = _047_;
    _001_[51] = _048_;
    _001_[52] = _049_;
    _001_[53] = _050_;
    _001_[54] = _051_;
    _001_[55] = _052_;
    _001_[56] = _053_;
    _001_[57] = _054_;
    _001_[58] = _055_;
    _001_[59] = _057_;
    _001_[60] = _058_;
    _001_[61] = _059_;
    _001_[62] = _060_;
    _001_[63] = _061_;
    (* src = "libresoc.v:142874.5-142874.29" *)
    casez (\initial )
      /* src = "libresoc.v:142874.9-142874.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _012_ = 1'h1;
        end
      default:
          _012_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$3 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _023_ = 1'h1;
        end
      default:
          _023_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$5 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _034_ = 1'h1;
        end
      default:
          _034_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$7 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _045_ = 1'h1;
        end
      default:
          _045_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _056_ = 1'h1;
        end
      default:
          _056_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$11 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _062_ = 1'h1;
        end
      default:
          _062_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _063_ = 1'h1;
        end
      default:
          _063_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$15 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _064_ = 1'h1;
        end
      default:
          _064_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$17 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _065_ = 1'h1;
        end
      default:
          _065_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$19 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _002_ = 1'h1;
        end
      default:
          _002_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$21 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _003_ = 1'h1;
        end
      default:
          _003_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$23 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _004_ = 1'h1;
        end
      default:
          _004_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$25 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _005_ = 1'h1;
        end
      default:
          _005_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$27 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _006_ = 1'h1;
        end
      default:
          _006_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$29 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _007_ = 1'h1;
        end
      default:
          _007_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$31 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _008_ = 1'h1;
        end
      default:
          _008_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$33 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _009_ = 1'h1;
        end
      default:
          _009_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$35 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _010_ = 1'h1;
        end
      default:
          _010_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$37 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _011_ = 1'h1;
        end
      default:
          _011_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$39 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _013_ = 1'h1;
        end
      default:
          _013_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$41 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _014_ = 1'h1;
        end
      default:
          _014_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$43 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _015_ = 1'h1;
        end
      default:
          _015_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$45 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _016_ = 1'h1;
        end
      default:
          _016_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$47 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _017_ = 1'h1;
        end
      default:
          _017_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _018_ = 1'h1;
        end
      default:
          _018_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$51 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _019_ = 1'h1;
        end
      default:
          _019_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$53 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _020_ = 1'h1;
        end
      default:
          _020_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _021_ = 1'h1;
        end
      default:
          _021_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$57 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _022_ = 1'h1;
        end
      default:
          _022_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$59 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _024_ = 1'h1;
        end
      default:
          _024_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$61 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _025_ = 1'h1;
        end
      default:
          _025_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$63 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _026_ = 1'h1;
        end
      default:
          _026_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$65 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _027_ = 1'h1;
        end
      default:
          _027_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$67 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _028_ = 1'h1;
        end
      default:
          _028_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$69 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _029_ = 1'h1;
        end
      default:
          _029_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$71 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _030_ = 1'h1;
        end
      default:
          _030_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$73 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _031_ = 1'h1;
        end
      default:
          _031_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$75 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _032_ = 1'h1;
        end
      default:
          _032_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$77 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = 1'h1;
        end
      default:
          _033_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$79 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = 1'h1;
        end
      default:
          _035_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$81 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _036_ = 1'h1;
        end
      default:
          _036_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$83 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _037_ = 1'h1;
        end
      default:
          _037_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$85 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _038_ = 1'h1;
        end
      default:
          _038_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$87 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _039_ = 1'h1;
        end
      default:
          _039_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$89 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _040_ = 1'h1;
        end
      default:
          _040_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$91 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _041_ = 1'h1;
        end
      default:
          _041_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$93 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _042_ = 1'h1;
        end
      default:
          _042_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$95 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _043_ = 1'h1;
        end
      default:
          _043_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$97 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _044_ = 1'h1;
        end
      default:
          _044_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$99 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _046_ = 1'h1;
        end
      default:
          _046_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$101 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _047_ = 1'h1;
        end
      default:
          _047_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$103 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _048_ = 1'h1;
        end
      default:
          _048_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$105 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _049_ = 1'h1;
        end
      default:
          _049_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$107 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _050_ = 1'h1;
        end
      default:
          _050_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$109 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _051_ = 1'h1;
        end
      default:
          _051_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$111 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _052_ = 1'h1;
        end
      default:
          _052_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _053_ = 1'h1;
        end
      default:
          _053_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _054_ = 1'h1;
        end
      default:
          _054_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$117 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _055_ = 1'h1;
        end
      default:
          _055_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$119 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _057_ = 1'h1;
        end
      default:
          _057_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$121 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _058_ = 1'h1;
        end
      default:
          _058_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$123 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _059_ = 1'h1;
        end
      default:
          _059_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$125 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _060_ = 1'h1;
        end
      default:
          _060_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$127 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _061_ = 1'h1;
        end
      default:
          _061_ = 1'h0;
    endcase
  end
  always @* begin
      mask <= _001_;
  end
  assign \$9  = _066_;
  assign \$99  = _067_;
  assign \$101  = _068_;
  assign \$103  = _069_;
  assign \$105  = _070_;
  assign \$107  = _071_;
  assign \$109  = _072_;
  assign \$111  = _073_;
  assign \$113  = _074_;
  assign \$115  = _075_;
  assign \$117  = _076_;
  assign \$11  = _077_;
  assign \$119  = _078_;
  assign \$121  = _079_;
  assign \$123  = _080_;
  assign \$125  = _081_;
  assign \$127  = _082_;
  assign \$13  = _083_;
  assign \$15  = _084_;
  assign \$17  = _085_;
  assign \$1  = _086_;
  assign \$19  = _087_;
  assign \$21  = _088_;
  assign \$23  = _089_;
  assign \$25  = _090_;
  assign \$27  = _091_;
  assign \$29  = _092_;
  assign \$31  = _093_;
  assign \$33  = _094_;
  assign \$35  = _095_;
  assign \$37  = _096_;
  assign \$3  = _097_;
  assign \$39  = _098_;
  assign \$41  = _099_;
  assign \$43  = _100_;
  assign \$45  = _101_;
  assign \$47  = _102_;
  assign \$49  = _103_;
  assign \$51  = _104_;
  assign \$53  = _105_;
  assign \$55  = _106_;
  assign \$57  = _107_;
  assign \$5  = _108_;
  assign \$59  = _109_;
  assign \$61  = _110_;
  assign \$63  = _111_;
  assign \$65  = _112_;
  assign \$67  = _113_;
  assign \$69  = _114_;
  assign \$71  = _115_;
  assign \$73  = _116_;
  assign \$75  = _117_;
  assign \$77  = _118_;
  assign \$7  = _119_;
  assign \$79  = _120_;
  assign \$81  = _121_;
  assign \$83  = _122_;
  assign \$85  = _123_;
  assign \$87  = _124_;
  assign \$89  = _125_;
  assign \$91  = _126_;
  assign \$93  = _127_;
  assign \$95  = _128_;
  assign \$97  = _129_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.lenexp" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:143265.1-143294.10" *)
module lenexp(addr_i, lexp_o, rexp_o, len_i);
  (* src = "libresoc.v:143289.17-143289.101" *)
  wire [63:0] _0_;
  (* src = "libresoc.v:143289.17-143289.101" *)
  wire [63:0] _1_;
  (* src = "libresoc.v:143286.17-143286.111" *)
  wire [19:0] _2_;
  (* src = "libresoc.v:143288.17-143288.113" *)
  wire [31:0] _3_;
  (* src = "libresoc.v:143287.17-143287.107" *)
  wire [20:0] _4_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *)
  wire [20:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *)
  wire [19:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *)
  wire [20:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *)
  wire [63:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *)
  wire [31:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *)
  input [3:0] addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" *)
  wire [16:0] binlen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" *)
  input [3:0] len_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" *)
  output [63:0] lexp_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" *)
  output [175:0] rexp_o;
  assign _0_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) \$7 ;
  assign _1_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) _0_;
  assign _2_ = 5'h01 <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) len_i;
  assign _3_ = binlen <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" *) addr_i;
  assign _4_ = \$2  - (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" *) 1'h1;
  assign \$2  = _2_;
  assign \$4  = _4_;
  assign \$7  = _3_;
  assign \$6  = _1_;
  assign \$1  = \$4 ;
  assign rexp_o = { lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21], lexp_o[21:20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20], lexp_o[20:19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19], lexp_o[19:18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18], lexp_o[18:17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17], lexp_o[17:16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16], lexp_o[16:15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15], lexp_o[15:14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14], lexp_o[14:13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13], lexp_o[13:12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12], lexp_o[12:11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11], lexp_o[11:10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10], lexp_o[10:9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9], lexp_o[9:8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8], lexp_o[8:7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7], lexp_o[7:6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6], lexp_o[6:5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5], lexp_o[5:4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4], lexp_o[4:3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3], lexp_o[3:2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2], lexp_o[2:1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1], lexp_o[1:0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0], lexp_o[0] };
  assign lexp_o = \$6 ;
  assign binlen = \$4 [16:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.lod_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:143298.1-143356.10" *)
module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:143299.7-143299.20" *)
  reg _00_;
  (* src = "libresoc.v:143344.3-143352.6" *)
  reg _01_;
  (* src = "libresoc.v:143342.3-143343.27" *)
  reg _02_;
  (* src = "libresoc.v:143344.3-143352.6" *)
  reg _03_;
  (* src = "libresoc.v:143321.7-143321.19" *)
  reg _04_;
  (* src = "libresoc.v:143334.17-143334.96" *)
  wire _05_;
  (* src = "libresoc.v:143339.17-143339.96" *)
  wire _06_;
  (* src = "libresoc.v:143336.18-143336.93" *)
  wire _07_;
  (* src = "libresoc.v:143338.17-143338.92" *)
  wire _08_;
  (* src = "libresoc.v:143341.17-143341.92" *)
  wire _09_;
  (* src = "libresoc.v:143335.18-143335.98" *)
  wire _10_;
  (* src = "libresoc.v:143337.18-143337.99" *)
  wire _11_;
  (* src = "libresoc.v:143340.17-143340.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:143299.7-143299.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  output qn_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_lod;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_lod;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_lod;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_lod;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_lod;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_lod;
  assign _11_ = q_lod | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_lod;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:143345.5-143345.29" *)
    casez (\initial )
      /* src = "libresoc.v:143345.9-143345.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_lod = \$15 ;
  assign qn_lod = \$13 ;
  assign q_lod = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:143360.1-144480.10" *)
module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:144105.3-144106.24" *)
  reg _000_;
  (* src = "libresoc.v:144103.3-144104.44" *)
  reg _001_;
  (* src = "libresoc.v:144410.3-144418.6" *)
  reg _002_;
  (* src = "libresoc.v:144027.3-144028.39" *)
  reg _003_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [3:0] _004_;
  (* src = "libresoc.v:144077.3-144078.83" *)
  reg [3:0] _005_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [13:0] _006_;
  (* src = "libresoc.v:144047.3-144048.81" *)
  reg [13:0] _007_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:144049.3-144050.95" *)
  reg [63:0] _009_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _010_;
  (* src = "libresoc.v:144051.3-144052.91" *)
  reg _011_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [1:0] _012_;
  (* src = "libresoc.v:144065.3-144066.89" *)
  reg [1:0] _013_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [31:0] _014_;
  (* src = "libresoc.v:144079.3-144080.75" *)
  reg [31:0] _015_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [6:0] _016_;
  (* src = "libresoc.v:144045.3-144046.85" *)
  reg [6:0] _017_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _018_;
  (* src = "libresoc.v:144061.3-144062.85" *)
  reg _019_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _020_;
  (* src = "libresoc.v:144067.3-144068.87" *)
  reg _021_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _022_;
  (* src = "libresoc.v:144073.3-144074.83" *)
  reg _023_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _024_;
  (* src = "libresoc.v:144075.3-144076.85" *)
  reg _025_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _026_;
  (* src = "libresoc.v:144057.3-144058.79" *)
  reg _027_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _028_;
  (* src = "libresoc.v:144059.3-144060.79" *)
  reg _029_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _030_;
  (* src = "libresoc.v:144071.3-144072.91" *)
  reg _031_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _032_;
  (* src = "libresoc.v:144055.3-144056.79" *)
  reg _033_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _034_;
  (* src = "libresoc.v:144053.3-144054.79" *)
  reg _035_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _036_;
  (* src = "libresoc.v:144069.3-144070.85" *)
  reg _037_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _038_;
  (* src = "libresoc.v:144063.3-144064.79" *)
  reg _039_;
  (* src = "libresoc.v:144401.3-144409.6" *)
  reg _040_;
  (* src = "libresoc.v:144029.3-144030.43" *)
  reg _041_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg [63:0] _042_;
  (* src = "libresoc.v:144041.3-144042.37" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg _044_;
  (* src = "libresoc.v:144043.3-144044.43" *)
  reg _045_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg [3:0] _046_;
  (* src = "libresoc.v:144037.3-144038.43" *)
  reg [3:0] _047_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg _048_;
  (* src = "libresoc.v:144039.3-144040.49" *)
  reg _049_;
  (* src = "libresoc.v:144419.3-144428.6" *)
  reg [63:0] _050_;
  (* src = "libresoc.v:144429.3-144438.6" *)
  reg [3:0] _051_;
  (* src = "libresoc.v:143361.7-143361.20" *)
  reg _052_;
  (* src = "libresoc.v:144243.3-144251.6" *)
  reg _053_;
  (* src = "libresoc.v:144089.3-144090.39" *)
  reg _054_;
  (* src = "libresoc.v:144234.3-144242.6" *)
  reg _055_;
  (* src = "libresoc.v:144091.3-144092.39" *)
  reg _056_;
  (* src = "libresoc.v:144439.3-144447.6" *)
  reg [1:0] _057_;
  (* src = "libresoc.v:144101.3-144102.37" *)
  reg [1:0] _058_;
  (* src = "libresoc.v:144188.3-144197.6" *)
  reg _059_;
  (* src = "libresoc.v:144279.3-144287.6" *)
  reg [1:0] _060_;
  (* src = "libresoc.v:144081.3-144082.39" *)
  reg [1:0] _061_;
  (* src = "libresoc.v:144270.3-144278.6" *)
  reg [1:0] _062_;
  (* src = "libresoc.v:144083.3-144084.39" *)
  reg [1:0] _063_;
  (* src = "libresoc.v:144207.3-144215.6" *)
  reg _064_;
  (* src = "libresoc.v:144097.3-144098.41" *)
  reg _065_;
  (* src = "libresoc.v:144198.3-144206.6" *)
  reg _066_;
  (* src = "libresoc.v:144099.3-144100.41" *)
  reg _067_;
  (* src = "libresoc.v:144225.3-144233.6" *)
  reg _068_;
  (* src = "libresoc.v:144093.3-144094.39" *)
  reg _069_;
  (* src = "libresoc.v:144216.3-144224.6" *)
  reg _070_;
  (* src = "libresoc.v:144095.3-144096.39" *)
  reg _071_;
  (* src = "libresoc.v:144261.3-144269.6" *)
  reg [2:0] _072_;
  (* src = "libresoc.v:144085.3-144086.39" *)
  reg [2:0] _073_;
  (* src = "libresoc.v:144252.3-144260.6" *)
  reg [2:0] _074_;
  (* src = "libresoc.v:144087.3-144088.39" *)
  reg [2:0] _075_;
  (* src = "libresoc.v:144371.3-144380.6" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:144035.3-144036.29" *)
  reg [63:0] _077_;
  (* src = "libresoc.v:144381.3-144390.6" *)
  reg [63:0] _078_;
  (* src = "libresoc.v:144033.3-144034.29" *)
  reg [63:0] _079_;
  (* src = "libresoc.v:144391.3-144400.6" *)
  reg _080_;
  (* src = "libresoc.v:144031.3-144032.29" *)
  reg _081_;
  (* src = "libresoc.v:143479.7-143479.24" *)
  reg _082_;
  (* src = "libresoc.v:143489.7-143489.26" *)
  reg _083_;
  (* src = "libresoc.v:144410.3-144418.6" *)
  reg _084_;
  (* src = "libresoc.v:143497.7-143497.25" *)
  reg _085_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [3:0] _086_;
  (* src = "libresoc.v:143505.13-143505.53" *)
  reg [3:0] _087_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [13:0] _088_;
  (* src = "libresoc.v:143524.14-143524.57" *)
  reg [13:0] _089_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [63:0] _090_;
  (* src = "libresoc.v:143528.14-143528.76" *)
  reg [63:0] _091_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _092_;
  (* src = "libresoc.v:143532.7-143532.51" *)
  reg _093_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [1:0] _094_;
  (* src = "libresoc.v:143540.13-143540.56" *)
  reg [1:0] _095_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [31:0] _096_;
  (* src = "libresoc.v:143544.14-143544.51" *)
  reg [31:0] _097_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [6:0] _098_;
  (* src = "libresoc.v:143623.13-143623.55" *)
  reg [6:0] _099_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _100_;
  (* src = "libresoc.v:143627.7-143627.48" *)
  reg _101_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _102_;
  (* src = "libresoc.v:143631.7-143631.49" *)
  reg _103_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _104_;
  (* src = "libresoc.v:143635.7-143635.47" *)
  reg _105_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _106_;
  (* src = "libresoc.v:143639.7-143639.48" *)
  reg _107_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _108_;
  (* src = "libresoc.v:143643.7-143643.45" *)
  reg _109_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _110_;
  (* src = "libresoc.v:143647.7-143647.45" *)
  reg _111_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _112_;
  (* src = "libresoc.v:143651.7-143651.51" *)
  reg _113_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _114_;
  (* src = "libresoc.v:143655.7-143655.45" *)
  reg _115_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _116_;
  (* src = "libresoc.v:143659.7-143659.45" *)
  reg _117_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _118_;
  (* src = "libresoc.v:143663.7-143663.48" *)
  reg _119_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _120_;
  (* src = "libresoc.v:143667.7-143667.45" *)
  reg _121_;
  (* src = "libresoc.v:144401.3-144409.6" *)
  reg _122_;
  (* src = "libresoc.v:143693.7-143693.27" *)
  reg _123_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg [63:0] _124_;
  (* src = "libresoc.v:143727.14-143727.47" *)
  reg [63:0] _125_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg _126_;
  (* src = "libresoc.v:143731.7-143731.27" *)
  reg _127_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg [3:0] _128_;
  (* src = "libresoc.v:143735.13-143735.33" *)
  reg [3:0] _129_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg _130_;
  (* src = "libresoc.v:143739.7-143739.30" *)
  reg _131_;
  (* src = "libresoc.v:144419.3-144428.6" *)
  reg [63:0] _132_;
  (* src = "libresoc.v:144429.3-144438.6" *)
  reg [3:0] _133_;
  (* src = "libresoc.v:144243.3-144251.6" *)
  reg _134_;
  (* src = "libresoc.v:143753.7-143753.25" *)
  reg _135_;
  (* src = "libresoc.v:144234.3-144242.6" *)
  reg _136_;
  (* src = "libresoc.v:143757.7-143757.25" *)
  reg _137_;
  (* src = "libresoc.v:144439.3-144447.6" *)
  reg [1:0] _138_;
  (* src = "libresoc.v:143891.13-143891.30" *)
  reg [1:0] _139_;
  (* src = "libresoc.v:144188.3-144197.6" *)
  reg _140_;
  (* src = "libresoc.v:144279.3-144287.6" *)
  reg [1:0] _141_;
  (* src = "libresoc.v:143899.13-143899.31" *)
  reg [1:0] _142_;
  (* src = "libresoc.v:144270.3-144278.6" *)
  reg [1:0] _143_;
  (* src = "libresoc.v:143903.13-143903.31" *)
  reg [1:0] _144_;
  (* src = "libresoc.v:144207.3-144215.6" *)
  reg _145_;
  (* src = "libresoc.v:143915.7-143915.26" *)
  reg _146_;
  (* src = "libresoc.v:144198.3-144206.6" *)
  reg _147_;
  (* src = "libresoc.v:143919.7-143919.26" *)
  reg _148_;
  (* src = "libresoc.v:144225.3-144233.6" *)
  reg _149_;
  (* src = "libresoc.v:143923.7-143923.25" *)
  reg _150_;
  (* src = "libresoc.v:144216.3-144224.6" *)
  reg _151_;
  (* src = "libresoc.v:143927.7-143927.25" *)
  reg _152_;
  (* src = "libresoc.v:144261.3-144269.6" *)
  reg [2:0] _153_;
  (* src = "libresoc.v:143941.13-143941.31" *)
  reg [2:0] _154_;
  (* src = "libresoc.v:144252.3-144260.6" *)
  reg [2:0] _155_;
  (* src = "libresoc.v:143945.13-143945.31" *)
  reg [2:0] _156_;
  (* src = "libresoc.v:144371.3-144380.6" *)
  reg [63:0] _157_;
  (* src = "libresoc.v:143953.14-143953.43" *)
  reg [63:0] _158_;
  (* src = "libresoc.v:144381.3-144390.6" *)
  reg [63:0] _159_;
  (* src = "libresoc.v:143957.14-143957.43" *)
  reg [63:0] _160_;
  (* src = "libresoc.v:144391.3-144400.6" *)
  reg _161_;
  (* src = "libresoc.v:143961.7-143961.20" *)
  reg _162_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg [63:0] _163_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _164_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _165_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _166_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _167_;
  (* src = "libresoc.v:144288.3-144326.6" *)
  reg _168_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg [63:0] _169_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg _170_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg [3:0] _171_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg _172_;
  (* src = "libresoc.v:144327.3-144348.6" *)
  reg _173_;
  (* src = "libresoc.v:144349.3-144370.6" *)
  reg _174_;
  (* src = "libresoc.v:143970.17-143970.109" *)
  wire _175_;
  (* src = "libresoc.v:143971.18-143971.130" *)
  wire [2:0] _176_;
  (* src = "libresoc.v:143973.19-143973.114" *)
  wire [2:0] _177_;
  (* src = "libresoc.v:143974.19-143974.125" *)
  wire _178_;
  (* src = "libresoc.v:143975.19-143975.125" *)
  wire _179_;
  (* src = "libresoc.v:143976.19-143976.133" *)
  wire [1:0] _180_;
  (* src = "libresoc.v:143977.19-143977.121" *)
  wire [1:0] _181_;
  (* src = "libresoc.v:143978.19-143978.127" *)
  wire _182_;
  (* src = "libresoc.v:143979.19-143979.127" *)
  wire _183_;
  (* src = "libresoc.v:143981.18-143981.98" *)
  wire _184_;
  (* src = "libresoc.v:143983.18-143983.100" *)
  wire _185_;
  (* src = "libresoc.v:143984.17-143984.123" *)
  wire _186_;
  (* src = "libresoc.v:143985.18-143985.138" *)
  wire [1:0] _187_;
  (* src = "libresoc.v:143987.18-143987.119" *)
  wire [1:0] _188_;
  (* src = "libresoc.v:143990.18-143990.116" *)
  wire _189_;
  (* src = "libresoc.v:143995.18-143995.113" *)
  wire _190_;
  (* src = "libresoc.v:143996.18-143996.125" *)
  wire [1:0] _191_;
  (* src = "libresoc.v:143998.18-143998.112" *)
  wire _192_;
  (* src = "libresoc.v:144001.18-144001.130" *)
  wire _193_;
  (* src = "libresoc.v:144002.18-144002.130" *)
  wire _194_;
  (* src = "libresoc.v:144003.18-144003.117" *)
  wire _195_;
  (* src = "libresoc.v:144008.18-144008.134" *)
  wire _196_;
  (* src = "libresoc.v:144009.18-144009.124" *)
  wire [1:0] _197_;
  (* src = "libresoc.v:144012.18-144012.116" *)
  wire _198_;
  (* src = "libresoc.v:144013.18-144013.119" *)
  wire _199_;
  (* src = "libresoc.v:144022.18-144022.138" *)
  wire _200_;
  (* src = "libresoc.v:144023.18-144023.136" *)
  wire _201_;
  (* src = "libresoc.v:144024.18-144024.149" *)
  wire [2:0] _202_;
  (* src = "libresoc.v:143997.18-143997.113" *)
  wire _203_;
  (* src = "libresoc.v:143999.18-143999.119" *)
  wire _204_;
  (* src = "libresoc.v:143972.19-143972.115" *)
  wire [2:0] _205_;
  (* src = "libresoc.v:143980.18-143980.97" *)
  wire _206_;
  (* src = "libresoc.v:143982.18-143982.99" *)
  wire _207_;
  (* src = "libresoc.v:143986.18-143986.113" *)
  wire [1:0] _208_;
  (* src = "libresoc.v:143989.18-143989.106" *)
  wire _209_;
  (* src = "libresoc.v:143994.18-143994.124" *)
  wire _210_;
  (* src = "libresoc.v:144000.17-144000.113" *)
  wire [2:0] _211_;
  (* src = "libresoc.v:144025.18-144025.133" *)
  wire _212_;
  (* src = "libresoc.v:144026.18-144026.139" *)
  wire _213_;
  (* src = "libresoc.v:143993.18-143993.112" *)
  wire _214_;
  (* src = "libresoc.v:144004.18-144004.122" *)
  wire _215_;
  (* src = "libresoc.v:144005.18-144005.124" *)
  wire _216_;
  (* src = "libresoc.v:144006.18-144006.142" *)
  wire [1:0] _217_;
  (* src = "libresoc.v:144007.18-144007.155" *)
  wire [2:0] _218_;
  (* src = "libresoc.v:144010.18-144010.120" *)
  wire [1:0] _219_;
  (* src = "libresoc.v:144011.17-144011.117" *)
  wire [2:0] _220_;
  (* src = "libresoc.v:144017.17-144017.104" *)
  wire _221_;
  (* src = "libresoc.v:143988.18-143988.106" *)
  wire _222_;
  (* src = "libresoc.v:143991.18-143991.113" *)
  wire _223_;
  (* src = "libresoc.v:143992.18-143992.112" *)
  wire _224_;
  (* src = "libresoc.v:144014.18-144014.162" *)
  wire _225_;
  (* src = "libresoc.v:144015.18-144015.163" *)
  wire [63:0] _226_;
  (* src = "libresoc.v:144016.18-144016.168" *)
  wire _227_;
  (* src = "libresoc.v:144018.18-144018.188" *)
  wire [63:0] _228_;
  (* src = "libresoc.v:144019.18-144019.115" *)
  wire [63:0] _229_;
  (* src = "libresoc.v:144020.18-144020.125" *)
  wire [63:0] _230_;
  (* src = "libresoc.v:144021.18-144021.118" *)
  wire _231_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [1:0] \$109 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [1:0] \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [1:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [1:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [1:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [1:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [1:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [2:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [1:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [1:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_logical0_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] alu_logical0_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \alu_logical0_logical_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_logical0_logical_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_logical0_logical_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_logical0_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_logical0_logical_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] alu_logical0_logical_op__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_logical0_logical_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_logical0_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_logical0_logical_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_logical0_logical_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_logical0_logical_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_logical0_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_logical0_logical_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_logical0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_logical0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_logical0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_logical0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_logical0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_logical0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_logical0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire alu_logical0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [1:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [1:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [1:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [1:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r1__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r1__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest2_o;
  reg [3:0] dest2_o;
  (* src = "libresoc.v:143361.7-143361.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] oper_i_alu_logical0__data_len;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_logical0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_logical0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_logical0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_logical0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_logical0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_logical0__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [1:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [1:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [1:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [1:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [1:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [1:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [1:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [2:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [1:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src3_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] \src_or_imm$80 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire \src_sel$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  assign _175_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$3 ;
  assign _176_ = \$93  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$97 , \$95  };
  assign _177_ = \$99  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$101 ;
  assign _178_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _179_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _180_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$105 , \$107  };
  assign _181_ = \$109  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _182_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _183_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _184_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$11 ;
  assign _185_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$15 ;
  assign _186_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _187_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o };
  assign _188_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _189_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$21 ;
  assign _190_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$37 ;
  assign _191_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _192_ = \$39  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$43 ;
  assign _193_ = \$47  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_logical0_n_ready_i;
  assign _194_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_logical0_n_valid_o;
  assign _195_ = \$51  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _196_ = alu_logical0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _197_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _198_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _199_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _200_ = alu_logical0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _201_ = alu_logical0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _202_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _203_ = \$41  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _204_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _205_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _206_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _207_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _208_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _209_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ;
  assign _210_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_logical0_n_ready_i;
  assign _211_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _212_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_logical0_logical_op__zero_a;
  assign _213_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_logical0_logical_op__imm_data__ok;
  assign _214_ = \$31  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$33 ;
  assign _215_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _216_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _217_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i };
  assign _218_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _219_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _220_ = \$4  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _221_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$6 ;
  assign _222_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ;
  assign _223_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _224_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _225_ = alu_logical0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[0];
  assign _226_ = alu_logical0_logical_op__zero_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) 64'h0000000000000000 : src1_i;
  assign _227_ = alu_logical0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _228_ = alu_logical0_logical_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_logical0_logical_op__imm_data__data : src2_i;
  assign _229_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r0;
  assign _230_ = \src_sel$77  ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) \src_or_imm$80  : src_r1;
  assign _231_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144107.14-144113.4" *)
  \alu_l$61  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144114.16-144146.4" *)
  alu_logical0 alu_logical0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_logical0_cr_a),
    .cr_a_ok(cr_a_ok),
    .logical_op__data_len(alu_logical0_logical_op__data_len),
    .logical_op__fn_unit(alu_logical0_logical_op__fn_unit),
    .logical_op__imm_data__data(alu_logical0_logical_op__imm_data__data),
    .logical_op__imm_data__ok(alu_logical0_logical_op__imm_data__ok),
    .logical_op__input_carry(alu_logical0_logical_op__input_carry),
    .logical_op__insn(alu_logical0_logical_op__insn),
    .logical_op__insn_type(alu_logical0_logical_op__insn_type),
    .logical_op__invert_in(alu_logical0_logical_op__invert_in),
    .logical_op__invert_out(alu_logical0_logical_op__invert_out),
    .logical_op__is_32bit(alu_logical0_logical_op__is_32bit),
    .logical_op__is_signed(alu_logical0_logical_op__is_signed),
    .logical_op__oe__oe(alu_logical0_logical_op__oe__oe),
    .logical_op__oe__ok(alu_logical0_logical_op__oe__ok),
    .logical_op__output_carry(alu_logical0_logical_op__output_carry),
    .logical_op__rc__ok(alu_logical0_logical_op__rc__ok),
    .logical_op__rc__rc(alu_logical0_logical_op__rc__rc),
    .logical_op__write_cr0(alu_logical0_logical_op__write_cr0),
    .logical_op__zero_a(alu_logical0_logical_op__zero_a),
    .n_ready_i(alu_logical0_n_ready_i),
    .n_valid_o(alu_logical0_n_valid_o),
    .o(alu_logical0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_logical0_p_ready_o),
    .p_valid_i(alu_logical0_p_valid_i),
    .ra(alu_logical0_ra),
    .rb(alu_logical0_rb),
    .xer_so(alu_logical0_xer_so)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144147.15-144153.4" *)
  \alui_l$60  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144154.14-144160.4" *)
  \opc_l$56  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144161.14-144167.4" *)
  \req_l$57  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144168.14-144174.4" *)
  \rok_l$59  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144175.14-144180.4" *)
  \rst_l$58  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:144181.14-144187.4" *)
  \src_l$55  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _052_ = 1'h0;
  end
  always @* begin
      \initial  <= _052_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__data_len <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__fn_unit <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__imm_data__data <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__imm_data__ok <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__input_carry <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__insn <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__insn_type <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__invert_in <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__invert_out <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__is_32bit <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__is_signed <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__oe__oe <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__oe__ok <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__output_carry <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__rc__ok <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__rc__rc <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__write_cr0 <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_logical0_logical_op__zero_a <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a_ok <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _139_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _139_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 2'h3;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _160_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _160_;
  end
  always @* begin
    if (\initial ) begin end
    _162_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _162_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \data_r1__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \data_r1__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a_ok <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \alu_logical0_logical_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__insn_type <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_logical0_logical_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__fn_unit <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_logical0_logical_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__imm_data__data <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_logical0_logical_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__imm_data__ok <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \alu_logical0_logical_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__rc__rc <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \alu_logical0_logical_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__rc__ok <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \alu_logical0_logical_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__oe__oe <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \alu_logical0_logical_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__oe__ok <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_logical0_logical_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__invert_in <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \alu_logical0_logical_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__zero_a <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_logical0_logical_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__input_carry <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alu_logical0_logical_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__invert_out <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \alu_logical0_logical_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__write_cr0 <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \alu_logical0_logical_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__output_carry <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \alu_logical0_logical_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__is_32bit <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \alu_logical0_logical_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__is_signed <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_logical0_logical_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__data_len <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \alu_logical0_logical_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_logical0_logical_op__insn <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = alu_logical0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$9 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _140_;
    (* src = "libresoc.v:144189.5-144189.29" *)
    casez (\initial )
      /* src = "libresoc.v:144189.9-144189.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$53 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _140_ = 1'h1;
        end
      default:
          _140_ = \$45 ;
    endcase
  end
  always @* begin
      req_done <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _147_;
    (* src = "libresoc.v:144199.5-144199.29" *)
    casez (\initial )
      /* src = "libresoc.v:144199.9-144199.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = 1'h0;
        end
      default:
          _147_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _145_;
    (* src = "libresoc.v:144208.5-144208.29" *)
    casez (\initial )
      /* src = "libresoc.v:144208.9-144208.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 1'h1;
        end
      default:
          _145_ = \$63 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _151_;
    (* src = "libresoc.v:144217.5-144217.29" *)
    casez (\initial )
      /* src = "libresoc.v:144217.9-144217.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = 1'h0;
        end
      default:
          _151_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = _149_;
    (* src = "libresoc.v:144226.5-144226.29" *)
    casez (\initial )
      /* src = "libresoc.v:144226.9-144226.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _149_ = 1'h1;
        end
      default:
          _149_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _136_;
    (* src = "libresoc.v:144235.5-144235.29" *)
    casez (\initial )
      /* src = "libresoc.v:144235.9-144235.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = 1'h0;
        end
      default:
          _136_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _134_;
    (* src = "libresoc.v:144244.5-144244.29" *)
    casez (\initial )
      /* src = "libresoc.v:144244.9-144244.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = 1'h1;
        end
      default:
          _134_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = _155_;
    (* src = "libresoc.v:144253.5-144253.29" *)
    casez (\initial )
      /* src = "libresoc.v:144253.9-144253.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _155_ = 3'h0;
        end
      default:
          _155_ = { cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _153_;
    (* src = "libresoc.v:144262.5-144262.29" *)
    casez (\initial )
      /* src = "libresoc.v:144262.9-144262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = 3'h7;
        end
      default:
          _153_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _143_;
    (* src = "libresoc.v:144271.5-144271.29" *)
    casez (\initial )
      /* src = "libresoc.v:144271.9-144271.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 2'h0;
        end
      default:
          _143_ = \$65 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _141_;
    (* src = "libresoc.v:144280.5-144280.29" *)
    casez (\initial )
      /* src = "libresoc.v:144280.9-144280.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 2'h3;
        end
      default:
          _141_ = \$67 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _086_;
    _006_ = _088_;
    _012_ = _094_;
    _014_ = _096_;
    _016_ = _098_;
    _018_ = _100_;
    _020_ = _102_;
    _022_ = _104_;
    _024_ = _106_;
    _030_ = _112_;
    _036_ = _118_;
    _038_ = _120_;
    _008_ = _163_;
    _010_ = _164_;
    _026_ = _165_;
    _028_ = _166_;
    _032_ = _167_;
    _034_ = _168_;
    (* src = "libresoc.v:144289.5-144289.29" *)
    casez (\initial )
      /* src = "libresoc.v:144289.9-144289.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _096_, _086_, _106_, _104_, _112_, _118_, _102_, _094_, _120_, _100_, _110_, _108_, _114_, _116_, _092_, _090_, _088_, _098_ } = { oper_i_alu_logical0__insn, oper_i_alu_logical0__data_len, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__insn_type };
        end
      default:
        begin
          _086_ = alu_logical0_logical_op__data_len;
          _088_ = alu_logical0_logical_op__fn_unit;
          _090_ = alu_logical0_logical_op__imm_data__data;
          _092_ = alu_logical0_logical_op__imm_data__ok;
          _094_ = alu_logical0_logical_op__input_carry;
          _096_ = alu_logical0_logical_op__insn;
          _098_ = alu_logical0_logical_op__insn_type;
          _100_ = alu_logical0_logical_op__invert_in;
          _102_ = alu_logical0_logical_op__invert_out;
          _104_ = alu_logical0_logical_op__is_32bit;
          _106_ = alu_logical0_logical_op__is_signed;
          _108_ = alu_logical0_logical_op__oe__oe;
          _110_ = alu_logical0_logical_op__oe__ok;
          _112_ = alu_logical0_logical_op__output_carry;
          _114_ = alu_logical0_logical_op__rc__ok;
          _116_ = alu_logical0_logical_op__rc__rc;
          _118_ = alu_logical0_logical_op__write_cr0;
          _120_ = alu_logical0_logical_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _163_ = 64'h0000000000000000;
          _164_ = 1'h0;
          _168_ = 1'h0;
          _167_ = 1'h0;
          _165_ = 1'h0;
          _166_ = 1'h0;
        end
      default:
        begin
          _163_ = _090_;
          _164_ = _092_;
          _165_ = _108_;
          _166_ = _110_;
          _167_ = _114_;
          _168_ = _116_;
        end
    endcase
  end
  always @* begin
      \alu_logical0_logical_op__data_len$next  <= _004_;
      \alu_logical0_logical_op__fn_unit$next  <= _006_;
      \alu_logical0_logical_op__imm_data__data$next  <= _008_;
      \alu_logical0_logical_op__imm_data__ok$next  <= _010_;
      \alu_logical0_logical_op__input_carry$next  <= _012_;
      \alu_logical0_logical_op__insn$next  <= _014_;
      \alu_logical0_logical_op__insn_type$next  <= _016_;
      \alu_logical0_logical_op__invert_in$next  <= _018_;
      \alu_logical0_logical_op__invert_out$next  <= _020_;
      \alu_logical0_logical_op__is_32bit$next  <= _022_;
      \alu_logical0_logical_op__is_signed$next  <= _024_;
      \alu_logical0_logical_op__oe__oe$next  <= _026_;
      \alu_logical0_logical_op__oe__ok$next  <= _028_;
      \alu_logical0_logical_op__output_carry$next  <= _030_;
      \alu_logical0_logical_op__rc__ok$next  <= _032_;
      \alu_logical0_logical_op__rc__rc$next  <= _034_;
      \alu_logical0_logical_op__write_cr0$next  <= _036_;
      \alu_logical0_logical_op__zero_a$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _169_;
    _044_ = _173_;
    (* src = "libresoc.v:144328.5-144328.29" *)
    casez (\initial )
      /* src = "libresoc.v:144328.9-144328.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _126_, _124_ } = { o_ok, alu_logical0_o };
        end
      default:
        begin
          _124_ = data_r0__o;
          _126_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _170_, _169_ } = 65'h00000000000000000;
        end
      default:
        begin
          _169_ = _124_;
          _170_ = _126_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 1'h0;
        end
      default:
          _173_ = _170_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _042_;
      \data_r0__o_ok$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _171_;
    _048_ = _174_;
    (* src = "libresoc.v:144350.5-144350.29" *)
    casez (\initial )
      /* src = "libresoc.v:144350.9-144350.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _130_, _128_ } = { cr_a_ok, alu_logical0_cr_a };
        end
      default:
        begin
          _128_ = data_r1__cr_a;
          _130_ = data_r1__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _172_, _171_ } = 5'h00;
        end
      default:
        begin
          _171_ = _128_;
          _172_ = _130_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _174_ = 1'h0;
        end
      default:
          _174_ = _172_;
    endcase
  end
  always @* begin
      \data_r1__cr_a$next  <= _046_;
      \data_r1__cr_a_ok$next  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = _157_;
    (* src = "libresoc.v:144372.5-144372.29" *)
    casez (\initial )
      /* src = "libresoc.v:144372.9-144372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = src_or_imm;
        end
      default:
          _157_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = _159_;
    (* src = "libresoc.v:144382.5-144382.29" *)
    casez (\initial )
      /* src = "libresoc.v:144382.9-144382.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (\src_sel$77 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _159_ = \src_or_imm$80 ;
        end
      default:
          _159_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = _161_;
    (* src = "libresoc.v:144392.5-144392.29" *)
    casez (\initial )
      /* src = "libresoc.v:144392.9-144392.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _161_ = src3_i;
        end
      default:
          _161_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _122_;
    (* src = "libresoc.v:144402.5-144402.29" *)
    casez (\initial )
      /* src = "libresoc.v:144402.9-144402.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _122_ = 1'h1;
        end
      default:
          _122_ = \$89 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _084_;
    (* src = "libresoc.v:144411.5-144411.29" *)
    casez (\initial )
      /* src = "libresoc.v:144411.9-144411.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _084_ = 1'h1;
        end
      default:
          _084_ = \$91 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _132_;
    (* src = "libresoc.v:144420.5-144420.29" *)
    casez (\initial )
      /* src = "libresoc.v:144420.9-144420.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = data_r0__o;
        end
      default:
          _132_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _133_;
    (* src = "libresoc.v:144430.5-144430.29" *)
    casez (\initial )
      /* src = "libresoc.v:144430.9-144430.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _133_ = data_r1__cr_a;
        end
      default:
          _133_ = 4'h0;
    endcase
  end
  always @* begin
      dest2_o <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _138_;
    (* src = "libresoc.v:144440.5-144440.29" *)
    casez (\initial )
      /* src = "libresoc.v:144440.9-144440.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _138_ = 2'h0;
        end
      default:
          _138_ = \$19 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _057_;
  end
  assign \$9  = _175_;
  assign \$99  = _176_;
  assign \$101  = _205_;
  assign \$103  = _177_;
  assign \$105  = _178_;
  assign \$107  = _179_;
  assign \$109  = _180_;
  assign \$111  = _181_;
  assign \$113  = _182_;
  assign \$115  = _183_;
  assign \$11  = _206_;
  assign \$13  = _184_;
  assign \$15  = _207_;
  assign \$17  = _185_;
  assign \$1  = _186_;
  assign \$19  = _187_;
  assign \$23  = _208_;
  assign \$25  = _188_;
  assign \$22  = _222_;
  assign \$21  = _209_;
  assign \$29  = _189_;
  assign \$31  = _223_;
  assign \$33  = _224_;
  assign \$35  = _214_;
  assign \$37  = _210_;
  assign \$39  = _190_;
  assign \$41  = _191_;
  assign \$43  = _203_;
  assign \$45  = _192_;
  assign \$47  = _204_;
  assign \$4  = _211_;
  assign \$49  = _193_;
  assign \$51  = _194_;
  assign \$53  = _195_;
  assign \$55  = _215_;
  assign \$57  = _216_;
  assign \$59  = _217_;
  assign \$61  = _218_;
  assign \$63  = _196_;
  assign \$65  = _197_;
  assign \$67  = _219_;
  assign \$6  = _220_;
  assign \$69  = _198_;
  assign \$71  = _199_;
  assign \$73  = _225_;
  assign \$75  = _226_;
  assign \$78  = _227_;
  assign \$3  = _221_;
  assign \$81  = _228_;
  assign \$83  = _229_;
  assign \$85  = _230_;
  assign \$87  = _231_;
  assign \$89  = _200_;
  assign \$91  = _201_;
  assign \$93  = _202_;
  assign \$95  = _212_;
  assign \$97  = _213_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$111 ;
  assign cu_rd__rel_o = \$103 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_logical0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_logical0_p_valid_i = alui_l_q_alui;
  assign alu_logical0_xer_so = \$87 ;
  assign alu_logical0_rb = \$85 ;
  assign alu_logical0_ra = \$83 ;
  assign \src_or_imm$80  = \$81 ;
  assign \src_sel$77  = \$78 ;
  assign src_or_imm = \$75 ;
  assign src_sel = \$73 ;
  assign cu_wrmask_o = { \$71 , \$69  };
  assign reset_r = \$61 ;
  assign reset_w = \$59 ;
  assign rst_r = \$57 ;
  assign reset = \$55 ;
  assign wr_any = \$35 ;
  assign cu_done_o = \$29 ;
  assign alu_pulsem = { alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$17 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_logical0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$13 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$9 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:144484.1-145875.10" *)
module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , ra, rb, \xer_so$20 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:145814.3-145832.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:145574.3-145575.25" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:145814.3-145832.6" *)
  reg _002_;
  (* src = "libresoc.v:145576.3-145577.31" *)
  reg _003_;
  (* src = "libresoc.v:144485.7-144485.20" *)
  reg _004_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [3:0] _005_;
  (* src = "libresoc.v:145614.3-145615.57" *)
  reg [3:0] _006_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [13:0] _007_;
  (* src = "libresoc.v:145584.3-145585.55" *)
  reg [13:0] _008_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [63:0] _009_;
  (* src = "libresoc.v:145586.3-145587.69" *)
  reg [63:0] _010_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _011_;
  (* src = "libresoc.v:145588.3-145589.65" *)
  reg _012_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [1:0] _013_;
  (* src = "libresoc.v:145602.3-145603.63" *)
  reg [1:0] _014_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [31:0] _015_;
  (* src = "libresoc.v:145616.3-145617.49" *)
  reg [31:0] _016_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [6:0] _017_;
  (* src = "libresoc.v:145582.3-145583.59" *)
  reg [6:0] _018_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _019_;
  (* src = "libresoc.v:145598.3-145599.59" *)
  reg _020_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _021_;
  (* src = "libresoc.v:145604.3-145605.61" *)
  reg _022_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _023_;
  (* src = "libresoc.v:145610.3-145611.57" *)
  reg _024_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _025_;
  (* src = "libresoc.v:145612.3-145613.59" *)
  reg _026_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _027_;
  (* src = "libresoc.v:145594.3-145595.53" *)
  reg _028_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _029_;
  (* src = "libresoc.v:145596.3-145597.53" *)
  reg _030_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _031_;
  (* src = "libresoc.v:145608.3-145609.65" *)
  reg _032_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _033_;
  (* src = "libresoc.v:145592.3-145593.53" *)
  reg _034_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _035_;
  (* src = "libresoc.v:145590.3-145591.53" *)
  reg _036_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _037_;
  (* src = "libresoc.v:145606.3-145607.59" *)
  reg _038_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _039_;
  (* src = "libresoc.v:145600.3-145601.53" *)
  reg _040_;
  (* src = "libresoc.v:145740.3-145752.6" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:145618.3-145619.27" *)
  reg [1:0] _042_;
  (* src = "libresoc.v:145795.3-145813.6" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:145578.3-145579.19" *)
  reg [63:0] _044_;
  (* src = "libresoc.v:145795.3-145813.6" *)
  reg _045_;
  (* src = "libresoc.v:145580.3-145581.25" *)
  reg _046_;
  (* src = "libresoc.v:145722.3-145739.6" *)
  reg _047_;
  (* src = "libresoc.v:145620.3-145621.29" *)
  reg _048_;
  (* src = "libresoc.v:145833.3-145851.6" *)
  reg _049_;
  (* src = "libresoc.v:145570.3-145571.29" *)
  reg _050_;
  (* src = "libresoc.v:145833.3-145851.6" *)
  reg _051_;
  (* src = "libresoc.v:145572.3-145573.35" *)
  reg _052_;
  (* src = "libresoc.v:145814.3-145832.6" *)
  reg [3:0] _053_;
  (* src = "libresoc.v:144494.13-144494.24" *)
  reg [3:0] _054_;
  (* src = "libresoc.v:145814.3-145832.6" *)
  reg _055_;
  (* src = "libresoc.v:144503.7-144503.21" *)
  reg _056_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [3:0] _057_;
  (* src = "libresoc.v:144788.13-144788.40" *)
  reg [3:0] _058_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [13:0] _059_;
  (* src = "libresoc.v:144812.14-144812.44" *)
  reg [13:0] _060_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:144851.14-144851.63" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _063_;
  (* src = "libresoc.v:144860.7-144860.38" *)
  reg _064_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [1:0] _065_;
  (* src = "libresoc.v:144873.13-144873.43" *)
  reg [1:0] _066_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [31:0] _067_;
  (* src = "libresoc.v:144890.14-144890.38" *)
  reg [31:0] _068_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [6:0] _069_;
  (* src = "libresoc.v:144974.13-144974.42" *)
  reg [6:0] _070_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _071_;
  (* src = "libresoc.v:145133.7-145133.35" *)
  reg _072_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _073_;
  (* src = "libresoc.v:145142.7-145142.36" *)
  reg _074_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _075_;
  (* src = "libresoc.v:145151.7-145151.34" *)
  reg _076_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _077_;
  (* src = "libresoc.v:145160.7-145160.35" *)
  reg _078_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _079_;
  (* src = "libresoc.v:145169.7-145169.32" *)
  reg _080_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _081_;
  (* src = "libresoc.v:145178.7-145178.32" *)
  reg _082_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _083_;
  (* src = "libresoc.v:145187.7-145187.38" *)
  reg _084_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _085_;
  (* src = "libresoc.v:145196.7-145196.32" *)
  reg _086_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _087_;
  (* src = "libresoc.v:145205.7-145205.32" *)
  reg _088_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _089_;
  (* src = "libresoc.v:145214.7-145214.35" *)
  reg _090_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _091_;
  (* src = "libresoc.v:145223.7-145223.32" *)
  reg _092_;
  (* src = "libresoc.v:145740.3-145752.6" *)
  reg [1:0] _093_;
  (* src = "libresoc.v:145508.13-145508.25" *)
  reg [1:0] _094_;
  (* src = "libresoc.v:145795.3-145813.6" *)
  reg [63:0] _095_;
  (* src = "libresoc.v:145523.14-145523.38" *)
  reg [63:0] _096_;
  (* src = "libresoc.v:145795.3-145813.6" *)
  reg _097_;
  (* src = "libresoc.v:145530.7-145530.18" *)
  reg _098_;
  (* src = "libresoc.v:145722.3-145739.6" *)
  reg _099_;
  (* src = "libresoc.v:145544.7-145544.20" *)
  reg _100_;
  (* src = "libresoc.v:145833.3-145851.6" *)
  reg _101_;
  (* src = "libresoc.v:145553.7-145553.20" *)
  reg _102_;
  (* src = "libresoc.v:145833.3-145851.6" *)
  reg _103_;
  (* src = "libresoc.v:145562.7-145562.23" *)
  reg _104_;
  (* src = "libresoc.v:145814.3-145832.6" *)
  reg _105_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg [63:0] _106_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _107_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _108_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _109_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _110_;
  (* src = "libresoc.v:145753.3-145794.6" *)
  reg _111_;
  (* src = "libresoc.v:145795.3-145813.6" *)
  reg _112_;
  (* src = "libresoc.v:145722.3-145739.6" *)
  reg _113_;
  (* src = "libresoc.v:145833.3-145851.6" *)
  reg _114_;
  (* src = "libresoc.v:145569.18-145569.118" *)
  wire _115_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "libresoc.v:144485.7-144485.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] input_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \input_logical_op__data_len$38 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] input_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \input_logical_op__fn_unit$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] input_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \input_logical_op__imm_data__data$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__imm_data__ok$25 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] input_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \input_logical_op__input_carry$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] input_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \input_logical_op__insn$39 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] input_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \input_logical_op__insn_type$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__invert_in$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__invert_out$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__is_32bit$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__is_signed$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__oe__oe$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__oe__ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__output_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__rc__ok$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__rc__rc$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__write_cr0$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__zero_a$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] input_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \input_muxid$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_ra$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rb$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire input_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \input_xer_so$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] logical_op__data_len;
  reg [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] \logical_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] logical_op__fn_unit;
  reg [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \logical_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] logical_op__imm_data__data;
  reg [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__imm_data__ok;
  reg logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] logical_op__input_carry;
  reg [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] \logical_op__input_carry$12 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] logical_op__insn;
  reg [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \logical_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] logical_op__insn_type;
  reg [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \logical_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__invert_in;
  reg logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__invert_out;
  reg logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__is_32bit;
  reg logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__is_signed;
  reg logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__oe__oe;
  reg logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__oe__ok;
  reg logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__output_carry;
  reg logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__rc__ok;
  reg logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__rc__rc;
  reg logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__write_cr0;
  reg logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__zero_a;
  reg logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] main_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \main_logical_op__data_len$60 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_logical_op__fn_unit$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_logical_op__imm_data__data$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__imm_data__ok$47 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] main_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \main_logical_op__input_carry$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_logical_op__insn$61 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_logical_op__insn_type$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__invert_in$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__invert_out$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__is_32bit$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__is_signed$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__oe__oe$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__oe__ok$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__output_carry$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__rc__ok$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__rc__rc$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__write_cr0$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_logical_op__zero_a$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire main_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \main_xer_so$62 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$66 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  reg xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _115_ = \p_valid_i$63  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:145622.14-145667.4" *)
  \input$50  \input  (
    .logical_op__data_len(input_logical_op__data_len),
    .\logical_op__data_len$18 (\input_logical_op__data_len$38 ),
    .logical_op__fn_unit(input_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$23 ),
    .logical_op__imm_data__data(input_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$24 ),
    .logical_op__imm_data__ok(input_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$25 ),
    .logical_op__input_carry(input_logical_op__input_carry),
    .\logical_op__input_carry$12 (\input_logical_op__input_carry$32 ),
    .logical_op__insn(input_logical_op__insn),
    .\logical_op__insn$19 (\input_logical_op__insn$39 ),
    .logical_op__insn_type(input_logical_op__insn_type),
    .\logical_op__insn_type$2 (\input_logical_op__insn_type$22 ),
    .logical_op__invert_in(input_logical_op__invert_in),
    .\logical_op__invert_in$10 (\input_logical_op__invert_in$30 ),
    .logical_op__invert_out(input_logical_op__invert_out),
    .\logical_op__invert_out$13 (\input_logical_op__invert_out$33 ),
    .logical_op__is_32bit(input_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$36 ),
    .logical_op__is_signed(input_logical_op__is_signed),
    .\logical_op__is_signed$17 (\input_logical_op__is_signed$37 ),
    .logical_op__oe__oe(input_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$28 ),
    .logical_op__oe__ok(input_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$29 ),
    .logical_op__output_carry(input_logical_op__output_carry),
    .\logical_op__output_carry$15 (\input_logical_op__output_carry$35 ),
    .logical_op__rc__ok(input_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$27 ),
    .logical_op__rc__rc(input_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$26 ),
    .logical_op__write_cr0(input_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$34 ),
    .logical_op__zero_a(input_logical_op__zero_a),
    .\logical_op__zero_a$11 (\input_logical_op__zero_a$31 ),
    .muxid(input_muxid),
    .\muxid$1 (\input_muxid$21 ),
    .ra(input_ra),
    .\ra$20 (\input_ra$40 ),
    .rb(input_rb),
    .\rb$21 (\input_rb$41 ),
    .xer_so(input_xer_so),
    .\xer_so$22 (\input_xer_so$42 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:145668.13-145713.4" *)
  \main$51  main (
    .logical_op__data_len(main_logical_op__data_len),
    .\logical_op__data_len$18 (\main_logical_op__data_len$60 ),
    .logical_op__fn_unit(main_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\main_logical_op__fn_unit$45 ),
    .logical_op__imm_data__data(main_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\main_logical_op__imm_data__data$46 ),
    .logical_op__imm_data__ok(main_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\main_logical_op__imm_data__ok$47 ),
    .logical_op__input_carry(main_logical_op__input_carry),
    .\logical_op__input_carry$12 (\main_logical_op__input_carry$54 ),
    .logical_op__insn(main_logical_op__insn),
    .\logical_op__insn$19 (\main_logical_op__insn$61 ),
    .logical_op__insn_type(main_logical_op__insn_type),
    .\logical_op__insn_type$2 (\main_logical_op__insn_type$44 ),
    .logical_op__invert_in(main_logical_op__invert_in),
    .\logical_op__invert_in$10 (\main_logical_op__invert_in$52 ),
    .logical_op__invert_out(main_logical_op__invert_out),
    .\logical_op__invert_out$13 (\main_logical_op__invert_out$55 ),
    .logical_op__is_32bit(main_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\main_logical_op__is_32bit$58 ),
    .logical_op__is_signed(main_logical_op__is_signed),
    .\logical_op__is_signed$17 (\main_logical_op__is_signed$59 ),
    .logical_op__oe__oe(main_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\main_logical_op__oe__oe$50 ),
    .logical_op__oe__ok(main_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\main_logical_op__oe__ok$51 ),
    .logical_op__output_carry(main_logical_op__output_carry),
    .\logical_op__output_carry$15 (\main_logical_op__output_carry$57 ),
    .logical_op__rc__ok(main_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\main_logical_op__rc__ok$49 ),
    .logical_op__rc__rc(main_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\main_logical_op__rc__rc$48 ),
    .logical_op__write_cr0(main_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\main_logical_op__write_cr0$56 ),
    .logical_op__zero_a(main_logical_op__zero_a),
    .\logical_op__zero_a$11 (\main_logical_op__zero_a$53 ),
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$43 ),
    .o(main_o),
    .o_ok(main_o_ok),
    .ra(main_ra),
    .rb(main_rb),
    .xer_so(main_xer_so),
    .\xer_so$20 (\main_xer_so$62 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:145714.10-145717.4" *)
  \n$49  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:145718.10-145721.4" *)
  \p$48  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _004_ = 1'h0;
  end
  always @* begin
      \initial  <= _004_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _054_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      cr_a <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__data_len <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      logical_op__fn_unit <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      logical_op__imm_data__data <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__imm_data__ok <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__input_carry <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      logical_op__insn <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      logical_op__insn_type <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__invert_in <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__invert_out <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__is_32bit <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__is_signed <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__oe__oe <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__oe__ok <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__output_carry <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__rc__ok <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__rc__rc <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__write_cr0 <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__zero_a <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \logical_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__insn_type <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \logical_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__fn_unit <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \logical_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__imm_data__data <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \logical_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__imm_data__ok <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \logical_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__rc__rc <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \logical_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__rc__ok <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \logical_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__oe__oe <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \logical_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__oe__ok <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \logical_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__invert_in <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \logical_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__zero_a <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \logical_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__input_carry <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \logical_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__invert_out <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \logical_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__write_cr0 <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \logical_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__output_carry <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \logical_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__is_32bit <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \logical_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__is_signed <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \logical_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__data_len <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \logical_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__insn <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _113_;
    (* src = "libresoc.v:145723.5-145723.29" *)
    casez (\initial )
      /* src = "libresoc.v:145723.9-145723.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _099_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _099_ = 1'h0;
        end
      default:
          _099_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = 1'h0;
        end
      default:
          _113_ = _099_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _093_;
    (* src = "libresoc.v:145741.5-145741.29" *)
    casez (\initial )
      /* src = "libresoc.v:145741.9-145741.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _093_ = \muxid$66 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _093_ = \muxid$66 ;
        end
      default:
          _093_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _057_;
    _007_ = _059_;
    _013_ = _065_;
    _015_ = _067_;
    _017_ = _069_;
    _019_ = _071_;
    _021_ = _073_;
    _023_ = _075_;
    _025_ = _077_;
    _031_ = _083_;
    _037_ = _089_;
    _039_ = _091_;
    _009_ = _106_;
    _011_ = _107_;
    _027_ = _108_;
    _029_ = _109_;
    _033_ = _110_;
    _035_ = _111_;
    (* src = "libresoc.v:145754.5-145754.29" *)
    casez (\initial )
      /* src = "libresoc.v:145754.9-145754.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _067_, _057_, _077_, _075_, _083_, _089_, _073_, _065_, _091_, _071_, _081_, _079_, _085_, _087_, _063_, _061_, _059_, _069_ } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _067_, _057_, _077_, _075_, _083_, _089_, _073_, _065_, _091_, _071_, _081_, _079_, _085_, _087_, _063_, _061_, _059_, _069_ } = { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67  };
        end
      default:
        begin
          _057_ = logical_op__data_len;
          _059_ = logical_op__fn_unit;
          _061_ = logical_op__imm_data__data;
          _063_ = logical_op__imm_data__ok;
          _065_ = logical_op__input_carry;
          _067_ = logical_op__insn;
          _069_ = logical_op__insn_type;
          _071_ = logical_op__invert_in;
          _073_ = logical_op__invert_out;
          _075_ = logical_op__is_32bit;
          _077_ = logical_op__is_signed;
          _079_ = logical_op__oe__oe;
          _081_ = logical_op__oe__ok;
          _083_ = logical_op__output_carry;
          _085_ = logical_op__rc__ok;
          _087_ = logical_op__rc__rc;
          _089_ = logical_op__write_cr0;
          _091_ = logical_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _106_ = 64'h0000000000000000;
          _107_ = 1'h0;
          _111_ = 1'h0;
          _110_ = 1'h0;
          _108_ = 1'h0;
          _109_ = 1'h0;
        end
      default:
        begin
          _106_ = _061_;
          _107_ = _063_;
          _108_ = _079_;
          _109_ = _081_;
          _110_ = _085_;
          _111_ = _087_;
        end
    endcase
  end
  always @* begin
      \logical_op__data_len$next  <= _005_;
      \logical_op__fn_unit$next  <= _007_;
      \logical_op__imm_data__data$next  <= _009_;
      \logical_op__imm_data__ok$next  <= _011_;
      \logical_op__input_carry$next  <= _013_;
      \logical_op__insn$next  <= _015_;
      \logical_op__insn_type$next  <= _017_;
      \logical_op__invert_in$next  <= _019_;
      \logical_op__invert_out$next  <= _021_;
      \logical_op__is_32bit$next  <= _023_;
      \logical_op__is_signed$next  <= _025_;
      \logical_op__oe__oe$next  <= _027_;
      \logical_op__oe__ok$next  <= _029_;
      \logical_op__output_carry$next  <= _031_;
      \logical_op__rc__ok$next  <= _033_;
      \logical_op__rc__rc$next  <= _035_;
      \logical_op__write_cr0$next  <= _037_;
      \logical_op__zero_a$next  <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _095_;
    _045_ = _112_;
    (* src = "libresoc.v:145796.5-145796.29" *)
    casez (\initial )
      /* src = "libresoc.v:145796.9-145796.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _097_, _095_ } = { \o_ok$86 , \o$85  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _097_, _095_ } = { \o_ok$86 , \o$85  };
        end
      default:
        begin
          _095_ = o;
          _097_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _112_ = 1'h0;
        end
      default:
          _112_ = _097_;
    endcase
  end
  always @* begin
      \o$next  <= _043_;
      \o_ok$next  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _053_;
    _002_ = _105_;
    (* src = "libresoc.v:145815.5-145815.29" *)
    casez (\initial )
      /* src = "libresoc.v:145815.9-145815.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _055_, _053_ } = { \cr_a_ok$88 , \cr_a$87  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _055_, _053_ } = { \cr_a_ok$88 , \cr_a$87  };
        end
      default:
        begin
          _053_ = cr_a;
          _055_ = cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = 1'h0;
        end
      default:
          _105_ = _055_;
    endcase
  end
  always @* begin
      \cr_a$next  <= _000_;
      \cr_a_ok$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _101_;
    _051_ = _114_;
    (* src = "libresoc.v:145834.5-145834.29" *)
    casez (\initial )
      /* src = "libresoc.v:145834.9-145834.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _103_, _101_ } = { \xer_so_ok$92 , \xer_so$91  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _103_, _101_ } = { \xer_so_ok$92 , \xer_so$91  };
        end
      default:
        begin
          _101_ = xer_so;
          _103_ = xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _114_ = 1'h0;
        end
      default:
          _114_ = _103_;
    endcase
  end
  always @* begin
      \xer_so$next  <= _049_;
      \xer_so_ok$next  <= _051_;
  end
  assign \$64  = _115_;
  assign \cr_a$89  = 4'h0;
  assign \cr_a_ok$90  = 1'h0;
  assign \xer_so_ok$93  = 1'h0;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_so_ok$92 , \xer_so$91  } = { 1'h0, \main_xer_so$62  };
  assign { \cr_a_ok$88 , \cr_a$87  } = 5'h00;
  assign { \o_ok$86 , \o$85  } = { main_o_ok, main_o };
  assign { \logical_op__insn$84 , \logical_op__data_len$83 , \logical_op__is_signed$82 , \logical_op__is_32bit$81 , \logical_op__output_carry$80 , \logical_op__write_cr0$79 , \logical_op__invert_out$78 , \logical_op__input_carry$77 , \logical_op__zero_a$76 , \logical_op__invert_in$75 , \logical_op__oe__ok$74 , \logical_op__oe__oe$73 , \logical_op__rc__ok$72 , \logical_op__rc__rc$71 , \logical_op__imm_data__ok$70 , \logical_op__imm_data__data$69 , \logical_op__fn_unit$68 , \logical_op__insn_type$67  } = { \main_logical_op__insn$61 , \main_logical_op__data_len$60 , \main_logical_op__is_signed$59 , \main_logical_op__is_32bit$58 , \main_logical_op__output_carry$57 , \main_logical_op__write_cr0$56 , \main_logical_op__invert_out$55 , \main_logical_op__input_carry$54 , \main_logical_op__zero_a$53 , \main_logical_op__invert_in$52 , \main_logical_op__oe__ok$51 , \main_logical_op__oe__oe$50 , \main_logical_op__rc__ok$49 , \main_logical_op__rc__rc$48 , \main_logical_op__imm_data__ok$47 , \main_logical_op__imm_data__data$46 , \main_logical_op__fn_unit$45 , \main_logical_op__insn_type$44  };
  assign \muxid$66  = \main_muxid$43 ;
  assign p_valid_i_p_ready_o = \$64 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$63  = p_valid_i;
  assign main_xer_so = \input_xer_so$42 ;
  assign main_rb = \input_rb$41 ;
  assign main_ra = \input_ra$40 ;
  assign { main_logical_op__insn, main_logical_op__data_len, main_logical_op__is_signed, main_logical_op__is_32bit, main_logical_op__output_carry, main_logical_op__write_cr0, main_logical_op__invert_out, main_logical_op__input_carry, main_logical_op__zero_a, main_logical_op__invert_in, main_logical_op__oe__ok, main_logical_op__oe__oe, main_logical_op__rc__ok, main_logical_op__rc__rc, main_logical_op__imm_data__ok, main_logical_op__imm_data__data, main_logical_op__fn_unit, main_logical_op__insn_type } = { \input_logical_op__insn$39 , \input_logical_op__data_len$38 , \input_logical_op__is_signed$37 , \input_logical_op__is_32bit$36 , \input_logical_op__output_carry$35 , \input_logical_op__write_cr0$34 , \input_logical_op__invert_out$33 , \input_logical_op__input_carry$32 , \input_logical_op__zero_a$31 , \input_logical_op__invert_in$30 , \input_logical_op__oe__ok$29 , \input_logical_op__oe__oe$28 , \input_logical_op__rc__ok$27 , \input_logical_op__rc__rc$26 , \input_logical_op__imm_data__ok$25 , \input_logical_op__imm_data__data$24 , \input_logical_op__fn_unit$23 , \input_logical_op__insn_type$22  };
  assign main_muxid = \input_muxid$21 ;
  assign input_xer_so = \xer_so$20 ;
  assign input_rb = rb;
  assign input_ra = ra;
  assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  };
  assign input_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:145879.1-146912.10" *)
module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:146879.3-146897.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:146683.3-146684.33" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:145891.13-145891.29" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:146879.3-146897.6" *)
  reg _003_;
  (* src = "libresoc.v:146685.3-146686.39" *)
  reg _004_;
  (* src = "libresoc.v:145900.7-145900.26" *)
  reg _005_;
  (* src = "libresoc.v:145880.7-145880.20" *)
  reg _006_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [3:0] _007_;
  (* src = "libresoc.v:146723.3-146724.65" *)
  reg [3:0] _008_;
  (* src = "libresoc.v:145911.13-145911.45" *)
  reg [3:0] _009_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [13:0] _010_;
  (* src = "libresoc.v:146693.3-146694.61" *)
  reg [13:0] _011_;
  (* src = "libresoc.v:145950.14-145950.48" *)
  reg [13:0] _012_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:146695.3-146696.75" *)
  reg [63:0] _014_;
  (* src = "libresoc.v:145974.14-145974.67" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _016_;
  (* src = "libresoc.v:146697.3-146698.71" *)
  reg _017_;
  (* src = "libresoc.v:145983.7-145983.42" *)
  reg _018_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [1:0] _019_;
  (* src = "libresoc.v:146711.3-146712.71" *)
  reg [1:0] _020_;
  (* src = "libresoc.v:146000.13-146000.48" *)
  reg [1:0] _021_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [31:0] _022_;
  (* src = "libresoc.v:146725.3-146726.57" *)
  reg [31:0] _023_;
  (* src = "libresoc.v:146013.14-146013.43" *)
  reg [31:0] _024_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [6:0] _025_;
  (* src = "libresoc.v:146691.3-146692.65" *)
  reg [6:0] _026_;
  (* src = "libresoc.v:146172.13-146172.46" *)
  reg [6:0] _027_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _028_;
  (* src = "libresoc.v:146707.3-146708.67" *)
  reg _029_;
  (* src = "libresoc.v:146256.7-146256.40" *)
  reg _030_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _031_;
  (* src = "libresoc.v:146713.3-146714.69" *)
  reg _032_;
  (* src = "libresoc.v:146265.7-146265.41" *)
  reg _033_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _034_;
  (* src = "libresoc.v:146719.3-146720.65" *)
  reg _035_;
  (* src = "libresoc.v:146274.7-146274.39" *)
  reg _036_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _037_;
  (* src = "libresoc.v:146721.3-146722.67" *)
  reg _038_;
  (* src = "libresoc.v:146283.7-146283.40" *)
  reg _039_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _040_;
  (* src = "libresoc.v:146703.3-146704.59" *)
  reg _041_;
  (* src = "libresoc.v:146294.7-146294.36" *)
  reg _042_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _043_;
  (* src = "libresoc.v:146705.3-146706.59" *)
  reg _044_;
  (* src = "libresoc.v:146303.7-146303.36" *)
  reg _045_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _046_;
  (* src = "libresoc.v:146717.3-146718.73" *)
  reg _047_;
  (* src = "libresoc.v:146310.7-146310.43" *)
  reg _048_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _049_;
  (* src = "libresoc.v:146701.3-146702.59" *)
  reg _050_;
  (* src = "libresoc.v:146321.7-146321.36" *)
  reg _051_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _052_;
  (* src = "libresoc.v:146699.3-146700.59" *)
  reg _053_;
  (* src = "libresoc.v:146330.7-146330.36" *)
  reg _054_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _055_;
  (* src = "libresoc.v:146715.3-146716.67" *)
  reg _056_;
  (* src = "libresoc.v:146337.7-146337.40" *)
  reg _057_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _058_;
  (* src = "libresoc.v:146709.3-146710.61" *)
  reg _059_;
  (* src = "libresoc.v:146346.7-146346.37" *)
  reg _060_;
  (* src = "libresoc.v:146805.3-146817.6" *)
  reg [1:0] _061_;
  (* src = "libresoc.v:146727.3-146728.33" *)
  reg [1:0] _062_;
  (* src = "libresoc.v:146355.13-146355.29" *)
  reg [1:0] _063_;
  (* src = "libresoc.v:146860.3-146878.6" *)
  reg [63:0] _064_;
  (* src = "libresoc.v:146687.3-146688.27" *)
  reg [63:0] _065_;
  (* src = "libresoc.v:146370.14-146370.43" *)
  reg [63:0] _066_;
  (* src = "libresoc.v:146860.3-146878.6" *)
  reg _067_;
  (* src = "libresoc.v:146689.3-146690.33" *)
  reg _068_;
  (* src = "libresoc.v:146379.7-146379.23" *)
  reg _069_;
  (* src = "libresoc.v:146787.3-146804.6" *)
  reg _070_;
  (* src = "libresoc.v:146729.3-146730.29" *)
  reg _071_;
  (* src = "libresoc.v:146879.3-146897.6" *)
  reg [3:0] _072_;
  (* src = "libresoc.v:146879.3-146897.6" *)
  reg _073_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [3:0] _074_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [13:0] _075_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _077_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [1:0] _078_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [31:0] _079_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [6:0] _080_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _081_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _082_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _083_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _084_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _085_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _086_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _087_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _088_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _089_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _090_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _091_;
  (* src = "libresoc.v:146805.3-146817.6" *)
  reg [1:0] _092_;
  (* src = "libresoc.v:146860.3-146878.6" *)
  reg [63:0] _093_;
  (* src = "libresoc.v:146860.3-146878.6" *)
  reg _094_;
  (* src = "libresoc.v:146787.3-146804.6" *)
  reg _095_;
  (* src = "libresoc.v:146673.7-146673.20" *)
  reg _096_;
  (* src = "libresoc.v:146879.3-146897.6" *)
  reg _097_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _099_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _100_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _101_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _102_;
  (* src = "libresoc.v:146818.3-146859.6" *)
  reg _103_;
  (* src = "libresoc.v:146860.3-146878.6" *)
  reg _104_;
  (* src = "libresoc.v:146787.3-146804.6" *)
  reg _105_;
  (* src = "libresoc.v:146682.18-146682.118" *)
  wire _106_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$22 ;
  reg [3:0] \cr_a$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$22$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$23 ;
  reg \cr_a_ok$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$23$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$73 ;
  (* src = "libresoc.v:145880.7-145880.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  reg [3:0] \logical_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$68 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  reg [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  reg [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  reg \logical_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$55 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  reg [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$12$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  reg [31:0] \logical_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$19$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$69 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  reg [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  reg \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  reg \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  reg \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  reg \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  reg \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  reg \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  reg \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  reg \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  reg \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  reg \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  reg \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$61 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$20 ;
  reg [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$20$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$21 ;
  reg \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$21$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] output_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \output_cr_a$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] output_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \output_logical_op__data_len$41 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_logical_op__fn_unit$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_logical_op__imm_data__data$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__imm_data__ok$28 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] output_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \output_logical_op__input_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_logical_op__insn$42 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_logical_op__insn_type$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__invert_in$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__invert_out$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__is_32bit$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__is_signed$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__oe__oe$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__oe__ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__output_carry$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__rc__ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__rc__rc$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__write_cr0$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__zero_a$34 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_muxid$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \output_o$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_o_ok$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$48 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$47 ;
  assign _106_ = \p_valid_i$48  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:146731.10-146734.4" *)
  \n$53  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:146735.15-146782.4" *)
  \output$54  \output  (
    .cr_a(output_cr_a),
    .\cr_a$22 (\output_cr_a$45 ),
    .cr_a_ok(output_cr_a_ok),
    .logical_op__data_len(output_logical_op__data_len),
    .\logical_op__data_len$18 (\output_logical_op__data_len$41 ),
    .logical_op__fn_unit(output_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$26 ),
    .logical_op__imm_data__data(output_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$27 ),
    .logical_op__imm_data__ok(output_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$28 ),
    .logical_op__input_carry(output_logical_op__input_carry),
    .\logical_op__input_carry$12 (\output_logical_op__input_carry$35 ),
    .logical_op__insn(output_logical_op__insn),
    .\logical_op__insn$19 (\output_logical_op__insn$42 ),
    .logical_op__insn_type(output_logical_op__insn_type),
    .\logical_op__insn_type$2 (\output_logical_op__insn_type$25 ),
    .logical_op__invert_in(output_logical_op__invert_in),
    .\logical_op__invert_in$10 (\output_logical_op__invert_in$33 ),
    .logical_op__invert_out(output_logical_op__invert_out),
    .\logical_op__invert_out$13 (\output_logical_op__invert_out$36 ),
    .logical_op__is_32bit(output_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$39 ),
    .logical_op__is_signed(output_logical_op__is_signed),
    .\logical_op__is_signed$17 (\output_logical_op__is_signed$40 ),
    .logical_op__oe__oe(output_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$31 ),
    .logical_op__oe__ok(output_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$32 ),
    .logical_op__output_carry(output_logical_op__output_carry),
    .\logical_op__output_carry$15 (\output_logical_op__output_carry$38 ),
    .logical_op__rc__ok(output_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$30 ),
    .logical_op__rc__rc(output_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$29 ),
    .logical_op__write_cr0(output_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$37 ),
    .logical_op__zero_a(output_logical_op__zero_a),
    .\logical_op__zero_a$11 (\output_logical_op__zero_a$34 ),
    .muxid(output_muxid),
    .\muxid$1 (\output_muxid$24 ),
    .o(output_o),
    .\o$20 (\output_o$43 ),
    .o_ok(output_o_ok),
    .\o_ok$21 (\output_o_ok$44 ),
    .xer_so(output_xer_so)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:146783.10-146786.4" *)
  \p$52  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _006_ = 1'h0;
  end
  always @* begin
      \initial  <= _006_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _002_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a$22  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a_ok$23  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__data_len$18  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \logical_op__fn_unit$3  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__data$4  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__ok$5  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__input_carry$12  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn$19  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn_type$2  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_in$10  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_out$13  <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_32bit$16  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_signed$17  <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__oe$8  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__ok$9  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__output_carry$15  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__ok$7  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__rc$6  <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__write_cr0$14  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__zero_a$11  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \o$20  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \o_ok$21  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$22$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a$22  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \cr_a_ok$23$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a_ok$23  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \o$20$next ;
  end
  always @(posedge coresync_clk) begin
      \o$20  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \o_ok$21$next ;
  end
  always @(posedge coresync_clk) begin
      \o_ok$21  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \logical_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn_type$2  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \logical_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__fn_unit$3  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \logical_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__data$4  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \logical_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__ok$5  <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \logical_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__rc$6  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \logical_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__ok$7  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \logical_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__oe$8  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \logical_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__ok$9  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \logical_op__invert_in$10$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_in$10  <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \logical_op__zero_a$11$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__zero_a$11  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \logical_op__input_carry$12$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__input_carry$12  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \logical_op__invert_out$13$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_out$13  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \logical_op__write_cr0$14$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__write_cr0$14  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \logical_op__output_carry$15$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__output_carry$15  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \logical_op__is_32bit$16$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_32bit$16  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \logical_op__is_signed$17$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_signed$17  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \logical_op__data_len$18$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__data_len$18  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \logical_op__insn$19$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn$19  <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _105_;
    (* src = "libresoc.v:146788.5-146788.29" *)
    casez (\initial )
      /* src = "libresoc.v:146788.9-146788.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _095_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _095_ = 1'h0;
        end
      default:
          _095_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = 1'h0;
        end
      default:
          _105_ = _095_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _092_;
    (* src = "libresoc.v:146806.5-146806.29" *)
    casez (\initial )
      /* src = "libresoc.v:146806.9-146806.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _092_ = \muxid$51 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _092_ = \muxid$51 ;
        end
      default:
          _092_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _074_;
    _010_ = _075_;
    _019_ = _078_;
    _022_ = _079_;
    _025_ = _080_;
    _028_ = _081_;
    _031_ = _082_;
    _034_ = _083_;
    _037_ = _084_;
    _046_ = _087_;
    _055_ = _090_;
    _058_ = _091_;
    _013_ = _098_;
    _016_ = _099_;
    _040_ = _100_;
    _043_ = _101_;
    _049_ = _102_;
    _052_ = _103_;
    (* src = "libresoc.v:146819.5-146819.29" *)
    casez (\initial )
      /* src = "libresoc.v:146819.9-146819.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _079_, _074_, _084_, _083_, _087_, _090_, _082_, _078_, _091_, _081_, _086_, _085_, _088_, _089_, _077_, _076_, _075_, _080_ } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _079_, _074_, _084_, _083_, _087_, _090_, _082_, _078_, _091_, _081_, _086_, _085_, _088_, _089_, _077_, _076_, _075_, _080_ } = { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52  };
        end
      default:
        begin
          _074_ = \logical_op__data_len$18 ;
          _075_ = \logical_op__fn_unit$3 ;
          _076_ = \logical_op__imm_data__data$4 ;
          _077_ = \logical_op__imm_data__ok$5 ;
          _078_ = \logical_op__input_carry$12 ;
          _079_ = \logical_op__insn$19 ;
          _080_ = \logical_op__insn_type$2 ;
          _081_ = \logical_op__invert_in$10 ;
          _082_ = \logical_op__invert_out$13 ;
          _083_ = \logical_op__is_32bit$16 ;
          _084_ = \logical_op__is_signed$17 ;
          _085_ = \logical_op__oe__oe$8 ;
          _086_ = \logical_op__oe__ok$9 ;
          _087_ = \logical_op__output_carry$15 ;
          _088_ = \logical_op__rc__ok$7 ;
          _089_ = \logical_op__rc__rc$6 ;
          _090_ = \logical_op__write_cr0$14 ;
          _091_ = \logical_op__zero_a$11 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _098_ = 64'h0000000000000000;
          _099_ = 1'h0;
          _103_ = 1'h0;
          _102_ = 1'h0;
          _100_ = 1'h0;
          _101_ = 1'h0;
        end
      default:
        begin
          _098_ = _076_;
          _099_ = _077_;
          _100_ = _085_;
          _101_ = _086_;
          _102_ = _088_;
          _103_ = _089_;
        end
    endcase
  end
  always @* begin
      \logical_op__data_len$18$next  <= _007_;
      \logical_op__fn_unit$3$next  <= _010_;
      \logical_op__imm_data__data$4$next  <= _013_;
      \logical_op__imm_data__ok$5$next  <= _016_;
      \logical_op__input_carry$12$next  <= _019_;
      \logical_op__insn$19$next  <= _022_;
      \logical_op__insn_type$2$next  <= _025_;
      \logical_op__invert_in$10$next  <= _028_;
      \logical_op__invert_out$13$next  <= _031_;
      \logical_op__is_32bit$16$next  <= _034_;
      \logical_op__is_signed$17$next  <= _037_;
      \logical_op__oe__oe$8$next  <= _040_;
      \logical_op__oe__ok$9$next  <= _043_;
      \logical_op__output_carry$15$next  <= _046_;
      \logical_op__rc__ok$7$next  <= _049_;
      \logical_op__rc__rc$6$next  <= _052_;
      \logical_op__write_cr0$14$next  <= _055_;
      \logical_op__zero_a$11$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _093_;
    _067_ = _104_;
    (* src = "libresoc.v:146861.5-146861.29" *)
    casez (\initial )
      /* src = "libresoc.v:146861.9-146861.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _094_, _093_ } = { \o_ok$71 , \o$70  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _094_, _093_ } = { \o_ok$71 , \o$70  };
        end
      default:
        begin
          _093_ = \o$20 ;
          _094_ = \o_ok$21 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = 1'h0;
        end
      default:
          _104_ = _094_;
    endcase
  end
  always @* begin
      \o$20$next  <= _064_;
      \o_ok$21$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _072_;
    _003_ = _097_;
    (* src = "libresoc.v:146880.5-146880.29" *)
    casez (\initial )
      /* src = "libresoc.v:146880.9-146880.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _073_, _072_ } = { \cr_a_ok$73 , \cr_a$72  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _073_, _072_ } = { \cr_a_ok$73 , \cr_a$72  };
        end
      default:
        begin
          _072_ = \cr_a$22 ;
          _073_ = \cr_a_ok$23 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = 1'h0;
        end
      default:
          _097_ = _073_;
    endcase
  end
  always @* begin
      \cr_a$22$next  <= _000_;
      \cr_a_ok$23$next  <= _003_;
  end
  assign \$49  = _106_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \cr_a_ok$73 , \cr_a$72  } = { output_cr_a_ok, \output_cr_a$45  };
  assign { \o_ok$71 , \o$70  } = { \output_o_ok$44 , \output_o$43  };
  assign { \logical_op__insn$69 , \logical_op__data_len$68 , \logical_op__is_signed$67 , \logical_op__is_32bit$66 , \logical_op__output_carry$65 , \logical_op__write_cr0$64 , \logical_op__invert_out$63 , \logical_op__input_carry$62 , \logical_op__zero_a$61 , \logical_op__invert_in$60 , \logical_op__oe__ok$59 , \logical_op__oe__oe$58 , \logical_op__rc__ok$57 , \logical_op__rc__rc$56 , \logical_op__imm_data__ok$55 , \logical_op__imm_data__data$54 , \logical_op__fn_unit$53 , \logical_op__insn_type$52  } = { \output_logical_op__insn$42 , \output_logical_op__data_len$41 , \output_logical_op__is_signed$40 , \output_logical_op__is_32bit$39 , \output_logical_op__output_carry$38 , \output_logical_op__write_cr0$37 , \output_logical_op__invert_out$36 , \output_logical_op__input_carry$35 , \output_logical_op__zero_a$34 , \output_logical_op__invert_in$33 , \output_logical_op__oe__ok$32 , \output_logical_op__oe__oe$31 , \output_logical_op__rc__ok$30 , \output_logical_op__rc__rc$29 , \output_logical_op__imm_data__ok$28 , \output_logical_op__imm_data__data$27 , \output_logical_op__fn_unit$26 , \output_logical_op__insn_type$25  };
  assign \muxid$51  = \output_muxid$24 ;
  assign p_valid_i_p_ready_o = \$49 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$48  = p_valid_i;
  assign { \xer_so_ok$47 , output_xer_so } = { xer_so_ok, xer_so };
  assign { \cr_a_ok$46 , output_cr_a } = { cr_a_ok, cr_a };
  assign { output_o_ok, output_o } = { o_ok, o };
  assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign output_muxid = muxid;
endmodule

(* cells_not_processed =  1  *)
(* src = "ls180.v:4.1-5899.10" *)
module ls180(uart_tx, uart_rx, i2c_scl, i2c_sda_i, i2c_sda_o, i2c_sda_oe, spimaster_clk, spimaster_mosi, spimaster_cs_n, spimaster_miso, gpio_i, gpio_o, gpio_oe, eint_0, eint_1, eint_2, sdram_a, sdram_dq_i, sdram_dq_o, sdram_dq_oe, sdram_we_n, sdram_ras_n, sdram_cas_n, sdram_cs_n, sdram_cke, sdram_ba, sdram_dm, sdram_clock, sys_clk, sys_rst, jtag_tms, jtag_tck, jtag_tdi, jtag_tdo, nc);
  reg \initial  = 0;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0000_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0001_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0002_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0003_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0004_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0005_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0006_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0007_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0008_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0009_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0010_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0011_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0012_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0013_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0014_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0015_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0016_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0017_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0018_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0019_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0020_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0021_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0022_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0023_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [2:0] _0024_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [24:0] _0025_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [24:0] _0026_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [2:0] _0027_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [24:0] _0028_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [24:0] _0029_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [2:0] _0030_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [24:0] _0031_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [24:0] _0032_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [2:0] _0033_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [24:0] _0034_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [24:0] _0035_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [3:0] _0036_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [9:0] _0037_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [9:0] _0038_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [3:0] _0039_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [9:0] _0040_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [9:0] _0041_;
  (* src = "ls180.v:3879.1-3895.4" *)
  reg [1:0] _0042_;
  (* src = "ls180.v:3896.1-3912.4" *)
  reg [12:0] _0043_;
  (* src = "ls180.v:3913.1-3929.4" *)
  reg _0044_;
  (* src = "ls180.v:3930.1-3946.4" *)
  reg _0045_;
  (* src = "ls180.v:3947.1-3963.4" *)
  reg _0046_;
  (* src = "ls180.v:3964.1-3980.4" *)
  reg _0047_;
  (* src = "ls180.v:3981.1-3997.4" *)
  reg _0048_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0049_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0050_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0051_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0052_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0053_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0054_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [15:0] _0055_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0056_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [39:0] _0057_;
  (* src = "ls180.v:1489.1-1494.4" *)
  reg [2:0] _0058_;
  (* src = "ls180.v:2833.1-2837.4" *)
  reg [1:0] _0059_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0060_;
  (* src = "ls180.v:2822.1-2826.4" *)
  reg [1:0] _0061_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0062_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0063_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0064_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0065_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0066_;
  (* src = "ls180.v:2901.1-2911.4" *)
  reg [7:0] _0067_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0068_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0069_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0070_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0071_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0072_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0073_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0074_;
  (* src = "ls180.v:2912.1-2922.4" *)
  reg [7:0] _0075_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0076_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0077_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [7:0] _0078_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0079_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0080_;
  (* src = "ls180.v:4119.1-4121.4" *)
  reg _0081_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0082_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0083_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0084_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0085_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [63:0] _0086_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0087_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0088_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0089_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0090_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [63:0] _0091_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0092_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [19:0] _0093_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0094_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0095_;
  (* src = "ls180.v:3079.1-3090.4" *)
  reg _0096_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0097_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0098_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0099_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0100_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg [29:0] _0101_;
  (* src = "ls180.v:149.11-149.64" *)
  reg [1:0] _0102_;
  (* src = "ls180.v:148.11-148.64" *)
  reg [2:0] _0103_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0104_;
  (* src = "ls180.v:1510.1-1520.4" *)
  reg [31:0] _0105_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg [3:0] _0106_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0107_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0108_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0109_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg [29:0] _0110_;
  (* src = "ls180.v:164.11-164.64" *)
  reg [1:0] _0111_;
  (* src = "ls180.v:163.11-163.64" *)
  reg [2:0] _0112_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0113_;
  (* src = "ls180.v:1570.1-1580.4" *)
  reg [31:0] _0114_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg [3:0] _0115_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0116_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0117_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0118_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0119_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0120_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0121_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0122_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0123_;
  (* src = "ls180.v:108.12-108.41" *)
  reg [63:0] _0124_;
  (* src = "ls180.v:2923.1-2941.4" *)
  reg [15:0] _0125_;
  (* src = "ls180.v:2942.1-2960.4" *)
  reg [15:0] _0126_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [12:0] _0127_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [1:0] _0128_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0129_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0130_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0131_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0132_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [1:0] _0133_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [15:0] _0134_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg [15:0] _0135_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0136_;
  (* src = "ls180.v:4123.1-4243.4" *)
  reg _0137_;
  (* src = "ls180.v:118.5-118.64" *)
  reg _0138_;
  (* src = "ls180.v:120.5-120.65" *)
  reg _0139_;
  (* src = "ls180.v:119.5-119.65" *)
  reg _0140_;
  (* src = "ls180.v:113.5-113.58" *)
  reg _0141_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0142_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0143_;
  (* src = "ls180.v:61.5-61.41" *)
  reg _0144_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0145_;
  (* src = "ls180.v:70.5-70.41" *)
  reg _0146_;
  (* src = "ls180.v:1501.1-1508.4" *)
  reg [15:0] _0147_;
  (* src = "ls180.v:102.11-102.50" *)
  reg [1:0] _0148_;
  (* src = "ls180.v:101.11-101.50" *)
  reg [2:0] _0149_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [13:0] _0150_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg [13:0] _0151_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg _0152_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0153_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg [7:0] _0154_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg _0155_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0156_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg _0157_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg _0158_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg _0159_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg [31:0] _0160_;
  (* src = "ls180.v:1049.5-1049.48" *)
  reg _0161_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0162_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0163_;
  (* src = "ls180.v:2965.1-3001.4" *)
  reg [1:0] _0164_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0165_;
  (* src = "ls180.v:180.5-180.35" *)
  reg _0166_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0167_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0168_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0169_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0170_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0171_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0172_;
  (* src = "ls180.v:3079.1-3090.4" *)
  reg _0173_;
  (* src = "ls180.v:3079.1-3090.4" *)
  reg [31:0] _0174_;
  (* src = "ls180.v:3020.1-3028.4" *)
  reg [5:0] _0175_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [5:0] _0176_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0177_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0178_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0179_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0180_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0181_;
  (* src = "ls180.v:1631.1-1637.4" *)
  reg [3:0] _0182_;
  (* src = "ls180.v:1643.1-1648.4" *)
  reg _0183_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0184_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0185_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg [29:0] _0186_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0187_;
  (* src = "ls180.v:2713.1-2723.4" *)
  reg [15:0] _0188_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg [1:0] _0189_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0190_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0191_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0192_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0193_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [24:0] _0194_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [24:0] _0195_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [24:0] _0196_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [24:0] _0197_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [9:0] _0198_;
  (* src = "ls180.v:5549.1-5552.4" *)
  reg [9:0] _0199_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [9:0] _0200_;
  (* src = "ls180.v:5566.1-5569.4" *)
  reg [9:0] _0201_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0202_;
  (* src = "ls180.v:222.5-222.31" *)
  reg _0203_;
  (* src = "ls180.v:1652.1-1658.4" *)
  reg [3:0] _0204_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0205_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0206_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0207_;
  (* src = "ls180.v:960.5-960.17" *)
  reg _0208_;
  (* src = "ls180.v:3365.1-3381.4" *)
  reg _0209_;
  (* src = "ls180.v:3586.1-3602.4" *)
  reg _0210_;
  (* src = "ls180.v:3603.1-3619.4" *)
  reg _0211_;
  (* src = "ls180.v:3671.1-3678.4" *)
  reg [21:0] _0212_;
  (* src = "ls180.v:3679.1-3686.4" *)
  reg _0213_;
  (* src = "ls180.v:3687.1-3694.4" *)
  reg _0214_;
  (* src = "ls180.v:3695.1-3702.4" *)
  reg [21:0] _0215_;
  (* src = "ls180.v:3703.1-3710.4" *)
  reg _0216_;
  (* src = "ls180.v:3711.1-3718.4" *)
  reg _0217_;
  (* src = "ls180.v:3719.1-3726.4" *)
  reg [21:0] _0218_;
  (* src = "ls180.v:3727.1-3734.4" *)
  reg _0219_;
  (* src = "ls180.v:3382.1-3398.4" *)
  reg [12:0] _0220_;
  (* src = "ls180.v:3735.1-3742.4" *)
  reg _0221_;
  (* src = "ls180.v:3743.1-3750.4" *)
  reg [21:0] _0222_;
  (* src = "ls180.v:3751.1-3758.4" *)
  reg _0223_;
  (* src = "ls180.v:3759.1-3766.4" *)
  reg _0224_;
  (* src = "ls180.v:3767.1-3780.4" *)
  reg [29:0] _0225_;
  (* src = "ls180.v:3781.1-3794.4" *)
  reg [31:0] _0226_;
  (* src = "ls180.v:3795.1-3808.4" *)
  reg [3:0] _0227_;
  (* src = "ls180.v:3809.1-3822.4" *)
  reg _0228_;
  (* src = "ls180.v:3823.1-3836.4" *)
  reg _0229_;
  (* src = "ls180.v:3837.1-3850.4" *)
  reg _0230_;
  (* src = "ls180.v:3399.1-3415.4" *)
  reg [1:0] _0231_;
  (* src = "ls180.v:3851.1-3864.4" *)
  reg [2:0] _0232_;
  (* src = "ls180.v:3865.1-3878.4" *)
  reg [1:0] _0233_;
  (* src = "ls180.v:3416.1-3432.4" *)
  reg _0234_;
  (* src = "ls180.v:3433.1-3449.4" *)
  reg _0235_;
  (* src = "ls180.v:3450.1-3466.4" *)
  reg _0236_;
  (* src = "ls180.v:3518.1-3534.4" *)
  reg _0237_;
  (* src = "ls180.v:3535.1-3551.4" *)
  reg [12:0] _0238_;
  (* src = "ls180.v:3552.1-3568.4" *)
  reg [1:0] _0239_;
  (* src = "ls180.v:3569.1-3585.4" *)
  reg _0240_;
  (* src = "ls180.v:2827.1-2832.4" *)
  reg _0241_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0242_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [4:0] _0243_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0244_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0245_;
  (* src = "ls180.v:942.5-942.27" *)
  reg _0246_;
  (* src = "ls180.v:2885.1-2892.4" *)
  reg [3:0] _0247_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0248_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0249_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0250_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0251_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0252_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0253_;
  (* src = "ls180.v:1870.1-1877.4" *)
  reg _0254_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0255_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0256_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0257_;
  (* src = "ls180.v:427.5-427.59" *)
  reg _0258_;
  (* src = "ls180.v:410.5-410.62" *)
  reg _0259_;
  (* src = "ls180.v:411.5-411.61" *)
  reg _0260_;
  (* src = "ls180.v:1892.1-1899.4" *)
  reg [2:0] _0261_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0262_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0263_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [21:0] _0264_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0265_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0266_;
  (* src = "ls180.v:1859.1-1866.4" *)
  reg [12:0] _0267_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0268_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0269_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0270_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0271_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0272_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0273_;
  (* src = "ls180.v:2557.1-2565.4" *)
  reg _0274_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0275_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0276_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0277_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0278_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0279_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0280_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0281_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg _0282_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0283_;
  (* src = "ls180.v:469.32-469.71" *)
  reg _0284_;
  (* src = "ls180.v:467.32-467.70" *)
  reg _0285_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0286_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0287_;
  (* src = "ls180.v:2027.1-2034.4" *)
  reg _0288_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0289_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0290_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0291_;
  (* src = "ls180.v:509.5-509.59" *)
  reg _0292_;
  (* src = "ls180.v:492.5-492.62" *)
  reg _0293_;
  (* src = "ls180.v:493.5-493.61" *)
  reg _0294_;
  (* src = "ls180.v:2049.1-2056.4" *)
  reg [2:0] _0295_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0296_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0297_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [21:0] _0298_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0299_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0300_;
  (* src = "ls180.v:2016.1-2023.4" *)
  reg [12:0] _0301_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0302_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0303_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0304_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0305_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0306_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0307_;
  (* src = "ls180.v:2566.1-2574.4" *)
  reg _0308_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0309_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0310_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0311_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0312_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0313_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0314_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0315_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg _0316_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0317_;
  (* src = "ls180.v:551.32-551.71" *)
  reg _0318_;
  (* src = "ls180.v:549.32-549.70" *)
  reg _0319_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0320_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0321_;
  (* src = "ls180.v:2184.1-2191.4" *)
  reg _0322_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0323_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0324_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0325_;
  (* src = "ls180.v:591.5-591.59" *)
  reg _0326_;
  (* src = "ls180.v:574.5-574.62" *)
  reg _0327_;
  (* src = "ls180.v:575.5-575.61" *)
  reg _0328_;
  (* src = "ls180.v:2206.1-2213.4" *)
  reg [2:0] _0329_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0330_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0331_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [21:0] _0332_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0333_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0334_;
  (* src = "ls180.v:2173.1-2180.4" *)
  reg [12:0] _0335_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0336_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0337_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0338_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0339_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0340_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0341_;
  (* src = "ls180.v:2575.1-2583.4" *)
  reg _0342_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0343_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0344_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0345_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0346_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0347_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0348_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0349_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg _0350_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0351_;
  (* src = "ls180.v:633.32-633.71" *)
  reg _0352_;
  (* src = "ls180.v:631.32-631.70" *)
  reg _0353_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0354_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0355_;
  (* src = "ls180.v:2341.1-2348.4" *)
  reg _0356_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0357_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0358_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0359_;
  (* src = "ls180.v:673.5-673.59" *)
  reg _0360_;
  (* src = "ls180.v:656.5-656.62" *)
  reg _0361_;
  (* src = "ls180.v:657.5-657.61" *)
  reg _0362_;
  (* src = "ls180.v:2363.1-2370.4" *)
  reg [2:0] _0363_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0364_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0365_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [21:0] _0366_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0367_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0368_;
  (* src = "ls180.v:2330.1-2337.4" *)
  reg [12:0] _0369_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0370_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0371_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0372_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0373_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0374_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0375_;
  (* src = "ls180.v:2584.1-2592.4" *)
  reg _0376_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0377_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0378_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0379_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0380_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0381_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0382_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0383_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg _0384_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0385_;
  (* src = "ls180.v:715.32-715.71" *)
  reg _0386_;
  (* src = "ls180.v:713.32-713.70" *)
  reg _0387_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0388_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0389_;
  (* src = "ls180.v:2506.1-2511.4" *)
  reg _0390_;
  (* src = "ls180.v:2512.1-2517.4" *)
  reg _0391_;
  (* src = "ls180.v:2518.1-2523.4" *)
  reg _0392_;
  (* src = "ls180.v:723.5-723.38" *)
  reg _0393_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0394_;
  (* src = "ls180.v:2492.1-2498.4" *)
  reg [3:0] _0395_;
  (* src = "ls180.v:721.5-721.43" *)
  reg _0396_;
  (* src = "ls180.v:720.5-720.38" *)
  reg _0397_;
  (* src = "ls180.v:718.5-718.39" *)
  reg _0398_;
  (* src = "ls180.v:719.5-719.40" *)
  reg _0399_;
  (* src = "ls180.v:2539.1-2544.4" *)
  reg _0400_;
  (* src = "ls180.v:2545.1-2550.4" *)
  reg _0401_;
  (* src = "ls180.v:2551.1-2556.4" *)
  reg _0402_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0403_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0404_;
  (* src = "ls180.v:2525.1-2531.4" *)
  reg [3:0] _0405_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0406_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0407_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0408_;
  (* src = "ls180.v:1814.1-1844.4" *)
  reg _0409_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0410_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0411_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0412_;
  (* src = "ls180.v:371.5-371.37" *)
  reg _0413_;
  (* src = "ls180.v:372.5-372.38" *)
  reg _0414_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0415_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0416_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0417_;
  (* src = "ls180.v:1814.1-1844.4" *)
  reg _0418_;
  (* src = "ls180.v:307.5-307.33" *)
  reg _0419_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0420_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [5:0] _0421_;
  (* src = "ls180.v:356.5-356.30" *)
  reg _0422_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [12:0] _0423_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0424_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0425_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0426_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0427_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0428_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0429_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0430_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0431_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg _0432_;
  (* src = "ls180.v:2693.1-2706.4" *)
  reg [15:0] _0433_;
  (* src = "ls180.v:2693.1-2706.4" *)
  reg [1:0] _0434_;
  (* src = "ls180.v:257.5-257.31" *)
  reg _0435_;
  (* src = "ls180.v:1755.1-1771.4" *)
  reg _0436_;
  (* src = "ls180.v:1755.1-1771.4" *)
  reg _0437_;
  (* src = "ls180.v:1755.1-1771.4" *)
  reg _0438_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [15:0] _0439_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0440_;
  (* src = "ls180.v:1755.1-1771.4" *)
  reg _0441_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0442_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [12:0] _0443_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [1:0] _0444_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0445_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0446_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0447_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0448_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0449_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0450_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0451_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0452_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [15:0] _0453_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0454_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [1:0] _0455_;
  (* src = "ls180.v:754.12-754.31" *)
  reg [12:0] _0456_;
  (* src = "ls180.v:755.11-755.30" *)
  reg [1:0] _0457_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0458_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0459_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0460_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0461_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0462_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0463_;
  (* src = "ls180.v:1814.1-1844.4" *)
  reg _0464_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg [15:0] _0465_;
  (* src = "ls180.v:1697.1-1751.4" *)
  reg _0466_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [15:0] _0467_;
  (* src = "ls180.v:757.5-757.26" *)
  reg _0468_;
  (* src = "ls180.v:758.5-758.26" *)
  reg _0469_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg [1:0] _0470_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0471_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0472_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0473_;
  (* src = "ls180.v:762.32-762.58" *)
  reg _0474_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [4:0] _0475_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0476_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [9:0] _0477_;
  (* src = "ls180.v:760.32-760.58" *)
  reg _0478_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0479_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0480_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0481_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [15:0] _0482_;
  (* src = "ls180.v:1908.1-2001.4" *)
  reg [2:0] _0483_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0484_;
  (* src = "ls180.v:2065.1-2158.4" *)
  reg [2:0] _0485_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0486_;
  (* src = "ls180.v:2222.1-2315.4" *)
  reg [2:0] _0487_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0488_;
  (* src = "ls180.v:2379.1-2472.4" *)
  reg [2:0] _0489_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0490_;
  (* src = "ls180.v:1522.1-1568.4" *)
  reg _0491_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0492_;
  (* src = "ls180.v:1582.1-1628.4" *)
  reg _0493_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0494_;
  (* src = "ls180.v:1022.5-1022.32" *)
  reg _0495_;
  (* src = "ls180.v:1023.5-1023.32" *)
  reg _0496_;
  (* src = "ls180.v:1024.5-1024.32" *)
  reg _0497_;
  (* src = "ls180.v:1025.5-1025.32" *)
  reg _0498_;
  (* src = "ls180.v:2597.1-2669.4" *)
  reg [2:0] _0499_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [2:0] _0500_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0501_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0502_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0503_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0504_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0505_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0506_;
  (* src = "ls180.v:1814.1-1844.4" *)
  reg [1:0] _0507_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [1:0] _0508_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0509_;
  (* src = "ls180.v:3467.1-3483.4" *)
  reg _0510_;
  (* src = "ls180.v:3484.1-3500.4" *)
  reg _0511_;
  (* src = "ls180.v:3501.1-3517.4" *)
  reg _0512_;
  (* src = "ls180.v:3620.1-3636.4" *)
  reg _0513_;
  (* src = "ls180.v:3637.1-3653.4" *)
  reg _0514_;
  (* src = "ls180.v:3654.1-3670.4" *)
  reg _0515_;
  (* src = "ls180.v:2816.1-2821.4" *)
  reg _0516_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0517_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [4:0] _0518_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0519_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0520_;
  (* src = "ls180.v:905.5-905.27" *)
  reg _0521_;
  (* src = "ls180.v:888.5-888.30" *)
  reg _0522_;
  (* src = "ls180.v:889.5-889.29" *)
  reg _0523_;
  (* src = "ls180.v:2855.1-2862.4" *)
  reg [3:0] _0524_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0525_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0526_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0527_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0528_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0529_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0530_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0531_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0532_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0533_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0534_;
  (* src = "ls180.v:833.5-833.33" *)
  reg _0535_;
  (* src = "ls180.v:834.5-834.32" *)
  reg _0536_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0537_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0538_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [31:0] _0539_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [3:0] _0540_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0541_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg [7:0] _0542_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0543_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0544_;
  (* src = "ls180.v:2725.1-2771.4" *)
  reg _0545_;
  (* src = "ls180.v:801.5-801.24" *)
  reg _0546_;
  (* src = "ls180.v:4245.1-5442.4" *)
  reg _0547_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0548_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0549_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0550_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0551_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0552_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0553_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0554_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0555_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0556_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [6:0] _0557_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0558_;
  (* src = "ls180.v:5446.1-5456.4" *)
  reg [31:0] _0559_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0560_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0561_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0562_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0563_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0564_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0565_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0566_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0567_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0568_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [4:0] _0569_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0570_;
  (* src = "ls180.v:5466.1-5476.4" *)
  reg [31:0] _0571_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [2:0] _0572_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [24:0] _0573_;
  (* src = "ls180.v:5486.1-5490.4" *)
  reg [24:0] _0574_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [2:0] _0575_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [24:0] _0576_;
  (* src = "ls180.v:5500.1-5504.4" *)
  reg [24:0] _0577_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [2:0] _0578_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [24:0] _0579_;
  (* src = "ls180.v:5514.1-5518.4" *)
  reg [24:0] _0580_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [2:0] _0581_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [24:0] _0582_;
  (* src = "ls180.v:5528.1-5532.4" *)
  reg [24:0] _0583_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [3:0] _0584_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [9:0] _0585_;
  (* src = "ls180.v:5543.1-5547.4" *)
  reg [9:0] _0586_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [3:0] _0587_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [9:0] _0588_;
  (* src = "ls180.v:5560.1-5564.4" *)
  reg [9:0] _0589_;
  (* src = "ls180.v:1359.11-1359.30" *)
  reg [1:0] _0590_;
  (* src = "ls180.v:1360.12-1360.32" *)
  reg [12:0] _0591_;
  (* src = "ls180.v:1361.5-1361.24" *)
  reg _0592_;
  (* src = "ls180.v:1362.5-1362.24" *)
  reg _0593_;
  (* src = "ls180.v:1363.5-1363.24" *)
  reg _0594_;
  (* src = "ls180.v:1364.5-1364.24" *)
  reg _0595_;
  (* src = "ls180.v:1365.5-1365.24" *)
  reg _0596_;
  (* src = "ls180.v:814.5-814.24" *)
  reg _0597_;
  (* src = "ls180.v:811.5-811.29" *)
  reg _0598_;
  (* src = "ls180.v:1033.5-1033.53" *)
  reg _0599_;
  (* src = "ls180.v:1034.5-1034.56" *)
  reg _0600_;
  (* src = "ls180.v:813.12-813.35" *)
  reg [31:0] _0601_;
  (* src = "ls180.v:810.5-810.26" *)
  reg _0602_;
  (* src = "ls180.v:245.12-245.33" *)
  reg [15:0] _0603_;
  (* src = "ls180.v:246.5-246.31" *)
  reg _0604_;
  (* src = "ls180.v:981.12-981.25" *)
  reg [39:0] _0605_;
  (* src = "ls180.v:979.11-979.26" *)
  reg [2:0] _0606_;
  (* src = "ls180.v:869.11-869.40" *)
  reg [1:0] _0607_;
  (* src = "ls180.v:871.5-871.27" *)
  reg _0608_;
  (* src = "ls180.v:865.11-865.39" *)
  reg [1:0] _0609_;
  (* src = "ls180.v:870.11-870.38" *)
  reg [1:0] _0610_;
  (* src = "ls180.v:962.5-962.23" *)
  reg _0611_;
  (* src = "ls180.v:961.11-961.34" *)
  reg [7:0] _0612_;
  (* src = "ls180.v:966.5-966.24" *)
  reg _0613_;
  (* src = "ls180.v:965.11-965.35" *)
  reg [7:0] _0614_;
  (* src = "ls180.v:967.11-967.35" *)
  reg [7:0] _0615_;
  (* src = "ls180.v:968.11-968.35" *)
  reg [7:0] _0616_;
  (* src = "ls180.v:969.11-969.36" *)
  reg [7:0] _0617_;
  (* src = "ls180.v:963.11-963.30" *)
  reg [7:0] _0618_;
  (* src = "ls180.v:971.5-971.23" *)
  reg _0619_;
  (* src = "ls180.v:970.11-970.34" *)
  reg [7:0] _0620_;
  (* src = "ls180.v:975.5-975.24" *)
  reg _0621_;
  (* src = "ls180.v:974.11-974.35" *)
  reg [7:0] _0622_;
  (* src = "ls180.v:976.11-976.35" *)
  reg [7:0] _0623_;
  (* src = "ls180.v:977.11-977.35" *)
  reg [7:0] _0624_;
  (* src = "ls180.v:978.11-978.36" *)
  reg [7:0] _0625_;
  (* src = "ls180.v:972.11-972.30" *)
  reg [7:0] _0626_;
  (* src = "ls180.v:986.5-986.18" *)
  reg _0627_;
  (* src = "ls180.v:985.11-985.29" *)
  reg [2:0] _0628_;
  (* src = "ls180.v:230.5-230.19" *)
  reg _0629_;
  (* src = "ls180.v:50.12-50.42" *)
  reg [31:0] _0630_;
  (* src = "ls180.v:152.5-152.42" *)
  reg _0631_;
  (* src = "ls180.v:992.5-992.77" *)
  reg _0632_;
  (* src = "ls180.v:993.5-993.80" *)
  reg _0633_;
  (* src = "ls180.v:154.12-154.48" *)
  reg [63:0] _0634_;
  (* src = "ls180.v:151.5-151.39" *)
  reg _0635_;
  (* src = "ls180.v:167.5-167.42" *)
  reg _0636_;
  (* src = "ls180.v:996.5-996.77" *)
  reg _0637_;
  (* src = "ls180.v:997.5-997.80" *)
  reg _0638_;
  (* src = "ls180.v:169.12-169.48" *)
  reg [63:0] _0639_;
  (* src = "ls180.v:166.5-166.39" *)
  reg _0640_;
  (* src = "ls180.v:1068.12-1068.43" *)
  reg [19:0] _0641_;
  (* src = "ls180.v:190.5-190.29" *)
  reg _0642_;
  (* src = "ls180.v:189.5-189.34" *)
  reg _0643_;
  (* src = "ls180.v:1065.5-1065.29" *)
  reg _0644_;
  (* src = "ls180.v:210.5-210.39" *)
  reg _0645_;
  (* src = "ls180.v:209.5-209.44" *)
  reg _0646_;
  (* src = "ls180.v:1062.11-1062.35" *)
  reg [1:0] _0647_;
  (* src = "ls180.v:1072.11-1072.55" *)
  reg [7:0] _0648_;
  (* src = "ls180.v:140.12-140.66" *)
  reg [29:0] _0649_;
  (* src = "ls180.v:144.5-144.58" *)
  reg _0650_;
  (* src = "ls180.v:141.12-141.68" *)
  reg [31:0] _0651_;
  (* src = "ls180.v:143.11-143.64" *)
  reg [3:0] _0652_;
  (* src = "ls180.v:145.5-145.58" *)
  reg _0653_;
  (* src = "ls180.v:147.5-147.57" *)
  reg _0654_;
  (* src = "ls180.v:1113.11-1113.55" *)
  reg [7:0] _0655_;
  (* src = "ls180.v:155.12-155.66" *)
  reg [29:0] _0656_;
  (* src = "ls180.v:159.5-159.58" *)
  reg _0657_;
  (* src = "ls180.v:156.12-156.68" *)
  reg [31:0] _0658_;
  (* src = "ls180.v:158.11-158.64" *)
  reg [3:0] _0659_;
  (* src = "ls180.v:160.5-160.58" *)
  reg _0660_;
  (* src = "ls180.v:162.5-162.57" *)
  reg _0661_;
  (* src = "ls180.v:1130.11-1130.55" *)
  reg [7:0] _0662_;
  (* src = "ls180.v:1147.11-1147.55" *)
  reg [7:0] _0663_;
  (* src = "ls180.v:1160.11-1160.55" *)
  reg [7:0] _0664_;
  (* src = "ls180.v:1201.11-1201.55" *)
  reg [7:0] _0665_;
  (* src = "ls180.v:1266.11-1266.55" *)
  reg [7:0] _0666_;
  (* src = "ls180.v:1291.11-1291.55" *)
  reg [7:0] _0667_;
  (* src = "ls180.v:123.12-123.65" *)
  reg [15:0] _0668_;
  (* src = "ls180.v:124.12-124.66" *)
  reg [15:0] _0669_;
  (* src = "ls180.v:128.12-128.66" *)
  reg [12:0] _0670_;
  (* src = "ls180.v:137.11-137.65" *)
  reg [1:0] _0671_;
  (* src = "ls180.v:134.5-134.62" *)
  reg _0672_;
  (* src = "ls180.v:136.5-136.60" *)
  reg _0673_;
  (* src = "ls180.v:139.5-139.62" *)
  reg _0674_;
  (* src = "ls180.v:135.5-135.61" *)
  reg _0675_;
  (* src = "ls180.v:138.11-138.65" *)
  reg [1:0] _0676_;
  (* src = "ls180.v:130.12-130.69" *)
  reg [15:0] _0677_;
  (* src = "ls180.v:131.12-131.70" *)
  reg [15:0] _0678_;
  (* src = "ls180.v:133.5-133.62" *)
  reg _0679_;
  (* src = "ls180.v:132.5-132.61" *)
  reg _0680_;
  (* src = "ls180.v:112.5-112.58" *)
  reg _0681_;
  (* src = "ls180.v:59.5-59.41" *)
  reg _0682_;
  (* src = "ls180.v:68.5-68.41" *)
  reg _0683_;
  (* src = "ls180.v:52.12-52.50" *)
  reg [15:0] _0684_;
  (* src = "ls180.v:1035.12-1035.47" *)
  reg [13:0] _0685_;
  (* src = "ls180.v:1317.12-1317.71" *)
  reg [13:0] _0686_;
  (* src = "ls180.v:1318.5-1318.66" *)
  reg _0687_;
  (* src = "ls180.v:1037.11-1037.47" *)
  reg [7:0] _0688_;
  (* src = "ls180.v:1315.11-1315.71" *)
  reg [7:0] _0689_;
  (* src = "ls180.v:1316.5-1316.68" *)
  reg _0690_;
  (* src = "ls180.v:1036.5-1036.38" *)
  reg _0691_;
  (* src = "ls180.v:1319.5-1319.62" *)
  reg _0692_;
  (* src = "ls180.v:1320.5-1320.65" *)
  reg _0693_;
  (* src = "ls180.v:1045.5-1045.48" *)
  reg _0694_;
  (* src = "ls180.v:1041.12-1041.58" *)
  reg [31:0] _0695_;
  (* src = "ls180.v:186.5-186.31" *)
  reg _0696_;
  (* src = "ls180.v:185.12-185.44" *)
  reg [31:0] _0697_;
  (* src = "ls180.v:1314.11-1314.40" *)
  reg [1:0] _0698_;
  (* src = "ls180.v:176.5-176.35" *)
  reg _0699_;
  (* src = "ls180.v:188.5-188.33" *)
  reg _0700_;
  (* src = "ls180.v:187.12-187.46" *)
  reg [31:0] _0701_;
  (* src = "ls180.v:43.5-43.32" *)
  reg _0702_;
  (* src = "ls180.v:42.5-42.37" *)
  reg _0703_;
  (* src = "ls180.v:45.5-45.34" *)
  reg _0704_;
  (* src = "ls180.v:44.12-44.55" *)
  reg [31:0] _0705_;
  (* src = "ls180.v:1056.5-1056.34" *)
  reg _0706_;
  (* src = "ls180.v:1052.12-1052.44" *)
  reg [31:0] _0707_;
  (* src = "ls180.v:1063.11-1063.39" *)
  reg [5:0] _0708_;
  (* src = "ls180.v:1064.11-1064.41" *)
  reg [5:0] _0709_;
  (* src = "ls180.v:1313.11-1313.35" *)
  reg [1:0] _0710_;
  (* src = "ls180.v:192.5-192.39" *)
  reg _0711_;
  (* src = "ls180.v:191.5-191.44" *)
  reg _0712_;
  (* src = "ls180.v:211.12-211.37" *)
  reg [31:0] _0713_;
  (* src = "ls180.v:193.12-193.44" *)
  reg [31:0] _0714_;
  (* src = "ls180.v:183.11-183.32" *)
  reg [3:0] _0715_;
  (* src = "ls180.v:199.5-199.34" *)
  reg _0716_;
  (* src = "ls180.v:200.5-200.40" *)
  reg _0717_;
  (* src = "ls180.v:197.5-197.36" *)
  reg _0718_;
  (* src = "ls180.v:802.12-802.35" *)
  reg [29:0] _0719_;
  (* src = "ls180.v:806.5-806.27" *)
  reg _0720_;
  (* src = "ls180.v:803.12-803.37" *)
  reg [15:0] _0721_;
  (* src = "ls180.v:805.11-805.33" *)
  reg [1:0] _0722_;
  (* src = "ls180.v:807.5-807.27" *)
  reg _0723_;
  (* src = "ls180.v:809.5-809.26" *)
  reg _0724_;
  (* src = "ls180.v:218.5-218.31" *)
  reg _0725_;
  (* src = "ls180.v:225.11-225.24" *)
  reg [3:0] _0726_;
  (* src = "ls180.v:247.11-247.27" *)
  reg [2:0] _0727_;
  (* src = "ls180.v:1437.32-1437.44" *)
  reg _0728_;
  (* src = "ls180.v:1438.32-1438.44" *)
  reg _0729_;
  (* src = "ls180.v:1321.5-1321.28" *)
  reg _0730_;
  (* src = "ls180.v:1334.5-1334.29" *)
  reg _0731_;
  (* src = "ls180.v:1335.5-1335.29" *)
  reg _0732_;
  (* src = "ls180.v:1339.12-1339.37" *)
  reg [21:0] _0733_;
  (* src = "ls180.v:1340.5-1340.29" *)
  reg _0734_;
  (* src = "ls180.v:1341.5-1341.29" *)
  reg _0735_;
  (* src = "ls180.v:1342.12-1342.37" *)
  reg [21:0] _0736_;
  (* src = "ls180.v:1343.5-1343.29" *)
  reg _0737_;
  (* src = "ls180.v:1344.5-1344.29" *)
  reg _0738_;
  (* src = "ls180.v:1345.12-1345.37" *)
  reg [21:0] _0739_;
  (* src = "ls180.v:1346.5-1346.29" *)
  reg _0740_;
  (* src = "ls180.v:1322.12-1322.36" *)
  reg [12:0] _0741_;
  (* src = "ls180.v:1347.5-1347.29" *)
  reg _0742_;
  (* src = "ls180.v:1348.12-1348.37" *)
  reg [21:0] _0743_;
  (* src = "ls180.v:1349.5-1349.29" *)
  reg _0744_;
  (* src = "ls180.v:1350.5-1350.29" *)
  reg _0745_;
  (* src = "ls180.v:1351.12-1351.37" *)
  reg [29:0] _0746_;
  (* src = "ls180.v:1352.12-1352.37" *)
  reg [31:0] _0747_;
  (* src = "ls180.v:1353.11-1353.35" *)
  reg [3:0] _0748_;
  (* src = "ls180.v:1354.5-1354.29" *)
  reg _0749_;
  (* src = "ls180.v:1355.5-1355.29" *)
  reg _0750_;
  (* src = "ls180.v:1356.5-1356.29" *)
  reg _0751_;
  (* src = "ls180.v:1323.11-1323.34" *)
  reg [1:0] _0752_;
  (* src = "ls180.v:1357.11-1357.35" *)
  reg [2:0] _0753_;
  (* src = "ls180.v:1358.11-1358.35" *)
  reg [1:0] _0754_;
  (* src = "ls180.v:1324.5-1324.28" *)
  reg _0755_;
  (* src = "ls180.v:1325.5-1325.28" *)
  reg _0756_;
  (* src = "ls180.v:1326.5-1326.28" *)
  reg _0757_;
  (* src = "ls180.v:1330.5-1330.28" *)
  reg _0758_;
  (* src = "ls180.v:1331.12-1331.36" *)
  reg [12:0] _0759_;
  (* src = "ls180.v:1332.11-1332.34" *)
  reg [1:0] _0760_;
  (* src = "ls180.v:1333.5-1333.28" *)
  reg _0761_;
  (* src = "ls180.v:860.5-860.20" *)
  reg _0762_;
  (* src = "ls180.v:944.11-944.33" *)
  reg [3:0] _0763_;
  (* src = "ls180.v:941.11-941.32" *)
  reg [4:0] _0764_;
  (* src = "ls180.v:943.11-943.33" *)
  reg [3:0] _0765_;
  (* src = "ls180.v:934.5-934.28" *)
  reg _0766_;
  (* src = "ls180.v:945.11-945.36" *)
  reg [3:0] _0767_;
  (* src = "ls180.v:861.5-861.26" *)
  reg _0768_;
  (* src = "ls180.v:858.5-858.22" *)
  reg _0769_;
  (* src = "ls180.v:309.5-309.28" *)
  reg _0770_;
  (* src = "ls180.v:308.12-308.41" *)
  reg [12:0] _0771_;
  (* src = "ls180.v:311.5-311.29" *)
  reg _0772_;
  (* src = "ls180.v:310.11-310.40" *)
  reg [1:0] _0773_;
  (* src = "ls180.v:407.5-407.45" *)
  reg _0774_;
  (* src = "ls180.v:429.11-429.65" *)
  reg [2:0] _0775_;
  (* src = "ls180.v:426.11-426.63" *)
  reg [3:0] _0776_;
  (* src = "ls180.v:428.11-428.65" *)
  reg [2:0] _0777_;
  (* src = "ls180.v:430.11-430.68" *)
  reg [2:0] _0778_;
  (* src = "ls180.v:453.5-453.54" *)
  reg _0779_;
  (* src = "ls180.v:454.5-454.53" *)
  reg _0780_;
  (* src = "ls180.v:456.12-456.69" *)
  reg [21:0] _0781_;
  (* src = "ls180.v:455.5-455.59" *)
  reg _0782_;
  (* src = "ls180.v:451.5-451.54" *)
  reg _0783_;
  (* src = "ls180.v:399.12-399.52" *)
  reg [12:0] _0784_;
  (* src = "ls180.v:401.5-401.46" *)
  reg _0785_;
  (* src = "ls180.v:404.5-404.49" *)
  reg _0786_;
  (* src = "ls180.v:405.5-405.50" *)
  reg _0787_;
  (* src = "ls180.v:406.5-406.51" *)
  reg _0788_;
  (* src = "ls180.v:402.5-402.46" *)
  reg _0789_;
  (* src = "ls180.v:403.5-403.45" *)
  reg _0790_;
  (* src = "ls180.v:398.5-398.40" *)
  reg _0791_;
  (* src = "ls180.v:397.5-397.40" *)
  reg _0792_;
  (* src = "ls180.v:396.5-396.42" *)
  reg _0793_;
  (* src = "ls180.v:394.5-394.46" *)
  reg _0794_;
  (* src = "ls180.v:393.5-393.46" *)
  reg _0795_;
  (* src = "ls180.v:457.12-457.42" *)
  reg [12:0] _0796_;
  (* src = "ls180.v:461.5-461.40" *)
  reg _0797_;
  (* src = "ls180.v:462.5-462.49" *)
  reg _0798_;
  (* src = "ls180.v:460.5-460.39" *)
  reg _0799_;
  (* src = "ls180.v:458.5-458.41" *)
  reg _0800_;
  (* src = "ls180.v:465.11-465.50" *)
  reg [2:0] _0801_;
  (* src = "ls180.v:464.32-464.71" *)
  reg _0802_;
  (* src = "ls180.v:489.5-489.45" *)
  reg _0803_;
  (* src = "ls180.v:511.11-511.65" *)
  reg [2:0] _0804_;
  (* src = "ls180.v:508.11-508.63" *)
  reg [3:0] _0805_;
  (* src = "ls180.v:510.11-510.65" *)
  reg [2:0] _0806_;
  (* src = "ls180.v:512.11-512.68" *)
  reg [2:0] _0807_;
  (* src = "ls180.v:535.5-535.54" *)
  reg _0808_;
  (* src = "ls180.v:536.5-536.53" *)
  reg _0809_;
  (* src = "ls180.v:538.12-538.69" *)
  reg [21:0] _0810_;
  (* src = "ls180.v:537.5-537.59" *)
  reg _0811_;
  (* src = "ls180.v:533.5-533.54" *)
  reg _0812_;
  (* src = "ls180.v:481.12-481.52" *)
  reg [12:0] _0813_;
  (* src = "ls180.v:483.5-483.46" *)
  reg _0814_;
  (* src = "ls180.v:486.5-486.49" *)
  reg _0815_;
  (* src = "ls180.v:487.5-487.50" *)
  reg _0816_;
  (* src = "ls180.v:488.5-488.51" *)
  reg _0817_;
  (* src = "ls180.v:484.5-484.46" *)
  reg _0818_;
  (* src = "ls180.v:485.5-485.45" *)
  reg _0819_;
  (* src = "ls180.v:480.5-480.40" *)
  reg _0820_;
  (* src = "ls180.v:479.5-479.40" *)
  reg _0821_;
  (* src = "ls180.v:478.5-478.42" *)
  reg _0822_;
  (* src = "ls180.v:476.5-476.46" *)
  reg _0823_;
  (* src = "ls180.v:475.5-475.46" *)
  reg _0824_;
  (* src = "ls180.v:539.12-539.42" *)
  reg [12:0] _0825_;
  (* src = "ls180.v:543.5-543.40" *)
  reg _0826_;
  (* src = "ls180.v:544.5-544.49" *)
  reg _0827_;
  (* src = "ls180.v:542.5-542.39" *)
  reg _0828_;
  (* src = "ls180.v:540.5-540.41" *)
  reg _0829_;
  (* src = "ls180.v:547.11-547.50" *)
  reg [2:0] _0830_;
  (* src = "ls180.v:546.32-546.71" *)
  reg _0831_;
  (* src = "ls180.v:571.5-571.45" *)
  reg _0832_;
  (* src = "ls180.v:593.11-593.65" *)
  reg [2:0] _0833_;
  (* src = "ls180.v:590.11-590.63" *)
  reg [3:0] _0834_;
  (* src = "ls180.v:592.11-592.65" *)
  reg [2:0] _0835_;
  (* src = "ls180.v:594.11-594.68" *)
  reg [2:0] _0836_;
  (* src = "ls180.v:617.5-617.54" *)
  reg _0837_;
  (* src = "ls180.v:618.5-618.53" *)
  reg _0838_;
  (* src = "ls180.v:620.12-620.69" *)
  reg [21:0] _0839_;
  (* src = "ls180.v:619.5-619.59" *)
  reg _0840_;
  (* src = "ls180.v:615.5-615.54" *)
  reg _0841_;
  (* src = "ls180.v:563.12-563.52" *)
  reg [12:0] _0842_;
  (* src = "ls180.v:565.5-565.46" *)
  reg _0843_;
  (* src = "ls180.v:568.5-568.49" *)
  reg _0844_;
  (* src = "ls180.v:569.5-569.50" *)
  reg _0845_;
  (* src = "ls180.v:570.5-570.51" *)
  reg _0846_;
  (* src = "ls180.v:566.5-566.46" *)
  reg _0847_;
  (* src = "ls180.v:567.5-567.45" *)
  reg _0848_;
  (* src = "ls180.v:562.5-562.40" *)
  reg _0849_;
  (* src = "ls180.v:561.5-561.40" *)
  reg _0850_;
  (* src = "ls180.v:560.5-560.42" *)
  reg _0851_;
  (* src = "ls180.v:558.5-558.46" *)
  reg _0852_;
  (* src = "ls180.v:557.5-557.46" *)
  reg _0853_;
  (* src = "ls180.v:621.12-621.42" *)
  reg [12:0] _0854_;
  (* src = "ls180.v:625.5-625.40" *)
  reg _0855_;
  (* src = "ls180.v:626.5-626.49" *)
  reg _0856_;
  (* src = "ls180.v:624.5-624.39" *)
  reg _0857_;
  (* src = "ls180.v:622.5-622.41" *)
  reg _0858_;
  (* src = "ls180.v:629.11-629.50" *)
  reg [2:0] _0859_;
  (* src = "ls180.v:628.32-628.71" *)
  reg _0860_;
  (* src = "ls180.v:653.5-653.45" *)
  reg _0861_;
  (* src = "ls180.v:675.11-675.65" *)
  reg [2:0] _0862_;
  (* src = "ls180.v:672.11-672.63" *)
  reg [3:0] _0863_;
  (* src = "ls180.v:674.11-674.65" *)
  reg [2:0] _0864_;
  (* src = "ls180.v:676.11-676.68" *)
  reg [2:0] _0865_;
  (* src = "ls180.v:699.5-699.54" *)
  reg _0866_;
  (* src = "ls180.v:700.5-700.53" *)
  reg _0867_;
  (* src = "ls180.v:702.12-702.69" *)
  reg [21:0] _0868_;
  (* src = "ls180.v:701.5-701.59" *)
  reg _0869_;
  (* src = "ls180.v:697.5-697.54" *)
  reg _0870_;
  (* src = "ls180.v:645.12-645.52" *)
  reg [12:0] _0871_;
  (* src = "ls180.v:647.5-647.46" *)
  reg _0872_;
  (* src = "ls180.v:650.5-650.49" *)
  reg _0873_;
  (* src = "ls180.v:651.5-651.50" *)
  reg _0874_;
  (* src = "ls180.v:652.5-652.51" *)
  reg _0875_;
  (* src = "ls180.v:648.5-648.46" *)
  reg _0876_;
  (* src = "ls180.v:649.5-649.45" *)
  reg _0877_;
  (* src = "ls180.v:644.5-644.40" *)
  reg _0878_;
  (* src = "ls180.v:643.5-643.40" *)
  reg _0879_;
  (* src = "ls180.v:642.5-642.42" *)
  reg _0880_;
  (* src = "ls180.v:640.5-640.46" *)
  reg _0881_;
  (* src = "ls180.v:639.5-639.46" *)
  reg _0882_;
  (* src = "ls180.v:703.12-703.42" *)
  reg [12:0] _0883_;
  (* src = "ls180.v:707.5-707.40" *)
  reg _0884_;
  (* src = "ls180.v:708.5-708.49" *)
  reg _0885_;
  (* src = "ls180.v:706.5-706.39" *)
  reg _0886_;
  (* src = "ls180.v:704.5-704.41" *)
  reg _0887_;
  (* src = "ls180.v:711.11-711.50" *)
  reg [2:0] _0888_;
  (* src = "ls180.v:710.32-710.71" *)
  reg _0889_;
  (* src = "ls180.v:726.5-726.44" *)
  reg _0890_;
  (* src = "ls180.v:727.5-727.44" *)
  reg _0891_;
  (* src = "ls180.v:728.5-728.43" *)
  reg _0892_;
  (* src = "ls180.v:734.11-734.40" *)
  reg [1:0] _0893_;
  (* src = "ls180.v:732.11-732.41" *)
  reg [3:0] _0894_;
  (* src = "ls180.v:744.5-744.44" *)
  reg _0895_;
  (* src = "ls180.v:745.5-745.44" *)
  reg _0896_;
  (* src = "ls180.v:746.5-746.43" *)
  reg _0897_;
  (* src = "ls180.v:741.5-741.38" *)
  reg _0898_;
  (* src = "ls180.v:752.11-752.40" *)
  reg [1:0] _0899_;
  (* src = "ls180.v:750.11-750.41" *)
  reg [3:0] _0900_;
  (* src = "ls180.v:739.5-739.43" *)
  reg _0901_;
  (* src = "ls180.v:736.5-736.39" *)
  reg _0902_;
  (* src = "ls180.v:737.5-737.40" *)
  reg _0903_;
  (* src = "ls180.v:365.5-365.26" *)
  reg _0904_;
  (* src = "ls180.v:366.12-366.39" *)
  reg [12:0] _0905_;
  (* src = "ls180.v:367.11-367.38" *)
  reg [1:0] _0906_;
  (* src = "ls180.v:368.5-368.33" *)
  reg _0907_;
  (* src = "ls180.v:369.5-369.33" *)
  reg _0908_;
  (* src = "ls180.v:370.5-370.32" *)
  reg _0909_;
  (* src = "ls180.v:364.5-364.27" *)
  reg _0910_;
  (* src = "ls180.v:363.5-363.27" *)
  reg _0911_;
  (* src = "ls180.v:303.5-303.28" *)
  reg _0912_;
  (* src = "ls180.v:302.11-302.39" *)
  reg [5:0] _0913_;
  (* src = "ls180.v:347.12-347.40" *)
  reg [12:0] _0914_;
  (* src = "ls180.v:348.11-348.35" *)
  reg [1:0] _0915_;
  (* src = "ls180.v:349.5-349.30" *)
  reg _0916_;
  (* src = "ls180.v:350.5-350.29" *)
  reg _0917_;
  (* src = "ls180.v:351.5-351.30" *)
  reg _0918_;
  (* src = "ls180.v:360.5-360.34" *)
  reg _0919_;
  (* src = "ls180.v:352.5-352.29" *)
  reg _0920_;
  (* src = "ls180.v:358.5-358.34" *)
  reg _0921_;
  (* src = "ls180.v:771.5-771.21" *)
  reg _0922_;
  (* src = "ls180.v:774.5-774.21" *)
  reg _0923_;
  (* src = "ls180.v:344.12-344.41" *)
  reg [15:0] _0924_;
  (* src = "ls180.v:345.11-345.42" *)
  reg [1:0] _0925_;
  (* src = "ls180.v:250.5-250.31" *)
  reg _0926_;
  (* src = "ls180.v:251.5-251.30" *)
  reg _0927_;
  (* src = "ls180.v:252.5-252.31" *)
  reg _0928_;
  (* src = "ls180.v:262.12-262.40" *)
  reg [15:0] _0929_;
  (* src = "ls180.v:263.5-263.38" *)
  reg _0930_;
  (* src = "ls180.v:253.5-253.30" *)
  reg _0931_;
  (* src = "ls180.v:289.5-289.33" *)
  reg _0932_;
  (* src = "ls180.v:280.12-280.43" *)
  reg [12:0] _0933_;
  (* src = "ls180.v:281.11-281.38" *)
  reg [1:0] _0934_;
  (* src = "ls180.v:282.5-282.33" *)
  reg _0935_;
  (* src = "ls180.v:286.5-286.31" *)
  reg _0936_;
  (* src = "ls180.v:283.5-283.32" *)
  reg _0937_;
  (* src = "ls180.v:287.5-287.31" *)
  reg _0938_;
  (* src = "ls180.v:284.5-284.33" *)
  reg _0939_;
  (* src = "ls180.v:293.5-293.37" *)
  reg _0940_;
  (* src = "ls180.v:288.5-288.35" *)
  reg _0941_;
  (* src = "ls180.v:285.5-285.32" *)
  reg _0942_;
  (* src = "ls180.v:290.12-290.42" *)
  reg [15:0] _0943_;
  (* src = "ls180.v:291.5-291.37" *)
  reg _0944_;
  (* src = "ls180.v:292.11-292.45" *)
  reg [1:0] _0945_;
  (* src = "ls180.v:381.5-381.33" *)
  reg _0946_;
  (* src = "ls180.v:380.5-380.33" *)
  reg _0947_;
  (* src = "ls180.v:301.5-301.20" *)
  reg _0948_;
  (* src = "ls180.v:387.5-387.33" *)
  reg _0949_;
  (* src = "ls180.v:386.11-386.41" *)
  reg [3:0] _0950_;
  (* src = "ls180.v:385.5-385.33" *)
  reg _0951_;
  (* src = "ls180.v:382.5-382.34" *)
  reg _0952_;
  (* src = "ls180.v:278.12-278.41" *)
  reg [15:0] _0953_;
  (* src = "ls180.v:279.5-279.39" *)
  reg _0954_;
  (* src = "ls180.v:314.12-314.32" *)
  reg [15:0] _0955_;
  (* src = "ls180.v:756.11-756.35" *)
  reg [1:0] _0956_;
  (* src = "ls180.v:300.11-300.31" *)
  reg [3:0] _0957_;
  (* src = "ls180.v:765.5-765.31" *)
  reg _0958_;
  (* src = "ls180.v:764.32-764.58" *)
  reg _0959_;
  (* src = "ls180.v:773.11-773.29" *)
  reg [4:0] _0960_;
  (* src = "ls180.v:776.11-776.29" *)
  reg [3:0] _0961_;
  (* src = "ls180.v:378.11-378.39" *)
  reg [9:0] _0962_;
  (* src = "ls180.v:768.11-768.37" *)
  reg [2:0] _0963_;
  (* src = "ls180.v:767.32-767.58" *)
  reg _0964_;
  (* src = "ls180.v:313.5-313.27" *)
  reg _0965_;
  (* src = "ls180.v:312.12-312.40" *)
  reg [15:0] _0966_;
  (* src = "ls180.v:1001.11-1001.54" *)
  reg [2:0] _0967_;
  (* src = "ls180.v:1000.11-1000.49" *)
  reg [2:0] _0968_;
  (* src = "ls180.v:1003.11-1003.54" *)
  reg [2:0] _0969_;
  (* src = "ls180.v:1002.11-1002.49" *)
  reg [2:0] _0970_;
  (* src = "ls180.v:1005.11-1005.54" *)
  reg [2:0] _0971_;
  (* src = "ls180.v:1004.11-1004.49" *)
  reg [2:0] _0972_;
  (* src = "ls180.v:1007.11-1007.54" *)
  reg [2:0] _0973_;
  (* src = "ls180.v:1006.11-1006.49" *)
  reg [2:0] _0974_;
  (* src = "ls180.v:991.5-991.46" *)
  reg _0975_;
  (* src = "ls180.v:990.5-990.41" *)
  reg _0976_;
  (* src = "ls180.v:995.5-995.46" *)
  reg _0977_;
  (* src = "ls180.v:994.5-994.41" *)
  reg _0978_;
  (* src = "ls180.v:1009.11-1009.53" *)
  reg [2:0] _0979_;
  (* src = "ls180.v:1008.11-1008.48" *)
  reg [2:0] _0980_;
  (* src = "ls180.v:1027.5-1027.48" *)
  reg _0981_;
  (* src = "ls180.v:1028.5-1028.48" *)
  reg _0982_;
  (* src = "ls180.v:1029.5-1029.48" *)
  reg _0983_;
  (* src = "ls180.v:1030.5-1030.48" *)
  reg _0984_;
  (* src = "ls180.v:1026.5-1026.47" *)
  reg _0985_;
  (* src = "ls180.v:1032.5-1032.35" *)
  reg _0986_;
  (* src = "ls180.v:999.11-999.51" *)
  reg [1:0] _0987_;
  (* src = "ls180.v:998.11-998.46" *)
  reg [1:0] _0988_;
  (* src = "ls180.v:1031.5-1031.30" *)
  reg _0989_;
  (* src = "ls180.v:1327.5-1327.26" *)
  reg _0990_;
  (* src = "ls180.v:1328.5-1328.26" *)
  reg _0991_;
  (* src = "ls180.v:1329.5-1329.26" *)
  reg _0992_;
  (* src = "ls180.v:1336.5-1336.26" *)
  reg _0993_;
  (* src = "ls180.v:1337.5-1337.26" *)
  reg _0994_;
  (* src = "ls180.v:1338.5-1338.26" *)
  reg _0995_;
  (* src = "ls180.v:855.5-855.20" *)
  reg _0996_;
  (* src = "ls180.v:907.11-907.33" *)
  reg [3:0] _0997_;
  (* src = "ls180.v:904.11-904.32" *)
  reg [4:0] _0998_;
  (* src = "ls180.v:906.11-906.33" *)
  reg [3:0] _0999_;
  (* src = "ls180.v:897.5-897.28" *)
  reg _1000_;
  (* src = "ls180.v:908.11-908.36" *)
  reg [3:0] _1001_;
  (* src = "ls180.v:856.5-856.26" *)
  reg _1002_;
  (* src = "ls180.v:853.5-853.22" *)
  reg _1003_;
  (* src = "ls180.v:837.12-837.49" *)
  reg [31:0] _1004_;
  (* src = "ls180.v:827.12-827.49" *)
  reg [31:0] _1005_;
  (* src = "ls180.v:820.5-820.23" *)
  reg _1006_;
  (* src = "ls180.v:841.11-841.38" *)
  reg [3:0] _1007_;
  (* src = "ls180.v:842.5-842.28" *)
  reg _1008_;
  (* src = "ls180.v:839.5-839.25" *)
  reg _1009_;
  (* src = "ls180.v:840.11-840.33" *)
  reg [7:0] _1010_;
  (* src = "ls180.v:822.5-822.31" *)
  reg _1011_;
  (* src = "ls180.v:835.11-835.46" *)
  reg [7:0] _1012_;
  (* src = "ls180.v:831.5-831.33" *)
  reg _1013_;
  (* src = "ls180.v:819.12-819.42" *)
  reg [31:0] _1014_;
  (* src = "ls180.v:829.11-829.38" *)
  reg [3:0] _1015_;
  (* src = "ls180.v:830.5-830.28" *)
  reg _1016_;
  (* src = "ls180.v:828.11-828.33" *)
  reg [7:0] _1017_;
  (* src = "ls180.v:836.5-836.34" *)
  reg _1018_;
  (* src = "ls180.v:826.5-826.34" *)
  reg _1019_;
  (* src = "ls180.v:797.5-797.24" *)
  reg _1020_;
  (* src = "ls180.v:815.5-815.26" *)
  reg _1021_;
  (* src = "ls180.v:1551.76-1551.113" *)
  wire _1022_;
  (* src = "ls180.v:1611.76-1611.113" *)
  wire _1023_;
  (* src = "ls180.v:2754.52-2754.76" *)
  wire _1024_;
  (* src = "ls180.v:2854.26-2854.59" *)
  wire [4:0] _1025_;
  (* src = "ls180.v:2884.26-2884.59" *)
  wire [4:0] _1026_;
  (* src = "ls180.v:4310.31-4310.60" *)
  wire [31:0] _1027_;
  (* src = "ls180.v:4399.32-4399.62" *)
  wire [3:0] _1028_;
  (* src = "ls180.v:4416.55-4416.109" *)
  wire [2:0] _1029_;
  (* src = "ls180.v:4419.55-4419.109" *)
  wire [2:0] _1030_;
  (* src = "ls180.v:4423.54-4423.106" *)
  wire [3:0] _1031_;
  (* src = "ls180.v:4462.55-4462.109" *)
  wire [2:0] _1032_;
  (* src = "ls180.v:4465.55-4465.109" *)
  wire [2:0] _1033_;
  (* src = "ls180.v:4469.54-4469.106" *)
  wire [3:0] _1034_;
  (* src = "ls180.v:4508.55-4508.109" *)
  wire [2:0] _1035_;
  (* src = "ls180.v:4511.55-4511.109" *)
  wire [2:0] _1036_;
  (* src = "ls180.v:4515.54-4515.106" *)
  wire [3:0] _1037_;
  (* src = "ls180.v:4554.55-4554.109" *)
  wire [2:0] _1038_;
  (* src = "ls180.v:4557.55-4557.109" *)
  wire [2:0] _1039_;
  (* src = "ls180.v:4561.54-4561.106" *)
  wire [3:0] _1040_;
  (* src = "ls180.v:4791.29-4791.56" *)
  wire [3:0] _1041_;
  (* src = "ls180.v:4807.63-4807.111" *)
  wire [32:0] _1042_;
  (* src = "ls180.v:4820.29-4820.56" *)
  wire [3:0] _1043_;
  (* src = "ls180.v:4839.63-4839.111" *)
  wire [32:0] _1044_;
  (* src = "ls180.v:4865.23-4865.45" *)
  wire [3:0] _1045_;
  (* src = "ls180.v:4868.23-4868.45" *)
  wire [3:0] _1046_;
  (* src = "ls180.v:4872.23-4872.44" *)
  wire [4:0] _1047_;
  (* src = "ls180.v:4887.23-4887.45" *)
  wire [3:0] _1048_;
  (* src = "ls180.v:4890.23-4890.45" *)
  wire [3:0] _1049_;
  (* src = "ls180.v:4894.23-4894.44" *)
  wire [4:0] _1050_;
  (* src = "ls180.v:1545.9-1545.70" *)
  wire _1051_;
  (* src = "ls180.v:1563.9-1563.70" *)
  wire _1052_;
  (* src = "ls180.v:1605.9-1605.70" *)
  wire _1053_;
  (* src = "ls180.v:1623.9-1623.70" *)
  wire _1054_;
  (* src = "ls180.v:1633.26-1633.75" *)
  wire _1055_;
  (* src = "ls180.v:1633.25-1633.101" *)
  wire _1056_;
  (* src = "ls180.v:1633.24-1633.131" *)
  wire _1057_;
  (* src = "ls180.v:1634.26-1634.75" *)
  wire _1058_;
  (* src = "ls180.v:1634.25-1634.101" *)
  wire _1059_;
  (* src = "ls180.v:1634.24-1634.131" *)
  wire _1060_;
  (* src = "ls180.v:1635.26-1635.75" *)
  wire _1061_;
  (* src = "ls180.v:1635.25-1635.101" *)
  wire _1062_;
  (* src = "ls180.v:1635.24-1635.131" *)
  wire _1063_;
  (* src = "ls180.v:1636.26-1636.75" *)
  wire _1064_;
  (* src = "ls180.v:1636.25-1636.101" *)
  wire _1065_;
  (* src = "ls180.v:1636.24-1636.131" *)
  wire _1066_;
  (* src = "ls180.v:1645.7-1645.79" *)
  wire _1067_;
  (* src = "ls180.v:1650.27-1650.96" *)
  wire _1068_;
  (* src = "ls180.v:1654.18-1654.59" *)
  wire _1069_;
  (* src = "ls180.v:1654.17-1654.81" *)
  wire _1070_;
  (* src = "ls180.v:1654.16-1654.107" *)
  wire _1071_;
  (* src = "ls180.v:1655.18-1655.59" *)
  wire _1072_;
  (* src = "ls180.v:1655.17-1655.81" *)
  wire _1073_;
  (* src = "ls180.v:1655.16-1655.107" *)
  wire _1074_;
  (* src = "ls180.v:1656.18-1656.59" *)
  wire _1075_;
  (* src = "ls180.v:1656.17-1656.81" *)
  wire _1076_;
  (* src = "ls180.v:1656.16-1656.107" *)
  wire _1077_;
  (* src = "ls180.v:1657.18-1657.59" *)
  wire _1078_;
  (* src = "ls180.v:1657.17-1657.81" *)
  wire _1079_;
  (* src = "ls180.v:1657.16-1657.107" *)
  wire _1080_;
  (* src = "ls180.v:1774.35-1774.84" *)
  wire _1081_;
  (* src = "ls180.v:1775.35-1775.84" *)
  wire _1082_;
  (* src = "ls180.v:1813.33-1813.88" *)
  wire _1083_;
  (* src = "ls180.v:1867.45-1867.104" *)
  wire _1084_;
  (* src = "ls180.v:1867.44-1867.147" *)
  wire _1085_;
  (* src = "ls180.v:1868.44-1868.103" *)
  wire _1086_;
  (* src = "ls180.v:1868.43-1868.134" *)
  wire _1087_;
  (* src = "ls180.v:1869.45-1869.104" *)
  wire _1088_;
  (* src = "ls180.v:1869.44-1869.135" *)
  wire _1089_;
  (* src = "ls180.v:1872.7-1872.104" *)
  wire _1090_;
  (* src = "ls180.v:1901.61-1901.226" *)
  wire _1091_;
  (* src = "ls180.v:1902.59-1902.172" *)
  wire _1092_;
  (* src = "ls180.v:1926.9-1926.76" *)
  wire _1093_;
  (* src = "ls180.v:1938.9-1938.76" *)
  wire _1094_;
  (* src = "ls180.v:1988.13-1988.77" *)
  wire _1095_;
  (* src = "ls180.v:2024.45-2024.104" *)
  wire _1096_;
  (* src = "ls180.v:2024.44-2024.147" *)
  wire _1097_;
  (* src = "ls180.v:2025.44-2025.103" *)
  wire _1098_;
  (* src = "ls180.v:2025.43-2025.134" *)
  wire _1099_;
  (* src = "ls180.v:2026.45-2026.104" *)
  wire _1100_;
  (* src = "ls180.v:2026.44-2026.135" *)
  wire _1101_;
  (* src = "ls180.v:2029.7-2029.104" *)
  wire _1102_;
  (* src = "ls180.v:2058.61-2058.226" *)
  wire _1103_;
  (* src = "ls180.v:2059.59-2059.172" *)
  wire _1104_;
  (* src = "ls180.v:2083.9-2083.76" *)
  wire _1105_;
  (* src = "ls180.v:2095.9-2095.76" *)
  wire _1106_;
  (* src = "ls180.v:2145.13-2145.77" *)
  wire _1107_;
  (* src = "ls180.v:2181.45-2181.104" *)
  wire _1108_;
  (* src = "ls180.v:2181.44-2181.147" *)
  wire _1109_;
  (* src = "ls180.v:2182.44-2182.103" *)
  wire _1110_;
  (* src = "ls180.v:2182.43-2182.134" *)
  wire _1111_;
  (* src = "ls180.v:2183.45-2183.104" *)
  wire _1112_;
  (* src = "ls180.v:2183.44-2183.135" *)
  wire _1113_;
  (* src = "ls180.v:2186.7-2186.104" *)
  wire _1114_;
  (* src = "ls180.v:2215.61-2215.226" *)
  wire _1115_;
  (* src = "ls180.v:2216.59-2216.172" *)
  wire _1116_;
  (* src = "ls180.v:2240.9-2240.76" *)
  wire _1117_;
  (* src = "ls180.v:2252.9-2252.76" *)
  wire _1118_;
  (* src = "ls180.v:2302.13-2302.77" *)
  wire _1119_;
  (* src = "ls180.v:2338.45-2338.104" *)
  wire _1120_;
  (* src = "ls180.v:2338.44-2338.147" *)
  wire _1121_;
  (* src = "ls180.v:2339.44-2339.103" *)
  wire _1122_;
  (* src = "ls180.v:2339.43-2339.134" *)
  wire _1123_;
  (* src = "ls180.v:2340.45-2340.104" *)
  wire _1124_;
  (* src = "ls180.v:2340.44-2340.135" *)
  wire _1125_;
  (* src = "ls180.v:2343.7-2343.104" *)
  wire _1126_;
  (* src = "ls180.v:2372.61-2372.226" *)
  wire _1127_;
  (* src = "ls180.v:2373.59-2373.172" *)
  wire _1128_;
  (* src = "ls180.v:2397.9-2397.76" *)
  wire _1129_;
  (* src = "ls180.v:2409.9-2409.76" *)
  wire _1130_;
  (* src = "ls180.v:2459.13-2459.77" *)
  wire _1131_;
  (* src = "ls180.v:2474.32-2474.87" *)
  wire _1132_;
  (* src = "ls180.v:2474.93-2474.163" *)
  wire _1133_;
  (* src = "ls180.v:2474.92-2474.201" *)
  wire _1134_;
  (* src = "ls180.v:2474.31-2474.202" *)
  wire _1135_;
  (* src = "ls180.v:2475.32-2475.87" *)
  wire _1136_;
  (* src = "ls180.v:2475.93-2475.163" *)
  wire _1137_;
  (* src = "ls180.v:2475.92-2475.201" *)
  wire _1138_;
  (* src = "ls180.v:2475.31-2475.202" *)
  wire _1139_;
  (* src = "ls180.v:2476.29-2476.70" *)
  wire _1140_;
  (* src = "ls180.v:2477.32-2477.87" *)
  wire _1141_;
  (* src = "ls180.v:2477.31-2477.169" *)
  wire _1142_;
  (* src = "ls180.v:2479.32-2479.87" *)
  wire _1143_;
  (* src = "ls180.v:2479.31-2479.128" *)
  wire _1144_;
  (* src = "ls180.v:2480.35-2480.104" *)
  wire _1145_;
  (* src = "ls180.v:2480.109-2480.178" *)
  wire _1146_;
  (* src = "ls180.v:2480.184-2480.253" *)
  wire _1147_;
  (* src = "ls180.v:2480.259-2480.328" *)
  wire _1148_;
  (* src = "ls180.v:2481.36-2481.106" *)
  wire _1149_;
  (* src = "ls180.v:2481.111-2481.181" *)
  wire _1150_;
  (* src = "ls180.v:2481.187-2481.257" *)
  wire _1151_;
  (* src = "ls180.v:2481.263-2481.333" *)
  wire _1152_;
  (* src = "ls180.v:2488.33-2488.96" *)
  wire _1153_;
  (* src = "ls180.v:2488.32-2488.130" *)
  wire _1154_;
  (* src = "ls180.v:2488.31-2488.164" *)
  wire _1155_;
  (* src = "ls180.v:2494.67-2494.133" *)
  wire _1156_;
  (* src = "ls180.v:2494.142-2494.216" *)
  wire _1157_;
  (* src = "ls180.v:2494.141-2494.256" *)
  wire _1158_;
  (* src = "ls180.v:2494.66-2494.293" *)
  wire _1159_;
  (* src = "ls180.v:2494.298-2494.445" *)
  wire _1160_;
  (* src = "ls180.v:2494.33-2494.447" *)
  wire _1161_;
  (* src = "ls180.v:2495.67-2495.133" *)
  wire _1162_;
  (* src = "ls180.v:2495.142-2495.216" *)
  wire _1163_;
  (* src = "ls180.v:2495.141-2495.256" *)
  wire _1164_;
  (* src = "ls180.v:2495.66-2495.293" *)
  wire _1165_;
  (* src = "ls180.v:2495.298-2495.445" *)
  wire _1166_;
  (* src = "ls180.v:2495.33-2495.447" *)
  wire _1167_;
  (* src = "ls180.v:2496.67-2496.133" *)
  wire _1168_;
  (* src = "ls180.v:2496.142-2496.216" *)
  wire _1169_;
  (* src = "ls180.v:2496.141-2496.256" *)
  wire _1170_;
  (* src = "ls180.v:2496.66-2496.293" *)
  wire _1171_;
  (* src = "ls180.v:2496.298-2496.445" *)
  wire _1172_;
  (* src = "ls180.v:2496.33-2496.447" *)
  wire _1173_;
  (* src = "ls180.v:2497.67-2497.133" *)
  wire _1174_;
  (* src = "ls180.v:2497.142-2497.216" *)
  wire _1175_;
  (* src = "ls180.v:2497.141-2497.256" *)
  wire _1176_;
  (* src = "ls180.v:2497.66-2497.293" *)
  wire _1177_;
  (* src = "ls180.v:2497.298-2497.445" *)
  wire _1178_;
  (* src = "ls180.v:2497.33-2497.447" *)
  wire _1179_;
  (* src = "ls180.v:2527.67-2527.133" *)
  wire _1180_;
  (* src = "ls180.v:2527.142-2527.216" *)
  wire _1181_;
  (* src = "ls180.v:2527.141-2527.256" *)
  wire _1182_;
  (* src = "ls180.v:2527.66-2527.293" *)
  wire _1183_;
  (* src = "ls180.v:2527.298-2527.445" *)
  wire _1184_;
  (* src = "ls180.v:2527.33-2527.447" *)
  wire _1185_;
  (* src = "ls180.v:2528.67-2528.133" *)
  wire _1186_;
  (* src = "ls180.v:2528.142-2528.216" *)
  wire _1187_;
  (* src = "ls180.v:2528.141-2528.256" *)
  wire _1188_;
  (* src = "ls180.v:2528.66-2528.293" *)
  wire _1189_;
  (* src = "ls180.v:2528.298-2528.445" *)
  wire _1190_;
  (* src = "ls180.v:2528.33-2528.447" *)
  wire _1191_;
  (* src = "ls180.v:2529.67-2529.133" *)
  wire _1192_;
  (* src = "ls180.v:2529.142-2529.216" *)
  wire _1193_;
  (* src = "ls180.v:2529.141-2529.256" *)
  wire _1194_;
  (* src = "ls180.v:2529.66-2529.293" *)
  wire _1195_;
  (* src = "ls180.v:2529.298-2529.445" *)
  wire _1196_;
  (* src = "ls180.v:2529.33-2529.447" *)
  wire _1197_;
  (* src = "ls180.v:2530.67-2530.133" *)
  wire _1198_;
  (* src = "ls180.v:2530.142-2530.216" *)
  wire _1199_;
  (* src = "ls180.v:2530.141-2530.256" *)
  wire _1200_;
  (* src = "ls180.v:2530.66-2530.293" *)
  wire _1201_;
  (* src = "ls180.v:2530.298-2530.445" *)
  wire _1202_;
  (* src = "ls180.v:2530.33-2530.447" *)
  wire _1203_;
  (* src = "ls180.v:2559.8-2559.63" *)
  wire _1204_;
  (* src = "ls180.v:2559.7-2559.99" *)
  wire _1205_;
  (* src = "ls180.v:2562.8-2562.63" *)
  wire _1206_;
  (* src = "ls180.v:2562.7-2562.99" *)
  wire _1207_;
  (* src = "ls180.v:2568.8-2568.63" *)
  wire _1208_;
  (* src = "ls180.v:2568.7-2568.99" *)
  wire _1209_;
  (* src = "ls180.v:2571.8-2571.63" *)
  wire _1210_;
  (* src = "ls180.v:2571.7-2571.99" *)
  wire _1211_;
  (* src = "ls180.v:2577.8-2577.63" *)
  wire _1212_;
  (* src = "ls180.v:2577.7-2577.99" *)
  wire _1213_;
  (* src = "ls180.v:2580.8-2580.63" *)
  wire _1214_;
  (* src = "ls180.v:2580.7-2580.99" *)
  wire _1215_;
  (* src = "ls180.v:2586.8-2586.63" *)
  wire _1216_;
  (* src = "ls180.v:2586.7-2586.99" *)
  wire _1217_;
  (* src = "ls180.v:2589.8-2589.63" *)
  wire _1218_;
  (* src = "ls180.v:2589.7-2589.99" *)
  wire _1219_;
  (* src = "ls180.v:2614.61-2614.131" *)
  wire _1220_;
  (* src = "ls180.v:2614.60-2614.169" *)
  wire _1221_;
  (* src = "ls180.v:2614.36-2614.192" *)
  wire _1222_;
  (* src = "ls180.v:2652.61-2652.131" *)
  wire _1223_;
  (* src = "ls180.v:2652.60-2652.169" *)
  wire _1224_;
  (* src = "ls180.v:2652.36-2652.192" *)
  wire _1225_;
  (* src = "ls180.v:2670.115-2670.184" *)
  wire _1226_;
  (* src = "ls180.v:2670.190-2670.259" *)
  wire _1227_;
  (* src = "ls180.v:2670.265-2670.334" *)
  wire _1228_;
  (* src = "ls180.v:2670.46-2670.337" *)
  wire _1229_;
  (* src = "ls180.v:2670.45-2670.355" *)
  wire _1230_;
  (* src = "ls180.v:2671.39-2671.101" *)
  wire _1231_;
  (* src = "ls180.v:2675.115-2675.184" *)
  wire _1232_;
  (* src = "ls180.v:2675.190-2675.259" *)
  wire _1233_;
  (* src = "ls180.v:2675.265-2675.334" *)
  wire _1234_;
  (* src = "ls180.v:2675.46-2675.337" *)
  wire _1235_;
  (* src = "ls180.v:2675.45-2675.355" *)
  wire _1236_;
  (* src = "ls180.v:2676.39-2676.101" *)
  wire _1237_;
  (* src = "ls180.v:2680.115-2680.184" *)
  wire _1238_;
  (* src = "ls180.v:2680.190-2680.259" *)
  wire _1239_;
  (* src = "ls180.v:2680.265-2680.334" *)
  wire _1240_;
  (* src = "ls180.v:2680.46-2680.337" *)
  wire _1241_;
  (* src = "ls180.v:2680.45-2680.355" *)
  wire _1242_;
  (* src = "ls180.v:2681.39-2681.101" *)
  wire _1243_;
  (* src = "ls180.v:2685.115-2685.184" *)
  wire _1244_;
  (* src = "ls180.v:2685.190-2685.259" *)
  wire _1245_;
  (* src = "ls180.v:2685.265-2685.334" *)
  wire _1246_;
  (* src = "ls180.v:2685.46-2685.337" *)
  wire _1247_;
  (* src = "ls180.v:2685.45-2685.355" *)
  wire _1248_;
  (* src = "ls180.v:2686.39-2686.101" *)
  wire _1249_;
  (* src = "ls180.v:2690.151-2690.220" *)
  wire _1250_;
  (* src = "ls180.v:2690.226-2690.295" *)
  wire _1251_;
  (* src = "ls180.v:2690.301-2690.370" *)
  wire _1252_;
  (* src = "ls180.v:2690.82-2690.373" *)
  wire _1253_;
  (* src = "ls180.v:2690.38-2690.374" *)
  wire _1254_;
  (* src = "ls180.v:2690.37-2690.405" *)
  wire _1255_;
  (* src = "ls180.v:2690.525-2690.594" *)
  wire _1256_;
  (* src = "ls180.v:2690.600-2690.669" *)
  wire _1257_;
  (* src = "ls180.v:2690.675-2690.744" *)
  wire _1258_;
  (* src = "ls180.v:2690.456-2690.747" *)
  wire _1259_;
  (* src = "ls180.v:2690.412-2690.748" *)
  wire _1260_;
  (* src = "ls180.v:2690.411-2690.779" *)
  wire _1261_;
  (* src = "ls180.v:2690.899-2690.968" *)
  wire _1262_;
  (* src = "ls180.v:2690.974-2690.1043" *)
  wire _1263_;
  (* src = "ls180.v:2690.1049-2690.1118" *)
  wire _1264_;
  (* src = "ls180.v:2690.830-2690.1121" *)
  wire _1265_;
  (* src = "ls180.v:2690.786-2690.1122" *)
  wire _1266_;
  (* src = "ls180.v:2690.785-2690.1153" *)
  wire _1267_;
  (* src = "ls180.v:2690.1273-2690.1342" *)
  wire _1268_;
  (* src = "ls180.v:2690.1348-2690.1417" *)
  wire _1269_;
  (* src = "ls180.v:2690.1423-2690.1492" *)
  wire _1270_;
  (* src = "ls180.v:2690.1204-2690.1495" *)
  wire _1271_;
  (* src = "ls180.v:2690.1160-2690.1496" *)
  wire _1272_;
  (* src = "ls180.v:2690.1159-2690.1527" *)
  wire _1273_;
  (* src = "ls180.v:2748.9-2748.36" *)
  wire _1274_;
  (* src = "ls180.v:2766.9-2766.36" *)
  wire _1275_;
  (* src = "ls180.v:2779.27-2779.60" *)
  wire _1276_;
  (* src = "ls180.v:2779.26-2779.79" *)
  wire _1277_;
  (* src = "ls180.v:2780.29-2780.82" *)
  wire _1278_;
  (* src = "ls180.v:2780.28-2780.103" *)
  wire _1279_;
  (* src = "ls180.v:2781.28-2781.84" *)
  wire _1280_;
  (* src = "ls180.v:2782.39-2782.65" *)
  wire _1281_;
  (* src = "ls180.v:2782.70-2782.99" *)
  wire _1282_;
  (* src = "ls180.v:2782.27-2782.101" *)
  wire _1283_;
  (* src = "ls180.v:2783.20-2783.51" *)
  wire _1284_;
  (* src = "ls180.v:2784.22-2784.57" *)
  wire _1285_;
  (* src = "ls180.v:2785.21-2785.56" *)
  wire _1286_;
  (* src = "ls180.v:2814.44-2814.58" *)
  wire _1287_;
  (* src = "ls180.v:2818.7-2818.58" *)
  wire _1288_;
  (* src = "ls180.v:2829.7-2829.58" *)
  wire _1289_;
  (* src = "ls180.v:2838.16-2838.67" *)
  wire _1290_;
  (* src = "ls180.v:2838.72-2838.123" *)
  wire _1291_;
  (* src = "ls180.v:2853.31-2853.93" *)
  wire _1292_;
  (* src = "ls180.v:2864.29-2864.96" *)
  wire _1293_;
  (* src = "ls180.v:2865.27-2865.74" *)
  wire _1294_;
  (* src = "ls180.v:2883.31-2883.93" *)
  wire _1295_;
  (* src = "ls180.v:2894.29-2894.96" *)
  wire _1296_;
  (* src = "ls180.v:2895.27-2895.74" *)
  wire _1297_;
  (* src = "ls180.v:2992.9-2992.84" *)
  wire _1298_;
  (* src = "ls180.v:2995.60-2995.144" *)
  wire _1299_;
  (* src = "ls180.v:3013.58-3013.110" *)
  wire _1300_;
  (* src = "ls180.v:3014.58-3014.110" *)
  wire _1301_;
  (* src = "ls180.v:3015.44-3015.96" *)
  wire _1302_;
  (* src = "ls180.v:3016.58-3016.110" *)
  wire _1303_;
  (* src = "ls180.v:3017.58-3017.110" *)
  wire _1304_;
  (* src = "ls180.v:3018.44-3018.96" *)
  wire _1305_;
  (* src = "ls180.v:3071.35-3071.84" *)
  wire _1306_;
  (* src = "ls180.v:3072.31-3072.80" *)
  wire _1307_;
  (* src = "ls180.v:3073.45-3073.94" *)
  wire _1308_;
  (* src = "ls180.v:3074.45-3074.94" *)
  wire _1309_;
  (* src = "ls180.v:3075.24-3075.73" *)
  wire _1310_;
  (* src = "ls180.v:3076.48-3076.97" *)
  wire _1311_;
  (* src = "ls180.v:3078.29-3078.76" *)
  wire _1312_;
  (* src = "ls180.v:3078.28-3078.105" *)
  wire _1313_;
  (* src = "ls180.v:3084.36-3084.96" *)
  wire [31:0] _1314_;
  (* src = "ls180.v:3084.101-3084.157" *)
  wire [31:0] _1315_;
  (* src = "ls180.v:3084.163-3084.233" *)
  wire [31:0] _1316_;
  (* src = "ls180.v:3084.239-3084.309" *)
  wire [31:0] _1317_;
  (* src = "ls180.v:3084.315-3084.364" *)
  wire [31:0] _1318_;
  (* src = "ls180.v:3084.370-3084.443" *)
  wire [31:0] _1319_;
  (* src = "ls180.v:3094.43-3094.104" *)
  wire _1320_;
  (* src = "ls180.v:3094.42-3094.158" *)
  wire _1321_;
  (* src = "ls180.v:3095.43-3095.107" *)
  wire _1322_;
  (* src = "ls180.v:3095.42-3095.161" *)
  wire _1323_;
  (* src = "ls180.v:3097.45-3097.106" *)
  wire _1324_;
  (* src = "ls180.v:3097.44-3097.160" *)
  wire _1325_;
  (* src = "ls180.v:3098.45-3098.109" *)
  wire _1326_;
  (* src = "ls180.v:3098.44-3098.163" *)
  wire _1327_;
  (* src = "ls180.v:3100.45-3100.106" *)
  wire _1328_;
  (* src = "ls180.v:3100.44-3100.160" *)
  wire _1329_;
  (* src = "ls180.v:3101.45-3101.109" *)
  wire _1330_;
  (* src = "ls180.v:3101.44-3101.163" *)
  wire _1331_;
  (* src = "ls180.v:3103.45-3103.106" *)
  wire _1332_;
  (* src = "ls180.v:3103.44-3103.160" *)
  wire _1333_;
  (* src = "ls180.v:3104.45-3104.109" *)
  wire _1334_;
  (* src = "ls180.v:3104.44-3104.163" *)
  wire _1335_;
  (* src = "ls180.v:3106.45-3106.106" *)
  wire _1336_;
  (* src = "ls180.v:3106.44-3106.160" *)
  wire _1337_;
  (* src = "ls180.v:3107.45-3107.109" *)
  wire _1338_;
  (* src = "ls180.v:3107.44-3107.163" *)
  wire _1339_;
  (* src = "ls180.v:3109.48-3109.109" *)
  wire _1340_;
  (* src = "ls180.v:3109.47-3109.163" *)
  wire _1341_;
  (* src = "ls180.v:3110.48-3110.112" *)
  wire _1342_;
  (* src = "ls180.v:3110.47-3110.166" *)
  wire _1343_;
  (* src = "ls180.v:3112.48-3112.109" *)
  wire _1344_;
  (* src = "ls180.v:3112.47-3112.163" *)
  wire _1345_;
  (* src = "ls180.v:3113.48-3113.112" *)
  wire _1346_;
  (* src = "ls180.v:3113.47-3113.166" *)
  wire _1347_;
  (* src = "ls180.v:3115.48-3115.109" *)
  wire _1348_;
  (* src = "ls180.v:3115.47-3115.163" *)
  wire _1349_;
  (* src = "ls180.v:3116.48-3116.112" *)
  wire _1350_;
  (* src = "ls180.v:3116.47-3116.166" *)
  wire _1351_;
  (* src = "ls180.v:3118.48-3118.109" *)
  wire _1352_;
  (* src = "ls180.v:3118.47-3118.163" *)
  wire _1353_;
  (* src = "ls180.v:3119.48-3119.112" *)
  wire _1354_;
  (* src = "ls180.v:3119.47-3119.166" *)
  wire _1355_;
  (* src = "ls180.v:3132.40-3132.101" *)
  wire _1356_;
  (* src = "ls180.v:3132.39-3132.155" *)
  wire _1357_;
  (* src = "ls180.v:3133.40-3133.104" *)
  wire _1358_;
  (* src = "ls180.v:3133.39-3133.158" *)
  wire _1359_;
  (* src = "ls180.v:3135.39-3135.100" *)
  wire _1360_;
  (* src = "ls180.v:3135.38-3135.154" *)
  wire _1361_;
  (* src = "ls180.v:3136.39-3136.103" *)
  wire _1362_;
  (* src = "ls180.v:3136.38-3136.157" *)
  wire _1363_;
  (* src = "ls180.v:3138.41-3138.102" *)
  wire _1364_;
  (* src = "ls180.v:3138.40-3138.156" *)
  wire _1365_;
  (* src = "ls180.v:3139.41-3139.105" *)
  wire _1366_;
  (* src = "ls180.v:3139.40-3139.159" *)
  wire _1367_;
  (* src = "ls180.v:3146.40-3146.101" *)
  wire _1368_;
  (* src = "ls180.v:3146.39-3146.155" *)
  wire _1369_;
  (* src = "ls180.v:3147.40-3147.104" *)
  wire _1370_;
  (* src = "ls180.v:3147.39-3147.158" *)
  wire _1371_;
  (* src = "ls180.v:3149.39-3149.100" *)
  wire _1372_;
  (* src = "ls180.v:3149.38-3149.154" *)
  wire _1373_;
  (* src = "ls180.v:3150.39-3150.103" *)
  wire _1374_;
  (* src = "ls180.v:3150.38-3150.157" *)
  wire _1375_;
  (* src = "ls180.v:3152.41-3152.102" *)
  wire _1376_;
  (* src = "ls180.v:3152.40-3152.156" *)
  wire _1377_;
  (* src = "ls180.v:3153.41-3153.105" *)
  wire _1378_;
  (* src = "ls180.v:3153.40-3153.159" *)
  wire _1379_;
  (* src = "ls180.v:3160.39-3160.100" *)
  wire _1380_;
  (* src = "ls180.v:3160.38-3160.152" *)
  wire _1381_;
  (* src = "ls180.v:3161.39-3161.103" *)
  wire _1382_;
  (* src = "ls180.v:3161.38-3161.155" *)
  wire _1383_;
  (* src = "ls180.v:3163.38-3163.99" *)
  wire _1384_;
  (* src = "ls180.v:3163.37-3163.151" *)
  wire _1385_;
  (* src = "ls180.v:3164.38-3164.102" *)
  wire _1386_;
  (* src = "ls180.v:3164.37-3164.154" *)
  wire _1387_;
  (* src = "ls180.v:3174.50-3174.111" *)
  wire _1388_;
  (* src = "ls180.v:3174.49-3174.165" *)
  wire _1389_;
  (* src = "ls180.v:3175.50-3175.114" *)
  wire _1390_;
  (* src = "ls180.v:3175.49-3175.168" *)
  wire _1391_;
  (* src = "ls180.v:3177.54-3177.115" *)
  wire _1392_;
  (* src = "ls180.v:3177.53-3177.169" *)
  wire _1393_;
  (* src = "ls180.v:3178.54-3178.118" *)
  wire _1394_;
  (* src = "ls180.v:3178.53-3178.172" *)
  wire _1395_;
  (* src = "ls180.v:3180.35-3180.96" *)
  wire _1396_;
  (* src = "ls180.v:3180.34-3180.150" *)
  wire _1397_;
  (* src = "ls180.v:3181.35-3181.99" *)
  wire _1398_;
  (* src = "ls180.v:3181.34-3181.153" *)
  wire _1399_;
  (* src = "ls180.v:3183.54-3183.115" *)
  wire _1400_;
  (* src = "ls180.v:3183.53-3183.169" *)
  wire _1401_;
  (* src = "ls180.v:3184.54-3184.118" *)
  wire _1402_;
  (* src = "ls180.v:3184.53-3184.172" *)
  wire _1403_;
  (* src = "ls180.v:3186.54-3186.115" *)
  wire _1404_;
  (* src = "ls180.v:3186.53-3186.169" *)
  wire _1405_;
  (* src = "ls180.v:3187.54-3187.118" *)
  wire _1406_;
  (* src = "ls180.v:3187.53-3187.172" *)
  wire _1407_;
  (* src = "ls180.v:3189.55-3189.116" *)
  wire _1408_;
  (* src = "ls180.v:3189.54-3189.170" *)
  wire _1409_;
  (* src = "ls180.v:3190.55-3190.119" *)
  wire _1410_;
  (* src = "ls180.v:3190.54-3190.173" *)
  wire _1411_;
  (* src = "ls180.v:3192.53-3192.114" *)
  wire _1412_;
  (* src = "ls180.v:3192.52-3192.168" *)
  wire _1413_;
  (* src = "ls180.v:3193.53-3193.117" *)
  wire _1414_;
  (* src = "ls180.v:3193.52-3193.171" *)
  wire _1415_;
  (* src = "ls180.v:3195.53-3195.114" *)
  wire _1416_;
  (* src = "ls180.v:3195.52-3195.168" *)
  wire _1417_;
  (* src = "ls180.v:3196.53-3196.117" *)
  wire _1418_;
  (* src = "ls180.v:3196.52-3196.171" *)
  wire _1419_;
  (* src = "ls180.v:3198.53-3198.114" *)
  wire _1420_;
  (* src = "ls180.v:3198.52-3198.168" *)
  wire _1421_;
  (* src = "ls180.v:3199.53-3199.117" *)
  wire _1422_;
  (* src = "ls180.v:3199.52-3199.171" *)
  wire _1423_;
  (* src = "ls180.v:3201.53-3201.114" *)
  wire _1424_;
  (* src = "ls180.v:3201.52-3201.168" *)
  wire _1425_;
  (* src = "ls180.v:3202.53-3202.117" *)
  wire _1426_;
  (* src = "ls180.v:3202.52-3202.171" *)
  wire _1427_;
  (* src = "ls180.v:3219.42-3219.103" *)
  wire _1428_;
  (* src = "ls180.v:3219.41-3219.157" *)
  wire _1429_;
  (* src = "ls180.v:3220.42-3220.106" *)
  wire _1430_;
  (* src = "ls180.v:3220.41-3220.160" *)
  wire _1431_;
  (* src = "ls180.v:3222.42-3222.103" *)
  wire _1432_;
  (* src = "ls180.v:3222.41-3222.157" *)
  wire _1433_;
  (* src = "ls180.v:3223.42-3223.106" *)
  wire _1434_;
  (* src = "ls180.v:3223.41-3223.160" *)
  wire _1435_;
  (* src = "ls180.v:3225.42-3225.103" *)
  wire _1436_;
  (* src = "ls180.v:3225.41-3225.157" *)
  wire _1437_;
  (* src = "ls180.v:3226.42-3226.106" *)
  wire _1438_;
  (* src = "ls180.v:3226.41-3226.160" *)
  wire _1439_;
  (* src = "ls180.v:3228.42-3228.103" *)
  wire _1440_;
  (* src = "ls180.v:3228.41-3228.157" *)
  wire _1441_;
  (* src = "ls180.v:3229.42-3229.106" *)
  wire _1442_;
  (* src = "ls180.v:3229.41-3229.160" *)
  wire _1443_;
  (* src = "ls180.v:3231.44-3231.105" *)
  wire _1444_;
  (* src = "ls180.v:3231.43-3231.159" *)
  wire _1445_;
  (* src = "ls180.v:3232.44-3232.108" *)
  wire _1446_;
  (* src = "ls180.v:3232.43-3232.162" *)
  wire _1447_;
  (* src = "ls180.v:3234.44-3234.105" *)
  wire _1448_;
  (* src = "ls180.v:3234.43-3234.159" *)
  wire _1449_;
  (* src = "ls180.v:3235.44-3235.108" *)
  wire _1450_;
  (* src = "ls180.v:3235.43-3235.162" *)
  wire _1451_;
  (* src = "ls180.v:3237.44-3237.105" *)
  wire _1452_;
  (* src = "ls180.v:3237.43-3237.159" *)
  wire _1453_;
  (* src = "ls180.v:3238.44-3238.108" *)
  wire _1454_;
  (* src = "ls180.v:3238.43-3238.162" *)
  wire _1455_;
  (* src = "ls180.v:3240.44-3240.105" *)
  wire _1456_;
  (* src = "ls180.v:3240.43-3240.159" *)
  wire _1457_;
  (* src = "ls180.v:3241.44-3241.108" *)
  wire _1458_;
  (* src = "ls180.v:3241.43-3241.162" *)
  wire _1459_;
  (* src = "ls180.v:3243.40-3243.101" *)
  wire _1460_;
  (* src = "ls180.v:3243.39-3243.155" *)
  wire _1461_;
  (* src = "ls180.v:3244.40-3244.104" *)
  wire _1462_;
  (* src = "ls180.v:3244.39-3244.158" *)
  wire _1463_;
  (* src = "ls180.v:3246.50-3246.111" *)
  wire _1464_;
  (* src = "ls180.v:3246.49-3246.165" *)
  wire _1465_;
  (* src = "ls180.v:3247.50-3247.114" *)
  wire _1466_;
  (* src = "ls180.v:3247.49-3247.168" *)
  wire _1467_;
  (* src = "ls180.v:3249.43-3249.104" *)
  wire _1468_;
  (* src = "ls180.v:3249.42-3249.159" *)
  wire _1469_;
  (* src = "ls180.v:3250.43-3250.107" *)
  wire _1470_;
  (* src = "ls180.v:3250.42-3250.162" *)
  wire _1471_;
  (* src = "ls180.v:3252.43-3252.104" *)
  wire _1472_;
  (* src = "ls180.v:3252.42-3252.159" *)
  wire _1473_;
  (* src = "ls180.v:3253.43-3253.107" *)
  wire _1474_;
  (* src = "ls180.v:3253.42-3253.162" *)
  wire _1475_;
  (* src = "ls180.v:3255.43-3255.104" *)
  wire _1476_;
  (* src = "ls180.v:3255.42-3255.159" *)
  wire _1477_;
  (* src = "ls180.v:3256.43-3256.107" *)
  wire _1478_;
  (* src = "ls180.v:3256.42-3256.162" *)
  wire _1479_;
  (* src = "ls180.v:3258.43-3258.104" *)
  wire _1480_;
  (* src = "ls180.v:3258.42-3258.159" *)
  wire _1481_;
  (* src = "ls180.v:3259.43-3259.107" *)
  wire _1482_;
  (* src = "ls180.v:3259.42-3259.162" *)
  wire _1483_;
  (* src = "ls180.v:3261.47-3261.108" *)
  wire _1484_;
  (* src = "ls180.v:3261.46-3261.163" *)
  wire _1485_;
  (* src = "ls180.v:3262.47-3262.111" *)
  wire _1486_;
  (* src = "ls180.v:3262.46-3262.166" *)
  wire _1487_;
  (* src = "ls180.v:3264.48-3264.109" *)
  wire _1488_;
  (* src = "ls180.v:3264.47-3264.164" *)
  wire _1489_;
  (* src = "ls180.v:3265.48-3265.112" *)
  wire _1490_;
  (* src = "ls180.v:3265.47-3265.167" *)
  wire _1491_;
  (* src = "ls180.v:3267.47-3267.108" *)
  wire _1492_;
  (* src = "ls180.v:3267.46-3267.163" *)
  wire _1493_;
  (* src = "ls180.v:3268.47-3268.111" *)
  wire _1494_;
  (* src = "ls180.v:3268.46-3268.166" *)
  wire _1495_;
  (* src = "ls180.v:3287.20-3287.81" *)
  wire _1496_;
  (* src = "ls180.v:3287.19-3287.135" *)
  wire _1497_;
  (* src = "ls180.v:3288.20-3288.84" *)
  wire _1498_;
  (* src = "ls180.v:3288.19-3288.138" *)
  wire _1499_;
  (* src = "ls180.v:3290.43-3290.104" *)
  wire _1500_;
  (* src = "ls180.v:3290.42-3290.158" *)
  wire _1501_;
  (* src = "ls180.v:3291.43-3291.107" *)
  wire _1502_;
  (* src = "ls180.v:3291.42-3291.161" *)
  wire _1503_;
  (* src = "ls180.v:3293.44-3293.105" *)
  wire _1504_;
  (* src = "ls180.v:3293.43-3293.159" *)
  wire _1505_;
  (* src = "ls180.v:3294.44-3294.108" *)
  wire _1506_;
  (* src = "ls180.v:3294.43-3294.162" *)
  wire _1507_;
  (* src = "ls180.v:3296.35-3296.96" *)
  wire _1508_;
  (* src = "ls180.v:3296.34-3296.150" *)
  wire _1509_;
  (* src = "ls180.v:3297.35-3297.99" *)
  wire _1510_;
  (* src = "ls180.v:3297.34-3297.153" *)
  wire _1511_;
  (* src = "ls180.v:3299.36-3299.97" *)
  wire _1512_;
  (* src = "ls180.v:3299.35-3299.151" *)
  wire _1513_;
  (* src = "ls180.v:3300.36-3300.100" *)
  wire _1514_;
  (* src = "ls180.v:3300.35-3300.154" *)
  wire _1515_;
  (* src = "ls180.v:3302.47-3302.108" *)
  wire _1516_;
  (* src = "ls180.v:3302.46-3302.162" *)
  wire _1517_;
  (* src = "ls180.v:3303.47-3303.111" *)
  wire _1518_;
  (* src = "ls180.v:3303.46-3303.165" *)
  wire _1519_;
  (* src = "ls180.v:3305.44-3305.105" *)
  wire _1520_;
  (* src = "ls180.v:3305.43-3305.159" *)
  wire _1521_;
  (* src = "ls180.v:3306.44-3306.108" *)
  wire _1522_;
  (* src = "ls180.v:3306.43-3306.162" *)
  wire _1523_;
  (* src = "ls180.v:3308.43-3308.104" *)
  wire _1524_;
  (* src = "ls180.v:3308.42-3308.158" *)
  wire _1525_;
  (* src = "ls180.v:3309.43-3309.107" *)
  wire _1526_;
  (* src = "ls180.v:3309.42-3309.161" *)
  wire _1527_;
  (* src = "ls180.v:3321.49-3321.110" *)
  wire _1528_;
  (* src = "ls180.v:3321.48-3321.164" *)
  wire _1529_;
  (* src = "ls180.v:3322.49-3322.113" *)
  wire _1530_;
  (* src = "ls180.v:3322.48-3322.167" *)
  wire _1531_;
  (* src = "ls180.v:3324.49-3324.110" *)
  wire _1532_;
  (* src = "ls180.v:3324.48-3324.164" *)
  wire _1533_;
  (* src = "ls180.v:3325.49-3325.113" *)
  wire _1534_;
  (* src = "ls180.v:3325.48-3325.167" *)
  wire _1535_;
  (* src = "ls180.v:3327.49-3327.110" *)
  wire _1536_;
  (* src = "ls180.v:3327.48-3327.164" *)
  wire _1537_;
  (* src = "ls180.v:3328.49-3328.113" *)
  wire _1538_;
  (* src = "ls180.v:3328.48-3328.167" *)
  wire _1539_;
  (* src = "ls180.v:3330.49-3330.110" *)
  wire _1540_;
  (* src = "ls180.v:3330.48-3330.164" *)
  wire _1541_;
  (* src = "ls180.v:3331.49-3331.113" *)
  wire _1542_;
  (* src = "ls180.v:3331.48-3331.167" *)
  wire _1543_;
  (* src = "ls180.v:3691.96-3691.165" *)
  wire _1544_;
  (* src = "ls180.v:3691.171-3691.240" *)
  wire _1545_;
  (* src = "ls180.v:3691.246-3691.315" *)
  wire _1546_;
  (* src = "ls180.v:3691.27-3691.318" *)
  wire _1547_;
  (* src = "ls180.v:3691.26-3691.336" *)
  wire _1548_;
  (* src = "ls180.v:3715.96-3715.165" *)
  wire _1549_;
  (* src = "ls180.v:3715.171-3715.240" *)
  wire _1550_;
  (* src = "ls180.v:3715.246-3715.315" *)
  wire _1551_;
  (* src = "ls180.v:3715.27-3715.318" *)
  wire _1552_;
  (* src = "ls180.v:3715.26-3715.336" *)
  wire _1553_;
  (* src = "ls180.v:3739.96-3739.165" *)
  wire _1554_;
  (* src = "ls180.v:3739.171-3739.240" *)
  wire _1555_;
  (* src = "ls180.v:3739.246-3739.315" *)
  wire _1556_;
  (* src = "ls180.v:3739.27-3739.318" *)
  wire _1557_;
  (* src = "ls180.v:3739.26-3739.336" *)
  wire _1558_;
  (* src = "ls180.v:3763.96-3763.165" *)
  wire _1559_;
  (* src = "ls180.v:3763.171-3763.240" *)
  wire _1560_;
  (* src = "ls180.v:3763.246-3763.315" *)
  wire _1561_;
  (* src = "ls180.v:3763.27-3763.318" *)
  wire _1562_;
  (* src = "ls180.v:3763.26-3763.336" *)
  wire _1563_;
  (* src = "ls180.v:3920.22-3920.77" *)
  wire _1564_;
  (* src = "ls180.v:3920.21-3920.113" *)
  wire _1565_;
  (* src = "ls180.v:3923.22-3923.77" *)
  wire _1566_;
  (* src = "ls180.v:3923.21-3923.113" *)
  wire _1567_;
  (* src = "ls180.v:3926.22-3926.55" *)
  wire _1568_;
  (* src = "ls180.v:3926.21-3926.80" *)
  wire _1569_;
  (* src = "ls180.v:3937.22-3937.77" *)
  wire _1570_;
  (* src = "ls180.v:3937.21-3937.113" *)
  wire _1571_;
  (* src = "ls180.v:3940.22-3940.77" *)
  wire _1572_;
  (* src = "ls180.v:3940.21-3940.113" *)
  wire _1573_;
  (* src = "ls180.v:3943.22-3943.55" *)
  wire _1574_;
  (* src = "ls180.v:3943.21-3943.80" *)
  wire _1575_;
  (* src = "ls180.v:3954.22-3954.77" *)
  wire _1576_;
  (* src = "ls180.v:3954.21-3954.112" *)
  wire _1577_;
  (* src = "ls180.v:3957.22-3957.77" *)
  wire _1578_;
  (* src = "ls180.v:3957.21-3957.112" *)
  wire _1579_;
  (* src = "ls180.v:3960.22-3960.55" *)
  wire _1580_;
  (* src = "ls180.v:3960.21-3960.79" *)
  wire _1581_;
  (* src = "ls180.v:3971.22-3971.77" *)
  wire _1582_;
  (* src = "ls180.v:3971.21-3971.117" *)
  wire _1583_;
  (* src = "ls180.v:3974.22-3974.77" *)
  wire _1584_;
  (* src = "ls180.v:3974.21-3974.117" *)
  wire _1585_;
  (* src = "ls180.v:3977.22-3977.55" *)
  wire _1586_;
  (* src = "ls180.v:3977.21-3977.84" *)
  wire _1587_;
  (* src = "ls180.v:3988.22-3988.77" *)
  wire _1588_;
  (* src = "ls180.v:3988.21-3988.118" *)
  wire _1589_;
  (* src = "ls180.v:3991.22-3991.77" *)
  wire _1590_;
  (* src = "ls180.v:3991.21-3991.118" *)
  wire _1591_;
  (* src = "ls180.v:3994.22-3994.55" *)
  wire _1592_;
  (* src = "ls180.v:3994.21-3994.85" *)
  wire _1593_;
  (* src = "ls180.v:4192.57-4192.97" *)
  wire _1594_;
  (* src = "ls180.v:4193.57-4193.97" *)
  wire _1595_;
  (* src = "ls180.v:4314.8-4314.57" *)
  wire _1596_;
  (* src = "ls180.v:4314.7-4314.87" *)
  wire _1597_;
  (* src = "ls180.v:4333.7-4333.65" *)
  wire _1598_;
  (* src = "ls180.v:4337.8-4337.49" *)
  wire _1599_;
  (* src = "ls180.v:4337.7-4337.75" *)
  wire _1600_;
  (* src = "ls180.v:4345.7-4345.46" *)
  wire _1601_;
  (* src = "ls180.v:4373.7-4373.65" *)
  wire _1602_;
  (* src = "ls180.v:4415.8-4415.121" *)
  wire _1603_;
  (* src = "ls180.v:4415.7-4415.175" *)
  wire _1604_;
  (* src = "ls180.v:4421.8-4421.121" *)
  wire _1605_;
  (* src = "ls180.v:4421.7-4421.175" *)
  wire _1606_;
  (* src = "ls180.v:4461.8-4461.121" *)
  wire _1607_;
  (* src = "ls180.v:4461.7-4461.175" *)
  wire _1608_;
  (* src = "ls180.v:4467.8-4467.121" *)
  wire _1609_;
  (* src = "ls180.v:4467.7-4467.175" *)
  wire _1610_;
  (* src = "ls180.v:4507.8-4507.121" *)
  wire _1611_;
  (* src = "ls180.v:4507.7-4507.175" *)
  wire _1612_;
  (* src = "ls180.v:4513.8-4513.121" *)
  wire _1613_;
  (* src = "ls180.v:4513.7-4513.175" *)
  wire _1614_;
  (* src = "ls180.v:4553.8-4553.121" *)
  wire _1615_;
  (* src = "ls180.v:4553.7-4553.175" *)
  wire _1616_;
  (* src = "ls180.v:4559.8-4559.121" *)
  wire _1617_;
  (* src = "ls180.v:4559.7-4559.175" *)
  wire _1618_;
  (* src = "ls180.v:4756.53-4756.129" *)
  wire _1619_;
  (* src = "ls180.v:4756.135-4756.211" *)
  wire _1620_;
  (* src = "ls180.v:4756.217-4756.293" *)
  wire _1621_;
  (* src = "ls180.v:4756.299-4756.375" *)
  wire _1622_;
  (* src = "ls180.v:4757.54-4757.130" *)
  wire _1623_;
  (* src = "ls180.v:4757.136-4757.212" *)
  wire _1624_;
  (* src = "ls180.v:4757.218-4757.294" *)
  wire _1625_;
  (* src = "ls180.v:4757.300-4757.376" *)
  wire _1626_;
  (* src = "ls180.v:4776.8-4776.39" *)
  wire _1627_;
  (* src = "ls180.v:4779.8-4779.43" *)
  wire _1628_;
  (* src = "ls180.v:4784.8-4784.49" *)
  wire _1629_;
  (* src = "ls180.v:4784.7-4784.75" *)
  wire _1630_;
  (* src = "ls180.v:4790.8-4790.49" *)
  wire _1631_;
  (* src = "ls180.v:4814.8-4814.38" *)
  wire _1632_;
  (* src = "ls180.v:4847.7-4847.37" *)
  wire _1633_;
  (* src = "ls180.v:4854.7-4854.37" *)
  wire _1634_;
  (* src = "ls180.v:4864.8-4864.55" *)
  wire _1635_;
  (* src = "ls180.v:4864.7-4864.77" *)
  wire _1636_;
  (* src = "ls180.v:4870.8-4870.55" *)
  wire _1637_;
  (* src = "ls180.v:4870.7-4870.77" *)
  wire _1638_;
  (* src = "ls180.v:4886.8-4886.55" *)
  wire _1639_;
  (* src = "ls180.v:4886.7-4886.77" *)
  wire _1640_;
  (* src = "ls180.v:4892.8-4892.55" *)
  wire _1641_;
  (* src = "ls180.v:4892.7-4892.77" *)
  wire _1642_;
  (* src = "ls180.v:1546.37-1546.91" *)
  wire _1643_;
  (* src = "ls180.v:1553.11-1553.49" *)
  wire _1644_;
  (* src = "ls180.v:1606.37-1606.91" *)
  wire _1645_;
  (* src = "ls180.v:1613.11-1613.49" *)
  wire _1646_;
  (* src = "ls180.v:1809.29-1809.55" *)
  wire _1647_;
  (* src = "ls180.v:1813.58-1813.87" *)
  wire _1648_;
  (* src = "ls180.v:1857.38-1857.119" *)
  wire _1649_;
  (* src = "ls180.v:1874.42-1874.78" *)
  wire _1650_;
  (* src = "ls180.v:2014.38-2014.119" *)
  wire _1651_;
  (* src = "ls180.v:2031.42-2031.78" *)
  wire _1652_;
  (* src = "ls180.v:2171.38-2171.119" *)
  wire _1653_;
  (* src = "ls180.v:2188.42-2188.78" *)
  wire _1654_;
  (* src = "ls180.v:2328.38-2328.119" *)
  wire _1655_;
  (* src = "ls180.v:2345.42-2345.78" *)
  wire _1656_;
  (* src = "ls180.v:2482.27-2482.46" *)
  wire _1657_;
  (* src = "ls180.v:2483.27-2483.46" *)
  wire _1658_;
  (* src = "ls180.v:2494.299-2494.368" *)
  wire _1659_;
  (* src = "ls180.v:2494.373-2494.444" *)
  wire _1660_;
  (* src = "ls180.v:2495.299-2495.368" *)
  wire _1661_;
  (* src = "ls180.v:2495.373-2495.444" *)
  wire _1662_;
  (* src = "ls180.v:2496.299-2496.368" *)
  wire _1663_;
  (* src = "ls180.v:2496.373-2496.444" *)
  wire _1664_;
  (* src = "ls180.v:2497.299-2497.368" *)
  wire _1665_;
  (* src = "ls180.v:2497.373-2497.444" *)
  wire _1666_;
  (* src = "ls180.v:2527.299-2527.368" *)
  wire _1667_;
  (* src = "ls180.v:2527.373-2527.444" *)
  wire _1668_;
  (* src = "ls180.v:2528.299-2528.368" *)
  wire _1669_;
  (* src = "ls180.v:2528.373-2528.444" *)
  wire _1670_;
  (* src = "ls180.v:2529.299-2529.368" *)
  wire _1671_;
  (* src = "ls180.v:2529.373-2529.444" *)
  wire _1672_;
  (* src = "ls180.v:2530.299-2530.368" *)
  wire _1673_;
  (* src = "ls180.v:2530.373-2530.444" *)
  wire _1674_;
  (* src = "ls180.v:2559.68-2559.98" *)
  wire _1675_;
  (* src = "ls180.v:2562.68-2562.98" *)
  wire _1676_;
  (* src = "ls180.v:2568.68-2568.98" *)
  wire _1677_;
  (* src = "ls180.v:2571.68-2571.98" *)
  wire _1678_;
  (* src = "ls180.v:2577.68-2577.98" *)
  wire _1679_;
  (* src = "ls180.v:2580.68-2580.98" *)
  wire _1680_;
  (* src = "ls180.v:2586.68-2586.98" *)
  wire _1681_;
  (* src = "ls180.v:2589.68-2589.98" *)
  wire _1682_;
  (* src = "ls180.v:2670.47-2670.82" *)
  wire _1683_;
  (* src = "ls180.v:2670.145-2670.183" *)
  wire _1684_;
  (* src = "ls180.v:2670.220-2670.258" *)
  wire _1685_;
  (* src = "ls180.v:2670.295-2670.333" *)
  wire _1686_;
  (* src = "ls180.v:2675.47-2675.82" *)
  wire _1687_;
  (* src = "ls180.v:2675.145-2675.183" *)
  wire _1688_;
  (* src = "ls180.v:2675.220-2675.258" *)
  wire _1689_;
  (* src = "ls180.v:2675.295-2675.333" *)
  wire _1690_;
  (* src = "ls180.v:2680.47-2680.82" *)
  wire _1691_;
  (* src = "ls180.v:2680.145-2680.183" *)
  wire _1692_;
  (* src = "ls180.v:2680.220-2680.258" *)
  wire _1693_;
  (* src = "ls180.v:2680.295-2680.333" *)
  wire _1694_;
  (* src = "ls180.v:2685.47-2685.82" *)
  wire _1695_;
  (* src = "ls180.v:2685.145-2685.183" *)
  wire _1696_;
  (* src = "ls180.v:2685.220-2685.258" *)
  wire _1697_;
  (* src = "ls180.v:2685.295-2685.333" *)
  wire _1698_;
  (* src = "ls180.v:2690.39-2690.77" *)
  wire _1699_;
  (* src = "ls180.v:2690.83-2690.118" *)
  wire _1700_;
  (* src = "ls180.v:2690.181-2690.219" *)
  wire _1701_;
  (* src = "ls180.v:2690.256-2690.294" *)
  wire _1702_;
  (* src = "ls180.v:2690.331-2690.369" *)
  wire _1703_;
  (* src = "ls180.v:2690.413-2690.451" *)
  wire _1704_;
  (* src = "ls180.v:2690.457-2690.492" *)
  wire _1705_;
  (* src = "ls180.v:2690.555-2690.593" *)
  wire _1706_;
  (* src = "ls180.v:2690.630-2690.668" *)
  wire _1707_;
  (* src = "ls180.v:2690.705-2690.743" *)
  wire _1708_;
  (* src = "ls180.v:2690.787-2690.825" *)
  wire _1709_;
  (* src = "ls180.v:2690.831-2690.866" *)
  wire _1710_;
  (* src = "ls180.v:2690.929-2690.967" *)
  wire _1711_;
  (* src = "ls180.v:2690.1004-2690.1042" *)
  wire _1712_;
  (* src = "ls180.v:2690.1079-2690.1117" *)
  wire _1713_;
  (* src = "ls180.v:2690.1161-2690.1199" *)
  wire _1714_;
  (* src = "ls180.v:2690.1205-2690.1240" *)
  wire _1715_;
  (* src = "ls180.v:2690.1303-2690.1341" *)
  wire _1716_;
  (* src = "ls180.v:2690.1378-2690.1416" *)
  wire _1717_;
  (* src = "ls180.v:2690.1453-2690.1491" *)
  wire _1718_;
  (* src = "ls180.v:2749.24-2749.47" *)
  wire _1719_;
  (* src = "ls180.v:2756.11-2756.36" *)
  wire _1720_;
  (* src = "ls180.v:3013.84-3013.109" *)
  wire _1721_;
  (* src = "ls180.v:3014.84-3014.109" *)
  wire _1722_;
  (* src = "ls180.v:3015.70-3015.95" *)
  wire _1723_;
  (* src = "ls180.v:3016.84-3016.109" *)
  wire _1724_;
  (* src = "ls180.v:3017.84-3017.109" *)
  wire _1725_;
  (* src = "ls180.v:3018.70-3018.95" *)
  wire _1726_;
  (* src = "ls180.v:3022.31-3022.67" *)
  wire _1727_;
  (* src = "ls180.v:3023.31-3023.68" *)
  wire _1728_;
  (* src = "ls180.v:3024.31-3024.76" *)
  wire _1729_;
  (* src = "ls180.v:3025.31-3025.74" *)
  wire _1730_;
  (* src = "ls180.v:3026.31-3026.69" *)
  wire _1731_;
  (* src = "ls180.v:3027.31-3027.73" *)
  wire _1732_;
  (* src = "ls180.v:3091.28-3091.53" *)
  wire _1733_;
  (* src = "ls180.v:3092.36-3092.85" *)
  wire _1734_;
  (* src = "ls180.v:3094.109-3094.157" *)
  wire _1735_;
  (* src = "ls180.v:3095.112-3095.160" *)
  wire _1736_;
  (* src = "ls180.v:3097.111-3097.159" *)
  wire _1737_;
  (* src = "ls180.v:3098.114-3098.162" *)
  wire _1738_;
  (* src = "ls180.v:3100.111-3100.159" *)
  wire _1739_;
  (* src = "ls180.v:3101.114-3101.162" *)
  wire _1740_;
  (* src = "ls180.v:3103.111-3103.159" *)
  wire _1741_;
  (* src = "ls180.v:3104.114-3104.162" *)
  wire _1742_;
  (* src = "ls180.v:3106.111-3106.159" *)
  wire _1743_;
  (* src = "ls180.v:3107.114-3107.162" *)
  wire _1744_;
  (* src = "ls180.v:3109.114-3109.162" *)
  wire _1745_;
  (* src = "ls180.v:3110.117-3110.165" *)
  wire _1746_;
  (* src = "ls180.v:3112.114-3112.162" *)
  wire _1747_;
  (* src = "ls180.v:3113.117-3113.165" *)
  wire _1748_;
  (* src = "ls180.v:3115.114-3115.162" *)
  wire _1749_;
  (* src = "ls180.v:3116.117-3116.165" *)
  wire _1750_;
  (* src = "ls180.v:3118.114-3118.162" *)
  wire _1751_;
  (* src = "ls180.v:3119.117-3119.165" *)
  wire _1752_;
  (* src = "ls180.v:3130.36-3130.85" *)
  wire _1753_;
  (* src = "ls180.v:3132.106-3132.154" *)
  wire _1754_;
  (* src = "ls180.v:3133.109-3133.157" *)
  wire _1755_;
  (* src = "ls180.v:3135.105-3135.153" *)
  wire _1756_;
  (* src = "ls180.v:3136.108-3136.156" *)
  wire _1757_;
  (* src = "ls180.v:3138.107-3138.155" *)
  wire _1758_;
  (* src = "ls180.v:3139.110-3139.158" *)
  wire _1759_;
  (* src = "ls180.v:3144.36-3144.85" *)
  wire _1760_;
  (* src = "ls180.v:3146.106-3146.154" *)
  wire _1761_;
  (* src = "ls180.v:3147.109-3147.157" *)
  wire _1762_;
  (* src = "ls180.v:3149.105-3149.153" *)
  wire _1763_;
  (* src = "ls180.v:3150.108-3150.156" *)
  wire _1764_;
  (* src = "ls180.v:3152.107-3152.155" *)
  wire _1765_;
  (* src = "ls180.v:3153.110-3153.158" *)
  wire _1766_;
  (* src = "ls180.v:3158.36-3158.85" *)
  wire _1767_;
  (* src = "ls180.v:3160.105-3160.151" *)
  wire _1768_;
  (* src = "ls180.v:3161.108-3161.154" *)
  wire _1769_;
  (* src = "ls180.v:3163.104-3163.150" *)
  wire _1770_;
  (* src = "ls180.v:3164.107-3164.153" *)
  wire _1771_;
  (* src = "ls180.v:3172.36-3172.85" *)
  wire _1772_;
  (* src = "ls180.v:3174.116-3174.164" *)
  wire _1773_;
  (* src = "ls180.v:3175.119-3175.167" *)
  wire _1774_;
  (* src = "ls180.v:3177.120-3177.168" *)
  wire _1775_;
  (* src = "ls180.v:3178.123-3178.171" *)
  wire _1776_;
  (* src = "ls180.v:3180.101-3180.149" *)
  wire _1777_;
  (* src = "ls180.v:3181.104-3181.152" *)
  wire _1778_;
  (* src = "ls180.v:3183.120-3183.168" *)
  wire _1779_;
  (* src = "ls180.v:3184.123-3184.171" *)
  wire _1780_;
  (* src = "ls180.v:3186.120-3186.168" *)
  wire _1781_;
  (* src = "ls180.v:3187.123-3187.171" *)
  wire _1782_;
  (* src = "ls180.v:3189.121-3189.169" *)
  wire _1783_;
  (* src = "ls180.v:3190.124-3190.172" *)
  wire _1784_;
  (* src = "ls180.v:3192.119-3192.167" *)
  wire _1785_;
  (* src = "ls180.v:3193.122-3193.170" *)
  wire _1786_;
  (* src = "ls180.v:3195.119-3195.167" *)
  wire _1787_;
  (* src = "ls180.v:3196.122-3196.170" *)
  wire _1788_;
  (* src = "ls180.v:3198.119-3198.167" *)
  wire _1789_;
  (* src = "ls180.v:3199.122-3199.170" *)
  wire _1790_;
  (* src = "ls180.v:3201.119-3201.167" *)
  wire _1791_;
  (* src = "ls180.v:3202.122-3202.170" *)
  wire _1792_;
  (* src = "ls180.v:3217.36-3217.85" *)
  wire _1793_;
  (* src = "ls180.v:3219.108-3219.156" *)
  wire _1794_;
  (* src = "ls180.v:3220.111-3220.159" *)
  wire _1795_;
  (* src = "ls180.v:3222.108-3222.156" *)
  wire _1796_;
  (* src = "ls180.v:3223.111-3223.159" *)
  wire _1797_;
  (* src = "ls180.v:3225.108-3225.156" *)
  wire _1798_;
  (* src = "ls180.v:3226.111-3226.159" *)
  wire _1799_;
  (* src = "ls180.v:3228.108-3228.156" *)
  wire _1800_;
  (* src = "ls180.v:3229.111-3229.159" *)
  wire _1801_;
  (* src = "ls180.v:3231.110-3231.158" *)
  wire _1802_;
  (* src = "ls180.v:3232.113-3232.161" *)
  wire _1803_;
  (* src = "ls180.v:3234.110-3234.158" *)
  wire _1804_;
  (* src = "ls180.v:3235.113-3235.161" *)
  wire _1805_;
  (* src = "ls180.v:3237.110-3237.158" *)
  wire _1806_;
  (* src = "ls180.v:3238.113-3238.161" *)
  wire _1807_;
  (* src = "ls180.v:3240.110-3240.158" *)
  wire _1808_;
  (* src = "ls180.v:3241.113-3241.161" *)
  wire _1809_;
  (* src = "ls180.v:3243.106-3243.154" *)
  wire _1810_;
  (* src = "ls180.v:3244.109-3244.157" *)
  wire _1811_;
  (* src = "ls180.v:3246.116-3246.164" *)
  wire _1812_;
  (* src = "ls180.v:3247.119-3247.167" *)
  wire _1813_;
  (* src = "ls180.v:3249.109-3249.158" *)
  wire _1814_;
  (* src = "ls180.v:3250.112-3250.161" *)
  wire _1815_;
  (* src = "ls180.v:3252.109-3252.158" *)
  wire _1816_;
  (* src = "ls180.v:3253.112-3253.161" *)
  wire _1817_;
  (* src = "ls180.v:3255.109-3255.158" *)
  wire _1818_;
  (* src = "ls180.v:3256.112-3256.161" *)
  wire _1819_;
  (* src = "ls180.v:3258.109-3258.158" *)
  wire _1820_;
  (* src = "ls180.v:3259.112-3259.161" *)
  wire _1821_;
  (* src = "ls180.v:3261.113-3261.162" *)
  wire _1822_;
  (* src = "ls180.v:3262.116-3262.165" *)
  wire _1823_;
  (* src = "ls180.v:3264.114-3264.163" *)
  wire _1824_;
  (* src = "ls180.v:3265.117-3265.166" *)
  wire _1825_;
  (* src = "ls180.v:3267.113-3267.162" *)
  wire _1826_;
  (* src = "ls180.v:3268.116-3268.165" *)
  wire _1827_;
  (* src = "ls180.v:3285.36-3285.85" *)
  wire _1828_;
  (* src = "ls180.v:3287.86-3287.134" *)
  wire _1829_;
  (* src = "ls180.v:3288.89-3288.137" *)
  wire _1830_;
  (* src = "ls180.v:3290.109-3290.157" *)
  wire _1831_;
  (* src = "ls180.v:3291.112-3291.160" *)
  wire _1832_;
  (* src = "ls180.v:3293.110-3293.158" *)
  wire _1833_;
  (* src = "ls180.v:3294.113-3294.161" *)
  wire _1834_;
  (* src = "ls180.v:3296.101-3296.149" *)
  wire _1835_;
  (* src = "ls180.v:3297.104-3297.152" *)
  wire _1836_;
  (* src = "ls180.v:3299.102-3299.150" *)
  wire _1837_;
  (* src = "ls180.v:3300.105-3300.153" *)
  wire _1838_;
  (* src = "ls180.v:3302.113-3302.161" *)
  wire _1839_;
  (* src = "ls180.v:3303.116-3303.164" *)
  wire _1840_;
  (* src = "ls180.v:3305.110-3305.158" *)
  wire _1841_;
  (* src = "ls180.v:3306.113-3306.161" *)
  wire _1842_;
  (* src = "ls180.v:3308.109-3308.157" *)
  wire _1843_;
  (* src = "ls180.v:3309.112-3309.160" *)
  wire _1844_;
  (* src = "ls180.v:3319.36-3319.85" *)
  wire _1845_;
  (* src = "ls180.v:3321.115-3321.163" *)
  wire _1846_;
  (* src = "ls180.v:3322.118-3322.166" *)
  wire _1847_;
  (* src = "ls180.v:3324.115-3324.163" *)
  wire _1848_;
  (* src = "ls180.v:3325.118-3325.166" *)
  wire _1849_;
  (* src = "ls180.v:3327.115-3327.163" *)
  wire _1850_;
  (* src = "ls180.v:3328.118-3328.166" *)
  wire _1851_;
  (* src = "ls180.v:3330.115-3330.163" *)
  wire _1852_;
  (* src = "ls180.v:3331.118-3331.166" *)
  wire _1853_;
  (* src = "ls180.v:3691.28-3691.63" *)
  wire _1854_;
  (* src = "ls180.v:3691.126-3691.164" *)
  wire _1855_;
  (* src = "ls180.v:3691.201-3691.239" *)
  wire _1856_;
  (* src = "ls180.v:3691.276-3691.314" *)
  wire _1857_;
  (* src = "ls180.v:3715.28-3715.63" *)
  wire _1858_;
  (* src = "ls180.v:3715.126-3715.164" *)
  wire _1859_;
  (* src = "ls180.v:3715.201-3715.239" *)
  wire _1860_;
  (* src = "ls180.v:3715.276-3715.314" *)
  wire _1861_;
  (* src = "ls180.v:3739.28-3739.63" *)
  wire _1862_;
  (* src = "ls180.v:3739.126-3739.164" *)
  wire _1863_;
  (* src = "ls180.v:3739.201-3739.239" *)
  wire _1864_;
  (* src = "ls180.v:3739.276-3739.314" *)
  wire _1865_;
  (* src = "ls180.v:3763.28-3763.63" *)
  wire _1866_;
  (* src = "ls180.v:3763.126-3763.164" *)
  wire _1867_;
  (* src = "ls180.v:3763.201-3763.239" *)
  wire _1868_;
  (* src = "ls180.v:3763.276-3763.314" *)
  wire _1869_;
  (* src = "ls180.v:4318.8-4318.33" *)
  wire _1870_;
  (* src = "ls180.v:4353.8-4353.37" *)
  wire _1871_;
  (* src = "ls180.v:4373.33-4373.64" *)
  wire _1872_;
  (* src = "ls180.v:4380.7-4380.38" *)
  wire _1873_;
  (* src = "ls180.v:4387.7-4387.38" *)
  wire _1874_;
  (* src = "ls180.v:4395.7-4395.38" *)
  wire _1875_;
  (* src = "ls180.v:4447.9-4447.49" *)
  wire _1876_;
  (* src = "ls180.v:4493.9-4493.49" *)
  wire _1877_;
  (* src = "ls180.v:4539.9-4539.49" *)
  wire _1878_;
  (* src = "ls180.v:4585.9-4585.49" *)
  wire _1879_;
  (* src = "ls180.v:4735.9-4735.36" *)
  wire _1880_;
  (* src = "ls180.v:4750.9-4750.36" *)
  wire _1881_;
  (* src = "ls180.v:4756.54-4756.92" *)
  wire _1882_;
  (* src = "ls180.v:4756.136-4756.174" *)
  wire _1883_;
  (* src = "ls180.v:4756.218-4756.256" *)
  wire _1884_;
  (* src = "ls180.v:4756.300-4756.338" *)
  wire _1885_;
  (* src = "ls180.v:4757.55-4757.93" *)
  wire _1886_;
  (* src = "ls180.v:4757.137-4757.175" *)
  wire _1887_;
  (* src = "ls180.v:4757.219-4757.257" *)
  wire _1888_;
  (* src = "ls180.v:4757.301-4757.339" *)
  wire _1889_;
  (* src = "ls180.v:4792.9-4792.37" *)
  wire _1890_;
  (* src = "ls180.v:4795.10-4795.38" *)
  wire _1891_;
  (* src = "ls180.v:4821.9-4821.37" *)
  wire _1892_;
  (* src = "ls180.v:4826.10-4826.38" *)
  wire _1893_;
  (* src = "ls180.v:5458.28-5458.31" *)
  wire [31:0] _1894_;
  (* src = "ls180.v:5478.20-5478.25" *)
  wire [31:0] _1895_;
  (* src = "ls180.v:5489.12-5489.19" *)
  wire [24:0] _1896_;
  (* src = "ls180.v:5496.63-5496.70" *)
  wire [24:0] _1897_;
  (* src = "ls180.v:5503.14-5503.23" *)
  wire [24:0] _1898_;
  (* src = "ls180.v:5510.63-5510.72" *)
  wire [24:0] _1899_;
  (* src = "ls180.v:5517.14-5517.23" *)
  wire [24:0] _1900_;
  (* src = "ls180.v:5524.63-5524.72" *)
  wire [24:0] _1901_;
  (* src = "ls180.v:5531.14-5531.23" *)
  wire [24:0] _1902_;
  (* src = "ls180.v:5538.63-5538.72" *)
  wire [24:0] _1903_;
  (* src = "ls180.v:5546.14-5546.23" *)
  wire [9:0] _1904_;
  (* src = "ls180.v:5551.15-5551.24" *)
  wire [9:0] _1905_;
  (* src = "ls180.v:5563.14-5563.23" *)
  wire [9:0] _1906_;
  (* src = "ls180.v:5568.15-5568.24" *)
  wire [9:0] _1907_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [6:0] _1908_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1909_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1910_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [6:0] _1911_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1912_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1913_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [6:0] _1914_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1915_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1916_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [6:0] _1917_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1918_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1919_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [4:0] _1920_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1921_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1922_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [4:0] _1923_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1924_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1925_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [4:0] _1926_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1927_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1928_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [4:0] _1929_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1930_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [31:0] _1931_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [2:0] _1932_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1933_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1934_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [2:0] _1935_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1936_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1937_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [2:0] _1938_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1939_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1940_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [2:0] _1941_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1942_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [24:0] _1943_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [3:0] _1944_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [9:0] _1945_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [9:0] _1946_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [3:0] _1947_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [9:0] _1948_;
  (* src = "ls180.v:0.0-0.0" *)
  reg [9:0] _1949_;
  (* src = "ls180.v:1641.36-1641.61" *)
  wire _1950_;
  (* src = "ls180.v:1812.60-1812.89" *)
  wire _1951_;
  (* src = "ls180.v:1873.8-1873.132" *)
  wire _1952_;
  (* src = "ls180.v:1905.70-1905.123" *)
  wire _1953_;
  (* src = "ls180.v:1906.70-1906.123" *)
  wire _1954_;
  (* src = "ls180.v:2030.8-2030.132" *)
  wire _1955_;
  (* src = "ls180.v:2062.70-2062.123" *)
  wire _1956_;
  (* src = "ls180.v:2063.70-2063.123" *)
  wire _1957_;
  (* src = "ls180.v:2187.8-2187.132" *)
  wire _1958_;
  (* src = "ls180.v:2219.70-2219.123" *)
  wire _1959_;
  (* src = "ls180.v:2220.70-2220.123" *)
  wire _1960_;
  (* src = "ls180.v:2344.8-2344.132" *)
  wire _1961_;
  (* src = "ls180.v:2376.70-2376.123" *)
  wire _1962_;
  (* src = "ls180.v:2377.70-2377.123" *)
  wire _1963_;
  (* src = "ls180.v:2869.37-2869.60" *)
  wire _1964_;
  (* src = "ls180.v:2870.37-2870.59" *)
  wire _1965_;
  (* src = "ls180.v:2899.37-2899.60" *)
  wire _1966_;
  (* src = "ls180.v:2900.37-2900.59" *)
  wire _1967_;
  (* src = "ls180.v:2995.99-2995.143" *)
  wire _1968_;
  (* src = "ls180.v:4308.7-4308.47" *)
  wire _1969_;
  (* src = "ls180.v:4362.9-4362.38" *)
  wire _1970_;
  (* src = "ls180.v:4398.8-4398.39" *)
  wire _1971_;
  (* src = "ls180.v:1509.40-1509.70" *)
  wire _1972_;
  (* src = "ls180.v:1548.56-1548.84" *)
  wire _1973_;
  (* src = "ls180.v:1549.56-1549.84" *)
  wire _1974_;
  (* src = "ls180.v:1569.40-1569.70" *)
  wire _1975_;
  (* src = "ls180.v:1608.56-1608.84" *)
  wire _1976_;
  (* src = "ls180.v:1609.56-1609.84" *)
  wire _1977_;
  (* src = "ls180.v:1761.29-1761.54" *)
  wire _1978_;
  (* src = "ls180.v:1762.26-1762.51" *)
  wire _1979_;
  (* src = "ls180.v:1763.27-1763.52" *)
  wire _1980_;
  (* src = "ls180.v:1764.27-1764.52" *)
  wire _1981_;
  (* src = "ls180.v:1806.28-1806.46" *)
  wire _1982_;
  (* src = "ls180.v:1907.53-1907.96" *)
  wire _1983_;
  (* src = "ls180.v:1961.9-1961.40" *)
  wire _1984_;
  (* src = "ls180.v:2064.53-2064.96" *)
  wire _1985_;
  (* src = "ls180.v:2118.9-2118.40" *)
  wire _1986_;
  (* src = "ls180.v:2221.53-2221.96" *)
  wire _1987_;
  (* src = "ls180.v:2275.9-2275.40" *)
  wire _1988_;
  (* src = "ls180.v:2378.53-2378.96" *)
  wire _1989_;
  (* src = "ls180.v:2432.9-2432.40" *)
  wire _1990_;
  (* src = "ls180.v:2474.129-2474.162" *)
  wire _1991_;
  (* src = "ls180.v:2474.168-2474.200" *)
  wire _1992_;
  (* src = "ls180.v:2475.129-2475.162" *)
  wire _1993_;
  (* src = "ls180.v:2475.168-2475.200" *)
  wire _1994_;
  (* src = "ls180.v:2491.38-2491.63" *)
  wire [1:0] _1995_;
  (* src = "ls180.v:2494.180-2494.215" *)
  wire _1996_;
  (* src = "ls180.v:2494.221-2494.255" *)
  wire _1997_;
  (* src = "ls180.v:2494.139-2494.257" *)
  wire _1998_;
  (* src = "ls180.v:2495.180-2495.215" *)
  wire _1999_;
  (* src = "ls180.v:2495.221-2495.255" *)
  wire _2000_;
  (* src = "ls180.v:2495.139-2495.257" *)
  wire _2001_;
  (* src = "ls180.v:2496.180-2496.215" *)
  wire _2002_;
  (* src = "ls180.v:2496.221-2496.255" *)
  wire _2003_;
  (* src = "ls180.v:2496.139-2496.257" *)
  wire _2004_;
  (* src = "ls180.v:2497.180-2497.215" *)
  wire _2005_;
  (* src = "ls180.v:2497.221-2497.255" *)
  wire _2006_;
  (* src = "ls180.v:2497.139-2497.257" *)
  wire _2007_;
  (* src = "ls180.v:2524.61-2524.88" *)
  wire _2008_;
  (* src = "ls180.v:2527.180-2527.215" *)
  wire _2009_;
  (* src = "ls180.v:2527.221-2527.255" *)
  wire _2010_;
  (* src = "ls180.v:2527.139-2527.257" *)
  wire _2011_;
  (* src = "ls180.v:2528.180-2528.215" *)
  wire _2012_;
  (* src = "ls180.v:2528.221-2528.255" *)
  wire _2013_;
  (* src = "ls180.v:2528.139-2528.257" *)
  wire _2014_;
  (* src = "ls180.v:2529.180-2529.215" *)
  wire _2015_;
  (* src = "ls180.v:2529.221-2529.255" *)
  wire _2016_;
  (* src = "ls180.v:2529.139-2529.257" *)
  wire _2017_;
  (* src = "ls180.v:2530.180-2530.215" *)
  wire _2018_;
  (* src = "ls180.v:2530.221-2530.255" *)
  wire _2019_;
  (* src = "ls180.v:2530.139-2530.257" *)
  wire _2020_;
  (* src = "ls180.v:2593.61-2593.88" *)
  wire _2021_;
  (* src = "ls180.v:2614.97-2614.130" *)
  wire _2022_;
  (* src = "ls180.v:2614.136-2614.168" *)
  wire _2023_;
  (* src = "ls180.v:2614.58-2614.170" *)
  wire _2024_;
  (* src = "ls180.v:2622.11-2622.33" *)
  wire _2025_;
  (* src = "ls180.v:2652.97-2652.130" *)
  wire _2026_;
  (* src = "ls180.v:2652.136-2652.168" *)
  wire _2027_;
  (* src = "ls180.v:2652.58-2652.170" *)
  wire _2028_;
  (* src = "ls180.v:2660.11-2660.32" *)
  wire _2029_;
  (* src = "ls180.v:2670.87-2670.336" *)
  wire _2030_;
  (* src = "ls180.v:2671.40-2671.68" *)
  wire _2031_;
  (* src = "ls180.v:2671.73-2671.100" *)
  wire _2032_;
  (* src = "ls180.v:2675.87-2675.336" *)
  wire _2033_;
  (* src = "ls180.v:2676.40-2676.68" *)
  wire _2034_;
  (* src = "ls180.v:2676.73-2676.100" *)
  wire _2035_;
  (* src = "ls180.v:2680.87-2680.336" *)
  wire _2036_;
  (* src = "ls180.v:2681.40-2681.68" *)
  wire _2037_;
  (* src = "ls180.v:2681.73-2681.100" *)
  wire _2038_;
  (* src = "ls180.v:2685.87-2685.336" *)
  wire _2039_;
  (* src = "ls180.v:2686.40-2686.68" *)
  wire _2040_;
  (* src = "ls180.v:2686.73-2686.100" *)
  wire _2041_;
  (* src = "ls180.v:2690.123-2690.372" *)
  wire _2042_;
  (* src = "ls180.v:2690.497-2690.746" *)
  wire _2043_;
  (* src = "ls180.v:2690.871-2690.1120" *)
  wire _2044_;
  (* src = "ls180.v:2690.1245-2690.1494" *)
  wire _2045_;
  (* src = "ls180.v:2712.27-2712.40" *)
  wire _2046_;
  (* src = "ls180.v:2751.25-2751.40" *)
  wire _2047_;
  (* src = "ls180.v:2752.25-2752.40" *)
  wire _2048_;
  (* src = "ls180.v:2777.22-2777.38" *)
  wire _2049_;
  (* src = "ls180.v:2778.25-2778.40" *)
  wire _2050_;
  (* src = "ls180.v:2779.65-2779.78" *)
  wire _2051_;
  (* src = "ls180.v:2780.87-2780.102" *)
  wire _2052_;
  (* src = "ls180.v:2781.63-2781.83" *)
  wire _2053_;
  (* src = "ls180.v:2782.71-2782.86" *)
  wire _2054_;
  (* src = "ls180.v:2798.25-2798.44" *)
  wire _2055_;
  (* src = "ls180.v:2799.26-2799.47" *)
  wire _2056_;
  (* src = "ls180.v:2805.22-2805.41" *)
  wire _2057_;
  (* src = "ls180.v:2811.26-2811.47" *)
  wire _2058_;
  (* src = "ls180.v:2812.25-2812.44" *)
  wire _2059_;
  (* src = "ls180.v:2815.22-2815.43" *)
  wire _2060_;
  (* src = "ls180.v:2853.61-2853.78" *)
  wire _2061_;
  (* src = "ls180.v:2883.61-2883.78" *)
  wire _2062_;
  (* src = "ls180.v:3078.81-3078.104" *)
  wire _2063_;
  (* src = "ls180.v:3095.71-3095.106" *)
  wire _2064_;
  (* src = "ls180.v:3098.73-3098.108" *)
  wire _2065_;
  (* src = "ls180.v:3101.73-3101.108" *)
  wire _2066_;
  (* src = "ls180.v:3104.73-3104.108" *)
  wire _2067_;
  (* src = "ls180.v:3107.73-3107.108" *)
  wire _2068_;
  (* src = "ls180.v:3110.76-3110.111" *)
  wire _2069_;
  (* src = "ls180.v:3113.76-3113.111" *)
  wire _2070_;
  (* src = "ls180.v:3116.76-3116.111" *)
  wire _2071_;
  (* src = "ls180.v:3119.76-3119.111" *)
  wire _2072_;
  (* src = "ls180.v:3133.68-3133.103" *)
  wire _2073_;
  (* src = "ls180.v:3136.67-3136.102" *)
  wire _2074_;
  (* src = "ls180.v:3139.69-3139.104" *)
  wire _2075_;
  (* src = "ls180.v:3147.68-3147.103" *)
  wire _2076_;
  (* src = "ls180.v:3150.67-3150.102" *)
  wire _2077_;
  (* src = "ls180.v:3153.69-3153.104" *)
  wire _2078_;
  (* src = "ls180.v:3161.67-3161.102" *)
  wire _2079_;
  (* src = "ls180.v:3164.66-3164.101" *)
  wire _2080_;
  (* src = "ls180.v:3175.78-3175.113" *)
  wire _2081_;
  (* src = "ls180.v:3178.82-3178.117" *)
  wire _2082_;
  (* src = "ls180.v:3181.63-3181.98" *)
  wire _2083_;
  (* src = "ls180.v:3184.82-3184.117" *)
  wire _2084_;
  (* src = "ls180.v:3187.82-3187.117" *)
  wire _2085_;
  (* src = "ls180.v:3190.83-3190.118" *)
  wire _2086_;
  (* src = "ls180.v:3193.81-3193.116" *)
  wire _2087_;
  (* src = "ls180.v:3196.81-3196.116" *)
  wire _2088_;
  (* src = "ls180.v:3199.81-3199.116" *)
  wire _2089_;
  (* src = "ls180.v:3202.81-3202.116" *)
  wire _2090_;
  (* src = "ls180.v:3220.70-3220.105" *)
  wire _2091_;
  (* src = "ls180.v:3223.70-3223.105" *)
  wire _2092_;
  (* src = "ls180.v:3226.70-3226.105" *)
  wire _2093_;
  (* src = "ls180.v:3229.70-3229.105" *)
  wire _2094_;
  (* src = "ls180.v:3232.72-3232.107" *)
  wire _2095_;
  (* src = "ls180.v:3235.72-3235.107" *)
  wire _2096_;
  (* src = "ls180.v:3238.72-3238.107" *)
  wire _2097_;
  (* src = "ls180.v:3241.72-3241.107" *)
  wire _2098_;
  (* src = "ls180.v:3244.68-3244.103" *)
  wire _2099_;
  (* src = "ls180.v:3247.78-3247.113" *)
  wire _2100_;
  (* src = "ls180.v:3250.71-3250.106" *)
  wire _2101_;
  (* src = "ls180.v:3253.71-3253.106" *)
  wire _2102_;
  (* src = "ls180.v:3256.71-3256.106" *)
  wire _2103_;
  (* src = "ls180.v:3259.71-3259.106" *)
  wire _2104_;
  (* src = "ls180.v:3262.75-3262.110" *)
  wire _2105_;
  (* src = "ls180.v:3265.76-3265.111" *)
  wire _2106_;
  (* src = "ls180.v:3268.75-3268.110" *)
  wire _2107_;
  (* src = "ls180.v:3288.48-3288.83" *)
  wire _2108_;
  (* src = "ls180.v:3291.71-3291.106" *)
  wire _2109_;
  (* src = "ls180.v:3294.72-3294.107" *)
  wire _2110_;
  (* src = "ls180.v:3297.63-3297.98" *)
  wire _2111_;
  (* src = "ls180.v:3300.64-3300.99" *)
  wire _2112_;
  (* src = "ls180.v:3303.75-3303.110" *)
  wire _2113_;
  (* src = "ls180.v:3306.72-3306.107" *)
  wire _2114_;
  (* src = "ls180.v:3309.71-3309.106" *)
  wire _2115_;
  (* src = "ls180.v:3322.77-3322.112" *)
  wire _2116_;
  (* src = "ls180.v:3325.77-3325.112" *)
  wire _2117_;
  (* src = "ls180.v:3328.77-3328.112" *)
  wire _2118_;
  (* src = "ls180.v:3331.77-3331.112" *)
  wire _2119_;
  (* src = "ls180.v:3691.68-3691.317" *)
  wire _2120_;
  (* src = "ls180.v:3715.68-3715.317" *)
  wire _2121_;
  (* src = "ls180.v:3739.68-3739.317" *)
  wire _2122_;
  (* src = "ls180.v:3763.68-3763.317" *)
  wire _2123_;
  (* src = "ls180.v:4314.62-4314.86" *)
  wire _2124_;
  (* src = "ls180.v:4333.8-4333.33" *)
  wire _2125_;
  (* src = "ls180.v:4337.54-4337.74" *)
  wire _2126_;
  (* src = "ls180.v:4345.27-4345.45" *)
  wire _2127_;
  (* src = "ls180.v:4415.126-4415.174" *)
  wire _2128_;
  (* src = "ls180.v:4421.126-4421.174" *)
  wire _2129_;
  (* src = "ls180.v:4422.8-4422.56" *)
  wire _2130_;
  (* src = "ls180.v:4430.8-4430.51" *)
  wire _2131_;
  (* src = "ls180.v:4445.8-4445.41" *)
  wire _2132_;
  (* src = "ls180.v:4461.126-4461.174" *)
  wire _2133_;
  (* src = "ls180.v:4467.126-4467.174" *)
  wire _2134_;
  (* src = "ls180.v:4468.8-4468.56" *)
  wire _2135_;
  (* src = "ls180.v:4476.8-4476.51" *)
  wire _2136_;
  (* src = "ls180.v:4491.8-4491.41" *)
  wire _2137_;
  (* src = "ls180.v:4507.126-4507.174" *)
  wire _2138_;
  (* src = "ls180.v:4513.126-4513.174" *)
  wire _2139_;
  (* src = "ls180.v:4514.8-4514.56" *)
  wire _2140_;
  (* src = "ls180.v:4522.8-4522.51" *)
  wire _2141_;
  (* src = "ls180.v:4537.8-4537.41" *)
  wire _2142_;
  (* src = "ls180.v:4553.126-4553.174" *)
  wire _2143_;
  (* src = "ls180.v:4559.126-4559.174" *)
  wire _2144_;
  (* src = "ls180.v:4560.8-4560.56" *)
  wire _2145_;
  (* src = "ls180.v:4568.8-4568.51" *)
  wire _2146_;
  (* src = "ls180.v:4583.8-4583.41" *)
  wire _2147_;
  (* src = "ls180.v:4591.7-4591.17" *)
  wire _2148_;
  (* src = "ls180.v:4594.8-4594.24" *)
  wire _2149_;
  (* src = "ls180.v:4598.7-4598.17" *)
  wire _2150_;
  (* src = "ls180.v:4601.8-4601.24" *)
  wire _2151_;
  (* src = "ls180.v:4720.25-4720.38" *)
  wire _2152_;
  (* src = "ls180.v:4721.25-4721.38" *)
  wire _2153_;
  (* src = "ls180.v:4722.24-4722.37" *)
  wire _2154_;
  (* src = "ls180.v:4733.8-4733.28" *)
  wire _2155_;
  (* src = "ls180.v:4748.8-4748.28" *)
  wire _2156_;
  (* src = "ls180.v:4784.31-4784.48" *)
  wire _2157_;
  (* src = "ls180.v:4784.54-4784.74" *)
  wire _2158_;
  (* src = "ls180.v:4813.7-4813.24" *)
  wire _2159_;
  (* src = "ls180.v:4814.9-4814.21" *)
  wire _2160_;
  (* src = "ls180.v:4847.8-4847.19" *)
  wire _2161_;
  (* src = "ls180.v:4854.8-4854.19" *)
  wire _2162_;
  (* src = "ls180.v:4864.60-4864.76" *)
  wire _2163_;
  (* src = "ls180.v:4870.60-4870.76" *)
  wire _2164_;
  (* src = "ls180.v:4871.8-4871.24" *)
  wire _2165_;
  (* src = "ls180.v:4886.60-4886.76" *)
  wire _2166_;
  (* src = "ls180.v:4892.60-4892.76" *)
  wire _2167_;
  (* src = "ls180.v:4893.8-4893.24" *)
  wire _2168_;
  (* src = "ls180.v:4927.9-4927.32" *)
  wire _2169_;
  (* src = "ls180.v:4938.9-4938.32" *)
  wire _2170_;
  (* src = "ls180.v:4949.9-4949.32" *)
  wire _2171_;
  (* src = "ls180.v:4962.8-4962.25" *)
  wire _2172_;
  (* src = "ls180.v:1550.10-1550.86" *)
  wire _2173_;
  (* src = "ls180.v:1610.10-1610.86" *)
  wire _2174_;
  (* src = "ls180.v:1812.34-1812.90" *)
  wire _2175_;
  (* src = "ls180.v:1855.54-1855.125" *)
  wire _2176_;
  (* src = "ls180.v:1856.39-1856.136" *)
  wire _2177_;
  (* src = "ls180.v:1864.40-1864.155" *)
  wire [12:0] _2178_;
  (* src = "ls180.v:1901.117-1901.225" *)
  wire _2179_;
  (* src = "ls180.v:1907.52-1907.142" *)
  wire _2180_;
  (* src = "ls180.v:2012.54-2012.125" *)
  wire _2181_;
  (* src = "ls180.v:2013.39-2013.136" *)
  wire _2182_;
  (* src = "ls180.v:2021.40-2021.155" *)
  wire [12:0] _2183_;
  (* src = "ls180.v:2058.117-2058.225" *)
  wire _2184_;
  (* src = "ls180.v:2064.52-2064.142" *)
  wire _2185_;
  (* src = "ls180.v:2169.54-2169.125" *)
  wire _2186_;
  (* src = "ls180.v:2170.39-2170.136" *)
  wire _2187_;
  (* src = "ls180.v:2178.40-2178.155" *)
  wire [12:0] _2188_;
  (* src = "ls180.v:2215.117-2215.225" *)
  wire _2189_;
  (* src = "ls180.v:2221.52-2221.142" *)
  wire _2190_;
  (* src = "ls180.v:2326.54-2326.125" *)
  wire _2191_;
  (* src = "ls180.v:2327.39-2327.136" *)
  wire _2192_;
  (* src = "ls180.v:2335.40-2335.155" *)
  wire [12:0] _2193_;
  (* src = "ls180.v:2372.117-2372.225" *)
  wire _2194_;
  (* src = "ls180.v:2378.52-2378.142" *)
  wire _2195_;
  (* src = "ls180.v:2477.92-2477.168" *)
  wire _2196_;
  (* src = "ls180.v:2480.34-2480.179" *)
  wire _2197_;
  (* src = "ls180.v:2480.33-2480.254" *)
  wire _2198_;
  (* src = "ls180.v:2480.32-2480.329" *)
  wire _2199_;
  (* src = "ls180.v:2481.35-2481.182" *)
  wire _2200_;
  (* src = "ls180.v:2481.34-2481.258" *)
  wire _2201_;
  (* src = "ls180.v:2481.33-2481.334" *)
  wire _2202_;
  (* src = "ls180.v:2494.138-2494.292" *)
  wire _2203_;
  (* src = "ls180.v:2494.65-2494.446" *)
  wire _2204_;
  (* src = "ls180.v:2495.138-2495.292" *)
  wire _2205_;
  (* src = "ls180.v:2495.65-2495.446" *)
  wire _2206_;
  (* src = "ls180.v:2496.138-2496.292" *)
  wire _2207_;
  (* src = "ls180.v:2496.65-2496.446" *)
  wire _2208_;
  (* src = "ls180.v:2497.138-2497.292" *)
  wire _2209_;
  (* src = "ls180.v:2497.65-2497.446" *)
  wire _2210_;
  (* src = "ls180.v:2524.31-2524.89" *)
  wire _2211_;
  (* src = "ls180.v:2527.138-2527.292" *)
  wire _2212_;
  (* src = "ls180.v:2527.65-2527.446" *)
  wire _2213_;
  (* src = "ls180.v:2528.138-2528.292" *)
  wire _2214_;
  (* src = "ls180.v:2528.65-2528.446" *)
  wire _2215_;
  (* src = "ls180.v:2529.138-2529.292" *)
  wire _2216_;
  (* src = "ls180.v:2529.65-2529.446" *)
  wire _2217_;
  (* src = "ls180.v:2530.138-2530.292" *)
  wire _2218_;
  (* src = "ls180.v:2530.65-2530.446" *)
  wire _2219_;
  (* src = "ls180.v:2593.31-2593.89" *)
  wire _2220_;
  (* src = "ls180.v:2614.57-2614.191" *)
  wire _2221_;
  (* src = "ls180.v:2622.10-2622.52" *)
  wire _2222_;
  (* src = "ls180.v:2652.57-2652.191" *)
  wire _2223_;
  (* src = "ls180.v:2660.10-2660.51" *)
  wire _2224_;
  (* src = "ls180.v:2670.91-2670.185" *)
  wire _2225_;
  (* src = "ls180.v:2670.90-2670.260" *)
  wire _2226_;
  (* src = "ls180.v:2670.89-2670.335" *)
  wire _2227_;
  (* src = "ls180.v:2675.91-2675.185" *)
  wire _2228_;
  (* src = "ls180.v:2675.90-2675.260" *)
  wire _2229_;
  (* src = "ls180.v:2675.89-2675.335" *)
  wire _2230_;
  (* src = "ls180.v:2680.91-2680.185" *)
  wire _2231_;
  (* src = "ls180.v:2680.90-2680.260" *)
  wire _2232_;
  (* src = "ls180.v:2680.89-2680.335" *)
  wire _2233_;
  (* src = "ls180.v:2685.91-2685.185" *)
  wire _2234_;
  (* src = "ls180.v:2685.90-2685.260" *)
  wire _2235_;
  (* src = "ls180.v:2685.89-2685.335" *)
  wire _2236_;
  (* src = "ls180.v:2690.127-2690.221" *)
  wire _2237_;
  (* src = "ls180.v:2690.126-2690.296" *)
  wire _2238_;
  (* src = "ls180.v:2690.125-2690.371" *)
  wire _2239_;
  (* src = "ls180.v:2690.29-2690.406" *)
  wire _2240_;
  (* src = "ls180.v:2690.501-2690.595" *)
  wire _2241_;
  (* src = "ls180.v:2690.500-2690.670" *)
  wire _2242_;
  (* src = "ls180.v:2690.499-2690.745" *)
  wire _2243_;
  (* src = "ls180.v:2690.28-2690.780" *)
  wire _2244_;
  (* src = "ls180.v:2690.875-2690.969" *)
  wire _2245_;
  (* src = "ls180.v:2690.874-2690.1044" *)
  wire _2246_;
  (* src = "ls180.v:2690.873-2690.1119" *)
  wire _2247_;
  (* src = "ls180.v:2690.27-2690.1154" *)
  wire _2248_;
  (* src = "ls180.v:2690.1249-2690.1343" *)
  wire _2249_;
  (* src = "ls180.v:2690.1248-2690.1418" *)
  wire _2250_;
  (* src = "ls180.v:2690.1247-2690.1493" *)
  wire _2251_;
  (* src = "ls180.v:2690.26-2690.1528" *)
  wire _2252_;
  (* src = "ls180.v:2753.10-2753.42" *)
  wire _2253_;
  (* src = "ls180.v:2780.30-2780.59" *)
  wire _2254_;
  (* src = "ls180.v:2781.29-2781.58" *)
  wire _2255_;
  (* src = "ls180.v:2782.38-2782.100" *)
  wire _2256_;
  (* src = "ls180.v:2783.19-2783.67" *)
  wire _2257_;
  (* src = "ls180.v:2784.21-2784.75" *)
  wire _2258_;
  (* src = "ls180.v:2814.32-2814.59" *)
  wire _2259_;
  (* src = "ls180.v:2838.15-2838.124" *)
  wire _2260_;
  (* src = "ls180.v:2853.60-2853.92" *)
  wire _2261_;
  (* src = "ls180.v:2864.52-2864.95" *)
  wire _2262_;
  (* src = "ls180.v:2883.60-2883.92" *)
  wire _2263_;
  (* src = "ls180.v:2894.52-2894.95" *)
  wire _2264_;
  (* src = "ls180.v:3077.38-3077.83" *)
  wire _2265_;
  (* src = "ls180.v:3077.37-3077.120" *)
  wire _2266_;
  (* src = "ls180.v:3077.36-3077.157" *)
  wire _2267_;
  (* src = "ls180.v:3077.35-3077.173" *)
  wire _2268_;
  (* src = "ls180.v:3077.34-3077.213" *)
  wire _2269_;
  (* src = "ls180.v:3083.33-3083.78" *)
  wire _2270_;
  (* src = "ls180.v:3083.32-3083.115" *)
  wire _2271_;
  (* src = "ls180.v:3083.31-3083.152" *)
  wire _2272_;
  (* src = "ls180.v:3083.30-3083.168" *)
  wire _2273_;
  (* src = "ls180.v:3083.29-3083.208" *)
  wire _2274_;
  (* src = "ls180.v:3084.35-3084.158" *)
  wire [31:0] _2275_;
  (* src = "ls180.v:3084.34-3084.234" *)
  wire [31:0] _2276_;
  (* src = "ls180.v:3084.33-3084.310" *)
  wire [31:0] _2277_;
  (* src = "ls180.v:3084.32-3084.365" *)
  wire [31:0] _2278_;
  (* src = "ls180.v:3084.31-3084.444" *)
  wire [31:0] _2279_;
  (* src = "ls180.v:3364.52-3364.129" *)
  wire [7:0] _2280_;
  (* src = "ls180.v:3364.51-3364.170" *)
  wire [7:0] _2281_;
  (* src = "ls180.v:3364.50-3364.211" *)
  wire [7:0] _2282_;
  (* src = "ls180.v:3364.49-3364.252" *)
  wire [7:0] _2283_;
  (* src = "ls180.v:3364.48-3364.293" *)
  wire [7:0] _2284_;
  (* src = "ls180.v:3364.47-3364.334" *)
  wire [7:0] _2285_;
  (* src = "ls180.v:3364.46-3364.375" *)
  wire [7:0] _2286_;
  (* src = "ls180.v:3691.72-3691.166" *)
  wire _2287_;
  (* src = "ls180.v:3691.71-3691.241" *)
  wire _2288_;
  (* src = "ls180.v:3691.70-3691.316" *)
  wire _2289_;
  (* src = "ls180.v:3715.72-3715.166" *)
  wire _2290_;
  (* src = "ls180.v:3715.71-3715.241" *)
  wire _2291_;
  (* src = "ls180.v:3715.70-3715.316" *)
  wire _2292_;
  (* src = "ls180.v:3739.72-3739.166" *)
  wire _2293_;
  (* src = "ls180.v:3739.71-3739.241" *)
  wire _2294_;
  (* src = "ls180.v:3739.70-3739.316" *)
  wire _2295_;
  (* src = "ls180.v:3763.72-3763.166" *)
  wire _2296_;
  (* src = "ls180.v:3763.71-3763.241" *)
  wire _2297_;
  (* src = "ls180.v:3763.70-3763.316" *)
  wire _2298_;
  (* src = "ls180.v:4246.15-4246.58" *)
  wire _2299_;
  (* src = "ls180.v:4247.15-4247.58" *)
  wire _2300_;
  (* src = "ls180.v:4248.15-4248.58" *)
  wire _2301_;
  (* src = "ls180.v:4249.15-4249.58" *)
  wire _2302_;
  (* src = "ls180.v:4250.15-4250.58" *)
  wire _2303_;
  (* src = "ls180.v:4251.15-4251.58" *)
  wire _2304_;
  (* src = "ls180.v:4252.15-4252.58" *)
  wire _2305_;
  (* src = "ls180.v:4253.15-4253.58" *)
  wire _2306_;
  (* src = "ls180.v:4254.15-4254.58" *)
  wire _2307_;
  (* src = "ls180.v:4255.15-4255.58" *)
  wire _2308_;
  (* src = "ls180.v:4256.16-4256.60" *)
  wire _2309_;
  (* src = "ls180.v:4257.16-4257.60" *)
  wire _2310_;
  (* src = "ls180.v:4258.16-4258.60" *)
  wire _2311_;
  (* src = "ls180.v:4259.16-4259.60" *)
  wire _2312_;
  (* src = "ls180.v:4260.16-4260.60" *)
  wire _2313_;
  (* src = "ls180.v:4261.16-4261.60" *)
  wire _2314_;
  (* src = "ls180.v:4262.16-4262.60" *)
  wire _2315_;
  (* src = "ls180.v:4263.16-4263.60" *)
  wire _2316_;
  (* src = "ls180.v:4264.16-4264.60" *)
  wire _2317_;
  (* src = "ls180.v:4265.16-4265.60" *)
  wire _2318_;
  (* src = "ls180.v:4266.16-4266.60" *)
  wire _2319_;
  (* src = "ls180.v:4267.16-4267.60" *)
  wire _2320_;
  (* src = "ls180.v:4268.16-4268.60" *)
  wire _2321_;
  (* src = "ls180.v:4269.16-4269.60" *)
  wire _2322_;
  (* src = "ls180.v:4270.16-4270.60" *)
  wire _2323_;
  (* src = "ls180.v:4271.16-4271.60" *)
  wire _2324_;
  (* src = "ls180.v:4272.16-4272.60" *)
  wire _2325_;
  (* src = "ls180.v:4273.16-4273.60" *)
  wire _2326_;
  (* src = "ls180.v:4274.16-4274.60" *)
  wire _2327_;
  (* src = "ls180.v:4275.16-4275.60" *)
  wire _2328_;
  (* src = "ls180.v:4276.16-4276.60" *)
  wire _2329_;
  (* src = "ls180.v:4277.16-4277.60" *)
  wire _2330_;
  (* src = "ls180.v:4278.16-4278.60" *)
  wire _2331_;
  (* src = "ls180.v:4279.16-4279.60" *)
  wire _2332_;
  (* src = "ls180.v:4280.16-4280.60" *)
  wire _2333_;
  (* src = "ls180.v:4281.16-4281.60" *)
  wire _2334_;
  (* src = "ls180.v:4282.16-4282.60" *)
  wire _2335_;
  (* src = "ls180.v:4283.16-4283.60" *)
  wire _2336_;
  (* src = "ls180.v:4284.16-4284.60" *)
  wire _2337_;
  (* src = "ls180.v:4285.16-4285.60" *)
  wire _2338_;
  (* src = "ls180.v:4286.7-4286.83" *)
  wire _2339_;
  (* src = "ls180.v:4297.7-4297.83" *)
  wire _2340_;
  (* src = "ls180.v:4430.7-4430.97" *)
  wire _2341_;
  (* src = "ls180.v:4476.7-4476.97" *)
  wire _2342_;
  (* src = "ls180.v:4522.7-4522.97" *)
  wire _2343_;
  (* src = "ls180.v:4568.7-4568.97" *)
  wire _2344_;
  (* src = "ls180.v:4756.45-4756.130" *)
  wire _2345_;
  (* src = "ls180.v:4756.44-4756.212" *)
  wire _2346_;
  (* src = "ls180.v:4756.43-4756.294" *)
  wire _2347_;
  (* src = "ls180.v:4756.42-4756.376" *)
  wire _2348_;
  (* src = "ls180.v:4757.46-4757.131" *)
  wire _2349_;
  (* src = "ls180.v:4757.45-4757.213" *)
  wire _2350_;
  (* src = "ls180.v:4757.44-4757.295" *)
  wire _2351_;
  (* src = "ls180.v:4757.43-4757.377" *)
  wire _2352_;
  (* src = "ls180.v:4761.7-4761.39" *)
  wire _2353_;
  (* src = "ls180.v:5667.8-5667.46" *)
  wire _2354_;
  (* src = "ls180.v:1864.41-1864.84" *)
  wire [12:0] _2355_;
  (* src = "ls180.v:2021.41-2021.84" *)
  wire [12:0] _2356_;
  (* src = "ls180.v:2178.41-2178.84" *)
  wire [12:0] _2357_;
  (* src = "ls180.v:2335.41-2335.84" *)
  wire [12:0] _2358_;
  (* src = "ls180.v:1895.58-1895.112" *)
  wire [2:0] _2359_;
  (* src = "ls180.v:2052.58-2052.112" *)
  wire [2:0] _2360_;
  (* src = "ls180.v:2209.58-2209.112" *)
  wire [2:0] _2361_;
  (* src = "ls180.v:2366.58-2366.112" *)
  wire [2:0] _2362_;
  (* src = "ls180.v:2772.33-2772.65" *)
  wire [30:0] _2363_;
  (* src = "ls180.v:2858.26-2858.48" *)
  wire [3:0] _2364_;
  (* src = "ls180.v:2888.26-2888.48" *)
  wire [3:0] _2365_;
  (* src = "ls180.v:4321.26-4321.50" *)
  wire [31:0] _2366_;
  (* src = "ls180.v:4346.26-4346.51" *)
  wire [9:0] _2367_;
  (* src = "ls180.v:4352.29-4352.57" *)
  wire _2368_;
  (* src = "ls180.v:4363.31-4363.59" *)
  wire _2369_;
  (* src = "ls180.v:4427.54-4427.106" *)
  wire [3:0] _2370_;
  (* src = "ls180.v:4446.41-4446.80" *)
  wire [2:0] _2371_;
  (* src = "ls180.v:4473.54-4473.106" *)
  wire [3:0] _2372_;
  (* src = "ls180.v:4492.41-4492.80" *)
  wire [2:0] _2373_;
  (* src = "ls180.v:4519.54-4519.106" *)
  wire [3:0] _2374_;
  (* src = "ls180.v:4538.41-4538.80" *)
  wire [2:0] _2375_;
  (* src = "ls180.v:4565.54-4565.106" *)
  wire [3:0] _2376_;
  (* src = "ls180.v:4584.41-4584.80" *)
  wire [2:0] _2377_;
  (* src = "ls180.v:4595.20-4595.38" *)
  wire [4:0] _2378_;
  (* src = "ls180.v:4602.20-4602.38" *)
  wire [3:0] _2379_;
  (* src = "ls180.v:4734.28-4734.54" *)
  wire _2380_;
  (* src = "ls180.v:4749.28-4749.54" *)
  wire [2:0] _2381_;
  (* src = "ls180.v:4876.23-4876.44" *)
  wire [4:0] _2382_;
  (* src = "ls180.v:4898.23-4898.44" *)
  wire [4:0] _2383_;
  (* src = "ls180.v:4963.26-4963.50" *)
  wire [19:0] _2384_;
  (* src = "ls180.v:816.6-816.13" *)
  wire ack_cmd;
  (* src = "ls180.v:818.6-818.15" *)
  wire ack_rdata;
  (* src = "ls180.v:817.6-817.15" *)
  wire ack_wdata;
  (* src = "ls180.v:1359.11-1359.23" *)
  reg [1:0] array_muxed0;
  (* src = "ls180.v:1360.12-1360.24" *)
  reg [12:0] array_muxed1;
  (* src = "ls180.v:1361.5-1361.17" *)
  reg array_muxed2;
  (* src = "ls180.v:1362.5-1362.17" *)
  reg array_muxed3;
  (* src = "ls180.v:1363.5-1363.17" *)
  reg array_muxed4;
  (* src = "ls180.v:1364.5-1364.17" *)
  reg array_muxed5;
  (* src = "ls180.v:1365.5-1365.17" *)
  reg array_muxed6;
  (* src = "ls180.v:814.5-814.17" *)
  reg cmd_consumed;
  (* src = "ls180.v:811.5-811.22" *)
  reg converter_counter;
  (* src = "ls180.v:1033.5-1033.46" *)
  reg converter_counter_subfragments_next_value;
  (* src = "ls180.v:1034.5-1034.49" *)
  reg converter_counter_subfragments_next_value_ce;
  (* src = "ls180.v:813.12-813.27" *)
  reg [31:0] converter_dat_r;
  (* src = "ls180.v:812.6-812.21" *)
  wire converter_reset;
  (* src = "ls180.v:810.5-810.19" *)
  reg converter_skip;
  (* src = "ls180.v:240.6-240.18" *)
  wire dfi_p0_act_n;
  (* src = "ls180.v:231.13-231.27" *)
  wire [12:0] dfi_p0_address;
  (* src = "ls180.v:232.12-232.23" *)
  wire [1:0] dfi_p0_bank;
  (* src = "ls180.v:233.6-233.18" *)
  wire dfi_p0_cas_n;
  (* src = "ls180.v:237.6-237.16" *)
  wire dfi_p0_cke;
  (* src = "ls180.v:234.6-234.17" *)
  wire dfi_p0_cs_n;
  (* src = "ls180.v:238.6-238.16" *)
  wire dfi_p0_odt;
  (* src = "ls180.v:235.6-235.18" *)
  wire dfi_p0_ras_n;
  (* src = "ls180.v:245.12-245.25" *)
  reg [15:0] dfi_p0_rddata;
  (* src = "ls180.v:244.6-244.22" *)
  wire dfi_p0_rddata_en;
  (* src = "ls180.v:246.5-246.24" *)
  reg dfi_p0_rddata_valid;
  (* src = "ls180.v:239.6-239.20" *)
  wire dfi_p0_reset_n;
  (* src = "ls180.v:236.6-236.17" *)
  wire dfi_p0_we_n;
  (* src = "ls180.v:241.13-241.26" *)
  wire [15:0] dfi_p0_wrdata;
  (* src = "ls180.v:242.6-242.22" *)
  wire dfi_p0_wrdata_en;
  (* src = "ls180.v:243.12-243.30" *)
  wire [1:0] dfi_p0_wrdata_mask;
  (* src = "ls180.v:981.12-981.17" *)
  reg [39:0] dummy;
  (* src = "ls180.v:18.13-18.19" *)
  input eint_0;
  (* src = "ls180.v:19.13-19.19" *)
  input eint_1;
  (* src = "ls180.v:20.13-20.19" *)
  input eint_2;
  (* src = "ls180.v:979.11-979.19" *)
  reg [2:0] eint_tmp;
  (* src = "ls180.v:867.12-867.34" *)
  wire [1:0] eventmanager_pending_r;
  (* src = "ls180.v:866.6-866.29" *)
  wire eventmanager_pending_re;
  (* src = "ls180.v:869.11-869.33" *)
  reg [1:0] eventmanager_pending_w;
  (* src = "ls180.v:868.6-868.29" *)
  wire eventmanager_pending_we;
  (* src = "ls180.v:871.5-871.20" *)
  reg eventmanager_re;
  (* src = "ls180.v:863.12-863.33" *)
  wire [1:0] eventmanager_status_r;
  (* src = "ls180.v:862.6-862.28" *)
  wire eventmanager_status_re;
  (* src = "ls180.v:865.11-865.32" *)
  reg [1:0] eventmanager_status_w;
  (* src = "ls180.v:864.6-864.28" *)
  wire eventmanager_status_we;
  (* src = "ls180.v:870.11-870.31" *)
  reg [1:0] eventmanager_storage;
  (* src = "ls180.v:962.5-962.16" *)
  reg gpio0_oe_re;
  (* src = "ls180.v:961.11-961.27" *)
  reg [7:0] gpio0_oe_storage;
  (* src = "ls180.v:966.5-966.17" *)
  reg gpio0_out_re;
  (* src = "ls180.v:965.11-965.28" *)
  reg [7:0] gpio0_out_storage;
  (* src = "ls180.v:967.11-967.28" *)
  reg [7:0] gpio0_pads_gpio0i;
  (* src = "ls180.v:968.11-968.28" *)
  reg [7:0] gpio0_pads_gpio0o;
  (* src = "ls180.v:969.11-969.29" *)
  reg [7:0] gpio0_pads_gpio0oe;
  (* src = "ls180.v:963.11-963.23" *)
  reg [7:0] gpio0_status;
  (* src = "ls180.v:964.6-964.14" *)
  wire gpio0_we;
  (* src = "ls180.v:971.5-971.16" *)
  reg gpio1_oe_re;
  (* src = "ls180.v:970.11-970.27" *)
  reg [7:0] gpio1_oe_storage;
  (* src = "ls180.v:975.5-975.17" *)
  reg gpio1_out_re;
  (* src = "ls180.v:974.11-974.28" *)
  reg [7:0] gpio1_out_storage;
  (* src = "ls180.v:976.11-976.28" *)
  reg [7:0] gpio1_pads_gpio1i;
  (* src = "ls180.v:977.11-977.28" *)
  reg [7:0] gpio1_pads_gpio1o;
  (* src = "ls180.v:978.11-978.29" *)
  reg [7:0] gpio1_pads_gpio1oe;
  (* src = "ls180.v:972.11-972.23" *)
  reg [7:0] gpio1_status;
  (* src = "ls180.v:973.6-973.14" *)
  wire gpio1_we;
  (* src = "ls180.v:15.20-15.26" *)
  input [15:0] gpio_i;
  (* src = "ls180.v:16.21-16.27" *)
  output [15:0] gpio_o;
  (* src = "ls180.v:17.21-17.28" *)
  output [15:0] gpio_oe;
  (* src = "ls180.v:983.6-983.12" *)
  wire i2c_oe;
  (* src = "ls180.v:986.5-986.11" *)
  reg i2c_re;
  (* src = "ls180.v:7.14-7.21" *)
  output i2c_scl;
  (* src = "ls180.v:982.6-982.15" *)
  wire i2c_scl_1;
  (* src = "ls180.v:984.6-984.14" *)
  wire i2c_sda0;
  (* src = "ls180.v:987.6-987.14" *)
  wire i2c_sda1;
  (* src = "ls180.v:8.13-8.22" *)
  input i2c_sda_i;
  (* src = "ls180.v:9.14-9.23" *)
  output i2c_sda_o;
  (* src = "ls180.v:10.14-10.24" *)
  output i2c_sda_oe;
  (* src = "ls180.v:988.6-988.16" *)
  wire i2c_status;
  (* src = "ls180.v:985.11-985.22" *)
  reg [2:0] i2c_storage;
  (* src = "ls180.v:989.6-989.12" *)
  wire i2c_we;
  (* src = "ls180.v:230.5-230.12" *)
  reg int_rst;
  (* src = "ls180.v:851.6-851.9" *)
  wire irq;
  (* src = "ls180.v:36.13-36.21" *)
  input jtag_tck;
  (* src = "ls180.v:37.13-37.21" *)
  input jtag_tdi;
  (* src = "ls180.v:38.14-38.22" *)
  output jtag_tdo;
  (* src = "ls180.v:35.13-35.21" *)
  input jtag_tms;
  (* src = "ls180.v:181.12-181.27" *)
  wire [6:0] libresocsim_adr;
  (* src = "ls180.v:49.6-49.27" *)
  wire libresocsim_bus_error;
  (* src = "ls180.v:50.12-50.34" *)
  reg [31:0] libresocsim_bus_errors;
  (* src = "ls180.v:46.13-46.42" *)
  wire [31:0] libresocsim_bus_errors_status;
  (* src = "ls180.v:47.6-47.31" *)
  wire libresocsim_bus_errors_we;
  (* src = "ls180.v:152.5-152.35" *)
  reg libresocsim_converter0_counter;
  (* src = "ls180.v:992.5-992.70" *)
  reg libresocsim_converter0_counter_subfragments_converter0_next_value;
  (* src = "ls180.v:993.5-993.73" *)
  reg libresocsim_converter0_counter_subfragments_converter0_next_value_ce;
  (* src = "ls180.v:154.12-154.40" *)
  reg [63:0] libresocsim_converter0_dat_r;
  (* src = "ls180.v:153.6-153.34" *)
  wire libresocsim_converter0_reset;
  (* src = "ls180.v:151.5-151.32" *)
  reg libresocsim_converter0_skip;
  (* src = "ls180.v:167.5-167.35" *)
  reg libresocsim_converter1_counter;
  (* src = "ls180.v:996.5-996.70" *)
  reg libresocsim_converter1_counter_subfragments_converter1_next_value;
  (* src = "ls180.v:997.5-997.73" *)
  reg libresocsim_converter1_counter_subfragments_converter1_next_value_ce;
  (* src = "ls180.v:169.12-169.40" *)
  reg [63:0] libresocsim_converter1_dat_r;
  (* src = "ls180.v:168.6-168.34" *)
  wire libresocsim_converter1_reset;
  (* src = "ls180.v:166.5-166.32" *)
  reg libresocsim_converter1_skip;
  (* src = "ls180.v:1068.12-1068.29" *)
  reg [19:0] libresocsim_count;
  (* src = "ls180.v:1309.13-1309.45" *)
  wire [13:0] libresocsim_csr_interconnect_adr;
  (* src = "ls180.v:1312.12-1312.46" *)
  wire [7:0] libresocsim_csr_interconnect_dat_r;
  (* src = "ls180.v:1311.12-1311.46" *)
  wire [7:0] libresocsim_csr_interconnect_dat_w;
  (* src = "ls180.v:1310.6-1310.37" *)
  wire libresocsim_csr_interconnect_we;
  (* src = "ls180.v:1106.12-1106.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors0_r;
  (* src = "ls180.v:1105.6-1105.41" *)
  wire libresocsim_csrbank0_bus_errors0_re;
  (* src = "ls180.v:1108.12-1108.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors0_w;
  (* src = "ls180.v:1107.6-1107.41" *)
  wire libresocsim_csrbank0_bus_errors0_we;
  (* src = "ls180.v:1102.12-1102.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors1_r;
  (* src = "ls180.v:1101.6-1101.41" *)
  wire libresocsim_csrbank0_bus_errors1_re;
  (* src = "ls180.v:1104.12-1104.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors1_w;
  (* src = "ls180.v:1103.6-1103.41" *)
  wire libresocsim_csrbank0_bus_errors1_we;
  (* src = "ls180.v:1098.12-1098.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors2_r;
  (* src = "ls180.v:1097.6-1097.41" *)
  wire libresocsim_csrbank0_bus_errors2_re;
  (* src = "ls180.v:1100.12-1100.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors2_w;
  (* src = "ls180.v:1099.6-1099.41" *)
  wire libresocsim_csrbank0_bus_errors2_we;
  (* src = "ls180.v:1094.12-1094.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors3_r;
  (* src = "ls180.v:1093.6-1093.41" *)
  wire libresocsim_csrbank0_bus_errors3_re;
  (* src = "ls180.v:1096.12-1096.46" *)
  wire [7:0] libresocsim_csrbank0_bus_errors3_w;
  (* src = "ls180.v:1095.6-1095.41" *)
  wire libresocsim_csrbank0_bus_errors3_we;
  (* src = "ls180.v:1074.6-1074.35" *)
  wire libresocsim_csrbank0_reset0_r;
  (* src = "ls180.v:1073.6-1073.36" *)
  wire libresocsim_csrbank0_reset0_re;
  (* src = "ls180.v:1076.6-1076.35" *)
  wire libresocsim_csrbank0_reset0_w;
  (* src = "ls180.v:1075.6-1075.36" *)
  wire libresocsim_csrbank0_reset0_we;
  (* src = "ls180.v:1090.12-1090.43" *)
  wire [7:0] libresocsim_csrbank0_scratch0_r;
  (* src = "ls180.v:1089.6-1089.38" *)
  wire libresocsim_csrbank0_scratch0_re;
  (* src = "ls180.v:1092.12-1092.43" *)
  wire [7:0] libresocsim_csrbank0_scratch0_w;
  (* src = "ls180.v:1091.6-1091.38" *)
  wire libresocsim_csrbank0_scratch0_we;
  (* src = "ls180.v:1086.12-1086.43" *)
  wire [7:0] libresocsim_csrbank0_scratch1_r;
  (* src = "ls180.v:1085.6-1085.38" *)
  wire libresocsim_csrbank0_scratch1_re;
  (* src = "ls180.v:1088.12-1088.43" *)
  wire [7:0] libresocsim_csrbank0_scratch1_w;
  (* src = "ls180.v:1087.6-1087.38" *)
  wire libresocsim_csrbank0_scratch1_we;
  (* src = "ls180.v:1082.12-1082.43" *)
  wire [7:0] libresocsim_csrbank0_scratch2_r;
  (* src = "ls180.v:1081.6-1081.38" *)
  wire libresocsim_csrbank0_scratch2_re;
  (* src = "ls180.v:1084.12-1084.43" *)
  wire [7:0] libresocsim_csrbank0_scratch2_w;
  (* src = "ls180.v:1083.6-1083.38" *)
  wire libresocsim_csrbank0_scratch2_we;
  (* src = "ls180.v:1078.12-1078.43" *)
  wire [7:0] libresocsim_csrbank0_scratch3_r;
  (* src = "ls180.v:1077.6-1077.38" *)
  wire libresocsim_csrbank0_scratch3_re;
  (* src = "ls180.v:1080.12-1080.43" *)
  wire [7:0] libresocsim_csrbank0_scratch3_w;
  (* src = "ls180.v:1079.6-1079.38" *)
  wire libresocsim_csrbank0_scratch3_we;
  (* src = "ls180.v:1109.6-1109.30" *)
  wire libresocsim_csrbank0_sel;
  (* src = "ls180.v:1119.12-1119.37" *)
  wire [7:0] libresocsim_csrbank1_in_r;
  (* src = "ls180.v:1118.6-1118.32" *)
  wire libresocsim_csrbank1_in_re;
  (* src = "ls180.v:1121.12-1121.37" *)
  wire [7:0] libresocsim_csrbank1_in_w;
  (* src = "ls180.v:1120.6-1120.32" *)
  wire libresocsim_csrbank1_in_we;
  (* src = "ls180.v:1115.12-1115.38" *)
  wire [7:0] libresocsim_csrbank1_oe0_r;
  (* src = "ls180.v:1114.6-1114.33" *)
  wire libresocsim_csrbank1_oe0_re;
  (* src = "ls180.v:1117.12-1117.38" *)
  wire [7:0] libresocsim_csrbank1_oe0_w;
  (* src = "ls180.v:1116.6-1116.33" *)
  wire libresocsim_csrbank1_oe0_we;
  (* src = "ls180.v:1123.12-1123.39" *)
  wire [7:0] libresocsim_csrbank1_out0_r;
  (* src = "ls180.v:1122.6-1122.34" *)
  wire libresocsim_csrbank1_out0_re;
  (* src = "ls180.v:1125.12-1125.39" *)
  wire [7:0] libresocsim_csrbank1_out0_w;
  (* src = "ls180.v:1124.6-1124.34" *)
  wire libresocsim_csrbank1_out0_we;
  (* src = "ls180.v:1126.6-1126.30" *)
  wire libresocsim_csrbank1_sel;
  (* src = "ls180.v:1136.12-1136.37" *)
  wire [7:0] libresocsim_csrbank2_in_r;
  (* src = "ls180.v:1135.6-1135.32" *)
  wire libresocsim_csrbank2_in_re;
  (* src = "ls180.v:1138.12-1138.37" *)
  wire [7:0] libresocsim_csrbank2_in_w;
  (* src = "ls180.v:1137.6-1137.32" *)
  wire libresocsim_csrbank2_in_we;
  (* src = "ls180.v:1132.12-1132.38" *)
  wire [7:0] libresocsim_csrbank2_oe0_r;
  (* src = "ls180.v:1131.6-1131.33" *)
  wire libresocsim_csrbank2_oe0_re;
  (* src = "ls180.v:1134.12-1134.38" *)
  wire [7:0] libresocsim_csrbank2_oe0_w;
  (* src = "ls180.v:1133.6-1133.33" *)
  wire libresocsim_csrbank2_oe0_we;
  (* src = "ls180.v:1140.12-1140.39" *)
  wire [7:0] libresocsim_csrbank2_out0_r;
  (* src = "ls180.v:1139.6-1139.34" *)
  wire libresocsim_csrbank2_out0_re;
  (* src = "ls180.v:1142.12-1142.39" *)
  wire [7:0] libresocsim_csrbank2_out0_w;
  (* src = "ls180.v:1141.6-1141.34" *)
  wire libresocsim_csrbank2_out0_we;
  (* src = "ls180.v:1143.6-1143.30" *)
  wire libresocsim_csrbank2_sel;
  (* src = "ls180.v:1153.6-1153.30" *)
  wire libresocsim_csrbank3_r_r;
  (* src = "ls180.v:1152.6-1152.31" *)
  wire libresocsim_csrbank3_r_re;
  (* src = "ls180.v:1155.6-1155.30" *)
  wire libresocsim_csrbank3_r_w;
  (* src = "ls180.v:1154.6-1154.31" *)
  wire libresocsim_csrbank3_r_we;
  (* src = "ls180.v:1156.6-1156.30" *)
  wire libresocsim_csrbank3_sel;
  (* src = "ls180.v:1149.12-1149.37" *)
  wire [2:0] libresocsim_csrbank3_w0_r;
  (* src = "ls180.v:1148.6-1148.32" *)
  wire libresocsim_csrbank3_w0_re;
  (* src = "ls180.v:1151.12-1151.37" *)
  wire [2:0] libresocsim_csrbank3_w0_w;
  (* src = "ls180.v:1150.6-1150.32" *)
  wire libresocsim_csrbank3_w0_we;
  (* src = "ls180.v:1162.12-1162.48" *)
  wire [3:0] libresocsim_csrbank4_dfii_control0_r;
  (* src = "ls180.v:1161.6-1161.43" *)
  wire libresocsim_csrbank4_dfii_control0_re;
  (* src = "ls180.v:1164.12-1164.48" *)
  wire [3:0] libresocsim_csrbank4_dfii_control0_w;
  (* src = "ls180.v:1163.6-1163.43" *)
  wire libresocsim_csrbank4_dfii_control0_we;
  (* src = "ls180.v:1174.12-1174.52" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_r;
  (* src = "ls180.v:1173.6-1173.47" *)
  wire libresocsim_csrbank4_dfii_pi0_address0_re;
  (* src = "ls180.v:1176.12-1176.52" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_address0_w;
  (* src = "ls180.v:1175.6-1175.47" *)
  wire libresocsim_csrbank4_dfii_pi0_address0_we;
  (* src = "ls180.v:1170.12-1170.52" *)
  wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_r;
  (* src = "ls180.v:1169.6-1169.47" *)
  wire libresocsim_csrbank4_dfii_pi0_address1_re;
  (* src = "ls180.v:1172.12-1172.52" *)
  wire [4:0] libresocsim_csrbank4_dfii_pi0_address1_w;
  (* src = "ls180.v:1171.6-1171.47" *)
  wire libresocsim_csrbank4_dfii_pi0_address1_we;
  (* src = "ls180.v:1178.12-1178.53" *)
  wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_r;
  (* src = "ls180.v:1177.6-1177.48" *)
  wire libresocsim_csrbank4_dfii_pi0_baddress0_re;
  (* src = "ls180.v:1180.12-1180.53" *)
  wire [1:0] libresocsim_csrbank4_dfii_pi0_baddress0_w;
  (* src = "ls180.v:1179.6-1179.48" *)
  wire libresocsim_csrbank4_dfii_pi0_baddress0_we;
  (* src = "ls180.v:1166.12-1166.52" *)
  wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_r;
  (* src = "ls180.v:1165.6-1165.47" *)
  wire libresocsim_csrbank4_dfii_pi0_command0_re;
  (* src = "ls180.v:1168.12-1168.52" *)
  wire [5:0] libresocsim_csrbank4_dfii_pi0_command0_w;
  (* src = "ls180.v:1167.6-1167.47" *)
  wire libresocsim_csrbank4_dfii_pi0_command0_we;
  (* src = "ls180.v:1194.12-1194.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_r;
  (* src = "ls180.v:1193.6-1193.46" *)
  wire libresocsim_csrbank4_dfii_pi0_rddata0_re;
  (* src = "ls180.v:1196.12-1196.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata0_w;
  (* src = "ls180.v:1195.6-1195.46" *)
  wire libresocsim_csrbank4_dfii_pi0_rddata0_we;
  (* src = "ls180.v:1190.12-1190.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_r;
  (* src = "ls180.v:1189.6-1189.46" *)
  wire libresocsim_csrbank4_dfii_pi0_rddata1_re;
  (* src = "ls180.v:1192.12-1192.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_rddata1_w;
  (* src = "ls180.v:1191.6-1191.46" *)
  wire libresocsim_csrbank4_dfii_pi0_rddata1_we;
  (* src = "ls180.v:1186.12-1186.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_r;
  (* src = "ls180.v:1185.6-1185.46" *)
  wire libresocsim_csrbank4_dfii_pi0_wrdata0_re;
  (* src = "ls180.v:1188.12-1188.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata0_w;
  (* src = "ls180.v:1187.6-1187.46" *)
  wire libresocsim_csrbank4_dfii_pi0_wrdata0_we;
  (* src = "ls180.v:1182.12-1182.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_r;
  (* src = "ls180.v:1181.6-1181.46" *)
  wire libresocsim_csrbank4_dfii_pi0_wrdata1_re;
  (* src = "ls180.v:1184.12-1184.51" *)
  wire [7:0] libresocsim_csrbank4_dfii_pi0_wrdata1_w;
  (* src = "ls180.v:1183.6-1183.46" *)
  wire libresocsim_csrbank4_dfii_pi0_wrdata1_we;
  (* src = "ls180.v:1197.6-1197.30" *)
  wire libresocsim_csrbank4_sel;
  (* src = "ls180.v:1235.6-1235.32" *)
  wire libresocsim_csrbank5_en0_r;
  (* src = "ls180.v:1234.6-1234.33" *)
  wire libresocsim_csrbank5_en0_re;
  (* src = "ls180.v:1237.6-1237.32" *)
  wire libresocsim_csrbank5_en0_w;
  (* src = "ls180.v:1236.6-1236.33" *)
  wire libresocsim_csrbank5_en0_we;
  (* src = "ls180.v:1259.6-1259.39" *)
  wire libresocsim_csrbank5_ev_enable0_r;
  (* src = "ls180.v:1258.6-1258.40" *)
  wire libresocsim_csrbank5_ev_enable0_re;
  (* src = "ls180.v:1261.6-1261.39" *)
  wire libresocsim_csrbank5_ev_enable0_w;
  (* src = "ls180.v:1260.6-1260.40" *)
  wire libresocsim_csrbank5_ev_enable0_we;
  (* src = "ls180.v:1215.12-1215.40" *)
  wire [7:0] libresocsim_csrbank5_load0_r;
  (* src = "ls180.v:1214.6-1214.35" *)
  wire libresocsim_csrbank5_load0_re;
  (* src = "ls180.v:1217.12-1217.40" *)
  wire [7:0] libresocsim_csrbank5_load0_w;
  (* src = "ls180.v:1216.6-1216.35" *)
  wire libresocsim_csrbank5_load0_we;
  (* src = "ls180.v:1211.12-1211.40" *)
  wire [7:0] libresocsim_csrbank5_load1_r;
  (* src = "ls180.v:1210.6-1210.35" *)
  wire libresocsim_csrbank5_load1_re;
  (* src = "ls180.v:1213.12-1213.40" *)
  wire [7:0] libresocsim_csrbank5_load1_w;
  (* src = "ls180.v:1212.6-1212.35" *)
  wire libresocsim_csrbank5_load1_we;
  (* src = "ls180.v:1207.12-1207.40" *)
  wire [7:0] libresocsim_csrbank5_load2_r;
  (* src = "ls180.v:1206.6-1206.35" *)
  wire libresocsim_csrbank5_load2_re;
  (* src = "ls180.v:1209.12-1209.40" *)
  wire [7:0] libresocsim_csrbank5_load2_w;
  (* src = "ls180.v:1208.6-1208.35" *)
  wire libresocsim_csrbank5_load2_we;
  (* src = "ls180.v:1203.12-1203.40" *)
  wire [7:0] libresocsim_csrbank5_load3_r;
  (* src = "ls180.v:1202.6-1202.35" *)
  wire libresocsim_csrbank5_load3_re;
  (* src = "ls180.v:1205.12-1205.40" *)
  wire [7:0] libresocsim_csrbank5_load3_w;
  (* src = "ls180.v:1204.6-1204.35" *)
  wire libresocsim_csrbank5_load3_we;
  (* src = "ls180.v:1231.12-1231.42" *)
  wire [7:0] libresocsim_csrbank5_reload0_r;
  (* src = "ls180.v:1230.6-1230.37" *)
  wire libresocsim_csrbank5_reload0_re;
  (* src = "ls180.v:1233.12-1233.42" *)
  wire [7:0] libresocsim_csrbank5_reload0_w;
  (* src = "ls180.v:1232.6-1232.37" *)
  wire libresocsim_csrbank5_reload0_we;
  (* src = "ls180.v:1227.12-1227.42" *)
  wire [7:0] libresocsim_csrbank5_reload1_r;
  (* src = "ls180.v:1226.6-1226.37" *)
  wire libresocsim_csrbank5_reload1_re;
  (* src = "ls180.v:1229.12-1229.42" *)
  wire [7:0] libresocsim_csrbank5_reload1_w;
  (* src = "ls180.v:1228.6-1228.37" *)
  wire libresocsim_csrbank5_reload1_we;
  (* src = "ls180.v:1223.12-1223.42" *)
  wire [7:0] libresocsim_csrbank5_reload2_r;
  (* src = "ls180.v:1222.6-1222.37" *)
  wire libresocsim_csrbank5_reload2_re;
  (* src = "ls180.v:1225.12-1225.42" *)
  wire [7:0] libresocsim_csrbank5_reload2_w;
  (* src = "ls180.v:1224.6-1224.37" *)
  wire libresocsim_csrbank5_reload2_we;
  (* src = "ls180.v:1219.12-1219.42" *)
  wire [7:0] libresocsim_csrbank5_reload3_r;
  (* src = "ls180.v:1218.6-1218.37" *)
  wire libresocsim_csrbank5_reload3_re;
  (* src = "ls180.v:1221.12-1221.42" *)
  wire [7:0] libresocsim_csrbank5_reload3_w;
  (* src = "ls180.v:1220.6-1220.37" *)
  wire libresocsim_csrbank5_reload3_we;
  (* src = "ls180.v:1262.6-1262.30" *)
  wire libresocsim_csrbank5_sel;
  (* src = "ls180.v:1239.6-1239.42" *)
  wire libresocsim_csrbank5_update_value0_r;
  (* src = "ls180.v:1238.6-1238.43" *)
  wire libresocsim_csrbank5_update_value0_re;
  (* src = "ls180.v:1241.6-1241.42" *)
  wire libresocsim_csrbank5_update_value0_w;
  (* src = "ls180.v:1240.6-1240.43" *)
  wire libresocsim_csrbank5_update_value0_we;
  (* src = "ls180.v:1255.12-1255.41" *)
  wire [7:0] libresocsim_csrbank5_value0_r;
  (* src = "ls180.v:1254.6-1254.36" *)
  wire libresocsim_csrbank5_value0_re;
  (* src = "ls180.v:1257.12-1257.41" *)
  wire [7:0] libresocsim_csrbank5_value0_w;
  (* src = "ls180.v:1256.6-1256.36" *)
  wire libresocsim_csrbank5_value0_we;
  (* src = "ls180.v:1251.12-1251.41" *)
  wire [7:0] libresocsim_csrbank5_value1_r;
  (* src = "ls180.v:1250.6-1250.36" *)
  wire libresocsim_csrbank5_value1_re;
  (* src = "ls180.v:1253.12-1253.41" *)
  wire [7:0] libresocsim_csrbank5_value1_w;
  (* src = "ls180.v:1252.6-1252.36" *)
  wire libresocsim_csrbank5_value1_we;
  (* src = "ls180.v:1247.12-1247.41" *)
  wire [7:0] libresocsim_csrbank5_value2_r;
  (* src = "ls180.v:1246.6-1246.36" *)
  wire libresocsim_csrbank5_value2_re;
  (* src = "ls180.v:1249.12-1249.41" *)
  wire [7:0] libresocsim_csrbank5_value2_w;
  (* src = "ls180.v:1248.6-1248.36" *)
  wire libresocsim_csrbank5_value2_we;
  (* src = "ls180.v:1243.12-1243.41" *)
  wire [7:0] libresocsim_csrbank5_value3_r;
  (* src = "ls180.v:1242.6-1242.36" *)
  wire libresocsim_csrbank5_value3_re;
  (* src = "ls180.v:1245.12-1245.41" *)
  wire [7:0] libresocsim_csrbank5_value3_w;
  (* src = "ls180.v:1244.6-1244.36" *)
  wire libresocsim_csrbank5_value3_we;
  (* src = "ls180.v:1276.12-1276.45" *)
  wire [1:0] libresocsim_csrbank6_ev_enable0_r;
  (* src = "ls180.v:1275.6-1275.40" *)
  wire libresocsim_csrbank6_ev_enable0_re;
  (* src = "ls180.v:1278.12-1278.45" *)
  wire [1:0] libresocsim_csrbank6_ev_enable0_w;
  (* src = "ls180.v:1277.6-1277.40" *)
  wire libresocsim_csrbank6_ev_enable0_we;
  (* src = "ls180.v:1272.6-1272.36" *)
  wire libresocsim_csrbank6_rxempty_r;
  (* src = "ls180.v:1271.6-1271.37" *)
  wire libresocsim_csrbank6_rxempty_re;
  (* src = "ls180.v:1274.6-1274.36" *)
  wire libresocsim_csrbank6_rxempty_w;
  (* src = "ls180.v:1273.6-1273.37" *)
  wire libresocsim_csrbank6_rxempty_we;
  (* src = "ls180.v:1284.6-1284.35" *)
  wire libresocsim_csrbank6_rxfull_r;
  (* src = "ls180.v:1283.6-1283.36" *)
  wire libresocsim_csrbank6_rxfull_re;
  (* src = "ls180.v:1286.6-1286.35" *)
  wire libresocsim_csrbank6_rxfull_w;
  (* src = "ls180.v:1285.6-1285.36" *)
  wire libresocsim_csrbank6_rxfull_we;
  (* src = "ls180.v:1287.6-1287.30" *)
  wire libresocsim_csrbank6_sel;
  (* src = "ls180.v:1280.6-1280.36" *)
  wire libresocsim_csrbank6_txempty_r;
  (* src = "ls180.v:1279.6-1279.37" *)
  wire libresocsim_csrbank6_txempty_re;
  (* src = "ls180.v:1282.6-1282.36" *)
  wire libresocsim_csrbank6_txempty_w;
  (* src = "ls180.v:1281.6-1281.37" *)
  wire libresocsim_csrbank6_txempty_we;
  (* src = "ls180.v:1268.6-1268.35" *)
  wire libresocsim_csrbank6_txfull_r;
  (* src = "ls180.v:1267.6-1267.36" *)
  wire libresocsim_csrbank6_txfull_re;
  (* src = "ls180.v:1270.6-1270.35" *)
  wire libresocsim_csrbank6_txfull_w;
  (* src = "ls180.v:1269.6-1269.36" *)
  wire libresocsim_csrbank6_txfull_we;
  (* src = "ls180.v:1308.6-1308.30" *)
  wire libresocsim_csrbank7_sel;
  (* src = "ls180.v:1305.12-1305.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word0_r;
  (* src = "ls180.v:1304.6-1304.42" *)
  wire libresocsim_csrbank7_tuning_word0_re;
  (* src = "ls180.v:1307.12-1307.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word0_w;
  (* src = "ls180.v:1306.6-1306.42" *)
  wire libresocsim_csrbank7_tuning_word0_we;
  (* src = "ls180.v:1301.12-1301.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word1_r;
  (* src = "ls180.v:1300.6-1300.42" *)
  wire libresocsim_csrbank7_tuning_word1_re;
  (* src = "ls180.v:1303.12-1303.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word1_w;
  (* src = "ls180.v:1302.6-1302.42" *)
  wire libresocsim_csrbank7_tuning_word1_we;
  (* src = "ls180.v:1297.12-1297.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word2_r;
  (* src = "ls180.v:1296.6-1296.42" *)
  wire libresocsim_csrbank7_tuning_word2_re;
  (* src = "ls180.v:1299.12-1299.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word2_w;
  (* src = "ls180.v:1298.6-1298.42" *)
  wire libresocsim_csrbank7_tuning_word2_we;
  (* src = "ls180.v:1293.12-1293.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word3_r;
  (* src = "ls180.v:1292.6-1292.42" *)
  wire libresocsim_csrbank7_tuning_word3_re;
  (* src = "ls180.v:1295.12-1295.47" *)
  wire [7:0] libresocsim_csrbank7_tuning_word3_w;
  (* src = "ls180.v:1294.6-1294.42" *)
  wire libresocsim_csrbank7_tuning_word3_we;
  (* src = "ls180.v:182.13-182.30" *)
  wire [31:0] libresocsim_dat_r;
  (* src = "ls180.v:184.13-184.30" *)
  wire [31:0] libresocsim_dat_w;
  (* src = "ls180.v:1067.6-1067.22" *)
  wire libresocsim_done;
  (* src = "ls180.v:190.5-190.22" *)
  reg libresocsim_en_re;
  (* src = "ls180.v:189.5-189.27" *)
  reg libresocsim_en_storage;
  (* src = "ls180.v:1065.5-1065.22" *)
  reg libresocsim_error;
  (* src = "ls180.v:206.6-206.40" *)
  wire libresocsim_eventmanager_pending_r;
  (* src = "ls180.v:205.6-205.41" *)
  wire libresocsim_eventmanager_pending_re;
  (* src = "ls180.v:208.6-208.40" *)
  wire libresocsim_eventmanager_pending_w;
  (* src = "ls180.v:207.6-207.41" *)
  wire libresocsim_eventmanager_pending_we;
  (* src = "ls180.v:210.5-210.32" *)
  reg libresocsim_eventmanager_re;
  (* src = "ls180.v:202.6-202.39" *)
  wire libresocsim_eventmanager_status_r;
  (* src = "ls180.v:201.6-201.40" *)
  wire libresocsim_eventmanager_status_re;
  (* src = "ls180.v:204.6-204.39" *)
  wire libresocsim_eventmanager_status_w;
  (* src = "ls180.v:203.6-203.40" *)
  wire libresocsim_eventmanager_status_we;
  (* src = "ls180.v:209.5-209.37" *)
  reg libresocsim_eventmanager_storage;
  (* src = "ls180.v:1062.11-1062.28" *)
  reg [1:0] libresocsim_grant;
  (* src = "ls180.v:1069.13-1069.48" *)
  wire [13:0] libresocsim_interface0_bank_bus_adr;
  (* src = "ls180.v:1072.11-1072.48" *)
  reg [7:0] libresocsim_interface0_bank_bus_dat_r;
  (* src = "ls180.v:1071.12-1071.49" *)
  wire [7:0] libresocsim_interface0_bank_bus_dat_w;
  (* src = "ls180.v:1070.6-1070.40" *)
  wire libresocsim_interface0_bank_bus_we;
  (* src = "ls180.v:146.6-146.52" *)
  wire libresocsim_interface0_converted_interface_ack;
  (* src = "ls180.v:140.12-140.58" *)
  reg [29:0] libresocsim_interface0_converted_interface_adr;
  (* src = "ls180.v:149.11-149.57" *)
  reg [1:0] libresocsim_interface0_converted_interface_bte;
  (* src = "ls180.v:148.11-148.57" *)
  reg [2:0] libresocsim_interface0_converted_interface_cti;
  (* src = "ls180.v:144.5-144.51" *)
  reg libresocsim_interface0_converted_interface_cyc;
  (* src = "ls180.v:142.13-142.61" *)
  wire [31:0] libresocsim_interface0_converted_interface_dat_r;
  (* src = "ls180.v:141.12-141.60" *)
  reg [31:0] libresocsim_interface0_converted_interface_dat_w;
  (* src = "ls180.v:150.6-150.52" *)
  wire libresocsim_interface0_converted_interface_err;
  (* src = "ls180.v:143.11-143.57" *)
  reg [3:0] libresocsim_interface0_converted_interface_sel;
  (* src = "ls180.v:145.5-145.51" *)
  reg libresocsim_interface0_converted_interface_stb;
  (* src = "ls180.v:147.5-147.50" *)
  reg libresocsim_interface0_converted_interface_we;
  (* src = "ls180.v:1110.13-1110.48" *)
  wire [13:0] libresocsim_interface1_bank_bus_adr;
  (* src = "ls180.v:1113.11-1113.48" *)
  reg [7:0] libresocsim_interface1_bank_bus_dat_r;
  (* src = "ls180.v:1112.12-1112.49" *)
  wire [7:0] libresocsim_interface1_bank_bus_dat_w;
  (* src = "ls180.v:1111.6-1111.40" *)
  wire libresocsim_interface1_bank_bus_we;
  (* src = "ls180.v:161.6-161.52" *)
  wire libresocsim_interface1_converted_interface_ack;
  (* src = "ls180.v:155.12-155.58" *)
  reg [29:0] libresocsim_interface1_converted_interface_adr;
  (* src = "ls180.v:164.11-164.57" *)
  reg [1:0] libresocsim_interface1_converted_interface_bte;
  (* src = "ls180.v:163.11-163.57" *)
  reg [2:0] libresocsim_interface1_converted_interface_cti;
  (* src = "ls180.v:159.5-159.51" *)
  reg libresocsim_interface1_converted_interface_cyc;
  (* src = "ls180.v:157.13-157.61" *)
  wire [31:0] libresocsim_interface1_converted_interface_dat_r;
  (* src = "ls180.v:156.12-156.60" *)
  reg [31:0] libresocsim_interface1_converted_interface_dat_w;
  (* src = "ls180.v:165.6-165.52" *)
  wire libresocsim_interface1_converted_interface_err;
  (* src = "ls180.v:158.11-158.57" *)
  reg [3:0] libresocsim_interface1_converted_interface_sel;
  (* src = "ls180.v:160.5-160.51" *)
  reg libresocsim_interface1_converted_interface_stb;
  (* src = "ls180.v:162.5-162.50" *)
  reg libresocsim_interface1_converted_interface_we;
  (* src = "ls180.v:1127.13-1127.48" *)
  wire [13:0] libresocsim_interface2_bank_bus_adr;
  (* src = "ls180.v:1130.11-1130.48" *)
  reg [7:0] libresocsim_interface2_bank_bus_dat_r;
  (* src = "ls180.v:1129.12-1129.49" *)
  wire [7:0] libresocsim_interface2_bank_bus_dat_w;
  (* src = "ls180.v:1128.6-1128.40" *)
  wire libresocsim_interface2_bank_bus_we;
  (* src = "ls180.v:1144.13-1144.48" *)
  wire [13:0] libresocsim_interface3_bank_bus_adr;
  (* src = "ls180.v:1147.11-1147.48" *)
  reg [7:0] libresocsim_interface3_bank_bus_dat_r;
  (* src = "ls180.v:1146.12-1146.49" *)
  wire [7:0] libresocsim_interface3_bank_bus_dat_w;
  (* src = "ls180.v:1145.6-1145.40" *)
  wire libresocsim_interface3_bank_bus_we;
  (* src = "ls180.v:1157.13-1157.48" *)
  wire [13:0] libresocsim_interface4_bank_bus_adr;
  (* src = "ls180.v:1160.11-1160.48" *)
  reg [7:0] libresocsim_interface4_bank_bus_dat_r;
  (* src = "ls180.v:1159.12-1159.49" *)
  wire [7:0] libresocsim_interface4_bank_bus_dat_w;
  (* src = "ls180.v:1158.6-1158.40" *)
  wire libresocsim_interface4_bank_bus_we;
  (* src = "ls180.v:1198.13-1198.48" *)
  wire [13:0] libresocsim_interface5_bank_bus_adr;
  (* src = "ls180.v:1201.11-1201.48" *)
  reg [7:0] libresocsim_interface5_bank_bus_dat_r;
  (* src = "ls180.v:1200.12-1200.49" *)
  wire [7:0] libresocsim_interface5_bank_bus_dat_w;
  (* src = "ls180.v:1199.6-1199.40" *)
  wire libresocsim_interface5_bank_bus_we;
  (* src = "ls180.v:1263.13-1263.48" *)
  wire [13:0] libresocsim_interface6_bank_bus_adr;
  (* src = "ls180.v:1266.11-1266.48" *)
  reg [7:0] libresocsim_interface6_bank_bus_dat_r;
  (* src = "ls180.v:1265.12-1265.49" *)
  wire [7:0] libresocsim_interface6_bank_bus_dat_w;
  (* src = "ls180.v:1264.6-1264.40" *)
  wire libresocsim_interface6_bank_bus_we;
  (* src = "ls180.v:1288.13-1288.48" *)
  wire [13:0] libresocsim_interface7_bank_bus_adr;
  (* src = "ls180.v:1291.11-1291.48" *)
  reg [7:0] libresocsim_interface7_bank_bus_dat_r;
  (* src = "ls180.v:1290.12-1290.49" *)
  wire [7:0] libresocsim_interface7_bank_bus_dat_w;
  (* src = "ls180.v:1289.6-1289.40" *)
  wire libresocsim_interface7_bank_bus_we;
  (* src = "ls180.v:195.6-195.21" *)
  wire libresocsim_irq;
  (* src = "ls180.v:108.12-108.33" *)
  reg [63:0] libresocsim_libresoc0;
  (* src = "ls180.v:109.6-109.27" *)
  wire libresocsim_libresoc1;
  (* src = "ls180.v:110.6-110.27" *)
  wire libresocsim_libresoc2;
  (* src = "ls180.v:111.13-111.34" *)
  wire [63:0] libresocsim_libresoc3;
  (* src = "ls180.v:125.6-125.51" *)
  wire libresocsim_libresoc_constraintmanager_eint_0;
  (* src = "ls180.v:126.6-126.51" *)
  wire libresocsim_libresoc_constraintmanager_eint_1;
  (* src = "ls180.v:127.6-127.51" *)
  wire libresocsim_libresoc_constraintmanager_eint_2;
  (* src = "ls180.v:122.13-122.58" *)
  wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i;
  (* src = "ls180.v:123.12-123.57" *)
  reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o;
  (* src = "ls180.v:124.12-124.58" *)
  reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe;
  (* src = "ls180.v:114.6-114.52" *)
  wire libresocsim_libresoc_constraintmanager_i2c_scl;
  (* src = "ls180.v:115.6-115.54" *)
  wire libresocsim_libresoc_constraintmanager_i2c_sda_i;
  (* src = "ls180.v:116.6-116.54" *)
  wire libresocsim_libresoc_constraintmanager_i2c_sda_o;
  (* src = "ls180.v:117.6-117.55" *)
  wire libresocsim_libresoc_constraintmanager_i2c_sda_oe;
  (* src = "ls180.v:128.12-128.58" *)
  reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a;
  (* src = "ls180.v:137.11-137.58" *)
  reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba;
  (* src = "ls180.v:134.5-134.55" *)
  reg libresocsim_libresoc_constraintmanager_sdram_cas_n;
  (* src = "ls180.v:136.5-136.53" *)
  reg libresocsim_libresoc_constraintmanager_sdram_cke;
  (* src = "ls180.v:139.5-139.55" *)
  reg libresocsim_libresoc_constraintmanager_sdram_clock;
  (* src = "ls180.v:135.5-135.54" *)
  reg libresocsim_libresoc_constraintmanager_sdram_cs_n;
  (* src = "ls180.v:138.11-138.58" *)
  reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm;
  (* src = "ls180.v:129.13-129.62" *)
  wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i;
  (* src = "ls180.v:130.12-130.61" *)
  reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o;
  (* src = "ls180.v:131.12-131.62" *)
  reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_oe;
  (* src = "ls180.v:133.5-133.55" *)
  reg libresocsim_libresoc_constraintmanager_sdram_ras_n;
  (* src = "ls180.v:132.5-132.54" *)
  reg libresocsim_libresoc_constraintmanager_sdram_we_n;
  (* src = "ls180.v:118.5-118.57" *)
  reg libresocsim_libresoc_constraintmanager_spimaster_clk;
  (* src = "ls180.v:120.5-120.58" *)
  reg libresocsim_libresoc_constraintmanager_spimaster_cs_n;
  (* src = "ls180.v:121.6-121.59" *)
  wire libresocsim_libresoc_constraintmanager_spimaster_miso;
  (* src = "ls180.v:119.5-119.58" *)
  reg libresocsim_libresoc_constraintmanager_spimaster_mosi;
  (* src = "ls180.v:113.5-113.51" *)
  reg libresocsim_libresoc_constraintmanager_uart_rx;
  (* src = "ls180.v:112.5-112.51" *)
  reg libresocsim_libresoc_constraintmanager_uart_tx;
  (* src = "ls180.v:59.5-59.34" *)
  reg libresocsim_libresoc_dbus_ack;
  (* src = "ls180.v:53.13-53.42" *)
  wire [28:0] libresocsim_libresoc_dbus_adr;
  (* src = "ls180.v:57.6-57.35" *)
  wire libresocsim_libresoc_dbus_cyc;
  (* src = "ls180.v:55.13-55.44" *)
  wire [63:0] libresocsim_libresoc_dbus_dat_r;
  (* src = "ls180.v:54.13-54.44" *)
  wire [63:0] libresocsim_libresoc_dbus_dat_w;
  (* src = "ls180.v:61.5-61.34" *)
  reg libresocsim_libresoc_dbus_err;
  (* src = "ls180.v:56.12-56.41" *)
  wire [7:0] libresocsim_libresoc_dbus_sel;
  (* src = "ls180.v:58.6-58.35" *)
  wire libresocsim_libresoc_dbus_stb;
  (* src = "ls180.v:60.6-60.34" *)
  wire libresocsim_libresoc_dbus_we;
  (* src = "ls180.v:68.5-68.34" *)
  reg libresocsim_libresoc_ibus_ack;
  (* src = "ls180.v:62.13-62.42" *)
  wire [28:0] libresocsim_libresoc_ibus_adr;
  (* src = "ls180.v:66.6-66.35" *)
  wire libresocsim_libresoc_ibus_cyc;
  (* src = "ls180.v:64.13-64.44" *)
  wire [63:0] libresocsim_libresoc_ibus_dat_r;
  (* src = "ls180.v:63.13-63.44" *)
  wire [63:0] libresocsim_libresoc_ibus_dat_w;
  (* src = "ls180.v:70.5-70.34" *)
  reg libresocsim_libresoc_ibus_err;
  (* src = "ls180.v:65.12-65.41" *)
  wire [7:0] libresocsim_libresoc_ibus_sel;
  (* src = "ls180.v:67.6-67.35" *)
  wire libresocsim_libresoc_ibus_stb;
  (* src = "ls180.v:69.6-69.34" *)
  wire libresocsim_libresoc_ibus_we;
  (* src = "ls180.v:52.12-52.42" *)
  reg [15:0] libresocsim_libresoc_interrupt;
  (* src = "ls180.v:104.6-104.35" *)
  wire libresocsim_libresoc_jtag_tck;
  (* src = "ls180.v:106.6-106.35" *)
  wire libresocsim_libresoc_jtag_tdi;
  (* src = "ls180.v:107.6-107.35" *)
  wire libresocsim_libresoc_jtag_tdo;
  (* src = "ls180.v:105.6-105.35" *)
  wire libresocsim_libresoc_jtag_tms;
  (* src = "ls180.v:99.6-99.38" *)
  wire libresocsim_libresoc_jtag_wb_ack;
  (* src = "ls180.v:93.13-93.45" *)
  wire [29:0] libresocsim_libresoc_jtag_wb_adr;
  (* src = "ls180.v:102.11-102.43" *)
  reg [1:0] libresocsim_libresoc_jtag_wb_bte;
  (* src = "ls180.v:101.11-101.43" *)
  reg [2:0] libresocsim_libresoc_jtag_wb_cti;
  (* src = "ls180.v:97.6-97.38" *)
  wire libresocsim_libresoc_jtag_wb_cyc;
  (* src = "ls180.v:95.13-95.47" *)
  wire [31:0] libresocsim_libresoc_jtag_wb_dat_r;
  (* src = "ls180.v:94.13-94.47" *)
  wire [31:0] libresocsim_libresoc_jtag_wb_dat_w;
  (* src = "ls180.v:103.6-103.38" *)
  wire libresocsim_libresoc_jtag_wb_err;
  (* src = "ls180.v:96.12-96.44" *)
  wire [3:0] libresocsim_libresoc_jtag_wb_sel;
  (* src = "ls180.v:98.6-98.38" *)
  wire libresocsim_libresoc_jtag_wb_stb;
  (* src = "ls180.v:100.6-100.37" *)
  wire libresocsim_libresoc_jtag_wb_we;
  (* src = "ls180.v:51.6-51.32" *)
  wire libresocsim_libresoc_reset;
  (* src = "ls180.v:77.6-77.39" *)
  wire libresocsim_libresoc_xics_icp_ack;
  (* src = "ls180.v:71.13-71.46" *)
  wire [29:0] libresocsim_libresoc_xics_icp_adr;
  (* src = "ls180.v:80.12-80.45" *)
  wire [1:0] libresocsim_libresoc_xics_icp_bte;
  (* src = "ls180.v:79.12-79.45" *)
  wire [2:0] libresocsim_libresoc_xics_icp_cti;
  (* src = "ls180.v:75.6-75.39" *)
  wire libresocsim_libresoc_xics_icp_cyc;
  (* src = "ls180.v:73.13-73.48" *)
  wire [31:0] libresocsim_libresoc_xics_icp_dat_r;
  (* src = "ls180.v:72.13-72.48" *)
  wire [31:0] libresocsim_libresoc_xics_icp_dat_w;
  (* src = "ls180.v:81.6-81.39" *)
  wire libresocsim_libresoc_xics_icp_err;
  (* src = "ls180.v:74.12-74.45" *)
  wire [3:0] libresocsim_libresoc_xics_icp_sel;
  (* src = "ls180.v:76.6-76.39" *)
  wire libresocsim_libresoc_xics_icp_stb;
  (* src = "ls180.v:78.6-78.38" *)
  wire libresocsim_libresoc_xics_icp_we;
  (* src = "ls180.v:88.6-88.39" *)
  wire libresocsim_libresoc_xics_ics_ack;
  (* src = "ls180.v:82.13-82.46" *)
  wire [29:0] libresocsim_libresoc_xics_ics_adr;
  (* src = "ls180.v:91.12-91.45" *)
  wire [1:0] libresocsim_libresoc_xics_ics_bte;
  (* src = "ls180.v:90.12-90.45" *)
  wire [2:0] libresocsim_libresoc_xics_ics_cti;
  (* src = "ls180.v:86.6-86.39" *)
  wire libresocsim_libresoc_xics_ics_cyc;
  (* src = "ls180.v:84.13-84.48" *)
  wire [31:0] libresocsim_libresoc_xics_ics_dat_r;
  (* src = "ls180.v:83.13-83.48" *)
  wire [31:0] libresocsim_libresoc_xics_ics_dat_w;
  (* src = "ls180.v:92.6-92.39" *)
  wire libresocsim_libresoc_xics_ics_err;
  (* src = "ls180.v:85.12-85.45" *)
  wire [3:0] libresocsim_libresoc_xics_ics_sel;
  (* src = "ls180.v:87.6-87.39" *)
  wire libresocsim_libresoc_xics_ics_stb;
  (* src = "ls180.v:89.6-89.38" *)
  wire libresocsim_libresoc_xics_ics_we;
  (* src = "ls180.v:1035.12-1035.39" *)
  reg [13:0] libresocsim_libresocsim_adr;
  (* src = "ls180.v:1317.12-1317.63" *)
  reg [13:0] libresocsim_libresocsim_adr_libresocsim_next_value1;
  (* src = "ls180.v:1318.5-1318.59" *)
  reg libresocsim_libresocsim_adr_libresocsim_next_value_ce1;
  (* src = "ls180.v:1038.12-1038.41" *)
  wire [7:0] libresocsim_libresocsim_dat_r;
  (* src = "ls180.v:1037.11-1037.40" *)
  reg [7:0] libresocsim_libresocsim_dat_w;
  (* src = "ls180.v:1315.11-1315.64" *)
  reg [7:0] libresocsim_libresocsim_dat_w_libresocsim_next_value0;
  (* src = "ls180.v:1316.5-1316.61" *)
  reg libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0;
  (* src = "ls180.v:1036.5-1036.31" *)
  reg libresocsim_libresocsim_we;
  (* src = "ls180.v:1319.5-1319.55" *)
  reg libresocsim_libresocsim_we_libresocsim_next_value2;
  (* src = "ls180.v:1320.5-1320.58" *)
  reg libresocsim_libresocsim_we_libresocsim_next_value_ce2;
  (* src = "ls180.v:1045.5-1045.41" *)
  reg libresocsim_libresocsim_wishbone_ack;
  (* src = "ls180.v:1039.13-1039.49" *)
  wire [29:0] libresocsim_libresocsim_wishbone_adr;
  (* src = "ls180.v:1048.12-1048.48" *)
  wire [1:0] libresocsim_libresocsim_wishbone_bte;
  (* src = "ls180.v:1047.12-1047.48" *)
  wire [2:0] libresocsim_libresocsim_wishbone_cti;
  (* src = "ls180.v:1043.6-1043.42" *)
  wire libresocsim_libresocsim_wishbone_cyc;
  (* src = "ls180.v:1041.12-1041.50" *)
  reg [31:0] libresocsim_libresocsim_wishbone_dat_r;
  (* src = "ls180.v:1040.13-1040.51" *)
  wire [31:0] libresocsim_libresocsim_wishbone_dat_w;
  (* src = "ls180.v:1049.5-1049.41" *)
  reg libresocsim_libresocsim_wishbone_err;
  (* src = "ls180.v:1042.12-1042.48" *)
  wire [3:0] libresocsim_libresocsim_wishbone_sel;
  (* src = "ls180.v:1044.6-1044.42" *)
  wire libresocsim_libresocsim_wishbone_stb;
  (* src = "ls180.v:1046.6-1046.41" *)
  wire libresocsim_libresocsim_wishbone_we;
  (* src = "ls180.v:186.5-186.24" *)
  reg libresocsim_load_re;
  (* src = "ls180.v:185.12-185.36" *)
  reg [31:0] libresocsim_load_storage;
  (* src = "ls180.v:1314.11-1314.33" *)
  reg [1:0] libresocsim_next_state;
  (* src = "ls180.v:176.5-176.28" *)
  reg libresocsim_ram_bus_ack;
  (* src = "ls180.v:170.13-170.36" *)
  wire [29:0] libresocsim_ram_bus_adr;
  (* src = "ls180.v:179.12-179.35" *)
  wire [1:0] libresocsim_ram_bus_bte;
  (* src = "ls180.v:178.12-178.35" *)
  wire [2:0] libresocsim_ram_bus_cti;
  (* src = "ls180.v:174.6-174.29" *)
  wire libresocsim_ram_bus_cyc;
  (* src = "ls180.v:172.13-172.38" *)
  wire [31:0] libresocsim_ram_bus_dat_r;
  (* src = "ls180.v:171.13-171.38" *)
  wire [31:0] libresocsim_ram_bus_dat_w;
  (* src = "ls180.v:180.5-180.28" *)
  reg libresocsim_ram_bus_err;
  (* src = "ls180.v:173.12-173.35" *)
  wire [3:0] libresocsim_ram_bus_sel;
  (* src = "ls180.v:175.6-175.29" *)
  wire libresocsim_ram_bus_stb;
  (* src = "ls180.v:177.6-177.28" *)
  wire libresocsim_ram_bus_we;
  (* src = "ls180.v:188.5-188.26" *)
  reg libresocsim_reload_re;
  (* src = "ls180.v:187.12-187.38" *)
  reg [31:0] libresocsim_reload_storage;
  (* src = "ls180.v:1061.12-1061.31" *)
  wire [2:0] libresocsim_request;
  (* src = "ls180.v:48.6-48.23" *)
  wire libresocsim_reset;
  (* src = "ls180.v:43.5-43.25" *)
  reg libresocsim_reset_re;
  (* src = "ls180.v:42.5-42.30" *)
  reg libresocsim_reset_storage;
  (* src = "ls180.v:45.5-45.27" *)
  reg libresocsim_scratch_re;
  (* src = "ls180.v:44.12-44.39" *)
  reg [31:0] libresocsim_scratch_storage;
  (* src = "ls180.v:1056.5-1056.27" *)
  reg libresocsim_shared_ack;
  (* src = "ls180.v:1050.13-1050.35" *)
  wire [29:0] libresocsim_shared_adr;
  (* src = "ls180.v:1059.12-1059.34" *)
  wire [1:0] libresocsim_shared_bte;
  (* src = "ls180.v:1058.12-1058.34" *)
  wire [2:0] libresocsim_shared_cti;
  (* src = "ls180.v:1054.6-1054.28" *)
  wire libresocsim_shared_cyc;
  (* src = "ls180.v:1052.12-1052.36" *)
  reg [31:0] libresocsim_shared_dat_r;
  (* src = "ls180.v:1051.13-1051.37" *)
  wire [31:0] libresocsim_shared_dat_w;
  (* src = "ls180.v:1060.6-1060.28" *)
  wire libresocsim_shared_err;
  (* src = "ls180.v:1053.12-1053.34" *)
  wire [3:0] libresocsim_shared_sel;
  (* src = "ls180.v:1055.6-1055.28" *)
  wire libresocsim_shared_stb;
  (* src = "ls180.v:1057.6-1057.27" *)
  wire libresocsim_shared_we;
  (* src = "ls180.v:1063.11-1063.32" *)
  reg [5:0] libresocsim_slave_sel;
  (* src = "ls180.v:1064.11-1064.34" *)
  reg [5:0] libresocsim_slave_sel_r;
  (* src = "ls180.v:1313.11-1313.28" *)
  reg [1:0] libresocsim_state;
  (* src = "ls180.v:192.5-192.32" *)
  reg libresocsim_update_value_re;
  (* src = "ls180.v:191.5-191.37" *)
  reg libresocsim_update_value_storage;
  (* src = "ls180.v:211.12-211.29" *)
  reg [31:0] libresocsim_value;
  (* src = "ls180.v:193.12-193.36" *)
  reg [31:0] libresocsim_value_status;
  (* src = "ls180.v:194.6-194.26" *)
  wire libresocsim_value_we;
  (* src = "ls180.v:1066.6-1066.22" *)
  wire libresocsim_wait;
  (* src = "ls180.v:183.11-183.25" *)
  reg [3:0] libresocsim_we;
  (* src = "ls180.v:199.5-199.27" *)
  reg libresocsim_zero_clear;
  (* src = "ls180.v:200.5-200.33" *)
  reg libresocsim_zero_old_trigger;
  (* src = "ls180.v:197.5-197.29" *)
  reg libresocsim_zero_pending;
  (* src = "ls180.v:196.6-196.29" *)
  wire libresocsim_zero_status;
  (* src = "ls180.v:198.6-198.30" *)
  wire libresocsim_zero_trigger;
  (* src = "ls180.v:808.6-808.21" *)
  wire litedram_wb_ack;
  (* src = "ls180.v:802.12-802.27" *)
  reg [29:0] litedram_wb_adr;
  (* src = "ls180.v:806.5-806.20" *)
  reg litedram_wb_cyc;
  (* src = "ls180.v:804.13-804.30" *)
  wire [15:0] litedram_wb_dat_r;
  (* src = "ls180.v:803.12-803.29" *)
  reg [15:0] litedram_wb_dat_w;
  (* src = "ls180.v:805.11-805.26" *)
  reg [1:0] litedram_wb_sel;
  (* src = "ls180.v:807.5-807.20" *)
  reg litedram_wb_stb;
  (* src = "ls180.v:809.5-809.19" *)
  reg litedram_wb_we;
  (* src = "ls180.v:5445.11-5445.17" *)
  reg [6:0] memadr;
  (* src = "ls180.v:5465.11-5465.19" *)
  reg [4:0] memadr_1;
  (* src = "ls180.v:5485.12-5485.18" *)
  reg [24:0] memdat;
  (* src = "ls180.v:5499.12-5499.20" *)
  reg [24:0] memdat_1;
  (* src = "ls180.v:5513.12-5513.20" *)
  reg [24:0] memdat_2;
  (* src = "ls180.v:5527.12-5527.20" *)
  reg [24:0] memdat_3;
  (* src = "ls180.v:5541.11-5541.19" *)
  reg [9:0] memdat_4;
  (* src = "ls180.v:5542.11-5542.19" *)
  reg [9:0] memdat_5;
  (* src = "ls180.v:5558.11-5558.19" *)
  reg [9:0] memdat_6;
  (* src = "ls180.v:5559.11-5559.19" *)
  reg [9:0] memdat_7;
  (* src = "ls180.v:39.20-39.22" *)
  input [39:0] nc;
  (* src = "ls180.v:980.13-980.17" *)
  wire [39:0] nc_1;
  (* src = "ls180.v:229.6-229.13" *)
  wire por_clk;
  (* src = "ls180.v:781.6-781.19" *)
  wire port_cmd_last;
  (* src = "ls180.v:783.13-783.34" *)
  wire [23:0] port_cmd_payload_addr;
  (* src = "ls180.v:782.6-782.25" *)
  wire port_cmd_payload_we;
  (* src = "ls180.v:780.6-780.20" *)
  wire port_cmd_ready;
  (* src = "ls180.v:779.6-779.20" *)
  wire port_cmd_valid;
  (* src = "ls180.v:778.6-778.16" *)
  wire port_flush;
  (* src = "ls180.v:790.13-790.36" *)
  wire [15:0] port_rdata_payload_data;
  (* src = "ls180.v:789.6-789.22" *)
  wire port_rdata_ready;
  (* src = "ls180.v:788.6-788.22" *)
  wire port_rdata_valid;
  (* src = "ls180.v:786.13-786.36" *)
  wire [15:0] port_wdata_payload_data;
  (* src = "ls180.v:787.12-787.33" *)
  wire [1:0] port_wdata_payload_we;
  (* src = "ls180.v:785.6-785.22" *)
  wire port_wdata_ready;
  (* src = "ls180.v:784.6-784.22" *)
  wire port_wdata_valid;
  (* src = "ls180.v:223.12-223.19" *)
  wire [4:0] ram_adr;
  (* src = "ls180.v:218.5-218.24" *)
  reg ram_bus_ram_bus_ack;
  (* src = "ls180.v:212.13-212.32" *)
  wire [29:0] ram_bus_ram_bus_adr;
  (* src = "ls180.v:221.12-221.31" *)
  wire [1:0] ram_bus_ram_bus_bte;
  (* src = "ls180.v:220.12-220.31" *)
  wire [2:0] ram_bus_ram_bus_cti;
  (* src = "ls180.v:216.6-216.25" *)
  wire ram_bus_ram_bus_cyc;
  (* src = "ls180.v:214.13-214.34" *)
  wire [31:0] ram_bus_ram_bus_dat_r;
  (* src = "ls180.v:213.13-213.34" *)
  wire [31:0] ram_bus_ram_bus_dat_w;
  (* src = "ls180.v:222.5-222.24" *)
  reg ram_bus_ram_bus_err;
  (* src = "ls180.v:215.12-215.31" *)
  wire [3:0] ram_bus_ram_bus_sel;
  (* src = "ls180.v:217.6-217.25" *)
  wire ram_bus_ram_bus_stb;
  (* src = "ls180.v:219.6-219.24" *)
  wire ram_bus_ram_bus_we;
  (* src = "ls180.v:224.13-224.22" *)
  wire [31:0] ram_dat_r;
  (* src = "ls180.v:226.13-226.22" *)
  wire [31:0] ram_dat_w;
  (* src = "ls180.v:225.11-225.17" *)
  reg [3:0] ram_we;
  (* src = "ls180.v:247.11-247.20" *)
  reg [2:0] rddata_en;
  (* no_retiming = "true" *)
  (* src = "ls180.v:1437.32-1437.37" *)
  reg regs0;
  (* no_retiming = "true" *)
  (* src = "ls180.v:1438.32-1438.37" *)
  reg regs1;
  (* src = "ls180.v:960.5-960.10" *)
  reg reset;
  (* src = "ls180.v:1321.5-1321.21" *)
  reg rhs_array_muxed0;
  (* src = "ls180.v:1322.12-1322.28" *)
  reg [12:0] rhs_array_muxed1;
  (* src = "ls180.v:1334.5-1334.22" *)
  reg rhs_array_muxed10;
  (* src = "ls180.v:1335.5-1335.22" *)
  reg rhs_array_muxed11;
  (* src = "ls180.v:1339.12-1339.29" *)
  reg [21:0] rhs_array_muxed12;
  (* src = "ls180.v:1340.5-1340.22" *)
  reg rhs_array_muxed13;
  (* src = "ls180.v:1341.5-1341.22" *)
  reg rhs_array_muxed14;
  (* src = "ls180.v:1342.12-1342.29" *)
  reg [21:0] rhs_array_muxed15;
  (* src = "ls180.v:1343.5-1343.22" *)
  reg rhs_array_muxed16;
  (* src = "ls180.v:1344.5-1344.22" *)
  reg rhs_array_muxed17;
  (* src = "ls180.v:1345.12-1345.29" *)
  reg [21:0] rhs_array_muxed18;
  (* src = "ls180.v:1346.5-1346.22" *)
  reg rhs_array_muxed19;
  (* src = "ls180.v:1323.11-1323.27" *)
  reg [1:0] rhs_array_muxed2;
  (* src = "ls180.v:1347.5-1347.22" *)
  reg rhs_array_muxed20;
  (* src = "ls180.v:1348.12-1348.29" *)
  reg [21:0] rhs_array_muxed21;
  (* src = "ls180.v:1349.5-1349.22" *)
  reg rhs_array_muxed22;
  (* src = "ls180.v:1350.5-1350.22" *)
  reg rhs_array_muxed23;
  (* src = "ls180.v:1351.12-1351.29" *)
  reg [29:0] rhs_array_muxed24;
  (* src = "ls180.v:1352.12-1352.29" *)
  reg [31:0] rhs_array_muxed25;
  (* src = "ls180.v:1353.11-1353.28" *)
  reg [3:0] rhs_array_muxed26;
  (* src = "ls180.v:1354.5-1354.22" *)
  reg rhs_array_muxed27;
  (* src = "ls180.v:1355.5-1355.22" *)
  reg rhs_array_muxed28;
  (* src = "ls180.v:1356.5-1356.22" *)
  reg rhs_array_muxed29;
  (* src = "ls180.v:1324.5-1324.21" *)
  reg rhs_array_muxed3;
  (* src = "ls180.v:1357.11-1357.28" *)
  reg [2:0] rhs_array_muxed30;
  (* src = "ls180.v:1358.11-1358.28" *)
  reg [1:0] rhs_array_muxed31;
  (* src = "ls180.v:1325.5-1325.21" *)
  reg rhs_array_muxed4;
  (* src = "ls180.v:1326.5-1326.21" *)
  reg rhs_array_muxed5;
  (* src = "ls180.v:1330.5-1330.21" *)
  reg rhs_array_muxed6;
  (* src = "ls180.v:1331.12-1331.28" *)
  reg [12:0] rhs_array_muxed7;
  (* src = "ls180.v:1332.11-1332.27" *)
  reg [1:0] rhs_array_muxed8;
  (* src = "ls180.v:1333.5-1333.21" *)
  reg rhs_array_muxed9;
  (* src = "ls180.v:860.5-860.13" *)
  reg rx_clear;
  (* src = "ls180.v:944.11-944.26" *)
  reg [3:0] rx_fifo_consume;
  (* src = "ls180.v:949.6-949.21" *)
  wire rx_fifo_do_read;
  (* src = "ls180.v:955.6-955.27" *)
  wire rx_fifo_fifo_in_first;
  (* src = "ls180.v:956.6-956.26" *)
  wire rx_fifo_fifo_in_last;
  (* src = "ls180.v:954.12-954.40" *)
  wire [7:0] rx_fifo_fifo_in_payload_data;
  (* src = "ls180.v:958.6-958.28" *)
  wire rx_fifo_fifo_out_first;
  (* src = "ls180.v:959.6-959.27" *)
  wire rx_fifo_fifo_out_last;
  (* src = "ls180.v:957.12-957.41" *)
  wire [7:0] rx_fifo_fifo_out_payload_data;
  (* src = "ls180.v:941.11-941.25" *)
  reg [4:0] rx_fifo_level0;
  (* src = "ls180.v:953.12-953.26" *)
  wire [4:0] rx_fifo_level1;
  (* src = "ls180.v:943.11-943.26" *)
  reg [3:0] rx_fifo_produce;
  (* src = "ls180.v:950.12-950.30" *)
  wire [3:0] rx_fifo_rdport_adr;
  (* src = "ls180.v:951.12-951.32" *)
  wire [9:0] rx_fifo_rdport_dat_r;
  (* src = "ls180.v:952.6-952.23" *)
  wire rx_fifo_rdport_re;
  (* src = "ls180.v:933.6-933.16" *)
  wire rx_fifo_re;
  (* src = "ls180.v:934.5-934.21" *)
  reg rx_fifo_readable;
  (* src = "ls180.v:942.5-942.20" *)
  reg rx_fifo_replace;
  (* src = "ls180.v:925.6-925.24" *)
  wire rx_fifo_sink_first;
  (* src = "ls180.v:926.6-926.23" *)
  wire rx_fifo_sink_last;
  (* src = "ls180.v:927.12-927.37" *)
  wire [7:0] rx_fifo_sink_payload_data;
  (* src = "ls180.v:924.6-924.24" *)
  wire rx_fifo_sink_ready;
  (* src = "ls180.v:923.6-923.24" *)
  wire rx_fifo_sink_valid;
  (* src = "ls180.v:930.6-930.26" *)
  wire rx_fifo_source_first;
  (* src = "ls180.v:931.6-931.25" *)
  wire rx_fifo_source_last;
  (* src = "ls180.v:932.12-932.39" *)
  wire [7:0] rx_fifo_source_payload_data;
  (* src = "ls180.v:929.6-929.26" *)
  wire rx_fifo_source_ready;
  (* src = "ls180.v:928.6-928.26" *)
  wire rx_fifo_source_valid;
  (* src = "ls180.v:939.12-939.32" *)
  wire [9:0] rx_fifo_syncfifo_din;
  (* src = "ls180.v:940.12-940.33" *)
  wire [9:0] rx_fifo_syncfifo_dout;
  (* src = "ls180.v:937.6-937.25" *)
  wire rx_fifo_syncfifo_re;
  (* src = "ls180.v:938.6-938.31" *)
  wire rx_fifo_syncfifo_readable;
  (* src = "ls180.v:935.6-935.25" *)
  wire rx_fifo_syncfifo_we;
  (* src = "ls180.v:936.6-936.31" *)
  wire rx_fifo_syncfifo_writable;
  (* src = "ls180.v:945.11-945.29" *)
  reg [3:0] rx_fifo_wrport_adr;
  (* src = "ls180.v:946.12-946.32" *)
  wire [9:0] rx_fifo_wrport_dat_r;
  (* src = "ls180.v:948.12-948.32" *)
  wire [9:0] rx_fifo_wrport_dat_w;
  (* src = "ls180.v:947.6-947.23" *)
  wire rx_fifo_wrport_we;
  (* src = "ls180.v:861.5-861.19" *)
  reg rx_old_trigger;
  (* src = "ls180.v:858.5-858.15" *)
  reg rx_pending;
  (* src = "ls180.v:857.6-857.15" *)
  wire rx_status;
  (* src = "ls180.v:859.6-859.16" *)
  wire rx_trigger;
  (* src = "ls180.v:849.6-849.20" *)
  wire rxempty_status;
  (* src = "ls180.v:850.6-850.16" *)
  wire rxempty_we;
  (* src = "ls180.v:874.6-874.19" *)
  wire rxfull_status;
  (* src = "ls180.v:875.6-875.15" *)
  wire rxfull_we;
  (* src = "ls180.v:844.12-844.18" *)
  wire [7:0] rxtx_r;
  (* src = "ls180.v:843.6-843.13" *)
  wire rxtx_re;
  (* src = "ls180.v:846.12-846.18" *)
  wire [7:0] rxtx_w;
  (* src = "ls180.v:845.6-845.13" *)
  wire rxtx_we;
  (* src = "ls180.v:21.21-21.28" *)
  output [12:0] sdram_a;
  (* src = "ls180.v:309.5-309.21" *)
  reg sdram_address_re;
  (* src = "ls180.v:308.12-308.33" *)
  reg [12:0] sdram_address_storage;
  (* src = "ls180.v:30.20-30.28" *)
  output [1:0] sdram_ba;
  (* src = "ls180.v:311.5-311.22" *)
  reg sdram_baddress_re;
  (* src = "ls180.v:310.11-310.33" *)
  reg [1:0] sdram_baddress_storage;
  (* src = "ls180.v:407.5-407.38" *)
  reg sdram_bankmachine0_auto_precharge;
  (* src = "ls180.v:429.11-429.58" *)
  reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_consume;
  (* src = "ls180.v:434.6-434.53" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_do_read;
  (* src = "ls180.v:439.6-439.59" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
  (* src = "ls180.v:440.6-440.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
  (* src = "ls180.v:438.13-438.73" *)
  wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
  (* src = "ls180.v:437.6-437.64" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
  (* src = "ls180.v:443.6-443.60" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
  (* src = "ls180.v:444.6-444.59" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
  (* src = "ls180.v:442.13-442.74" *)
  wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
  (* src = "ls180.v:441.6-441.65" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
  (* src = "ls180.v:426.11-426.56" *)
  reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_level;
  (* src = "ls180.v:428.11-428.58" *)
  reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_produce;
  (* src = "ls180.v:435.12-435.62" *)
  wire [2:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
  (* src = "ls180.v:436.13-436.65" *)
  wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
  (* src = "ls180.v:427.5-427.52" *)
  reg sdram_bankmachine0_cmd_buffer_lookahead_replace;
  (* src = "ls180.v:410.5-410.55" *)
  reg sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
  (* src = "ls180.v:411.5-411.54" *)
  reg sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
  (* src = "ls180.v:413.13-413.70" *)
  wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
  (* src = "ls180.v:412.6-412.61" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
  (* src = "ls180.v:409.6-409.56" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
  (* src = "ls180.v:408.6-408.56" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
  (* src = "ls180.v:416.6-416.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_source_first;
  (* src = "ls180.v:417.6-417.57" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_source_last;
  (* src = "ls180.v:419.13-419.72" *)
  wire [21:0] sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
  (* src = "ls180.v:418.6-418.63" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
  (* src = "ls180.v:415.6-415.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
  (* src = "ls180.v:414.6-414.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
  (* src = "ls180.v:424.13-424.66" *)
  wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
  (* src = "ls180.v:425.13-425.67" *)
  wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
  (* src = "ls180.v:422.6-422.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
  (* src = "ls180.v:423.6-423.64" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
  (* src = "ls180.v:420.6-420.58" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
  (* src = "ls180.v:421.6-421.64" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
  (* src = "ls180.v:430.11-430.61" *)
  reg [2:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr;
  (* src = "ls180.v:431.13-431.65" *)
  wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
  (* src = "ls180.v:433.13-433.65" *)
  wire [24:0] sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
  (* src = "ls180.v:432.6-432.55" *)
  wire sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
  (* src = "ls180.v:447.6-447.46" *)
  wire sdram_bankmachine0_cmd_buffer_sink_first;
  (* src = "ls180.v:448.6-448.45" *)
  wire sdram_bankmachine0_cmd_buffer_sink_last;
  (* src = "ls180.v:450.13-450.60" *)
  wire [21:0] sdram_bankmachine0_cmd_buffer_sink_payload_addr;
  (* src = "ls180.v:449.6-449.51" *)
  wire sdram_bankmachine0_cmd_buffer_sink_payload_we;
  (* src = "ls180.v:446.6-446.46" *)
  wire sdram_bankmachine0_cmd_buffer_sink_ready;
  (* src = "ls180.v:445.6-445.46" *)
  wire sdram_bankmachine0_cmd_buffer_sink_valid;
  (* src = "ls180.v:453.5-453.47" *)
  reg sdram_bankmachine0_cmd_buffer_source_first;
  (* src = "ls180.v:454.5-454.46" *)
  reg sdram_bankmachine0_cmd_buffer_source_last;
  (* src = "ls180.v:456.12-456.61" *)
  reg [21:0] sdram_bankmachine0_cmd_buffer_source_payload_addr;
  (* src = "ls180.v:455.5-455.52" *)
  reg sdram_bankmachine0_cmd_buffer_source_payload_we;
  (* src = "ls180.v:452.6-452.48" *)
  wire sdram_bankmachine0_cmd_buffer_source_ready;
  (* src = "ls180.v:451.5-451.47" *)
  reg sdram_bankmachine0_cmd_buffer_source_valid;
  (* src = "ls180.v:399.12-399.44" *)
  reg [12:0] sdram_bankmachine0_cmd_payload_a;
  (* src = "ls180.v:400.12-400.45" *)
  wire [1:0] sdram_bankmachine0_cmd_payload_ba;
  (* src = "ls180.v:401.5-401.39" *)
  reg sdram_bankmachine0_cmd_payload_cas;
  (* src = "ls180.v:404.5-404.42" *)
  reg sdram_bankmachine0_cmd_payload_is_cmd;
  (* src = "ls180.v:405.5-405.43" *)
  reg sdram_bankmachine0_cmd_payload_is_read;
  (* src = "ls180.v:406.5-406.44" *)
  reg sdram_bankmachine0_cmd_payload_is_write;
  (* src = "ls180.v:402.5-402.39" *)
  reg sdram_bankmachine0_cmd_payload_ras;
  (* src = "ls180.v:403.5-403.38" *)
  reg sdram_bankmachine0_cmd_payload_we;
  (* src = "ls180.v:398.5-398.33" *)
  reg sdram_bankmachine0_cmd_ready;
  (* src = "ls180.v:397.5-397.33" *)
  reg sdram_bankmachine0_cmd_valid;
  (* src = "ls180.v:396.5-396.35" *)
  reg sdram_bankmachine0_refresh_gnt;
  (* src = "ls180.v:395.6-395.36" *)
  wire sdram_bankmachine0_refresh_req;
  (* src = "ls180.v:391.13-391.40" *)
  wire [21:0] sdram_bankmachine0_req_addr;
  (* src = "ls180.v:392.6-392.33" *)
  wire sdram_bankmachine0_req_lock;
  (* src = "ls180.v:394.5-394.39" *)
  reg sdram_bankmachine0_req_rdata_valid;
  (* src = "ls180.v:389.6-389.34" *)
  wire sdram_bankmachine0_req_ready;
  (* src = "ls180.v:388.6-388.34" *)
  wire sdram_bankmachine0_req_valid;
  (* src = "ls180.v:393.5-393.39" *)
  reg sdram_bankmachine0_req_wdata_ready;
  (* src = "ls180.v:390.6-390.31" *)
  wire sdram_bankmachine0_req_we;
  (* src = "ls180.v:457.12-457.34" *)
  reg [12:0] sdram_bankmachine0_row;
  (* src = "ls180.v:461.5-461.33" *)
  reg sdram_bankmachine0_row_close;
  (* src = "ls180.v:462.5-462.42" *)
  reg sdram_bankmachine0_row_col_n_addr_sel;
  (* src = "ls180.v:459.6-459.32" *)
  wire sdram_bankmachine0_row_hit;
  (* src = "ls180.v:460.5-460.32" *)
  reg sdram_bankmachine0_row_open;
  (* src = "ls180.v:458.5-458.34" *)
  reg sdram_bankmachine0_row_opened;
  (* no_retiming = "true" *)
  (* src = "ls180.v:469.32-469.64" *)
  reg sdram_bankmachine0_trascon_ready;
  (* src = "ls180.v:468.6-468.38" *)
  wire sdram_bankmachine0_trascon_valid;
  (* no_retiming = "true" *)
  (* src = "ls180.v:467.32-467.63" *)
  reg sdram_bankmachine0_trccon_ready;
  (* src = "ls180.v:466.6-466.37" *)
  wire sdram_bankmachine0_trccon_valid;
  (* src = "ls180.v:465.11-465.43" *)
  reg [2:0] sdram_bankmachine0_twtpcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:464.32-464.64" *)
  reg sdram_bankmachine0_twtpcon_ready;
  (* src = "ls180.v:463.6-463.38" *)
  wire sdram_bankmachine0_twtpcon_valid;
  (* src = "ls180.v:489.5-489.38" *)
  reg sdram_bankmachine1_auto_precharge;
  (* src = "ls180.v:511.11-511.58" *)
  reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_consume;
  (* src = "ls180.v:516.6-516.53" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_do_read;
  (* src = "ls180.v:521.6-521.59" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
  (* src = "ls180.v:522.6-522.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
  (* src = "ls180.v:520.13-520.73" *)
  wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
  (* src = "ls180.v:519.6-519.64" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
  (* src = "ls180.v:525.6-525.60" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
  (* src = "ls180.v:526.6-526.59" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
  (* src = "ls180.v:524.13-524.74" *)
  wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
  (* src = "ls180.v:523.6-523.65" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
  (* src = "ls180.v:508.11-508.56" *)
  reg [3:0] sdram_bankmachine1_cmd_buffer_lookahead_level;
  (* src = "ls180.v:510.11-510.58" *)
  reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_produce;
  (* src = "ls180.v:517.12-517.62" *)
  wire [2:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
  (* src = "ls180.v:518.13-518.65" *)
  wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
  (* src = "ls180.v:509.5-509.52" *)
  reg sdram_bankmachine1_cmd_buffer_lookahead_replace;
  (* src = "ls180.v:492.5-492.55" *)
  reg sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
  (* src = "ls180.v:493.5-493.54" *)
  reg sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
  (* src = "ls180.v:495.13-495.70" *)
  wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
  (* src = "ls180.v:494.6-494.61" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
  (* src = "ls180.v:491.6-491.56" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
  (* src = "ls180.v:490.6-490.56" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
  (* src = "ls180.v:498.6-498.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_source_first;
  (* src = "ls180.v:499.6-499.57" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_source_last;
  (* src = "ls180.v:501.13-501.72" *)
  wire [21:0] sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
  (* src = "ls180.v:500.6-500.63" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
  (* src = "ls180.v:497.6-497.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
  (* src = "ls180.v:496.6-496.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
  (* src = "ls180.v:506.13-506.66" *)
  wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
  (* src = "ls180.v:507.13-507.67" *)
  wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
  (* src = "ls180.v:504.6-504.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
  (* src = "ls180.v:505.6-505.64" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
  (* src = "ls180.v:502.6-502.58" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
  (* src = "ls180.v:503.6-503.64" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
  (* src = "ls180.v:512.11-512.61" *)
  reg [2:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr;
  (* src = "ls180.v:513.13-513.65" *)
  wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
  (* src = "ls180.v:515.13-515.65" *)
  wire [24:0] sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
  (* src = "ls180.v:514.6-514.55" *)
  wire sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
  (* src = "ls180.v:529.6-529.46" *)
  wire sdram_bankmachine1_cmd_buffer_sink_first;
  (* src = "ls180.v:530.6-530.45" *)
  wire sdram_bankmachine1_cmd_buffer_sink_last;
  (* src = "ls180.v:532.13-532.60" *)
  wire [21:0] sdram_bankmachine1_cmd_buffer_sink_payload_addr;
  (* src = "ls180.v:531.6-531.51" *)
  wire sdram_bankmachine1_cmd_buffer_sink_payload_we;
  (* src = "ls180.v:528.6-528.46" *)
  wire sdram_bankmachine1_cmd_buffer_sink_ready;
  (* src = "ls180.v:527.6-527.46" *)
  wire sdram_bankmachine1_cmd_buffer_sink_valid;
  (* src = "ls180.v:535.5-535.47" *)
  reg sdram_bankmachine1_cmd_buffer_source_first;
  (* src = "ls180.v:536.5-536.46" *)
  reg sdram_bankmachine1_cmd_buffer_source_last;
  (* src = "ls180.v:538.12-538.61" *)
  reg [21:0] sdram_bankmachine1_cmd_buffer_source_payload_addr;
  (* src = "ls180.v:537.5-537.52" *)
  reg sdram_bankmachine1_cmd_buffer_source_payload_we;
  (* src = "ls180.v:534.6-534.48" *)
  wire sdram_bankmachine1_cmd_buffer_source_ready;
  (* src = "ls180.v:533.5-533.47" *)
  reg sdram_bankmachine1_cmd_buffer_source_valid;
  (* src = "ls180.v:481.12-481.44" *)
  reg [12:0] sdram_bankmachine1_cmd_payload_a;
  (* src = "ls180.v:482.12-482.45" *)
  wire [1:0] sdram_bankmachine1_cmd_payload_ba;
  (* src = "ls180.v:483.5-483.39" *)
  reg sdram_bankmachine1_cmd_payload_cas;
  (* src = "ls180.v:486.5-486.42" *)
  reg sdram_bankmachine1_cmd_payload_is_cmd;
  (* src = "ls180.v:487.5-487.43" *)
  reg sdram_bankmachine1_cmd_payload_is_read;
  (* src = "ls180.v:488.5-488.44" *)
  reg sdram_bankmachine1_cmd_payload_is_write;
  (* src = "ls180.v:484.5-484.39" *)
  reg sdram_bankmachine1_cmd_payload_ras;
  (* src = "ls180.v:485.5-485.38" *)
  reg sdram_bankmachine1_cmd_payload_we;
  (* src = "ls180.v:480.5-480.33" *)
  reg sdram_bankmachine1_cmd_ready;
  (* src = "ls180.v:479.5-479.33" *)
  reg sdram_bankmachine1_cmd_valid;
  (* src = "ls180.v:478.5-478.35" *)
  reg sdram_bankmachine1_refresh_gnt;
  (* src = "ls180.v:477.6-477.36" *)
  wire sdram_bankmachine1_refresh_req;
  (* src = "ls180.v:473.13-473.40" *)
  wire [21:0] sdram_bankmachine1_req_addr;
  (* src = "ls180.v:474.6-474.33" *)
  wire sdram_bankmachine1_req_lock;
  (* src = "ls180.v:476.5-476.39" *)
  reg sdram_bankmachine1_req_rdata_valid;
  (* src = "ls180.v:471.6-471.34" *)
  wire sdram_bankmachine1_req_ready;
  (* src = "ls180.v:470.6-470.34" *)
  wire sdram_bankmachine1_req_valid;
  (* src = "ls180.v:475.5-475.39" *)
  reg sdram_bankmachine1_req_wdata_ready;
  (* src = "ls180.v:472.6-472.31" *)
  wire sdram_bankmachine1_req_we;
  (* src = "ls180.v:539.12-539.34" *)
  reg [12:0] sdram_bankmachine1_row;
  (* src = "ls180.v:543.5-543.33" *)
  reg sdram_bankmachine1_row_close;
  (* src = "ls180.v:544.5-544.42" *)
  reg sdram_bankmachine1_row_col_n_addr_sel;
  (* src = "ls180.v:541.6-541.32" *)
  wire sdram_bankmachine1_row_hit;
  (* src = "ls180.v:542.5-542.32" *)
  reg sdram_bankmachine1_row_open;
  (* src = "ls180.v:540.5-540.34" *)
  reg sdram_bankmachine1_row_opened;
  (* no_retiming = "true" *)
  (* src = "ls180.v:551.32-551.64" *)
  reg sdram_bankmachine1_trascon_ready;
  (* src = "ls180.v:550.6-550.38" *)
  wire sdram_bankmachine1_trascon_valid;
  (* no_retiming = "true" *)
  (* src = "ls180.v:549.32-549.63" *)
  reg sdram_bankmachine1_trccon_ready;
  (* src = "ls180.v:548.6-548.37" *)
  wire sdram_bankmachine1_trccon_valid;
  (* src = "ls180.v:547.11-547.43" *)
  reg [2:0] sdram_bankmachine1_twtpcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:546.32-546.64" *)
  reg sdram_bankmachine1_twtpcon_ready;
  (* src = "ls180.v:545.6-545.38" *)
  wire sdram_bankmachine1_twtpcon_valid;
  (* src = "ls180.v:571.5-571.38" *)
  reg sdram_bankmachine2_auto_precharge;
  (* src = "ls180.v:593.11-593.58" *)
  reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_consume;
  (* src = "ls180.v:598.6-598.53" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_do_read;
  (* src = "ls180.v:603.6-603.59" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
  (* src = "ls180.v:604.6-604.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
  (* src = "ls180.v:602.13-602.73" *)
  wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
  (* src = "ls180.v:601.6-601.64" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
  (* src = "ls180.v:607.6-607.60" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
  (* src = "ls180.v:608.6-608.59" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
  (* src = "ls180.v:606.13-606.74" *)
  wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
  (* src = "ls180.v:605.6-605.65" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
  (* src = "ls180.v:590.11-590.56" *)
  reg [3:0] sdram_bankmachine2_cmd_buffer_lookahead_level;
  (* src = "ls180.v:592.11-592.58" *)
  reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_produce;
  (* src = "ls180.v:599.12-599.62" *)
  wire [2:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
  (* src = "ls180.v:600.13-600.65" *)
  wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
  (* src = "ls180.v:591.5-591.52" *)
  reg sdram_bankmachine2_cmd_buffer_lookahead_replace;
  (* src = "ls180.v:574.5-574.55" *)
  reg sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
  (* src = "ls180.v:575.5-575.54" *)
  reg sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
  (* src = "ls180.v:577.13-577.70" *)
  wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
  (* src = "ls180.v:576.6-576.61" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
  (* src = "ls180.v:573.6-573.56" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
  (* src = "ls180.v:572.6-572.56" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
  (* src = "ls180.v:580.6-580.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_source_first;
  (* src = "ls180.v:581.6-581.57" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_source_last;
  (* src = "ls180.v:583.13-583.72" *)
  wire [21:0] sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
  (* src = "ls180.v:582.6-582.63" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
  (* src = "ls180.v:579.6-579.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
  (* src = "ls180.v:578.6-578.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
  (* src = "ls180.v:588.13-588.66" *)
  wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
  (* src = "ls180.v:589.13-589.67" *)
  wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
  (* src = "ls180.v:586.6-586.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
  (* src = "ls180.v:587.6-587.64" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
  (* src = "ls180.v:584.6-584.58" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
  (* src = "ls180.v:585.6-585.64" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
  (* src = "ls180.v:594.11-594.61" *)
  reg [2:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr;
  (* src = "ls180.v:595.13-595.65" *)
  wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
  (* src = "ls180.v:597.13-597.65" *)
  wire [24:0] sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
  (* src = "ls180.v:596.6-596.55" *)
  wire sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
  (* src = "ls180.v:611.6-611.46" *)
  wire sdram_bankmachine2_cmd_buffer_sink_first;
  (* src = "ls180.v:612.6-612.45" *)
  wire sdram_bankmachine2_cmd_buffer_sink_last;
  (* src = "ls180.v:614.13-614.60" *)
  wire [21:0] sdram_bankmachine2_cmd_buffer_sink_payload_addr;
  (* src = "ls180.v:613.6-613.51" *)
  wire sdram_bankmachine2_cmd_buffer_sink_payload_we;
  (* src = "ls180.v:610.6-610.46" *)
  wire sdram_bankmachine2_cmd_buffer_sink_ready;
  (* src = "ls180.v:609.6-609.46" *)
  wire sdram_bankmachine2_cmd_buffer_sink_valid;
  (* src = "ls180.v:617.5-617.47" *)
  reg sdram_bankmachine2_cmd_buffer_source_first;
  (* src = "ls180.v:618.5-618.46" *)
  reg sdram_bankmachine2_cmd_buffer_source_last;
  (* src = "ls180.v:620.12-620.61" *)
  reg [21:0] sdram_bankmachine2_cmd_buffer_source_payload_addr;
  (* src = "ls180.v:619.5-619.52" *)
  reg sdram_bankmachine2_cmd_buffer_source_payload_we;
  (* src = "ls180.v:616.6-616.48" *)
  wire sdram_bankmachine2_cmd_buffer_source_ready;
  (* src = "ls180.v:615.5-615.47" *)
  reg sdram_bankmachine2_cmd_buffer_source_valid;
  (* src = "ls180.v:563.12-563.44" *)
  reg [12:0] sdram_bankmachine2_cmd_payload_a;
  (* src = "ls180.v:564.12-564.45" *)
  wire [1:0] sdram_bankmachine2_cmd_payload_ba;
  (* src = "ls180.v:565.5-565.39" *)
  reg sdram_bankmachine2_cmd_payload_cas;
  (* src = "ls180.v:568.5-568.42" *)
  reg sdram_bankmachine2_cmd_payload_is_cmd;
  (* src = "ls180.v:569.5-569.43" *)
  reg sdram_bankmachine2_cmd_payload_is_read;
  (* src = "ls180.v:570.5-570.44" *)
  reg sdram_bankmachine2_cmd_payload_is_write;
  (* src = "ls180.v:566.5-566.39" *)
  reg sdram_bankmachine2_cmd_payload_ras;
  (* src = "ls180.v:567.5-567.38" *)
  reg sdram_bankmachine2_cmd_payload_we;
  (* src = "ls180.v:562.5-562.33" *)
  reg sdram_bankmachine2_cmd_ready;
  (* src = "ls180.v:561.5-561.33" *)
  reg sdram_bankmachine2_cmd_valid;
  (* src = "ls180.v:560.5-560.35" *)
  reg sdram_bankmachine2_refresh_gnt;
  (* src = "ls180.v:559.6-559.36" *)
  wire sdram_bankmachine2_refresh_req;
  (* src = "ls180.v:555.13-555.40" *)
  wire [21:0] sdram_bankmachine2_req_addr;
  (* src = "ls180.v:556.6-556.33" *)
  wire sdram_bankmachine2_req_lock;
  (* src = "ls180.v:558.5-558.39" *)
  reg sdram_bankmachine2_req_rdata_valid;
  (* src = "ls180.v:553.6-553.34" *)
  wire sdram_bankmachine2_req_ready;
  (* src = "ls180.v:552.6-552.34" *)
  wire sdram_bankmachine2_req_valid;
  (* src = "ls180.v:557.5-557.39" *)
  reg sdram_bankmachine2_req_wdata_ready;
  (* src = "ls180.v:554.6-554.31" *)
  wire sdram_bankmachine2_req_we;
  (* src = "ls180.v:621.12-621.34" *)
  reg [12:0] sdram_bankmachine2_row;
  (* src = "ls180.v:625.5-625.33" *)
  reg sdram_bankmachine2_row_close;
  (* src = "ls180.v:626.5-626.42" *)
  reg sdram_bankmachine2_row_col_n_addr_sel;
  (* src = "ls180.v:623.6-623.32" *)
  wire sdram_bankmachine2_row_hit;
  (* src = "ls180.v:624.5-624.32" *)
  reg sdram_bankmachine2_row_open;
  (* src = "ls180.v:622.5-622.34" *)
  reg sdram_bankmachine2_row_opened;
  (* no_retiming = "true" *)
  (* src = "ls180.v:633.32-633.64" *)
  reg sdram_bankmachine2_trascon_ready;
  (* src = "ls180.v:632.6-632.38" *)
  wire sdram_bankmachine2_trascon_valid;
  (* no_retiming = "true" *)
  (* src = "ls180.v:631.32-631.63" *)
  reg sdram_bankmachine2_trccon_ready;
  (* src = "ls180.v:630.6-630.37" *)
  wire sdram_bankmachine2_trccon_valid;
  (* src = "ls180.v:629.11-629.43" *)
  reg [2:0] sdram_bankmachine2_twtpcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:628.32-628.64" *)
  reg sdram_bankmachine2_twtpcon_ready;
  (* src = "ls180.v:627.6-627.38" *)
  wire sdram_bankmachine2_twtpcon_valid;
  (* src = "ls180.v:653.5-653.38" *)
  reg sdram_bankmachine3_auto_precharge;
  (* src = "ls180.v:675.11-675.58" *)
  reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_consume;
  (* src = "ls180.v:680.6-680.53" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_do_read;
  (* src = "ls180.v:685.6-685.59" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
  (* src = "ls180.v:686.6-686.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
  (* src = "ls180.v:684.13-684.73" *)
  wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
  (* src = "ls180.v:683.6-683.64" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
  (* src = "ls180.v:689.6-689.60" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
  (* src = "ls180.v:690.6-690.59" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
  (* src = "ls180.v:688.13-688.74" *)
  wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
  (* src = "ls180.v:687.6-687.65" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
  (* src = "ls180.v:672.11-672.56" *)
  reg [3:0] sdram_bankmachine3_cmd_buffer_lookahead_level;
  (* src = "ls180.v:674.11-674.58" *)
  reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_produce;
  (* src = "ls180.v:681.12-681.62" *)
  wire [2:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
  (* src = "ls180.v:682.13-682.65" *)
  wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
  (* src = "ls180.v:673.5-673.52" *)
  reg sdram_bankmachine3_cmd_buffer_lookahead_replace;
  (* src = "ls180.v:656.5-656.55" *)
  reg sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
  (* src = "ls180.v:657.5-657.54" *)
  reg sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
  (* src = "ls180.v:659.13-659.70" *)
  wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
  (* src = "ls180.v:658.6-658.61" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
  (* src = "ls180.v:655.6-655.56" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
  (* src = "ls180.v:654.6-654.56" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
  (* src = "ls180.v:662.6-662.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_source_first;
  (* src = "ls180.v:663.6-663.57" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_source_last;
  (* src = "ls180.v:665.13-665.72" *)
  wire [21:0] sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
  (* src = "ls180.v:664.6-664.63" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
  (* src = "ls180.v:661.6-661.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
  (* src = "ls180.v:660.6-660.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
  (* src = "ls180.v:670.13-670.66" *)
  wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
  (* src = "ls180.v:671.13-671.67" *)
  wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
  (* src = "ls180.v:668.6-668.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
  (* src = "ls180.v:669.6-669.64" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
  (* src = "ls180.v:666.6-666.58" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
  (* src = "ls180.v:667.6-667.64" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
  (* src = "ls180.v:676.11-676.61" *)
  reg [2:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr;
  (* src = "ls180.v:677.13-677.65" *)
  wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
  (* src = "ls180.v:679.13-679.65" *)
  wire [24:0] sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
  (* src = "ls180.v:678.6-678.55" *)
  wire sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
  (* src = "ls180.v:693.6-693.46" *)
  wire sdram_bankmachine3_cmd_buffer_sink_first;
  (* src = "ls180.v:694.6-694.45" *)
  wire sdram_bankmachine3_cmd_buffer_sink_last;
  (* src = "ls180.v:696.13-696.60" *)
  wire [21:0] sdram_bankmachine3_cmd_buffer_sink_payload_addr;
  (* src = "ls180.v:695.6-695.51" *)
  wire sdram_bankmachine3_cmd_buffer_sink_payload_we;
  (* src = "ls180.v:692.6-692.46" *)
  wire sdram_bankmachine3_cmd_buffer_sink_ready;
  (* src = "ls180.v:691.6-691.46" *)
  wire sdram_bankmachine3_cmd_buffer_sink_valid;
  (* src = "ls180.v:699.5-699.47" *)
  reg sdram_bankmachine3_cmd_buffer_source_first;
  (* src = "ls180.v:700.5-700.46" *)
  reg sdram_bankmachine3_cmd_buffer_source_last;
  (* src = "ls180.v:702.12-702.61" *)
  reg [21:0] sdram_bankmachine3_cmd_buffer_source_payload_addr;
  (* src = "ls180.v:701.5-701.52" *)
  reg sdram_bankmachine3_cmd_buffer_source_payload_we;
  (* src = "ls180.v:698.6-698.48" *)
  wire sdram_bankmachine3_cmd_buffer_source_ready;
  (* src = "ls180.v:697.5-697.47" *)
  reg sdram_bankmachine3_cmd_buffer_source_valid;
  (* src = "ls180.v:645.12-645.44" *)
  reg [12:0] sdram_bankmachine3_cmd_payload_a;
  (* src = "ls180.v:646.12-646.45" *)
  wire [1:0] sdram_bankmachine3_cmd_payload_ba;
  (* src = "ls180.v:647.5-647.39" *)
  reg sdram_bankmachine3_cmd_payload_cas;
  (* src = "ls180.v:650.5-650.42" *)
  reg sdram_bankmachine3_cmd_payload_is_cmd;
  (* src = "ls180.v:651.5-651.43" *)
  reg sdram_bankmachine3_cmd_payload_is_read;
  (* src = "ls180.v:652.5-652.44" *)
  reg sdram_bankmachine3_cmd_payload_is_write;
  (* src = "ls180.v:648.5-648.39" *)
  reg sdram_bankmachine3_cmd_payload_ras;
  (* src = "ls180.v:649.5-649.38" *)
  reg sdram_bankmachine3_cmd_payload_we;
  (* src = "ls180.v:644.5-644.33" *)
  reg sdram_bankmachine3_cmd_ready;
  (* src = "ls180.v:643.5-643.33" *)
  reg sdram_bankmachine3_cmd_valid;
  (* src = "ls180.v:642.5-642.35" *)
  reg sdram_bankmachine3_refresh_gnt;
  (* src = "ls180.v:641.6-641.36" *)
  wire sdram_bankmachine3_refresh_req;
  (* src = "ls180.v:637.13-637.40" *)
  wire [21:0] sdram_bankmachine3_req_addr;
  (* src = "ls180.v:638.6-638.33" *)
  wire sdram_bankmachine3_req_lock;
  (* src = "ls180.v:640.5-640.39" *)
  reg sdram_bankmachine3_req_rdata_valid;
  (* src = "ls180.v:635.6-635.34" *)
  wire sdram_bankmachine3_req_ready;
  (* src = "ls180.v:634.6-634.34" *)
  wire sdram_bankmachine3_req_valid;
  (* src = "ls180.v:639.5-639.39" *)
  reg sdram_bankmachine3_req_wdata_ready;
  (* src = "ls180.v:636.6-636.31" *)
  wire sdram_bankmachine3_req_we;
  (* src = "ls180.v:703.12-703.34" *)
  reg [12:0] sdram_bankmachine3_row;
  (* src = "ls180.v:707.5-707.33" *)
  reg sdram_bankmachine3_row_close;
  (* src = "ls180.v:708.5-708.42" *)
  reg sdram_bankmachine3_row_col_n_addr_sel;
  (* src = "ls180.v:705.6-705.32" *)
  wire sdram_bankmachine3_row_hit;
  (* src = "ls180.v:706.5-706.32" *)
  reg sdram_bankmachine3_row_open;
  (* src = "ls180.v:704.5-704.34" *)
  reg sdram_bankmachine3_row_opened;
  (* no_retiming = "true" *)
  (* src = "ls180.v:715.32-715.64" *)
  reg sdram_bankmachine3_trascon_ready;
  (* src = "ls180.v:714.6-714.38" *)
  wire sdram_bankmachine3_trascon_valid;
  (* no_retiming = "true" *)
  (* src = "ls180.v:713.32-713.63" *)
  reg sdram_bankmachine3_trccon_ready;
  (* src = "ls180.v:712.6-712.37" *)
  wire sdram_bankmachine3_trccon_valid;
  (* src = "ls180.v:711.11-711.43" *)
  reg [2:0] sdram_bankmachine3_twtpcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:710.32-710.64" *)
  reg sdram_bankmachine3_twtpcon_ready;
  (* src = "ls180.v:709.6-709.38" *)
  wire sdram_bankmachine3_twtpcon_valid;
  (* src = "ls180.v:717.6-717.23" *)
  wire sdram_cas_allowed;
  (* src = "ls180.v:27.14-27.25" *)
  output sdram_cas_n;
  (* src = "ls180.v:735.6-735.25" *)
  wire sdram_choose_cmd_ce;
  (* src = "ls180.v:724.13-724.43" *)
  wire [12:0] sdram_choose_cmd_cmd_payload_a;
  (* src = "ls180.v:725.12-725.43" *)
  wire [1:0] sdram_choose_cmd_cmd_payload_ba;
  (* src = "ls180.v:726.5-726.37" *)
  reg sdram_choose_cmd_cmd_payload_cas;
  (* src = "ls180.v:729.6-729.41" *)
  wire sdram_choose_cmd_cmd_payload_is_cmd;
  (* src = "ls180.v:730.6-730.42" *)
  wire sdram_choose_cmd_cmd_payload_is_read;
  (* src = "ls180.v:731.6-731.43" *)
  wire sdram_choose_cmd_cmd_payload_is_write;
  (* src = "ls180.v:727.5-727.37" *)
  reg sdram_choose_cmd_cmd_payload_ras;
  (* src = "ls180.v:728.5-728.36" *)
  reg sdram_choose_cmd_cmd_payload_we;
  (* src = "ls180.v:723.5-723.31" *)
  reg sdram_choose_cmd_cmd_ready;
  (* src = "ls180.v:722.6-722.32" *)
  wire sdram_choose_cmd_cmd_valid;
  (* src = "ls180.v:734.11-734.33" *)
  reg [1:0] sdram_choose_cmd_grant;
  (* src = "ls180.v:733.12-733.36" *)
  wire [3:0] sdram_choose_cmd_request;
  (* src = "ls180.v:732.11-732.34" *)
  reg [3:0] sdram_choose_cmd_valids;
  (* src = "ls180.v:721.5-721.36" *)
  reg sdram_choose_cmd_want_activates;
  (* src = "ls180.v:720.5-720.31" *)
  reg sdram_choose_cmd_want_cmds;
  (* src = "ls180.v:718.5-718.32" *)
  reg sdram_choose_cmd_want_reads;
  (* src = "ls180.v:719.5-719.33" *)
  reg sdram_choose_cmd_want_writes;
  (* src = "ls180.v:753.6-753.25" *)
  wire sdram_choose_req_ce;
  (* src = "ls180.v:742.13-742.43" *)
  wire [12:0] sdram_choose_req_cmd_payload_a;
  (* src = "ls180.v:743.12-743.43" *)
  wire [1:0] sdram_choose_req_cmd_payload_ba;
  (* src = "ls180.v:744.5-744.37" *)
  reg sdram_choose_req_cmd_payload_cas;
  (* src = "ls180.v:747.6-747.41" *)
  wire sdram_choose_req_cmd_payload_is_cmd;
  (* src = "ls180.v:748.6-748.42" *)
  wire sdram_choose_req_cmd_payload_is_read;
  (* src = "ls180.v:749.6-749.43" *)
  wire sdram_choose_req_cmd_payload_is_write;
  (* src = "ls180.v:745.5-745.37" *)
  reg sdram_choose_req_cmd_payload_ras;
  (* src = "ls180.v:746.5-746.36" *)
  reg sdram_choose_req_cmd_payload_we;
  (* src = "ls180.v:741.5-741.31" *)
  reg sdram_choose_req_cmd_ready;
  (* src = "ls180.v:740.6-740.32" *)
  wire sdram_choose_req_cmd_valid;
  (* src = "ls180.v:752.11-752.33" *)
  reg [1:0] sdram_choose_req_grant;
  (* src = "ls180.v:751.12-751.36" *)
  wire [3:0] sdram_choose_req_request;
  (* src = "ls180.v:750.11-750.34" *)
  reg [3:0] sdram_choose_req_valids;
  (* src = "ls180.v:739.5-739.36" *)
  reg sdram_choose_req_want_activates;
  (* src = "ls180.v:738.6-738.32" *)
  wire sdram_choose_req_want_cmds;
  (* src = "ls180.v:736.5-736.32" *)
  reg sdram_choose_req_want_reads;
  (* src = "ls180.v:737.5-737.33" *)
  reg sdram_choose_req_want_writes;
  (* src = "ls180.v:29.14-29.23" *)
  output sdram_cke;
  (* src = "ls180.v:297.6-297.17" *)
  wire sdram_cke_1;
  (* src = "ls180.v:32.14-32.25" *)
  output sdram_clock;
  (* src = "ls180.v:365.5-365.19" *)
  reg sdram_cmd_last;
  (* src = "ls180.v:366.12-366.31" *)
  reg [12:0] sdram_cmd_payload_a;
  (* src = "ls180.v:367.11-367.31" *)
  reg [1:0] sdram_cmd_payload_ba;
  (* src = "ls180.v:368.5-368.26" *)
  reg sdram_cmd_payload_cas;
  (* src = "ls180.v:371.5-371.30" *)
  reg sdram_cmd_payload_is_read;
  (* src = "ls180.v:372.5-372.31" *)
  reg sdram_cmd_payload_is_write;
  (* src = "ls180.v:369.5-369.26" *)
  reg sdram_cmd_payload_ras;
  (* src = "ls180.v:370.5-370.25" *)
  reg sdram_cmd_payload_we;
  (* src = "ls180.v:364.5-364.20" *)
  reg sdram_cmd_ready;
  (* src = "ls180.v:363.5-363.20" *)
  reg sdram_cmd_valid;
  (* src = "ls180.v:305.6-305.27" *)
  wire sdram_command_issue_r;
  (* src = "ls180.v:304.6-304.28" *)
  wire sdram_command_issue_re;
  (* src = "ls180.v:307.5-307.26" *)
  reg sdram_command_issue_w;
  (* src = "ls180.v:306.6-306.28" *)
  wire sdram_command_issue_we;
  (* src = "ls180.v:303.5-303.21" *)
  reg sdram_command_re;
  (* src = "ls180.v:302.11-302.32" *)
  reg [5:0] sdram_command_storage;
  (* src = "ls180.v:28.14-28.24" *)
  output sdram_cs_n;
  (* src = "ls180.v:356.5-356.23" *)
  reg sdram_dfi_p0_act_n;
  (* src = "ls180.v:347.12-347.32" *)
  reg [12:0] sdram_dfi_p0_address;
  (* src = "ls180.v:348.11-348.28" *)
  reg [1:0] sdram_dfi_p0_bank;
  (* src = "ls180.v:349.5-349.23" *)
  reg sdram_dfi_p0_cas_n;
  (* src = "ls180.v:353.6-353.22" *)
  wire sdram_dfi_p0_cke;
  (* src = "ls180.v:350.5-350.22" *)
  reg sdram_dfi_p0_cs_n;
  (* src = "ls180.v:354.6-354.22" *)
  wire sdram_dfi_p0_odt;
  (* src = "ls180.v:351.5-351.23" *)
  reg sdram_dfi_p0_ras_n;
  (* src = "ls180.v:361.13-361.32" *)
  wire [15:0] sdram_dfi_p0_rddata;
  (* src = "ls180.v:360.5-360.27" *)
  reg sdram_dfi_p0_rddata_en;
  (* src = "ls180.v:362.6-362.31" *)
  wire sdram_dfi_p0_rddata_valid;
  (* src = "ls180.v:355.6-355.26" *)
  wire sdram_dfi_p0_reset_n;
  (* src = "ls180.v:352.5-352.22" *)
  reg sdram_dfi_p0_we_n;
  (* src = "ls180.v:357.13-357.32" *)
  wire [15:0] sdram_dfi_p0_wrdata;
  (* src = "ls180.v:358.5-358.27" *)
  reg sdram_dfi_p0_wrdata_en;
  (* src = "ls180.v:359.12-359.36" *)
  wire [1:0] sdram_dfi_p0_wrdata_mask;
  (* src = "ls180.v:31.20-31.28" *)
  output [1:0] sdram_dm;
  (* src = "ls180.v:22.20-22.30" *)
  input [15:0] sdram_dq_i;
  (* src = "ls180.v:23.21-23.31" *)
  output [15:0] sdram_dq_o;
  (* src = "ls180.v:24.21-24.32" *)
  output [15:0] sdram_dq_oe;
  (* src = "ls180.v:771.5-771.14" *)
  reg sdram_en0;
  (* src = "ls180.v:774.5-774.14" *)
  reg sdram_en1;
  (* src = "ls180.v:777.6-777.25" *)
  wire sdram_go_to_refresh;
  (* src = "ls180.v:319.13-319.39" *)
  wire [21:0] sdram_interface_bank0_addr;
  (* src = "ls180.v:320.6-320.32" *)
  wire sdram_interface_bank0_lock;
  (* src = "ls180.v:322.6-322.39" *)
  wire sdram_interface_bank0_rdata_valid;
  (* src = "ls180.v:317.6-317.33" *)
  wire sdram_interface_bank0_ready;
  (* src = "ls180.v:316.6-316.33" *)
  wire sdram_interface_bank0_valid;
  (* src = "ls180.v:321.6-321.39" *)
  wire sdram_interface_bank0_wdata_ready;
  (* src = "ls180.v:318.6-318.30" *)
  wire sdram_interface_bank0_we;
  (* src = "ls180.v:326.13-326.39" *)
  wire [21:0] sdram_interface_bank1_addr;
  (* src = "ls180.v:327.6-327.32" *)
  wire sdram_interface_bank1_lock;
  (* src = "ls180.v:329.6-329.39" *)
  wire sdram_interface_bank1_rdata_valid;
  (* src = "ls180.v:324.6-324.33" *)
  wire sdram_interface_bank1_ready;
  (* src = "ls180.v:323.6-323.33" *)
  wire sdram_interface_bank1_valid;
  (* src = "ls180.v:328.6-328.39" *)
  wire sdram_interface_bank1_wdata_ready;
  (* src = "ls180.v:325.6-325.30" *)
  wire sdram_interface_bank1_we;
  (* src = "ls180.v:333.13-333.39" *)
  wire [21:0] sdram_interface_bank2_addr;
  (* src = "ls180.v:334.6-334.32" *)
  wire sdram_interface_bank2_lock;
  (* src = "ls180.v:336.6-336.39" *)
  wire sdram_interface_bank2_rdata_valid;
  (* src = "ls180.v:331.6-331.33" *)
  wire sdram_interface_bank2_ready;
  (* src = "ls180.v:330.6-330.33" *)
  wire sdram_interface_bank2_valid;
  (* src = "ls180.v:335.6-335.39" *)
  wire sdram_interface_bank2_wdata_ready;
  (* src = "ls180.v:332.6-332.30" *)
  wire sdram_interface_bank2_we;
  (* src = "ls180.v:340.13-340.39" *)
  wire [21:0] sdram_interface_bank3_addr;
  (* src = "ls180.v:341.6-341.32" *)
  wire sdram_interface_bank3_lock;
  (* src = "ls180.v:343.6-343.39" *)
  wire sdram_interface_bank3_rdata_valid;
  (* src = "ls180.v:338.6-338.33" *)
  wire sdram_interface_bank3_ready;
  (* src = "ls180.v:337.6-337.33" *)
  wire sdram_interface_bank3_valid;
  (* src = "ls180.v:342.6-342.39" *)
  wire sdram_interface_bank3_wdata_ready;
  (* src = "ls180.v:339.6-339.30" *)
  wire sdram_interface_bank3_we;
  (* src = "ls180.v:346.13-346.34" *)
  wire [15:0] sdram_interface_rdata;
  (* src = "ls180.v:344.12-344.33" *)
  reg [15:0] sdram_interface_wdata;
  (* src = "ls180.v:345.11-345.35" *)
  reg [1:0] sdram_interface_wdata_we;
  (* src = "ls180.v:257.5-257.24" *)
  reg sdram_inti_p0_act_n;
  (* src = "ls180.v:248.13-248.34" *)
  wire [12:0] sdram_inti_p0_address;
  (* src = "ls180.v:249.12-249.30" *)
  wire [1:0] sdram_inti_p0_bank;
  (* src = "ls180.v:250.5-250.24" *)
  reg sdram_inti_p0_cas_n;
  (* src = "ls180.v:254.6-254.23" *)
  wire sdram_inti_p0_cke;
  (* src = "ls180.v:251.5-251.23" *)
  reg sdram_inti_p0_cs_n;
  (* src = "ls180.v:255.6-255.23" *)
  wire sdram_inti_p0_odt;
  (* src = "ls180.v:252.5-252.24" *)
  reg sdram_inti_p0_ras_n;
  (* src = "ls180.v:262.12-262.32" *)
  reg [15:0] sdram_inti_p0_rddata;
  (* src = "ls180.v:261.6-261.29" *)
  wire sdram_inti_p0_rddata_en;
  (* src = "ls180.v:263.5-263.31" *)
  reg sdram_inti_p0_rddata_valid;
  (* src = "ls180.v:256.6-256.27" *)
  wire sdram_inti_p0_reset_n;
  (* src = "ls180.v:253.5-253.23" *)
  reg sdram_inti_p0_we_n;
  (* src = "ls180.v:258.13-258.33" *)
  wire [15:0] sdram_inti_p0_wrdata;
  (* src = "ls180.v:259.6-259.29" *)
  wire sdram_inti_p0_wrdata_en;
  (* src = "ls180.v:260.12-260.37" *)
  wire [1:0] sdram_inti_p0_wrdata_mask;
  (* src = "ls180.v:289.5-289.26" *)
  reg sdram_master_p0_act_n;
  (* src = "ls180.v:280.12-280.35" *)
  reg [12:0] sdram_master_p0_address;
  (* src = "ls180.v:281.11-281.31" *)
  reg [1:0] sdram_master_p0_bank;
  (* src = "ls180.v:282.5-282.26" *)
  reg sdram_master_p0_cas_n;
  (* src = "ls180.v:286.5-286.24" *)
  reg sdram_master_p0_cke;
  (* src = "ls180.v:283.5-283.25" *)
  reg sdram_master_p0_cs_n;
  (* src = "ls180.v:287.5-287.24" *)
  reg sdram_master_p0_odt;
  (* src = "ls180.v:284.5-284.26" *)
  reg sdram_master_p0_ras_n;
  (* src = "ls180.v:294.13-294.35" *)
  wire [15:0] sdram_master_p0_rddata;
  (* src = "ls180.v:293.5-293.30" *)
  reg sdram_master_p0_rddata_en;
  (* src = "ls180.v:295.6-295.34" *)
  wire sdram_master_p0_rddata_valid;
  (* src = "ls180.v:288.5-288.28" *)
  reg sdram_master_p0_reset_n;
  (* src = "ls180.v:285.5-285.25" *)
  reg sdram_master_p0_we_n;
  (* src = "ls180.v:290.12-290.34" *)
  reg [15:0] sdram_master_p0_wrdata;
  (* src = "ls180.v:291.5-291.30" *)
  reg sdram_master_p0_wrdata_en;
  (* src = "ls180.v:292.11-292.38" *)
  reg [1:0] sdram_master_p0_wrdata_mask;
  (* src = "ls180.v:772.6-772.21" *)
  wire sdram_max_time0;
  (* src = "ls180.v:775.6-775.21" *)
  wire sdram_max_time1;
  (* src = "ls180.v:754.12-754.23" *)
  reg [12:0] sdram_nop_a;
  (* src = "ls180.v:755.11-755.23" *)
  reg [1:0] sdram_nop_ba;
  (* src = "ls180.v:298.6-298.15" *)
  wire sdram_odt;
  (* src = "ls180.v:381.5-381.26" *)
  reg sdram_postponer_count;
  (* src = "ls180.v:379.6-379.27" *)
  wire sdram_postponer_req_i;
  (* src = "ls180.v:380.5-380.26" *)
  reg sdram_postponer_req_o;
  (* src = "ls180.v:716.6-716.23" *)
  wire sdram_ras_allowed;
  (* src = "ls180.v:26.14-26.25" *)
  output sdram_ras_n;
  (* src = "ls180.v:301.5-301.13" *)
  reg sdram_re;
  (* src = "ls180.v:769.6-769.26" *)
  wire sdram_read_available;
  (* src = "ls180.v:299.6-299.19" *)
  wire sdram_reset_n;
  (* src = "ls180.v:296.6-296.15" *)
  wire sdram_sel;
  (* src = "ls180.v:387.5-387.26" *)
  reg sdram_sequencer_count;
  (* src = "ls180.v:386.11-386.34" *)
  reg [3:0] sdram_sequencer_counter;
  (* src = "ls180.v:383.6-383.27" *)
  wire sdram_sequencer_done0;
  (* src = "ls180.v:385.5-385.26" *)
  reg sdram_sequencer_done1;
  (* src = "ls180.v:382.5-382.27" *)
  reg sdram_sequencer_start0;
  (* src = "ls180.v:384.6-384.28" *)
  wire sdram_sequencer_start1;
  (* src = "ls180.v:273.6-273.26" *)
  wire sdram_slave_p0_act_n;
  (* src = "ls180.v:264.13-264.35" *)
  wire [12:0] sdram_slave_p0_address;
  (* src = "ls180.v:265.12-265.31" *)
  wire [1:0] sdram_slave_p0_bank;
  (* src = "ls180.v:266.6-266.26" *)
  wire sdram_slave_p0_cas_n;
  (* src = "ls180.v:270.6-270.24" *)
  wire sdram_slave_p0_cke;
  (* src = "ls180.v:267.6-267.25" *)
  wire sdram_slave_p0_cs_n;
  (* src = "ls180.v:271.6-271.24" *)
  wire sdram_slave_p0_odt;
  (* src = "ls180.v:268.6-268.26" *)
  wire sdram_slave_p0_ras_n;
  (* src = "ls180.v:278.12-278.33" *)
  reg [15:0] sdram_slave_p0_rddata;
  (* src = "ls180.v:277.6-277.30" *)
  wire sdram_slave_p0_rddata_en;
  (* src = "ls180.v:279.5-279.32" *)
  reg sdram_slave_p0_rddata_valid;
  (* src = "ls180.v:272.6-272.28" *)
  wire sdram_slave_p0_reset_n;
  (* src = "ls180.v:269.6-269.25" *)
  wire sdram_slave_p0_we_n;
  (* src = "ls180.v:274.13-274.34" *)
  wire [15:0] sdram_slave_p0_wrdata;
  (* src = "ls180.v:275.6-275.30" *)
  wire sdram_slave_p0_wrdata_en;
  (* src = "ls180.v:276.12-276.38" *)
  wire [1:0] sdram_slave_p0_wrdata_mask;
  (* src = "ls180.v:314.12-314.24" *)
  reg [15:0] sdram_status;
  (* src = "ls180.v:757.5-757.19" *)
  reg sdram_steerer0;
  (* src = "ls180.v:758.5-758.19" *)
  reg sdram_steerer1;
  (* src = "ls180.v:756.11-756.28" *)
  reg [1:0] sdram_steerer_sel;
  (* src = "ls180.v:300.11-300.24" *)
  reg [3:0] sdram_storage;
  (* src = "ls180.v:765.5-765.24" *)
  reg sdram_tccdcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:764.32-764.51" *)
  reg sdram_tccdcon_ready;
  (* src = "ls180.v:763.6-763.25" *)
  wire sdram_tccdcon_valid;
  (* no_retiming = "true" *)
  (* src = "ls180.v:762.32-762.51" *)
  reg sdram_tfawcon_ready;
  (* src = "ls180.v:761.6-761.25" *)
  wire sdram_tfawcon_valid;
  (* src = "ls180.v:773.11-773.22" *)
  reg [4:0] sdram_time0;
  (* src = "ls180.v:776.11-776.22" *)
  reg [3:0] sdram_time1;
  (* src = "ls180.v:376.12-376.30" *)
  wire [9:0] sdram_timer_count0;
  (* src = "ls180.v:378.11-378.29" *)
  reg [9:0] sdram_timer_count1;
  (* src = "ls180.v:375.6-375.23" *)
  wire sdram_timer_done0;
  (* src = "ls180.v:377.6-377.23" *)
  wire sdram_timer_done1;
  (* src = "ls180.v:374.6-374.22" *)
  wire sdram_timer_wait;
  (* no_retiming = "true" *)
  (* src = "ls180.v:760.32-760.51" *)
  reg sdram_trrdcon_ready;
  (* src = "ls180.v:759.6-759.25" *)
  wire sdram_trrdcon_valid;
  (* src = "ls180.v:768.11-768.30" *)
  reg [2:0] sdram_twtrcon_count;
  (* no_retiming = "true" *)
  (* src = "ls180.v:767.32-767.51" *)
  reg sdram_twtrcon_ready;
  (* src = "ls180.v:766.6-766.25" *)
  wire sdram_twtrcon_valid;
  (* src = "ls180.v:373.6-373.25" *)
  wire sdram_wants_refresh;
  (* src = "ls180.v:315.6-315.14" *)
  wire sdram_we;
  (* src = "ls180.v:25.14-25.24" *)
  output sdram_we_n;
  (* src = "ls180.v:313.5-313.20" *)
  reg sdram_wrdata_re;
  (* src = "ls180.v:312.12-312.32" *)
  reg [15:0] sdram_wrdata_storage;
  (* src = "ls180.v:770.6-770.27" *)
  wire sdram_write_available;
  (* src = "ls180.v:1366.6-1366.15" *)
  wire sdrio_clk;
  (* src = "ls180.v:1367.6-1367.17" *)
  wire sdrio_clk_1;
  (* src = "ls180.v:1376.6-1376.18" *)
  wire sdrio_clk_10;
  (* src = "ls180.v:1468.6-1468.19" *)
  wire sdrio_clk_100;
  (* src = "ls180.v:1469.6-1469.19" *)
  wire sdrio_clk_101;
  (* src = "ls180.v:1470.6-1470.19" *)
  wire sdrio_clk_102;
  (* src = "ls180.v:1471.6-1471.19" *)
  wire sdrio_clk_103;
  (* src = "ls180.v:1472.6-1472.19" *)
  wire sdrio_clk_104;
  (* src = "ls180.v:1473.6-1473.19" *)
  wire sdrio_clk_105;
  (* src = "ls180.v:1474.6-1474.19" *)
  wire sdrio_clk_106;
  (* src = "ls180.v:1475.6-1475.19" *)
  wire sdrio_clk_107;
  (* src = "ls180.v:1476.6-1476.19" *)
  wire sdrio_clk_108;
  (* src = "ls180.v:1477.6-1477.19" *)
  wire sdrio_clk_109;
  (* src = "ls180.v:1377.6-1377.18" *)
  wire sdrio_clk_11;
  (* src = "ls180.v:1478.6-1478.19" *)
  wire sdrio_clk_110;
  (* src = "ls180.v:1479.6-1479.19" *)
  wire sdrio_clk_111;
  (* src = "ls180.v:1480.6-1480.19" *)
  wire sdrio_clk_112;
  (* src = "ls180.v:1481.6-1481.19" *)
  wire sdrio_clk_113;
  (* src = "ls180.v:1482.6-1482.19" *)
  wire sdrio_clk_114;
  (* src = "ls180.v:1483.6-1483.19" *)
  wire sdrio_clk_115;
  (* src = "ls180.v:1484.6-1484.19" *)
  wire sdrio_clk_116;
  (* src = "ls180.v:1485.6-1485.19" *)
  wire sdrio_clk_117;
  (* src = "ls180.v:1486.6-1486.19" *)
  wire sdrio_clk_118;
  (* src = "ls180.v:1378.6-1378.18" *)
  wire sdrio_clk_12;
  (* src = "ls180.v:1379.6-1379.18" *)
  wire sdrio_clk_13;
  (* src = "ls180.v:1380.6-1380.18" *)
  wire sdrio_clk_14;
  (* src = "ls180.v:1381.6-1381.18" *)
  wire sdrio_clk_15;
  (* src = "ls180.v:1382.6-1382.18" *)
  wire sdrio_clk_16;
  (* src = "ls180.v:1383.6-1383.18" *)
  wire sdrio_clk_17;
  (* src = "ls180.v:1384.6-1384.18" *)
  wire sdrio_clk_18;
  (* src = "ls180.v:1385.6-1385.18" *)
  wire sdrio_clk_19;
  (* src = "ls180.v:1368.6-1368.17" *)
  wire sdrio_clk_2;
  (* src = "ls180.v:1386.6-1386.18" *)
  wire sdrio_clk_20;
  (* src = "ls180.v:1387.6-1387.18" *)
  wire sdrio_clk_21;
  (* src = "ls180.v:1388.6-1388.18" *)
  wire sdrio_clk_22;
  (* src = "ls180.v:1389.6-1389.18" *)
  wire sdrio_clk_23;
  (* src = "ls180.v:1390.6-1390.18" *)
  wire sdrio_clk_24;
  (* src = "ls180.v:1391.6-1391.18" *)
  wire sdrio_clk_25;
  (* src = "ls180.v:1392.6-1392.18" *)
  wire sdrio_clk_26;
  (* src = "ls180.v:1393.6-1393.18" *)
  wire sdrio_clk_27;
  (* src = "ls180.v:1394.6-1394.18" *)
  wire sdrio_clk_28;
  (* src = "ls180.v:1395.6-1395.18" *)
  wire sdrio_clk_29;
  (* src = "ls180.v:1369.6-1369.17" *)
  wire sdrio_clk_3;
  (* src = "ls180.v:1396.6-1396.18" *)
  wire sdrio_clk_30;
  (* src = "ls180.v:1397.6-1397.18" *)
  wire sdrio_clk_31;
  (* src = "ls180.v:1398.6-1398.18" *)
  wire sdrio_clk_32;
  (* src = "ls180.v:1399.6-1399.18" *)
  wire sdrio_clk_33;
  (* src = "ls180.v:1400.6-1400.18" *)
  wire sdrio_clk_34;
  (* src = "ls180.v:1401.6-1401.18" *)
  wire sdrio_clk_35;
  (* src = "ls180.v:1402.6-1402.18" *)
  wire sdrio_clk_36;
  (* src = "ls180.v:1403.6-1403.18" *)
  wire sdrio_clk_37;
  (* src = "ls180.v:1404.6-1404.18" *)
  wire sdrio_clk_38;
  (* src = "ls180.v:1405.6-1405.18" *)
  wire sdrio_clk_39;
  (* src = "ls180.v:1370.6-1370.17" *)
  wire sdrio_clk_4;
  (* src = "ls180.v:1406.6-1406.18" *)
  wire sdrio_clk_40;
  (* src = "ls180.v:1407.6-1407.18" *)
  wire sdrio_clk_41;
  (* src = "ls180.v:1408.6-1408.18" *)
  wire sdrio_clk_42;
  (* src = "ls180.v:1409.6-1409.18" *)
  wire sdrio_clk_43;
  (* src = "ls180.v:1410.6-1410.18" *)
  wire sdrio_clk_44;
  (* src = "ls180.v:1411.6-1411.18" *)
  wire sdrio_clk_45;
  (* src = "ls180.v:1412.6-1412.18" *)
  wire sdrio_clk_46;
  (* src = "ls180.v:1413.6-1413.18" *)
  wire sdrio_clk_47;
  (* src = "ls180.v:1414.6-1414.18" *)
  wire sdrio_clk_48;
  (* src = "ls180.v:1415.6-1415.18" *)
  wire sdrio_clk_49;
  (* src = "ls180.v:1371.6-1371.17" *)
  wire sdrio_clk_5;
  (* src = "ls180.v:1416.6-1416.18" *)
  wire sdrio_clk_50;
  (* src = "ls180.v:1417.6-1417.18" *)
  wire sdrio_clk_51;
  (* src = "ls180.v:1418.6-1418.18" *)
  wire sdrio_clk_52;
  (* src = "ls180.v:1419.6-1419.18" *)
  wire sdrio_clk_53;
  (* src = "ls180.v:1420.6-1420.18" *)
  wire sdrio_clk_54;
  (* src = "ls180.v:1421.6-1421.18" *)
  wire sdrio_clk_55;
  (* src = "ls180.v:1422.6-1422.18" *)
  wire sdrio_clk_56;
  (* src = "ls180.v:1423.6-1423.18" *)
  wire sdrio_clk_57;
  (* src = "ls180.v:1424.6-1424.18" *)
  wire sdrio_clk_58;
  (* src = "ls180.v:1425.6-1425.18" *)
  wire sdrio_clk_59;
  (* src = "ls180.v:1372.6-1372.17" *)
  wire sdrio_clk_6;
  (* src = "ls180.v:1426.6-1426.18" *)
  wire sdrio_clk_60;
  (* src = "ls180.v:1427.6-1427.18" *)
  wire sdrio_clk_61;
  (* src = "ls180.v:1428.6-1428.18" *)
  wire sdrio_clk_62;
  (* src = "ls180.v:1429.6-1429.18" *)
  wire sdrio_clk_63;
  (* src = "ls180.v:1430.6-1430.18" *)
  wire sdrio_clk_64;
  (* src = "ls180.v:1431.6-1431.18" *)
  wire sdrio_clk_65;
  (* src = "ls180.v:1432.6-1432.18" *)
  wire sdrio_clk_66;
  (* src = "ls180.v:1433.6-1433.18" *)
  wire sdrio_clk_67;
  (* src = "ls180.v:1434.6-1434.18" *)
  wire sdrio_clk_68;
  (* src = "ls180.v:1435.6-1435.18" *)
  wire sdrio_clk_69;
  (* src = "ls180.v:1373.6-1373.17" *)
  wire sdrio_clk_7;
  (* src = "ls180.v:1436.6-1436.18" *)
  wire sdrio_clk_70;
  (* src = "ls180.v:1439.6-1439.18" *)
  wire sdrio_clk_71;
  (* src = "ls180.v:1440.6-1440.18" *)
  wire sdrio_clk_72;
  (* src = "ls180.v:1441.6-1441.18" *)
  wire sdrio_clk_73;
  (* src = "ls180.v:1442.6-1442.18" *)
  wire sdrio_clk_74;
  (* src = "ls180.v:1443.6-1443.18" *)
  wire sdrio_clk_75;
  (* src = "ls180.v:1444.6-1444.18" *)
  wire sdrio_clk_76;
  (* src = "ls180.v:1445.6-1445.18" *)
  wire sdrio_clk_77;
  (* src = "ls180.v:1446.6-1446.18" *)
  wire sdrio_clk_78;
  (* src = "ls180.v:1447.6-1447.18" *)
  wire sdrio_clk_79;
  (* src = "ls180.v:1374.6-1374.17" *)
  wire sdrio_clk_8;
  (* src = "ls180.v:1448.6-1448.18" *)
  wire sdrio_clk_80;
  (* src = "ls180.v:1449.6-1449.18" *)
  wire sdrio_clk_81;
  (* src = "ls180.v:1450.6-1450.18" *)
  wire sdrio_clk_82;
  (* src = "ls180.v:1451.6-1451.18" *)
  wire sdrio_clk_83;
  (* src = "ls180.v:1452.6-1452.18" *)
  wire sdrio_clk_84;
  (* src = "ls180.v:1453.6-1453.18" *)
  wire sdrio_clk_85;
  (* src = "ls180.v:1454.6-1454.18" *)
  wire sdrio_clk_86;
  (* src = "ls180.v:1455.6-1455.18" *)
  wire sdrio_clk_87;
  (* src = "ls180.v:1456.6-1456.18" *)
  wire sdrio_clk_88;
  (* src = "ls180.v:1457.6-1457.18" *)
  wire sdrio_clk_89;
  (* src = "ls180.v:1375.6-1375.17" *)
  wire sdrio_clk_9;
  (* src = "ls180.v:1458.6-1458.18" *)
  wire sdrio_clk_90;
  (* src = "ls180.v:1459.6-1459.18" *)
  wire sdrio_clk_91;
  (* src = "ls180.v:1460.6-1460.18" *)
  wire sdrio_clk_92;
  (* src = "ls180.v:1461.6-1461.18" *)
  wire sdrio_clk_93;
  (* src = "ls180.v:1462.6-1462.18" *)
  wire sdrio_clk_94;
  (* src = "ls180.v:1463.6-1463.18" *)
  wire sdrio_clk_95;
  (* src = "ls180.v:1464.6-1464.18" *)
  wire sdrio_clk_96;
  (* src = "ls180.v:1465.6-1465.18" *)
  wire sdrio_clk_97;
  (* src = "ls180.v:1466.6-1466.18" *)
  wire sdrio_clk_98;
  (* src = "ls180.v:1467.6-1467.18" *)
  wire sdrio_clk_99;
  (* src = "ls180.v:11.14-11.27" *)
  output spimaster_clk;
  (* src = "ls180.v:13.14-13.28" *)
  output spimaster_cs_n;
  (* src = "ls180.v:14.13-14.27" *)
  input spimaster_miso;
  (* src = "ls180.v:12.14-12.28" *)
  output spimaster_mosi;
  (* src = "ls180.v:1001.11-1001.47" *)
  reg [2:0] subfragments_bankmachine0_next_state;
  (* src = "ls180.v:1000.11-1000.42" *)
  reg [2:0] subfragments_bankmachine0_state;
  (* src = "ls180.v:1003.11-1003.47" *)
  reg [2:0] subfragments_bankmachine1_next_state;
  (* src = "ls180.v:1002.11-1002.42" *)
  reg [2:0] subfragments_bankmachine1_state;
  (* src = "ls180.v:1005.11-1005.47" *)
  reg [2:0] subfragments_bankmachine2_next_state;
  (* src = "ls180.v:1004.11-1004.42" *)
  reg [2:0] subfragments_bankmachine2_state;
  (* src = "ls180.v:1007.11-1007.47" *)
  reg [2:0] subfragments_bankmachine3_next_state;
  (* src = "ls180.v:1006.11-1006.42" *)
  reg [2:0] subfragments_bankmachine3_state;
  (* src = "ls180.v:991.5-991.39" *)
  reg subfragments_converter0_next_state;
  (* src = "ls180.v:990.5-990.34" *)
  reg subfragments_converter0_state;
  (* src = "ls180.v:995.5-995.39" *)
  reg subfragments_converter1_next_state;
  (* src = "ls180.v:994.5-994.34" *)
  reg subfragments_converter1_state;
  (* src = "ls180.v:1022.5-1022.25" *)
  reg subfragments_locked0;
  (* src = "ls180.v:1023.5-1023.25" *)
  reg subfragments_locked1;
  (* src = "ls180.v:1024.5-1024.25" *)
  reg subfragments_locked2;
  (* src = "ls180.v:1025.5-1025.25" *)
  reg subfragments_locked3;
  (* src = "ls180.v:1009.11-1009.46" *)
  reg [2:0] subfragments_multiplexer_next_state;
  (* src = "ls180.v:1008.11-1008.41" *)
  reg [2:0] subfragments_multiplexer_state;
  (* src = "ls180.v:1027.5-1027.41" *)
  reg subfragments_new_master_rdata_valid0;
  (* src = "ls180.v:1028.5-1028.41" *)
  reg subfragments_new_master_rdata_valid1;
  (* src = "ls180.v:1029.5-1029.41" *)
  reg subfragments_new_master_rdata_valid2;
  (* src = "ls180.v:1030.5-1030.41" *)
  reg subfragments_new_master_rdata_valid3;
  (* src = "ls180.v:1026.5-1026.40" *)
  reg subfragments_new_master_wdata_ready;
  (* src = "ls180.v:1032.5-1032.28" *)
  reg subfragments_next_state;
  (* src = "ls180.v:999.11-999.44" *)
  reg [1:0] subfragments_refresher_next_state;
  (* src = "ls180.v:998.11-998.39" *)
  reg [1:0] subfragments_refresher_state;
  (* src = "ls180.v:1012.6-1012.33" *)
  wire subfragments_roundrobin0_ce;
  (* src = "ls180.v:1011.6-1011.36" *)
  wire subfragments_roundrobin0_grant;
  (* src = "ls180.v:1010.6-1010.38" *)
  wire subfragments_roundrobin0_request;
  (* src = "ls180.v:1015.6-1015.33" *)
  wire subfragments_roundrobin1_ce;
  (* src = "ls180.v:1014.6-1014.36" *)
  wire subfragments_roundrobin1_grant;
  (* src = "ls180.v:1013.6-1013.38" *)
  wire subfragments_roundrobin1_request;
  (* src = "ls180.v:1018.6-1018.33" *)
  wire subfragments_roundrobin2_ce;
  (* src = "ls180.v:1017.6-1017.36" *)
  wire subfragments_roundrobin2_grant;
  (* src = "ls180.v:1016.6-1016.38" *)
  wire subfragments_roundrobin2_request;
  (* src = "ls180.v:1021.6-1021.33" *)
  wire subfragments_roundrobin3_ce;
  (* src = "ls180.v:1020.6-1020.36" *)
  wire subfragments_roundrobin3_grant;
  (* src = "ls180.v:1019.6-1019.38" *)
  wire subfragments_roundrobin3_request;
  (* src = "ls180.v:1031.5-1031.23" *)
  reg subfragments_state;
  (* src = "ls180.v:33.13-33.20" *)
  input sys_clk;
  (* src = "ls180.v:227.6-227.15" *)
  wire sys_clk_1;
  (* src = "ls180.v:34.13-34.20" *)
  input sys_rst;
  (* src = "ls180.v:228.6-228.15" *)
  wire sys_rst_1;
  (* src = "ls180.v:1327.5-1327.19" *)
  reg t_array_muxed0;
  (* src = "ls180.v:1328.5-1328.19" *)
  reg t_array_muxed1;
  (* src = "ls180.v:1329.5-1329.19" *)
  reg t_array_muxed2;
  (* src = "ls180.v:1336.5-1336.19" *)
  reg t_array_muxed3;
  (* src = "ls180.v:1337.5-1337.19" *)
  reg t_array_muxed4;
  (* src = "ls180.v:1338.5-1338.19" *)
  reg t_array_muxed5;
  (* src = "ls180.v:855.5-855.13" *)
  reg tx_clear;
  (* src = "ls180.v:907.11-907.26" *)
  reg [3:0] tx_fifo_consume;
  (* src = "ls180.v:912.6-912.21" *)
  wire tx_fifo_do_read;
  (* src = "ls180.v:918.6-918.27" *)
  wire tx_fifo_fifo_in_first;
  (* src = "ls180.v:919.6-919.26" *)
  wire tx_fifo_fifo_in_last;
  (* src = "ls180.v:917.12-917.40" *)
  wire [7:0] tx_fifo_fifo_in_payload_data;
  (* src = "ls180.v:921.6-921.28" *)
  wire tx_fifo_fifo_out_first;
  (* src = "ls180.v:922.6-922.27" *)
  wire tx_fifo_fifo_out_last;
  (* src = "ls180.v:920.12-920.41" *)
  wire [7:0] tx_fifo_fifo_out_payload_data;
  (* src = "ls180.v:904.11-904.25" *)
  reg [4:0] tx_fifo_level0;
  (* src = "ls180.v:916.12-916.26" *)
  wire [4:0] tx_fifo_level1;
  (* src = "ls180.v:906.11-906.26" *)
  reg [3:0] tx_fifo_produce;
  (* src = "ls180.v:913.12-913.30" *)
  wire [3:0] tx_fifo_rdport_adr;
  (* src = "ls180.v:914.12-914.32" *)
  wire [9:0] tx_fifo_rdport_dat_r;
  (* src = "ls180.v:915.6-915.23" *)
  wire tx_fifo_rdport_re;
  (* src = "ls180.v:896.6-896.16" *)
  wire tx_fifo_re;
  (* src = "ls180.v:897.5-897.21" *)
  reg tx_fifo_readable;
  (* src = "ls180.v:905.5-905.20" *)
  reg tx_fifo_replace;
  (* src = "ls180.v:888.5-888.23" *)
  reg tx_fifo_sink_first;
  (* src = "ls180.v:889.5-889.22" *)
  reg tx_fifo_sink_last;
  (* src = "ls180.v:890.12-890.37" *)
  wire [7:0] tx_fifo_sink_payload_data;
  (* src = "ls180.v:887.6-887.24" *)
  wire tx_fifo_sink_ready;
  (* src = "ls180.v:886.6-886.24" *)
  wire tx_fifo_sink_valid;
  (* src = "ls180.v:893.6-893.26" *)
  wire tx_fifo_source_first;
  (* src = "ls180.v:894.6-894.25" *)
  wire tx_fifo_source_last;
  (* src = "ls180.v:895.12-895.39" *)
  wire [7:0] tx_fifo_source_payload_data;
  (* src = "ls180.v:892.6-892.26" *)
  wire tx_fifo_source_ready;
  (* src = "ls180.v:891.6-891.26" *)
  wire tx_fifo_source_valid;
  (* src = "ls180.v:902.12-902.32" *)
  wire [9:0] tx_fifo_syncfifo_din;
  (* src = "ls180.v:903.12-903.33" *)
  wire [9:0] tx_fifo_syncfifo_dout;
  (* src = "ls180.v:900.6-900.25" *)
  wire tx_fifo_syncfifo_re;
  (* src = "ls180.v:901.6-901.31" *)
  wire tx_fifo_syncfifo_readable;
  (* src = "ls180.v:898.6-898.25" *)
  wire tx_fifo_syncfifo_we;
  (* src = "ls180.v:899.6-899.31" *)
  wire tx_fifo_syncfifo_writable;
  (* src = "ls180.v:908.11-908.29" *)
  reg [3:0] tx_fifo_wrport_adr;
  (* src = "ls180.v:909.12-909.32" *)
  wire [9:0] tx_fifo_wrport_dat_r;
  (* src = "ls180.v:911.12-911.32" *)
  wire [9:0] tx_fifo_wrport_dat_w;
  (* src = "ls180.v:910.6-910.23" *)
  wire tx_fifo_wrport_we;
  (* src = "ls180.v:856.5-856.19" *)
  reg tx_old_trigger;
  (* src = "ls180.v:853.5-853.15" *)
  reg tx_pending;
  (* src = "ls180.v:852.6-852.15" *)
  wire tx_status;
  (* src = "ls180.v:854.6-854.16" *)
  wire tx_trigger;
  (* src = "ls180.v:872.6-872.20" *)
  wire txempty_status;
  (* src = "ls180.v:873.6-873.16" *)
  wire txempty_we;
  (* src = "ls180.v:847.6-847.19" *)
  wire txfull_status;
  (* src = "ls180.v:848.6-848.15" *)
  wire txfull_we;
  (* src = "ls180.v:837.12-837.41" *)
  reg [31:0] uart_phy_phase_accumulator_rx;
  (* src = "ls180.v:827.12-827.41" *)
  reg [31:0] uart_phy_phase_accumulator_tx;
  (* src = "ls180.v:820.5-820.16" *)
  reg uart_phy_re;
  (* src = "ls180.v:838.6-838.17" *)
  wire uart_phy_rx;
  (* src = "ls180.v:841.11-841.31" *)
  reg [3:0] uart_phy_rx_bitcount;
  (* src = "ls180.v:842.5-842.21" *)
  reg uart_phy_rx_busy;
  (* src = "ls180.v:839.5-839.18" *)
  reg uart_phy_rx_r;
  (* src = "ls180.v:840.11-840.26" *)
  reg [7:0] uart_phy_rx_reg;
  (* src = "ls180.v:823.6-823.25" *)
  wire uart_phy_sink_first;
  (* src = "ls180.v:824.6-824.24" *)
  wire uart_phy_sink_last;
  (* src = "ls180.v:825.12-825.38" *)
  wire [7:0] uart_phy_sink_payload_data;
  (* src = "ls180.v:822.5-822.24" *)
  reg uart_phy_sink_ready;
  (* src = "ls180.v:821.6-821.25" *)
  wire uart_phy_sink_valid;
  (* src = "ls180.v:833.5-833.26" *)
  reg uart_phy_source_first;
  (* src = "ls180.v:834.5-834.25" *)
  reg uart_phy_source_last;
  (* src = "ls180.v:835.11-835.39" *)
  reg [7:0] uart_phy_source_payload_data;
  (* src = "ls180.v:832.6-832.27" *)
  wire uart_phy_source_ready;
  (* src = "ls180.v:831.5-831.26" *)
  reg uart_phy_source_valid;
  (* src = "ls180.v:819.12-819.28" *)
  reg [31:0] uart_phy_storage;
  (* src = "ls180.v:829.11-829.31" *)
  reg [3:0] uart_phy_tx_bitcount;
  (* src = "ls180.v:830.5-830.21" *)
  reg uart_phy_tx_busy;
  (* src = "ls180.v:828.11-828.26" *)
  reg [7:0] uart_phy_tx_reg;
  (* src = "ls180.v:836.5-836.27" *)
  reg uart_phy_uart_clk_rxen;
  (* src = "ls180.v:826.5-826.27" *)
  reg uart_phy_uart_clk_txen;
  (* src = "ls180.v:6.13-6.20" *)
  input uart_rx;
  (* src = "ls180.v:878.6-878.21" *)
  wire uart_sink_first;
  (* src = "ls180.v:879.6-879.20" *)
  wire uart_sink_last;
  (* src = "ls180.v:880.12-880.34" *)
  wire [7:0] uart_sink_payload_data;
  (* src = "ls180.v:877.6-877.21" *)
  wire uart_sink_ready;
  (* src = "ls180.v:876.6-876.21" *)
  wire uart_sink_valid;
  (* src = "ls180.v:883.6-883.23" *)
  wire uart_source_first;
  (* src = "ls180.v:884.6-884.22" *)
  wire uart_source_last;
  (* src = "ls180.v:885.12-885.36" *)
  wire [7:0] uart_source_payload_data;
  (* src = "ls180.v:882.6-882.23" *)
  wire uart_source_ready;
  (* src = "ls180.v:881.6-881.23" *)
  wire uart_source_valid;
  (* src = "ls180.v:5.13-5.20" *)
  input uart_tx;
  (* src = "ls180.v:797.5-797.17" *)
  reg wb_sdram_ack;
  (* src = "ls180.v:791.13-791.25" *)
  wire [29:0] wb_sdram_adr;
  (* src = "ls180.v:800.12-800.24" *)
  wire [1:0] wb_sdram_bte;
  (* src = "ls180.v:799.12-799.24" *)
  wire [2:0] wb_sdram_cti;
  (* src = "ls180.v:795.6-795.18" *)
  wire wb_sdram_cyc;
  (* src = "ls180.v:793.13-793.27" *)
  wire [31:0] wb_sdram_dat_r;
  (* src = "ls180.v:792.13-792.27" *)
  wire [31:0] wb_sdram_dat_w;
  (* src = "ls180.v:801.5-801.17" *)
  reg wb_sdram_err;
  (* src = "ls180.v:794.12-794.24" *)
  wire [3:0] wb_sdram_sel;
  (* src = "ls180.v:796.6-796.18" *)
  wire wb_sdram_stb;
  (* src = "ls180.v:798.6-798.17" *)
  wire wb_sdram_we;
  (* src = "ls180.v:815.5-815.19" *)
  reg wdata_consumed;
  (* src = "ls180.v:5444.12-5444.15" *)
  reg [31:0] mem [127:0];
  assign _1894_ = mem[memadr];
  (* src = "ls180.v:5464.12-5464.17" *)
  reg [31:0] mem_1 [31:0];
  assign _1895_ = mem_1[memadr_1];
  (* src = "ls180.v:5484.12-5484.19" *)
  reg [24:0] storage [7:0];
  assign _1897_ = storage[sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
  assign _1896_ = storage[sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
  (* src = "ls180.v:5498.12-5498.21" *)
  reg [24:0] storage_1 [7:0];
  assign _1899_ = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
  assign _1898_ = storage_1[sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
  (* src = "ls180.v:5512.12-5512.21" *)
  reg [24:0] storage_2 [7:0];
  assign _1901_ = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
  assign _1900_ = storage_2[sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
  (* src = "ls180.v:5526.12-5526.21" *)
  reg [24:0] storage_3 [7:0];
  assign _1903_ = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
  assign _1902_ = storage_3[sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
  (* src = "ls180.v:5540.11-5540.20" *)
  reg [9:0] storage_4 [15:0];
  assign _1905_ = storage_4[tx_fifo_rdport_adr];
  assign _1904_ = storage_4[tx_fifo_wrport_adr];
  (* src = "ls180.v:5557.11-5557.20" *)
  reg [9:0] storage_5 [15:0];
  assign _1907_ = storage_5[rx_fifo_rdport_adr];
  assign _1906_ = storage_5[rx_fifo_wrport_adr];
  assign _1022_ = libresocsim_converter0_counter + (* src = "ls180.v:1551.76-1551.113" *) 1'h1;
  assign _1023_ = libresocsim_converter1_counter + (* src = "ls180.v:1611.76-1611.113" *) 1'h1;
  assign _1024_ = converter_counter + (* src = "ls180.v:2754.52-2754.76" *) 1'h1;
  assign _1025_ = tx_fifo_level0 + (* src = "ls180.v:2854.26-2854.59" *) tx_fifo_readable;
  assign _1026_ = rx_fifo_level0 + (* src = "ls180.v:2884.26-2884.59" *) rx_fifo_readable;
  assign _1027_ = libresocsim_bus_errors + (* src = "ls180.v:4310.31-4310.60" *) 1'h1;
  assign _1028_ = sdram_sequencer_counter + (* src = "ls180.v:4399.32-4399.62" *) 1'h1;
  assign _1029_ = sdram_bankmachine0_cmd_buffer_lookahead_produce + (* src = "ls180.v:4416.55-4416.109" *) 1'h1;
  assign _1030_ = sdram_bankmachine0_cmd_buffer_lookahead_consume + (* src = "ls180.v:4419.55-4419.109" *) 1'h1;
  assign _1031_ = sdram_bankmachine0_cmd_buffer_lookahead_level + (* src = "ls180.v:4423.54-4423.106" *) 1'h1;
  assign _1032_ = sdram_bankmachine1_cmd_buffer_lookahead_produce + (* src = "ls180.v:4462.55-4462.109" *) 1'h1;
  assign _1033_ = sdram_bankmachine1_cmd_buffer_lookahead_consume + (* src = "ls180.v:4465.55-4465.109" *) 1'h1;
  assign _1034_ = sdram_bankmachine1_cmd_buffer_lookahead_level + (* src = "ls180.v:4469.54-4469.106" *) 1'h1;
  assign _1035_ = sdram_bankmachine2_cmd_buffer_lookahead_produce + (* src = "ls180.v:4508.55-4508.109" *) 1'h1;
  assign _1036_ = sdram_bankmachine2_cmd_buffer_lookahead_consume + (* src = "ls180.v:4511.55-4511.109" *) 1'h1;
  assign _1037_ = sdram_bankmachine2_cmd_buffer_lookahead_level + (* src = "ls180.v:4515.54-4515.106" *) 1'h1;
  assign _1038_ = sdram_bankmachine3_cmd_buffer_lookahead_produce + (* src = "ls180.v:4554.55-4554.109" *) 1'h1;
  assign _1039_ = sdram_bankmachine3_cmd_buffer_lookahead_consume + (* src = "ls180.v:4557.55-4557.109" *) 1'h1;
  assign _1040_ = sdram_bankmachine3_cmd_buffer_lookahead_level + (* src = "ls180.v:4561.54-4561.106" *) 1'h1;
  assign _1041_ = uart_phy_tx_bitcount + (* src = "ls180.v:4791.29-4791.56" *) 1'h1;
  assign _1042_ = uart_phy_phase_accumulator_tx + (* src = "ls180.v:4807.63-4807.111" *) uart_phy_storage;
  assign _1043_ = uart_phy_rx_bitcount + (* src = "ls180.v:4820.29-4820.56" *) 1'h1;
  assign _1044_ = uart_phy_phase_accumulator_rx + (* src = "ls180.v:4839.63-4839.111" *) uart_phy_storage;
  assign _1045_ = tx_fifo_produce + (* src = "ls180.v:4865.23-4865.45" *) 1'h1;
  assign _1046_ = tx_fifo_consume + (* src = "ls180.v:4868.23-4868.45" *) 1'h1;
  assign _1047_ = tx_fifo_level0 + (* src = "ls180.v:4872.23-4872.44" *) 1'h1;
  assign _1048_ = rx_fifo_produce + (* src = "ls180.v:4887.23-4887.45" *) 1'h1;
  assign _1049_ = rx_fifo_consume + (* src = "ls180.v:4890.23-4890.45" *) 1'h1;
  assign _1050_ = rx_fifo_level0 + (* src = "ls180.v:4894.23-4894.44" *) 1'h1;
  assign _1051_ = libresocsim_libresoc_ibus_stb & (* src = "ls180.v:1545.9-1545.70" *) libresocsim_libresoc_ibus_cyc;
  assign _1052_ = libresocsim_libresoc_ibus_stb & (* src = "ls180.v:1563.9-1563.70" *) libresocsim_libresoc_ibus_cyc;
  assign _1053_ = libresocsim_libresoc_dbus_stb & (* src = "ls180.v:1605.9-1605.70" *) libresocsim_libresoc_dbus_cyc;
  assign _1054_ = libresocsim_libresoc_dbus_stb & (* src = "ls180.v:1623.9-1623.70" *) libresocsim_libresoc_dbus_cyc;
  assign _1055_ = libresocsim_ram_bus_cyc & (* src = "ls180.v:1633.26-1633.75" *) libresocsim_ram_bus_stb;
  assign _1056_ = _1055_ & (* src = "ls180.v:1633.25-1633.101" *) libresocsim_ram_bus_we;
  assign _1057_ = _1056_ & (* src = "ls180.v:1633.24-1633.131" *) libresocsim_ram_bus_sel[0];
  assign _1058_ = libresocsim_ram_bus_cyc & (* src = "ls180.v:1634.26-1634.75" *) libresocsim_ram_bus_stb;
  assign _1059_ = _1058_ & (* src = "ls180.v:1634.25-1634.101" *) libresocsim_ram_bus_we;
  assign _1060_ = _1059_ & (* src = "ls180.v:1634.24-1634.131" *) libresocsim_ram_bus_sel[1];
  assign _1061_ = libresocsim_ram_bus_cyc & (* src = "ls180.v:1635.26-1635.75" *) libresocsim_ram_bus_stb;
  assign _1062_ = _1061_ & (* src = "ls180.v:1635.25-1635.101" *) libresocsim_ram_bus_we;
  assign _1063_ = _1062_ & (* src = "ls180.v:1635.24-1635.131" *) libresocsim_ram_bus_sel[2];
  assign _1064_ = libresocsim_ram_bus_cyc & (* src = "ls180.v:1636.26-1636.75" *) libresocsim_ram_bus_stb;
  assign _1065_ = _1064_ & (* src = "ls180.v:1636.25-1636.101" *) libresocsim_ram_bus_we;
  assign _1066_ = _1065_ & (* src = "ls180.v:1636.24-1636.131" *) libresocsim_ram_bus_sel[3];
  assign _1067_ = libresocsim_eventmanager_pending_re & (* src = "ls180.v:1645.7-1645.79" *) libresocsim_eventmanager_pending_r;
  assign _1068_ = libresocsim_eventmanager_pending_w & (* src = "ls180.v:1650.27-1650.96" *) libresocsim_eventmanager_storage;
  assign _1069_ = ram_bus_ram_bus_cyc & (* src = "ls180.v:1654.18-1654.59" *) ram_bus_ram_bus_stb;
  assign _1070_ = _1069_ & (* src = "ls180.v:1654.17-1654.81" *) ram_bus_ram_bus_we;
  assign _1071_ = _1070_ & (* src = "ls180.v:1654.16-1654.107" *) ram_bus_ram_bus_sel[0];
  assign _1072_ = ram_bus_ram_bus_cyc & (* src = "ls180.v:1655.18-1655.59" *) ram_bus_ram_bus_stb;
  assign _1073_ = _1072_ & (* src = "ls180.v:1655.17-1655.81" *) ram_bus_ram_bus_we;
  assign _1074_ = _1073_ & (* src = "ls180.v:1655.16-1655.107" *) ram_bus_ram_bus_sel[1];
  assign _1075_ = ram_bus_ram_bus_cyc & (* src = "ls180.v:1656.18-1656.59" *) ram_bus_ram_bus_stb;
  assign _1076_ = _1075_ & (* src = "ls180.v:1656.17-1656.81" *) ram_bus_ram_bus_we;
  assign _1077_ = _1076_ & (* src = "ls180.v:1656.16-1656.107" *) ram_bus_ram_bus_sel[2];
  assign _1078_ = ram_bus_ram_bus_cyc & (* src = "ls180.v:1657.18-1657.59" *) ram_bus_ram_bus_stb;
  assign _1079_ = _1078_ & (* src = "ls180.v:1657.17-1657.81" *) ram_bus_ram_bus_we;
  assign _1080_ = _1079_ & (* src = "ls180.v:1657.16-1657.107" *) ram_bus_ram_bus_sel[3];
  assign _1081_ = sdram_command_issue_re & (* src = "ls180.v:1774.35-1774.84" *) sdram_command_storage[4];
  assign _1082_ = sdram_command_issue_re & (* src = "ls180.v:1775.35-1775.84" *) sdram_command_storage[5];
  assign _1083_ = sdram_sequencer_done1 & (* src = "ls180.v:1813.33-1813.88" *) _1648_;
  assign _1084_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:1867.45-1867.104" *) sdram_bankmachine0_cmd_ready;
  assign _1085_ = _1084_ & (* src = "ls180.v:1867.44-1867.147" *) sdram_bankmachine0_cmd_payload_is_write;
  assign _1086_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:1868.44-1868.103" *) sdram_bankmachine0_cmd_ready;
  assign _1087_ = _1086_ & (* src = "ls180.v:1868.43-1868.134" *) sdram_bankmachine0_row_open;
  assign _1088_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:1869.45-1869.104" *) sdram_bankmachine0_cmd_ready;
  assign _1089_ = _1088_ & (* src = "ls180.v:1869.44-1869.135" *) sdram_bankmachine0_row_open;
  assign _1090_ = sdram_bankmachine0_cmd_buffer_lookahead_source_valid & (* src = "ls180.v:1872.7-1872.104" *) sdram_bankmachine0_cmd_buffer_source_valid;
  assign _1091_ = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (* src = "ls180.v:1901.61-1901.226" *) _2179_;
  assign _1092_ = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & (* src = "ls180.v:1902.59-1902.172" *) sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
  assign _1093_ = sdram_bankmachine0_twtpcon_ready & (* src = "ls180.v:1926.9-1926.76" *) sdram_bankmachine0_trascon_ready;
  assign _1094_ = sdram_bankmachine0_twtpcon_ready & (* src = "ls180.v:1938.9-1938.76" *) sdram_bankmachine0_trascon_ready;
  assign _1095_ = sdram_bankmachine0_cmd_ready & (* src = "ls180.v:1988.13-1988.77" *) sdram_bankmachine0_auto_precharge;
  assign _1096_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2024.45-2024.104" *) sdram_bankmachine1_cmd_ready;
  assign _1097_ = _1096_ & (* src = "ls180.v:2024.44-2024.147" *) sdram_bankmachine1_cmd_payload_is_write;
  assign _1098_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2025.44-2025.103" *) sdram_bankmachine1_cmd_ready;
  assign _1099_ = _1098_ & (* src = "ls180.v:2025.43-2025.134" *) sdram_bankmachine1_row_open;
  assign _1100_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2026.45-2026.104" *) sdram_bankmachine1_cmd_ready;
  assign _1101_ = _1100_ & (* src = "ls180.v:2026.44-2026.135" *) sdram_bankmachine1_row_open;
  assign _1102_ = sdram_bankmachine1_cmd_buffer_lookahead_source_valid & (* src = "ls180.v:2029.7-2029.104" *) sdram_bankmachine1_cmd_buffer_source_valid;
  assign _1103_ = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (* src = "ls180.v:2058.61-2058.226" *) _2184_;
  assign _1104_ = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & (* src = "ls180.v:2059.59-2059.172" *) sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
  assign _1105_ = sdram_bankmachine1_twtpcon_ready & (* src = "ls180.v:2083.9-2083.76" *) sdram_bankmachine1_trascon_ready;
  assign _1106_ = sdram_bankmachine1_twtpcon_ready & (* src = "ls180.v:2095.9-2095.76" *) sdram_bankmachine1_trascon_ready;
  assign _1107_ = sdram_bankmachine1_cmd_ready & (* src = "ls180.v:2145.13-2145.77" *) sdram_bankmachine1_auto_precharge;
  assign _1108_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2181.45-2181.104" *) sdram_bankmachine2_cmd_ready;
  assign _1109_ = _1108_ & (* src = "ls180.v:2181.44-2181.147" *) sdram_bankmachine2_cmd_payload_is_write;
  assign _1110_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2182.44-2182.103" *) sdram_bankmachine2_cmd_ready;
  assign _1111_ = _1110_ & (* src = "ls180.v:2182.43-2182.134" *) sdram_bankmachine2_row_open;
  assign _1112_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2183.45-2183.104" *) sdram_bankmachine2_cmd_ready;
  assign _1113_ = _1112_ & (* src = "ls180.v:2183.44-2183.135" *) sdram_bankmachine2_row_open;
  assign _1114_ = sdram_bankmachine2_cmd_buffer_lookahead_source_valid & (* src = "ls180.v:2186.7-2186.104" *) sdram_bankmachine2_cmd_buffer_source_valid;
  assign _1115_ = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (* src = "ls180.v:2215.61-2215.226" *) _2189_;
  assign _1116_ = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & (* src = "ls180.v:2216.59-2216.172" *) sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
  assign _1117_ = sdram_bankmachine2_twtpcon_ready & (* src = "ls180.v:2240.9-2240.76" *) sdram_bankmachine2_trascon_ready;
  assign _1118_ = sdram_bankmachine2_twtpcon_ready & (* src = "ls180.v:2252.9-2252.76" *) sdram_bankmachine2_trascon_ready;
  assign _1119_ = sdram_bankmachine2_cmd_ready & (* src = "ls180.v:2302.13-2302.77" *) sdram_bankmachine2_auto_precharge;
  assign _1120_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2338.45-2338.104" *) sdram_bankmachine3_cmd_ready;
  assign _1121_ = _1120_ & (* src = "ls180.v:2338.44-2338.147" *) sdram_bankmachine3_cmd_payload_is_write;
  assign _1122_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2339.44-2339.103" *) sdram_bankmachine3_cmd_ready;
  assign _1123_ = _1122_ & (* src = "ls180.v:2339.43-2339.134" *) sdram_bankmachine3_row_open;
  assign _1124_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2340.45-2340.104" *) sdram_bankmachine3_cmd_ready;
  assign _1125_ = _1124_ & (* src = "ls180.v:2340.44-2340.135" *) sdram_bankmachine3_row_open;
  assign _1126_ = sdram_bankmachine3_cmd_buffer_lookahead_source_valid & (* src = "ls180.v:2343.7-2343.104" *) sdram_bankmachine3_cmd_buffer_source_valid;
  assign _1127_ = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (* src = "ls180.v:2372.61-2372.226" *) _2194_;
  assign _1128_ = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & (* src = "ls180.v:2373.59-2373.172" *) sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
  assign _1129_ = sdram_bankmachine3_twtpcon_ready & (* src = "ls180.v:2397.9-2397.76" *) sdram_bankmachine3_trascon_ready;
  assign _1130_ = sdram_bankmachine3_twtpcon_ready & (* src = "ls180.v:2409.9-2409.76" *) sdram_bankmachine3_trascon_ready;
  assign _1131_ = sdram_bankmachine3_cmd_ready & (* src = "ls180.v:2459.13-2459.77" *) sdram_bankmachine3_auto_precharge;
  assign _1132_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2474.32-2474.87" *) sdram_choose_req_cmd_ready;
  assign _1133_ = sdram_choose_req_cmd_payload_ras & (* src = "ls180.v:2474.93-2474.163" *) _1991_;
  assign _1134_ = _1133_ & (* src = "ls180.v:2474.92-2474.201" *) _1992_;
  assign _1135_ = _1132_ & (* src = "ls180.v:2474.31-2474.202" *) _1134_;
  assign _1136_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2475.32-2475.87" *) sdram_choose_req_cmd_ready;
  assign _1137_ = sdram_choose_req_cmd_payload_ras & (* src = "ls180.v:2475.93-2475.163" *) _1993_;
  assign _1138_ = _1137_ & (* src = "ls180.v:2475.92-2475.201" *) _1994_;
  assign _1139_ = _1136_ & (* src = "ls180.v:2475.31-2475.202" *) _1138_;
  assign _1140_ = sdram_trrdcon_ready & (* src = "ls180.v:2476.29-2476.70" *) sdram_tfawcon_ready;
  assign _1141_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2477.32-2477.87" *) sdram_choose_req_cmd_ready;
  assign _1142_ = _1141_ & (* src = "ls180.v:2477.31-2477.169" *) _2196_;
  assign _1143_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2479.32-2479.87" *) sdram_choose_req_cmd_ready;
  assign _1144_ = _1143_ & (* src = "ls180.v:2479.31-2479.128" *) sdram_choose_req_cmd_payload_is_write;
  assign _1145_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:2480.35-2480.104" *) sdram_bankmachine0_cmd_payload_is_read;
  assign _1146_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2480.109-2480.178" *) sdram_bankmachine1_cmd_payload_is_read;
  assign _1147_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2480.184-2480.253" *) sdram_bankmachine2_cmd_payload_is_read;
  assign _1148_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2480.259-2480.328" *) sdram_bankmachine3_cmd_payload_is_read;
  assign _1149_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:2481.36-2481.106" *) sdram_bankmachine0_cmd_payload_is_write;
  assign _1150_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2481.111-2481.181" *) sdram_bankmachine1_cmd_payload_is_write;
  assign _1151_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2481.187-2481.257" *) sdram_bankmachine2_cmd_payload_is_write;
  assign _1152_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2481.263-2481.333" *) sdram_bankmachine3_cmd_payload_is_write;
  assign _1153_ = sdram_bankmachine0_refresh_gnt & (* src = "ls180.v:2488.33-2488.96" *) sdram_bankmachine1_refresh_gnt;
  assign _1154_ = _1153_ & (* src = "ls180.v:2488.32-2488.130" *) sdram_bankmachine2_refresh_gnt;
  assign _1155_ = _1154_ & (* src = "ls180.v:2488.31-2488.164" *) sdram_bankmachine3_refresh_gnt;
  assign _1156_ = sdram_bankmachine0_cmd_payload_is_cmd & (* src = "ls180.v:2494.67-2494.133" *) sdram_choose_cmd_want_cmds;
  assign _1157_ = sdram_bankmachine0_cmd_payload_ras & (* src = "ls180.v:2494.142-2494.216" *) _1996_;
  assign _1158_ = _1157_ & (* src = "ls180.v:2494.141-2494.256" *) _1997_;
  assign _1159_ = _1156_ & (* src = "ls180.v:2494.66-2494.293" *) _2203_;
  assign _1160_ = _1659_ & (* src = "ls180.v:2494.298-2494.445" *) _1660_;
  assign _1161_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:2494.33-2494.447" *) _2204_;
  assign _1162_ = sdram_bankmachine1_cmd_payload_is_cmd & (* src = "ls180.v:2495.67-2495.133" *) sdram_choose_cmd_want_cmds;
  assign _1163_ = sdram_bankmachine1_cmd_payload_ras & (* src = "ls180.v:2495.142-2495.216" *) _1999_;
  assign _1164_ = _1163_ & (* src = "ls180.v:2495.141-2495.256" *) _2000_;
  assign _1165_ = _1162_ & (* src = "ls180.v:2495.66-2495.293" *) _2205_;
  assign _1166_ = _1661_ & (* src = "ls180.v:2495.298-2495.445" *) _1662_;
  assign _1167_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2495.33-2495.447" *) _2206_;
  assign _1168_ = sdram_bankmachine2_cmd_payload_is_cmd & (* src = "ls180.v:2496.67-2496.133" *) sdram_choose_cmd_want_cmds;
  assign _1169_ = sdram_bankmachine2_cmd_payload_ras & (* src = "ls180.v:2496.142-2496.216" *) _2002_;
  assign _1170_ = _1169_ & (* src = "ls180.v:2496.141-2496.256" *) _2003_;
  assign _1171_ = _1168_ & (* src = "ls180.v:2496.66-2496.293" *) _2207_;
  assign _1172_ = _1663_ & (* src = "ls180.v:2496.298-2496.445" *) _1664_;
  assign _1173_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2496.33-2496.447" *) _2208_;
  assign _1174_ = sdram_bankmachine3_cmd_payload_is_cmd & (* src = "ls180.v:2497.67-2497.133" *) sdram_choose_cmd_want_cmds;
  assign _1175_ = sdram_bankmachine3_cmd_payload_ras & (* src = "ls180.v:2497.142-2497.216" *) _2005_;
  assign _1176_ = _1175_ & (* src = "ls180.v:2497.141-2497.256" *) _2006_;
  assign _1177_ = _1174_ & (* src = "ls180.v:2497.66-2497.293" *) _2209_;
  assign _1178_ = _1665_ & (* src = "ls180.v:2497.298-2497.445" *) _1666_;
  assign _1179_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2497.33-2497.447" *) _2210_;
  assign _1180_ = sdram_bankmachine0_cmd_payload_is_cmd & (* src = "ls180.v:2527.67-2527.133" *) sdram_choose_req_want_cmds;
  assign _1181_ = sdram_bankmachine0_cmd_payload_ras & (* src = "ls180.v:2527.142-2527.216" *) _2009_;
  assign _1182_ = _1181_ & (* src = "ls180.v:2527.141-2527.256" *) _2010_;
  assign _1183_ = _1180_ & (* src = "ls180.v:2527.66-2527.293" *) _2212_;
  assign _1184_ = _1667_ & (* src = "ls180.v:2527.298-2527.445" *) _1668_;
  assign _1185_ = sdram_bankmachine0_cmd_valid & (* src = "ls180.v:2527.33-2527.447" *) _2213_;
  assign _1186_ = sdram_bankmachine1_cmd_payload_is_cmd & (* src = "ls180.v:2528.67-2528.133" *) sdram_choose_req_want_cmds;
  assign _1187_ = sdram_bankmachine1_cmd_payload_ras & (* src = "ls180.v:2528.142-2528.216" *) _2012_;
  assign _1188_ = _1187_ & (* src = "ls180.v:2528.141-2528.256" *) _2013_;
  assign _1189_ = _1186_ & (* src = "ls180.v:2528.66-2528.293" *) _2214_;
  assign _1190_ = _1669_ & (* src = "ls180.v:2528.298-2528.445" *) _1670_;
  assign _1191_ = sdram_bankmachine1_cmd_valid & (* src = "ls180.v:2528.33-2528.447" *) _2215_;
  assign _1192_ = sdram_bankmachine2_cmd_payload_is_cmd & (* src = "ls180.v:2529.67-2529.133" *) sdram_choose_req_want_cmds;
  assign _1193_ = sdram_bankmachine2_cmd_payload_ras & (* src = "ls180.v:2529.142-2529.216" *) _2015_;
  assign _1194_ = _1193_ & (* src = "ls180.v:2529.141-2529.256" *) _2016_;
  assign _1195_ = _1192_ & (* src = "ls180.v:2529.66-2529.293" *) _2216_;
  assign _1196_ = _1671_ & (* src = "ls180.v:2529.298-2529.445" *) _1672_;
  assign _1197_ = sdram_bankmachine2_cmd_valid & (* src = "ls180.v:2529.33-2529.447" *) _2217_;
  assign _1198_ = sdram_bankmachine3_cmd_payload_is_cmd & (* src = "ls180.v:2530.67-2530.133" *) sdram_choose_req_want_cmds;
  assign _1199_ = sdram_bankmachine3_cmd_payload_ras & (* src = "ls180.v:2530.142-2530.216" *) _2018_;
  assign _1200_ = _1199_ & (* src = "ls180.v:2530.141-2530.256" *) _2019_;
  assign _1201_ = _1198_ & (* src = "ls180.v:2530.66-2530.293" *) _2218_;
  assign _1202_ = _1673_ & (* src = "ls180.v:2530.298-2530.445" *) _1674_;
  assign _1203_ = sdram_bankmachine3_cmd_valid & (* src = "ls180.v:2530.33-2530.447" *) _2219_;
  assign _1204_ = sdram_choose_cmd_cmd_valid & (* src = "ls180.v:2559.8-2559.63" *) sdram_choose_cmd_cmd_ready;
  assign _1205_ = _1204_ & (* src = "ls180.v:2559.7-2559.99" *) _1675_;
  assign _1206_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2562.8-2562.63" *) sdram_choose_req_cmd_ready;
  assign _1207_ = _1206_ & (* src = "ls180.v:2562.7-2562.99" *) _1676_;
  assign _1208_ = sdram_choose_cmd_cmd_valid & (* src = "ls180.v:2568.8-2568.63" *) sdram_choose_cmd_cmd_ready;
  assign _1209_ = _1208_ & (* src = "ls180.v:2568.7-2568.99" *) _1677_;
  assign _1210_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2571.8-2571.63" *) sdram_choose_req_cmd_ready;
  assign _1211_ = _1210_ & (* src = "ls180.v:2571.7-2571.99" *) _1678_;
  assign _1212_ = sdram_choose_cmd_cmd_valid & (* src = "ls180.v:2577.8-2577.63" *) sdram_choose_cmd_cmd_ready;
  assign _1213_ = _1212_ & (* src = "ls180.v:2577.7-2577.99" *) _1679_;
  assign _1214_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2580.8-2580.63" *) sdram_choose_req_cmd_ready;
  assign _1215_ = _1214_ & (* src = "ls180.v:2580.7-2580.99" *) _1680_;
  assign _1216_ = sdram_choose_cmd_cmd_valid & (* src = "ls180.v:2586.8-2586.63" *) sdram_choose_cmd_cmd_ready;
  assign _1217_ = _1216_ & (* src = "ls180.v:2586.7-2586.99" *) _1681_;
  assign _1218_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:2589.8-2589.63" *) sdram_choose_req_cmd_ready;
  assign _1219_ = _1218_ & (* src = "ls180.v:2589.7-2589.99" *) _1682_;
  assign _1220_ = sdram_choose_req_cmd_payload_ras & (* src = "ls180.v:2614.61-2614.131" *) _2022_;
  assign _1221_ = _1220_ & (* src = "ls180.v:2614.60-2614.169" *) _2023_;
  assign _1222_ = sdram_cas_allowed & (* src = "ls180.v:2614.36-2614.192" *) _2221_;
  assign _1223_ = sdram_choose_req_cmd_payload_ras & (* src = "ls180.v:2652.61-2652.131" *) _2026_;
  assign _1224_ = _1223_ & (* src = "ls180.v:2652.60-2652.169" *) _2027_;
  assign _1225_ = sdram_cas_allowed & (* src = "ls180.v:2652.36-2652.192" *) _2223_;
  assign _1226_ = sdram_interface_bank1_lock & (* src = "ls180.v:2670.115-2670.184" *) _1684_;
  assign _1227_ = sdram_interface_bank2_lock & (* src = "ls180.v:2670.190-2670.259" *) _1685_;
  assign _1228_ = sdram_interface_bank3_lock & (* src = "ls180.v:2670.265-2670.334" *) _1686_;
  assign _1229_ = _1683_ & (* src = "ls180.v:2670.46-2670.337" *) _2030_;
  assign _1230_ = _1229_ & (* src = "ls180.v:2670.45-2670.355" *) port_cmd_valid;
  assign _1231_ = _2031_ & (* src = "ls180.v:2671.39-2671.101" *) _2032_;
  assign _1232_ = sdram_interface_bank0_lock & (* src = "ls180.v:2675.115-2675.184" *) _1688_;
  assign _1233_ = sdram_interface_bank2_lock & (* src = "ls180.v:2675.190-2675.259" *) _1689_;
  assign _1234_ = sdram_interface_bank3_lock & (* src = "ls180.v:2675.265-2675.334" *) _1690_;
  assign _1235_ = _1687_ & (* src = "ls180.v:2675.46-2675.337" *) _2033_;
  assign _1236_ = _1235_ & (* src = "ls180.v:2675.45-2675.355" *) port_cmd_valid;
  assign _1237_ = _2034_ & (* src = "ls180.v:2676.39-2676.101" *) _2035_;
  assign _1238_ = sdram_interface_bank0_lock & (* src = "ls180.v:2680.115-2680.184" *) _1692_;
  assign _1239_ = sdram_interface_bank1_lock & (* src = "ls180.v:2680.190-2680.259" *) _1693_;
  assign _1240_ = sdram_interface_bank3_lock & (* src = "ls180.v:2680.265-2680.334" *) _1694_;
  assign _1241_ = _1691_ & (* src = "ls180.v:2680.46-2680.337" *) _2036_;
  assign _1242_ = _1241_ & (* src = "ls180.v:2680.45-2680.355" *) port_cmd_valid;
  assign _1243_ = _2037_ & (* src = "ls180.v:2681.39-2681.101" *) _2038_;
  assign _1244_ = sdram_interface_bank0_lock & (* src = "ls180.v:2685.115-2685.184" *) _1696_;
  assign _1245_ = sdram_interface_bank1_lock & (* src = "ls180.v:2685.190-2685.259" *) _1697_;
  assign _1246_ = sdram_interface_bank2_lock & (* src = "ls180.v:2685.265-2685.334" *) _1698_;
  assign _1247_ = _1695_ & (* src = "ls180.v:2685.46-2685.337" *) _2039_;
  assign _1248_ = _1247_ & (* src = "ls180.v:2685.45-2685.355" *) port_cmd_valid;
  assign _1249_ = _2040_ & (* src = "ls180.v:2686.39-2686.101" *) _2041_;
  assign _1250_ = sdram_interface_bank1_lock & (* src = "ls180.v:2690.151-2690.220" *) _1701_;
  assign _1251_ = sdram_interface_bank2_lock & (* src = "ls180.v:2690.226-2690.295" *) _1702_;
  assign _1252_ = sdram_interface_bank3_lock & (* src = "ls180.v:2690.301-2690.370" *) _1703_;
  assign _1253_ = _1700_ & (* src = "ls180.v:2690.82-2690.373" *) _2042_;
  assign _1254_ = _1699_ & (* src = "ls180.v:2690.38-2690.374" *) _1253_;
  assign _1255_ = _1254_ & (* src = "ls180.v:2690.37-2690.405" *) sdram_interface_bank0_ready;
  assign _1256_ = sdram_interface_bank0_lock & (* src = "ls180.v:2690.525-2690.594" *) _1706_;
  assign _1257_ = sdram_interface_bank2_lock & (* src = "ls180.v:2690.600-2690.669" *) _1707_;
  assign _1258_ = sdram_interface_bank3_lock & (* src = "ls180.v:2690.675-2690.744" *) _1708_;
  assign _1259_ = _1705_ & (* src = "ls180.v:2690.456-2690.747" *) _2043_;
  assign _1260_ = _1704_ & (* src = "ls180.v:2690.412-2690.748" *) _1259_;
  assign _1261_ = _1260_ & (* src = "ls180.v:2690.411-2690.779" *) sdram_interface_bank1_ready;
  assign _1262_ = sdram_interface_bank0_lock & (* src = "ls180.v:2690.899-2690.968" *) _1711_;
  assign _1263_ = sdram_interface_bank1_lock & (* src = "ls180.v:2690.974-2690.1043" *) _1712_;
  assign _1264_ = sdram_interface_bank3_lock & (* src = "ls180.v:2690.1049-2690.1118" *) _1713_;
  assign _1265_ = _1710_ & (* src = "ls180.v:2690.830-2690.1121" *) _2044_;
  assign _1266_ = _1709_ & (* src = "ls180.v:2690.786-2690.1122" *) _1265_;
  assign _1267_ = _1266_ & (* src = "ls180.v:2690.785-2690.1153" *) sdram_interface_bank2_ready;
  assign _1268_ = sdram_interface_bank0_lock & (* src = "ls180.v:2690.1273-2690.1342" *) _1716_;
  assign _1269_ = sdram_interface_bank1_lock & (* src = "ls180.v:2690.1348-2690.1417" *) _1717_;
  assign _1270_ = sdram_interface_bank2_lock & (* src = "ls180.v:2690.1423-2690.1492" *) _1718_;
  assign _1271_ = _1715_ & (* src = "ls180.v:2690.1204-2690.1495" *) _2045_;
  assign _1272_ = _1714_ & (* src = "ls180.v:2690.1160-2690.1496" *) _1271_;
  assign _1273_ = _1272_ & (* src = "ls180.v:2690.1159-2690.1527" *) sdram_interface_bank3_ready;
  assign _1274_ = wb_sdram_stb & (* src = "ls180.v:2748.9-2748.36" *) wb_sdram_cyc;
  assign _1275_ = wb_sdram_stb & (* src = "ls180.v:2766.9-2766.36" *) wb_sdram_cyc;
  assign _1276_ = litedram_wb_cyc & (* src = "ls180.v:2779.27-2779.60" *) litedram_wb_stb;
  assign _1277_ = _1276_ & (* src = "ls180.v:2779.26-2779.79" *) _2051_;
  assign _1278_ = _2254_ & (* src = "ls180.v:2780.29-2780.82" *) port_cmd_payload_we;
  assign _1279_ = _1278_ & (* src = "ls180.v:2780.28-2780.103" *) _2052_;
  assign _1280_ = _2255_ & (* src = "ls180.v:2781.28-2781.84" *) _2053_;
  assign _1281_ = litedram_wb_we & (* src = "ls180.v:2782.39-2782.65" *) ack_wdata;
  assign _1282_ = _2054_ & (* src = "ls180.v:2782.70-2782.99" *) ack_rdata;
  assign _1283_ = ack_cmd & (* src = "ls180.v:2782.27-2782.101" *) _2256_;
  assign _1284_ = port_cmd_valid & (* src = "ls180.v:2783.20-2783.51" *) port_cmd_ready;
  assign _1285_ = port_wdata_valid & (* src = "ls180.v:2784.22-2784.57" *) port_wdata_ready;
  assign _1286_ = port_rdata_valid & (* src = "ls180.v:2785.21-2785.56" *) port_rdata_ready;
  assign _1287_ = 1'h0 & (* src = "ls180.v:2814.44-2814.58" *) rxtx_we;
  assign _1288_ = eventmanager_pending_re & (* src = "ls180.v:2818.7-2818.58" *) eventmanager_pending_r[0];
  assign _1289_ = eventmanager_pending_re & (* src = "ls180.v:2829.7-2829.58" *) eventmanager_pending_r[1];
  assign _1290_ = eventmanager_pending_w[0] & (* src = "ls180.v:2838.16-2838.67" *) eventmanager_storage[0];
  assign _1291_ = eventmanager_pending_w[1] & (* src = "ls180.v:2838.72-2838.123" *) eventmanager_storage[1];
  assign _1292_ = tx_fifo_syncfifo_readable & (* src = "ls180.v:2853.31-2853.93" *) _2261_;
  assign _1293_ = tx_fifo_syncfifo_we & (* src = "ls180.v:2864.29-2864.96" *) _2262_;
  assign _1294_ = tx_fifo_syncfifo_readable & (* src = "ls180.v:2865.27-2865.74" *) tx_fifo_syncfifo_re;
  assign _1295_ = rx_fifo_syncfifo_readable & (* src = "ls180.v:2883.31-2883.93" *) _2263_;
  assign _1296_ = rx_fifo_syncfifo_we & (* src = "ls180.v:2894.29-2894.96" *) _2264_;
  assign _1297_ = rx_fifo_syncfifo_readable & (* src = "ls180.v:2895.27-2895.74" *) rx_fifo_syncfifo_re;
  assign _1298_ = libresocsim_libresocsim_wishbone_cyc & (* src = "ls180.v:2992.9-2992.84" *) libresocsim_libresocsim_wishbone_stb;
  assign _1299_ = libresocsim_libresocsim_wishbone_we & (* src = "ls180.v:2995.60-2995.144" *) _1968_;
  assign _1300_ = libresocsim_shared_ack & (* src = "ls180.v:3013.58-3013.110" *) _1721_;
  assign _1301_ = libresocsim_shared_ack & (* src = "ls180.v:3014.58-3014.110" *) _1722_;
  assign _1302_ = libresocsim_shared_ack & (* src = "ls180.v:3015.44-3015.96" *) _1723_;
  assign _1303_ = libresocsim_shared_err & (* src = "ls180.v:3016.58-3016.110" *) _1724_;
  assign _1304_ = libresocsim_shared_err & (* src = "ls180.v:3017.58-3017.110" *) _1725_;
  assign _1305_ = libresocsim_shared_err & (* src = "ls180.v:3018.44-3018.96" *) _1726_;
  assign _1306_ = libresocsim_shared_cyc & (* src = "ls180.v:3071.35-3071.84" *) libresocsim_slave_sel[0];
  assign _1307_ = libresocsim_shared_cyc & (* src = "ls180.v:3072.31-3072.80" *) libresocsim_slave_sel[1];
  assign _1308_ = libresocsim_shared_cyc & (* src = "ls180.v:3073.45-3073.94" *) libresocsim_slave_sel[2];
  assign _1309_ = libresocsim_shared_cyc & (* src = "ls180.v:3074.45-3074.94" *) libresocsim_slave_sel[3];
  assign _1310_ = libresocsim_shared_cyc & (* src = "ls180.v:3075.24-3075.73" *) libresocsim_slave_sel[4];
  assign _1311_ = libresocsim_shared_cyc & (* src = "ls180.v:3076.48-3076.97" *) libresocsim_slave_sel[5];
  assign _1312_ = libresocsim_shared_stb & (* src = "ls180.v:3078.29-3078.76" *) libresocsim_shared_cyc;
  assign _1313_ = _1312_ & (* src = "ls180.v:3078.28-3078.105" *) _2063_;
  assign _1314_ = { libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0], libresocsim_slave_sel_r[0] } & (* src = "ls180.v:3084.36-3084.96" *) libresocsim_ram_bus_dat_r;
  assign _1315_ = { libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1], libresocsim_slave_sel_r[1] } & (* src = "ls180.v:3084.101-3084.157" *) ram_bus_ram_bus_dat_r;
  assign _1316_ = { libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2], libresocsim_slave_sel_r[2] } & (* src = "ls180.v:3084.163-3084.233" *) libresocsim_libresoc_xics_icp_dat_r;
  assign _1317_ = { libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3], libresocsim_slave_sel_r[3] } & (* src = "ls180.v:3084.239-3084.309" *) libresocsim_libresoc_xics_ics_dat_r;
  assign _1318_ = { libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4], libresocsim_slave_sel_r[4] } & (* src = "ls180.v:3084.315-3084.364" *) wb_sdram_dat_r;
  assign _1319_ = { libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5], libresocsim_slave_sel_r[5] } & (* src = "ls180.v:3084.370-3084.443" *) libresocsim_libresocsim_wishbone_dat_r;
  assign _1320_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3094.43-3094.104" *) libresocsim_interface0_bank_bus_we;
  assign _1321_ = _1320_ & (* src = "ls180.v:3094.42-3094.158" *) _1735_;
  assign _1322_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3095.43-3095.107" *) _2064_;
  assign _1323_ = _1322_ & (* src = "ls180.v:3095.42-3095.161" *) _1736_;
  assign _1324_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3097.45-3097.106" *) libresocsim_interface0_bank_bus_we;
  assign _1325_ = _1324_ & (* src = "ls180.v:3097.44-3097.160" *) _1737_;
  assign _1326_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3098.45-3098.109" *) _2065_;
  assign _1327_ = _1326_ & (* src = "ls180.v:3098.44-3098.163" *) _1738_;
  assign _1328_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3100.45-3100.106" *) libresocsim_interface0_bank_bus_we;
  assign _1329_ = _1328_ & (* src = "ls180.v:3100.44-3100.160" *) _1739_;
  assign _1330_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3101.45-3101.109" *) _2066_;
  assign _1331_ = _1330_ & (* src = "ls180.v:3101.44-3101.163" *) _1740_;
  assign _1332_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3103.45-3103.106" *) libresocsim_interface0_bank_bus_we;
  assign _1333_ = _1332_ & (* src = "ls180.v:3103.44-3103.160" *) _1741_;
  assign _1334_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3104.45-3104.109" *) _2067_;
  assign _1335_ = _1334_ & (* src = "ls180.v:3104.44-3104.163" *) _1742_;
  assign _1336_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3106.45-3106.106" *) libresocsim_interface0_bank_bus_we;
  assign _1337_ = _1336_ & (* src = "ls180.v:3106.44-3106.160" *) _1743_;
  assign _1338_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3107.45-3107.109" *) _2068_;
  assign _1339_ = _1338_ & (* src = "ls180.v:3107.44-3107.163" *) _1744_;
  assign _1340_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3109.48-3109.109" *) libresocsim_interface0_bank_bus_we;
  assign _1341_ = _1340_ & (* src = "ls180.v:3109.47-3109.163" *) _1745_;
  assign _1342_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3110.48-3110.112" *) _2069_;
  assign _1343_ = _1342_ & (* src = "ls180.v:3110.47-3110.166" *) _1746_;
  assign _1344_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3112.48-3112.109" *) libresocsim_interface0_bank_bus_we;
  assign _1345_ = _1344_ & (* src = "ls180.v:3112.47-3112.163" *) _1747_;
  assign _1346_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3113.48-3113.112" *) _2070_;
  assign _1347_ = _1346_ & (* src = "ls180.v:3113.47-3113.166" *) _1748_;
  assign _1348_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3115.48-3115.109" *) libresocsim_interface0_bank_bus_we;
  assign _1349_ = _1348_ & (* src = "ls180.v:3115.47-3115.163" *) _1749_;
  assign _1350_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3116.48-3116.112" *) _2071_;
  assign _1351_ = _1350_ & (* src = "ls180.v:3116.47-3116.166" *) _1750_;
  assign _1352_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3118.48-3118.109" *) libresocsim_interface0_bank_bus_we;
  assign _1353_ = _1352_ & (* src = "ls180.v:3118.47-3118.163" *) _1751_;
  assign _1354_ = libresocsim_csrbank0_sel & (* src = "ls180.v:3119.48-3119.112" *) _2072_;
  assign _1355_ = _1354_ & (* src = "ls180.v:3119.47-3119.166" *) _1752_;
  assign _1356_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3132.40-3132.101" *) libresocsim_interface1_bank_bus_we;
  assign _1357_ = _1356_ & (* src = "ls180.v:3132.39-3132.155" *) _1754_;
  assign _1358_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3133.40-3133.104" *) _2073_;
  assign _1359_ = _1358_ & (* src = "ls180.v:3133.39-3133.158" *) _1755_;
  assign _1360_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3135.39-3135.100" *) libresocsim_interface1_bank_bus_we;
  assign _1361_ = _1360_ & (* src = "ls180.v:3135.38-3135.154" *) _1756_;
  assign _1362_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3136.39-3136.103" *) _2074_;
  assign _1363_ = _1362_ & (* src = "ls180.v:3136.38-3136.157" *) _1757_;
  assign _1364_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3138.41-3138.102" *) libresocsim_interface1_bank_bus_we;
  assign _1365_ = _1364_ & (* src = "ls180.v:3138.40-3138.156" *) _1758_;
  assign _1366_ = libresocsim_csrbank1_sel & (* src = "ls180.v:3139.41-3139.105" *) _2075_;
  assign _1367_ = _1366_ & (* src = "ls180.v:3139.40-3139.159" *) _1759_;
  assign _1368_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3146.40-3146.101" *) libresocsim_interface2_bank_bus_we;
  assign _1369_ = _1368_ & (* src = "ls180.v:3146.39-3146.155" *) _1761_;
  assign _1370_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3147.40-3147.104" *) _2076_;
  assign _1371_ = _1370_ & (* src = "ls180.v:3147.39-3147.158" *) _1762_;
  assign _1372_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3149.39-3149.100" *) libresocsim_interface2_bank_bus_we;
  assign _1373_ = _1372_ & (* src = "ls180.v:3149.38-3149.154" *) _1763_;
  assign _1374_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3150.39-3150.103" *) _2077_;
  assign _1375_ = _1374_ & (* src = "ls180.v:3150.38-3150.157" *) _1764_;
  assign _1376_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3152.41-3152.102" *) libresocsim_interface2_bank_bus_we;
  assign _1377_ = _1376_ & (* src = "ls180.v:3152.40-3152.156" *) _1765_;
  assign _1378_ = libresocsim_csrbank2_sel & (* src = "ls180.v:3153.41-3153.105" *) _2078_;
  assign _1379_ = _1378_ & (* src = "ls180.v:3153.40-3153.159" *) _1766_;
  assign _1380_ = libresocsim_csrbank3_sel & (* src = "ls180.v:3160.39-3160.100" *) libresocsim_interface3_bank_bus_we;
  assign _1381_ = _1380_ & (* src = "ls180.v:3160.38-3160.152" *) _1768_;
  assign _1382_ = libresocsim_csrbank3_sel & (* src = "ls180.v:3161.39-3161.103" *) _2079_;
  assign _1383_ = _1382_ & (* src = "ls180.v:3161.38-3161.155" *) _1769_;
  assign _1384_ = libresocsim_csrbank3_sel & (* src = "ls180.v:3163.38-3163.99" *) libresocsim_interface3_bank_bus_we;
  assign _1385_ = _1384_ & (* src = "ls180.v:3163.37-3163.151" *) _1770_;
  assign _1386_ = libresocsim_csrbank3_sel & (* src = "ls180.v:3164.38-3164.102" *) _2080_;
  assign _1387_ = _1386_ & (* src = "ls180.v:3164.37-3164.154" *) _1771_;
  assign _1388_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3174.50-3174.111" *) libresocsim_interface4_bank_bus_we;
  assign _1389_ = _1388_ & (* src = "ls180.v:3174.49-3174.165" *) _1773_;
  assign _1390_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3175.50-3175.114" *) _2081_;
  assign _1391_ = _1390_ & (* src = "ls180.v:3175.49-3175.168" *) _1774_;
  assign _1392_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3177.54-3177.115" *) libresocsim_interface4_bank_bus_we;
  assign _1393_ = _1392_ & (* src = "ls180.v:3177.53-3177.169" *) _1775_;
  assign _1394_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3178.54-3178.118" *) _2082_;
  assign _1395_ = _1394_ & (* src = "ls180.v:3178.53-3178.172" *) _1776_;
  assign _1396_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3180.35-3180.96" *) libresocsim_interface4_bank_bus_we;
  assign _1397_ = _1396_ & (* src = "ls180.v:3180.34-3180.150" *) _1777_;
  assign _1398_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3181.35-3181.99" *) _2083_;
  assign _1399_ = _1398_ & (* src = "ls180.v:3181.34-3181.153" *) _1778_;
  assign _1400_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3183.54-3183.115" *) libresocsim_interface4_bank_bus_we;
  assign _1401_ = _1400_ & (* src = "ls180.v:3183.53-3183.169" *) _1779_;
  assign _1402_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3184.54-3184.118" *) _2084_;
  assign _1403_ = _1402_ & (* src = "ls180.v:3184.53-3184.172" *) _1780_;
  assign _1404_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3186.54-3186.115" *) libresocsim_interface4_bank_bus_we;
  assign _1405_ = _1404_ & (* src = "ls180.v:3186.53-3186.169" *) _1781_;
  assign _1406_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3187.54-3187.118" *) _2085_;
  assign _1407_ = _1406_ & (* src = "ls180.v:3187.53-3187.172" *) _1782_;
  assign _1408_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3189.55-3189.116" *) libresocsim_interface4_bank_bus_we;
  assign _1409_ = _1408_ & (* src = "ls180.v:3189.54-3189.170" *) _1783_;
  assign _1410_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3190.55-3190.119" *) _2086_;
  assign _1411_ = _1410_ & (* src = "ls180.v:3190.54-3190.173" *) _1784_;
  assign _1412_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3192.53-3192.114" *) libresocsim_interface4_bank_bus_we;
  assign _1413_ = _1412_ & (* src = "ls180.v:3192.52-3192.168" *) _1785_;
  assign _1414_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3193.53-3193.117" *) _2087_;
  assign _1415_ = _1414_ & (* src = "ls180.v:3193.52-3193.171" *) _1786_;
  assign _1416_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3195.53-3195.114" *) libresocsim_interface4_bank_bus_we;
  assign _1417_ = _1416_ & (* src = "ls180.v:3195.52-3195.168" *) _1787_;
  assign _1418_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3196.53-3196.117" *) _2088_;
  assign _1419_ = _1418_ & (* src = "ls180.v:3196.52-3196.171" *) _1788_;
  assign _1420_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3198.53-3198.114" *) libresocsim_interface4_bank_bus_we;
  assign _1421_ = _1420_ & (* src = "ls180.v:3198.52-3198.168" *) _1789_;
  assign _1422_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3199.53-3199.117" *) _2089_;
  assign _1423_ = _1422_ & (* src = "ls180.v:3199.52-3199.171" *) _1790_;
  assign _1424_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3201.53-3201.114" *) libresocsim_interface4_bank_bus_we;
  assign _1425_ = _1424_ & (* src = "ls180.v:3201.52-3201.168" *) _1791_;
  assign _1426_ = libresocsim_csrbank4_sel & (* src = "ls180.v:3202.53-3202.117" *) _2090_;
  assign _1427_ = _1426_ & (* src = "ls180.v:3202.52-3202.171" *) _1792_;
  assign _1428_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3219.42-3219.103" *) libresocsim_interface5_bank_bus_we;
  assign _1429_ = _1428_ & (* src = "ls180.v:3219.41-3219.157" *) _1794_;
  assign _1430_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3220.42-3220.106" *) _2091_;
  assign _1431_ = _1430_ & (* src = "ls180.v:3220.41-3220.160" *) _1795_;
  assign _1432_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3222.42-3222.103" *) libresocsim_interface5_bank_bus_we;
  assign _1433_ = _1432_ & (* src = "ls180.v:3222.41-3222.157" *) _1796_;
  assign _1434_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3223.42-3223.106" *) _2092_;
  assign _1435_ = _1434_ & (* src = "ls180.v:3223.41-3223.160" *) _1797_;
  assign _1436_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3225.42-3225.103" *) libresocsim_interface5_bank_bus_we;
  assign _1437_ = _1436_ & (* src = "ls180.v:3225.41-3225.157" *) _1798_;
  assign _1438_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3226.42-3226.106" *) _2093_;
  assign _1439_ = _1438_ & (* src = "ls180.v:3226.41-3226.160" *) _1799_;
  assign _1440_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3228.42-3228.103" *) libresocsim_interface5_bank_bus_we;
  assign _1441_ = _1440_ & (* src = "ls180.v:3228.41-3228.157" *) _1800_;
  assign _1442_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3229.42-3229.106" *) _2094_;
  assign _1443_ = _1442_ & (* src = "ls180.v:3229.41-3229.160" *) _1801_;
  assign _1444_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3231.44-3231.105" *) libresocsim_interface5_bank_bus_we;
  assign _1445_ = _1444_ & (* src = "ls180.v:3231.43-3231.159" *) _1802_;
  assign _1446_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3232.44-3232.108" *) _2095_;
  assign _1447_ = _1446_ & (* src = "ls180.v:3232.43-3232.162" *) _1803_;
  assign _1448_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3234.44-3234.105" *) libresocsim_interface5_bank_bus_we;
  assign _1449_ = _1448_ & (* src = "ls180.v:3234.43-3234.159" *) _1804_;
  assign _1450_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3235.44-3235.108" *) _2096_;
  assign _1451_ = _1450_ & (* src = "ls180.v:3235.43-3235.162" *) _1805_;
  assign _1452_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3237.44-3237.105" *) libresocsim_interface5_bank_bus_we;
  assign _1453_ = _1452_ & (* src = "ls180.v:3237.43-3237.159" *) _1806_;
  assign _1454_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3238.44-3238.108" *) _2097_;
  assign _1455_ = _1454_ & (* src = "ls180.v:3238.43-3238.162" *) _1807_;
  assign _1456_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3240.44-3240.105" *) libresocsim_interface5_bank_bus_we;
  assign _1457_ = _1456_ & (* src = "ls180.v:3240.43-3240.159" *) _1808_;
  assign _1458_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3241.44-3241.108" *) _2098_;
  assign _1459_ = _1458_ & (* src = "ls180.v:3241.43-3241.162" *) _1809_;
  assign _1460_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3243.40-3243.101" *) libresocsim_interface5_bank_bus_we;
  assign _1461_ = _1460_ & (* src = "ls180.v:3243.39-3243.155" *) _1810_;
  assign _1462_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3244.40-3244.104" *) _2099_;
  assign _1463_ = _1462_ & (* src = "ls180.v:3244.39-3244.158" *) _1811_;
  assign _1464_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3246.50-3246.111" *) libresocsim_interface5_bank_bus_we;
  assign _1465_ = _1464_ & (* src = "ls180.v:3246.49-3246.165" *) _1812_;
  assign _1466_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3247.50-3247.114" *) _2100_;
  assign _1467_ = _1466_ & (* src = "ls180.v:3247.49-3247.168" *) _1813_;
  assign _1468_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3249.43-3249.104" *) libresocsim_interface5_bank_bus_we;
  assign _1469_ = _1468_ & (* src = "ls180.v:3249.42-3249.159" *) _1814_;
  assign _1470_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3250.43-3250.107" *) _2101_;
  assign _1471_ = _1470_ & (* src = "ls180.v:3250.42-3250.162" *) _1815_;
  assign _1472_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3252.43-3252.104" *) libresocsim_interface5_bank_bus_we;
  assign _1473_ = _1472_ & (* src = "ls180.v:3252.42-3252.159" *) _1816_;
  assign _1474_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3253.43-3253.107" *) _2102_;
  assign _1475_ = _1474_ & (* src = "ls180.v:3253.42-3253.162" *) _1817_;
  assign _1476_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3255.43-3255.104" *) libresocsim_interface5_bank_bus_we;
  assign _1477_ = _1476_ & (* src = "ls180.v:3255.42-3255.159" *) _1818_;
  assign _1478_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3256.43-3256.107" *) _2103_;
  assign _1479_ = _1478_ & (* src = "ls180.v:3256.42-3256.162" *) _1819_;
  assign _1480_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3258.43-3258.104" *) libresocsim_interface5_bank_bus_we;
  assign _1481_ = _1480_ & (* src = "ls180.v:3258.42-3258.159" *) _1820_;
  assign _1482_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3259.43-3259.107" *) _2104_;
  assign _1483_ = _1482_ & (* src = "ls180.v:3259.42-3259.162" *) _1821_;
  assign _1484_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3261.47-3261.108" *) libresocsim_interface5_bank_bus_we;
  assign _1485_ = _1484_ & (* src = "ls180.v:3261.46-3261.163" *) _1822_;
  assign _1486_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3262.47-3262.111" *) _2105_;
  assign _1487_ = _1486_ & (* src = "ls180.v:3262.46-3262.166" *) _1823_;
  assign _1488_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3264.48-3264.109" *) libresocsim_interface5_bank_bus_we;
  assign _1489_ = _1488_ & (* src = "ls180.v:3264.47-3264.164" *) _1824_;
  assign _1490_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3265.48-3265.112" *) _2106_;
  assign _1491_ = _1490_ & (* src = "ls180.v:3265.47-3265.167" *) _1825_;
  assign _1492_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3267.47-3267.108" *) libresocsim_interface5_bank_bus_we;
  assign _1493_ = _1492_ & (* src = "ls180.v:3267.46-3267.163" *) _1826_;
  assign _1494_ = libresocsim_csrbank5_sel & (* src = "ls180.v:3268.47-3268.111" *) _2107_;
  assign _1495_ = _1494_ & (* src = "ls180.v:3268.46-3268.166" *) _1827_;
  assign _1496_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3287.20-3287.81" *) libresocsim_interface6_bank_bus_we;
  assign _1497_ = _1496_ & (* src = "ls180.v:3287.19-3287.135" *) _1829_;
  assign _1498_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3288.20-3288.84" *) _2108_;
  assign _1499_ = _1498_ & (* src = "ls180.v:3288.19-3288.138" *) _1830_;
  assign _1500_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3290.43-3290.104" *) libresocsim_interface6_bank_bus_we;
  assign _1501_ = _1500_ & (* src = "ls180.v:3290.42-3290.158" *) _1831_;
  assign _1502_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3291.43-3291.107" *) _2109_;
  assign _1503_ = _1502_ & (* src = "ls180.v:3291.42-3291.161" *) _1832_;
  assign _1504_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3293.44-3293.105" *) libresocsim_interface6_bank_bus_we;
  assign _1505_ = _1504_ & (* src = "ls180.v:3293.43-3293.159" *) _1833_;
  assign _1506_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3294.44-3294.108" *) _2110_;
  assign _1507_ = _1506_ & (* src = "ls180.v:3294.43-3294.162" *) _1834_;
  assign _1508_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3296.35-3296.96" *) libresocsim_interface6_bank_bus_we;
  assign _1509_ = _1508_ & (* src = "ls180.v:3296.34-3296.150" *) _1835_;
  assign _1510_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3297.35-3297.99" *) _2111_;
  assign _1511_ = _1510_ & (* src = "ls180.v:3297.34-3297.153" *) _1836_;
  assign _1512_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3299.36-3299.97" *) libresocsim_interface6_bank_bus_we;
  assign _1513_ = _1512_ & (* src = "ls180.v:3299.35-3299.151" *) _1837_;
  assign _1514_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3300.36-3300.100" *) _2112_;
  assign _1515_ = _1514_ & (* src = "ls180.v:3300.35-3300.154" *) _1838_;
  assign _1516_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3302.47-3302.108" *) libresocsim_interface6_bank_bus_we;
  assign _1517_ = _1516_ & (* src = "ls180.v:3302.46-3302.162" *) _1839_;
  assign _1518_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3303.47-3303.111" *) _2113_;
  assign _1519_ = _1518_ & (* src = "ls180.v:3303.46-3303.165" *) _1840_;
  assign _1520_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3305.44-3305.105" *) libresocsim_interface6_bank_bus_we;
  assign _1521_ = _1520_ & (* src = "ls180.v:3305.43-3305.159" *) _1841_;
  assign _1522_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3306.44-3306.108" *) _2114_;
  assign _1523_ = _1522_ & (* src = "ls180.v:3306.43-3306.162" *) _1842_;
  assign _1524_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3308.43-3308.104" *) libresocsim_interface6_bank_bus_we;
  assign _1525_ = _1524_ & (* src = "ls180.v:3308.42-3308.158" *) _1843_;
  assign _1526_ = libresocsim_csrbank6_sel & (* src = "ls180.v:3309.43-3309.107" *) _2115_;
  assign _1527_ = _1526_ & (* src = "ls180.v:3309.42-3309.161" *) _1844_;
  assign _1528_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3321.49-3321.110" *) libresocsim_interface7_bank_bus_we;
  assign _1529_ = _1528_ & (* src = "ls180.v:3321.48-3321.164" *) _1846_;
  assign _1530_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3322.49-3322.113" *) _2116_;
  assign _1531_ = _1530_ & (* src = "ls180.v:3322.48-3322.167" *) _1847_;
  assign _1532_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3324.49-3324.110" *) libresocsim_interface7_bank_bus_we;
  assign _1533_ = _1532_ & (* src = "ls180.v:3324.48-3324.164" *) _1848_;
  assign _1534_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3325.49-3325.113" *) _2117_;
  assign _1535_ = _1534_ & (* src = "ls180.v:3325.48-3325.167" *) _1849_;
  assign _1536_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3327.49-3327.110" *) libresocsim_interface7_bank_bus_we;
  assign _1537_ = _1536_ & (* src = "ls180.v:3327.48-3327.164" *) _1850_;
  assign _1538_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3328.49-3328.113" *) _2118_;
  assign _1539_ = _1538_ & (* src = "ls180.v:3328.48-3328.167" *) _1851_;
  assign _1540_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3330.49-3330.110" *) libresocsim_interface7_bank_bus_we;
  assign _1541_ = _1540_ & (* src = "ls180.v:3330.48-3330.164" *) _1852_;
  assign _1542_ = libresocsim_csrbank7_sel & (* src = "ls180.v:3331.49-3331.113" *) _2119_;
  assign _1543_ = _1542_ & (* src = "ls180.v:3331.48-3331.167" *) _1853_;
  assign _1544_ = sdram_interface_bank1_lock & (* src = "ls180.v:3691.96-3691.165" *) _1855_;
  assign _1545_ = sdram_interface_bank2_lock & (* src = "ls180.v:3691.171-3691.240" *) _1856_;
  assign _1546_ = sdram_interface_bank3_lock & (* src = "ls180.v:3691.246-3691.315" *) _1857_;
  assign _1547_ = _1854_ & (* src = "ls180.v:3691.27-3691.318" *) _2120_;
  assign _1548_ = _1547_ & (* src = "ls180.v:3691.26-3691.336" *) port_cmd_valid;
  assign _1549_ = sdram_interface_bank0_lock & (* src = "ls180.v:3715.96-3715.165" *) _1859_;
  assign _1550_ = sdram_interface_bank2_lock & (* src = "ls180.v:3715.171-3715.240" *) _1860_;
  assign _1551_ = sdram_interface_bank3_lock & (* src = "ls180.v:3715.246-3715.315" *) _1861_;
  assign _1552_ = _1858_ & (* src = "ls180.v:3715.27-3715.318" *) _2121_;
  assign _1553_ = _1552_ & (* src = "ls180.v:3715.26-3715.336" *) port_cmd_valid;
  assign _1554_ = sdram_interface_bank0_lock & (* src = "ls180.v:3739.96-3739.165" *) _1863_;
  assign _1555_ = sdram_interface_bank1_lock & (* src = "ls180.v:3739.171-3739.240" *) _1864_;
  assign _1556_ = sdram_interface_bank3_lock & (* src = "ls180.v:3739.246-3739.315" *) _1865_;
  assign _1557_ = _1862_ & (* src = "ls180.v:3739.27-3739.318" *) _2122_;
  assign _1558_ = _1557_ & (* src = "ls180.v:3739.26-3739.336" *) port_cmd_valid;
  assign _1559_ = sdram_interface_bank0_lock & (* src = "ls180.v:3763.96-3763.165" *) _1867_;
  assign _1560_ = sdram_interface_bank1_lock & (* src = "ls180.v:3763.171-3763.240" *) _1868_;
  assign _1561_ = sdram_interface_bank2_lock & (* src = "ls180.v:3763.246-3763.315" *) _1869_;
  assign _1562_ = _1866_ & (* src = "ls180.v:3763.27-3763.318" *) _2123_;
  assign _1563_ = _1562_ & (* src = "ls180.v:3763.26-3763.336" *) port_cmd_valid;
  assign _1564_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3920.22-3920.77" *) sdram_choose_req_cmd_ready;
  assign _1565_ = _1564_ & (* src = "ls180.v:3920.21-3920.113" *) sdram_choose_req_cmd_payload_cas;
  assign _1566_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3923.22-3923.77" *) sdram_choose_req_cmd_ready;
  assign _1567_ = _1566_ & (* src = "ls180.v:3923.21-3923.113" *) sdram_choose_req_cmd_payload_cas;
  assign _1568_ = sdram_cmd_valid & (* src = "ls180.v:3926.22-3926.55" *) sdram_cmd_ready;
  assign _1569_ = _1568_ & (* src = "ls180.v:3926.21-3926.80" *) sdram_cmd_payload_cas;
  assign _1570_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3937.22-3937.77" *) sdram_choose_req_cmd_ready;
  assign _1571_ = _1570_ & (* src = "ls180.v:3937.21-3937.113" *) sdram_choose_req_cmd_payload_ras;
  assign _1572_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3940.22-3940.77" *) sdram_choose_req_cmd_ready;
  assign _1573_ = _1572_ & (* src = "ls180.v:3940.21-3940.113" *) sdram_choose_req_cmd_payload_ras;
  assign _1574_ = sdram_cmd_valid & (* src = "ls180.v:3943.22-3943.55" *) sdram_cmd_ready;
  assign _1575_ = _1574_ & (* src = "ls180.v:3943.21-3943.80" *) sdram_cmd_payload_ras;
  assign _1576_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3954.22-3954.77" *) sdram_choose_req_cmd_ready;
  assign _1577_ = _1576_ & (* src = "ls180.v:3954.21-3954.112" *) sdram_choose_req_cmd_payload_we;
  assign _1578_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3957.22-3957.77" *) sdram_choose_req_cmd_ready;
  assign _1579_ = _1578_ & (* src = "ls180.v:3957.21-3957.112" *) sdram_choose_req_cmd_payload_we;
  assign _1580_ = sdram_cmd_valid & (* src = "ls180.v:3960.22-3960.55" *) sdram_cmd_ready;
  assign _1581_ = _1580_ & (* src = "ls180.v:3960.21-3960.79" *) sdram_cmd_payload_we;
  assign _1582_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3971.22-3971.77" *) sdram_choose_req_cmd_ready;
  assign _1583_ = _1582_ & (* src = "ls180.v:3971.21-3971.117" *) sdram_choose_req_cmd_payload_is_read;
  assign _1584_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3974.22-3974.77" *) sdram_choose_req_cmd_ready;
  assign _1585_ = _1584_ & (* src = "ls180.v:3974.21-3974.117" *) sdram_choose_req_cmd_payload_is_read;
  assign _1586_ = sdram_cmd_valid & (* src = "ls180.v:3977.22-3977.55" *) sdram_cmd_ready;
  assign _1587_ = _1586_ & (* src = "ls180.v:3977.21-3977.84" *) sdram_cmd_payload_is_read;
  assign _1588_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3988.22-3988.77" *) sdram_choose_req_cmd_ready;
  assign _1589_ = _1588_ & (* src = "ls180.v:3988.21-3988.118" *) sdram_choose_req_cmd_payload_is_write;
  assign _1590_ = sdram_choose_req_cmd_valid & (* src = "ls180.v:3991.22-3991.77" *) sdram_choose_req_cmd_ready;
  assign _1591_ = _1590_ & (* src = "ls180.v:3991.21-3991.118" *) sdram_choose_req_cmd_payload_is_write;
  assign _1592_ = sdram_cmd_valid & (* src = "ls180.v:3994.22-3994.55" *) sdram_cmd_ready;
  assign _1593_ = _1592_ & (* src = "ls180.v:3994.21-3994.85" *) sdram_cmd_payload_is_write;
  assign _1594_ = dfi_p0_wrdata_en & (* src = "ls180.v:4192.57-4192.97" *) dfi_p0_wrdata_mask[0];
  assign _1595_ = dfi_p0_wrdata_en & (* src = "ls180.v:4193.57-4193.97" *) dfi_p0_wrdata_mask[1];
  assign _1596_ = libresocsim_ram_bus_cyc & (* src = "ls180.v:4314.8-4314.57" *) libresocsim_ram_bus_stb;
  assign _1597_ = _1596_ & (* src = "ls180.v:4314.7-4314.87" *) _2124_;
  assign _1598_ = _2125_ & (* src = "ls180.v:4333.7-4333.65" *) libresocsim_zero_old_trigger;
  assign _1599_ = ram_bus_ram_bus_cyc & (* src = "ls180.v:4337.8-4337.49" *) ram_bus_ram_bus_stb;
  assign _1600_ = _1599_ & (* src = "ls180.v:4337.7-4337.75" *) _2126_;
  assign _1601_ = sdram_timer_wait & (* src = "ls180.v:4345.7-4345.46" *) _2127_;
  assign _1602_ = sdram_sequencer_start1 & (* src = "ls180.v:4373.7-4373.65" *) _1872_;
  assign _1603_ = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (* src = "ls180.v:4415.8-4415.121" *) sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
  assign _1604_ = _1603_ & (* src = "ls180.v:4415.7-4415.175" *) _2128_;
  assign _1605_ = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (* src = "ls180.v:4421.8-4421.121" *) sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
  assign _1606_ = _1605_ & (* src = "ls180.v:4421.7-4421.175" *) _2129_;
  assign _1607_ = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (* src = "ls180.v:4461.8-4461.121" *) sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
  assign _1608_ = _1607_ & (* src = "ls180.v:4461.7-4461.175" *) _2133_;
  assign _1609_ = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (* src = "ls180.v:4467.8-4467.121" *) sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
  assign _1610_ = _1609_ & (* src = "ls180.v:4467.7-4467.175" *) _2134_;
  assign _1611_ = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (* src = "ls180.v:4507.8-4507.121" *) sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
  assign _1612_ = _1611_ & (* src = "ls180.v:4507.7-4507.175" *) _2138_;
  assign _1613_ = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (* src = "ls180.v:4513.8-4513.121" *) sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
  assign _1614_ = _1613_ & (* src = "ls180.v:4513.7-4513.175" *) _2139_;
  assign _1615_ = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (* src = "ls180.v:4553.8-4553.121" *) sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
  assign _1616_ = _1615_ & (* src = "ls180.v:4553.7-4553.175" *) _2143_;
  assign _1617_ = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (* src = "ls180.v:4559.8-4559.121" *) sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
  assign _1618_ = _1617_ & (* src = "ls180.v:4559.7-4559.175" *) _2144_;
  assign _1619_ = _1882_ & (* src = "ls180.v:4756.53-4756.129" *) sdram_interface_bank0_wdata_ready;
  assign _1620_ = _1883_ & (* src = "ls180.v:4756.135-4756.211" *) sdram_interface_bank1_wdata_ready;
  assign _1621_ = _1884_ & (* src = "ls180.v:4756.217-4756.293" *) sdram_interface_bank2_wdata_ready;
  assign _1622_ = _1885_ & (* src = "ls180.v:4756.299-4756.375" *) sdram_interface_bank3_wdata_ready;
  assign _1623_ = _1886_ & (* src = "ls180.v:4757.54-4757.130" *) sdram_interface_bank0_rdata_valid;
  assign _1624_ = _1887_ & (* src = "ls180.v:4757.136-4757.212" *) sdram_interface_bank1_rdata_valid;
  assign _1625_ = _1888_ & (* src = "ls180.v:4757.218-4757.294" *) sdram_interface_bank2_rdata_valid;
  assign _1626_ = _1889_ & (* src = "ls180.v:4757.300-4757.376" *) sdram_interface_bank3_rdata_valid;
  assign _1627_ = port_cmd_valid & (* src = "ls180.v:4776.8-4776.39" *) port_cmd_ready;
  assign _1628_ = port_wdata_valid & (* src = "ls180.v:4779.8-4779.43" *) port_wdata_ready;
  assign _1629_ = uart_phy_sink_valid & (* src = "ls180.v:4784.8-4784.49" *) _2157_;
  assign _1630_ = _1629_ & (* src = "ls180.v:4784.7-4784.75" *) _2158_;
  assign _1631_ = uart_phy_uart_clk_txen & (* src = "ls180.v:4790.8-4790.49" *) uart_phy_tx_busy;
  assign _1632_ = _2160_ & (* src = "ls180.v:4814.8-4814.38" *) uart_phy_rx_r;
  assign _1633_ = _2161_ & (* src = "ls180.v:4847.7-4847.37" *) tx_old_trigger;
  assign _1634_ = _2162_ & (* src = "ls180.v:4854.7-4854.37" *) rx_old_trigger;
  assign _1635_ = tx_fifo_syncfifo_we & (* src = "ls180.v:4864.8-4864.55" *) tx_fifo_syncfifo_writable;
  assign _1636_ = _1635_ & (* src = "ls180.v:4864.7-4864.77" *) _2163_;
  assign _1637_ = tx_fifo_syncfifo_we & (* src = "ls180.v:4870.8-4870.55" *) tx_fifo_syncfifo_writable;
  assign _1638_ = _1637_ & (* src = "ls180.v:4870.7-4870.77" *) _2164_;
  assign _1639_ = rx_fifo_syncfifo_we & (* src = "ls180.v:4886.8-4886.55" *) rx_fifo_syncfifo_writable;
  assign _1640_ = _1639_ & (* src = "ls180.v:4886.7-4886.77" *) _2166_;
  assign _1641_ = rx_fifo_syncfifo_we & (* src = "ls180.v:4892.8-4892.55" *) rx_fifo_syncfifo_writable;
  assign _1642_ = _1641_ & (* src = "ls180.v:4892.7-4892.77" *) _2167_;
  assign _1643_ = libresocsim_interface0_converted_interface_sel == (* src = "ls180.v:1546.37-1546.91" *) 1'h0;
  assign _1644_ = libresocsim_converter0_counter == (* src = "ls180.v:1553.11-1553.49" *) 1'h1;
  assign _1645_ = libresocsim_interface1_converted_interface_sel == (* src = "ls180.v:1606.37-1606.91" *) 1'h0;
  assign _1646_ = libresocsim_converter1_counter == (* src = "ls180.v:1613.11-1613.49" *) 1'h1;
  assign _1647_ = sdram_timer_count1 == (* src = "ls180.v:1809.29-1809.55" *) 1'h0;
  assign _1648_ = sdram_sequencer_count == (* src = "ls180.v:1813.58-1813.87" *) 1'h0;
  assign _1649_ = sdram_bankmachine0_row == (* src = "ls180.v:1857.38-1857.119" *) sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
  assign _1650_ = sdram_bankmachine0_row_close == (* src = "ls180.v:1874.42-1874.78" *) 1'h0;
  assign _1651_ = sdram_bankmachine1_row == (* src = "ls180.v:2014.38-2014.119" *) sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
  assign _1652_ = sdram_bankmachine1_row_close == (* src = "ls180.v:2031.42-2031.78" *) 1'h0;
  assign _1653_ = sdram_bankmachine2_row == (* src = "ls180.v:2171.38-2171.119" *) sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
  assign _1654_ = sdram_bankmachine2_row_close == (* src = "ls180.v:2188.42-2188.78" *) 1'h0;
  assign _1655_ = sdram_bankmachine3_row == (* src = "ls180.v:2328.38-2328.119" *) sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
  assign _1656_ = sdram_bankmachine3_row_close == (* src = "ls180.v:2345.42-2345.78" *) 1'h0;
  assign _1657_ = sdram_time0 == (* src = "ls180.v:2482.27-2482.46" *) 1'h0;
  assign _1658_ = sdram_time1 == (* src = "ls180.v:2483.27-2483.46" *) 1'h0;
  assign _1659_ = sdram_bankmachine0_cmd_payload_is_read == (* src = "ls180.v:2494.299-2494.368" *) sdram_choose_cmd_want_reads;
  assign _1660_ = sdram_bankmachine0_cmd_payload_is_write == (* src = "ls180.v:2494.373-2494.444" *) sdram_choose_cmd_want_writes;
  assign _1661_ = sdram_bankmachine1_cmd_payload_is_read == (* src = "ls180.v:2495.299-2495.368" *) sdram_choose_cmd_want_reads;
  assign _1662_ = sdram_bankmachine1_cmd_payload_is_write == (* src = "ls180.v:2495.373-2495.444" *) sdram_choose_cmd_want_writes;
  assign _1663_ = sdram_bankmachine2_cmd_payload_is_read == (* src = "ls180.v:2496.299-2496.368" *) sdram_choose_cmd_want_reads;
  assign _1664_ = sdram_bankmachine2_cmd_payload_is_write == (* src = "ls180.v:2496.373-2496.444" *) sdram_choose_cmd_want_writes;
  assign _1665_ = sdram_bankmachine3_cmd_payload_is_read == (* src = "ls180.v:2497.299-2497.368" *) sdram_choose_cmd_want_reads;
  assign _1666_ = sdram_bankmachine3_cmd_payload_is_write == (* src = "ls180.v:2497.373-2497.444" *) sdram_choose_cmd_want_writes;
  assign _1667_ = sdram_bankmachine0_cmd_payload_is_read == (* src = "ls180.v:2527.299-2527.368" *) sdram_choose_req_want_reads;
  assign _1668_ = sdram_bankmachine0_cmd_payload_is_write == (* src = "ls180.v:2527.373-2527.444" *) sdram_choose_req_want_writes;
  assign _1669_ = sdram_bankmachine1_cmd_payload_is_read == (* src = "ls180.v:2528.299-2528.368" *) sdram_choose_req_want_reads;
  assign _1670_ = sdram_bankmachine1_cmd_payload_is_write == (* src = "ls180.v:2528.373-2528.444" *) sdram_choose_req_want_writes;
  assign _1671_ = sdram_bankmachine2_cmd_payload_is_read == (* src = "ls180.v:2529.299-2529.368" *) sdram_choose_req_want_reads;
  assign _1672_ = sdram_bankmachine2_cmd_payload_is_write == (* src = "ls180.v:2529.373-2529.444" *) sdram_choose_req_want_writes;
  assign _1673_ = sdram_bankmachine3_cmd_payload_is_read == (* src = "ls180.v:2530.299-2530.368" *) sdram_choose_req_want_reads;
  assign _1674_ = sdram_bankmachine3_cmd_payload_is_write == (* src = "ls180.v:2530.373-2530.444" *) sdram_choose_req_want_writes;
  assign _1675_ = sdram_choose_cmd_grant == (* src = "ls180.v:2559.68-2559.98" *) 1'h0;
  assign _1676_ = sdram_choose_req_grant == (* src = "ls180.v:2562.68-2562.98" *) 1'h0;
  assign _1677_ = sdram_choose_cmd_grant == (* src = "ls180.v:2568.68-2568.98" *) 1'h1;
  assign _1678_ = sdram_choose_req_grant == (* src = "ls180.v:2571.68-2571.98" *) 1'h1;
  assign _1679_ = sdram_choose_cmd_grant == (* src = "ls180.v:2577.68-2577.98" *) 2'h2;
  assign _1680_ = sdram_choose_req_grant == (* src = "ls180.v:2580.68-2580.98" *) 2'h2;
  assign _1681_ = sdram_choose_cmd_grant == (* src = "ls180.v:2586.68-2586.98" *) 2'h3;
  assign _1682_ = sdram_choose_req_grant == (* src = "ls180.v:2589.68-2589.98" *) 2'h3;
  assign _1683_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2670.47-2670.82" *) 1'h0;
  assign _1684_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2670.145-2670.183" *) 1'h0;
  assign _1685_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2670.220-2670.258" *) 1'h0;
  assign _1686_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2670.295-2670.333" *) 1'h0;
  assign _1687_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2675.47-2675.82" *) 1'h1;
  assign _1688_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2675.145-2675.183" *) 1'h0;
  assign _1689_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2675.220-2675.258" *) 1'h0;
  assign _1690_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2675.295-2675.333" *) 1'h0;
  assign _1691_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2680.47-2680.82" *) 2'h2;
  assign _1692_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2680.145-2680.183" *) 1'h0;
  assign _1693_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2680.220-2680.258" *) 1'h0;
  assign _1694_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2680.295-2680.333" *) 1'h0;
  assign _1695_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2685.47-2685.82" *) 2'h3;
  assign _1696_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2685.145-2685.183" *) 1'h0;
  assign _1697_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2685.220-2685.258" *) 1'h0;
  assign _1698_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2685.295-2685.333" *) 1'h0;
  assign _1699_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2690.39-2690.77" *) 1'h0;
  assign _1700_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2690.83-2690.118" *) 1'h0;
  assign _1701_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2690.181-2690.219" *) 1'h0;
  assign _1702_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2690.256-2690.294" *) 1'h0;
  assign _1703_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2690.331-2690.369" *) 1'h0;
  assign _1704_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2690.413-2690.451" *) 1'h0;
  assign _1705_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2690.457-2690.492" *) 1'h1;
  assign _1706_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2690.555-2690.593" *) 1'h0;
  assign _1707_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2690.630-2690.668" *) 1'h0;
  assign _1708_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2690.705-2690.743" *) 1'h0;
  assign _1709_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2690.787-2690.825" *) 1'h0;
  assign _1710_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2690.831-2690.866" *) 2'h2;
  assign _1711_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2690.929-2690.967" *) 1'h0;
  assign _1712_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2690.1004-2690.1042" *) 1'h0;
  assign _1713_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2690.1079-2690.1117" *) 1'h0;
  assign _1714_ = subfragments_roundrobin3_grant == (* src = "ls180.v:2690.1161-2690.1199" *) 1'h0;
  assign _1715_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:2690.1205-2690.1240" *) 2'h3;
  assign _1716_ = subfragments_roundrobin0_grant == (* src = "ls180.v:2690.1303-2690.1341" *) 1'h0;
  assign _1717_ = subfragments_roundrobin1_grant == (* src = "ls180.v:2690.1378-2690.1416" *) 1'h0;
  assign _1718_ = subfragments_roundrobin2_grant == (* src = "ls180.v:2690.1453-2690.1491" *) 1'h0;
  assign _1719_ = litedram_wb_sel == (* src = "ls180.v:2749.24-2749.47" *) 1'h0;
  assign _1720_ = converter_counter == (* src = "ls180.v:2756.11-2756.36" *) 1'h1;
  assign _1721_ = libresocsim_grant == (* src = "ls180.v:3013.84-3013.109" *) 1'h0;
  assign _1722_ = libresocsim_grant == (* src = "ls180.v:3014.84-3014.109" *) 1'h1;
  assign _1723_ = libresocsim_grant == (* src = "ls180.v:3015.70-3015.95" *) 2'h2;
  assign _1724_ = libresocsim_grant == (* src = "ls180.v:3016.84-3016.109" *) 1'h0;
  assign _1725_ = libresocsim_grant == (* src = "ls180.v:3017.84-3017.109" *) 1'h1;
  assign _1726_ = libresocsim_grant == (* src = "ls180.v:3018.70-3018.95" *) 2'h2;
  assign _1727_ = libresocsim_shared_adr[29:7] == (* src = "ls180.v:3022.31-3022.67" *) 1'h0;
  assign _1728_ = libresocsim_shared_adr[29:5] == (* src = "ls180.v:3023.31-3023.68" *) 4'he;
  assign _1729_ = libresocsim_shared_adr[29:3] == (* src = "ls180.v:3024.31-3024.76" *) 27'h6000800;
  assign _1730_ = libresocsim_shared_adr[29:10] == (* src = "ls180.v:3025.31-3025.74" *) 20'hc0011;
  assign _1731_ = libresocsim_shared_adr[29:23] == (* src = "ls180.v:3026.31-3026.69" *) 7'h48;
  assign _1732_ = libresocsim_shared_adr[29:14] == (* src = "ls180.v:3027.31-3027.73" *) 16'hc000;
  assign _1733_ = libresocsim_count == (* src = "ls180.v:3091.28-3091.53" *) 1'h0;
  assign _1734_ = libresocsim_interface0_bank_bus_adr[13:9] == (* src = "ls180.v:3092.36-3092.85" *) 1'h0;
  assign _1735_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3094.109-3094.157" *) 1'h0;
  assign _1736_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3095.112-3095.160" *) 1'h0;
  assign _1737_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3097.111-3097.159" *) 1'h1;
  assign _1738_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3098.114-3098.162" *) 1'h1;
  assign _1739_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3100.111-3100.159" *) 2'h2;
  assign _1740_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3101.114-3101.162" *) 2'h2;
  assign _1741_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3103.111-3103.159" *) 2'h3;
  assign _1742_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3104.114-3104.162" *) 2'h3;
  assign _1743_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3106.111-3106.159" *) 3'h4;
  assign _1744_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3107.114-3107.162" *) 3'h4;
  assign _1745_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3109.114-3109.162" *) 3'h5;
  assign _1746_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3110.117-3110.165" *) 3'h5;
  assign _1747_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3112.114-3112.162" *) 3'h6;
  assign _1748_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3113.117-3113.165" *) 3'h6;
  assign _1749_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3115.114-3115.162" *) 3'h7;
  assign _1750_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3116.117-3116.165" *) 3'h7;
  assign _1751_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3118.114-3118.162" *) 4'h8;
  assign _1752_ = libresocsim_interface0_bank_bus_adr[3:0] == (* src = "ls180.v:3119.117-3119.165" *) 4'h8;
  assign _1753_ = libresocsim_interface1_bank_bus_adr[13:9] == (* src = "ls180.v:3130.36-3130.85" *) 3'h6;
  assign _1754_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3132.106-3132.154" *) 1'h0;
  assign _1755_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3133.109-3133.157" *) 1'h0;
  assign _1756_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3135.105-3135.153" *) 1'h1;
  assign _1757_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3136.108-3136.156" *) 1'h1;
  assign _1758_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3138.107-3138.155" *) 2'h2;
  assign _1759_ = libresocsim_interface1_bank_bus_adr[1:0] == (* src = "ls180.v:3139.110-3139.158" *) 2'h2;
  assign _1760_ = libresocsim_interface2_bank_bus_adr[13:9] == (* src = "ls180.v:3144.36-3144.85" *) 3'h7;
  assign _1761_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3146.106-3146.154" *) 1'h0;
  assign _1762_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3147.109-3147.157" *) 1'h0;
  assign _1763_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3149.105-3149.153" *) 1'h1;
  assign _1764_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3150.108-3150.156" *) 1'h1;
  assign _1765_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3152.107-3152.155" *) 2'h2;
  assign _1766_ = libresocsim_interface2_bank_bus_adr[1:0] == (* src = "ls180.v:3153.110-3153.158" *) 2'h2;
  assign _1767_ = libresocsim_interface3_bank_bus_adr[13:9] == (* src = "ls180.v:3158.36-3158.85" *) 4'h8;
  assign _1768_ = libresocsim_interface3_bank_bus_adr[0] == (* src = "ls180.v:3160.105-3160.151" *) 1'h0;
  assign _1769_ = libresocsim_interface3_bank_bus_adr[0] == (* src = "ls180.v:3161.108-3161.154" *) 1'h0;
  assign _1770_ = libresocsim_interface3_bank_bus_adr[0] == (* src = "ls180.v:3163.104-3163.150" *) 1'h1;
  assign _1771_ = libresocsim_interface3_bank_bus_adr[0] == (* src = "ls180.v:3164.107-3164.153" *) 1'h1;
  assign _1772_ = libresocsim_interface4_bank_bus_adr[13:9] == (* src = "ls180.v:3172.36-3172.85" *) 2'h3;
  assign _1773_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3174.116-3174.164" *) 1'h0;
  assign _1774_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3175.119-3175.167" *) 1'h0;
  assign _1775_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3177.120-3177.168" *) 1'h1;
  assign _1776_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3178.123-3178.171" *) 1'h1;
  assign _1777_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3180.101-3180.149" *) 2'h2;
  assign _1778_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3181.104-3181.152" *) 2'h2;
  assign _1779_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3183.120-3183.168" *) 2'h3;
  assign _1780_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3184.123-3184.171" *) 2'h3;
  assign _1781_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3186.120-3186.168" *) 3'h4;
  assign _1782_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3187.123-3187.171" *) 3'h4;
  assign _1783_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3189.121-3189.169" *) 3'h5;
  assign _1784_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3190.124-3190.172" *) 3'h5;
  assign _1785_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3192.119-3192.167" *) 3'h6;
  assign _1786_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3193.122-3193.170" *) 3'h6;
  assign _1787_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3195.119-3195.167" *) 3'h7;
  assign _1788_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3196.122-3196.170" *) 3'h7;
  assign _1789_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3198.119-3198.167" *) 4'h8;
  assign _1790_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3199.122-3199.170" *) 4'h8;
  assign _1791_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3201.119-3201.167" *) 4'h9;
  assign _1792_ = libresocsim_interface4_bank_bus_adr[3:0] == (* src = "ls180.v:3202.122-3202.170" *) 4'h9;
  assign _1793_ = libresocsim_interface5_bank_bus_adr[13:9] == (* src = "ls180.v:3217.36-3217.85" *) 2'h2;
  assign _1794_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3219.108-3219.156" *) 1'h0;
  assign _1795_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3220.111-3220.159" *) 1'h0;
  assign _1796_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3222.108-3222.156" *) 1'h1;
  assign _1797_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3223.111-3223.159" *) 1'h1;
  assign _1798_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3225.108-3225.156" *) 2'h2;
  assign _1799_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3226.111-3226.159" *) 2'h2;
  assign _1800_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3228.108-3228.156" *) 2'h3;
  assign _1801_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3229.111-3229.159" *) 2'h3;
  assign _1802_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3231.110-3231.158" *) 3'h4;
  assign _1803_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3232.113-3232.161" *) 3'h4;
  assign _1804_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3234.110-3234.158" *) 3'h5;
  assign _1805_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3235.113-3235.161" *) 3'h5;
  assign _1806_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3237.110-3237.158" *) 3'h6;
  assign _1807_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3238.113-3238.161" *) 3'h6;
  assign _1808_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3240.110-3240.158" *) 3'h7;
  assign _1809_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3241.113-3241.161" *) 3'h7;
  assign _1810_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3243.106-3243.154" *) 4'h8;
  assign _1811_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3244.109-3244.157" *) 4'h8;
  assign _1812_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3246.116-3246.164" *) 4'h9;
  assign _1813_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3247.119-3247.167" *) 4'h9;
  assign _1814_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3249.109-3249.158" *) 4'ha;
  assign _1815_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3250.112-3250.161" *) 4'ha;
  assign _1816_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3252.109-3252.158" *) 4'hb;
  assign _1817_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3253.112-3253.161" *) 4'hb;
  assign _1818_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3255.109-3255.158" *) 4'hc;
  assign _1819_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3256.112-3256.161" *) 4'hc;
  assign _1820_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3258.109-3258.158" *) 4'hd;
  assign _1821_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3259.112-3259.161" *) 4'hd;
  assign _1822_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3261.113-3261.162" *) 4'he;
  assign _1823_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3262.116-3262.165" *) 4'he;
  assign _1824_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3264.114-3264.163" *) 4'hf;
  assign _1825_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3265.117-3265.166" *) 4'hf;
  assign _1826_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3267.113-3267.162" *) 5'h10;
  assign _1827_ = libresocsim_interface5_bank_bus_adr[4:0] == (* src = "ls180.v:3268.116-3268.165" *) 5'h10;
  assign _1828_ = libresocsim_interface6_bank_bus_adr[13:9] == (* src = "ls180.v:3285.36-3285.85" *) 3'h5;
  assign _1829_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3287.86-3287.134" *) 1'h0;
  assign _1830_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3288.89-3288.137" *) 1'h0;
  assign _1831_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3290.109-3290.157" *) 1'h1;
  assign _1832_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3291.112-3291.160" *) 1'h1;
  assign _1833_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3293.110-3293.158" *) 2'h2;
  assign _1834_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3294.113-3294.161" *) 2'h2;
  assign _1835_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3296.101-3296.149" *) 2'h3;
  assign _1836_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3297.104-3297.152" *) 2'h3;
  assign _1837_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3299.102-3299.150" *) 3'h4;
  assign _1838_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3300.105-3300.153" *) 3'h4;
  assign _1839_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3302.113-3302.161" *) 3'h5;
  assign _1840_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3303.116-3303.164" *) 3'h5;
  assign _1841_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3305.110-3305.158" *) 3'h6;
  assign _1842_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3306.113-3306.161" *) 3'h6;
  assign _1843_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3308.109-3308.157" *) 3'h7;
  assign _1844_ = libresocsim_interface6_bank_bus_adr[2:0] == (* src = "ls180.v:3309.112-3309.160" *) 3'h7;
  assign _1845_ = libresocsim_interface7_bank_bus_adr[13:9] == (* src = "ls180.v:3319.36-3319.85" *) 3'h4;
  assign _1846_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3321.115-3321.163" *) 1'h0;
  assign _1847_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3322.118-3322.166" *) 1'h0;
  assign _1848_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3324.115-3324.163" *) 1'h1;
  assign _1849_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3325.118-3325.166" *) 1'h1;
  assign _1850_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3327.115-3327.163" *) 2'h2;
  assign _1851_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3328.118-3328.166" *) 2'h2;
  assign _1852_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3330.115-3330.163" *) 2'h3;
  assign _1853_ = libresocsim_interface7_bank_bus_adr[1:0] == (* src = "ls180.v:3331.118-3331.166" *) 2'h3;
  assign _1854_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:3691.28-3691.63" *) 1'h0;
  assign _1855_ = subfragments_roundrobin1_grant == (* src = "ls180.v:3691.126-3691.164" *) 1'h0;
  assign _1856_ = subfragments_roundrobin2_grant == (* src = "ls180.v:3691.201-3691.239" *) 1'h0;
  assign _1857_ = subfragments_roundrobin3_grant == (* src = "ls180.v:3691.276-3691.314" *) 1'h0;
  assign _1858_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:3715.28-3715.63" *) 1'h1;
  assign _1859_ = subfragments_roundrobin0_grant == (* src = "ls180.v:3715.126-3715.164" *) 1'h0;
  assign _1860_ = subfragments_roundrobin2_grant == (* src = "ls180.v:3715.201-3715.239" *) 1'h0;
  assign _1861_ = subfragments_roundrobin3_grant == (* src = "ls180.v:3715.276-3715.314" *) 1'h0;
  assign _1862_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:3739.28-3739.63" *) 2'h2;
  assign _1863_ = subfragments_roundrobin0_grant == (* src = "ls180.v:3739.126-3739.164" *) 1'h0;
  assign _1864_ = subfragments_roundrobin1_grant == (* src = "ls180.v:3739.201-3739.239" *) 1'h0;
  assign _1865_ = subfragments_roundrobin3_grant == (* src = "ls180.v:3739.276-3739.314" *) 1'h0;
  assign _1866_ = port_cmd_payload_addr[10:9] == (* src = "ls180.v:3763.28-3763.63" *) 2'h3;
  assign _1867_ = subfragments_roundrobin0_grant == (* src = "ls180.v:3763.126-3763.164" *) 1'h0;
  assign _1868_ = subfragments_roundrobin1_grant == (* src = "ls180.v:3763.201-3763.239" *) 1'h0;
  assign _1869_ = subfragments_roundrobin2_grant == (* src = "ls180.v:3763.276-3763.314" *) 1'h0;
  assign _1870_ = libresocsim_value == (* src = "ls180.v:4318.8-4318.33" *) 1'h0;
  assign _1871_ = sdram_postponer_count == (* src = "ls180.v:4353.8-4353.37" *) 1'h0;
  assign _1872_ = sdram_sequencer_counter == (* src = "ls180.v:4373.33-4373.64" *) 1'h0;
  assign _1873_ = sdram_sequencer_counter == (* src = "ls180.v:4380.7-4380.38" *) 2'h2;
  assign _1874_ = sdram_sequencer_counter == (* src = "ls180.v:4387.7-4387.38" *) 4'h8;
  assign _1875_ = sdram_sequencer_counter == (* src = "ls180.v:4395.7-4395.38" *) 4'h8;
  assign _1876_ = sdram_bankmachine0_twtpcon_count == (* src = "ls180.v:4447.9-4447.49" *) 1'h1;
  assign _1877_ = sdram_bankmachine1_twtpcon_count == (* src = "ls180.v:4493.9-4493.49" *) 1'h1;
  assign _1878_ = sdram_bankmachine2_twtpcon_count == (* src = "ls180.v:4539.9-4539.49" *) 1'h1;
  assign _1879_ = sdram_bankmachine3_twtpcon_count == (* src = "ls180.v:4585.9-4585.49" *) 1'h1;
  assign _1880_ = sdram_tccdcon_count == (* src = "ls180.v:4735.9-4735.36" *) 1'h1;
  assign _1881_ = sdram_twtrcon_count == (* src = "ls180.v:4750.9-4750.36" *) 1'h1;
  assign _1882_ = subfragments_roundrobin0_grant == (* src = "ls180.v:4756.54-4756.92" *) 1'h0;
  assign _1883_ = subfragments_roundrobin1_grant == (* src = "ls180.v:4756.136-4756.174" *) 1'h0;
  assign _1884_ = subfragments_roundrobin2_grant == (* src = "ls180.v:4756.218-4756.256" *) 1'h0;
  assign _1885_ = subfragments_roundrobin3_grant == (* src = "ls180.v:4756.300-4756.338" *) 1'h0;
  assign _1886_ = subfragments_roundrobin0_grant == (* src = "ls180.v:4757.55-4757.93" *) 1'h0;
  assign _1887_ = subfragments_roundrobin1_grant == (* src = "ls180.v:4757.137-4757.175" *) 1'h0;
  assign _1888_ = subfragments_roundrobin2_grant == (* src = "ls180.v:4757.219-4757.257" *) 1'h0;
  assign _1889_ = subfragments_roundrobin3_grant == (* src = "ls180.v:4757.301-4757.339" *) 1'h0;
  assign _1890_ = uart_phy_tx_bitcount == (* src = "ls180.v:4792.9-4792.37" *) 4'h8;
  assign _1891_ = uart_phy_tx_bitcount == (* src = "ls180.v:4795.10-4795.38" *) 4'h9;
  assign _1892_ = uart_phy_rx_bitcount == (* src = "ls180.v:4821.9-4821.37" *) 1'h0;
  assign _1893_ = uart_phy_rx_bitcount == (* src = "ls180.v:4826.10-4826.38" *) 4'h9;
  assign _1950_ = libresocsim_value != (* src = "ls180.v:1641.36-1641.61" *) 1'h0;
  assign _1951_ = sdram_sequencer_count != (* src = "ls180.v:1812.60-1812.89" *) 1'h0;
  assign _1952_ = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:9] != (* src = "ls180.v:1873.8-1873.132" *) sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
  assign _1953_ = sdram_bankmachine0_cmd_buffer_lookahead_level != (* src = "ls180.v:1905.70-1905.123" *) 4'h8;
  assign _1954_ = sdram_bankmachine0_cmd_buffer_lookahead_level != (* src = "ls180.v:1906.70-1906.123" *) 1'h0;
  assign _1955_ = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:9] != (* src = "ls180.v:2030.8-2030.132" *) sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
  assign _1956_ = sdram_bankmachine1_cmd_buffer_lookahead_level != (* src = "ls180.v:2062.70-2062.123" *) 4'h8;
  assign _1957_ = sdram_bankmachine1_cmd_buffer_lookahead_level != (* src = "ls180.v:2063.70-2063.123" *) 1'h0;
  assign _1958_ = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:9] != (* src = "ls180.v:2187.8-2187.132" *) sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
  assign _1959_ = sdram_bankmachine2_cmd_buffer_lookahead_level != (* src = "ls180.v:2219.70-2219.123" *) 4'h8;
  assign _1960_ = sdram_bankmachine2_cmd_buffer_lookahead_level != (* src = "ls180.v:2220.70-2220.123" *) 1'h0;
  assign _1961_ = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:9] != (* src = "ls180.v:2344.8-2344.132" *) sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
  assign _1962_ = sdram_bankmachine3_cmd_buffer_lookahead_level != (* src = "ls180.v:2376.70-2376.123" *) 4'h8;
  assign _1963_ = sdram_bankmachine3_cmd_buffer_lookahead_level != (* src = "ls180.v:2377.70-2377.123" *) 1'h0;
  assign _1964_ = tx_fifo_level0 != (* src = "ls180.v:2869.37-2869.60" *) 5'h10;
  assign _1965_ = tx_fifo_level0 != (* src = "ls180.v:2870.37-2870.59" *) 1'h0;
  assign _1966_ = rx_fifo_level0 != (* src = "ls180.v:2899.37-2899.60" *) 5'h10;
  assign _1967_ = rx_fifo_level0 != (* src = "ls180.v:2900.37-2900.59" *) 1'h0;
  assign _1968_ = libresocsim_libresocsim_wishbone_sel != (* src = "ls180.v:2995.99-2995.143" *) 1'h0;
  assign _1969_ = libresocsim_bus_errors != (* src = "ls180.v:4308.7-4308.47" *) 32'd4294967295;
  assign _1970_ = sdram_sequencer_count != (* src = "ls180.v:4362.9-4362.38" *) 1'h0;
  assign _1971_ = sdram_sequencer_counter != (* src = "ls180.v:4398.8-4398.39" *) 1'h0;
  assign _1972_ = ~ (* src = "ls180.v:1509.40-1509.70" *) libresocsim_libresoc_ibus_cyc;
  assign _1973_ = ~ (* src = "ls180.v:1548.56-1548.84" *) libresocsim_converter0_skip;
  assign _1974_ = ~ (* src = "ls180.v:1549.56-1549.84" *) libresocsim_converter0_skip;
  assign _1975_ = ~ (* src = "ls180.v:1569.40-1569.70" *) libresocsim_libresoc_dbus_cyc;
  assign _1976_ = ~ (* src = "ls180.v:1608.56-1608.84" *) libresocsim_converter1_skip;
  assign _1977_ = ~ (* src = "ls180.v:1609.56-1609.84" *) libresocsim_converter1_skip;
  assign _1978_ = ~ (* src = "ls180.v:1761.29-1761.54" *) sdram_command_storage[0];
  assign _1979_ = ~ (* src = "ls180.v:1762.26-1762.51" *) sdram_command_storage[1];
  assign _1980_ = ~ (* src = "ls180.v:1763.27-1763.52" *) sdram_command_storage[2];
  assign _1981_ = ~ (* src = "ls180.v:1764.27-1764.52" *) sdram_command_storage[3];
  assign _1982_ = ~ (* src = "ls180.v:1806.28-1806.46" *) sdram_timer_done0;
  assign _1983_ = ~ (* src = "ls180.v:1907.53-1907.96" *) sdram_bankmachine0_cmd_buffer_source_valid;
  assign _1984_ = ~ (* src = "ls180.v:1961.9-1961.40" *) sdram_bankmachine0_refresh_req;
  assign _1985_ = ~ (* src = "ls180.v:2064.53-2064.96" *) sdram_bankmachine1_cmd_buffer_source_valid;
  assign _1986_ = ~ (* src = "ls180.v:2118.9-2118.40" *) sdram_bankmachine1_refresh_req;
  assign _1987_ = ~ (* src = "ls180.v:2221.53-2221.96" *) sdram_bankmachine2_cmd_buffer_source_valid;
  assign _1988_ = ~ (* src = "ls180.v:2275.9-2275.40" *) sdram_bankmachine2_refresh_req;
  assign _1989_ = ~ (* src = "ls180.v:2378.53-2378.96" *) sdram_bankmachine3_cmd_buffer_source_valid;
  assign _1990_ = ~ (* src = "ls180.v:2432.9-2432.40" *) sdram_bankmachine3_refresh_req;
  assign _1991_ = ~ (* src = "ls180.v:2474.129-2474.162" *) sdram_choose_req_cmd_payload_cas;
  assign _1992_ = ~ (* src = "ls180.v:2474.168-2474.200" *) sdram_choose_req_cmd_payload_we;
  assign _1993_ = ~ (* src = "ls180.v:2475.129-2475.162" *) sdram_choose_req_cmd_payload_cas;
  assign _1994_ = ~ (* src = "ls180.v:2475.168-2475.200" *) sdram_choose_req_cmd_payload_we;
  assign _1995_ = ~ (* src = "ls180.v:2491.38-2491.63" *) sdram_interface_wdata_we;
  assign _1996_ = ~ (* src = "ls180.v:2494.180-2494.215" *) sdram_bankmachine0_cmd_payload_cas;
  assign _1997_ = ~ (* src = "ls180.v:2494.221-2494.255" *) sdram_bankmachine0_cmd_payload_we;
  assign _1998_ = ~ (* src = "ls180.v:2494.139-2494.257" *) _1158_;
  assign _1999_ = ~ (* src = "ls180.v:2495.180-2495.215" *) sdram_bankmachine1_cmd_payload_cas;
  assign _2000_ = ~ (* src = "ls180.v:2495.221-2495.255" *) sdram_bankmachine1_cmd_payload_we;
  assign _2001_ = ~ (* src = "ls180.v:2495.139-2495.257" *) _1164_;
  assign _2002_ = ~ (* src = "ls180.v:2496.180-2496.215" *) sdram_bankmachine2_cmd_payload_cas;
  assign _2003_ = ~ (* src = "ls180.v:2496.221-2496.255" *) sdram_bankmachine2_cmd_payload_we;
  assign _2004_ = ~ (* src = "ls180.v:2496.139-2496.257" *) _1170_;
  assign _2005_ = ~ (* src = "ls180.v:2497.180-2497.215" *) sdram_bankmachine3_cmd_payload_cas;
  assign _2006_ = ~ (* src = "ls180.v:2497.221-2497.255" *) sdram_bankmachine3_cmd_payload_we;
  assign _2007_ = ~ (* src = "ls180.v:2497.139-2497.257" *) _1176_;
  assign _2008_ = ~ (* src = "ls180.v:2524.61-2524.88" *) sdram_choose_cmd_cmd_valid;
  assign _2009_ = ~ (* src = "ls180.v:2527.180-2527.215" *) sdram_bankmachine0_cmd_payload_cas;
  assign _2010_ = ~ (* src = "ls180.v:2527.221-2527.255" *) sdram_bankmachine0_cmd_payload_we;
  assign _2011_ = ~ (* src = "ls180.v:2527.139-2527.257" *) _1182_;
  assign _2012_ = ~ (* src = "ls180.v:2528.180-2528.215" *) sdram_bankmachine1_cmd_payload_cas;
  assign _2013_ = ~ (* src = "ls180.v:2528.221-2528.255" *) sdram_bankmachine1_cmd_payload_we;
  assign _2014_ = ~ (* src = "ls180.v:2528.139-2528.257" *) _1188_;
  assign _2015_ = ~ (* src = "ls180.v:2529.180-2529.215" *) sdram_bankmachine2_cmd_payload_cas;
  assign _2016_ = ~ (* src = "ls180.v:2529.221-2529.255" *) sdram_bankmachine2_cmd_payload_we;
  assign _2017_ = ~ (* src = "ls180.v:2529.139-2529.257" *) _1194_;
  assign _2018_ = ~ (* src = "ls180.v:2530.180-2530.215" *) sdram_bankmachine3_cmd_payload_cas;
  assign _2019_ = ~ (* src = "ls180.v:2530.221-2530.255" *) sdram_bankmachine3_cmd_payload_we;
  assign _2020_ = ~ (* src = "ls180.v:2530.139-2530.257" *) _1200_;
  assign _2021_ = ~ (* src = "ls180.v:2593.61-2593.88" *) sdram_choose_req_cmd_valid;
  assign _2022_ = ~ (* src = "ls180.v:2614.97-2614.130" *) sdram_choose_req_cmd_payload_cas;
  assign _2023_ = ~ (* src = "ls180.v:2614.136-2614.168" *) sdram_choose_req_cmd_payload_we;
  assign _2024_ = ~ (* src = "ls180.v:2614.58-2614.170" *) _1221_;
  assign _2025_ = ~ (* src = "ls180.v:2622.11-2622.33" *) sdram_write_available;
  assign _2026_ = ~ (* src = "ls180.v:2652.97-2652.130" *) sdram_choose_req_cmd_payload_cas;
  assign _2027_ = ~ (* src = "ls180.v:2652.136-2652.168" *) sdram_choose_req_cmd_payload_we;
  assign _2028_ = ~ (* src = "ls180.v:2652.58-2652.170" *) _1224_;
  assign _2029_ = ~ (* src = "ls180.v:2660.11-2660.32" *) sdram_read_available;
  assign _2030_ = ~ (* src = "ls180.v:2670.87-2670.336" *) _2227_;
  assign _2031_ = ~ (* src = "ls180.v:2671.40-2671.68" *) sdram_interface_bank0_valid;
  assign _2032_ = ~ (* src = "ls180.v:2671.73-2671.100" *) sdram_interface_bank0_lock;
  assign _2033_ = ~ (* src = "ls180.v:2675.87-2675.336" *) _2230_;
  assign _2034_ = ~ (* src = "ls180.v:2676.40-2676.68" *) sdram_interface_bank1_valid;
  assign _2035_ = ~ (* src = "ls180.v:2676.73-2676.100" *) sdram_interface_bank1_lock;
  assign _2036_ = ~ (* src = "ls180.v:2680.87-2680.336" *) _2233_;
  assign _2037_ = ~ (* src = "ls180.v:2681.40-2681.68" *) sdram_interface_bank2_valid;
  assign _2038_ = ~ (* src = "ls180.v:2681.73-2681.100" *) sdram_interface_bank2_lock;
  assign _2039_ = ~ (* src = "ls180.v:2685.87-2685.336" *) _2236_;
  assign _2040_ = ~ (* src = "ls180.v:2686.40-2686.68" *) sdram_interface_bank3_valid;
  assign _2041_ = ~ (* src = "ls180.v:2686.73-2686.100" *) sdram_interface_bank3_lock;
  assign _2042_ = ~ (* src = "ls180.v:2690.123-2690.372" *) _2239_;
  assign _2043_ = ~ (* src = "ls180.v:2690.497-2690.746" *) _2243_;
  assign _2044_ = ~ (* src = "ls180.v:2690.871-2690.1120" *) _2247_;
  assign _2045_ = ~ (* src = "ls180.v:2690.1245-2690.1494" *) _2251_;
  assign _2046_ = ~ (* src = "ls180.v:2712.27-2712.40" *) wb_sdram_cyc;
  assign _2047_ = ~ (* src = "ls180.v:2751.25-2751.40" *) converter_skip;
  assign _2048_ = ~ (* src = "ls180.v:2752.25-2752.40" *) converter_skip;
  assign _2049_ = ~ (* src = "ls180.v:2777.22-2777.38" *) litedram_wb_cyc;
  assign _2050_ = ~ (* src = "ls180.v:2778.25-2778.40" *) litedram_wb_we;
  assign _2051_ = ~ (* src = "ls180.v:2779.65-2779.78" *) cmd_consumed;
  assign _2052_ = ~ (* src = "ls180.v:2780.87-2780.102" *) wdata_consumed;
  assign _2053_ = ~ (* src = "ls180.v:2781.63-2781.83" *) port_cmd_payload_we;
  assign _2054_ = ~ (* src = "ls180.v:2782.71-2782.86" *) litedram_wb_we;
  assign _2055_ = ~ (* src = "ls180.v:2798.25-2798.44" *) tx_fifo_sink_ready;
  assign _2056_ = ~ (* src = "ls180.v:2799.26-2799.47" *) tx_fifo_source_valid;
  assign _2057_ = ~ (* src = "ls180.v:2805.22-2805.41" *) tx_fifo_sink_ready;
  assign _2058_ = ~ (* src = "ls180.v:2811.26-2811.47" *) rx_fifo_source_valid;
  assign _2059_ = ~ (* src = "ls180.v:2812.25-2812.44" *) rx_fifo_sink_ready;
  assign _2060_ = ~ (* src = "ls180.v:2815.22-2815.43" *) rx_fifo_source_valid;
  assign _2061_ = ~ (* src = "ls180.v:2853.61-2853.78" *) tx_fifo_readable;
  assign _2062_ = ~ (* src = "ls180.v:2883.61-2883.78" *) rx_fifo_readable;
  assign _2063_ = ~ (* src = "ls180.v:3078.81-3078.104" *) libresocsim_shared_ack;
  assign _2064_ = ~ (* src = "ls180.v:3095.71-3095.106" *) libresocsim_interface0_bank_bus_we;
  assign _2065_ = ~ (* src = "ls180.v:3098.73-3098.108" *) libresocsim_interface0_bank_bus_we;
  assign _2066_ = ~ (* src = "ls180.v:3101.73-3101.108" *) libresocsim_interface0_bank_bus_we;
  assign _2067_ = ~ (* src = "ls180.v:3104.73-3104.108" *) libresocsim_interface0_bank_bus_we;
  assign _2068_ = ~ (* src = "ls180.v:3107.73-3107.108" *) libresocsim_interface0_bank_bus_we;
  assign _2069_ = ~ (* src = "ls180.v:3110.76-3110.111" *) libresocsim_interface0_bank_bus_we;
  assign _2070_ = ~ (* src = "ls180.v:3113.76-3113.111" *) libresocsim_interface0_bank_bus_we;
  assign _2071_ = ~ (* src = "ls180.v:3116.76-3116.111" *) libresocsim_interface0_bank_bus_we;
  assign _2072_ = ~ (* src = "ls180.v:3119.76-3119.111" *) libresocsim_interface0_bank_bus_we;
  assign _2073_ = ~ (* src = "ls180.v:3133.68-3133.103" *) libresocsim_interface1_bank_bus_we;
  assign _2074_ = ~ (* src = "ls180.v:3136.67-3136.102" *) libresocsim_interface1_bank_bus_we;
  assign _2075_ = ~ (* src = "ls180.v:3139.69-3139.104" *) libresocsim_interface1_bank_bus_we;
  assign _2076_ = ~ (* src = "ls180.v:3147.68-3147.103" *) libresocsim_interface2_bank_bus_we;
  assign _2077_ = ~ (* src = "ls180.v:3150.67-3150.102" *) libresocsim_interface2_bank_bus_we;
  assign _2078_ = ~ (* src = "ls180.v:3153.69-3153.104" *) libresocsim_interface2_bank_bus_we;
  assign _2079_ = ~ (* src = "ls180.v:3161.67-3161.102" *) libresocsim_interface3_bank_bus_we;
  assign _2080_ = ~ (* src = "ls180.v:3164.66-3164.101" *) libresocsim_interface3_bank_bus_we;
  assign _2081_ = ~ (* src = "ls180.v:3175.78-3175.113" *) libresocsim_interface4_bank_bus_we;
  assign _2082_ = ~ (* src = "ls180.v:3178.82-3178.117" *) libresocsim_interface4_bank_bus_we;
  assign _2083_ = ~ (* src = "ls180.v:3181.63-3181.98" *) libresocsim_interface4_bank_bus_we;
  assign _2084_ = ~ (* src = "ls180.v:3184.82-3184.117" *) libresocsim_interface4_bank_bus_we;
  assign _2085_ = ~ (* src = "ls180.v:3187.82-3187.117" *) libresocsim_interface4_bank_bus_we;
  assign _2086_ = ~ (* src = "ls180.v:3190.83-3190.118" *) libresocsim_interface4_bank_bus_we;
  assign _2087_ = ~ (* src = "ls180.v:3193.81-3193.116" *) libresocsim_interface4_bank_bus_we;
  assign _2088_ = ~ (* src = "ls180.v:3196.81-3196.116" *) libresocsim_interface4_bank_bus_we;
  assign _2089_ = ~ (* src = "ls180.v:3199.81-3199.116" *) libresocsim_interface4_bank_bus_we;
  assign _2090_ = ~ (* src = "ls180.v:3202.81-3202.116" *) libresocsim_interface4_bank_bus_we;
  assign _2091_ = ~ (* src = "ls180.v:3220.70-3220.105" *) libresocsim_interface5_bank_bus_we;
  assign _2092_ = ~ (* src = "ls180.v:3223.70-3223.105" *) libresocsim_interface5_bank_bus_we;
  assign _2093_ = ~ (* src = "ls180.v:3226.70-3226.105" *) libresocsim_interface5_bank_bus_we;
  assign _2094_ = ~ (* src = "ls180.v:3229.70-3229.105" *) libresocsim_interface5_bank_bus_we;
  assign _2095_ = ~ (* src = "ls180.v:3232.72-3232.107" *) libresocsim_interface5_bank_bus_we;
  assign _2096_ = ~ (* src = "ls180.v:3235.72-3235.107" *) libresocsim_interface5_bank_bus_we;
  assign _2097_ = ~ (* src = "ls180.v:3238.72-3238.107" *) libresocsim_interface5_bank_bus_we;
  assign _2098_ = ~ (* src = "ls180.v:3241.72-3241.107" *) libresocsim_interface5_bank_bus_we;
  assign _2099_ = ~ (* src = "ls180.v:3244.68-3244.103" *) libresocsim_interface5_bank_bus_we;
  assign _2100_ = ~ (* src = "ls180.v:3247.78-3247.113" *) libresocsim_interface5_bank_bus_we;
  assign _2101_ = ~ (* src = "ls180.v:3250.71-3250.106" *) libresocsim_interface5_bank_bus_we;
  assign _2102_ = ~ (* src = "ls180.v:3253.71-3253.106" *) libresocsim_interface5_bank_bus_we;
  assign _2103_ = ~ (* src = "ls180.v:3256.71-3256.106" *) libresocsim_interface5_bank_bus_we;
  assign _2104_ = ~ (* src = "ls180.v:3259.71-3259.106" *) libresocsim_interface5_bank_bus_we;
  assign _2105_ = ~ (* src = "ls180.v:3262.75-3262.110" *) libresocsim_interface5_bank_bus_we;
  assign _2106_ = ~ (* src = "ls180.v:3265.76-3265.111" *) libresocsim_interface5_bank_bus_we;
  assign _2107_ = ~ (* src = "ls180.v:3268.75-3268.110" *) libresocsim_interface5_bank_bus_we;
  assign _2108_ = ~ (* src = "ls180.v:3288.48-3288.83" *) libresocsim_interface6_bank_bus_we;
  assign _2109_ = ~ (* src = "ls180.v:3291.71-3291.106" *) libresocsim_interface6_bank_bus_we;
  assign _2110_ = ~ (* src = "ls180.v:3294.72-3294.107" *) libresocsim_interface6_bank_bus_we;
  assign _2111_ = ~ (* src = "ls180.v:3297.63-3297.98" *) libresocsim_interface6_bank_bus_we;
  assign _2112_ = ~ (* src = "ls180.v:3300.64-3300.99" *) libresocsim_interface6_bank_bus_we;
  assign _2113_ = ~ (* src = "ls180.v:3303.75-3303.110" *) libresocsim_interface6_bank_bus_we;
  assign _2114_ = ~ (* src = "ls180.v:3306.72-3306.107" *) libresocsim_interface6_bank_bus_we;
  assign _2115_ = ~ (* src = "ls180.v:3309.71-3309.106" *) libresocsim_interface6_bank_bus_we;
  assign _2116_ = ~ (* src = "ls180.v:3322.77-3322.112" *) libresocsim_interface7_bank_bus_we;
  assign _2117_ = ~ (* src = "ls180.v:3325.77-3325.112" *) libresocsim_interface7_bank_bus_we;
  assign _2118_ = ~ (* src = "ls180.v:3328.77-3328.112" *) libresocsim_interface7_bank_bus_we;
  assign _2119_ = ~ (* src = "ls180.v:3331.77-3331.112" *) libresocsim_interface7_bank_bus_we;
  assign _2120_ = ~ (* src = "ls180.v:3691.68-3691.317" *) _2289_;
  assign _2121_ = ~ (* src = "ls180.v:3715.68-3715.317" *) _2292_;
  assign _2122_ = ~ (* src = "ls180.v:3739.68-3739.317" *) _2295_;
  assign _2123_ = ~ (* src = "ls180.v:3763.68-3763.317" *) _2298_;
  assign _2124_ = ~ (* src = "ls180.v:4314.62-4314.86" *) libresocsim_ram_bus_ack;
  assign _2125_ = ~ (* src = "ls180.v:4333.8-4333.33" *) libresocsim_zero_trigger;
  assign _2126_ = ~ (* src = "ls180.v:4337.54-4337.74" *) ram_bus_ram_bus_ack;
  assign _2127_ = ~ (* src = "ls180.v:4345.27-4345.45" *) sdram_timer_done0;
  assign _2128_ = ~ (* src = "ls180.v:4415.126-4415.174" *) sdram_bankmachine0_cmd_buffer_lookahead_replace;
  assign _2129_ = ~ (* src = "ls180.v:4421.126-4421.174" *) sdram_bankmachine0_cmd_buffer_lookahead_replace;
  assign _2130_ = ~ (* src = "ls180.v:4422.8-4422.56" *) sdram_bankmachine0_cmd_buffer_lookahead_do_read;
  assign _2131_ = ~ (* src = "ls180.v:4430.8-4430.51" *) sdram_bankmachine0_cmd_buffer_source_valid;
  assign _2132_ = ~ (* src = "ls180.v:4445.8-4445.41" *) sdram_bankmachine0_twtpcon_ready;
  assign _2133_ = ~ (* src = "ls180.v:4461.126-4461.174" *) sdram_bankmachine1_cmd_buffer_lookahead_replace;
  assign _2134_ = ~ (* src = "ls180.v:4467.126-4467.174" *) sdram_bankmachine1_cmd_buffer_lookahead_replace;
  assign _2135_ = ~ (* src = "ls180.v:4468.8-4468.56" *) sdram_bankmachine1_cmd_buffer_lookahead_do_read;
  assign _2136_ = ~ (* src = "ls180.v:4476.8-4476.51" *) sdram_bankmachine1_cmd_buffer_source_valid;
  assign _2137_ = ~ (* src = "ls180.v:4491.8-4491.41" *) sdram_bankmachine1_twtpcon_ready;
  assign _2138_ = ~ (* src = "ls180.v:4507.126-4507.174" *) sdram_bankmachine2_cmd_buffer_lookahead_replace;
  assign _2139_ = ~ (* src = "ls180.v:4513.126-4513.174" *) sdram_bankmachine2_cmd_buffer_lookahead_replace;
  assign _2140_ = ~ (* src = "ls180.v:4514.8-4514.56" *) sdram_bankmachine2_cmd_buffer_lookahead_do_read;
  assign _2141_ = ~ (* src = "ls180.v:4522.8-4522.51" *) sdram_bankmachine2_cmd_buffer_source_valid;
  assign _2142_ = ~ (* src = "ls180.v:4537.8-4537.41" *) sdram_bankmachine2_twtpcon_ready;
  assign _2143_ = ~ (* src = "ls180.v:4553.126-4553.174" *) sdram_bankmachine3_cmd_buffer_lookahead_replace;
  assign _2144_ = ~ (* src = "ls180.v:4559.126-4559.174" *) sdram_bankmachine3_cmd_buffer_lookahead_replace;
  assign _2145_ = ~ (* src = "ls180.v:4560.8-4560.56" *) sdram_bankmachine3_cmd_buffer_lookahead_do_read;
  assign _2146_ = ~ (* src = "ls180.v:4568.8-4568.51" *) sdram_bankmachine3_cmd_buffer_source_valid;
  assign _2147_ = ~ (* src = "ls180.v:4583.8-4583.41" *) sdram_bankmachine3_twtpcon_ready;
  assign _2148_ = ~ (* src = "ls180.v:4591.7-4591.17" *) sdram_en0;
  assign _2149_ = ~ (* src = "ls180.v:4594.8-4594.24" *) sdram_max_time0;
  assign _2150_ = ~ (* src = "ls180.v:4598.7-4598.17" *) sdram_en1;
  assign _2151_ = ~ (* src = "ls180.v:4601.8-4601.24" *) sdram_max_time1;
  assign _2152_ = ~ (* src = "ls180.v:4720.25-4720.38" *) array_muxed2;
  assign _2153_ = ~ (* src = "ls180.v:4721.25-4721.38" *) array_muxed3;
  assign _2154_ = ~ (* src = "ls180.v:4722.24-4722.37" *) array_muxed4;
  assign _2155_ = ~ (* src = "ls180.v:4733.8-4733.28" *) sdram_tccdcon_ready;
  assign _2156_ = ~ (* src = "ls180.v:4748.8-4748.28" *) sdram_twtrcon_ready;
  assign _2157_ = ~ (* src = "ls180.v:4784.31-4784.48" *) uart_phy_tx_busy;
  assign _2158_ = ~ (* src = "ls180.v:4784.54-4784.74" *) uart_phy_sink_ready;
  assign _2159_ = ~ (* src = "ls180.v:4813.7-4813.24" *) uart_phy_rx_busy;
  assign _2160_ = ~ (* src = "ls180.v:4814.9-4814.21" *) uart_phy_rx;
  assign _2161_ = ~ (* src = "ls180.v:4847.8-4847.19" *) tx_trigger;
  assign _2162_ = ~ (* src = "ls180.v:4854.8-4854.19" *) rx_trigger;
  assign _2163_ = ~ (* src = "ls180.v:4864.60-4864.76" *) tx_fifo_replace;
  assign _2164_ = ~ (* src = "ls180.v:4870.60-4870.76" *) tx_fifo_replace;
  assign _2165_ = ~ (* src = "ls180.v:4871.8-4871.24" *) tx_fifo_do_read;
  assign _2166_ = ~ (* src = "ls180.v:4886.60-4886.76" *) rx_fifo_replace;
  assign _2167_ = ~ (* src = "ls180.v:4892.60-4892.76" *) rx_fifo_replace;
  assign _2168_ = ~ (* src = "ls180.v:4893.8-4893.24" *) rx_fifo_do_read;
  assign _2169_ = ~ (* src = "ls180.v:4927.9-4927.32" *) libresocsim_request[0];
  assign _2170_ = ~ (* src = "ls180.v:4938.9-4938.32" *) libresocsim_request[1];
  assign _2171_ = ~ (* src = "ls180.v:4949.9-4949.32" *) libresocsim_request[2];
  assign _2172_ = ~ (* src = "ls180.v:4962.8-4962.25" *) libresocsim_done;
  assign _2173_ = libresocsim_interface0_converted_interface_ack | (* src = "ls180.v:1550.10-1550.86" *) libresocsim_converter0_skip;
  assign _2174_ = libresocsim_interface1_converted_interface_ack | (* src = "ls180.v:1610.10-1610.86" *) libresocsim_converter1_skip;
  assign _2175_ = sdram_sequencer_start0 | (* src = "ls180.v:1812.34-1812.90" *) _1951_;
  assign _2176_ = sdram_bankmachine0_req_wdata_ready | (* src = "ls180.v:1855.54-1855.125" *) sdram_bankmachine0_req_rdata_valid;
  assign _2177_ = sdram_bankmachine0_cmd_buffer_lookahead_source_valid | (* src = "ls180.v:1856.39-1856.136" *) sdram_bankmachine0_cmd_buffer_source_valid;
  assign _2178_ = _2355_ | (* src = "ls180.v:1864.40-1864.155" *) { 4'h0, sdram_bankmachine0_cmd_buffer_source_payload_addr[8:0] };
  assign _2179_ = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | (* src = "ls180.v:1901.117-1901.225" *) sdram_bankmachine0_cmd_buffer_lookahead_replace;
  assign _2180_ = _1983_ | (* src = "ls180.v:1907.52-1907.142" *) sdram_bankmachine0_cmd_buffer_source_ready;
  assign _2181_ = sdram_bankmachine1_req_wdata_ready | (* src = "ls180.v:2012.54-2012.125" *) sdram_bankmachine1_req_rdata_valid;
  assign _2182_ = sdram_bankmachine1_cmd_buffer_lookahead_source_valid | (* src = "ls180.v:2013.39-2013.136" *) sdram_bankmachine1_cmd_buffer_source_valid;
  assign _2183_ = _2356_ | (* src = "ls180.v:2021.40-2021.155" *) { 4'h0, sdram_bankmachine1_cmd_buffer_source_payload_addr[8:0] };
  assign _2184_ = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | (* src = "ls180.v:2058.117-2058.225" *) sdram_bankmachine1_cmd_buffer_lookahead_replace;
  assign _2185_ = _1985_ | (* src = "ls180.v:2064.52-2064.142" *) sdram_bankmachine1_cmd_buffer_source_ready;
  assign _2186_ = sdram_bankmachine2_req_wdata_ready | (* src = "ls180.v:2169.54-2169.125" *) sdram_bankmachine2_req_rdata_valid;
  assign _2187_ = sdram_bankmachine2_cmd_buffer_lookahead_source_valid | (* src = "ls180.v:2170.39-2170.136" *) sdram_bankmachine2_cmd_buffer_source_valid;
  assign _2188_ = _2357_ | (* src = "ls180.v:2178.40-2178.155" *) { 4'h0, sdram_bankmachine2_cmd_buffer_source_payload_addr[8:0] };
  assign _2189_ = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | (* src = "ls180.v:2215.117-2215.225" *) sdram_bankmachine2_cmd_buffer_lookahead_replace;
  assign _2190_ = _1987_ | (* src = "ls180.v:2221.52-2221.142" *) sdram_bankmachine2_cmd_buffer_source_ready;
  assign _2191_ = sdram_bankmachine3_req_wdata_ready | (* src = "ls180.v:2326.54-2326.125" *) sdram_bankmachine3_req_rdata_valid;
  assign _2192_ = sdram_bankmachine3_cmd_buffer_lookahead_source_valid | (* src = "ls180.v:2327.39-2327.136" *) sdram_bankmachine3_cmd_buffer_source_valid;
  assign _2193_ = _2358_ | (* src = "ls180.v:2335.40-2335.155" *) { 4'h0, sdram_bankmachine3_cmd_buffer_source_payload_addr[8:0] };
  assign _2194_ = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | (* src = "ls180.v:2372.117-2372.225" *) sdram_bankmachine3_cmd_buffer_lookahead_replace;
  assign _2195_ = _1989_ | (* src = "ls180.v:2378.52-2378.142" *) sdram_bankmachine3_cmd_buffer_source_ready;
  assign _2196_ = sdram_choose_req_cmd_payload_is_write | (* src = "ls180.v:2477.92-2477.168" *) sdram_choose_req_cmd_payload_is_read;
  assign _2197_ = _1145_ | (* src = "ls180.v:2480.34-2480.179" *) _1146_;
  assign _2198_ = _2197_ | (* src = "ls180.v:2480.33-2480.254" *) _1147_;
  assign _2199_ = _2198_ | (* src = "ls180.v:2480.32-2480.329" *) _1148_;
  assign _2200_ = _1149_ | (* src = "ls180.v:2481.35-2481.182" *) _1150_;
  assign _2201_ = _2200_ | (* src = "ls180.v:2481.34-2481.258" *) _1151_;
  assign _2202_ = _2201_ | (* src = "ls180.v:2481.33-2481.334" *) _1152_;
  assign _2203_ = _1998_ | (* src = "ls180.v:2494.138-2494.292" *) sdram_choose_cmd_want_activates;
  assign _2204_ = _1159_ | (* src = "ls180.v:2494.65-2494.446" *) _1160_;
  assign _2205_ = _2001_ | (* src = "ls180.v:2495.138-2495.292" *) sdram_choose_cmd_want_activates;
  assign _2206_ = _1165_ | (* src = "ls180.v:2495.65-2495.446" *) _1166_;
  assign _2207_ = _2004_ | (* src = "ls180.v:2496.138-2496.292" *) sdram_choose_cmd_want_activates;
  assign _2208_ = _1171_ | (* src = "ls180.v:2496.65-2496.446" *) _1172_;
  assign _2209_ = _2007_ | (* src = "ls180.v:2497.138-2497.292" *) sdram_choose_cmd_want_activates;
  assign _2210_ = _1177_ | (* src = "ls180.v:2497.65-2497.446" *) _1178_;
  assign _2211_ = sdram_choose_cmd_cmd_ready | (* src = "ls180.v:2524.31-2524.89" *) _2008_;
  assign _2212_ = _2011_ | (* src = "ls180.v:2527.138-2527.292" *) sdram_choose_req_want_activates;
  assign _2213_ = _1183_ | (* src = "ls180.v:2527.65-2527.446" *) _1184_;
  assign _2214_ = _2014_ | (* src = "ls180.v:2528.138-2528.292" *) sdram_choose_req_want_activates;
  assign _2215_ = _1189_ | (* src = "ls180.v:2528.65-2528.446" *) _1190_;
  assign _2216_ = _2017_ | (* src = "ls180.v:2529.138-2529.292" *) sdram_choose_req_want_activates;
  assign _2217_ = _1195_ | (* src = "ls180.v:2529.65-2529.446" *) _1196_;
  assign _2218_ = _2020_ | (* src = "ls180.v:2530.138-2530.292" *) sdram_choose_req_want_activates;
  assign _2219_ = _1201_ | (* src = "ls180.v:2530.65-2530.446" *) _1202_;
  assign _2220_ = sdram_choose_req_cmd_ready | (* src = "ls180.v:2593.31-2593.89" *) _2021_;
  assign _2221_ = _2024_ | (* src = "ls180.v:2614.57-2614.191" *) sdram_ras_allowed;
  assign _2222_ = _2025_ | (* src = "ls180.v:2622.10-2622.52" *) sdram_max_time1;
  assign _2223_ = _2028_ | (* src = "ls180.v:2652.57-2652.191" *) sdram_ras_allowed;
  assign _2224_ = _2029_ | (* src = "ls180.v:2660.10-2660.51" *) sdram_max_time0;
  assign _2225_ = subfragments_locked0 | (* src = "ls180.v:2670.91-2670.185" *) _1226_;
  assign _2226_ = _2225_ | (* src = "ls180.v:2670.90-2670.260" *) _1227_;
  assign _2227_ = _2226_ | (* src = "ls180.v:2670.89-2670.335" *) _1228_;
  assign _2228_ = subfragments_locked1 | (* src = "ls180.v:2675.91-2675.185" *) _1232_;
  assign _2229_ = _2228_ | (* src = "ls180.v:2675.90-2675.260" *) _1233_;
  assign _2230_ = _2229_ | (* src = "ls180.v:2675.89-2675.335" *) _1234_;
  assign _2231_ = subfragments_locked2 | (* src = "ls180.v:2680.91-2680.185" *) _1238_;
  assign _2232_ = _2231_ | (* src = "ls180.v:2680.90-2680.260" *) _1239_;
  assign _2233_ = _2232_ | (* src = "ls180.v:2680.89-2680.335" *) _1240_;
  assign _2234_ = subfragments_locked3 | (* src = "ls180.v:2685.91-2685.185" *) _1244_;
  assign _2235_ = _2234_ | (* src = "ls180.v:2685.90-2685.260" *) _1245_;
  assign _2236_ = _2235_ | (* src = "ls180.v:2685.89-2685.335" *) _1246_;
  assign _2237_ = subfragments_locked0 | (* src = "ls180.v:2690.127-2690.221" *) _1250_;
  assign _2238_ = _2237_ | (* src = "ls180.v:2690.126-2690.296" *) _1251_;
  assign _2239_ = _2238_ | (* src = "ls180.v:2690.125-2690.371" *) _1252_;
  assign _2240_ = 1'h0 | (* src = "ls180.v:2690.29-2690.406" *) _1255_;
  assign _2241_ = subfragments_locked1 | (* src = "ls180.v:2690.501-2690.595" *) _1256_;
  assign _2242_ = _2241_ | (* src = "ls180.v:2690.500-2690.670" *) _1257_;
  assign _2243_ = _2242_ | (* src = "ls180.v:2690.499-2690.745" *) _1258_;
  assign _2244_ = _2240_ | (* src = "ls180.v:2690.28-2690.780" *) _1261_;
  assign _2245_ = subfragments_locked2 | (* src = "ls180.v:2690.875-2690.969" *) _1262_;
  assign _2246_ = _2245_ | (* src = "ls180.v:2690.874-2690.1044" *) _1263_;
  assign _2247_ = _2246_ | (* src = "ls180.v:2690.873-2690.1119" *) _1264_;
  assign _2248_ = _2244_ | (* src = "ls180.v:2690.27-2690.1154" *) _1267_;
  assign _2249_ = subfragments_locked3 | (* src = "ls180.v:2690.1249-2690.1343" *) _1268_;
  assign _2250_ = _2249_ | (* src = "ls180.v:2690.1248-2690.1418" *) _1269_;
  assign _2251_ = _2250_ | (* src = "ls180.v:2690.1247-2690.1493" *) _1270_;
  assign _2252_ = _2248_ | (* src = "ls180.v:2690.26-2690.1528" *) _1273_;
  assign _2253_ = litedram_wb_ack | (* src = "ls180.v:2753.10-2753.42" *) converter_skip;
  assign _2254_ = port_cmd_valid | (* src = "ls180.v:2780.30-2780.59" *) cmd_consumed;
  assign _2255_ = port_cmd_valid | (* src = "ls180.v:2781.29-2781.58" *) cmd_consumed;
  assign _2256_ = _1281_ | (* src = "ls180.v:2782.38-2782.100" *) _1282_;
  assign _2257_ = _1284_ | (* src = "ls180.v:2783.19-2783.67" *) cmd_consumed;
  assign _2258_ = _1285_ | (* src = "ls180.v:2784.21-2784.75" *) wdata_consumed;
  assign _2259_ = rx_clear | (* src = "ls180.v:2814.32-2814.59" *) _1287_;
  assign _2260_ = _1290_ | (* src = "ls180.v:2838.15-2838.124" *) _1291_;
  assign _2261_ = _2061_ | (* src = "ls180.v:2853.60-2853.92" *) tx_fifo_re;
  assign _2262_ = tx_fifo_syncfifo_writable | (* src = "ls180.v:2864.52-2864.95" *) tx_fifo_replace;
  assign _2263_ = _2062_ | (* src = "ls180.v:2883.60-2883.92" *) rx_fifo_re;
  assign _2264_ = rx_fifo_syncfifo_writable | (* src = "ls180.v:2894.52-2894.95" *) rx_fifo_replace;
  assign _2265_ = libresocsim_ram_bus_err | (* src = "ls180.v:3077.38-3077.83" *) ram_bus_ram_bus_err;
  assign _2266_ = _2265_ | (* src = "ls180.v:3077.37-3077.120" *) libresocsim_libresoc_xics_icp_err;
  assign _2267_ = _2266_ | (* src = "ls180.v:3077.36-3077.157" *) libresocsim_libresoc_xics_ics_err;
  assign _2268_ = _2267_ | (* src = "ls180.v:3077.35-3077.173" *) wb_sdram_err;
  assign _2269_ = _2268_ | (* src = "ls180.v:3077.34-3077.213" *) libresocsim_libresocsim_wishbone_err;
  assign _2270_ = libresocsim_ram_bus_ack | (* src = "ls180.v:3083.33-3083.78" *) ram_bus_ram_bus_ack;
  assign _2271_ = _2270_ | (* src = "ls180.v:3083.32-3083.115" *) libresocsim_libresoc_xics_icp_ack;
  assign _2272_ = _2271_ | (* src = "ls180.v:3083.31-3083.152" *) libresocsim_libresoc_xics_ics_ack;
  assign _2273_ = _2272_ | (* src = "ls180.v:3083.30-3083.168" *) wb_sdram_ack;
  assign _2274_ = _2273_ | (* src = "ls180.v:3083.29-3083.208" *) libresocsim_libresocsim_wishbone_ack;
  assign _2275_ = _1314_ | (* src = "ls180.v:3084.35-3084.158" *) _1315_;
  assign _2276_ = _2275_ | (* src = "ls180.v:3084.34-3084.234" *) _1316_;
  assign _2277_ = _2276_ | (* src = "ls180.v:3084.33-3084.310" *) _1317_;
  assign _2278_ = _2277_ | (* src = "ls180.v:3084.32-3084.365" *) _1318_;
  assign _2279_ = _2278_ | (* src = "ls180.v:3084.31-3084.444" *) _1319_;
  assign _2280_ = libresocsim_interface0_bank_bus_dat_r | (* src = "ls180.v:3364.52-3364.129" *) libresocsim_interface1_bank_bus_dat_r;
  assign _2281_ = _2280_ | (* src = "ls180.v:3364.51-3364.170" *) libresocsim_interface2_bank_bus_dat_r;
  assign _2282_ = _2281_ | (* src = "ls180.v:3364.50-3364.211" *) libresocsim_interface3_bank_bus_dat_r;
  assign _2283_ = _2282_ | (* src = "ls180.v:3364.49-3364.252" *) libresocsim_interface4_bank_bus_dat_r;
  assign _2284_ = _2283_ | (* src = "ls180.v:3364.48-3364.293" *) libresocsim_interface5_bank_bus_dat_r;
  assign _2285_ = _2284_ | (* src = "ls180.v:3364.47-3364.334" *) libresocsim_interface6_bank_bus_dat_r;
  assign _2286_ = _2285_ | (* src = "ls180.v:3364.46-3364.375" *) libresocsim_interface7_bank_bus_dat_r;
  assign _2287_ = subfragments_locked0 | (* src = "ls180.v:3691.72-3691.166" *) _1544_;
  assign _2288_ = _2287_ | (* src = "ls180.v:3691.71-3691.241" *) _1545_;
  assign _2289_ = _2288_ | (* src = "ls180.v:3691.70-3691.316" *) _1546_;
  assign _2290_ = subfragments_locked1 | (* src = "ls180.v:3715.72-3715.166" *) _1549_;
  assign _2291_ = _2290_ | (* src = "ls180.v:3715.71-3715.241" *) _1550_;
  assign _2292_ = _2291_ | (* src = "ls180.v:3715.70-3715.316" *) _1551_;
  assign _2293_ = subfragments_locked2 | (* src = "ls180.v:3739.72-3739.166" *) _1554_;
  assign _2294_ = _2293_ | (* src = "ls180.v:3739.71-3739.241" *) _1555_;
  assign _2295_ = _2294_ | (* src = "ls180.v:3739.70-3739.316" *) _1556_;
  assign _2296_ = subfragments_locked3 | (* src = "ls180.v:3763.72-3763.166" *) _1559_;
  assign _2297_ = _2296_ | (* src = "ls180.v:3763.71-3763.241" *) _1560_;
  assign _2298_ = _2297_ | (* src = "ls180.v:3763.70-3763.316" *) _1561_;
  assign _2299_ = nc_1[0] | (* src = "ls180.v:4246.15-4246.58" *) libresocsim_libresoc_interrupt[0];
  assign _2300_ = nc_1[1] | (* src = "ls180.v:4247.15-4247.58" *) libresocsim_libresoc_interrupt[0];
  assign _2301_ = nc_1[2] | (* src = "ls180.v:4248.15-4248.58" *) libresocsim_libresoc_interrupt[0];
  assign _2302_ = nc_1[3] | (* src = "ls180.v:4249.15-4249.58" *) libresocsim_libresoc_interrupt[0];
  assign _2303_ = nc_1[4] | (* src = "ls180.v:4250.15-4250.58" *) libresocsim_libresoc_interrupt[0];
  assign _2304_ = nc_1[5] | (* src = "ls180.v:4251.15-4251.58" *) libresocsim_libresoc_interrupt[0];
  assign _2305_ = nc_1[6] | (* src = "ls180.v:4252.15-4252.58" *) libresocsim_libresoc_interrupt[0];
  assign _2306_ = nc_1[7] | (* src = "ls180.v:4253.15-4253.58" *) libresocsim_libresoc_interrupt[0];
  assign _2307_ = nc_1[8] | (* src = "ls180.v:4254.15-4254.58" *) libresocsim_libresoc_interrupt[0];
  assign _2308_ = nc_1[9] | (* src = "ls180.v:4255.15-4255.58" *) libresocsim_libresoc_interrupt[0];
  assign _2309_ = nc_1[10] | (* src = "ls180.v:4256.16-4256.60" *) libresocsim_libresoc_interrupt[0];
  assign _2310_ = nc_1[11] | (* src = "ls180.v:4257.16-4257.60" *) libresocsim_libresoc_interrupt[0];
  assign _2311_ = nc_1[12] | (* src = "ls180.v:4258.16-4258.60" *) libresocsim_libresoc_interrupt[0];
  assign _2312_ = nc_1[13] | (* src = "ls180.v:4259.16-4259.60" *) libresocsim_libresoc_interrupt[0];
  assign _2313_ = nc_1[14] | (* src = "ls180.v:4260.16-4260.60" *) libresocsim_libresoc_interrupt[0];
  assign _2314_ = nc_1[15] | (* src = "ls180.v:4261.16-4261.60" *) libresocsim_libresoc_interrupt[0];
  assign _2315_ = nc_1[16] | (* src = "ls180.v:4262.16-4262.60" *) libresocsim_libresoc_interrupt[0];
  assign _2316_ = nc_1[17] | (* src = "ls180.v:4263.16-4263.60" *) libresocsim_libresoc_interrupt[0];
  assign _2317_ = nc_1[18] | (* src = "ls180.v:4264.16-4264.60" *) libresocsim_libresoc_interrupt[0];
  assign _2318_ = nc_1[19] | (* src = "ls180.v:4265.16-4265.60" *) libresocsim_libresoc_interrupt[0];
  assign _2319_ = nc_1[20] | (* src = "ls180.v:4266.16-4266.60" *) libresocsim_libresoc_interrupt[0];
  assign _2320_ = nc_1[21] | (* src = "ls180.v:4267.16-4267.60" *) libresocsim_libresoc_interrupt[0];
  assign _2321_ = nc_1[22] | (* src = "ls180.v:4268.16-4268.60" *) libresocsim_libresoc_interrupt[0];
  assign _2322_ = nc_1[23] | (* src = "ls180.v:4269.16-4269.60" *) libresocsim_libresoc_interrupt[0];
  assign _2323_ = nc_1[24] | (* src = "ls180.v:4270.16-4270.60" *) libresocsim_libresoc_interrupt[0];
  assign _2324_ = nc_1[25] | (* src = "ls180.v:4271.16-4271.60" *) libresocsim_libresoc_interrupt[0];
  assign _2325_ = nc_1[26] | (* src = "ls180.v:4272.16-4272.60" *) libresocsim_libresoc_interrupt[0];
  assign _2326_ = nc_1[27] | (* src = "ls180.v:4273.16-4273.60" *) libresocsim_libresoc_interrupt[0];
  assign _2327_ = nc_1[28] | (* src = "ls180.v:4274.16-4274.60" *) libresocsim_libresoc_interrupt[0];
  assign _2328_ = nc_1[29] | (* src = "ls180.v:4275.16-4275.60" *) libresocsim_libresoc_interrupt[0];
  assign _2329_ = nc_1[30] | (* src = "ls180.v:4276.16-4276.60" *) libresocsim_libresoc_interrupt[0];
  assign _2330_ = nc_1[31] | (* src = "ls180.v:4277.16-4277.60" *) libresocsim_libresoc_interrupt[0];
  assign _2331_ = nc_1[32] | (* src = "ls180.v:4278.16-4278.60" *) libresocsim_libresoc_interrupt[0];
  assign _2332_ = nc_1[33] | (* src = "ls180.v:4279.16-4279.60" *) libresocsim_libresoc_interrupt[0];
  assign _2333_ = nc_1[34] | (* src = "ls180.v:4280.16-4280.60" *) libresocsim_libresoc_interrupt[0];
  assign _2334_ = nc_1[35] | (* src = "ls180.v:4281.16-4281.60" *) libresocsim_libresoc_interrupt[0];
  assign _2335_ = nc_1[36] | (* src = "ls180.v:4282.16-4282.60" *) libresocsim_libresoc_interrupt[0];
  assign _2336_ = nc_1[37] | (* src = "ls180.v:4283.16-4283.60" *) libresocsim_libresoc_interrupt[0];
  assign _2337_ = nc_1[38] | (* src = "ls180.v:4284.16-4284.60" *) libresocsim_libresoc_interrupt[0];
  assign _2338_ = nc_1[39] | (* src = "ls180.v:4285.16-4285.60" *) libresocsim_libresoc_interrupt[0];
  assign _2339_ = libresocsim_interface0_converted_interface_ack | (* src = "ls180.v:4286.7-4286.83" *) libresocsim_converter0_skip;
  assign _2340_ = libresocsim_interface1_converted_interface_ack | (* src = "ls180.v:4297.7-4297.83" *) libresocsim_converter1_skip;
  assign _2341_ = _2131_ | (* src = "ls180.v:4430.7-4430.97" *) sdram_bankmachine0_cmd_buffer_source_ready;
  assign _2342_ = _2136_ | (* src = "ls180.v:4476.7-4476.97" *) sdram_bankmachine1_cmd_buffer_source_ready;
  assign _2343_ = _2141_ | (* src = "ls180.v:4522.7-4522.97" *) sdram_bankmachine2_cmd_buffer_source_ready;
  assign _2344_ = _2146_ | (* src = "ls180.v:4568.7-4568.97" *) sdram_bankmachine3_cmd_buffer_source_ready;
  assign _2345_ = 1'h0 | (* src = "ls180.v:4756.45-4756.130" *) _1619_;
  assign _2346_ = _2345_ | (* src = "ls180.v:4756.44-4756.212" *) _1620_;
  assign _2347_ = _2346_ | (* src = "ls180.v:4756.43-4756.294" *) _1621_;
  assign _2348_ = _2347_ | (* src = "ls180.v:4756.42-4756.376" *) _1622_;
  assign _2349_ = 1'h0 | (* src = "ls180.v:4757.46-4757.131" *) _1623_;
  assign _2350_ = _2349_ | (* src = "ls180.v:4757.45-4757.213" *) _1624_;
  assign _2351_ = _2350_ | (* src = "ls180.v:4757.44-4757.295" *) _1625_;
  assign _2352_ = _2351_ | (* src = "ls180.v:4757.43-4757.377" *) _1626_;
  assign _2353_ = litedram_wb_ack | (* src = "ls180.v:4761.7-4761.39" *) converter_skip;
  assign _2354_ = sys_rst_1 | (* src = "ls180.v:5667.8-5667.46" *) libresocsim_libresoc_reset;
  assign _2355_ = sdram_bankmachine0_auto_precharge <<< (* src = "ls180.v:1864.41-1864.84" *) 4'ha;
  assign _2356_ = sdram_bankmachine1_auto_precharge <<< (* src = "ls180.v:2021.41-2021.84" *) 4'ha;
  assign _2357_ = sdram_bankmachine2_auto_precharge <<< (* src = "ls180.v:2178.41-2178.84" *) 4'ha;
  assign _2358_ = sdram_bankmachine3_auto_precharge <<< (* src = "ls180.v:2335.41-2335.84" *) 4'ha;
  assign _2359_ = sdram_bankmachine0_cmd_buffer_lookahead_produce - (* src = "ls180.v:1895.58-1895.112" *) 1'h1;
  assign _2360_ = sdram_bankmachine1_cmd_buffer_lookahead_produce - (* src = "ls180.v:2052.58-2052.112" *) 1'h1;
  assign _2361_ = sdram_bankmachine2_cmd_buffer_lookahead_produce - (* src = "ls180.v:2209.58-2209.112" *) 1'h1;
  assign _2362_ = sdram_bankmachine3_cmd_buffer_lookahead_produce - (* src = "ls180.v:2366.58-2366.112" *) 1'h1;
  assign _2363_ = litedram_wb_adr - (* src = "ls180.v:2772.33-2772.65" *) 31'h48000000;
  assign _2364_ = tx_fifo_produce - (* src = "ls180.v:2858.26-2858.48" *) 1'h1;
  assign _2365_ = rx_fifo_produce - (* src = "ls180.v:2888.26-2888.48" *) 1'h1;
  assign _2366_ = libresocsim_value - (* src = "ls180.v:4321.26-4321.50" *) 1'h1;
  assign _2367_ = sdram_timer_count1 - (* src = "ls180.v:4346.26-4346.51" *) 1'h1;
  assign _2368_ = sdram_postponer_count - (* src = "ls180.v:4352.29-4352.57" *) 1'h1;
  assign _2369_ = sdram_sequencer_count - (* src = "ls180.v:4363.31-4363.59" *) 1'h1;
  assign _2370_ = sdram_bankmachine0_cmd_buffer_lookahead_level - (* src = "ls180.v:4427.54-4427.106" *) 1'h1;
  assign _2371_ = sdram_bankmachine0_twtpcon_count - (* src = "ls180.v:4446.41-4446.80" *) 1'h1;
  assign _2372_ = sdram_bankmachine1_cmd_buffer_lookahead_level - (* src = "ls180.v:4473.54-4473.106" *) 1'h1;
  assign _2373_ = sdram_bankmachine1_twtpcon_count - (* src = "ls180.v:4492.41-4492.80" *) 1'h1;
  assign _2374_ = sdram_bankmachine2_cmd_buffer_lookahead_level - (* src = "ls180.v:4519.54-4519.106" *) 1'h1;
  assign _2375_ = sdram_bankmachine2_twtpcon_count - (* src = "ls180.v:4538.41-4538.80" *) 1'h1;
  assign _2376_ = sdram_bankmachine3_cmd_buffer_lookahead_level - (* src = "ls180.v:4565.54-4565.106" *) 1'h1;
  assign _2377_ = sdram_bankmachine3_twtpcon_count - (* src = "ls180.v:4584.41-4584.80" *) 1'h1;
  assign _2378_ = sdram_time0 - (* src = "ls180.v:4595.20-4595.38" *) 1'h1;
  assign _2379_ = sdram_time1 - (* src = "ls180.v:4602.20-4602.38" *) 1'h1;
  assign _2380_ = sdram_tccdcon_count - (* src = "ls180.v:4734.28-4734.54" *) 1'h1;
  assign _2381_ = sdram_twtrcon_count - (* src = "ls180.v:4749.28-4749.54" *) 1'h1;
  assign _2382_ = tx_fifo_level0 - (* src = "ls180.v:4876.23-4876.44" *) 1'h1;
  assign _2383_ = rx_fifo_level0 - (* src = "ls180.v:4898.23-4898.44" *) 1'h1;
  assign _2384_ = libresocsim_count - (* src = "ls180.v:4963.26-4963.50" *) 1'h1;
  (* module_not_derived = 32'd1 *)
  (* src = "ls180.v:5574.13-5897.2" *)
  test_issuer test_issuer (
    .TAP_bus__tck(libresocsim_libresoc_jtag_tck),
    .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi),
    .TAP_bus__tdo(libresocsim_libresoc_jtag_tdo),
    .TAP_bus__tms(libresocsim_libresoc_jtag_tms),
    .busy_o(libresocsim_libresoc1),
    .clk(sys_clk_1),
    .core_bigendian_i(1'h0),
    .dbus__ack(libresocsim_libresoc_dbus_ack),
    .dbus__adr(libresocsim_libresoc_dbus_adr),
    .dbus__bte(1'h0),
    .dbus__cti(1'h0),
    .dbus__cyc(libresocsim_libresoc_dbus_cyc),
    .dbus__dat_r(libresocsim_libresoc_dbus_dat_r),
    .dbus__dat_w(libresocsim_libresoc_dbus_dat_w),
    .dbus__err(libresocsim_libresoc_dbus_err),
    .dbus__sel(libresocsim_libresoc_dbus_sel),
    .dbus__stb(libresocsim_libresoc_dbus_stb),
    .dbus__we(libresocsim_libresoc_dbus_we),
    .eint_0__core__i(libresocsim_libresoc_constraintmanager_eint_0),
    .eint_0__pad__i(eint_0),
    .eint_1__core__i(libresocsim_libresoc_constraintmanager_eint_1),
    .eint_1__pad__i(eint_1),
    .eint_2__core__i(libresocsim_libresoc_constraintmanager_eint_2),
    .eint_2__pad__i(eint_2),
    .gpio_e10__core__i(libresocsim_libresoc_constraintmanager_gpio_i[10]),
    .gpio_e10__core__o(libresocsim_libresoc_constraintmanager_gpio_o[10]),
    .gpio_e10__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[10]),
    .gpio_e10__pad__i(gpio_i[10]),
    .gpio_e10__pad__o(gpio_o[10]),
    .gpio_e10__pad__oe(gpio_oe[10]),
    .gpio_e11__core__i(libresocsim_libresoc_constraintmanager_gpio_i[11]),
    .gpio_e11__core__o(libresocsim_libresoc_constraintmanager_gpio_o[11]),
    .gpio_e11__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[11]),
    .gpio_e11__pad__i(gpio_i[11]),
    .gpio_e11__pad__o(gpio_o[11]),
    .gpio_e11__pad__oe(gpio_oe[11]),
    .gpio_e12__core__i(libresocsim_libresoc_constraintmanager_gpio_i[12]),
    .gpio_e12__core__o(libresocsim_libresoc_constraintmanager_gpio_o[12]),
    .gpio_e12__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[12]),
    .gpio_e12__pad__i(gpio_i[12]),
    .gpio_e12__pad__o(gpio_o[12]),
    .gpio_e12__pad__oe(gpio_oe[12]),
    .gpio_e13__core__i(libresocsim_libresoc_constraintmanager_gpio_i[13]),
    .gpio_e13__core__o(libresocsim_libresoc_constraintmanager_gpio_o[13]),
    .gpio_e13__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[13]),
    .gpio_e13__pad__i(gpio_i[13]),
    .gpio_e13__pad__o(gpio_o[13]),
    .gpio_e13__pad__oe(gpio_oe[13]),
    .gpio_e14__core__i(libresocsim_libresoc_constraintmanager_gpio_i[14]),
    .gpio_e14__core__o(libresocsim_libresoc_constraintmanager_gpio_o[14]),
    .gpio_e14__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[14]),
    .gpio_e14__pad__i(gpio_i[14]),
    .gpio_e14__pad__o(gpio_o[14]),
    .gpio_e14__pad__oe(gpio_oe[14]),
    .gpio_e15__core__i(libresocsim_libresoc_constraintmanager_gpio_i[15]),
    .gpio_e15__core__o(libresocsim_libresoc_constraintmanager_gpio_o[15]),
    .gpio_e15__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[15]),
    .gpio_e15__pad__i(gpio_i[15]),
    .gpio_e15__pad__o(gpio_o[15]),
    .gpio_e15__pad__oe(gpio_oe[15]),
    .gpio_e8__core__i(libresocsim_libresoc_constraintmanager_gpio_i[8]),
    .gpio_e8__core__o(libresocsim_libresoc_constraintmanager_gpio_o[8]),
    .gpio_e8__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[8]),
    .gpio_e8__pad__i(gpio_i[8]),
    .gpio_e8__pad__o(gpio_o[8]),
    .gpio_e8__pad__oe(gpio_oe[8]),
    .gpio_e9__core__i(libresocsim_libresoc_constraintmanager_gpio_i[9]),
    .gpio_e9__core__o(libresocsim_libresoc_constraintmanager_gpio_o[9]),
    .gpio_e9__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[9]),
    .gpio_e9__pad__i(gpio_i[9]),
    .gpio_e9__pad__o(gpio_o[9]),
    .gpio_e9__pad__oe(gpio_oe[9]),
    .gpio_s0__core__i(libresocsim_libresoc_constraintmanager_gpio_i[0]),
    .gpio_s0__core__o(libresocsim_libresoc_constraintmanager_gpio_o[0]),
    .gpio_s0__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[0]),
    .gpio_s0__pad__i(gpio_i[0]),
    .gpio_s0__pad__o(gpio_o[0]),
    .gpio_s0__pad__oe(gpio_oe[0]),
    .gpio_s1__core__i(libresocsim_libresoc_constraintmanager_gpio_i[1]),
    .gpio_s1__core__o(libresocsim_libresoc_constraintmanager_gpio_o[1]),
    .gpio_s1__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[1]),
    .gpio_s1__pad__i(gpio_i[1]),
    .gpio_s1__pad__o(gpio_o[1]),
    .gpio_s1__pad__oe(gpio_oe[1]),
    .gpio_s2__core__i(libresocsim_libresoc_constraintmanager_gpio_i[2]),
    .gpio_s2__core__o(libresocsim_libresoc_constraintmanager_gpio_o[2]),
    .gpio_s2__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[2]),
    .gpio_s2__pad__i(gpio_i[2]),
    .gpio_s2__pad__o(gpio_o[2]),
    .gpio_s2__pad__oe(gpio_oe[2]),
    .gpio_s3__core__i(libresocsim_libresoc_constraintmanager_gpio_i[3]),
    .gpio_s3__core__o(libresocsim_libresoc_constraintmanager_gpio_o[3]),
    .gpio_s3__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[3]),
    .gpio_s3__pad__i(gpio_i[3]),
    .gpio_s3__pad__o(gpio_o[3]),
    .gpio_s3__pad__oe(gpio_oe[3]),
    .gpio_s4__core__i(libresocsim_libresoc_constraintmanager_gpio_i[4]),
    .gpio_s4__core__o(libresocsim_libresoc_constraintmanager_gpio_o[4]),
    .gpio_s4__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[4]),
    .gpio_s4__pad__i(gpio_i[4]),
    .gpio_s4__pad__o(gpio_o[4]),
    .gpio_s4__pad__oe(gpio_oe[4]),
    .gpio_s5__core__i(libresocsim_libresoc_constraintmanager_gpio_i[5]),
    .gpio_s5__core__o(libresocsim_libresoc_constraintmanager_gpio_o[5]),
    .gpio_s5__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[5]),
    .gpio_s5__pad__i(gpio_i[5]),
    .gpio_s5__pad__o(gpio_o[5]),
    .gpio_s5__pad__oe(gpio_oe[5]),
    .gpio_s6__core__i(libresocsim_libresoc_constraintmanager_gpio_i[6]),
    .gpio_s6__core__o(libresocsim_libresoc_constraintmanager_gpio_o[6]),
    .gpio_s6__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[6]),
    .gpio_s6__pad__i(gpio_i[6]),
    .gpio_s6__pad__o(gpio_o[6]),
    .gpio_s6__pad__oe(gpio_oe[6]),
    .gpio_s7__core__i(libresocsim_libresoc_constraintmanager_gpio_i[7]),
    .gpio_s7__core__o(libresocsim_libresoc_constraintmanager_gpio_o[7]),
    .gpio_s7__core__oe(libresocsim_libresoc_constraintmanager_gpio_oe[7]),
    .gpio_s7__pad__i(gpio_i[7]),
    .gpio_s7__pad__o(gpio_o[7]),
    .gpio_s7__pad__oe(gpio_oe[7]),
    .ibus__ack(libresocsim_libresoc_ibus_ack),
    .ibus__adr(libresocsim_libresoc_ibus_adr),
    .ibus__bte(1'h0),
    .ibus__cti(1'h0),
    .ibus__cyc(libresocsim_libresoc_ibus_cyc),
    .ibus__dat_r(libresocsim_libresoc_ibus_dat_r),
    .ibus__dat_w(libresocsim_libresoc_ibus_dat_w),
    .ibus__err(libresocsim_libresoc_ibus_err),
    .ibus__sel(libresocsim_libresoc_ibus_sel),
    .ibus__stb(libresocsim_libresoc_ibus_stb),
    .ibus__we(libresocsim_libresoc_ibus_we),
    .icp_wb__ack(libresocsim_libresoc_xics_icp_ack),
    .icp_wb__adr(libresocsim_libresoc_xics_icp_adr),
    .icp_wb__cyc(libresocsim_libresoc_xics_icp_cyc),
    .icp_wb__dat_r(libresocsim_libresoc_xics_icp_dat_r),
    .icp_wb__dat_w(libresocsim_libresoc_xics_icp_dat_w),
    .icp_wb__err(libresocsim_libresoc_xics_icp_err),
    .icp_wb__sel(libresocsim_libresoc_xics_icp_sel),
    .icp_wb__stb(libresocsim_libresoc_xics_icp_stb),
    .icp_wb__we(libresocsim_libresoc_xics_icp_we),
    .ics_wb__ack(libresocsim_libresoc_xics_ics_ack),
    .ics_wb__adr(libresocsim_libresoc_xics_ics_adr),
    .ics_wb__cyc(libresocsim_libresoc_xics_ics_cyc),
    .ics_wb__dat_r(libresocsim_libresoc_xics_ics_dat_r),
    .ics_wb__dat_w(libresocsim_libresoc_xics_ics_dat_w),
    .ics_wb__err(libresocsim_libresoc_xics_ics_err),
    .ics_wb__sel(libresocsim_libresoc_xics_ics_sel),
    .ics_wb__stb(libresocsim_libresoc_xics_ics_stb),
    .ics_wb__we(libresocsim_libresoc_xics_ics_we),
    .int_level_i(libresocsim_libresoc_interrupt),
    .jtag_wb__ack(libresocsim_libresoc_jtag_wb_ack),
    .jtag_wb__adr(libresocsim_libresoc_jtag_wb_adr),
    .jtag_wb__cyc(libresocsim_libresoc_jtag_wb_cyc),
    .jtag_wb__dat_r(libresocsim_libresoc_jtag_wb_dat_r),
    .jtag_wb__dat_w(libresocsim_libresoc_jtag_wb_dat_w),
    .jtag_wb__err(libresocsim_libresoc_jtag_wb_err),
    .jtag_wb__sel(libresocsim_libresoc_jtag_wb_sel),
    .jtag_wb__stb(libresocsim_libresoc_jtag_wb_stb),
    .jtag_wb__we(libresocsim_libresoc_jtag_wb_we),
    .memerr_o(libresocsim_libresoc2),
    .mspi0_clk__core__o(libresocsim_libresoc_constraintmanager_spimaster_clk),
    .mspi0_clk__pad__o(spimaster_clk),
    .mspi0_cs_n__core__o(libresocsim_libresoc_constraintmanager_spimaster_cs_n),
    .mspi0_cs_n__pad__o(spimaster_cs_n),
    .mspi0_miso__core__i(libresocsim_libresoc_constraintmanager_spimaster_miso),
    .mspi0_miso__pad__i(spimaster_miso),
    .mspi0_mosi__core__o(libresocsim_libresoc_constraintmanager_spimaster_mosi),
    .mspi0_mosi__pad__o(spimaster_mosi),
    .mtwi_scl__core__o(libresocsim_libresoc_constraintmanager_i2c_scl),
    .mtwi_scl__pad__o(i2c_scl),
    .mtwi_sda__core__i(libresocsim_libresoc_constraintmanager_i2c_sda_i),
    .mtwi_sda__core__o(libresocsim_libresoc_constraintmanager_i2c_sda_o),
    .mtwi_sda__core__oe(libresocsim_libresoc_constraintmanager_i2c_sda_oe),
    .mtwi_sda__pad__i(i2c_sda_i),
    .mtwi_sda__pad__o(i2c_sda_o),
    .mtwi_sda__pad__oe(i2c_sda_oe),
    .pc_i(libresocsim_libresoc0),
    .pc_i_ok(1'h0),
    .pc_o(libresocsim_libresoc3),
    .rst(_2354_),
    .sdr_a_0__core__o(libresocsim_libresoc_constraintmanager_sdram_a[0]),
    .sdr_a_0__pad__o(sdram_a[0]),
    .sdr_a_10__core__o(libresocsim_libresoc_constraintmanager_sdram_a[10]),
    .sdr_a_10__pad__o(sdram_a[10]),
    .sdr_a_11__core__o(libresocsim_libresoc_constraintmanager_sdram_a[11]),
    .sdr_a_11__pad__o(sdram_a[11]),
    .sdr_a_12__core__o(libresocsim_libresoc_constraintmanager_sdram_a[12]),
    .sdr_a_12__pad__o(sdram_a[12]),
    .sdr_a_1__core__o(libresocsim_libresoc_constraintmanager_sdram_a[1]),
    .sdr_a_1__pad__o(sdram_a[1]),
    .sdr_a_2__core__o(libresocsim_libresoc_constraintmanager_sdram_a[2]),
    .sdr_a_2__pad__o(sdram_a[2]),
    .sdr_a_3__core__o(libresocsim_libresoc_constraintmanager_sdram_a[3]),
    .sdr_a_3__pad__o(sdram_a[3]),
    .sdr_a_4__core__o(libresocsim_libresoc_constraintmanager_sdram_a[4]),
    .sdr_a_4__pad__o(sdram_a[4]),
    .sdr_a_5__core__o(libresocsim_libresoc_constraintmanager_sdram_a[5]),
    .sdr_a_5__pad__o(sdram_a[5]),
    .sdr_a_6__core__o(libresocsim_libresoc_constraintmanager_sdram_a[6]),
    .sdr_a_6__pad__o(sdram_a[6]),
    .sdr_a_7__core__o(libresocsim_libresoc_constraintmanager_sdram_a[7]),
    .sdr_a_7__pad__o(sdram_a[7]),
    .sdr_a_8__core__o(libresocsim_libresoc_constraintmanager_sdram_a[8]),
    .sdr_a_8__pad__o(sdram_a[8]),
    .sdr_a_9__core__o(libresocsim_libresoc_constraintmanager_sdram_a[9]),
    .sdr_a_9__pad__o(sdram_a[9]),
    .sdr_ba_0__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[0]),
    .sdr_ba_0__pad__o(sdram_ba[0]),
    .sdr_ba_1__core__o(libresocsim_libresoc_constraintmanager_sdram_ba[1]),
    .sdr_ba_1__pad__o(sdram_ba[1]),
    .sdr_cas_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cas_n),
    .sdr_cas_n__pad__o(sdram_cas_n),
    .sdr_cke__core__o(libresocsim_libresoc_constraintmanager_sdram_cke),
    .sdr_cke__pad__o(sdram_cke),
    .sdr_clock__core__o(libresocsim_libresoc_constraintmanager_sdram_clock),
    .sdr_clock__pad__o(sdram_clock),
    .sdr_cs_n__core__o(libresocsim_libresoc_constraintmanager_sdram_cs_n),
    .sdr_cs_n__pad__o(sdram_cs_n),
    .sdr_dm_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[0]),
    .sdr_dm_0__pad__o(sdram_dm[0]),
    .sdr_dm_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dm[1]),
    .sdr_dm_1__pad__o(sdram_dm[1]),
    .sdr_dq_0__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[0]),
    .sdr_dq_0__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[0]),
    .sdr_dq_0__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[0]),
    .sdr_dq_0__pad__i(sdram_dq_i[0]),
    .sdr_dq_0__pad__o(sdram_dq_o[0]),
    .sdr_dq_0__pad__oe(sdram_dq_oe[0]),
    .sdr_dq_10__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[10]),
    .sdr_dq_10__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[10]),
    .sdr_dq_10__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[10]),
    .sdr_dq_10__pad__i(sdram_dq_i[10]),
    .sdr_dq_10__pad__o(sdram_dq_o[10]),
    .sdr_dq_10__pad__oe(sdram_dq_oe[10]),
    .sdr_dq_11__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[11]),
    .sdr_dq_11__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[11]),
    .sdr_dq_11__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[11]),
    .sdr_dq_11__pad__i(sdram_dq_i[11]),
    .sdr_dq_11__pad__o(sdram_dq_o[11]),
    .sdr_dq_11__pad__oe(sdram_dq_oe[11]),
    .sdr_dq_12__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[12]),
    .sdr_dq_12__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[12]),
    .sdr_dq_12__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[12]),
    .sdr_dq_12__pad__i(sdram_dq_i[12]),
    .sdr_dq_12__pad__o(sdram_dq_o[12]),
    .sdr_dq_12__pad__oe(sdram_dq_oe[12]),
    .sdr_dq_13__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[13]),
    .sdr_dq_13__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[13]),
    .sdr_dq_13__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[13]),
    .sdr_dq_13__pad__i(sdram_dq_i[13]),
    .sdr_dq_13__pad__o(sdram_dq_o[13]),
    .sdr_dq_13__pad__oe(sdram_dq_oe[13]),
    .sdr_dq_14__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[14]),
    .sdr_dq_14__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[14]),
    .sdr_dq_14__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[14]),
    .sdr_dq_14__pad__i(sdram_dq_i[14]),
    .sdr_dq_14__pad__o(sdram_dq_o[14]),
    .sdr_dq_14__pad__oe(sdram_dq_oe[14]),
    .sdr_dq_15__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[15]),
    .sdr_dq_15__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[15]),
    .sdr_dq_15__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[15]),
    .sdr_dq_15__pad__i(sdram_dq_i[15]),
    .sdr_dq_15__pad__o(sdram_dq_o[15]),
    .sdr_dq_15__pad__oe(sdram_dq_oe[15]),
    .sdr_dq_1__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[1]),
    .sdr_dq_1__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[1]),
    .sdr_dq_1__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[1]),
    .sdr_dq_1__pad__i(sdram_dq_i[1]),
    .sdr_dq_1__pad__o(sdram_dq_o[1]),
    .sdr_dq_1__pad__oe(sdram_dq_oe[1]),
    .sdr_dq_2__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[2]),
    .sdr_dq_2__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[2]),
    .sdr_dq_2__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[2]),
    .sdr_dq_2__pad__i(sdram_dq_i[2]),
    .sdr_dq_2__pad__o(sdram_dq_o[2]),
    .sdr_dq_2__pad__oe(sdram_dq_oe[2]),
    .sdr_dq_3__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[3]),
    .sdr_dq_3__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[3]),
    .sdr_dq_3__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[3]),
    .sdr_dq_3__pad__i(sdram_dq_i[3]),
    .sdr_dq_3__pad__o(sdram_dq_o[3]),
    .sdr_dq_3__pad__oe(sdram_dq_oe[3]),
    .sdr_dq_4__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[4]),
    .sdr_dq_4__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[4]),
    .sdr_dq_4__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[4]),
    .sdr_dq_4__pad__i(sdram_dq_i[4]),
    .sdr_dq_4__pad__o(sdram_dq_o[4]),
    .sdr_dq_4__pad__oe(sdram_dq_oe[4]),
    .sdr_dq_5__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[5]),
    .sdr_dq_5__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[5]),
    .sdr_dq_5__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[5]),
    .sdr_dq_5__pad__i(sdram_dq_i[5]),
    .sdr_dq_5__pad__o(sdram_dq_o[5]),
    .sdr_dq_5__pad__oe(sdram_dq_oe[5]),
    .sdr_dq_6__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[6]),
    .sdr_dq_6__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[6]),
    .sdr_dq_6__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[6]),
    .sdr_dq_6__pad__i(sdram_dq_i[6]),
    .sdr_dq_6__pad__o(sdram_dq_o[6]),
    .sdr_dq_6__pad__oe(sdram_dq_oe[6]),
    .sdr_dq_7__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[7]),
    .sdr_dq_7__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[7]),
    .sdr_dq_7__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[7]),
    .sdr_dq_7__pad__i(sdram_dq_i[7]),
    .sdr_dq_7__pad__o(sdram_dq_o[7]),
    .sdr_dq_7__pad__oe(sdram_dq_oe[7]),
    .sdr_dq_8__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[8]),
    .sdr_dq_8__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[8]),
    .sdr_dq_8__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[8]),
    .sdr_dq_8__pad__i(sdram_dq_i[8]),
    .sdr_dq_8__pad__o(sdram_dq_o[8]),
    .sdr_dq_8__pad__oe(sdram_dq_oe[8]),
    .sdr_dq_9__core__i(libresocsim_libresoc_constraintmanager_sdram_dq_i[9]),
    .sdr_dq_9__core__o(libresocsim_libresoc_constraintmanager_sdram_dq_o[9]),
    .sdr_dq_9__core__oe(libresocsim_libresoc_constraintmanager_sdram_dq_oe[9]),
    .sdr_dq_9__pad__i(sdram_dq_i[9]),
    .sdr_dq_9__pad__o(sdram_dq_o[9]),
    .sdr_dq_9__pad__oe(sdram_dq_oe[9]),
    .sdr_ras_n__core__o(libresocsim_libresoc_constraintmanager_sdram_ras_n),
    .sdr_ras_n__pad__o(sdram_ras_n),
    .sdr_we_n__core__o(libresocsim_libresoc_constraintmanager_sdram_we_n),
    .sdr_we_n__pad__o(sdram_we_n)
  );
  always @* begin
    if (\initial ) begin end
  end
  always @* begin
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
  end
  always @* begin
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0968_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine0_state <= _0968_;
  end
  always @* begin
    if (\initial ) begin end
    _0967_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine0_next_state <= _0967_;
  end
  always @* begin
    if (\initial ) begin end
    _0970_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine1_state <= _0970_;
  end
  always @* begin
    if (\initial ) begin end
    _0969_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine1_next_state <= _0969_;
  end
  always @* begin
    if (\initial ) begin end
    _0972_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine2_state <= _0972_;
  end
  always @* begin
    if (\initial ) begin end
    _0971_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine2_next_state <= _0971_;
  end
  always @* begin
    if (\initial ) begin end
    _0974_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine3_state <= _0974_;
  end
  always @* begin
    if (\initial ) begin end
    _0973_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_bankmachine3_next_state <= _0973_;
  end
  always @* begin
    if (\initial ) begin end
    _0980_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_multiplexer_state <= _0980_;
  end
  always @* begin
    if (\initial ) begin end
    _0979_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_multiplexer_next_state <= _0979_;
  end
  always @* begin
    if (\initial ) begin end
    _0149_ = 3'h0;
  end
  always @* begin
      libresocsim_libresoc_jtag_wb_cti <= _0149_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0148_ = 2'h0;
  end
  always @* begin
      libresocsim_libresoc_jtag_wb_bte <= _0148_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0495_ = 1'h0;
  end
  always @* begin
      subfragments_locked0 <= _0495_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0496_ = 1'h0;
  end
  always @* begin
      subfragments_locked1 <= _0496_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0497_ = 1'h0;
  end
  always @* begin
      subfragments_locked2 <= _0497_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0498_ = 1'h0;
  end
  always @* begin
      subfragments_locked3 <= _0498_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0985_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_new_master_wdata_ready <= _0985_;
  end
  always @* begin
    if (\initial ) begin end
    _0981_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_new_master_rdata_valid0 <= _0981_;
  end
  always @* begin
    if (\initial ) begin end
    _0982_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_new_master_rdata_valid1 <= _0982_;
  end
  always @* begin
    if (\initial ) begin end
    _0983_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_new_master_rdata_valid2 <= _0983_;
  end
  always @* begin
    if (\initial ) begin end
    _0984_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_new_master_rdata_valid3 <= _0984_;
  end
  always @* begin
    if (\initial ) begin end
    _0989_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_state <= _0989_;
  end
  always @* begin
    if (\initial ) begin end
    _0986_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_next_state <= _0986_;
  end
  always @* begin
    if (\initial ) begin end
    _0599_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      converter_counter_subfragments_next_value <= _0599_;
  end
  always @* begin
    if (\initial ) begin end
    _0600_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      converter_counter_subfragments_next_value_ce <= _0600_;
  end
  always @* begin
    if (\initial ) begin end
    _0685_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_adr <= _0685_;
  end
  always @* begin
    if (\initial ) begin end
    _0691_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_we <= _0691_;
  end
  always @* begin
    if (\initial ) begin end
    _0688_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_dat_w <= _0688_;
  end
  always @* begin
    if (\initial ) begin end
    _0695_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_wishbone_dat_r <= _0695_;
  end
  always @* begin
    if (\initial ) begin end
    _0694_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_wishbone_ack <= _0694_;
  end
  always @* begin
    if (\initial ) begin end
    _0161_ = 1'h0;
  end
  always @* begin
      libresocsim_libresocsim_wishbone_err <= _0161_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0707_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_shared_dat_r <= _0707_;
  end
  always @* begin
    if (\initial ) begin end
    _0706_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_shared_ack <= _0706_;
  end
  always @* begin
    if (\initial ) begin end
    _0647_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_grant <= _0647_;
  end
  always @* begin
    if (\initial ) begin end
    _0708_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_slave_sel <= _0708_;
  end
  always @* begin
    if (\initial ) begin end
    _0709_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_slave_sel_r <= _0709_;
  end
  always @* begin
    if (\initial ) begin end
    _0644_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_error <= _0644_;
  end
  always @* begin
    if (\initial ) begin end
    _0641_ = 20'hf4240;
  end
  always @* begin
  end
  initial begin
      libresocsim_count <= _0641_;
  end
  always @* begin
    if (\initial ) begin end
    _0648_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_bank_bus_dat_r <= _0648_;
  end
  always @* begin
    if (\initial ) begin end
    _0124_ = 64'h0000000000000000;
  end
  always @* begin
      libresocsim_libresoc0 <= _0124_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0655_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_bank_bus_dat_r <= _0655_;
  end
  always @* begin
    if (\initial ) begin end
    _0681_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_uart_tx <= _0681_;
  end
  always @* begin
    if (\initial ) begin end
    _0141_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_uart_rx <= _0141_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0662_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface2_bank_bus_dat_r <= _0662_;
  end
  always @* begin
    if (\initial ) begin end
    _0663_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface3_bank_bus_dat_r <= _0663_;
  end
  always @* begin
    if (\initial ) begin end
    _0664_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface4_bank_bus_dat_r <= _0664_;
  end
  always @* begin
    if (\initial ) begin end
    _0138_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_spimaster_clk <= _0138_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0140_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_spimaster_mosi <= _0140_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0139_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_spimaster_cs_n <= _0139_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0665_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface5_bank_bus_dat_r <= _0665_;
  end
  always @* begin
    if (\initial ) begin end
    _0668_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_gpio_o <= _0668_;
  end
  always @* begin
    if (\initial ) begin end
    _0669_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_gpio_oe <= _0669_;
  end
  always @* begin
    if (\initial ) begin end
    _0666_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface6_bank_bus_dat_r <= _0666_;
  end
  always @* begin
    if (\initial ) begin end
    _0670_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_a <= _0670_;
  end
  always @* begin
    if (\initial ) begin end
    _0667_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface7_bank_bus_dat_r <= _0667_;
  end
  always @* begin
    if (\initial ) begin end
    _0677_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_dq_o <= _0677_;
  end
  always @* begin
    if (\initial ) begin end
    _0678_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_dq_oe <= _0678_;
  end
  always @* begin
    if (\initial ) begin end
    _0710_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_state <= _0710_;
  end
  always @* begin
    if (\initial ) begin end
    _0698_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_next_state <= _0698_;
  end
  always @* begin
    if (\initial ) begin end
    _0689_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= _0689_;
  end
  always @* begin
    if (\initial ) begin end
    _0690_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= _0690_;
  end
  always @* begin
    if (\initial ) begin end
    _0686_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_adr_libresocsim_next_value1 <= _0686_;
  end
  always @* begin
    if (\initial ) begin end
    _0687_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= _0687_;
  end
  always @* begin
    if (\initial ) begin end
    _0692_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_we_libresocsim_next_value2 <= _0692_;
  end
  always @* begin
    if (\initial ) begin end
    _0680_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_we_n <= _0680_;
  end
  always @* begin
    if (\initial ) begin end
    _0693_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= _0693_;
  end
  always @* begin
    if (\initial ) begin end
    _0730_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed0 <= _0730_;
  end
  always @* begin
    if (\initial ) begin end
    _0741_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed1 <= _0741_;
  end
  always @* begin
    if (\initial ) begin end
    _0752_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed2 <= _0752_;
  end
  always @* begin
    if (\initial ) begin end
    _0755_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed3 <= _0755_;
  end
  always @* begin
    if (\initial ) begin end
    _0756_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed4 <= _0756_;
  end
  always @* begin
    if (\initial ) begin end
    _0757_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed5 <= _0757_;
  end
  always @* begin
    if (\initial ) begin end
    _0990_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed0 <= _0990_;
  end
  always @* begin
    if (\initial ) begin end
    _0991_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed1 <= _0991_;
  end
  always @* begin
    if (\initial ) begin end
    _0992_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed2 <= _0992_;
  end
  always @* begin
    if (\initial ) begin end
    _0679_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_ras_n <= _0679_;
  end
  always @* begin
    if (\initial ) begin end
    _0758_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed6 <= _0758_;
  end
  always @* begin
    if (\initial ) begin end
    _0759_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed7 <= _0759_;
  end
  always @* begin
    if (\initial ) begin end
    _0760_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed8 <= _0760_;
  end
  always @* begin
    if (\initial ) begin end
    _0761_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed9 <= _0761_;
  end
  always @* begin
    if (\initial ) begin end
    _0731_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed10 <= _0731_;
  end
  always @* begin
    if (\initial ) begin end
    _0732_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed11 <= _0732_;
  end
  always @* begin
    if (\initial ) begin end
    _0993_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed3 <= _0993_;
  end
  always @* begin
    if (\initial ) begin end
    _0994_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed4 <= _0994_;
  end
  always @* begin
    if (\initial ) begin end
    _0995_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      t_array_muxed5 <= _0995_;
  end
  always @* begin
    if (\initial ) begin end
    _0733_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed12 <= _0733_;
  end
  always @* begin
    if (\initial ) begin end
    _0672_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_cas_n <= _0672_;
  end
  always @* begin
    if (\initial ) begin end
    _0734_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed13 <= _0734_;
  end
  always @* begin
    if (\initial ) begin end
    _0735_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed14 <= _0735_;
  end
  always @* begin
    if (\initial ) begin end
    _0736_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed15 <= _0736_;
  end
  always @* begin
    if (\initial ) begin end
    _0737_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed16 <= _0737_;
  end
  always @* begin
    if (\initial ) begin end
    _0738_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed17 <= _0738_;
  end
  always @* begin
    if (\initial ) begin end
    _0739_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed18 <= _0739_;
  end
  always @* begin
    if (\initial ) begin end
    _0740_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed19 <= _0740_;
  end
  always @* begin
    if (\initial ) begin end
    _0742_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed20 <= _0742_;
  end
  always @* begin
    if (\initial ) begin end
    _0743_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed21 <= _0743_;
  end
  always @* begin
    if (\initial ) begin end
    _0744_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed22 <= _0744_;
  end
  always @* begin
    if (\initial ) begin end
    _0675_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_cs_n <= _0675_;
  end
  always @* begin
    if (\initial ) begin end
    _0745_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed23 <= _0745_;
  end
  always @* begin
    if (\initial ) begin end
    _0746_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed24 <= _0746_;
  end
  always @* begin
    if (\initial ) begin end
    _0747_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed25 <= _0747_;
  end
  always @* begin
    if (\initial ) begin end
    _0748_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed26 <= _0748_;
  end
  always @* begin
    if (\initial ) begin end
    _0749_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed27 <= _0749_;
  end
  always @* begin
    if (\initial ) begin end
    _0750_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed28 <= _0750_;
  end
  always @* begin
    if (\initial ) begin end
    _0751_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed29 <= _0751_;
  end
  always @* begin
    if (\initial ) begin end
    _0753_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed30 <= _0753_;
  end
  always @* begin
    if (\initial ) begin end
    _0754_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      rhs_array_muxed31 <= _0754_;
  end
  always @* begin
    if (\initial ) begin end
    _0590_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed0 <= _0590_;
  end
  always @* begin
    if (\initial ) begin end
    _0673_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_cke <= _0673_;
  end
  always @* begin
    if (\initial ) begin end
    _0591_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      array_muxed1 <= _0591_;
  end
  always @* begin
    if (\initial ) begin end
    _0592_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed2 <= _0592_;
  end
  always @* begin
    if (\initial ) begin end
    _0593_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed3 <= _0593_;
  end
  always @* begin
    if (\initial ) begin end
    _0594_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed4 <= _0594_;
  end
  always @* begin
    if (\initial ) begin end
    _0595_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed5 <= _0595_;
  end
  always @* begin
    if (\initial ) begin end
    _0596_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      array_muxed6 <= _0596_;
  end
  always @* begin
    if (\initial ) begin end
    _0671_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_ba <= _0671_;
  end
  always @* begin
    if (\initial ) begin end
    _0676_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_dm <= _0676_;
  end
  always @* begin
    if (\initial ) begin end
    _0674_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_constraintmanager_sdram_clock <= _0674_;
  end
  always @* begin
    if (\initial ) begin end
    _0649_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_adr <= _0649_;
  end
  always @* begin
    if (\initial ) begin end
    _0651_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_dat_w <= _0651_;
  end
  always @* begin
    if (\initial ) begin end
    _0652_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_sel <= _0652_;
  end
  always @* begin
    if (\initial ) begin end
    _0728_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      regs0 <= _0728_;
  end
  always @* begin
    if (\initial ) begin end
    _0729_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      regs1 <= _0729_;
  end
  always @* begin
    if (\initial ) begin end
    _0650_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_cyc <= _0650_;
  end
  always @* begin
    if (\initial ) begin end
    _0653_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_stb <= _0653_;
  end
  always @* begin
    if (\initial ) begin end
    _0654_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface0_converted_interface_we <= _0654_;
  end
  always @* begin
    if (\initial ) begin end
    _0103_ = 3'h0;
  end
  always @* begin
      libresocsim_interface0_converted_interface_cti <= _0103_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0058_[0] = libresocsim_libresoc_constraintmanager_eint_0;
    _0058_[1] = libresocsim_libresoc_constraintmanager_eint_1;
    _0058_[2] = libresocsim_libresoc_constraintmanager_eint_2;
  end
  always @* begin
      eint_tmp <= _0058_;
  end
  always @* begin
    if (\initial ) begin end
    _0102_ = 2'h0;
  end
  always @* begin
      libresocsim_interface0_converted_interface_bte <= _0102_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0147_[12:2] = 11'h000;
    _0147_[13] = eint_tmp[0];
    _0147_[14] = eint_tmp[1];
    _0147_[15] = eint_tmp[2];
    _0147_[0] = libresocsim_irq;
    _0147_[1] = irq;
  end
  always @* begin
      libresocsim_libresoc_interrupt <= _0147_;
  end
  always @* begin
    if (\initial ) begin end
    _0635_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter0_skip <= _0635_;
  end
  always @* begin
    if (\initial ) begin end
    _0105_ = 32'd0;
    (* src = "ls180.v:1512.2-1519.9" *)
    casez (libresocsim_converter0_counter)
      /* src = "ls180.v:0.0-0.0" */
      1'h0:
          _0105_ = libresocsim_libresoc_ibus_dat_w[31:0];
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
          _0105_ = libresocsim_libresoc_ibus_dat_w[63:32];
      default:
          /* empty */;
    endcase
  end
  always @* begin
      libresocsim_interface0_converted_interface_dat_w <= _0105_;
  end
  always @* begin
    if (\initial ) begin end
    _0631_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter0_counter <= _0631_;
  end
  always @* begin
    if (\initial ) begin end
    _0106_ = 4'h0;
    _0104_ = 1'h0;
    _0145_ = 1'h0;
    _0107_ = 1'h0;
    _0084_ = 1'h0;
    _0108_ = 1'h0;
    _0085_ = 1'h0;
    _0087_ = 1'h0;
    _0101_ = 30'h00000000;
    _0491_ = subfragments_converter0_state;
    (* src = "ls180.v:1534.2-1567.9" *)
    casez (subfragments_converter0_state)
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
        begin
          _0101_ = { libresocsim_libresoc_ibus_adr, libresocsim_converter0_counter };
          (* src = "ls180.v:1537.4-1544.11" *)
          casez (libresocsim_converter0_counter)
            /* src = "ls180.v:0.0-0.0" */
            1'h0:
                _0106_ = libresocsim_libresoc_ibus_sel[3:0];
            /* src = "ls180.v:0.0-0.0" */
            1'h1:
                _0106_ = libresocsim_libresoc_ibus_sel[7:4];
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:1545.4-1558.7" *)
          casez (_1051_)
            /* src = "ls180.v:1545.8-1545.71" */
            1'h1:
              begin
                _0087_ = _1643_;
                _0108_ = libresocsim_libresoc_ibus_we;
                _0104_ = _1973_;
                _0107_ = _1974_;
                (* src = "ls180.v:1550.5-1557.8" *)
                casez (_2173_)
                  /* src = "ls180.v:1550.9-1550.87" */
                  1'h1:
                    begin
                      _0084_ = _1022_;
                      _0085_ = 1'h1;
                      (* src = "ls180.v:1553.6-1556.9" *)
                      casez (_1644_)
                        /* src = "ls180.v:1553.10-1553.50" */
                        1'h1:
                          begin
                            _0145_ = 1'h1;
                            _0491_ = 1'h0;
                          end
                        default:
                            /* empty */;
                      endcase
                    end
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0084_ = 1'h0;
          _0085_ = 1'h1;
          (* src = "ls180.v:1563.4-1565.7" *)
          casez (_1052_)
            /* src = "ls180.v:1563.8-1563.71" */
            1'h1:
                _0491_ = 1'h1;
            default:
                /* empty */;
          endcase
        end
    endcase
  end
  always @* begin
      libresocsim_libresoc_ibus_ack <= _0145_;
      libresocsim_interface0_converted_interface_adr <= _0101_;
      libresocsim_interface0_converted_interface_sel <= _0106_;
      libresocsim_interface0_converted_interface_cyc <= _0104_;
      libresocsim_interface0_converted_interface_stb <= _0107_;
      libresocsim_interface0_converted_interface_we <= _0108_;
      libresocsim_converter0_skip <= _0087_;
      subfragments_converter0_next_state <= _0491_;
      libresocsim_converter0_counter_subfragments_converter0_next_value <= _0084_;
      libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= _0085_;
  end
  always @* begin
    if (\initial ) begin end
    _0634_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter0_dat_r <= _0634_;
  end
  always @* begin
    if (\initial ) begin end
    _0656_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_adr <= _0656_;
  end
  always @* begin
    if (\initial ) begin end
    _0658_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_dat_w <= _0658_;
  end
  always @* begin
    if (\initial ) begin end
    _0114_ = 32'd0;
    (* src = "ls180.v:1572.2-1579.9" *)
    casez (libresocsim_converter1_counter)
      /* src = "ls180.v:0.0-0.0" */
      1'h0:
          _0114_ = libresocsim_libresoc_dbus_dat_w[31:0];
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
          _0114_ = libresocsim_libresoc_dbus_dat_w[63:32];
      default:
          /* empty */;
    endcase
  end
  always @* begin
      libresocsim_interface1_converted_interface_dat_w <= _0114_;
  end
  always @* begin
    if (\initial ) begin end
    _0659_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_sel <= _0659_;
  end
  always @* begin
    if (\initial ) begin end
    _0117_ = 1'h0;
    _0089_ = 1'h0;
    _0090_ = 1'h0;
    _0092_ = 1'h0;
    _0143_ = 1'h0;
    _0110_ = 30'h00000000;
    _0115_ = 4'h0;
    _0113_ = 1'h0;
    _0116_ = 1'h0;
    _0493_ = subfragments_converter1_state;
    (* src = "ls180.v:1594.2-1627.9" *)
    casez (subfragments_converter1_state)
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
        begin
          _0110_ = { libresocsim_libresoc_dbus_adr, libresocsim_converter1_counter };
          (* src = "ls180.v:1597.4-1604.11" *)
          casez (libresocsim_converter1_counter)
            /* src = "ls180.v:0.0-0.0" */
            1'h0:
                _0115_ = libresocsim_libresoc_dbus_sel[3:0];
            /* src = "ls180.v:0.0-0.0" */
            1'h1:
                _0115_ = libresocsim_libresoc_dbus_sel[7:4];
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:1605.4-1618.7" *)
          casez (_1053_)
            /* src = "ls180.v:1605.8-1605.71" */
            1'h1:
              begin
                _0092_ = _1645_;
                _0117_ = libresocsim_libresoc_dbus_we;
                _0113_ = _1976_;
                _0116_ = _1977_;
                (* src = "ls180.v:1610.5-1617.8" *)
                casez (_2174_)
                  /* src = "ls180.v:1610.9-1610.87" */
                  1'h1:
                    begin
                      _0089_ = _1023_;
                      _0090_ = 1'h1;
                      (* src = "ls180.v:1613.6-1616.9" *)
                      casez (_1646_)
                        /* src = "ls180.v:1613.10-1613.50" */
                        1'h1:
                          begin
                            _0143_ = 1'h1;
                            _0493_ = 1'h0;
                          end
                        default:
                            /* empty */;
                      endcase
                    end
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0089_ = 1'h0;
          _0090_ = 1'h1;
          (* src = "ls180.v:1623.4-1625.7" *)
          casez (_1054_)
            /* src = "ls180.v:1623.8-1623.71" */
            1'h1:
                _0493_ = 1'h1;
            default:
                /* empty */;
          endcase
        end
    endcase
  end
  always @* begin
      libresocsim_libresoc_dbus_ack <= _0143_;
      libresocsim_interface1_converted_interface_adr <= _0110_;
      libresocsim_interface1_converted_interface_sel <= _0115_;
      libresocsim_interface1_converted_interface_cyc <= _0113_;
      libresocsim_interface1_converted_interface_stb <= _0116_;
      libresocsim_interface1_converted_interface_we <= _0117_;
      libresocsim_converter1_skip <= _0092_;
      subfragments_converter1_next_state <= _0493_;
      libresocsim_converter1_counter_subfragments_converter1_next_value <= _0089_;
      libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= _0090_;
  end
  always @* begin
    if (\initial ) begin end
    _0657_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_cyc <= _0657_;
  end
  always @* begin
    if (\initial ) begin end
    _0660_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_stb <= _0660_;
  end
  always @* begin
    if (\initial ) begin end
    _0661_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_interface1_converted_interface_we <= _0661_;
  end
  always @* begin
    if (\initial ) begin end
    _0112_ = 3'h0;
  end
  always @* begin
      libresocsim_interface1_converted_interface_cti <= _0112_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0182_[0] = _1057_;
    _0182_[1] = _1060_;
    _0182_[2] = _1063_;
    _0182_[3] = _1066_;
  end
  always @* begin
      libresocsim_we <= _0182_;
  end
  always @* begin
    if (\initial ) begin end
    _0111_ = 2'h0;
  end
  always @* begin
      libresocsim_interface1_converted_interface_bte <= _0111_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0183_ = 1'h0;
    (* src = "ls180.v:1645.2-1647.5" *)
    casez (_1067_)
      /* src = "ls180.v:1645.6-1645.80" */
      1'h1:
          _0183_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      libresocsim_zero_clear <= _0183_;
  end
  always @* begin
    if (\initial ) begin end
    _0204_[0] = _1071_;
    _0204_[1] = _1074_;
    _0204_[2] = _1077_;
    _0204_[3] = _1080_;
  end
  always @* begin
      ram_we <= _0204_;
  end
  always @* begin
    if (\initial ) begin end
    _0640_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter1_skip <= _0640_;
  end
  always @* begin
    if (\initial ) begin end
    _0636_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter1_counter <= _0636_;
  end
  always @* begin
    if (\initial ) begin end
    _0639_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter1_dat_r <= _0639_;
  end
  always @* begin
    if (\initial ) begin end
    _0449_ = 1'h1;
    _0452_ = 1'h1;
    _0446_ = 1'h0;
    _0448_ = 1'h0;
    _0451_ = 1'h0;
    _0442_ = 1'h1;
    _0439_ = 16'h0000;
    _0453_ = 16'h0000;
    _0440_ = 1'h0;
    _0454_ = 1'h0;
    _0455_ = 2'h0;
    _0450_ = 1'h0;
    _0465_ = 16'h0000;
    _0466_ = 1'h0;
    _0443_ = 13'h0000;
    _0444_ = 2'h0;
    _0445_ = 1'h1;
    _0447_ = 1'h1;
    (* src = "ls180.v:1716.2-1750.5" *)
    casez (sdram_sel)
      /* src = "ls180.v:1716.6-1716.15" */
      1'h1:
        begin
          _0443_ = sdram_slave_p0_address;
          _0444_ = sdram_slave_p0_bank;
          _0445_ = sdram_slave_p0_cas_n;
          _0447_ = sdram_slave_p0_cs_n;
          _0449_ = sdram_slave_p0_ras_n;
          _0452_ = sdram_slave_p0_we_n;
          _0446_ = sdram_slave_p0_cke;
          _0448_ = sdram_slave_p0_odt;
          _0451_ = sdram_slave_p0_reset_n;
          _0442_ = sdram_slave_p0_act_n;
          _0453_ = sdram_slave_p0_wrdata;
          _0454_ = sdram_slave_p0_wrdata_en;
          _0455_ = sdram_slave_p0_wrdata_mask;
          _0450_ = sdram_slave_p0_rddata_en;
          _0465_ = sdram_master_p0_rddata;
          _0466_ = sdram_master_p0_rddata_valid;
        end
      /* src = "ls180.v:1733.6-1733.10" */
      default:
        begin
          _0443_ = sdram_inti_p0_address;
          _0444_ = sdram_inti_p0_bank;
          _0445_ = sdram_inti_p0_cas_n;
          _0447_ = sdram_inti_p0_cs_n;
          _0449_ = sdram_inti_p0_ras_n;
          _0452_ = sdram_inti_p0_we_n;
          _0446_ = sdram_inti_p0_cke;
          _0448_ = sdram_inti_p0_odt;
          _0451_ = sdram_inti_p0_reset_n;
          _0442_ = sdram_inti_p0_act_n;
          _0453_ = sdram_inti_p0_wrdata;
          _0454_ = sdram_inti_p0_wrdata_en;
          _0455_ = sdram_inti_p0_wrdata_mask;
          _0450_ = sdram_inti_p0_rddata_en;
          _0439_ = sdram_master_p0_rddata;
          _0440_ = sdram_master_p0_rddata_valid;
        end
    endcase
  end
  always @* begin
      sdram_inti_p0_rddata <= _0439_;
      sdram_inti_p0_rddata_valid <= _0440_;
      sdram_slave_p0_rddata <= _0465_;
      sdram_slave_p0_rddata_valid <= _0466_;
      sdram_master_p0_address <= _0443_;
      sdram_master_p0_bank <= _0444_;
      sdram_master_p0_cas_n <= _0445_;
      sdram_master_p0_cs_n <= _0447_;
      sdram_master_p0_ras_n <= _0449_;
      sdram_master_p0_we_n <= _0452_;
      sdram_master_p0_cke <= _0446_;
      sdram_master_p0_odt <= _0448_;
      sdram_master_p0_reset_n <= _0451_;
      sdram_master_p0_act_n <= _0442_;
      sdram_master_p0_wrdata <= _0453_;
      sdram_master_p0_wrdata_en <= _0454_;
      sdram_master_p0_wrdata_mask <= _0455_;
      sdram_master_p0_rddata_en <= _0450_;
  end
  always @* begin
    if (\initial ) begin end
    _0441_ = 1'h1;
    _0436_ = 1'h1;
    _0437_ = 1'h1;
    _0438_ = 1'h1;
    (* src = "ls180.v:1760.2-1770.5" *)
    casez (sdram_command_issue_re)
      /* src = "ls180.v:1760.6-1760.28" */
      1'h1:
        begin
          _0437_ = _1978_;
          _0441_ = _1979_;
          _0436_ = _1980_;
          _0438_ = _1981_;
        end
      /* src = "ls180.v:1765.6-1765.10" */
      default:
        begin
          _0437_ = 1'h1;
          _0441_ = 1'h1;
          _0436_ = 1'h1;
          _0438_ = 1'h1;
        end
    endcase
  end
  always @* begin
      sdram_inti_p0_cas_n <= _0436_;
      sdram_inti_p0_cs_n <= _0437_;
      sdram_inti_p0_ras_n <= _0438_;
      sdram_inti_p0_we_n <= _0441_;
  end
  always @* begin
    if (\initial ) begin end
    _0699_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_ram_bus_ack <= _0699_;
  end
  always @* begin
    if (\initial ) begin end
    _0166_ = 1'h0;
  end
  always @* begin
      libresocsim_ram_bus_err <= _0166_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0464_ = 1'h0;
    _0418_ = 1'h0;
    _0409_ = 1'h0;
    _0507_ = subfragments_refresher_state;
    (* src = "ls180.v:1820.2-1843.9" *)
    casez (subfragments_refresher_state)
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
        begin
          _0418_ = 1'h1;
          (* src = "ls180.v:1823.4-1826.7" *)
          casez (sdram_cmd_ready)
            /* src = "ls180.v:1823.8-1823.23" */
            1'h1:
              begin
                _0464_ = 1'h1;
                _0507_ = 2'h2;
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
        begin
          _0418_ = 1'h1;
          (* src = "ls180.v:1830.4-1834.7" *)
          casez (sdram_sequencer_done0)
            /* src = "ls180.v:1830.8-1830.29" */
            1'h1:
              begin
                _0418_ = 1'h0;
                _0409_ = 1'h1;
                _0507_ = 2'h0;
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
          (* src = "ls180.v:1837.4-1841.7" *)
          casez (1'h1)
            /* src = "ls180.v:1837.8-1837.12" */
            1'h1:
                (* src = "ls180.v:1838.5-1840.8" *)
                casez (sdram_wants_refresh)
                  /* src = "ls180.v:1838.9-1838.28" */
                  1'h1:
                      _0507_ = 2'h1;
                  default:
                      /* empty */;
                endcase
            default:
                /* empty */;
          endcase
    endcase
  end
  always @* begin
      sdram_cmd_valid <= _0418_;
      sdram_cmd_last <= _0409_;
      sdram_sequencer_start0 <= _0464_;
      subfragments_refresher_next_state <= _0507_;
  end
  always @* begin
    if (\initial ) begin end
    _0715_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_we <= _0715_;
  end
  always @* begin
    if (\initial ) begin end
    _0697_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_load_storage <= _0697_;
  end
  always @* begin
    if (\initial ) begin end
    _0267_ = 13'h0000;
    (* src = "ls180.v:1861.2-1865.5" *)
    casez (sdram_bankmachine0_row_col_n_addr_sel)
      /* src = "ls180.v:1861.6-1861.43" */
      1'h1:
          _0267_ = sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
      /* src = "ls180.v:1863.6-1863.10" */
      default:
          _0267_ = _2178_;
    endcase
  end
  always @* begin
      sdram_bankmachine0_cmd_payload_a <= _0267_;
  end
  always @* begin
    if (\initial ) begin end
    _0696_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_load_re <= _0696_;
  end
  always @* begin
    if (\initial ) begin end
    _0701_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_reload_storage <= _0701_;
  end
  always @* begin
    if (\initial ) begin end
    _0254_ = 1'h0;
    (* src = "ls180.v:1872.2-1876.5" *)
    casez (_1090_)
      /* src = "ls180.v:1872.6-1872.105" */
      1'h1:
          (* src = "ls180.v:1873.3-1875.6" *)
          casez (_1952_)
            /* src = "ls180.v:1873.7-1873.133" */
            1'h1:
                _0254_ = _1650_;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine0_auto_precharge <= _0254_;
  end
  always @* begin
    if (\initial ) begin end
    _0700_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_reload_re <= _0700_;
  end
  always @* begin
    if (\initial ) begin end
    _0643_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_en_storage <= _0643_;
  end
  always @* begin
    if (\initial ) begin end
    _0261_ = 3'h0;
    (* src = "ls180.v:1894.2-1898.5" *)
    casez (sdram_bankmachine0_cmd_buffer_lookahead_replace)
      /* src = "ls180.v:1894.6-1894.53" */
      1'h1:
          _0261_ = _2359_;
      /* src = "ls180.v:1896.6-1896.10" */
      default:
          _0261_ = sdram_bankmachine0_cmd_buffer_lookahead_produce;
    endcase
  end
  always @* begin
      sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= _0261_;
  end
  always @* begin
    if (\initial ) begin end
    _0642_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_en_re <= _0642_;
  end
  always @* begin
    if (\initial ) begin end
    _0268_ = 1'h0;
    _0272_ = 1'h0;
    _0273_ = 1'h0;
    _0281_ = 1'h0;
    _0269_ = 1'h0;
    _0270_ = 1'h0;
    _0271_ = 1'h0;
    _0278_ = 1'h0;
    _0277_ = 1'h0;
    _0276_ = 1'h0;
    _0275_ = 1'h0;
    _0282_ = 1'h0;
    _0280_ = 1'h0;
    _0483_ = subfragments_bankmachine0_state;
    (* src = "ls180.v:1924.2-2000.9" *)
    casez (subfragments_bankmachine0_state)
      /* src = "ls180.v:0.0-0.0" */
      3'h1:
        begin
          _0280_ = 1'h1;
          (* src = "ls180.v:1926.4-1934.7" *)
          casez (_1093_)
            /* src = "ls180.v:1926.8-1926.77" */
            1'h1:
              begin
                _0275_ = 1'h1;
                _0272_ = 1'h1;
                _0273_ = 1'h1;
                _0269_ = 1'h1;
                (* src = "ls180.v:1928.5-1930.8" *)
                casez (sdram_bankmachine0_cmd_ready)
                  /* src = "ls180.v:1928.9-1928.37" */
                  1'h1:
                      _0483_ = 3'h5;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h2:
        begin
          _0280_ = 1'h1;
          (* src = "ls180.v:1938.4-1940.7" *)
          casez (_1094_)
            /* src = "ls180.v:1938.8-1938.77" */
            1'h1:
                _0483_ = 3'h5;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h3:
          (* src = "ls180.v:1944.4-1953.7" *)
          casez (sdram_bankmachine0_trccon_ready)
            /* src = "ls180.v:1944.8-1944.39" */
            1'h1:
              begin
                _0281_ = 1'h1;
                _0282_ = 1'h1;
                _0275_ = 1'h1;
                _0269_ = 1'h1;
                _0272_ = 1'h1;
                (* src = "ls180.v:1949.5-1951.8" *)
                casez (sdram_bankmachine0_cmd_ready)
                  /* src = "ls180.v:1949.9-1949.37" */
                  1'h1:
                      _0483_ = 3'h6;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      3'h4:
        begin
          _0280_ = 1'h1;
          _0269_ = 1'h1;
          (* src = "ls180.v:1956.4-1958.7" *)
          casez (sdram_bankmachine0_twtpcon_ready)
            /* src = "ls180.v:1956.8-1956.40" */
            1'h1:
                _0276_ = 1'h1;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:1961.4-1963.7" *)
          casez (_1984_)
            /* src = "ls180.v:1961.8-1961.41" */
            1'h1:
                _0483_ = 3'h0;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h5:
          _0483_ = 3'h3;
      /* src = "ls180.v:0.0-0.0" */
      3'h6:
          _0483_ = 3'h0;
      /* src = "ls180.v:0.0-0.0" */
      default:
          (* src = "ls180.v:1972.4-1998.7" *)
          casez (sdram_bankmachine0_refresh_req)
            /* src = "ls180.v:1972.8-1972.38" */
            1'h1:
                _0483_ = 3'h4;
            /* src = "ls180.v:1974.8-1974.12" */
            default:
                (* src = "ls180.v:1975.5-1997.8" *)
                casez (sdram_bankmachine0_cmd_buffer_source_valid)
                  /* src = "ls180.v:1975.9-1975.51" */
                  1'h1:
                      (* src = "ls180.v:1976.6-1996.9" *)
                      casez (sdram_bankmachine0_row_opened)
                        /* src = "ls180.v:1976.10-1976.39" */
                        1'h1:
                            (* src = "ls180.v:1977.7-1993.10" *)
                            casez (sdram_bankmachine0_row_hit)
                              /* src = "ls180.v:1977.11-1977.37" */
                              1'h1:
                                begin
                                  _0275_ = 1'h1;
                                  _0268_ = 1'h1;
                                  (* src = "ls180.v:1979.8-1986.11" *)
                                  casez (sdram_bankmachine0_cmd_buffer_source_payload_we)
                                    /* src = "ls180.v:1979.12-1979.59" */
                                    1'h1:
                                      begin
                                        _0278_ = sdram_bankmachine0_cmd_ready;
                                        _0271_ = 1'h1;
                                        _0273_ = 1'h1;
                                      end
                                    /* src = "ls180.v:1983.12-1983.16" */
                                    default:
                                      begin
                                        _0277_ = sdram_bankmachine0_cmd_ready;
                                        _0270_ = 1'h1;
                                      end
                                  endcase
                                  (* src = "ls180.v:1988.8-1990.11" *)
                                  casez (_1095_)
                                    /* src = "ls180.v:1988.12-1988.78" */
                                    1'h1:
                                        _0483_ = 3'h2;
                                    default:
                                        /* empty */;
                                  endcase
                                end
                              /* src = "ls180.v:1991.11-1991.15" */
                              default:
                                  _0483_ = 3'h1;
                            endcase
                        /* src = "ls180.v:1994.10-1994.14" */
                        default:
                            _0483_ = 3'h3;
                      endcase
                  default:
                      /* empty */;
                endcase
          endcase
    endcase
  end
  always @* begin
      sdram_bankmachine0_req_wdata_ready <= _0278_;
      sdram_bankmachine0_req_rdata_valid <= _0277_;
      sdram_bankmachine0_refresh_gnt <= _0276_;
      sdram_bankmachine0_cmd_valid <= _0275_;
      sdram_bankmachine0_cmd_payload_cas <= _0268_;
      sdram_bankmachine0_cmd_payload_ras <= _0272_;
      sdram_bankmachine0_cmd_payload_we <= _0273_;
      sdram_bankmachine0_cmd_payload_is_cmd <= _0269_;
      sdram_bankmachine0_cmd_payload_is_read <= _0270_;
      sdram_bankmachine0_cmd_payload_is_write <= _0271_;
      sdram_bankmachine0_row_open <= _0282_;
      sdram_bankmachine0_row_close <= _0280_;
      sdram_bankmachine0_row_col_n_addr_sel <= _0281_;
      subfragments_bankmachine0_next_state <= _0483_;
  end
  always @* begin
    if (\initial ) begin end
    _0712_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_update_value_storage <= _0712_;
  end
  always @* begin
    if (\initial ) begin end
    _0711_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_update_value_re <= _0711_;
  end
  always @* begin
    if (\initial ) begin end
    _0714_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_value_status <= _0714_;
  end
  always @* begin
    if (\initial ) begin end
    _0718_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_zero_pending <= _0718_;
  end
  always @* begin
    if (\initial ) begin end
    _0716_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_zero_clear <= _0716_;
  end
  always @* begin
    if (\initial ) begin end
    _0717_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_zero_old_trigger <= _0717_;
  end
  always @* begin
    if (\initial ) begin end
    _0301_ = 13'h0000;
    (* src = "ls180.v:2018.2-2022.5" *)
    casez (sdram_bankmachine1_row_col_n_addr_sel)
      /* src = "ls180.v:2018.6-2018.43" */
      1'h1:
          _0301_ = sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
      /* src = "ls180.v:2020.6-2020.10" */
      default:
          _0301_ = _2183_;
    endcase
  end
  always @* begin
      sdram_bankmachine1_cmd_payload_a <= _0301_;
  end
  always @* begin
    if (\initial ) begin end
    _0288_ = 1'h0;
    (* src = "ls180.v:2029.2-2033.5" *)
    casez (_1102_)
      /* src = "ls180.v:2029.6-2029.105" */
      1'h1:
          (* src = "ls180.v:2030.3-2032.6" *)
          casez (_1955_)
            /* src = "ls180.v:2030.7-2030.133" */
            1'h1:
                _0288_ = _1652_;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine1_auto_precharge <= _0288_;
  end
  always @* begin
    if (\initial ) begin end
    _0295_ = 3'h0;
    (* src = "ls180.v:2051.2-2055.5" *)
    casez (sdram_bankmachine1_cmd_buffer_lookahead_replace)
      /* src = "ls180.v:2051.6-2051.53" */
      1'h1:
          _0295_ = _2360_;
      /* src = "ls180.v:2053.6-2053.10" */
      default:
          _0295_ = sdram_bankmachine1_cmd_buffer_lookahead_produce;
    endcase
  end
  always @* begin
      sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= _0295_;
  end
  always @* begin
    if (\initial ) begin end
    _0316_ = 1'h0;
    _0314_ = 1'h0;
    _0302_ = 1'h0;
    _0306_ = 1'h0;
    _0307_ = 1'h0;
    _0315_ = 1'h0;
    _0303_ = 1'h0;
    _0304_ = 1'h0;
    _0305_ = 1'h0;
    _0312_ = 1'h0;
    _0311_ = 1'h0;
    _0310_ = 1'h0;
    _0309_ = 1'h0;
    _0485_ = subfragments_bankmachine1_state;
    (* src = "ls180.v:2081.2-2157.9" *)
    casez (subfragments_bankmachine1_state)
      /* src = "ls180.v:0.0-0.0" */
      3'h1:
        begin
          _0314_ = 1'h1;
          (* src = "ls180.v:2083.4-2091.7" *)
          casez (_1105_)
            /* src = "ls180.v:2083.8-2083.77" */
            1'h1:
              begin
                _0309_ = 1'h1;
                _0306_ = 1'h1;
                _0307_ = 1'h1;
                _0303_ = 1'h1;
                (* src = "ls180.v:2085.5-2087.8" *)
                casez (sdram_bankmachine1_cmd_ready)
                  /* src = "ls180.v:2085.9-2085.37" */
                  1'h1:
                      _0485_ = 3'h5;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h2:
        begin
          _0314_ = 1'h1;
          (* src = "ls180.v:2095.4-2097.7" *)
          casez (_1106_)
            /* src = "ls180.v:2095.8-2095.77" */
            1'h1:
                _0485_ = 3'h5;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h3:
          (* src = "ls180.v:2101.4-2110.7" *)
          casez (sdram_bankmachine1_trccon_ready)
            /* src = "ls180.v:2101.8-2101.39" */
            1'h1:
              begin
                _0315_ = 1'h1;
                _0316_ = 1'h1;
                _0309_ = 1'h1;
                _0303_ = 1'h1;
                _0306_ = 1'h1;
                (* src = "ls180.v:2106.5-2108.8" *)
                casez (sdram_bankmachine1_cmd_ready)
                  /* src = "ls180.v:2106.9-2106.37" */
                  1'h1:
                      _0485_ = 3'h6;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      3'h4:
        begin
          _0314_ = 1'h1;
          _0303_ = 1'h1;
          (* src = "ls180.v:2113.4-2115.7" *)
          casez (sdram_bankmachine1_twtpcon_ready)
            /* src = "ls180.v:2113.8-2113.40" */
            1'h1:
                _0310_ = 1'h1;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2118.4-2120.7" *)
          casez (_1986_)
            /* src = "ls180.v:2118.8-2118.41" */
            1'h1:
                _0485_ = 3'h0;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h5:
          _0485_ = 3'h3;
      /* src = "ls180.v:0.0-0.0" */
      3'h6:
          _0485_ = 3'h0;
      /* src = "ls180.v:0.0-0.0" */
      default:
          (* src = "ls180.v:2129.4-2155.7" *)
          casez (sdram_bankmachine1_refresh_req)
            /* src = "ls180.v:2129.8-2129.38" */
            1'h1:
                _0485_ = 3'h4;
            /* src = "ls180.v:2131.8-2131.12" */
            default:
                (* src = "ls180.v:2132.5-2154.8" *)
                casez (sdram_bankmachine1_cmd_buffer_source_valid)
                  /* src = "ls180.v:2132.9-2132.51" */
                  1'h1:
                      (* src = "ls180.v:2133.6-2153.9" *)
                      casez (sdram_bankmachine1_row_opened)
                        /* src = "ls180.v:2133.10-2133.39" */
                        1'h1:
                            (* src = "ls180.v:2134.7-2150.10" *)
                            casez (sdram_bankmachine1_row_hit)
                              /* src = "ls180.v:2134.11-2134.37" */
                              1'h1:
                                begin
                                  _0309_ = 1'h1;
                                  _0302_ = 1'h1;
                                  (* src = "ls180.v:2136.8-2143.11" *)
                                  casez (sdram_bankmachine1_cmd_buffer_source_payload_we)
                                    /* src = "ls180.v:2136.12-2136.59" */
                                    1'h1:
                                      begin
                                        _0312_ = sdram_bankmachine1_cmd_ready;
                                        _0305_ = 1'h1;
                                        _0307_ = 1'h1;
                                      end
                                    /* src = "ls180.v:2140.12-2140.16" */
                                    default:
                                      begin
                                        _0311_ = sdram_bankmachine1_cmd_ready;
                                        _0304_ = 1'h1;
                                      end
                                  endcase
                                  (* src = "ls180.v:2145.8-2147.11" *)
                                  casez (_1107_)
                                    /* src = "ls180.v:2145.12-2145.78" */
                                    1'h1:
                                        _0485_ = 3'h2;
                                    default:
                                        /* empty */;
                                  endcase
                                end
                              /* src = "ls180.v:2148.11-2148.15" */
                              default:
                                  _0485_ = 3'h1;
                            endcase
                        /* src = "ls180.v:2151.10-2151.14" */
                        default:
                            _0485_ = 3'h3;
                      endcase
                  default:
                      /* empty */;
                endcase
          endcase
    endcase
  end
  always @* begin
      sdram_bankmachine1_req_wdata_ready <= _0312_;
      sdram_bankmachine1_req_rdata_valid <= _0311_;
      sdram_bankmachine1_refresh_gnt <= _0310_;
      sdram_bankmachine1_cmd_valid <= _0309_;
      sdram_bankmachine1_cmd_payload_cas <= _0302_;
      sdram_bankmachine1_cmd_payload_ras <= _0306_;
      sdram_bankmachine1_cmd_payload_we <= _0307_;
      sdram_bankmachine1_cmd_payload_is_cmd <= _0303_;
      sdram_bankmachine1_cmd_payload_is_read <= _0304_;
      sdram_bankmachine1_cmd_payload_is_write <= _0305_;
      sdram_bankmachine1_row_open <= _0316_;
      sdram_bankmachine1_row_close <= _0314_;
      sdram_bankmachine1_row_col_n_addr_sel <= _0315_;
      subfragments_bankmachine1_next_state <= _0485_;
  end
  always @* begin
    if (\initial ) begin end
    _0646_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_eventmanager_storage <= _0646_;
  end
  always @* begin
    if (\initial ) begin end
    _0645_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_eventmanager_re <= _0645_;
  end
  always @* begin
    if (\initial ) begin end
    _0713_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_value <= _0713_;
  end
  always @* begin
    if (\initial ) begin end
    _0335_ = 13'h0000;
    (* src = "ls180.v:2175.2-2179.5" *)
    casez (sdram_bankmachine2_row_col_n_addr_sel)
      /* src = "ls180.v:2175.6-2175.43" */
      1'h1:
          _0335_ = sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
      /* src = "ls180.v:2177.6-2177.10" */
      default:
          _0335_ = _2188_;
    endcase
  end
  always @* begin
      sdram_bankmachine2_cmd_payload_a <= _0335_;
  end
  always @* begin
    if (\initial ) begin end
    _0725_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ram_bus_ram_bus_ack <= _0725_;
  end
  always @* begin
    if (\initial ) begin end
    _0322_ = 1'h0;
    (* src = "ls180.v:2186.2-2190.5" *)
    casez (_1114_)
      /* src = "ls180.v:2186.6-2186.105" */
      1'h1:
          (* src = "ls180.v:2187.3-2189.6" *)
          casez (_1958_)
            /* src = "ls180.v:2187.7-2187.133" */
            1'h1:
                _0322_ = _1654_;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine2_auto_precharge <= _0322_;
  end
  always @* begin
    if (\initial ) begin end
    _0329_ = 3'h0;
    (* src = "ls180.v:2208.2-2212.5" *)
    casez (sdram_bankmachine2_cmd_buffer_lookahead_replace)
      /* src = "ls180.v:2208.6-2208.53" */
      1'h1:
          _0329_ = _2361_;
      /* src = "ls180.v:2210.6-2210.10" */
      default:
          _0329_ = sdram_bankmachine2_cmd_buffer_lookahead_produce;
    endcase
  end
  always @* begin
      sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= _0329_;
  end
  always @* begin
    if (\initial ) begin end
    _0203_ = 1'h0;
  end
  always @* begin
      ram_bus_ram_bus_err <= _0203_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0344_ = 1'h0;
    _0343_ = 1'h0;
    _0350_ = 1'h0;
    _0348_ = 1'h0;
    _0336_ = 1'h0;
    _0340_ = 1'h0;
    _0341_ = 1'h0;
    _0349_ = 1'h0;
    _0337_ = 1'h0;
    _0338_ = 1'h0;
    _0339_ = 1'h0;
    _0346_ = 1'h0;
    _0345_ = 1'h0;
    _0487_ = subfragments_bankmachine2_state;
    (* src = "ls180.v:2238.2-2314.9" *)
    casez (subfragments_bankmachine2_state)
      /* src = "ls180.v:0.0-0.0" */
      3'h1:
        begin
          _0348_ = 1'h1;
          (* src = "ls180.v:2240.4-2248.7" *)
          casez (_1117_)
            /* src = "ls180.v:2240.8-2240.77" */
            1'h1:
              begin
                _0343_ = 1'h1;
                _0340_ = 1'h1;
                _0341_ = 1'h1;
                _0337_ = 1'h1;
                (* src = "ls180.v:2242.5-2244.8" *)
                casez (sdram_bankmachine2_cmd_ready)
                  /* src = "ls180.v:2242.9-2242.37" */
                  1'h1:
                      _0487_ = 3'h5;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h2:
        begin
          _0348_ = 1'h1;
          (* src = "ls180.v:2252.4-2254.7" *)
          casez (_1118_)
            /* src = "ls180.v:2252.8-2252.77" */
            1'h1:
                _0487_ = 3'h5;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h3:
          (* src = "ls180.v:2258.4-2267.7" *)
          casez (sdram_bankmachine2_trccon_ready)
            /* src = "ls180.v:2258.8-2258.39" */
            1'h1:
              begin
                _0349_ = 1'h1;
                _0350_ = 1'h1;
                _0343_ = 1'h1;
                _0337_ = 1'h1;
                _0340_ = 1'h1;
                (* src = "ls180.v:2263.5-2265.8" *)
                casez (sdram_bankmachine2_cmd_ready)
                  /* src = "ls180.v:2263.9-2263.37" */
                  1'h1:
                      _0487_ = 3'h6;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      3'h4:
        begin
          _0348_ = 1'h1;
          _0337_ = 1'h1;
          (* src = "ls180.v:2270.4-2272.7" *)
          casez (sdram_bankmachine2_twtpcon_ready)
            /* src = "ls180.v:2270.8-2270.40" */
            1'h1:
                _0344_ = 1'h1;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2275.4-2277.7" *)
          casez (_1988_)
            /* src = "ls180.v:2275.8-2275.41" */
            1'h1:
                _0487_ = 3'h0;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h5:
          _0487_ = 3'h3;
      /* src = "ls180.v:0.0-0.0" */
      3'h6:
          _0487_ = 3'h0;
      /* src = "ls180.v:0.0-0.0" */
      default:
          (* src = "ls180.v:2286.4-2312.7" *)
          casez (sdram_bankmachine2_refresh_req)
            /* src = "ls180.v:2286.8-2286.38" */
            1'h1:
                _0487_ = 3'h4;
            /* src = "ls180.v:2288.8-2288.12" */
            default:
                (* src = "ls180.v:2289.5-2311.8" *)
                casez (sdram_bankmachine2_cmd_buffer_source_valid)
                  /* src = "ls180.v:2289.9-2289.51" */
                  1'h1:
                      (* src = "ls180.v:2290.6-2310.9" *)
                      casez (sdram_bankmachine2_row_opened)
                        /* src = "ls180.v:2290.10-2290.39" */
                        1'h1:
                            (* src = "ls180.v:2291.7-2307.10" *)
                            casez (sdram_bankmachine2_row_hit)
                              /* src = "ls180.v:2291.11-2291.37" */
                              1'h1:
                                begin
                                  _0343_ = 1'h1;
                                  _0336_ = 1'h1;
                                  (* src = "ls180.v:2293.8-2300.11" *)
                                  casez (sdram_bankmachine2_cmd_buffer_source_payload_we)
                                    /* src = "ls180.v:2293.12-2293.59" */
                                    1'h1:
                                      begin
                                        _0346_ = sdram_bankmachine2_cmd_ready;
                                        _0339_ = 1'h1;
                                        _0341_ = 1'h1;
                                      end
                                    /* src = "ls180.v:2297.12-2297.16" */
                                    default:
                                      begin
                                        _0345_ = sdram_bankmachine2_cmd_ready;
                                        _0338_ = 1'h1;
                                      end
                                  endcase
                                  (* src = "ls180.v:2302.8-2304.11" *)
                                  casez (_1119_)
                                    /* src = "ls180.v:2302.12-2302.78" */
                                    1'h1:
                                        _0487_ = 3'h2;
                                    default:
                                        /* empty */;
                                  endcase
                                end
                              /* src = "ls180.v:2305.11-2305.15" */
                              default:
                                  _0487_ = 3'h1;
                            endcase
                        /* src = "ls180.v:2308.10-2308.14" */
                        default:
                            _0487_ = 3'h3;
                      endcase
                  default:
                      /* empty */;
                endcase
          endcase
    endcase
  end
  always @* begin
      sdram_bankmachine2_req_wdata_ready <= _0346_;
      sdram_bankmachine2_req_rdata_valid <= _0345_;
      sdram_bankmachine2_refresh_gnt <= _0344_;
      sdram_bankmachine2_cmd_valid <= _0343_;
      sdram_bankmachine2_cmd_payload_cas <= _0336_;
      sdram_bankmachine2_cmd_payload_ras <= _0340_;
      sdram_bankmachine2_cmd_payload_we <= _0341_;
      sdram_bankmachine2_cmd_payload_is_cmd <= _0337_;
      sdram_bankmachine2_cmd_payload_is_read <= _0338_;
      sdram_bankmachine2_cmd_payload_is_write <= _0339_;
      sdram_bankmachine2_row_open <= _0350_;
      sdram_bankmachine2_row_close <= _0348_;
      sdram_bankmachine2_row_col_n_addr_sel <= _0349_;
      subfragments_bankmachine2_next_state <= _0487_;
  end
  always @* begin
    if (\initial ) begin end
    _0726_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      ram_we <= _0726_;
  end
  always @* begin
    if (\initial ) begin end
    _0629_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      int_rst <= _0629_;
  end
  always @* begin
    if (\initial ) begin end
    _0369_ = 13'h0000;
    (* src = "ls180.v:2332.2-2336.5" *)
    casez (sdram_bankmachine3_row_col_n_addr_sel)
      /* src = "ls180.v:2332.6-2332.43" */
      1'h1:
          _0369_ = sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
      /* src = "ls180.v:2334.6-2334.10" */
      default:
          _0369_ = _2193_;
    endcase
  end
  always @* begin
      sdram_bankmachine3_cmd_payload_a <= _0369_;
  end
  always @* begin
    if (\initial ) begin end
    _0356_ = 1'h0;
    (* src = "ls180.v:2343.2-2347.5" *)
    casez (_1126_)
      /* src = "ls180.v:2343.6-2343.105" */
      1'h1:
          (* src = "ls180.v:2344.3-2346.6" *)
          casez (_1961_)
            /* src = "ls180.v:2344.7-2344.133" */
            1'h1:
                _0356_ = _1656_;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine3_auto_precharge <= _0356_;
  end
  always @* begin
    if (\initial ) begin end
    _0363_ = 3'h0;
    (* src = "ls180.v:2365.2-2369.5" *)
    casez (sdram_bankmachine3_cmd_buffer_lookahead_replace)
      /* src = "ls180.v:2365.6-2365.53" */
      1'h1:
          _0363_ = _2362_;
      /* src = "ls180.v:2367.6-2367.10" */
      default:
          _0363_ = sdram_bankmachine3_cmd_buffer_lookahead_produce;
    endcase
  end
  always @* begin
      sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= _0363_;
  end
  always @* begin
    if (\initial ) begin end
    _0372_ = 1'h0;
    _0373_ = 1'h0;
    _0380_ = 1'h0;
    _0379_ = 1'h0;
    _0378_ = 1'h0;
    _0377_ = 1'h0;
    _0384_ = 1'h0;
    _0382_ = 1'h0;
    _0370_ = 1'h0;
    _0383_ = 1'h0;
    _0374_ = 1'h0;
    _0375_ = 1'h0;
    _0371_ = 1'h0;
    _0489_ = subfragments_bankmachine3_state;
    (* src = "ls180.v:2395.2-2471.9" *)
    casez (subfragments_bankmachine3_state)
      /* src = "ls180.v:0.0-0.0" */
      3'h1:
        begin
          _0382_ = 1'h1;
          (* src = "ls180.v:2397.4-2405.7" *)
          casez (_1129_)
            /* src = "ls180.v:2397.8-2397.77" */
            1'h1:
              begin
                _0377_ = 1'h1;
                _0374_ = 1'h1;
                _0375_ = 1'h1;
                _0371_ = 1'h1;
                (* src = "ls180.v:2399.5-2401.8" *)
                casez (sdram_bankmachine3_cmd_ready)
                  /* src = "ls180.v:2399.9-2399.37" */
                  1'h1:
                      _0489_ = 3'h5;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h2:
        begin
          _0382_ = 1'h1;
          (* src = "ls180.v:2409.4-2411.7" *)
          casez (_1130_)
            /* src = "ls180.v:2409.8-2409.77" */
            1'h1:
                _0489_ = 3'h5;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h3:
          (* src = "ls180.v:2415.4-2424.7" *)
          casez (sdram_bankmachine3_trccon_ready)
            /* src = "ls180.v:2415.8-2415.39" */
            1'h1:
              begin
                _0383_ = 1'h1;
                _0384_ = 1'h1;
                _0377_ = 1'h1;
                _0371_ = 1'h1;
                _0374_ = 1'h1;
                (* src = "ls180.v:2420.5-2422.8" *)
                casez (sdram_bankmachine3_cmd_ready)
                  /* src = "ls180.v:2420.9-2420.37" */
                  1'h1:
                      _0489_ = 3'h6;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      3'h4:
        begin
          _0382_ = 1'h1;
          _0371_ = 1'h1;
          (* src = "ls180.v:2427.4-2429.7" *)
          casez (sdram_bankmachine3_twtpcon_ready)
            /* src = "ls180.v:2427.8-2427.40" */
            1'h1:
                _0378_ = 1'h1;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2432.4-2434.7" *)
          casez (_1990_)
            /* src = "ls180.v:2432.8-2432.41" */
            1'h1:
                _0489_ = 3'h0;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h5:
          _0489_ = 3'h3;
      /* src = "ls180.v:0.0-0.0" */
      3'h6:
          _0489_ = 3'h0;
      /* src = "ls180.v:0.0-0.0" */
      default:
          (* src = "ls180.v:2443.4-2469.7" *)
          casez (sdram_bankmachine3_refresh_req)
            /* src = "ls180.v:2443.8-2443.38" */
            1'h1:
                _0489_ = 3'h4;
            /* src = "ls180.v:2445.8-2445.12" */
            default:
                (* src = "ls180.v:2446.5-2468.8" *)
                casez (sdram_bankmachine3_cmd_buffer_source_valid)
                  /* src = "ls180.v:2446.9-2446.51" */
                  1'h1:
                      (* src = "ls180.v:2447.6-2467.9" *)
                      casez (sdram_bankmachine3_row_opened)
                        /* src = "ls180.v:2447.10-2447.39" */
                        1'h1:
                            (* src = "ls180.v:2448.7-2464.10" *)
                            casez (sdram_bankmachine3_row_hit)
                              /* src = "ls180.v:2448.11-2448.37" */
                              1'h1:
                                begin
                                  _0377_ = 1'h1;
                                  _0370_ = 1'h1;
                                  (* src = "ls180.v:2450.8-2457.11" *)
                                  casez (sdram_bankmachine3_cmd_buffer_source_payload_we)
                                    /* src = "ls180.v:2450.12-2450.59" */
                                    1'h1:
                                      begin
                                        _0380_ = sdram_bankmachine3_cmd_ready;
                                        _0373_ = 1'h1;
                                        _0375_ = 1'h1;
                                      end
                                    /* src = "ls180.v:2454.12-2454.16" */
                                    default:
                                      begin
                                        _0379_ = sdram_bankmachine3_cmd_ready;
                                        _0372_ = 1'h1;
                                      end
                                  endcase
                                  (* src = "ls180.v:2459.8-2461.11" *)
                                  casez (_1131_)
                                    /* src = "ls180.v:2459.12-2459.78" */
                                    1'h1:
                                        _0489_ = 3'h2;
                                    default:
                                        /* empty */;
                                  endcase
                                end
                              /* src = "ls180.v:2462.11-2462.15" */
                              default:
                                  _0489_ = 3'h1;
                            endcase
                        /* src = "ls180.v:2465.10-2465.14" */
                        default:
                            _0489_ = 3'h3;
                      endcase
                  default:
                      /* empty */;
                endcase
          endcase
    endcase
  end
  always @* begin
      sdram_bankmachine3_req_wdata_ready <= _0380_;
      sdram_bankmachine3_req_rdata_valid <= _0379_;
      sdram_bankmachine3_refresh_gnt <= _0378_;
      sdram_bankmachine3_cmd_valid <= _0377_;
      sdram_bankmachine3_cmd_payload_cas <= _0370_;
      sdram_bankmachine3_cmd_payload_ras <= _0374_;
      sdram_bankmachine3_cmd_payload_we <= _0375_;
      sdram_bankmachine3_cmd_payload_is_cmd <= _0371_;
      sdram_bankmachine3_cmd_payload_is_read <= _0372_;
      sdram_bankmachine3_cmd_payload_is_write <= _0373_;
      sdram_bankmachine3_row_open <= _0384_;
      sdram_bankmachine3_row_close <= _0382_;
      sdram_bankmachine3_row_col_n_addr_sel <= _0383_;
      subfragments_bankmachine3_next_state <= _0489_;
  end
  always @* begin
    if (\initial ) begin end
    _0603_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      dfi_p0_rddata <= _0603_;
  end
  always @* begin
    if (\initial ) begin end
    _0604_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dfi_p0_rddata_valid <= _0604_;
  end
  always @* begin
    if (\initial ) begin end
    _0727_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      rddata_en <= _0727_;
  end
  always @* begin
    if (\initial ) begin end
    _0395_[0] = _1161_;
    _0395_[1] = _1167_;
    _0395_[2] = _1173_;
    _0395_[3] = _1179_;
  end
  always @* begin
      sdram_choose_cmd_valids <= _0395_;
  end
  always @* begin
    if (\initial ) begin end
    _0926_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_cas_n <= _0926_;
  end
  always @* begin
    if (\initial ) begin end
    _0390_ = 1'h0;
    (* src = "ls180.v:2508.2-2510.5" *)
    casez (sdram_choose_cmd_cmd_valid)
      /* src = "ls180.v:2508.6-2508.32" */
      1'h1:
          _0390_ = t_array_muxed0;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_cmd_cmd_payload_cas <= _0390_;
  end
  always @* begin
    if (\initial ) begin end
    _0927_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_cs_n <= _0927_;
  end
  always @* begin
    if (\initial ) begin end
    _0391_ = 1'h0;
    (* src = "ls180.v:2514.2-2516.5" *)
    casez (sdram_choose_cmd_cmd_valid)
      /* src = "ls180.v:2514.6-2514.32" */
      1'h1:
          _0391_ = t_array_muxed1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_cmd_cmd_payload_ras <= _0391_;
  end
  always @* begin
    if (\initial ) begin end
    _0392_ = 1'h0;
    (* src = "ls180.v:2520.2-2522.5" *)
    casez (sdram_choose_cmd_cmd_valid)
      /* src = "ls180.v:2520.6-2520.32" */
      1'h1:
          _0392_ = t_array_muxed2;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_cmd_cmd_payload_we <= _0392_;
  end
  always @* begin
    if (\initial ) begin end
    _0928_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_ras_n <= _0928_;
  end
  always @* begin
    if (\initial ) begin end
    _0405_[0] = _1185_;
    _0405_[1] = _1191_;
    _0405_[2] = _1197_;
    _0405_[3] = _1203_;
  end
  always @* begin
      sdram_choose_req_valids <= _0405_;
  end
  always @* begin
    if (\initial ) begin end
    _0931_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_we_n <= _0931_;
  end
  always @* begin
    if (\initial ) begin end
    _0400_ = 1'h0;
    (* src = "ls180.v:2541.2-2543.5" *)
    casez (sdram_choose_req_cmd_valid)
      /* src = "ls180.v:2541.6-2541.32" */
      1'h1:
          _0400_ = t_array_muxed3;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_req_cmd_payload_cas <= _0400_;
  end
  always @* begin
    if (\initial ) begin end
    _0401_ = 1'h0;
    (* src = "ls180.v:2547.2-2549.5" *)
    casez (sdram_choose_req_cmd_valid)
      /* src = "ls180.v:2547.6-2547.32" */
      1'h1:
          _0401_ = t_array_muxed4;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_req_cmd_payload_ras <= _0401_;
  end
  always @* begin
    if (\initial ) begin end
    _0402_ = 1'h0;
    (* src = "ls180.v:2553.2-2555.5" *)
    casez (sdram_choose_req_cmd_valid)
      /* src = "ls180.v:2553.6-2553.32" */
      1'h1:
          _0402_ = t_array_muxed5;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_choose_req_cmd_payload_we <= _0402_;
  end
  always @* begin
    if (\initial ) begin end
    _0274_ = 1'h0;
    (* src = "ls180.v:2559.2-2561.5" *)
    casez (_1205_)
      /* src = "ls180.v:2559.6-2559.100" */
      1'h1:
          _0274_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:2562.2-2564.5" *)
    casez (_1207_)
      /* src = "ls180.v:2562.6-2562.100" */
      1'h1:
          _0274_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine0_cmd_ready <= _0274_;
  end
  always @* begin
    if (\initial ) begin end
    _0308_ = 1'h0;
    (* src = "ls180.v:2568.2-2570.5" *)
    casez (_1209_)
      /* src = "ls180.v:2568.6-2568.100" */
      1'h1:
          _0308_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:2571.2-2573.5" *)
    casez (_1211_)
      /* src = "ls180.v:2571.6-2571.100" */
      1'h1:
          _0308_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine1_cmd_ready <= _0308_;
  end
  always @* begin
    if (\initial ) begin end
    _0435_ = 1'h1;
  end
  always @* begin
      sdram_inti_p0_act_n <= _0435_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0342_ = 1'h0;
    (* src = "ls180.v:2577.2-2579.5" *)
    casez (_1213_)
      /* src = "ls180.v:2577.6-2577.100" */
      1'h1:
          _0342_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:2580.2-2582.5" *)
    casez (_1215_)
      /* src = "ls180.v:2580.6-2580.100" */
      1'h1:
          _0342_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine2_cmd_ready <= _0342_;
  end
  always @* begin
    if (\initial ) begin end
    _0376_ = 1'h0;
    (* src = "ls180.v:2586.2-2588.5" *)
    casez (_1217_)
      /* src = "ls180.v:2586.6-2586.100" */
      1'h1:
          _0376_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:2589.2-2591.5" *)
    casez (_1219_)
      /* src = "ls180.v:2589.6-2589.100" */
      1'h1:
          _0376_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      sdram_bankmachine3_cmd_ready <= _0376_;
  end
  always @* begin
    if (\initial ) begin end
    _0432_ = 1'h0;
    _0407_ = 1'h0;
    _0408_ = 1'h0;
    _0417_ = 1'h0;
    _0470_ = 2'h0;
    _0403_ = 1'h0;
    _0431_ = 1'h0;
    _0406_ = sdram_ras_allowed;
    _0499_ = subfragments_multiplexer_state;
    (* src = "ls180.v:2609.2-2668.9" *)
    casez (subfragments_multiplexer_state)
      /* src = "ls180.v:0.0-0.0" */
      3'h1:
        begin
          _0432_ = 1'h1;
          _0408_ = 1'h1;
          _0470_ = 2'h2;
          (* src = "ls180.v:2613.4-2619.7" *)
          casez (1'h1)
            /* src = "ls180.v:2613.8-2613.12" */
            1'h1:
                _0403_ = _1222_;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2621.4-2625.7" *)
          casez (sdram_read_available)
            /* src = "ls180.v:2621.8-2621.28" */
            1'h1:
                (* src = "ls180.v:2622.5-2624.8" *)
                casez (_2222_)
                  /* src = "ls180.v:2622.9-2622.53" */
                  1'h1:
                      _0499_ = 3'h3;
                  default:
                      /* empty */;
                endcase
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2626.4-2628.7" *)
          casez (sdram_go_to_refresh)
            /* src = "ls180.v:2626.8-2626.27" */
            1'h1:
                _0499_ = 3'h2;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h2:
        begin
          _0470_ = 2'h3;
          _0417_ = 1'h1;
          (* src = "ls180.v:2633.4-2635.7" *)
          casez (sdram_cmd_last)
            /* src = "ls180.v:2633.8-2633.22" */
            1'h1:
                _0499_ = 3'h0;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      3'h3:
          (* src = "ls180.v:2638.4-2640.7" *)
          casez (sdram_twtrcon_ready)
            /* src = "ls180.v:2638.8-2638.27" */
            1'h1:
                _0499_ = 3'h0;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      3'h4:
          _0499_ = 3'h5;
      /* src = "ls180.v:0.0-0.0" */
      3'h5:
          _0499_ = 3'h1;
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0431_ = 1'h1;
          _0407_ = 1'h1;
          _0470_ = 2'h2;
          (* src = "ls180.v:2651.4-2657.7" *)
          casez (1'h1)
            /* src = "ls180.v:2651.8-2651.12" */
            1'h1:
                _0403_ = _1225_;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2659.4-2663.7" *)
          casez (sdram_write_available)
            /* src = "ls180.v:2659.8-2659.29" */
            1'h1:
                (* src = "ls180.v:2660.5-2662.8" *)
                casez (_2224_)
                  /* src = "ls180.v:2660.9-2660.52" */
                  1'h1:
                      _0499_ = 3'h4;
                  default:
                      /* empty */;
                endcase
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2664.4-2666.7" *)
          casez (sdram_go_to_refresh)
            /* src = "ls180.v:2664.8-2664.27" */
            1'h1:
                _0499_ = 3'h2;
            default:
                /* empty */;
          endcase
        end
    endcase
  end
  always @* begin
      sdram_cmd_ready <= _0417_;
      sdram_choose_req_want_reads <= _0407_;
      sdram_choose_req_want_writes <= _0408_;
      sdram_choose_req_want_activates <= _0406_;
      sdram_choose_req_cmd_ready <= _0403_;
      sdram_steerer_sel <= _0470_;
      sdram_en0 <= _0431_;
      sdram_en1 <= _0432_;
      subfragments_multiplexer_next_state <= _0499_;
  end
  always @* begin
    if (\initial ) begin end
    _0929_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_rddata <= _0929_;
  end
  always @* begin
    if (\initial ) begin end
    _0930_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_inti_p0_rddata_valid <= _0930_;
  end
  always @* begin
    if (\initial ) begin end
    _0433_ = 16'h0000;
    _0434_ = 2'h0;
    (* src = "ls180.v:2696.2-2705.9" *)
    casez (subfragments_new_master_wdata_ready)
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
        begin
          _0433_ = port_wdata_payload_data;
          _0434_ = port_wdata_payload_we;
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0433_ = 16'h0000;
          _0434_ = 2'h0;
        end
    endcase
  end
  always @* begin
      sdram_interface_wdata <= _0433_;
      sdram_interface_wdata_we <= _0434_;
  end
  always @* begin
    if (\initial ) begin end
    _0188_ = 16'h0000;
    (* src = "ls180.v:2715.2-2722.9" *)
    casez (converter_counter)
      /* src = "ls180.v:0.0-0.0" */
      1'h0:
          _0188_ = wb_sdram_dat_w[15:0];
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
          _0188_ = wb_sdram_dat_w[31:16];
      default:
          /* empty */;
    endcase
  end
  always @* begin
      litedram_wb_dat_w <= _0188_;
  end
  always @* begin
    if (\initial ) begin end
    _0189_ = 2'h0;
    _0187_ = 1'h0;
    _0190_ = 1'h0;
    _0051_ = 1'h0;
    _0191_ = 1'h0;
    _0052_ = 1'h0;
    _0054_ = 1'h0;
    _0545_ = 1'h0;
    _0186_ = 30'h00000000;
    _0506_ = subfragments_state;
    (* src = "ls180.v:2737.2-2770.9" *)
    casez (subfragments_state)
      /* src = "ls180.v:0.0-0.0" */
      1'h1:
        begin
          _0186_ = { wb_sdram_adr[28:0], converter_counter };
          (* src = "ls180.v:2740.4-2747.11" *)
          casez (converter_counter)
            /* src = "ls180.v:0.0-0.0" */
            1'h0:
                _0189_ = wb_sdram_sel[1:0];
            /* src = "ls180.v:0.0-0.0" */
            1'h1:
                _0189_ = wb_sdram_sel[3:2];
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:2748.4-2761.7" *)
          casez (_1274_)
            /* src = "ls180.v:2748.8-2748.37" */
            1'h1:
              begin
                _0054_ = _1719_;
                _0191_ = wb_sdram_we;
                _0187_ = _2047_;
                _0190_ = _2048_;
                (* src = "ls180.v:2753.5-2760.8" *)
                casez (_2253_)
                  /* src = "ls180.v:2753.9-2753.43" */
                  1'h1:
                    begin
                      _0051_ = _1024_;
                      _0052_ = 1'h1;
                      (* src = "ls180.v:2756.6-2759.9" *)
                      casez (_1720_)
                        /* src = "ls180.v:2756.10-2756.37" */
                        1'h1:
                          begin
                            _0545_ = 1'h1;
                            _0506_ = 1'h0;
                          end
                        default:
                            /* empty */;
                      endcase
                    end
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0051_ = 1'h0;
          _0052_ = 1'h1;
          (* src = "ls180.v:2766.4-2768.7" *)
          casez (_1275_)
            /* src = "ls180.v:2766.8-2766.37" */
            1'h1:
                _0506_ = 1'h1;
            default:
                /* empty */;
          endcase
        end
    endcase
  end
  always @* begin
      wb_sdram_ack <= _0545_;
      litedram_wb_adr <= _0186_;
      litedram_wb_sel <= _0189_;
      litedram_wb_cyc <= _0187_;
      litedram_wb_stb <= _0190_;
      litedram_wb_we <= _0191_;
      converter_skip <= _0054_;
      subfragments_next_state <= _0506_;
      converter_counter_subfragments_next_value <= _0051_;
      converter_counter_subfragments_next_value_ce <= _0052_;
  end
  always @* begin
    if (\initial ) begin end
    _0953_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_slave_p0_rddata <= _0953_;
  end
  always @* begin
    if (\initial ) begin end
    _0954_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_slave_p0_rddata_valid <= _0954_;
  end
  always @* begin
    if (\initial ) begin end
    _0933_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_address <= _0933_;
  end
  always @* begin
    if (\initial ) begin end
    _0934_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_bank <= _0934_;
  end
  always @* begin
    if (\initial ) begin end
    _0516_ = 1'h0;
    (* src = "ls180.v:2818.2-2820.5" *)
    casez (_1288_)
      /* src = "ls180.v:2818.6-2818.59" */
      1'h1:
          _0516_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      tx_clear <= _0516_;
  end
  always @* begin
    if (\initial ) begin end
    _0935_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_cas_n <= _0935_;
  end
  always @* begin
    if (\initial ) begin end
    _0061_[0] = tx_status;
    _0061_[1] = rx_status;
  end
  always @* begin
      eventmanager_status_w <= _0061_;
  end
  always @* begin
    if (\initial ) begin end
    _0241_ = 1'h0;
    (* src = "ls180.v:2829.2-2831.5" *)
    casez (_1289_)
      /* src = "ls180.v:2829.6-2829.59" */
      1'h1:
          _0241_ = 1'h1;
      default:
          /* empty */;
    endcase
  end
  always @* begin
      rx_clear <= _0241_;
  end
  always @* begin
    if (\initial ) begin end
    _0937_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_cs_n <= _0937_;
  end
  always @* begin
    if (\initial ) begin end
    _0059_[0] = tx_pending;
    _0059_[1] = rx_pending;
  end
  always @* begin
      eventmanager_pending_w <= _0059_;
  end
  always @* begin
    if (\initial ) begin end
    _0939_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_ras_n <= _0939_;
  end
  always @* begin
    if (\initial ) begin end
    _0942_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_we_n <= _0942_;
  end
  always @* begin
    if (\initial ) begin end
    _0524_ = 4'h0;
    (* src = "ls180.v:2857.2-2861.5" *)
    casez (tx_fifo_replace)
      /* src = "ls180.v:2857.6-2857.21" */
      1'h1:
          _0524_ = _2364_;
      /* src = "ls180.v:2859.6-2859.10" */
      default:
          _0524_ = tx_fifo_produce;
    endcase
  end
  always @* begin
      tx_fifo_wrport_adr <= _0524_;
  end
  always @* begin
    if (\initial ) begin end
    _0936_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_cke <= _0936_;
  end
  always @* begin
    if (\initial ) begin end
    _0938_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_odt <= _0938_;
  end
  always @* begin
    if (\initial ) begin end
    _0941_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_reset_n <= _0941_;
  end
  always @* begin
    if (\initial ) begin end
    _0247_ = 4'h0;
    (* src = "ls180.v:2887.2-2891.5" *)
    casez (rx_fifo_replace)
      /* src = "ls180.v:2887.6-2887.21" */
      1'h1:
          _0247_ = _2365_;
      /* src = "ls180.v:2889.6-2889.10" */
      default:
          _0247_ = rx_fifo_produce;
    endcase
  end
  always @* begin
      rx_fifo_wrport_adr <= _0247_;
  end
  always @* begin
    if (\initial ) begin end
    _0932_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_act_n <= _0932_;
  end
  always @* begin
    if (\initial ) begin end
    _0943_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_wrdata <= _0943_;
  end
  always @* begin
    if (\initial ) begin end
    _0067_[0] = libresocsim_libresoc_constraintmanager_gpio_i[0];
    _0067_[1] = libresocsim_libresoc_constraintmanager_gpio_i[1];
    _0067_[2] = libresocsim_libresoc_constraintmanager_gpio_i[2];
    _0067_[3] = libresocsim_libresoc_constraintmanager_gpio_i[3];
    _0067_[4] = libresocsim_libresoc_constraintmanager_gpio_i[4];
    _0067_[5] = libresocsim_libresoc_constraintmanager_gpio_i[5];
    _0067_[6] = libresocsim_libresoc_constraintmanager_gpio_i[6];
    _0067_[7] = libresocsim_libresoc_constraintmanager_gpio_i[7];
  end
  always @* begin
      gpio0_pads_gpio0i <= _0067_;
  end
  always @* begin
    if (\initial ) begin end
    _0944_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_wrdata_en <= _0944_;
  end
  always @* begin
    if (\initial ) begin end
    _0075_[0] = libresocsim_libresoc_constraintmanager_gpio_i[8];
    _0075_[1] = libresocsim_libresoc_constraintmanager_gpio_i[9];
    _0075_[2] = libresocsim_libresoc_constraintmanager_gpio_i[10];
    _0075_[3] = libresocsim_libresoc_constraintmanager_gpio_i[11];
    _0075_[4] = libresocsim_libresoc_constraintmanager_gpio_i[12];
    _0075_[5] = libresocsim_libresoc_constraintmanager_gpio_i[13];
    _0075_[6] = libresocsim_libresoc_constraintmanager_gpio_i[14];
    _0075_[7] = libresocsim_libresoc_constraintmanager_gpio_i[15];
  end
  always @* begin
      gpio1_pads_gpio1i <= _0075_;
  end
  always @* begin
    if (\initial ) begin end
    _0945_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_wrdata_mask <= _0945_;
  end
  always @* begin
    if (\initial ) begin end
    _0125_[0] = gpio0_pads_gpio0o[0];
    _0125_[1] = gpio0_pads_gpio0o[1];
    _0125_[2] = gpio0_pads_gpio0o[2];
    _0125_[3] = gpio0_pads_gpio0o[3];
    _0125_[4] = gpio0_pads_gpio0o[4];
    _0125_[5] = gpio0_pads_gpio0o[5];
    _0125_[6] = gpio0_pads_gpio0o[6];
    _0125_[7] = gpio0_pads_gpio0o[7];
    _0125_[8] = gpio1_pads_gpio1o[0];
    _0125_[9] = gpio1_pads_gpio1o[1];
    _0125_[10] = gpio1_pads_gpio1o[2];
    _0125_[11] = gpio1_pads_gpio1o[3];
    _0125_[12] = gpio1_pads_gpio1o[4];
    _0125_[13] = gpio1_pads_gpio1o[5];
    _0125_[14] = gpio1_pads_gpio1o[6];
    _0125_[15] = gpio1_pads_gpio1o[7];
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_gpio_o <= _0125_;
  end
  always @* begin
    if (\initial ) begin end
    _0940_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_master_p0_rddata_en <= _0940_;
  end
  always @* begin
    if (\initial ) begin end
    _0126_[0] = gpio0_pads_gpio0oe[0];
    _0126_[1] = gpio0_pads_gpio0oe[1];
    _0126_[2] = gpio0_pads_gpio0oe[2];
    _0126_[3] = gpio0_pads_gpio0oe[3];
    _0126_[4] = gpio0_pads_gpio0oe[4];
    _0126_[5] = gpio0_pads_gpio0oe[5];
    _0126_[6] = gpio0_pads_gpio0oe[6];
    _0126_[7] = gpio0_pads_gpio0oe[7];
    _0126_[8] = gpio1_pads_gpio1oe[0];
    _0126_[9] = gpio1_pads_gpio1oe[1];
    _0126_[10] = gpio1_pads_gpio1oe[2];
    _0126_[11] = gpio1_pads_gpio1oe[3];
    _0126_[12] = gpio1_pads_gpio1oe[4];
    _0126_[13] = gpio1_pads_gpio1oe[5];
    _0126_[14] = gpio1_pads_gpio1oe[6];
    _0126_[15] = gpio1_pads_gpio1oe[7];
  end
  always @* begin
      libresocsim_libresoc_constraintmanager_gpio_oe <= _0126_;
  end
  always @* begin
    if (\initial ) begin end
    _0154_ = 8'h00;
    _0155_ = 1'h0;
    _0151_ = 14'h0000;
    _0152_ = 1'h0;
    _0160_ = 32'd0;
    _0157_ = 1'h0;
    _0158_ = 1'h0;
    _0159_ = 1'h0;
    _0164_ = libresocsim_state;
    (* src = "ls180.v:2976.2-3000.9" *)
    casez (libresocsim_state)
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
        begin
          _0151_ = 14'h0000;
          _0152_ = 1'h1;
          _0157_ = 1'h0;
          _0158_ = 1'h1;
          _0164_ = 2'h2;
        end
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
        begin
          _0159_ = 1'h1;
          _0160_ = { 24'h000000, libresocsim_libresocsim_dat_r };
          _0164_ = 2'h0;
        end
      /* src = "ls180.v:0.0-0.0" */
      default:
        begin
          _0154_ = libresocsim_libresocsim_wishbone_dat_w[7:0];
          _0155_ = 1'h1;
          (* src = "ls180.v:2992.4-2998.7" *)
          casez (_1298_)
            /* src = "ls180.v:2992.8-2992.85" */
            1'h1:
              begin
                _0151_ = libresocsim_libresocsim_wishbone_adr[13:0];
                _0152_ = 1'h1;
                _0157_ = _1299_;
                _0158_ = 1'h1;
                _0164_ = 2'h1;
              end
            default:
                /* empty */;
          endcase
        end
    endcase
  end
  always @* begin
      libresocsim_libresocsim_wishbone_dat_r <= _0160_;
      libresocsim_libresocsim_wishbone_ack <= _0159_;
      libresocsim_next_state <= _0164_;
      libresocsim_libresocsim_dat_w_libresocsim_next_value0 <= _0154_;
      libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 <= _0155_;
      libresocsim_libresocsim_adr_libresocsim_next_value1 <= _0151_;
      libresocsim_libresocsim_adr_libresocsim_next_value_ce1 <= _0152_;
      libresocsim_libresocsim_we_libresocsim_next_value2 <= _0157_;
      libresocsim_libresocsim_we_libresocsim_next_value_ce2 <= _0158_;
  end
  always @* begin
    if (\initial ) begin end
    _0957_ = 4'h1;
  end
  always @* begin
  end
  initial begin
      sdram_storage <= _0957_;
  end
  always @* begin
    if (\initial ) begin end
    _0948_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_re <= _0948_;
  end
  always @* begin
    if (\initial ) begin end
    _0913_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      sdram_command_storage <= _0913_;
  end
  always @* begin
    if (\initial ) begin end
    _0175_[0] = _1727_;
    _0175_[1] = _1728_;
    _0175_[2] = _1729_;
    _0175_[3] = _1730_;
    _0175_[4] = _1731_;
    _0175_[5] = _1732_;
  end
  always @* begin
      libresocsim_slave_sel <= _0175_;
  end
  always @* begin
    if (\initial ) begin end
    _0912_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_command_re <= _0912_;
  end
  always @* begin
    if (\initial ) begin end
    _0419_ = 1'h0;
  end
  always @* begin
      sdram_command_issue_w <= _0419_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0096_ = 1'h0;
    _0173_ = _2274_;
    _0174_ = _2279_;
    (* src = "ls180.v:3085.2-3089.5" *)
    casez (libresocsim_done)
      /* src = "ls180.v:3085.6-3085.22" */
      1'h1:
        begin
          _0174_ = 32'd4294967295;
          _0173_ = 1'h1;
          _0096_ = 1'h1;
        end
      default:
          /* empty */;
    endcase
  end
  always @* begin
      libresocsim_shared_dat_r <= _0174_;
      libresocsim_shared_ack <= _0173_;
      libresocsim_error <= _0096_;
  end
  always @* begin
    if (\initial ) begin end
    _0771_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_address_storage <= _0771_;
  end
  always @* begin
    if (\initial ) begin end
    _0770_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_address_re <= _0770_;
  end
  always @* begin
    if (\initial ) begin end
    _0773_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_baddress_storage <= _0773_;
  end
  always @* begin
    if (\initial ) begin end
    _0772_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_baddress_re <= _0772_;
  end
  always @* begin
    if (\initial ) begin end
    _0966_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_wrdata_storage <= _0966_;
  end
  always @* begin
    if (\initial ) begin end
    _0965_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_wrdata_re <= _0965_;
  end
  always @* begin
    if (\initial ) begin end
    _0955_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_status <= _0955_;
  end
  always @* begin
    if (\initial ) begin end
    _0209_ = 1'h0;
    (* src = "ls180.v:3367.2-3380.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0209_ = sdram_choose_cmd_valids[0];
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0209_ = sdram_choose_cmd_valids[1];
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0209_ = sdram_choose_cmd_valids[2];
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0209_ = sdram_choose_cmd_valids[3];
    endcase
  end
  always @* begin
      rhs_array_muxed0 <= _0209_;
  end
  always @* begin
    if (\initial ) begin end
    _0220_ = 13'h0000;
    (* src = "ls180.v:3384.2-3397.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0220_ = sdram_bankmachine0_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0220_ = sdram_bankmachine1_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0220_ = sdram_bankmachine2_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0220_ = sdram_bankmachine3_cmd_payload_a;
    endcase
  end
  always @* begin
      rhs_array_muxed1 <= _0220_;
  end
  always @* begin
    if (\initial ) begin end
    _0231_ = 2'h0;
    (* src = "ls180.v:3401.2-3414.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0231_ = sdram_bankmachine0_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0231_ = sdram_bankmachine1_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0231_ = sdram_bankmachine2_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0231_ = sdram_bankmachine3_cmd_payload_ba;
    endcase
  end
  always @* begin
      rhs_array_muxed2 <= _0231_;
  end
  always @* begin
    if (\initial ) begin end
    _0234_ = 1'h0;
    (* src = "ls180.v:3418.2-3431.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0234_ = sdram_bankmachine0_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0234_ = sdram_bankmachine1_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0234_ = sdram_bankmachine2_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0234_ = sdram_bankmachine3_cmd_payload_is_read;
    endcase
  end
  always @* begin
      rhs_array_muxed3 <= _0234_;
  end
  always @* begin
    if (\initial ) begin end
    _0235_ = 1'h0;
    (* src = "ls180.v:3435.2-3448.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0235_ = sdram_bankmachine0_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0235_ = sdram_bankmachine1_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0235_ = sdram_bankmachine2_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0235_ = sdram_bankmachine3_cmd_payload_is_write;
    endcase
  end
  always @* begin
      rhs_array_muxed4 <= _0235_;
  end
  always @* begin
    if (\initial ) begin end
    _0924_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_interface_wdata <= _0924_;
  end
  always @* begin
    if (\initial ) begin end
    _0925_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_interface_wdata_we <= _0925_;
  end
  always @* begin
    if (\initial ) begin end
    _0236_ = 1'h0;
    (* src = "ls180.v:3452.2-3465.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0236_ = sdram_bankmachine0_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0236_ = sdram_bankmachine1_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0236_ = sdram_bankmachine2_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0236_ = sdram_bankmachine3_cmd_payload_is_cmd;
    endcase
  end
  always @* begin
      rhs_array_muxed5 <= _0236_;
  end
  always @* begin
    if (\initial ) begin end
    _0510_ = 1'h0;
    (* src = "ls180.v:3469.2-3482.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0510_ = sdram_bankmachine0_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0510_ = sdram_bankmachine1_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0510_ = sdram_bankmachine2_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0510_ = sdram_bankmachine3_cmd_payload_cas;
    endcase
  end
  always @* begin
      t_array_muxed0 <= _0510_;
  end
  always @* begin
    if (\initial ) begin end
    _0914_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_address <= _0914_;
  end
  always @* begin
    if (\initial ) begin end
    _0915_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_bank <= _0915_;
  end
  always @* begin
    if (\initial ) begin end
    _0511_ = 1'h0;
    (* src = "ls180.v:3486.2-3499.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0511_ = sdram_bankmachine0_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0511_ = sdram_bankmachine1_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0511_ = sdram_bankmachine2_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0511_ = sdram_bankmachine3_cmd_payload_ras;
    endcase
  end
  always @* begin
      t_array_muxed1 <= _0511_;
  end
  always @* begin
    if (\initial ) begin end
    _0916_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_cas_n <= _0916_;
  end
  always @* begin
    if (\initial ) begin end
    _0917_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_cs_n <= _0917_;
  end
  always @* begin
    if (\initial ) begin end
    _0512_ = 1'h0;
    (* src = "ls180.v:3503.2-3516.9" *)
    casez (sdram_choose_cmd_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0512_ = sdram_bankmachine0_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0512_ = sdram_bankmachine1_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0512_ = sdram_bankmachine2_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0512_ = sdram_bankmachine3_cmd_payload_we;
    endcase
  end
  always @* begin
      t_array_muxed2 <= _0512_;
  end
  always @* begin
    if (\initial ) begin end
    _0918_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_ras_n <= _0918_;
  end
  always @* begin
    if (\initial ) begin end
    _0237_ = 1'h0;
    (* src = "ls180.v:3520.2-3533.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0237_ = sdram_choose_req_valids[0];
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0237_ = sdram_choose_req_valids[1];
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0237_ = sdram_choose_req_valids[2];
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0237_ = sdram_choose_req_valids[3];
    endcase
  end
  always @* begin
      rhs_array_muxed6 <= _0237_;
  end
  always @* begin
    if (\initial ) begin end
    _0920_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_we_n <= _0920_;
  end
  always @* begin
    if (\initial ) begin end
    _0238_ = 13'h0000;
    (* src = "ls180.v:3537.2-3550.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0238_ = sdram_bankmachine0_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0238_ = sdram_bankmachine1_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0238_ = sdram_bankmachine2_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0238_ = sdram_bankmachine3_cmd_payload_a;
    endcase
  end
  always @* begin
      rhs_array_muxed7 <= _0238_;
  end
  always @* begin
    if (\initial ) begin end
    _0239_ = 2'h0;
    (* src = "ls180.v:3554.2-3567.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0239_ = sdram_bankmachine0_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0239_ = sdram_bankmachine1_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0239_ = sdram_bankmachine2_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0239_ = sdram_bankmachine3_cmd_payload_ba;
    endcase
  end
  always @* begin
      rhs_array_muxed8 <= _0239_;
  end
  always @* begin
    if (\initial ) begin end
    _0422_ = 1'h1;
  end
  always @* begin
      sdram_dfi_p0_act_n <= _0422_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0240_ = 1'h0;
    (* src = "ls180.v:3571.2-3584.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0240_ = sdram_bankmachine0_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0240_ = sdram_bankmachine1_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0240_ = sdram_bankmachine2_cmd_payload_is_read;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0240_ = sdram_bankmachine3_cmd_payload_is_read;
    endcase
  end
  always @* begin
      rhs_array_muxed9 <= _0240_;
  end
  always @* begin
    if (\initial ) begin end
    _0921_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_wrdata_en <= _0921_;
  end
  always @* begin
    if (\initial ) begin end
    _0210_ = 1'h0;
    (* src = "ls180.v:3588.2-3601.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0210_ = sdram_bankmachine0_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0210_ = sdram_bankmachine1_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0210_ = sdram_bankmachine2_cmd_payload_is_write;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0210_ = sdram_bankmachine3_cmd_payload_is_write;
    endcase
  end
  always @* begin
      rhs_array_muxed10 <= _0210_;
  end
  always @* begin
    if (\initial ) begin end
    _0919_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_dfi_p0_rddata_en <= _0919_;
  end
  always @* begin
    if (\initial ) begin end
    _0211_ = 1'h0;
    (* src = "ls180.v:3605.2-3618.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0211_ = sdram_bankmachine0_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0211_ = sdram_bankmachine1_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0211_ = sdram_bankmachine2_cmd_payload_is_cmd;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0211_ = sdram_bankmachine3_cmd_payload_is_cmd;
    endcase
  end
  always @* begin
      rhs_array_muxed11 <= _0211_;
  end
  always @* begin
    if (\initial ) begin end
    _0513_ = 1'h0;
    (* src = "ls180.v:3622.2-3635.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0513_ = sdram_bankmachine0_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0513_ = sdram_bankmachine1_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0513_ = sdram_bankmachine2_cmd_payload_cas;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0513_ = sdram_bankmachine3_cmd_payload_cas;
    endcase
  end
  always @* begin
      t_array_muxed3 <= _0513_;
  end
  always @* begin
    if (\initial ) begin end
    _0911_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_valid <= _0911_;
  end
  always @* begin
    if (\initial ) begin end
    _0514_ = 1'h0;
    (* src = "ls180.v:3639.2-3652.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0514_ = sdram_bankmachine0_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0514_ = sdram_bankmachine1_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0514_ = sdram_bankmachine2_cmd_payload_ras;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0514_ = sdram_bankmachine3_cmd_payload_ras;
    endcase
  end
  always @* begin
      t_array_muxed4 <= _0514_;
  end
  always @* begin
    if (\initial ) begin end
    _0910_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_ready <= _0910_;
  end
  always @* begin
    if (\initial ) begin end
    _0904_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_last <= _0904_;
  end
  always @* begin
    if (\initial ) begin end
    _0515_ = 1'h0;
    (* src = "ls180.v:3656.2-3669.9" *)
    casez (sdram_choose_req_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0515_ = sdram_bankmachine0_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0515_ = sdram_bankmachine1_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0515_ = sdram_bankmachine2_cmd_payload_we;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0515_ = sdram_bankmachine3_cmd_payload_we;
    endcase
  end
  always @* begin
      t_array_muxed5 <= _0515_;
  end
  always @* begin
    if (\initial ) begin end
    _0905_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_payload_a <= _0905_;
  end
  always @* begin
    if (\initial ) begin end
    _0906_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_payload_ba <= _0906_;
  end
  always @* begin
    if (\initial ) begin end
    _0212_ = 22'h000000;
    (* src = "ls180.v:3673.2-3677.9" *)
    casez (subfragments_roundrobin0_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0212_ = { port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0] };
    endcase
  end
  always @* begin
      rhs_array_muxed12 <= _0212_;
  end
  always @* begin
    if (\initial ) begin end
    _0213_ = 1'h0;
    (* src = "ls180.v:3681.2-3685.9" *)
    casez (subfragments_roundrobin0_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0213_ = port_cmd_payload_we;
    endcase
  end
  always @* begin
      rhs_array_muxed13 <= _0213_;
  end
  always @* begin
    if (\initial ) begin end
    _0907_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_payload_cas <= _0907_;
  end
  always @* begin
    if (\initial ) begin end
    _0214_ = 1'h0;
    (* src = "ls180.v:3689.2-3693.9" *)
    casez (subfragments_roundrobin0_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0214_ = _1548_;
    endcase
  end
  always @* begin
      rhs_array_muxed14 <= _0214_;
  end
  always @* begin
    if (\initial ) begin end
    _0908_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_payload_ras <= _0908_;
  end
  always @* begin
    if (\initial ) begin end
    _0215_ = 22'h000000;
    (* src = "ls180.v:3697.2-3701.9" *)
    casez (subfragments_roundrobin1_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0215_ = { port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0] };
    endcase
  end
  always @* begin
      rhs_array_muxed15 <= _0215_;
  end
  always @* begin
    if (\initial ) begin end
    _0909_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_cmd_payload_we <= _0909_;
  end
  always @* begin
    if (\initial ) begin end
    _0216_ = 1'h0;
    (* src = "ls180.v:3705.2-3709.9" *)
    casez (subfragments_roundrobin1_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0216_ = port_cmd_payload_we;
    endcase
  end
  always @* begin
      rhs_array_muxed16 <= _0216_;
  end
  always @* begin
    if (\initial ) begin end
    _0413_ = 1'h0;
  end
  always @* begin
      sdram_cmd_payload_is_read <= _0413_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0217_ = 1'h0;
    (* src = "ls180.v:3713.2-3717.9" *)
    casez (subfragments_roundrobin1_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0217_ = _1553_;
    endcase
  end
  always @* begin
      rhs_array_muxed17 <= _0217_;
  end
  always @* begin
    if (\initial ) begin end
    _0218_ = 22'h000000;
    (* src = "ls180.v:3721.2-3725.9" *)
    casez (subfragments_roundrobin2_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0218_ = { port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0] };
    endcase
  end
  always @* begin
      rhs_array_muxed18 <= _0218_;
  end
  always @* begin
    if (\initial ) begin end
    _0414_ = 1'h0;
  end
  always @* begin
      sdram_cmd_payload_is_write <= _0414_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0219_ = 1'h0;
    (* src = "ls180.v:3729.2-3733.9" *)
    casez (subfragments_roundrobin2_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0219_ = port_cmd_payload_we;
    endcase
  end
  always @* begin
      rhs_array_muxed19 <= _0219_;
  end
  always @* begin
    if (\initial ) begin end
    _0221_ = 1'h0;
    (* src = "ls180.v:3737.2-3741.9" *)
    casez (subfragments_roundrobin2_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0221_ = _1558_;
    endcase
  end
  always @* begin
      rhs_array_muxed20 <= _0221_;
  end
  always @* begin
    if (\initial ) begin end
    _0222_ = 22'h000000;
    (* src = "ls180.v:3745.2-3749.9" *)
    casez (subfragments_roundrobin3_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0222_ = { port_cmd_payload_addr[23:11], port_cmd_payload_addr[8:0] };
    endcase
  end
  always @* begin
      rhs_array_muxed21 <= _0222_;
  end
  always @* begin
    if (\initial ) begin end
    _0223_ = 1'h0;
    (* src = "ls180.v:3753.2-3757.9" *)
    casez (subfragments_roundrobin3_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0223_ = port_cmd_payload_we;
    endcase
  end
  always @* begin
      rhs_array_muxed22 <= _0223_;
  end
  always @* begin
    if (\initial ) begin end
    _0224_ = 1'h0;
    (* src = "ls180.v:3761.2-3765.9" *)
    casez (subfragments_roundrobin3_grant)
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0224_ = _1563_;
    endcase
  end
  always @* begin
      rhs_array_muxed23 <= _0224_;
  end
  always @* begin
    if (\initial ) begin end
    _0225_ = 30'h00000000;
    (* src = "ls180.v:3769.2-3779.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0225_ = libresocsim_interface0_converted_interface_adr;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0225_ = libresocsim_interface1_converted_interface_adr;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0225_ = libresocsim_libresoc_jtag_wb_adr;
    endcase
  end
  always @* begin
      rhs_array_muxed24 <= _0225_;
  end
  always @* begin
    if (\initial ) begin end
    _0962_ = 10'h30d;
  end
  always @* begin
  end
  initial begin
      sdram_timer_count1 <= _0962_;
  end
  always @* begin
    if (\initial ) begin end
    _0226_ = 32'd0;
    (* src = "ls180.v:3783.2-3793.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0226_ = libresocsim_interface0_converted_interface_dat_w;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0226_ = libresocsim_interface1_converted_interface_dat_w;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0226_ = libresocsim_libresoc_jtag_wb_dat_w;
    endcase
  end
  always @* begin
      rhs_array_muxed25 <= _0226_;
  end
  always @* begin
    if (\initial ) begin end
    _0227_ = 4'h0;
    (* src = "ls180.v:3797.2-3807.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0227_ = libresocsim_interface0_converted_interface_sel;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0227_ = libresocsim_interface1_converted_interface_sel;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0227_ = libresocsim_libresoc_jtag_wb_sel;
    endcase
  end
  always @* begin
      rhs_array_muxed26 <= _0227_;
  end
  always @* begin
    if (\initial ) begin end
    _0947_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_postponer_req_o <= _0947_;
  end
  always @* begin
    if (\initial ) begin end
    _0228_ = 1'h0;
    (* src = "ls180.v:3811.2-3821.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0228_ = libresocsim_interface0_converted_interface_cyc;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0228_ = libresocsim_interface1_converted_interface_cyc;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0228_ = libresocsim_libresoc_jtag_wb_cyc;
    endcase
  end
  always @* begin
      rhs_array_muxed27 <= _0228_;
  end
  always @* begin
    if (\initial ) begin end
    _0946_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_postponer_count <= _0946_;
  end
  always @* begin
    if (\initial ) begin end
    _0952_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_sequencer_start0 <= _0952_;
  end
  always @* begin
    if (\initial ) begin end
    _0229_ = 1'h0;
    (* src = "ls180.v:3825.2-3835.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0229_ = libresocsim_interface0_converted_interface_stb;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0229_ = libresocsim_interface1_converted_interface_stb;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0229_ = libresocsim_libresoc_jtag_wb_stb;
    endcase
  end
  always @* begin
      rhs_array_muxed28 <= _0229_;
  end
  always @* begin
    if (\initial ) begin end
    _0230_ = 1'h0;
    (* src = "ls180.v:3839.2-3849.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0230_ = libresocsim_interface0_converted_interface_we;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0230_ = libresocsim_interface1_converted_interface_we;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0230_ = libresocsim_libresoc_jtag_wb_we;
    endcase
  end
  always @* begin
      rhs_array_muxed29 <= _0230_;
  end
  always @* begin
    if (\initial ) begin end
    _0951_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_sequencer_done1 <= _0951_;
  end
  always @* begin
    if (\initial ) begin end
    _0232_ = 3'h0;
    (* src = "ls180.v:3853.2-3863.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0232_ = libresocsim_interface0_converted_interface_cti;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0232_ = libresocsim_interface1_converted_interface_cti;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0232_ = libresocsim_libresoc_jtag_wb_cti;
    endcase
  end
  always @* begin
      rhs_array_muxed30 <= _0232_;
  end
  always @* begin
    if (\initial ) begin end
    _0950_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_sequencer_counter <= _0950_;
  end
  always @* begin
    if (\initial ) begin end
    _0233_ = 2'h0;
    (* src = "ls180.v:3867.2-3877.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0233_ = libresocsim_interface0_converted_interface_bte;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0233_ = libresocsim_interface1_converted_interface_bte;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0233_ = libresocsim_libresoc_jtag_wb_bte;
    endcase
  end
  always @* begin
      rhs_array_muxed31 <= _0233_;
  end
  always @* begin
    if (\initial ) begin end
    _0949_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_sequencer_count <= _0949_;
  end
  always @* begin
    if (\initial ) begin end
    _0042_ = 2'h0;
    (* src = "ls180.v:3881.2-3894.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0042_ = sdram_nop_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0042_ = sdram_choose_req_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0042_ = sdram_choose_req_cmd_payload_ba;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0042_ = sdram_cmd_payload_ba;
    endcase
  end
  always @* begin
      array_muxed0 <= _0042_;
  end
  always @* begin
    if (\initial ) begin end
    _0043_ = 13'h0000;
    (* src = "ls180.v:3898.2-3911.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0043_ = sdram_nop_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0043_ = sdram_choose_req_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0043_ = sdram_choose_req_cmd_payload_a;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0043_ = sdram_cmd_payload_a;
    endcase
  end
  always @* begin
      array_muxed1 <= _0043_;
  end
  always @* begin
    if (\initial ) begin end
    _0044_ = 1'h0;
    (* src = "ls180.v:3915.2-3928.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0044_ = 1'h0;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0044_ = _1565_;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0044_ = _1567_;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0044_ = _1569_;
    endcase
  end
  always @* begin
      array_muxed2 <= _0044_;
  end
  always @* begin
    if (\initial ) begin end
    _0795_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_req_wdata_ready <= _0795_;
  end
  always @* begin
    if (\initial ) begin end
    _0045_ = 1'h0;
    (* src = "ls180.v:3932.2-3945.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0045_ = 1'h0;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0045_ = _1571_;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0045_ = _1573_;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0045_ = _1575_;
    endcase
  end
  always @* begin
      array_muxed3 <= _0045_;
  end
  always @* begin
    if (\initial ) begin end
    _0794_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_req_rdata_valid <= _0794_;
  end
  always @* begin
    if (\initial ) begin end
    _0046_ = 1'h0;
    (* src = "ls180.v:3949.2-3962.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0046_ = 1'h0;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0046_ = _1577_;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0046_ = _1579_;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0046_ = _1581_;
    endcase
  end
  always @* begin
      array_muxed4 <= _0046_;
  end
  always @* begin
    if (\initial ) begin end
    _0793_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_refresh_gnt <= _0793_;
  end
  always @* begin
    if (\initial ) begin end
    _0047_ = 1'h0;
    (* src = "ls180.v:3966.2-3979.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0047_ = 1'h0;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0047_ = _1583_;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0047_ = _1585_;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0047_ = _1587_;
    endcase
  end
  always @* begin
      array_muxed5 <= _0047_;
  end
  always @* begin
    if (\initial ) begin end
    _0792_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_valid <= _0792_;
  end
  always @* begin
    if (\initial ) begin end
    _0791_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_ready <= _0791_;
  end
  always @* begin
    if (\initial ) begin end
    _0048_ = 1'h0;
    (* src = "ls180.v:3983.2-3996.9" *)
    casez (sdram_steerer_sel)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          _0048_ = 1'h0;
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          _0048_ = _1589_;
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          _0048_ = _1591_;
      /* src = "ls180.v:0.0-0.0" */
      default:
          _0048_ = _1593_;
    endcase
  end
  always @* begin
      array_muxed6 <= _0048_;
  end
  always @* begin
    if (\initial ) begin end
    _0784_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_a <= _0784_;
  end
  always @* begin
    if (\initial ) begin end
    _0785_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_cas <= _0785_;
  end
  always @* begin
    if (\initial ) begin end
    _0789_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_ras <= _0789_;
  end
  always @* begin
    if (\initial ) begin end
    _0790_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_we <= _0790_;
  end
  always @* begin
    if (\initial ) begin end
    _0786_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_is_cmd <= _0786_;
  end
  always @* begin
    if (\initial ) begin end
    _0787_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_is_read <= _0787_;
  end
  always @* begin
    if (\initial ) begin end
    _0788_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_payload_is_write <= _0788_;
  end
  always @* begin
    if (\initial ) begin end
    _0774_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_auto_precharge <= _0774_;
  end
  always @* begin
    if (\initial ) begin end
    _0259_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine0_cmd_buffer_lookahead_sink_first <= _0259_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0260_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine0_cmd_buffer_lookahead_sink_last <= _0260_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0081_ = sys_rst;
  end
  always @(posedge por_clk) begin
      int_rst <= _0081_;
  end
  always @* begin
    if (\initial ) begin end
    _0127_[0] = dfi_p0_address[0];
    _0127_[1] = dfi_p0_address[1];
    _0127_[2] = dfi_p0_address[2];
    _0127_[3] = dfi_p0_address[3];
    _0127_[4] = dfi_p0_address[4];
    _0127_[5] = dfi_p0_address[5];
    _0127_[6] = dfi_p0_address[6];
    _0127_[7] = dfi_p0_address[7];
    _0127_[8] = dfi_p0_address[8];
    _0127_[9] = dfi_p0_address[9];
    _0127_[10] = dfi_p0_address[10];
    _0127_[11] = dfi_p0_address[11];
    _0127_[12] = dfi_p0_address[12];
    _0128_[0] = dfi_p0_bank[0];
    _0128_[1] = dfi_p0_bank[1];
    _0129_ = dfi_p0_cas_n;
    _0136_ = dfi_p0_ras_n;
    _0137_ = dfi_p0_we_n;
    _0130_ = dfi_p0_cke;
    _0132_ = dfi_p0_cs_n;
    _0135_[0] = dfi_p0_wrdata_en;
    _0134_[0] = dfi_p0_wrdata[0];
    _0055_[0] = libresocsim_libresoc_constraintmanager_sdram_dq_i[0];
    _0135_[1] = dfi_p0_wrdata_en;
    _0134_[1] = dfi_p0_wrdata[1];
    _0055_[1] = libresocsim_libresoc_constraintmanager_sdram_dq_i[1];
    _0135_[2] = dfi_p0_wrdata_en;
    _0134_[2] = dfi_p0_wrdata[2];
    _0055_[2] = libresocsim_libresoc_constraintmanager_sdram_dq_i[2];
    _0135_[3] = dfi_p0_wrdata_en;
    _0134_[3] = dfi_p0_wrdata[3];
    _0055_[3] = libresocsim_libresoc_constraintmanager_sdram_dq_i[3];
    _0135_[4] = dfi_p0_wrdata_en;
    _0134_[4] = dfi_p0_wrdata[4];
    _0055_[4] = libresocsim_libresoc_constraintmanager_sdram_dq_i[4];
    _0135_[5] = dfi_p0_wrdata_en;
    _0134_[5] = dfi_p0_wrdata[5];
    _0055_[5] = libresocsim_libresoc_constraintmanager_sdram_dq_i[5];
    _0135_[6] = dfi_p0_wrdata_en;
    _0134_[6] = dfi_p0_wrdata[6];
    _0055_[6] = libresocsim_libresoc_constraintmanager_sdram_dq_i[6];
    _0135_[7] = dfi_p0_wrdata_en;
    _0134_[7] = dfi_p0_wrdata[7];
    _0055_[7] = libresocsim_libresoc_constraintmanager_sdram_dq_i[7];
    _0135_[8] = dfi_p0_wrdata_en;
    _0134_[8] = dfi_p0_wrdata[8];
    _0055_[8] = libresocsim_libresoc_constraintmanager_sdram_dq_i[8];
    _0135_[9] = dfi_p0_wrdata_en;
    _0134_[9] = dfi_p0_wrdata[9];
    _0055_[9] = libresocsim_libresoc_constraintmanager_sdram_dq_i[9];
    _0135_[10] = dfi_p0_wrdata_en;
    _0134_[10] = dfi_p0_wrdata[10];
    _0055_[10] = libresocsim_libresoc_constraintmanager_sdram_dq_i[10];
    _0135_[11] = dfi_p0_wrdata_en;
    _0134_[11] = dfi_p0_wrdata[11];
    _0055_[11] = libresocsim_libresoc_constraintmanager_sdram_dq_i[11];
    _0135_[12] = dfi_p0_wrdata_en;
    _0134_[12] = dfi_p0_wrdata[12];
    _0055_[12] = libresocsim_libresoc_constraintmanager_sdram_dq_i[12];
    _0135_[13] = dfi_p0_wrdata_en;
    _0134_[13] = dfi_p0_wrdata[13];
    _0055_[13] = libresocsim_libresoc_constraintmanager_sdram_dq_i[13];
    _0135_[14] = dfi_p0_wrdata_en;
    _0134_[14] = dfi_p0_wrdata[14];
    _0055_[14] = libresocsim_libresoc_constraintmanager_sdram_dq_i[14];
    _0135_[15] = dfi_p0_wrdata_en;
    _0134_[15] = dfi_p0_wrdata[15];
    _0055_[15] = libresocsim_libresoc_constraintmanager_sdram_dq_i[15];
    _0133_[0] = _1594_;
    _0133_[1] = _1595_;
    _0131_ = sys_clk_1;
    _0069_[0] = gpio0_oe_storage[0];
    _0068_[0] = gpio0_out_storage[0];
    _0070_[0] = gpio0_pads_gpio0i[0];
    _0069_[1] = gpio0_oe_storage[1];
    _0068_[1] = gpio0_out_storage[1];
    _0070_[1] = gpio0_pads_gpio0i[1];
    _0069_[2] = gpio0_oe_storage[2];
    _0068_[2] = gpio0_out_storage[2];
    _0070_[2] = gpio0_pads_gpio0i[2];
    _0069_[3] = gpio0_oe_storage[3];
    _0068_[3] = gpio0_out_storage[3];
    _0070_[3] = gpio0_pads_gpio0i[3];
    _0069_[4] = gpio0_oe_storage[4];
    _0068_[4] = gpio0_out_storage[4];
    _0070_[4] = gpio0_pads_gpio0i[4];
    _0069_[5] = gpio0_oe_storage[5];
    _0068_[5] = gpio0_out_storage[5];
    _0070_[5] = gpio0_pads_gpio0i[5];
    _0069_[6] = gpio0_oe_storage[6];
    _0068_[6] = gpio0_out_storage[6];
    _0070_[6] = gpio0_pads_gpio0i[6];
    _0069_[7] = gpio0_oe_storage[7];
    _0068_[7] = gpio0_out_storage[7];
    _0070_[7] = gpio0_pads_gpio0i[7];
    _0077_[0] = gpio1_oe_storage[0];
    _0076_[0] = gpio1_out_storage[0];
    _0078_[0] = gpio1_pads_gpio1i[0];
    _0077_[1] = gpio1_oe_storage[1];
    _0076_[1] = gpio1_out_storage[1];
    _0078_[1] = gpio1_pads_gpio1i[1];
    _0077_[2] = gpio1_oe_storage[2];
    _0076_[2] = gpio1_out_storage[2];
    _0078_[2] = gpio1_pads_gpio1i[2];
    _0077_[3] = gpio1_oe_storage[3];
    _0076_[3] = gpio1_out_storage[3];
    _0078_[3] = gpio1_pads_gpio1i[3];
    _0077_[4] = gpio1_oe_storage[4];
    _0076_[4] = gpio1_out_storage[4];
    _0078_[4] = gpio1_pads_gpio1i[4];
    _0077_[5] = gpio1_oe_storage[5];
    _0076_[5] = gpio1_out_storage[5];
    _0078_[5] = gpio1_pads_gpio1i[5];
    _0077_[6] = gpio1_oe_storage[6];
    _0076_[6] = gpio1_out_storage[6];
    _0078_[6] = gpio1_pads_gpio1i[6];
    _0077_[7] = gpio1_oe_storage[7];
    _0076_[7] = gpio1_out_storage[7];
    _0078_[7] = gpio1_pads_gpio1i[7];
  end
  always @(posedge sdrio_clk) begin
      libresocsim_libresoc_constraintmanager_sdram_a <= _0127_;
      libresocsim_libresoc_constraintmanager_sdram_dq_o <= _0134_;
      libresocsim_libresoc_constraintmanager_sdram_dq_oe <= _0135_;
      libresocsim_libresoc_constraintmanager_sdram_we_n <= _0137_;
      libresocsim_libresoc_constraintmanager_sdram_ras_n <= _0136_;
      libresocsim_libresoc_constraintmanager_sdram_cas_n <= _0129_;
      libresocsim_libresoc_constraintmanager_sdram_cs_n <= _0132_;
      libresocsim_libresoc_constraintmanager_sdram_cke <= _0130_;
      libresocsim_libresoc_constraintmanager_sdram_ba <= _0128_;
      libresocsim_libresoc_constraintmanager_sdram_dm <= _0133_;
      libresocsim_libresoc_constraintmanager_sdram_clock <= _0131_;
      dfi_p0_rddata <= _0055_;
      gpio0_status <= _0070_;
      gpio0_pads_gpio0o <= _0068_;
      gpio0_pads_gpio0oe <= _0069_;
      gpio1_status <= _0078_;
      gpio1_pads_gpio1o <= _0076_;
      gpio1_pads_gpio1oe <= _0077_;
  end
  always @* begin
    if (\initial ) begin end
    _0703_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_reset_storage <= _0703_;
  end
  always @* begin
    if (\initial ) begin end
    _0170_ = libresocsim_reset_storage;
    _0172_ = libresocsim_scratch_storage;
    _0082_ = libresocsim_bus_errors;
    _0142_ = libresocsim_libresoc_constraintmanager_uart_tx;
    _0083_ = libresocsim_converter0_counter;
    _0086_ = libresocsim_converter0_dat_r;
    _0088_ = libresocsim_converter1_counter;
    _0091_ = libresocsim_converter1_dat_r;
    _0163_ = libresocsim_load_storage;
    _0168_ = libresocsim_reload_storage;
    _0095_ = libresocsim_en_storage;
    _0179_ = libresocsim_update_value_storage;
    _0181_ = libresocsim_value_status;
    _0185_ = libresocsim_zero_pending;
    _0098_ = libresocsim_eventmanager_storage;
    _0180_ = libresocsim_value;
    _0471_ = sdram_storage;
    _0421_ = sdram_command_storage;
    _0251_ = sdram_address_storage;
    _0253_ = sdram_baddress_storage;
    _0482_ = sdram_wrdata_storage;
    _0467_ = sdram_status;
    _0477_ = sdram_timer_count1;
    _0458_ = sdram_postponer_count;
    _0462_ = sdram_sequencer_counter;
    _0461_ = sdram_sequencer_count;
    _0256_ = sdram_bankmachine0_cmd_buffer_lookahead_level;
    _0257_ = sdram_bankmachine0_cmd_buffer_lookahead_produce;
    _0255_ = sdram_bankmachine0_cmd_buffer_lookahead_consume;
    _0266_ = sdram_bankmachine0_cmd_buffer_source_valid;
    _0262_ = sdram_bankmachine0_cmd_buffer_source_first;
    _0263_ = sdram_bankmachine0_cmd_buffer_source_last;
    _0265_ = sdram_bankmachine0_cmd_buffer_source_payload_we;
    _0264_ = sdram_bankmachine0_cmd_buffer_source_payload_addr;
    _0279_ = sdram_bankmachine0_row;
    _0283_ = sdram_bankmachine0_row_opened;
    _0287_ = sdram_bankmachine0_twtpcon_ready;
    _0286_ = sdram_bankmachine0_twtpcon_count;
    _0290_ = sdram_bankmachine1_cmd_buffer_lookahead_level;
    _0291_ = sdram_bankmachine1_cmd_buffer_lookahead_produce;
    _0289_ = sdram_bankmachine1_cmd_buffer_lookahead_consume;
    _0300_ = sdram_bankmachine1_cmd_buffer_source_valid;
    _0296_ = sdram_bankmachine1_cmd_buffer_source_first;
    _0297_ = sdram_bankmachine1_cmd_buffer_source_last;
    _0299_ = sdram_bankmachine1_cmd_buffer_source_payload_we;
    _0298_ = sdram_bankmachine1_cmd_buffer_source_payload_addr;
    _0313_ = sdram_bankmachine1_row;
    _0317_ = sdram_bankmachine1_row_opened;
    _0321_ = sdram_bankmachine1_twtpcon_ready;
    _0320_ = sdram_bankmachine1_twtpcon_count;
    _0324_ = sdram_bankmachine2_cmd_buffer_lookahead_level;
    _0325_ = sdram_bankmachine2_cmd_buffer_lookahead_produce;
    _0323_ = sdram_bankmachine2_cmd_buffer_lookahead_consume;
    _0334_ = sdram_bankmachine2_cmd_buffer_source_valid;
    _0330_ = sdram_bankmachine2_cmd_buffer_source_first;
    _0331_ = sdram_bankmachine2_cmd_buffer_source_last;
    _0333_ = sdram_bankmachine2_cmd_buffer_source_payload_we;
    _0332_ = sdram_bankmachine2_cmd_buffer_source_payload_addr;
    _0347_ = sdram_bankmachine2_row;
    _0351_ = sdram_bankmachine2_row_opened;
    _0355_ = sdram_bankmachine2_twtpcon_ready;
    _0354_ = sdram_bankmachine2_twtpcon_count;
    _0358_ = sdram_bankmachine3_cmd_buffer_lookahead_level;
    _0359_ = sdram_bankmachine3_cmd_buffer_lookahead_produce;
    _0357_ = sdram_bankmachine3_cmd_buffer_lookahead_consume;
    _0368_ = sdram_bankmachine3_cmd_buffer_source_valid;
    _0364_ = sdram_bankmachine3_cmd_buffer_source_first;
    _0365_ = sdram_bankmachine3_cmd_buffer_source_last;
    _0367_ = sdram_bankmachine3_cmd_buffer_source_payload_we;
    _0366_ = sdram_bankmachine3_cmd_buffer_source_payload_addr;
    _0381_ = sdram_bankmachine3_row;
    _0385_ = sdram_bankmachine3_row_opened;
    _0389_ = sdram_bankmachine3_twtpcon_ready;
    _0388_ = sdram_bankmachine3_twtpcon_count;
    _0394_ = sdram_choose_cmd_grant;
    _0404_ = sdram_choose_req_grant;
    _0473_ = sdram_tccdcon_ready;
    _0472_ = sdram_tccdcon_count;
    _0480_ = sdram_twtrcon_ready;
    _0479_ = sdram_twtrcon_count;
    _0475_ = sdram_time0;
    _0476_ = sdram_time1;
    _0050_ = converter_counter;
    _0053_ = converter_dat_r;
    _0049_ = cmd_consumed;
    _0547_ = wdata_consumed;
    _0539_ = uart_phy_storage;
    _0544_ = uart_phy_uart_clk_txen;
    _0528_ = uart_phy_phase_accumulator_tx;
    _0542_ = uart_phy_tx_reg;
    _0540_ = uart_phy_tx_bitcount;
    _0541_ = uart_phy_tx_busy;
    _0537_ = uart_phy_source_payload_data;
    _0543_ = uart_phy_uart_clk_rxen;
    _0527_ = uart_phy_phase_accumulator_rx;
    _0533_ = uart_phy_rx_reg;
    _0530_ = uart_phy_rx_bitcount;
    _0531_ = uart_phy_rx_busy;
    _0526_ = tx_pending;
    _0249_ = rx_pending;
    _0062_ = eventmanager_storage;
    _0520_ = tx_fifo_readable;
    _0518_ = tx_fifo_level0;
    _0519_ = tx_fifo_produce;
    _0517_ = tx_fifo_consume;
    _0245_ = rx_fifo_readable;
    _0243_ = rx_fifo_level0;
    _0244_ = rx_fifo_produce;
    _0242_ = rx_fifo_consume;
    _0064_ = gpio0_oe_storage;
    _0066_ = gpio0_out_storage;
    _0072_ = gpio1_oe_storage;
    _0074_ = gpio1_out_storage;
    _0080_ = i2c_storage;
    _0150_ = libresocsim_libresocsim_adr;
    _0156_ = libresocsim_libresocsim_we;
    _0153_ = libresocsim_libresocsim_dat_w;
    _0099_ = libresocsim_grant;
    _0093_ = libresocsim_count;
    _0057_[0] = _2299_;
    _0057_[1] = _2300_;
    _0057_[2] = _2301_;
    _0057_[3] = _2302_;
    _0057_[4] = _2303_;
    _0057_[5] = _2304_;
    _0057_[6] = _2305_;
    _0057_[7] = _2306_;
    _0057_[8] = _2307_;
    _0057_[9] = _2308_;
    _0057_[10] = _2309_;
    _0057_[11] = _2310_;
    _0057_[12] = _2311_;
    _0057_[13] = _2312_;
    _0057_[14] = _2313_;
    _0057_[15] = _2314_;
    _0057_[16] = _2315_;
    _0057_[17] = _2316_;
    _0057_[18] = _2317_;
    _0057_[19] = _2318_;
    _0057_[20] = _2319_;
    _0057_[21] = _2320_;
    _0057_[22] = _2321_;
    _0057_[23] = _2322_;
    _0057_[24] = _2323_;
    _0057_[25] = _2324_;
    _0057_[26] = _2325_;
    _0057_[27] = _2326_;
    _0057_[28] = _2327_;
    _0057_[29] = _2328_;
    _0057_[30] = _2329_;
    _0057_[31] = _2330_;
    _0057_[32] = _2331_;
    _0057_[33] = _2332_;
    _0057_[34] = _2333_;
    _0057_[35] = _2334_;
    _0057_[36] = _2335_;
    _0057_[37] = _2336_;
    _0057_[38] = _2337_;
    _0057_[39] = _2338_;
    _0492_ = subfragments_converter0_next_state;
    _0494_ = subfragments_converter1_next_state;
    _0165_ = 1'h0;
    _0184_ = libresocsim_zero_trigger;
    _0202_ = 1'h0;
    _0205_ = { rddata_en[1:0], dfi_p0_rddata_en };
    _0056_ = rddata_en[2];
    _0459_ = 1'h0;
    _0410_ = 13'h0000;
    _0411_ = 2'h0;
    _0412_ = 1'h0;
    _0415_ = 1'h0;
    _0416_ = 1'h0;
    _0463_ = 1'h0;
    _0508_ = subfragments_refresher_next_state;
    _0484_ = subfragments_bankmachine0_next_state;
    _0486_ = subfragments_bankmachine1_next_state;
    _0488_ = subfragments_bankmachine2_next_state;
    _0490_ = subfragments_bankmachine3_next_state;
    _0426_ = 1'h0;
    _0424_ = array_muxed0;
    _0423_ = array_muxed1;
    _0425_ = _2152_;
    _0427_ = _2153_;
    _0429_ = _2154_;
    _0428_ = array_muxed5;
    _0430_ = array_muxed6;
    _0500_ = subfragments_multiplexer_next_state;
    _0505_ = _2348_;
    _0501_ = _2352_;
    _0502_ = subfragments_new_master_rdata_valid0;
    _0503_ = subfragments_new_master_rdata_valid1;
    _0504_ = subfragments_new_master_rdata_valid2;
    _0509_ = subfragments_next_state;
    _0534_ = 1'h0;
    _0538_ = 1'h0;
    _0532_ = uart_phy_rx;
    _0525_ = tx_trigger;
    _0248_ = rx_trigger;
    _0177_ = libresocsim_next_state;
    _0176_ = libresocsim_slave_sel;
    _0100_ = 8'h00;
    _0169_ = libresocsim_csrbank0_reset0_re;
    _0171_ = libresocsim_csrbank0_scratch0_re;
    _0109_ = 8'h00;
    _0063_ = libresocsim_csrbank1_oe0_re;
    _0065_ = libresocsim_csrbank1_out0_re;
    _0118_ = 8'h00;
    _0071_ = libresocsim_csrbank2_oe0_re;
    _0073_ = libresocsim_csrbank2_out0_re;
    _0119_ = 8'h00;
    _0079_ = libresocsim_csrbank3_w0_re;
    _0120_ = 8'h00;
    _0460_ = libresocsim_csrbank4_dfii_control0_re;
    _0420_ = libresocsim_csrbank4_dfii_pi0_command0_re;
    _0250_ = libresocsim_csrbank4_dfii_pi0_address0_re;
    _0252_ = libresocsim_csrbank4_dfii_pi0_baddress0_re;
    _0481_ = libresocsim_csrbank4_dfii_pi0_wrdata0_re;
    _0121_ = 8'h00;
    _0162_ = libresocsim_csrbank5_load0_re;
    _0167_ = libresocsim_csrbank5_reload0_re;
    _0094_ = libresocsim_csrbank5_en0_re;
    _0178_ = libresocsim_csrbank5_update_value0_re;
    _0097_ = libresocsim_csrbank5_ev_enable0_re;
    _0122_ = 8'h00;
    _0060_ = libresocsim_csrbank6_ev_enable0_re;
    _0123_ = 8'h00;
    _0529_ = libresocsim_csrbank7_tuning_word0_re;
    _0206_ = libresocsim_libresoc_constraintmanager_uart_rx;
    _0207_ = regs0;
    (* src = "ls180.v:4286.2-4288.5" *)
    casez (_2339_)
      /* src = "ls180.v:4286.6-4286.84" */
      1'h1:
          _0086_ = libresocsim_libresoc_ibus_dat_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4290.2-4292.5" *)
    casez (libresocsim_converter0_counter_subfragments_converter0_next_value_ce)
      /* src = "ls180.v:4290.6-4290.74" */
      1'h1:
          _0083_ = libresocsim_converter0_counter_subfragments_converter0_next_value;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4293.2-4296.5" *)
    casez (libresocsim_converter0_reset)
      /* src = "ls180.v:4293.6-4293.34" */
      1'h1:
        begin
          _0083_ = 1'h0;
          _0492_ = 1'h0;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4297.2-4299.5" *)
    casez (_2340_)
      /* src = "ls180.v:4297.6-4297.84" */
      1'h1:
          _0091_ = libresocsim_libresoc_dbus_dat_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4301.2-4303.5" *)
    casez (libresocsim_converter1_counter_subfragments_converter1_next_value_ce)
      /* src = "ls180.v:4301.6-4301.74" */
      1'h1:
          _0088_ = libresocsim_converter1_counter_subfragments_converter1_next_value;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4304.2-4307.5" *)
    casez (libresocsim_converter1_reset)
      /* src = "ls180.v:4304.6-4304.34" */
      1'h1:
        begin
          _0088_ = 1'h0;
          _0494_ = 1'h0;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4308.2-4312.5" *)
    casez (_1969_)
      /* src = "ls180.v:4308.6-4308.48" */
      1'h1:
          (* src = "ls180.v:4309.3-4311.6" *)
          casez (libresocsim_bus_error)
            /* src = "ls180.v:4309.7-4309.28" */
            1'h1:
                _0082_ = _1027_;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4314.2-4316.5" *)
    casez (_1597_)
      /* src = "ls180.v:4314.6-4314.88" */
      1'h1:
          _0165_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4317.2-4325.5" *)
    casez (libresocsim_en_storage)
      /* src = "ls180.v:4317.6-4317.28" */
      1'h1:
          (* src = "ls180.v:4318.3-4322.6" *)
          casez (_1870_)
            /* src = "ls180.v:4318.7-4318.34" */
            1'h1:
                _0180_ = libresocsim_reload_storage;
            /* src = "ls180.v:4320.7-4320.11" */
            default:
                _0180_ = _2366_;
          endcase
      /* src = "ls180.v:4323.6-4323.10" */
      default:
          _0180_ = libresocsim_load_storage;
    endcase
    (* src = "ls180.v:4326.2-4328.5" *)
    casez (libresocsim_update_value_re)
      /* src = "ls180.v:4326.6-4326.33" */
      1'h1:
          _0181_ = libresocsim_value;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4329.2-4331.5" *)
    casez (libresocsim_zero_clear)
      /* src = "ls180.v:4329.6-4329.28" */
      1'h1:
          _0185_ = 1'h0;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4333.2-4335.5" *)
    casez (_1598_)
      /* src = "ls180.v:4333.6-4333.66" */
      1'h1:
          _0185_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4337.2-4339.5" *)
    casez (_1600_)
      /* src = "ls180.v:4337.6-4337.76" */
      1'h1:
          _0202_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4342.2-4344.5" *)
    casez (sdram_inti_p0_rddata_valid)
      /* src = "ls180.v:4342.6-4342.32" */
      1'h1:
          _0467_ = sdram_inti_p0_rddata;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4345.2-4349.5" *)
    casez (_1601_)
      /* src = "ls180.v:4345.6-4345.47" */
      1'h1:
          _0477_ = _2367_;
      /* src = "ls180.v:4347.6-4347.10" */
      default:
          _0477_ = 10'h30d;
    endcase
    (* src = "ls180.v:4351.2-4357.5" *)
    casez (sdram_postponer_req_i)
      /* src = "ls180.v:4351.6-4351.27" */
      1'h1:
        begin
          _0458_ = _2368_;
          (* src = "ls180.v:4353.3-4356.6" *)
          casez (_1871_)
            /* src = "ls180.v:4353.7-4353.38" */
            1'h1:
              begin
                _0458_ = 1'h0;
                _0459_ = 1'h1;
              end
            default:
                /* empty */;
          endcase
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4358.2-4366.5" *)
    casez (sdram_sequencer_start0)
      /* src = "ls180.v:4358.6-4358.28" */
      1'h1:
          _0461_ = 1'h0;
      /* src = "ls180.v:4360.6-4360.10" */
      default:
          (* src = "ls180.v:4361.3-4365.6" *)
          casez (sdram_sequencer_done1)
            /* src = "ls180.v:4361.7-4361.28" */
            1'h1:
                (* src = "ls180.v:4362.4-4364.7" *)
                casez (_1970_)
                  /* src = "ls180.v:4362.8-4362.39" */
                  1'h1:
                      _0461_ = _2369_;
                  default:
                      /* empty */;
                endcase
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4373.2-4379.5" *)
    casez (_1602_)
      /* src = "ls180.v:4373.6-4373.66" */
      1'h1:
        begin
          _0410_ = 13'h0400;
          _0411_ = 2'h0;
          _0412_ = 1'h0;
          _0415_ = 1'h1;
          _0416_ = 1'h1;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4380.2-4386.5" *)
    casez (_1873_)
      /* src = "ls180.v:4380.6-4380.39" */
      1'h1:
        begin
          _0410_ = 13'h0000;
          _0411_ = 2'h0;
          _0412_ = 1'h1;
          _0415_ = 1'h1;
          _0416_ = 1'h0;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4387.2-4394.5" *)
    casez (_1874_)
      /* src = "ls180.v:4387.6-4387.39" */
      1'h1:
        begin
          _0410_ = 13'h0000;
          _0411_ = 2'h0;
          _0412_ = 1'h0;
          _0415_ = 1'h0;
          _0416_ = 1'h0;
          _0463_ = 1'h1;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4395.2-4405.5" *)
    casez (_1875_)
      /* src = "ls180.v:4395.6-4395.39" */
      1'h1:
          _0462_ = 4'h0;
      /* src = "ls180.v:4397.6-4397.10" */
      default:
          (* src = "ls180.v:4398.3-4404.6" *)
          casez (_1971_)
            /* src = "ls180.v:4398.7-4398.40" */
            1'h1:
                _0462_ = _1028_;
            /* src = "ls180.v:4400.7-4400.11" */
            default:
                (* src = "ls180.v:4401.4-4403.7" *)
                casez (sdram_sequencer_start1)
                  /* src = "ls180.v:4401.8-4401.30" */
                  1'h1:
                      _0462_ = 4'h1;
                  default:
                      /* empty */;
                endcase
          endcase
    endcase
    (* src = "ls180.v:4407.2-4414.5" *)
    casez (sdram_bankmachine0_row_close)
      /* src = "ls180.v:4407.6-4407.34" */
      1'h1:
          _0283_ = 1'h0;
      /* src = "ls180.v:4409.6-4409.10" */
      default:
          (* src = "ls180.v:4410.3-4413.6" *)
          casez (sdram_bankmachine0_row_open)
            /* src = "ls180.v:4410.7-4410.34" */
            1'h1:
              begin
                _0283_ = 1'h1;
                _0279_ = sdram_bankmachine0_cmd_buffer_source_payload_addr[21:9];
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4415.2-4417.5" *)
    casez (_1604_)
      /* src = "ls180.v:4415.6-4415.176" */
      1'h1:
          _0257_ = _1029_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4418.2-4420.5" *)
    casez (sdram_bankmachine0_cmd_buffer_lookahead_do_read)
      /* src = "ls180.v:4418.6-4418.53" */
      1'h1:
          _0255_ = _1030_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4421.2-4429.5" *)
    casez (_1606_)
      /* src = "ls180.v:4421.6-4421.176" */
      1'h1:
          (* src = "ls180.v:4422.3-4424.6" *)
          casez (_2130_)
            /* src = "ls180.v:4422.7-4422.57" */
            1'h1:
                _0256_ = _1031_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4425.6-4425.10" */
      default:
          (* src = "ls180.v:4426.3-4428.6" *)
          casez (sdram_bankmachine0_cmd_buffer_lookahead_do_read)
            /* src = "ls180.v:4426.7-4426.54" */
            1'h1:
                _0256_ = _2370_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4430.2-4436.5" *)
    casez (_2341_)
      /* src = "ls180.v:4430.6-4430.98" */
      1'h1:
        begin
          _0266_ = sdram_bankmachine0_cmd_buffer_sink_valid;
          _0262_ = sdram_bankmachine0_cmd_buffer_sink_first;
          _0263_ = sdram_bankmachine0_cmd_buffer_sink_last;
          _0265_ = sdram_bankmachine0_cmd_buffer_sink_payload_we;
          _0264_ = sdram_bankmachine0_cmd_buffer_sink_payload_addr;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4437.2-4451.5" *)
    casez (sdram_bankmachine0_twtpcon_valid)
      /* src = "ls180.v:4437.6-4437.38" */
      1'h1:
        begin
          _0286_ = 3'h4;
          (* src = "ls180.v:4439.3-4443.6" *)
          casez (1'h0)
            /* src = "ls180.v:4441.7-4441.11" */
            default:
                _0287_ = 1'h0;
          endcase
        end
      /* src = "ls180.v:4444.6-4444.10" */
      default:
          (* src = "ls180.v:4445.3-4450.6" *)
          casez (_2132_)
            /* src = "ls180.v:4445.7-4445.42" */
            1'h1:
              begin
                _0286_ = _2371_;
                (* src = "ls180.v:4447.4-4449.7" *)
                casez (_1876_)
                  /* src = "ls180.v:4447.8-4447.50" */
                  1'h1:
                      _0287_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4453.2-4460.5" *)
    casez (sdram_bankmachine1_row_close)
      /* src = "ls180.v:4453.6-4453.34" */
      1'h1:
          _0317_ = 1'h0;
      /* src = "ls180.v:4455.6-4455.10" */
      default:
          (* src = "ls180.v:4456.3-4459.6" *)
          casez (sdram_bankmachine1_row_open)
            /* src = "ls180.v:4456.7-4456.34" */
            1'h1:
              begin
                _0317_ = 1'h1;
                _0313_ = sdram_bankmachine1_cmd_buffer_source_payload_addr[21:9];
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4461.2-4463.5" *)
    casez (_1608_)
      /* src = "ls180.v:4461.6-4461.176" */
      1'h1:
          _0291_ = _1032_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4464.2-4466.5" *)
    casez (sdram_bankmachine1_cmd_buffer_lookahead_do_read)
      /* src = "ls180.v:4464.6-4464.53" */
      1'h1:
          _0289_ = _1033_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4467.2-4475.5" *)
    casez (_1610_)
      /* src = "ls180.v:4467.6-4467.176" */
      1'h1:
          (* src = "ls180.v:4468.3-4470.6" *)
          casez (_2135_)
            /* src = "ls180.v:4468.7-4468.57" */
            1'h1:
                _0290_ = _1034_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4471.6-4471.10" */
      default:
          (* src = "ls180.v:4472.3-4474.6" *)
          casez (sdram_bankmachine1_cmd_buffer_lookahead_do_read)
            /* src = "ls180.v:4472.7-4472.54" */
            1'h1:
                _0290_ = _2372_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4476.2-4482.5" *)
    casez (_2342_)
      /* src = "ls180.v:4476.6-4476.98" */
      1'h1:
        begin
          _0300_ = sdram_bankmachine1_cmd_buffer_sink_valid;
          _0296_ = sdram_bankmachine1_cmd_buffer_sink_first;
          _0297_ = sdram_bankmachine1_cmd_buffer_sink_last;
          _0299_ = sdram_bankmachine1_cmd_buffer_sink_payload_we;
          _0298_ = sdram_bankmachine1_cmd_buffer_sink_payload_addr;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4483.2-4497.5" *)
    casez (sdram_bankmachine1_twtpcon_valid)
      /* src = "ls180.v:4483.6-4483.38" */
      1'h1:
        begin
          _0320_ = 3'h4;
          (* src = "ls180.v:4485.3-4489.6" *)
          casez (1'h0)
            /* src = "ls180.v:4487.7-4487.11" */
            default:
                _0321_ = 1'h0;
          endcase
        end
      /* src = "ls180.v:4490.6-4490.10" */
      default:
          (* src = "ls180.v:4491.3-4496.6" *)
          casez (_2137_)
            /* src = "ls180.v:4491.7-4491.42" */
            1'h1:
              begin
                _0320_ = _2373_;
                (* src = "ls180.v:4493.4-4495.7" *)
                casez (_1877_)
                  /* src = "ls180.v:4493.8-4493.50" */
                  1'h1:
                      _0321_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4499.2-4506.5" *)
    casez (sdram_bankmachine2_row_close)
      /* src = "ls180.v:4499.6-4499.34" */
      1'h1:
          _0351_ = 1'h0;
      /* src = "ls180.v:4501.6-4501.10" */
      default:
          (* src = "ls180.v:4502.3-4505.6" *)
          casez (sdram_bankmachine2_row_open)
            /* src = "ls180.v:4502.7-4502.34" */
            1'h1:
              begin
                _0351_ = 1'h1;
                _0347_ = sdram_bankmachine2_cmd_buffer_source_payload_addr[21:9];
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4507.2-4509.5" *)
    casez (_1612_)
      /* src = "ls180.v:4507.6-4507.176" */
      1'h1:
          _0325_ = _1035_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4510.2-4512.5" *)
    casez (sdram_bankmachine2_cmd_buffer_lookahead_do_read)
      /* src = "ls180.v:4510.6-4510.53" */
      1'h1:
          _0323_ = _1036_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4513.2-4521.5" *)
    casez (_1614_)
      /* src = "ls180.v:4513.6-4513.176" */
      1'h1:
          (* src = "ls180.v:4514.3-4516.6" *)
          casez (_2140_)
            /* src = "ls180.v:4514.7-4514.57" */
            1'h1:
                _0324_ = _1037_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4517.6-4517.10" */
      default:
          (* src = "ls180.v:4518.3-4520.6" *)
          casez (sdram_bankmachine2_cmd_buffer_lookahead_do_read)
            /* src = "ls180.v:4518.7-4518.54" */
            1'h1:
                _0324_ = _2374_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4522.2-4528.5" *)
    casez (_2343_)
      /* src = "ls180.v:4522.6-4522.98" */
      1'h1:
        begin
          _0334_ = sdram_bankmachine2_cmd_buffer_sink_valid;
          _0330_ = sdram_bankmachine2_cmd_buffer_sink_first;
          _0331_ = sdram_bankmachine2_cmd_buffer_sink_last;
          _0333_ = sdram_bankmachine2_cmd_buffer_sink_payload_we;
          _0332_ = sdram_bankmachine2_cmd_buffer_sink_payload_addr;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4529.2-4543.5" *)
    casez (sdram_bankmachine2_twtpcon_valid)
      /* src = "ls180.v:4529.6-4529.38" */
      1'h1:
        begin
          _0354_ = 3'h4;
          (* src = "ls180.v:4531.3-4535.6" *)
          casez (1'h0)
            /* src = "ls180.v:4533.7-4533.11" */
            default:
                _0355_ = 1'h0;
          endcase
        end
      /* src = "ls180.v:4536.6-4536.10" */
      default:
          (* src = "ls180.v:4537.3-4542.6" *)
          casez (_2142_)
            /* src = "ls180.v:4537.7-4537.42" */
            1'h1:
              begin
                _0354_ = _2375_;
                (* src = "ls180.v:4539.4-4541.7" *)
                casez (_1878_)
                  /* src = "ls180.v:4539.8-4539.50" */
                  1'h1:
                      _0355_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4545.2-4552.5" *)
    casez (sdram_bankmachine3_row_close)
      /* src = "ls180.v:4545.6-4545.34" */
      1'h1:
          _0385_ = 1'h0;
      /* src = "ls180.v:4547.6-4547.10" */
      default:
          (* src = "ls180.v:4548.3-4551.6" *)
          casez (sdram_bankmachine3_row_open)
            /* src = "ls180.v:4548.7-4548.34" */
            1'h1:
              begin
                _0385_ = 1'h1;
                _0381_ = sdram_bankmachine3_cmd_buffer_source_payload_addr[21:9];
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4553.2-4555.5" *)
    casez (_1616_)
      /* src = "ls180.v:4553.6-4553.176" */
      1'h1:
          _0359_ = _1038_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4556.2-4558.5" *)
    casez (sdram_bankmachine3_cmd_buffer_lookahead_do_read)
      /* src = "ls180.v:4556.6-4556.53" */
      1'h1:
          _0357_ = _1039_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4559.2-4567.5" *)
    casez (_1618_)
      /* src = "ls180.v:4559.6-4559.176" */
      1'h1:
          (* src = "ls180.v:4560.3-4562.6" *)
          casez (_2145_)
            /* src = "ls180.v:4560.7-4560.57" */
            1'h1:
                _0358_ = _1040_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4563.6-4563.10" */
      default:
          (* src = "ls180.v:4564.3-4566.6" *)
          casez (sdram_bankmachine3_cmd_buffer_lookahead_do_read)
            /* src = "ls180.v:4564.7-4564.54" */
            1'h1:
                _0358_ = _2376_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4568.2-4574.5" *)
    casez (_2344_)
      /* src = "ls180.v:4568.6-4568.98" */
      1'h1:
        begin
          _0368_ = sdram_bankmachine3_cmd_buffer_sink_valid;
          _0364_ = sdram_bankmachine3_cmd_buffer_sink_first;
          _0365_ = sdram_bankmachine3_cmd_buffer_sink_last;
          _0367_ = sdram_bankmachine3_cmd_buffer_sink_payload_we;
          _0366_ = sdram_bankmachine3_cmd_buffer_sink_payload_addr;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4575.2-4589.5" *)
    casez (sdram_bankmachine3_twtpcon_valid)
      /* src = "ls180.v:4575.6-4575.38" */
      1'h1:
        begin
          _0388_ = 3'h4;
          (* src = "ls180.v:4577.3-4581.6" *)
          casez (1'h0)
            /* src = "ls180.v:4579.7-4579.11" */
            default:
                _0389_ = 1'h0;
          endcase
        end
      /* src = "ls180.v:4582.6-4582.10" */
      default:
          (* src = "ls180.v:4583.3-4588.6" *)
          casez (_2147_)
            /* src = "ls180.v:4583.7-4583.42" */
            1'h1:
              begin
                _0388_ = _2377_;
                (* src = "ls180.v:4585.4-4587.7" *)
                casez (_1879_)
                  /* src = "ls180.v:4585.8-4585.50" */
                  1'h1:
                      _0389_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4591.2-4597.5" *)
    casez (_2148_)
      /* src = "ls180.v:4591.6-4591.18" */
      1'h1:
          _0475_ = 5'h1f;
      /* src = "ls180.v:4593.6-4593.10" */
      default:
          (* src = "ls180.v:4594.3-4596.6" *)
          casez (_2149_)
            /* src = "ls180.v:4594.7-4594.25" */
            1'h1:
                _0475_ = _2378_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4598.2-4604.5" *)
    casez (_2150_)
      /* src = "ls180.v:4598.6-4598.18" */
      1'h1:
          _0476_ = 4'hf;
      /* src = "ls180.v:4600.6-4600.10" */
      default:
          (* src = "ls180.v:4601.3-4603.6" *)
          casez (_2151_)
            /* src = "ls180.v:4601.7-4601.25" */
            1'h1:
                _0476_ = _2379_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4605.2-4660.5" *)
    casez (sdram_choose_cmd_ce)
      /* src = "ls180.v:4605.6-4605.25" */
      1'h1:
          (* src = "ls180.v:4606.3-4659.10" *)
          casez (sdram_choose_cmd_grant)
            /* src = "ls180.v:0.0-0.0" */
            2'h0:
                (* src = "ls180.v:4608.5-4618.8" *)
                casez (sdram_choose_cmd_request[1])
                  /* src = "ls180.v:4608.9-4608.36" */
                  1'h1:
                      _0394_ = 2'h1;
                  /* src = "ls180.v:4610.9-4610.13" */
                  default:
                      (* src = "ls180.v:4611.6-4617.9" *)
                      casez (sdram_choose_cmd_request[2])
                        /* src = "ls180.v:4611.10-4611.37" */
                        1'h1:
                            _0394_ = 2'h2;
                        /* src = "ls180.v:4613.10-4613.14" */
                        default:
                            (* src = "ls180.v:4614.7-4616.10" *)
                            casez (sdram_choose_cmd_request[3])
                              /* src = "ls180.v:4614.11-4614.38" */
                              1'h1:
                                  _0394_ = 2'h3;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h1:
                (* src = "ls180.v:4621.5-4631.8" *)
                casez (sdram_choose_cmd_request[2])
                  /* src = "ls180.v:4621.9-4621.36" */
                  1'h1:
                      _0394_ = 2'h2;
                  /* src = "ls180.v:4623.9-4623.13" */
                  default:
                      (* src = "ls180.v:4624.6-4630.9" *)
                      casez (sdram_choose_cmd_request[3])
                        /* src = "ls180.v:4624.10-4624.37" */
                        1'h1:
                            _0394_ = 2'h3;
                        /* src = "ls180.v:4626.10-4626.14" */
                        default:
                            (* src = "ls180.v:4627.7-4629.10" *)
                            casez (sdram_choose_cmd_request[0])
                              /* src = "ls180.v:4627.11-4627.38" */
                              1'h1:
                                  _0394_ = 2'h0;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h2:
                (* src = "ls180.v:4634.5-4644.8" *)
                casez (sdram_choose_cmd_request[3])
                  /* src = "ls180.v:4634.9-4634.36" */
                  1'h1:
                      _0394_ = 2'h3;
                  /* src = "ls180.v:4636.9-4636.13" */
                  default:
                      (* src = "ls180.v:4637.6-4643.9" *)
                      casez (sdram_choose_cmd_request[0])
                        /* src = "ls180.v:4637.10-4637.37" */
                        1'h1:
                            _0394_ = 2'h0;
                        /* src = "ls180.v:4639.10-4639.14" */
                        default:
                            (* src = "ls180.v:4640.7-4642.10" *)
                            casez (sdram_choose_cmd_request[1])
                              /* src = "ls180.v:4640.11-4640.38" */
                              1'h1:
                                  _0394_ = 2'h1;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h3:
                (* src = "ls180.v:4647.5-4657.8" *)
                casez (sdram_choose_cmd_request[0])
                  /* src = "ls180.v:4647.9-4647.36" */
                  1'h1:
                      _0394_ = 2'h0;
                  /* src = "ls180.v:4649.9-4649.13" */
                  default:
                      (* src = "ls180.v:4650.6-4656.9" *)
                      casez (sdram_choose_cmd_request[1])
                        /* src = "ls180.v:4650.10-4650.37" */
                        1'h1:
                            _0394_ = 2'h1;
                        /* src = "ls180.v:4652.10-4652.14" */
                        default:
                            (* src = "ls180.v:4653.7-4655.10" *)
                            casez (sdram_choose_cmd_request[2])
                              /* src = "ls180.v:4653.11-4653.38" */
                              1'h1:
                                  _0394_ = 2'h2;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4661.2-4716.5" *)
    casez (sdram_choose_req_ce)
      /* src = "ls180.v:4661.6-4661.25" */
      1'h1:
          (* src = "ls180.v:4662.3-4715.10" *)
          casez (sdram_choose_req_grant)
            /* src = "ls180.v:0.0-0.0" */
            2'h0:
                (* src = "ls180.v:4664.5-4674.8" *)
                casez (sdram_choose_req_request[1])
                  /* src = "ls180.v:4664.9-4664.36" */
                  1'h1:
                      _0404_ = 2'h1;
                  /* src = "ls180.v:4666.9-4666.13" */
                  default:
                      (* src = "ls180.v:4667.6-4673.9" *)
                      casez (sdram_choose_req_request[2])
                        /* src = "ls180.v:4667.10-4667.37" */
                        1'h1:
                            _0404_ = 2'h2;
                        /* src = "ls180.v:4669.10-4669.14" */
                        default:
                            (* src = "ls180.v:4670.7-4672.10" *)
                            casez (sdram_choose_req_request[3])
                              /* src = "ls180.v:4670.11-4670.38" */
                              1'h1:
                                  _0404_ = 2'h3;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h1:
                (* src = "ls180.v:4677.5-4687.8" *)
                casez (sdram_choose_req_request[2])
                  /* src = "ls180.v:4677.9-4677.36" */
                  1'h1:
                      _0404_ = 2'h2;
                  /* src = "ls180.v:4679.9-4679.13" */
                  default:
                      (* src = "ls180.v:4680.6-4686.9" *)
                      casez (sdram_choose_req_request[3])
                        /* src = "ls180.v:4680.10-4680.37" */
                        1'h1:
                            _0404_ = 2'h3;
                        /* src = "ls180.v:4682.10-4682.14" */
                        default:
                            (* src = "ls180.v:4683.7-4685.10" *)
                            casez (sdram_choose_req_request[0])
                              /* src = "ls180.v:4683.11-4683.38" */
                              1'h1:
                                  _0404_ = 2'h0;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h2:
                (* src = "ls180.v:4690.5-4700.8" *)
                casez (sdram_choose_req_request[3])
                  /* src = "ls180.v:4690.9-4690.36" */
                  1'h1:
                      _0404_ = 2'h3;
                  /* src = "ls180.v:4692.9-4692.13" */
                  default:
                      (* src = "ls180.v:4693.6-4699.9" *)
                      casez (sdram_choose_req_request[0])
                        /* src = "ls180.v:4693.10-4693.37" */
                        1'h1:
                            _0404_ = 2'h0;
                        /* src = "ls180.v:4695.10-4695.14" */
                        default:
                            (* src = "ls180.v:4696.7-4698.10" *)
                            casez (sdram_choose_req_request[1])
                              /* src = "ls180.v:4696.11-4696.38" */
                              1'h1:
                                  _0404_ = 2'h1;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            /* src = "ls180.v:0.0-0.0" */
            2'h3:
                (* src = "ls180.v:4703.5-4713.8" *)
                casez (sdram_choose_req_request[0])
                  /* src = "ls180.v:4703.9-4703.36" */
                  1'h1:
                      _0404_ = 2'h0;
                  /* src = "ls180.v:4705.9-4705.13" */
                  default:
                      (* src = "ls180.v:4706.6-4712.9" *)
                      casez (sdram_choose_req_request[1])
                        /* src = "ls180.v:4706.10-4706.37" */
                        1'h1:
                            _0404_ = 2'h1;
                        /* src = "ls180.v:4708.10-4708.14" */
                        default:
                            (* src = "ls180.v:4709.7-4711.10" *)
                            casez (sdram_choose_req_request[2])
                              /* src = "ls180.v:4709.11-4709.38" */
                              1'h1:
                                  _0404_ = 2'h2;
                              default:
                                  /* empty */;
                            endcase
                      endcase
                endcase
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4725.2-4739.5" *)
    casez (sdram_tccdcon_valid)
      /* src = "ls180.v:4725.6-4725.25" */
      1'h1:
        begin
          _0472_ = 1'h0;
          (* src = "ls180.v:4727.3-4731.6" *)
          casez (1'h1)
            /* src = "ls180.v:4727.7-4727.11" */
            1'h1:
                _0473_ = 1'h1;
            default:
                /* empty */;
          endcase
        end
      /* src = "ls180.v:4732.6-4732.10" */
      default:
          (* src = "ls180.v:4733.3-4738.6" *)
          casez (_2155_)
            /* src = "ls180.v:4733.7-4733.29" */
            1'h1:
              begin
                _0472_ = _2380_;
                (* src = "ls180.v:4735.4-4737.7" *)
                casez (_1880_)
                  /* src = "ls180.v:4735.8-4735.37" */
                  1'h1:
                      _0473_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4740.2-4754.5" *)
    casez (sdram_twtrcon_valid)
      /* src = "ls180.v:4740.6-4740.25" */
      1'h1:
        begin
          _0479_ = 3'h4;
          (* src = "ls180.v:4742.3-4746.6" *)
          casez (1'h0)
            /* src = "ls180.v:4744.7-4744.11" */
            default:
                _0480_ = 1'h0;
          endcase
        end
      /* src = "ls180.v:4747.6-4747.10" */
      default:
          (* src = "ls180.v:4748.3-4753.6" *)
          casez (_2156_)
            /* src = "ls180.v:4748.7-4748.29" */
            1'h1:
              begin
                _0479_ = _2381_;
                (* src = "ls180.v:4750.4-4752.7" *)
                casez (_1881_)
                  /* src = "ls180.v:4750.8-4750.37" */
                  1'h1:
                      _0480_ = 1'h1;
                  default:
                      /* empty */;
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4761.2-4763.5" *)
    casez (_2353_)
      /* src = "ls180.v:4761.6-4761.40" */
      1'h1:
          _0053_ = wb_sdram_dat_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4765.2-4767.5" *)
    casez (converter_counter_subfragments_next_value_ce)
      /* src = "ls180.v:4765.6-4765.50" */
      1'h1:
          _0050_ = converter_counter_subfragments_next_value;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4768.2-4771.5" *)
    casez (converter_reset)
      /* src = "ls180.v:4768.6-4768.21" */
      1'h1:
        begin
          _0050_ = 1'h0;
          _0509_ = 1'h0;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4772.2-4782.5" *)
    casez (litedram_wb_ack)
      /* src = "ls180.v:4772.6-4772.21" */
      1'h1:
        begin
          _0049_ = 1'h0;
          _0547_ = 1'h0;
        end
      /* src = "ls180.v:4775.6-4775.10" */
      default:
        begin
          (* src = "ls180.v:4776.3-4778.6" *)
          casez (_1627_)
            /* src = "ls180.v:4776.7-4776.40" */
            1'h1:
                _0049_ = 1'h1;
            default:
                /* empty */;
          endcase
          (* src = "ls180.v:4779.3-4781.6" *)
          casez (_1628_)
            /* src = "ls180.v:4779.7-4779.44" */
            1'h1:
                _0547_ = 1'h1;
            default:
                /* empty */;
          endcase
        end
    endcase
    (* src = "ls180.v:4784.2-4805.5" *)
    casez (_1630_)
      /* src = "ls180.v:4784.6-4784.76" */
      1'h1:
        begin
          _0542_ = uart_phy_sink_payload_data;
          _0540_ = 4'h0;
          _0541_ = 1'h1;
          _0142_ = 1'h0;
        end
      /* src = "ls180.v:4789.6-4789.10" */
      default:
          (* src = "ls180.v:4790.3-4804.6" *)
          casez (_1631_)
            /* src = "ls180.v:4790.7-4790.50" */
            1'h1:
              begin
                _0540_ = _1041_;
                (* src = "ls180.v:4792.4-4803.7" *)
                casez (_1890_)
                  /* src = "ls180.v:4792.8-4792.38" */
                  1'h1:
                      _0142_ = 1'h1;
                  /* src = "ls180.v:4794.8-4794.12" */
                  default:
                      (* src = "ls180.v:4795.5-4802.8" *)
                      casez (_1891_)
                        /* src = "ls180.v:4795.9-4795.39" */
                        1'h1:
                          begin
                            _0142_ = 1'h1;
                            _0541_ = 1'h0;
                            _0534_ = 1'h1;
                          end
                        /* src = "ls180.v:4799.9-4799.13" */
                        default:
                          begin
                            _0142_ = uart_phy_tx_reg[0];
                            _0542_ = { 1'h0, uart_phy_tx_reg[7:1] };
                          end
                      endcase
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4806.2-4810.5" *)
    casez (uart_phy_tx_busy)
      /* src = "ls180.v:4806.6-4806.22" */
      1'h1:
          { _0544_, _0528_ } = _1042_;
      /* src = "ls180.v:4808.6-4808.10" */
      default:
          { _0544_, _0528_ } = { 1'h0, uart_phy_storage };
    endcase
    (* src = "ls180.v:4813.2-4837.5" *)
    casez (_2159_)
      /* src = "ls180.v:4813.6-4813.25" */
      1'h1:
          (* src = "ls180.v:4814.3-4817.6" *)
          casez (_1632_)
            /* src = "ls180.v:4814.7-4814.39" */
            1'h1:
              begin
                _0531_ = 1'h1;
                _0530_ = 4'h0;
              end
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4818.6-4818.10" */
      default:
          (* src = "ls180.v:4819.3-4836.6" *)
          casez (uart_phy_uart_clk_rxen)
            /* src = "ls180.v:4819.7-4819.29" */
            1'h1:
              begin
                _0530_ = _1043_;
                (* src = "ls180.v:4821.4-4835.7" *)
                casez (_1892_)
                  /* src = "ls180.v:4821.8-4821.38" */
                  1'h1:
                      (* src = "ls180.v:4822.5-4824.8" *)
                      casez (uart_phy_rx)
                        /* src = "ls180.v:4822.9-4822.20" */
                        1'h1:
                            _0531_ = 1'h0;
                        default:
                            /* empty */;
                      endcase
                  /* src = "ls180.v:4825.8-4825.12" */
                  default:
                      (* src = "ls180.v:4826.5-4834.8" *)
                      casez (_1893_)
                        /* src = "ls180.v:4826.9-4826.39" */
                        1'h1:
                          begin
                            _0531_ = 1'h0;
                            (* src = "ls180.v:4828.6-4831.9" *)
                            casez (uart_phy_rx)
                              /* src = "ls180.v:4828.10-4828.21" */
                              1'h1:
                                begin
                                  _0537_ = uart_phy_rx_reg;
                                  _0538_ = 1'h1;
                                end
                              default:
                                  /* empty */;
                            endcase
                          end
                        /* src = "ls180.v:4832.9-4832.13" */
                        default:
                            _0533_ = { uart_phy_rx, uart_phy_rx_reg[7:1] };
                      endcase
                endcase
              end
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4838.2-4842.5" *)
    casez (uart_phy_rx_busy)
      /* src = "ls180.v:4838.6-4838.22" */
      1'h1:
          { _0543_, _0527_ } = _1044_;
      /* src = "ls180.v:4840.6-4840.10" */
      default:
          { _0543_, _0527_ } = 33'h080000000;
    endcase
    (* src = "ls180.v:4843.2-4845.5" *)
    casez (tx_clear)
      /* src = "ls180.v:4843.6-4843.14" */
      1'h1:
          _0526_ = 1'h0;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4847.2-4849.5" *)
    casez (_1633_)
      /* src = "ls180.v:4847.6-4847.38" */
      1'h1:
          _0526_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4850.2-4852.5" *)
    casez (rx_clear)
      /* src = "ls180.v:4850.6-4850.14" */
      1'h1:
          _0249_ = 1'h0;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4854.2-4856.5" *)
    casez (_1634_)
      /* src = "ls180.v:4854.6-4854.38" */
      1'h1:
          _0249_ = 1'h1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4857.2-4863.5" *)
    casez (tx_fifo_syncfifo_re)
      /* src = "ls180.v:4857.6-4857.25" */
      1'h1:
          _0520_ = 1'h1;
      /* src = "ls180.v:4859.6-4859.10" */
      default:
          (* src = "ls180.v:4860.3-4862.6" *)
          casez (tx_fifo_re)
            /* src = "ls180.v:4860.7-4860.17" */
            1'h1:
                _0520_ = 1'h0;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4864.2-4866.5" *)
    casez (_1636_)
      /* src = "ls180.v:4864.6-4864.78" */
      1'h1:
          _0519_ = _1045_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4867.2-4869.5" *)
    casez (tx_fifo_do_read)
      /* src = "ls180.v:4867.6-4867.21" */
      1'h1:
          _0517_ = _1046_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4870.2-4878.5" *)
    casez (_1638_)
      /* src = "ls180.v:4870.6-4870.78" */
      1'h1:
          (* src = "ls180.v:4871.3-4873.6" *)
          casez (_2165_)
            /* src = "ls180.v:4871.7-4871.25" */
            1'h1:
                _0518_ = _1047_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4874.6-4874.10" */
      default:
          (* src = "ls180.v:4875.3-4877.6" *)
          casez (tx_fifo_do_read)
            /* src = "ls180.v:4875.7-4875.22" */
            1'h1:
                _0518_ = _2382_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4879.2-4885.5" *)
    casez (rx_fifo_syncfifo_re)
      /* src = "ls180.v:4879.6-4879.25" */
      1'h1:
          _0245_ = 1'h1;
      /* src = "ls180.v:4881.6-4881.10" */
      default:
          (* src = "ls180.v:4882.3-4884.6" *)
          casez (rx_fifo_re)
            /* src = "ls180.v:4882.7-4882.17" */
            1'h1:
                _0245_ = 1'h0;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4886.2-4888.5" *)
    casez (_1640_)
      /* src = "ls180.v:4886.6-4886.78" */
      1'h1:
          _0244_ = _1048_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4889.2-4891.5" *)
    casez (rx_fifo_do_read)
      /* src = "ls180.v:4889.6-4889.21" */
      1'h1:
          _0242_ = _1049_;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4892.2-4900.5" *)
    casez (_1642_)
      /* src = "ls180.v:4892.6-4892.78" */
      1'h1:
          (* src = "ls180.v:4893.3-4895.6" *)
          casez (_2168_)
            /* src = "ls180.v:4893.7-4893.25" */
            1'h1:
                _0243_ = _1050_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4896.6-4896.10" */
      default:
          (* src = "ls180.v:4897.3-4899.6" *)
          casez (rx_fifo_do_read)
            /* src = "ls180.v:4897.7-4897.22" */
            1'h1:
                _0243_ = _2383_;
            default:
                /* empty */;
          endcase
    endcase
    (* src = "ls180.v:4901.2-4914.5" *)
    casez (reset)
      /* src = "ls180.v:4901.6-4901.11" */
      1'h1:
        begin
          _0526_ = 1'h0;
          _0525_ = 1'h0;
          _0249_ = 1'h0;
          _0248_ = 1'h0;
          _0520_ = 1'h0;
          _0518_ = 5'h00;
          _0519_ = 4'h0;
          _0517_ = 4'h0;
          _0245_ = 1'h0;
          _0243_ = 5'h00;
          _0244_ = 4'h0;
          _0242_ = 4'h0;
        end
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4916.2-4918.5" *)
    casez (libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0)
      /* src = "ls180.v:4916.6-4916.62" */
      1'h1:
          _0153_ = libresocsim_libresocsim_dat_w_libresocsim_next_value0;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4919.2-4921.5" *)
    casez (libresocsim_libresocsim_adr_libresocsim_next_value_ce1)
      /* src = "ls180.v:4919.6-4919.60" */
      1'h1:
          _0150_ = libresocsim_libresocsim_adr_libresocsim_next_value1;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4922.2-4924.5" *)
    casez (libresocsim_libresocsim_we_libresocsim_next_value_ce2)
      /* src = "ls180.v:4922.6-4922.59" */
      1'h1:
          _0156_ = libresocsim_libresocsim_we_libresocsim_next_value2;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4925.2-4959.9" *)
    casez (libresocsim_grant)
      /* src = "ls180.v:0.0-0.0" */
      2'h0:
          (* src = "ls180.v:4927.4-4935.7" *)
          casez (_2169_)
            /* src = "ls180.v:4927.8-4927.33" */
            1'h1:
                (* src = "ls180.v:4928.5-4934.8" *)
                casez (libresocsim_request[1])
                  /* src = "ls180.v:4928.9-4928.31" */
                  1'h1:
                      _0099_ = 2'h1;
                  /* src = "ls180.v:4930.9-4930.13" */
                  default:
                      (* src = "ls180.v:4931.6-4933.9" *)
                      casez (libresocsim_request[2])
                        /* src = "ls180.v:4931.10-4931.32" */
                        1'h1:
                            _0099_ = 2'h2;
                        default:
                            /* empty */;
                      endcase
                endcase
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      2'h1:
          (* src = "ls180.v:4938.4-4946.7" *)
          casez (_2170_)
            /* src = "ls180.v:4938.8-4938.33" */
            1'h1:
                (* src = "ls180.v:4939.5-4945.8" *)
                casez (libresocsim_request[2])
                  /* src = "ls180.v:4939.9-4939.31" */
                  1'h1:
                      _0099_ = 2'h2;
                  /* src = "ls180.v:4941.9-4941.13" */
                  default:
                      (* src = "ls180.v:4942.6-4944.9" *)
                      casez (libresocsim_request[0])
                        /* src = "ls180.v:4942.10-4942.32" */
                        1'h1:
                            _0099_ = 2'h0;
                        default:
                            /* empty */;
                      endcase
                endcase
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:0.0-0.0" */
      2'h2:
          (* src = "ls180.v:4949.4-4957.7" *)
          casez (_2171_)
            /* src = "ls180.v:4949.8-4949.33" */
            1'h1:
                (* src = "ls180.v:4950.5-4956.8" *)
                casez (libresocsim_request[0])
                  /* src = "ls180.v:4950.9-4950.31" */
                  1'h1:
                      _0099_ = 2'h0;
                  /* src = "ls180.v:4952.9-4952.13" */
                  default:
                      (* src = "ls180.v:4953.6-4955.9" *)
                      casez (libresocsim_request[1])
                        /* src = "ls180.v:4953.10-4953.32" */
                        1'h1:
                            _0099_ = 2'h1;
                        default:
                            /* empty */;
                      endcase
                endcase
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:4961.2-4967.5" *)
    casez (libresocsim_wait)
      /* src = "ls180.v:4961.6-4961.22" */
      1'h1:
          (* src = "ls180.v:4962.3-4964.6" *)
          casez (_2172_)
            /* src = "ls180.v:4962.7-4962.26" */
            1'h1:
                _0093_ = _2384_;
            default:
                /* empty */;
          endcase
      /* src = "ls180.v:4965.6-4965.10" */
      default:
          _0093_ = 20'hf4240;
    endcase
    (* src = "ls180.v:4969.2-4999.5" *)
    casez (libresocsim_csrbank0_sel)
      /* src = "ls180.v:4969.6-4969.30" */
      1'h1:
          (* src = "ls180.v:4970.3-4998.10" *)
          casez (libresocsim_interface0_bank_bus_adr[3:0])
            /* src = "ls180.v:0.0-0.0" */
            4'h0:
                _0100_ = { 7'h00, libresocsim_csrbank0_reset0_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h1:
                _0100_ = libresocsim_csrbank0_scratch3_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h2:
                _0100_ = libresocsim_csrbank0_scratch2_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h3:
                _0100_ = libresocsim_csrbank0_scratch1_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h4:
                _0100_ = libresocsim_csrbank0_scratch0_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h5:
                _0100_ = libresocsim_csrbank0_bus_errors3_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h6:
                _0100_ = libresocsim_csrbank0_bus_errors2_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h7:
                _0100_ = libresocsim_csrbank0_bus_errors1_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h8:
                _0100_ = libresocsim_csrbank0_bus_errors0_w;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5000.2-5002.5" *)
    casez (libresocsim_csrbank0_reset0_re)
      /* src = "ls180.v:5000.6-5000.36" */
      1'h1:
          _0170_ = libresocsim_csrbank0_reset0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5004.2-5006.5" *)
    casez (libresocsim_csrbank0_scratch3_re)
      /* src = "ls180.v:5004.6-5004.38" */
      1'h1:
          _0172_[31:24] = libresocsim_csrbank0_scratch3_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5007.2-5009.5" *)
    casez (libresocsim_csrbank0_scratch2_re)
      /* src = "ls180.v:5007.6-5007.38" */
      1'h1:
          _0172_[23:16] = libresocsim_csrbank0_scratch2_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5010.2-5012.5" *)
    casez (libresocsim_csrbank0_scratch1_re)
      /* src = "ls180.v:5010.6-5010.38" */
      1'h1:
          _0172_[15:8] = libresocsim_csrbank0_scratch1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5013.2-5015.5" *)
    casez (libresocsim_csrbank0_scratch0_re)
      /* src = "ls180.v:5013.6-5013.38" */
      1'h1:
          _0172_[7:0] = libresocsim_csrbank0_scratch0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5018.2-5030.5" *)
    casez (libresocsim_csrbank1_sel)
      /* src = "ls180.v:5018.6-5018.30" */
      1'h1:
          (* src = "ls180.v:5019.3-5029.10" *)
          casez (libresocsim_interface1_bank_bus_adr[1:0])
            /* src = "ls180.v:0.0-0.0" */
            2'h0:
                _0109_ = libresocsim_csrbank1_oe0_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h1:
                _0109_ = libresocsim_csrbank1_in_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h2:
                _0109_ = libresocsim_csrbank1_out0_w;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5031.2-5033.5" *)
    casez (libresocsim_csrbank1_oe0_re)
      /* src = "ls180.v:5031.6-5031.33" */
      1'h1:
          _0064_ = libresocsim_csrbank1_oe0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5035.2-5037.5" *)
    casez (libresocsim_csrbank1_out0_re)
      /* src = "ls180.v:5035.6-5035.34" */
      1'h1:
          _0066_ = libresocsim_csrbank1_out0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5040.2-5052.5" *)
    casez (libresocsim_csrbank2_sel)
      /* src = "ls180.v:5040.6-5040.30" */
      1'h1:
          (* src = "ls180.v:5041.3-5051.10" *)
          casez (libresocsim_interface2_bank_bus_adr[1:0])
            /* src = "ls180.v:0.0-0.0" */
            2'h0:
                _0118_ = libresocsim_csrbank2_oe0_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h1:
                _0118_ = libresocsim_csrbank2_in_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h2:
                _0118_ = libresocsim_csrbank2_out0_w;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5053.2-5055.5" *)
    casez (libresocsim_csrbank2_oe0_re)
      /* src = "ls180.v:5053.6-5053.33" */
      1'h1:
          _0072_ = libresocsim_csrbank2_oe0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5057.2-5059.5" *)
    casez (libresocsim_csrbank2_out0_re)
      /* src = "ls180.v:5057.6-5057.34" */
      1'h1:
          _0074_ = libresocsim_csrbank2_out0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5062.2-5071.5" *)
    casez (libresocsim_csrbank3_sel)
      /* src = "ls180.v:5062.6-5062.30" */
      1'h1:
          (* src = "ls180.v:5063.3-5070.10" *)
          casez (libresocsim_interface3_bank_bus_adr[0])
            /* src = "ls180.v:0.0-0.0" */
            1'h0:
                _0119_ = { 5'h00, libresocsim_csrbank3_w0_w };
            /* src = "ls180.v:0.0-0.0" */
            1'h1:
                _0119_ = { 7'h00, libresocsim_csrbank3_r_w };
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5072.2-5074.5" *)
    casez (libresocsim_csrbank3_w0_re)
      /* src = "ls180.v:5072.6-5072.32" */
      1'h1:
          _0080_ = libresocsim_csrbank3_w0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5077.2-5110.5" *)
    casez (libresocsim_csrbank4_sel)
      /* src = "ls180.v:5077.6-5077.30" */
      1'h1:
          (* src = "ls180.v:5078.3-5109.10" *)
          casez (libresocsim_interface4_bank_bus_adr[3:0])
            /* src = "ls180.v:0.0-0.0" */
            4'h0:
                _0120_ = { 4'h0, libresocsim_csrbank4_dfii_control0_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h1:
                _0120_ = { 2'h0, libresocsim_csrbank4_dfii_pi0_command0_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h2:
                _0120_ = { 7'h00, sdram_command_issue_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h3:
                _0120_ = { 3'h0, libresocsim_csrbank4_dfii_pi0_address1_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h4:
                _0120_ = libresocsim_csrbank4_dfii_pi0_address0_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h5:
                _0120_ = { 6'h00, libresocsim_csrbank4_dfii_pi0_baddress0_w };
            /* src = "ls180.v:0.0-0.0" */
            4'h6:
                _0120_ = libresocsim_csrbank4_dfii_pi0_wrdata1_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h7:
                _0120_ = libresocsim_csrbank4_dfii_pi0_wrdata0_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h8:
                _0120_ = libresocsim_csrbank4_dfii_pi0_rddata1_w;
            /* src = "ls180.v:0.0-0.0" */
            4'h9:
                _0120_ = libresocsim_csrbank4_dfii_pi0_rddata0_w;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5111.2-5113.5" *)
    casez (libresocsim_csrbank4_dfii_control0_re)
      /* src = "ls180.v:5111.6-5111.43" */
      1'h1:
          _0471_ = libresocsim_csrbank4_dfii_control0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5115.2-5117.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_command0_re)
      /* src = "ls180.v:5115.6-5115.47" */
      1'h1:
          _0421_ = libresocsim_csrbank4_dfii_pi0_command0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5119.2-5121.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_address1_re)
      /* src = "ls180.v:5119.6-5119.47" */
      1'h1:
          _0251_[12:8] = libresocsim_csrbank4_dfii_pi0_address1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5122.2-5124.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_address0_re)
      /* src = "ls180.v:5122.6-5122.47" */
      1'h1:
          _0251_[7:0] = libresocsim_csrbank4_dfii_pi0_address0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5126.2-5128.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_baddress0_re)
      /* src = "ls180.v:5126.6-5126.48" */
      1'h1:
          _0253_ = libresocsim_csrbank4_dfii_pi0_baddress0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5130.2-5132.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_wrdata1_re)
      /* src = "ls180.v:5130.6-5130.46" */
      1'h1:
          _0482_[15:8] = libresocsim_csrbank4_dfii_pi0_wrdata1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5133.2-5135.5" *)
    casez (libresocsim_csrbank4_dfii_pi0_wrdata0_re)
      /* src = "ls180.v:5133.6-5133.46" */
      1'h1:
          _0482_[7:0] = libresocsim_csrbank4_dfii_pi0_wrdata0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5138.2-5192.5" *)
    casez (libresocsim_csrbank5_sel)
      /* src = "ls180.v:5138.6-5138.30" */
      1'h1:
          (* src = "ls180.v:5139.3-5191.10" *)
          casez (libresocsim_interface5_bank_bus_adr[4:0])
            /* src = "ls180.v:0.0-0.0" */
            5'h00:
                _0121_ = libresocsim_csrbank5_load3_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h01:
                _0121_ = libresocsim_csrbank5_load2_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h02:
                _0121_ = libresocsim_csrbank5_load1_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h03:
                _0121_ = libresocsim_csrbank5_load0_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h04:
                _0121_ = libresocsim_csrbank5_reload3_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h05:
                _0121_ = libresocsim_csrbank5_reload2_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h06:
                _0121_ = libresocsim_csrbank5_reload1_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h07:
                _0121_ = libresocsim_csrbank5_reload0_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h08:
                _0121_ = { 7'h00, libresocsim_csrbank5_en0_w };
            /* src = "ls180.v:0.0-0.0" */
            5'h09:
                _0121_ = { 7'h00, libresocsim_csrbank5_update_value0_w };
            /* src = "ls180.v:0.0-0.0" */
            5'h0a:
                _0121_ = libresocsim_csrbank5_value3_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h0b:
                _0121_ = libresocsim_csrbank5_value2_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h0c:
                _0121_ = libresocsim_csrbank5_value1_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h0d:
                _0121_ = libresocsim_csrbank5_value0_w;
            /* src = "ls180.v:0.0-0.0" */
            5'h0e:
                _0121_ = { 7'h00, libresocsim_eventmanager_status_w };
            /* src = "ls180.v:0.0-0.0" */
            5'h0f:
                _0121_ = { 7'h00, libresocsim_eventmanager_pending_w };
            /* src = "ls180.v:0.0-0.0" */
            5'h10:
                _0121_ = { 7'h00, libresocsim_csrbank5_ev_enable0_w };
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5193.2-5195.5" *)
    casez (libresocsim_csrbank5_load3_re)
      /* src = "ls180.v:5193.6-5193.35" */
      1'h1:
          _0163_[31:24] = libresocsim_csrbank5_load3_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5196.2-5198.5" *)
    casez (libresocsim_csrbank5_load2_re)
      /* src = "ls180.v:5196.6-5196.35" */
      1'h1:
          _0163_[23:16] = libresocsim_csrbank5_load2_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5199.2-5201.5" *)
    casez (libresocsim_csrbank5_load1_re)
      /* src = "ls180.v:5199.6-5199.35" */
      1'h1:
          _0163_[15:8] = libresocsim_csrbank5_load1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5202.2-5204.5" *)
    casez (libresocsim_csrbank5_load0_re)
      /* src = "ls180.v:5202.6-5202.35" */
      1'h1:
          _0163_[7:0] = libresocsim_csrbank5_load0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5206.2-5208.5" *)
    casez (libresocsim_csrbank5_reload3_re)
      /* src = "ls180.v:5206.6-5206.37" */
      1'h1:
          _0168_[31:24] = libresocsim_csrbank5_reload3_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5209.2-5211.5" *)
    casez (libresocsim_csrbank5_reload2_re)
      /* src = "ls180.v:5209.6-5209.37" */
      1'h1:
          _0168_[23:16] = libresocsim_csrbank5_reload2_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5212.2-5214.5" *)
    casez (libresocsim_csrbank5_reload1_re)
      /* src = "ls180.v:5212.6-5212.37" */
      1'h1:
          _0168_[15:8] = libresocsim_csrbank5_reload1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5215.2-5217.5" *)
    casez (libresocsim_csrbank5_reload0_re)
      /* src = "ls180.v:5215.6-5215.37" */
      1'h1:
          _0168_[7:0] = libresocsim_csrbank5_reload0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5219.2-5221.5" *)
    casez (libresocsim_csrbank5_en0_re)
      /* src = "ls180.v:5219.6-5219.33" */
      1'h1:
          _0095_ = libresocsim_csrbank5_en0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5223.2-5225.5" *)
    casez (libresocsim_csrbank5_update_value0_re)
      /* src = "ls180.v:5223.6-5223.43" */
      1'h1:
          _0179_ = libresocsim_csrbank5_update_value0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5227.2-5229.5" *)
    casez (libresocsim_csrbank5_ev_enable0_re)
      /* src = "ls180.v:5227.6-5227.40" */
      1'h1:
          _0098_ = libresocsim_csrbank5_ev_enable0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5232.2-5259.5" *)
    casez (libresocsim_csrbank6_sel)
      /* src = "ls180.v:5232.6-5232.30" */
      1'h1:
          (* src = "ls180.v:5233.3-5258.10" *)
          casez (libresocsim_interface6_bank_bus_adr[2:0])
            /* src = "ls180.v:0.0-0.0" */
            3'h0:
                _0122_ = rxtx_w;
            /* src = "ls180.v:0.0-0.0" */
            3'h1:
                _0122_ = { 7'h00, libresocsim_csrbank6_txfull_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h2:
                _0122_ = { 7'h00, libresocsim_csrbank6_rxempty_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h3:
                _0122_ = { 6'h00, eventmanager_status_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h4:
                _0122_ = { 6'h00, eventmanager_pending_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h5:
                _0122_ = { 6'h00, libresocsim_csrbank6_ev_enable0_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h6:
                _0122_ = { 7'h00, libresocsim_csrbank6_txempty_w };
            /* src = "ls180.v:0.0-0.0" */
            3'h7:
                _0122_ = { 7'h00, libresocsim_csrbank6_rxfull_w };
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5260.2-5262.5" *)
    casez (libresocsim_csrbank6_ev_enable0_re)
      /* src = "ls180.v:5260.6-5260.40" */
      1'h1:
          _0062_ = libresocsim_csrbank6_ev_enable0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5265.2-5280.5" *)
    casez (libresocsim_csrbank7_sel)
      /* src = "ls180.v:5265.6-5265.30" */
      1'h1:
          (* src = "ls180.v:5266.3-5279.10" *)
          casez (libresocsim_interface7_bank_bus_adr[1:0])
            /* src = "ls180.v:0.0-0.0" */
            2'h0:
                _0123_ = libresocsim_csrbank7_tuning_word3_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h1:
                _0123_ = libresocsim_csrbank7_tuning_word2_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h2:
                _0123_ = libresocsim_csrbank7_tuning_word1_w;
            /* src = "ls180.v:0.0-0.0" */
            2'h3:
                _0123_ = libresocsim_csrbank7_tuning_word0_w;
            default:
                /* empty */;
          endcase
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5281.2-5283.5" *)
    casez (libresocsim_csrbank7_tuning_word3_re)
      /* src = "ls180.v:5281.6-5281.42" */
      1'h1:
          _0539_[31:24] = libresocsim_csrbank7_tuning_word3_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5284.2-5286.5" *)
    casez (libresocsim_csrbank7_tuning_word2_re)
      /* src = "ls180.v:5284.6-5284.42" */
      1'h1:
          _0539_[23:16] = libresocsim_csrbank7_tuning_word2_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5287.2-5289.5" *)
    casez (libresocsim_csrbank7_tuning_word1_re)
      /* src = "ls180.v:5287.6-5287.42" */
      1'h1:
          _0539_[15:8] = libresocsim_csrbank7_tuning_word1_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5290.2-5292.5" *)
    casez (libresocsim_csrbank7_tuning_word0_re)
      /* src = "ls180.v:5290.6-5290.42" */
      1'h1:
          _0539_[7:0] = libresocsim_csrbank7_tuning_word0_r;
      default:
          /* empty */;
    endcase
    (* src = "ls180.v:5294.2-5439.5" *)
    casez (sys_rst_1)
      /* src = "ls180.v:5294.6-5294.15" */
      1'h1:
        begin
          _0170_ = 1'h0;
          _0169_ = 1'h0;
          _0172_ = 32'd305419896;
          _0171_ = 1'h0;
          _0082_ = 32'd0;
          _0142_ = 1'h1;
          _0083_ = 1'h0;
          _0088_ = 1'h0;
          _0165_ = 1'h0;
          _0163_ = 32'd0;
          _0162_ = 1'h0;
          _0168_ = 32'd0;
          _0167_ = 1'h0;
          _0095_ = 1'h0;
          _0094_ = 1'h0;
          _0179_ = 1'h0;
          _0178_ = 1'h0;
          _0181_ = 32'd0;
          _0185_ = 1'h0;
          _0184_ = 1'h0;
          _0098_ = 1'h0;
          _0097_ = 1'h0;
          _0180_ = 32'd0;
          _0202_ = 1'h0;
          _0056_ = 1'h0;
          _0205_ = 3'h0;
          _0471_ = 4'h1;
          _0460_ = 1'h0;
          _0421_ = 6'h00;
          _0420_ = 1'h0;
          _0250_ = 1'h0;
          _0252_ = 1'h0;
          _0481_ = 1'h0;
          _0467_ = 16'h0000;
          _0423_ = 13'h0000;
          _0424_ = 2'h0;
          _0425_ = 1'h1;
          _0426_ = 1'h1;
          _0427_ = 1'h1;
          _0429_ = 1'h1;
          _0430_ = 1'h0;
          _0428_ = 1'h0;
          _0477_ = 10'h30d;
          _0459_ = 1'h0;
          _0458_ = 1'h0;
          _0463_ = 1'h0;
          _0462_ = 4'h0;
          _0461_ = 1'h0;
          _0256_ = 4'h0;
          _0257_ = 3'h0;
          _0255_ = 3'h0;
          _0266_ = 1'h0;
          _0279_ = 13'h0000;
          _0283_ = 1'h0;
          _0287_ = 1'h0;
          _0286_ = 3'h0;
          _0290_ = 4'h0;
          _0291_ = 3'h0;
          _0289_ = 3'h0;
          _0300_ = 1'h0;
          _0313_ = 13'h0000;
          _0317_ = 1'h0;
          _0321_ = 1'h0;
          _0320_ = 3'h0;
          _0324_ = 4'h0;
          _0325_ = 3'h0;
          _0323_ = 3'h0;
          _0334_ = 1'h0;
          _0347_ = 13'h0000;
          _0351_ = 1'h0;
          _0355_ = 1'h0;
          _0354_ = 3'h0;
          _0358_ = 4'h0;
          _0359_ = 3'h0;
          _0357_ = 3'h0;
          _0368_ = 1'h0;
          _0381_ = 13'h0000;
          _0385_ = 1'h0;
          _0389_ = 1'h0;
          _0388_ = 3'h0;
          _0394_ = 2'h0;
          _0404_ = 2'h0;
          _0473_ = 1'h0;
          _0472_ = 1'h0;
          _0480_ = 1'h0;
          _0479_ = 3'h0;
          _0475_ = 5'h00;
          _0476_ = 4'h0;
          _0050_ = 1'h0;
          _0049_ = 1'h0;
          _0547_ = 1'h0;
          _0539_ = 32'd9895604;
          _0529_ = 1'h0;
          _0534_ = 1'h0;
          _0544_ = 1'h0;
          _0541_ = 1'h0;
          _0538_ = 1'h0;
          _0543_ = 1'h0;
          _0532_ = 1'h0;
          _0531_ = 1'h0;
          _0526_ = 1'h0;
          _0525_ = 1'h0;
          _0249_ = 1'h0;
          _0248_ = 1'h0;
          _0062_ = 2'h0;
          _0060_ = 1'h0;
          _0520_ = 1'h0;
          _0518_ = 5'h00;
          _0519_ = 4'h0;
          _0517_ = 4'h0;
          _0245_ = 1'h0;
          _0243_ = 5'h00;
          _0244_ = 4'h0;
          _0242_ = 4'h0;
          _0064_ = 8'h00;
          _0063_ = 1'h0;
          _0066_ = 8'h00;
          _0065_ = 1'h0;
          _0072_ = 8'h00;
          _0071_ = 1'h0;
          _0074_ = 8'h00;
          _0073_ = 1'h0;
          _0057_ = 40'h0000000000;
          _0080_ = 3'h0;
          _0079_ = 1'h0;
          _0492_ = 1'h0;
          _0494_ = 1'h0;
          _0508_ = 2'h0;
          _0484_ = 3'h0;
          _0486_ = 3'h0;
          _0488_ = 3'h0;
          _0490_ = 3'h0;
          _0500_ = 3'h0;
          _0505_ = 1'h0;
          _0501_ = 1'h0;
          _0502_ = 1'h0;
          _0503_ = 1'h0;
          _0504_ = 1'h0;
          _0509_ = 1'h0;
          _0156_ = 1'h0;
          _0099_ = 2'h0;
          _0176_ = 6'h00;
          _0093_ = 20'hf4240;
          _0177_ = 2'h0;
        end
      default:
          /* empty */;
    endcase
  end
  always @(posedge sys_clk_1) begin
      dummy <= _0057_;
      libresocsim_reset_storage <= _0170_;
      libresocsim_reset_re <= _0169_;
      libresocsim_scratch_storage <= _0172_;
      libresocsim_scratch_re <= _0171_;
      libresocsim_bus_errors <= _0082_;
      libresocsim_libresoc_constraintmanager_uart_tx <= _0142_;
      libresocsim_converter0_counter <= _0083_;
      libresocsim_converter0_dat_r <= _0086_;
      libresocsim_converter1_counter <= _0088_;
      libresocsim_converter1_dat_r <= _0091_;
      libresocsim_ram_bus_ack <= _0165_;
      libresocsim_load_storage <= _0163_;
      libresocsim_load_re <= _0162_;
      libresocsim_reload_storage <= _0168_;
      libresocsim_reload_re <= _0167_;
      libresocsim_en_storage <= _0095_;
      libresocsim_en_re <= _0094_;
      libresocsim_update_value_storage <= _0179_;
      libresocsim_update_value_re <= _0178_;
      libresocsim_value_status <= _0181_;
      libresocsim_zero_pending <= _0185_;
      libresocsim_zero_old_trigger <= _0184_;
      libresocsim_eventmanager_storage <= _0098_;
      libresocsim_eventmanager_re <= _0097_;
      libresocsim_value <= _0180_;
      ram_bus_ram_bus_ack <= _0202_;
      dfi_p0_rddata_valid <= _0056_;
      rddata_en <= _0205_;
      sdram_storage <= _0471_;
      sdram_re <= _0460_;
      sdram_command_storage <= _0421_;
      sdram_command_re <= _0420_;
      sdram_address_storage <= _0251_;
      sdram_address_re <= _0250_;
      sdram_baddress_storage <= _0253_;
      sdram_baddress_re <= _0252_;
      sdram_wrdata_storage <= _0482_;
      sdram_wrdata_re <= _0481_;
      sdram_status <= _0467_;
      sdram_dfi_p0_address <= _0423_;
      sdram_dfi_p0_bank <= _0424_;
      sdram_dfi_p0_cas_n <= _0425_;
      sdram_dfi_p0_cs_n <= _0426_;
      sdram_dfi_p0_ras_n <= _0427_;
      sdram_dfi_p0_we_n <= _0429_;
      sdram_dfi_p0_wrdata_en <= _0430_;
      sdram_dfi_p0_rddata_en <= _0428_;
      sdram_cmd_payload_a <= _0410_;
      sdram_cmd_payload_ba <= _0411_;
      sdram_cmd_payload_cas <= _0412_;
      sdram_cmd_payload_ras <= _0415_;
      sdram_cmd_payload_we <= _0416_;
      sdram_timer_count1 <= _0477_;
      sdram_postponer_req_o <= _0459_;
      sdram_postponer_count <= _0458_;
      sdram_sequencer_done1 <= _0463_;
      sdram_sequencer_counter <= _0462_;
      sdram_sequencer_count <= _0461_;
      sdram_bankmachine0_cmd_buffer_lookahead_level <= _0256_;
      sdram_bankmachine0_cmd_buffer_lookahead_produce <= _0257_;
      sdram_bankmachine0_cmd_buffer_lookahead_consume <= _0255_;
      sdram_bankmachine0_cmd_buffer_source_valid <= _0266_;
      sdram_bankmachine0_cmd_buffer_source_first <= _0262_;
      sdram_bankmachine0_cmd_buffer_source_last <= _0263_;
      sdram_bankmachine0_cmd_buffer_source_payload_we <= _0265_;
      sdram_bankmachine0_cmd_buffer_source_payload_addr <= _0264_;
      sdram_bankmachine0_row <= _0279_;
      sdram_bankmachine0_row_opened <= _0283_;
      sdram_bankmachine0_twtpcon_ready <= _0287_;
      sdram_bankmachine0_twtpcon_count <= _0286_;
      sdram_bankmachine1_cmd_buffer_lookahead_level <= _0290_;
      sdram_bankmachine1_cmd_buffer_lookahead_produce <= _0291_;
      sdram_bankmachine1_cmd_buffer_lookahead_consume <= _0289_;
      sdram_bankmachine1_cmd_buffer_source_valid <= _0300_;
      sdram_bankmachine1_cmd_buffer_source_first <= _0296_;
      sdram_bankmachine1_cmd_buffer_source_last <= _0297_;
      sdram_bankmachine1_cmd_buffer_source_payload_we <= _0299_;
      sdram_bankmachine1_cmd_buffer_source_payload_addr <= _0298_;
      sdram_bankmachine1_row <= _0313_;
      sdram_bankmachine1_row_opened <= _0317_;
      sdram_bankmachine1_twtpcon_ready <= _0321_;
      sdram_bankmachine1_twtpcon_count <= _0320_;
      sdram_bankmachine2_cmd_buffer_lookahead_level <= _0324_;
      sdram_bankmachine2_cmd_buffer_lookahead_produce <= _0325_;
      sdram_bankmachine2_cmd_buffer_lookahead_consume <= _0323_;
      sdram_bankmachine2_cmd_buffer_source_valid <= _0334_;
      sdram_bankmachine2_cmd_buffer_source_first <= _0330_;
      sdram_bankmachine2_cmd_buffer_source_last <= _0331_;
      sdram_bankmachine2_cmd_buffer_source_payload_we <= _0333_;
      sdram_bankmachine2_cmd_buffer_source_payload_addr <= _0332_;
      sdram_bankmachine2_row <= _0347_;
      sdram_bankmachine2_row_opened <= _0351_;
      sdram_bankmachine2_twtpcon_ready <= _0355_;
      sdram_bankmachine2_twtpcon_count <= _0354_;
      sdram_bankmachine3_cmd_buffer_lookahead_level <= _0358_;
      sdram_bankmachine3_cmd_buffer_lookahead_produce <= _0359_;
      sdram_bankmachine3_cmd_buffer_lookahead_consume <= _0357_;
      sdram_bankmachine3_cmd_buffer_source_valid <= _0368_;
      sdram_bankmachine3_cmd_buffer_source_first <= _0364_;
      sdram_bankmachine3_cmd_buffer_source_last <= _0365_;
      sdram_bankmachine3_cmd_buffer_source_payload_we <= _0367_;
      sdram_bankmachine3_cmd_buffer_source_payload_addr <= _0366_;
      sdram_bankmachine3_row <= _0381_;
      sdram_bankmachine3_row_opened <= _0385_;
      sdram_bankmachine3_twtpcon_ready <= _0389_;
      sdram_bankmachine3_twtpcon_count <= _0388_;
      sdram_choose_cmd_grant <= _0394_;
      sdram_choose_req_grant <= _0404_;
      sdram_tccdcon_ready <= _0473_;
      sdram_tccdcon_count <= _0472_;
      sdram_twtrcon_ready <= _0480_;
      sdram_twtrcon_count <= _0479_;
      sdram_time0 <= _0475_;
      sdram_time1 <= _0476_;
      converter_counter <= _0050_;
      converter_dat_r <= _0053_;
      cmd_consumed <= _0049_;
      wdata_consumed <= _0547_;
      uart_phy_storage <= _0539_;
      uart_phy_re <= _0529_;
      uart_phy_sink_ready <= _0534_;
      uart_phy_uart_clk_txen <= _0544_;
      uart_phy_phase_accumulator_tx <= _0528_;
      uart_phy_tx_reg <= _0542_;
      uart_phy_tx_bitcount <= _0540_;
      uart_phy_tx_busy <= _0541_;
      uart_phy_source_valid <= _0538_;
      uart_phy_source_payload_data <= _0537_;
      uart_phy_uart_clk_rxen <= _0543_;
      uart_phy_phase_accumulator_rx <= _0527_;
      uart_phy_rx_r <= _0532_;
      uart_phy_rx_reg <= _0533_;
      uart_phy_rx_bitcount <= _0530_;
      uart_phy_rx_busy <= _0531_;
      tx_pending <= _0526_;
      tx_old_trigger <= _0525_;
      rx_pending <= _0249_;
      rx_old_trigger <= _0248_;
      eventmanager_storage <= _0062_;
      eventmanager_re <= _0060_;
      tx_fifo_readable <= _0520_;
      tx_fifo_level0 <= _0518_;
      tx_fifo_produce <= _0519_;
      tx_fifo_consume <= _0517_;
      rx_fifo_readable <= _0245_;
      rx_fifo_level0 <= _0243_;
      rx_fifo_produce <= _0244_;
      rx_fifo_consume <= _0242_;
      gpio0_oe_storage <= _0064_;
      gpio0_oe_re <= _0063_;
      gpio0_out_storage <= _0066_;
      gpio0_out_re <= _0065_;
      gpio1_oe_storage <= _0072_;
      gpio1_oe_re <= _0071_;
      gpio1_out_storage <= _0074_;
      gpio1_out_re <= _0073_;
      i2c_storage <= _0080_;
      i2c_re <= _0079_;
      subfragments_converter0_state <= _0492_;
      subfragments_converter1_state <= _0494_;
      subfragments_refresher_state <= _0508_;
      subfragments_bankmachine0_state <= _0484_;
      subfragments_bankmachine1_state <= _0486_;
      subfragments_bankmachine2_state <= _0488_;
      subfragments_bankmachine3_state <= _0490_;
      subfragments_multiplexer_state <= _0500_;
      subfragments_new_master_wdata_ready <= _0505_;
      subfragments_new_master_rdata_valid0 <= _0501_;
      subfragments_new_master_rdata_valid1 <= _0502_;
      subfragments_new_master_rdata_valid2 <= _0503_;
      subfragments_new_master_rdata_valid3 <= _0504_;
      subfragments_state <= _0509_;
      libresocsim_libresocsim_adr <= _0150_;
      libresocsim_libresocsim_we <= _0156_;
      libresocsim_libresocsim_dat_w <= _0153_;
      libresocsim_grant <= _0099_;
      libresocsim_slave_sel_r <= _0176_;
      libresocsim_count <= _0093_;
      libresocsim_interface0_bank_bus_dat_r <= _0100_;
      libresocsim_interface1_bank_bus_dat_r <= _0109_;
      libresocsim_interface2_bank_bus_dat_r <= _0118_;
      libresocsim_interface3_bank_bus_dat_r <= _0119_;
      libresocsim_interface4_bank_bus_dat_r <= _0120_;
      libresocsim_interface5_bank_bus_dat_r <= _0121_;
      libresocsim_interface6_bank_bus_dat_r <= _0122_;
      libresocsim_interface7_bank_bus_dat_r <= _0123_;
      libresocsim_state <= _0177_;
      regs0 <= _0206_;
      regs1 <= _0207_;
  end
  always @* begin
    if (\initial ) begin end
    _0776_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_lookahead_level <= _0776_;
  end
  always @* begin
    if (\initial ) begin end
    _0258_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine0_cmd_buffer_lookahead_replace <= _0258_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0777_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_lookahead_produce <= _0777_;
  end
  always @* begin
    if (\initial ) begin end
    _0775_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_lookahead_consume <= _0775_;
  end
  always @* begin
    if (\initial ) begin end
    _0702_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_reset_re <= _0702_;
  end
  always @* begin
    if (\initial ) begin end
    _0778_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= _0778_;
  end
  always @* begin
    if (\initial ) begin end
    _0705_ = 32'd305419896;
  end
  always @* begin
  end
  initial begin
      libresocsim_scratch_storage <= _0705_;
  end
  always @* begin
    if (\initial ) begin end
    _0704_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_scratch_re <= _0704_;
  end
  always @* begin
    if (\initial ) begin end
    _0783_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_source_valid <= _0783_;
  end
  always @* begin
    if (\initial ) begin end
    _0779_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_source_first <= _0779_;
  end
  always @* begin
    if (\initial ) begin end
    _0780_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_source_last <= _0780_;
  end
  always @* begin
    if (\initial ) begin end
    _0782_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_source_payload_we <= _0782_;
  end
  always @* begin
    if (\initial ) begin end
    _0781_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_cmd_buffer_source_payload_addr <= _0781_;
  end
  always @* begin
    if (\initial ) begin end
    _0796_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_row <= _0796_;
  end
  always @* begin
    if (\initial ) begin end
    _0800_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_row_opened <= _0800_;
  end
  always @* begin
    if (\initial ) begin end
    _0799_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_row_open <= _0799_;
  end
  always @* begin
    if (\initial ) begin end
    _0797_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_row_close <= _0797_;
  end
  always @* begin
    if (\initial ) begin end
    _0798_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_row_col_n_addr_sel <= _0798_;
  end
  always @* begin
    if (\initial ) begin end
    _0802_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_twtpcon_ready <= _0802_;
  end
  always @* begin
    if (\initial ) begin end
    _0801_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine0_twtpcon_count <= _0801_;
  end
  always @* begin
    if (\initial ) begin end
    _0285_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine0_trccon_ready <= _0285_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0284_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine0_trascon_ready <= _0284_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0824_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_req_wdata_ready <= _0824_;
  end
  always @* begin
    if (\initial ) begin end
    _0823_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_req_rdata_valid <= _0823_;
  end
  always @* begin
    if (\initial ) begin end
    _0822_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_refresh_gnt <= _0822_;
  end
  always @* begin
    if (\initial ) begin end
    _0821_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_valid <= _0821_;
  end
  always @* begin
    if (\initial ) begin end
    _0820_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_ready <= _0820_;
  end
  always @* begin
    if (\initial ) begin end
    _0813_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_a <= _0813_;
  end
  always @* begin
    if (\initial ) begin end
    _0814_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_cas <= _0814_;
  end
  always @* begin
    if (\initial ) begin end
    _0818_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_ras <= _0818_;
  end
  always @* begin
    if (\initial ) begin end
    _0819_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_we <= _0819_;
  end
  always @* begin
    if (\initial ) begin end
    _0815_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_is_cmd <= _0815_;
  end
  always @* begin
    if (\initial ) begin end
    _0816_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_is_read <= _0816_;
  end
  always @* begin
    if (\initial ) begin end
    _0817_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_payload_is_write <= _0817_;
  end
  always @* begin
    if (\initial ) begin end
    _0803_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_auto_precharge <= _0803_;
  end
  always @* begin
    if (\initial ) begin end
    _0293_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine1_cmd_buffer_lookahead_sink_first <= _0293_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0294_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine1_cmd_buffer_lookahead_sink_last <= _0294_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0630_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      libresocsim_bus_errors <= _0630_;
  end
  always @* begin
    if (\initial ) begin end
    _0805_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_lookahead_level <= _0805_;
  end
  always @* begin
    if (\initial ) begin end
    _0292_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine1_cmd_buffer_lookahead_replace <= _0292_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0806_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_lookahead_produce <= _0806_;
  end
  always @* begin
    if (\initial ) begin end
    _0804_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_lookahead_consume <= _0804_;
  end
  always @* begin
    if (\initial ) begin end
    _0807_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= _0807_;
  end
  always @* begin
    if (\initial ) begin end
    _0684_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_interrupt <= _0684_;
  end
  always @* begin
    if (\initial ) begin end
    _0812_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_source_valid <= _0812_;
  end
  always @* begin
    if (\initial ) begin end
    _0808_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_source_first <= _0808_;
  end
  always @* begin
    if (\initial ) begin end
    _0809_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_source_last <= _0809_;
  end
  always @* begin
    if (\initial ) begin end
    _0811_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_source_payload_we <= _0811_;
  end
  always @* begin
    if (\initial ) begin end
    _0810_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_cmd_buffer_source_payload_addr <= _0810_;
  end
  always @* begin
    if (\initial ) begin end
    _0825_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_row <= _0825_;
  end
  always @* begin
    if (\initial ) begin end
    _0829_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_row_opened <= _0829_;
  end
  always @* begin
    if (\initial ) begin end
    _0828_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_row_open <= _0828_;
  end
  always @* begin
    if (\initial ) begin end
    _0826_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_row_close <= _0826_;
  end
  always @* begin
    if (\initial ) begin end
    _0827_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_row_col_n_addr_sel <= _0827_;
  end
  always @* begin
    if (\initial ) begin end
    _0000_ = _0548_;
    _0001_ = _0549_;
    _0002_ = _0550_;
    _0003_ = _0551_;
    _0004_ = _0552_;
    _0005_ = _0553_;
    _0006_ = _0554_;
    _0007_ = _0555_;
    _0008_ = _0556_;
    _0009_ = _0557_;
    _0010_ = _0558_;
    _0011_ = _0559_;
    _0192_ = libresocsim_adr;
    (* src = "ls180.v:5447.2-5448.55" *)
    casez (libresocsim_we[0])
      /* src = "ls180.v:5447.6-5447.23" */
      1'h1:
        begin
          _0548_ = libresocsim_adr;
          _0549_ = { 24'h000000, libresocsim_dat_w[7:0] };
          _0550_ = 32'd255;
        end
      default:
        begin
          _0548_ = 7'hxx;
          _0549_ = 32'hxxxxxxxx;
          _0550_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5449.2-5450.57" *)
    casez (libresocsim_we[1])
      /* src = "ls180.v:5449.6-5449.23" */
      1'h1:
        begin
          _0551_ = libresocsim_adr;
          _0552_ = { 16'h0000, libresocsim_dat_w[15:8], 8'hxx };
          _0553_ = 32'd65280;
        end
      default:
        begin
          _0551_ = 7'hxx;
          _0552_ = 32'hxxxxxxxx;
          _0553_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5451.2-5452.59" *)
    casez (libresocsim_we[2])
      /* src = "ls180.v:5451.6-5451.23" */
      1'h1:
        begin
          _0554_ = libresocsim_adr;
          _0555_ = { 8'h00, libresocsim_dat_w[23:16], 16'hxxxx };
          _0556_ = 32'd16711680;
        end
      default:
        begin
          _0554_ = 7'hxx;
          _0555_ = 32'hxxxxxxxx;
          _0556_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5453.2-5454.59" *)
    casez (libresocsim_we[3])
      /* src = "ls180.v:5453.6-5453.23" */
      1'h1:
        begin
          _0557_ = libresocsim_adr;
          _0558_ = { libresocsim_dat_w[31:24], 24'hxxxxxx };
          _0559_ = 32'd4278190080;
        end
      default:
        begin
          _0557_ = 7'hxx;
          _0558_ = 32'hxxxxxxxx;
          _0559_ = 32'd0;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memadr <= _0192_;
      _1908_ <= _0000_;
      _1909_ <= _0001_;
      _1910_ <= _0002_;
      _1911_ <= _0003_;
      _1912_ <= _0004_;
      _1913_ <= _0005_;
      _1914_ <= _0006_;
      _1915_ <= _0007_;
      _1916_ <= _0008_;
      _1917_ <= _0009_;
      _1918_ <= _0010_;
      _1919_ <= _0011_;
  end
  always @* begin
    if (\initial ) begin end
    _0831_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_twtpcon_ready <= _0831_;
  end
  always @* begin
    if (\initial ) begin end
    _0012_ = _0560_;
    _0013_ = _0561_;
    _0014_ = _0562_;
    _0015_ = _0563_;
    _0016_ = _0564_;
    _0017_ = _0565_;
    _0018_ = _0566_;
    _0019_ = _0567_;
    _0020_ = _0568_;
    _0021_ = _0569_;
    _0022_ = _0570_;
    _0023_ = _0571_;
    _0193_ = ram_adr;
    (* src = "ls180.v:5467.2-5468.41" *)
    casez (ram_we[0])
      /* src = "ls180.v:5467.6-5467.15" */
      1'h1:
        begin
          _0560_ = ram_adr;
          _0561_ = { 24'h000000, ram_dat_w[7:0] };
          _0562_ = 32'd255;
        end
      default:
        begin
          _0560_ = 5'hxx;
          _0561_ = 32'hxxxxxxxx;
          _0562_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5469.2-5470.43" *)
    casez (ram_we[1])
      /* src = "ls180.v:5469.6-5469.15" */
      1'h1:
        begin
          _0563_ = ram_adr;
          _0564_ = { 16'h0000, ram_dat_w[15:8], 8'hxx };
          _0565_ = 32'd65280;
        end
      default:
        begin
          _0563_ = 5'hxx;
          _0564_ = 32'hxxxxxxxx;
          _0565_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5471.2-5472.45" *)
    casez (ram_we[2])
      /* src = "ls180.v:5471.6-5471.15" */
      1'h1:
        begin
          _0566_ = ram_adr;
          _0567_ = { 8'h00, ram_dat_w[23:16], 16'hxxxx };
          _0568_ = 32'd16711680;
        end
      default:
        begin
          _0566_ = 5'hxx;
          _0567_ = 32'hxxxxxxxx;
          _0568_ = 32'd0;
        end
    endcase
    (* src = "ls180.v:5473.2-5474.45" *)
    casez (ram_we[3])
      /* src = "ls180.v:5473.6-5473.15" */
      1'h1:
        begin
          _0569_ = ram_adr;
          _0570_ = { ram_dat_w[31:24], 24'hxxxxxx };
          _0571_ = 32'd4278190080;
        end
      default:
        begin
          _0569_ = 5'hxx;
          _0570_ = 32'hxxxxxxxx;
          _0571_ = 32'd0;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memadr_1 <= _0193_;
      _1920_ <= _0012_;
      _1921_ <= _0013_;
      _1922_ <= _0014_;
      _1923_ <= _0015_;
      _1924_ <= _0016_;
      _1925_ <= _0017_;
      _1926_ <= _0018_;
      _1927_ <= _0019_;
      _1928_ <= _0020_;
      _1929_ <= _0021_;
      _1930_ <= _0022_;
      _1931_ <= _0023_;
  end
  always @* begin
    if (\initial ) begin end
    _0830_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine1_twtpcon_count <= _0830_;
  end
  always @* begin
    if (\initial ) begin end
    _0024_ = _0572_;
    _0025_ = _0573_;
    _0026_ = _0574_;
    _0194_ = _1896_;
    (* src = "ls180.v:5487.2-5488.119" *)
    casez (sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
      /* src = "ls180.v:5487.6-5487.55" */
      1'h1:
        begin
          _0572_ = sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr;
          _0573_ = sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
          _0574_ = 25'h1ffffff;
        end
      default:
        begin
          _0572_ = 3'hx;
          _0573_ = 25'hxxxxxxx;
          _0574_ = 25'h0000000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat <= _0194_;
      _1932_ <= _0024_;
      _1933_ <= _0025_;
      _1934_ <= _0026_;
  end
  always @* begin
    if (\initial ) begin end
    _0319_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine1_trccon_ready <= _0319_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
  end
  always @(posedge sys_clk_1) begin
  end
  always @* begin
    if (\initial ) begin end
    _0027_ = _0575_;
    _0028_ = _0576_;
    _0029_ = _0577_;
    _0195_ = _1898_;
    (* src = "ls180.v:5501.2-5502.121" *)
    casez (sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
      /* src = "ls180.v:5501.6-5501.55" */
      1'h1:
        begin
          _0575_ = sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr;
          _0576_ = sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
          _0577_ = 25'h1ffffff;
        end
      default:
        begin
          _0575_ = 3'hx;
          _0576_ = 25'hxxxxxxx;
          _0577_ = 25'h0000000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_1 <= _0195_;
      _1935_ <= _0027_;
      _1936_ <= _0028_;
      _1937_ <= _0029_;
  end
  always @* begin
    if (\initial ) begin end
  end
  always @(posedge sys_clk_1) begin
  end
  always @* begin
    if (\initial ) begin end
    _0318_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine1_trascon_ready <= _0318_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0030_ = _0578_;
    _0031_ = _0579_;
    _0032_ = _0580_;
    _0196_ = _1900_;
    (* src = "ls180.v:5515.2-5516.121" *)
    casez (sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
      /* src = "ls180.v:5515.6-5515.55" */
      1'h1:
        begin
          _0578_ = sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr;
          _0579_ = sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
          _0580_ = 25'h1ffffff;
        end
      default:
        begin
          _0578_ = 3'hx;
          _0579_ = 25'hxxxxxxx;
          _0580_ = 25'h0000000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_2 <= _0196_;
      _1938_ <= _0030_;
      _1939_ <= _0031_;
      _1940_ <= _0032_;
  end
  always @* begin
    if (\initial ) begin end
  end
  always @(posedge sys_clk_1) begin
  end
  always @* begin
    if (\initial ) begin end
    _0033_ = _0581_;
    _0034_ = _0582_;
    _0035_ = _0583_;
    _0197_ = _1902_;
    (* src = "ls180.v:5529.2-5530.121" *)
    casez (sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
      /* src = "ls180.v:5529.6-5529.55" */
      1'h1:
        begin
          _0581_ = sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr;
          _0582_ = sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
          _0583_ = 25'h1ffffff;
        end
      default:
        begin
          _0581_ = 3'hx;
          _0582_ = 25'hxxxxxxx;
          _0583_ = 25'h0000000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_3 <= _0197_;
      _1941_ <= _0033_;
      _1942_ <= _0034_;
      _1943_ <= _0035_;
  end
  always @* begin
    if (\initial ) begin end
  end
  always @(posedge sys_clk_1) begin
  end
  always @* begin
    if (\initial ) begin end
    _0036_ = _0584_;
    _0037_ = _0585_;
    _0038_ = _0586_;
    _0198_ = _1904_;
    (* src = "ls180.v:5544.2-5545.57" *)
    casez (tx_fifo_wrport_we)
      /* src = "ls180.v:5544.6-5544.23" */
      1'h1:
        begin
          _0584_ = tx_fifo_wrport_adr;
          _0585_ = tx_fifo_wrport_dat_w;
          _0586_ = 10'h3ff;
        end
      default:
        begin
          _0584_ = 4'hx;
          _0585_ = 10'hxxx;
          _0586_ = 10'h000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_4 <= _0198_;
      _1944_ <= _0036_;
      _1945_ <= _0037_;
      _1946_ <= _0038_;
  end
  always @* begin
    if (\initial ) begin end
    _0199_ = memdat_5;
    (* src = "ls180.v:5550.2-5551.45" *)
    casez (tx_fifo_rdport_re)
      /* src = "ls180.v:5550.6-5550.23" */
      1'h1:
          _0199_ = _1905_;
      default:
          /* empty */;
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_5 <= _0199_;
  end
  always @* begin
    if (\initial ) begin end
    _0039_ = _0587_;
    _0040_ = _0588_;
    _0041_ = _0589_;
    _0200_ = _1906_;
    (* src = "ls180.v:5561.2-5562.57" *)
    casez (rx_fifo_wrport_we)
      /* src = "ls180.v:5561.6-5561.23" */
      1'h1:
        begin
          _0587_ = rx_fifo_wrport_adr;
          _0588_ = rx_fifo_wrport_dat_w;
          _0589_ = 10'h3ff;
        end
      default:
        begin
          _0587_ = 4'hx;
          _0588_ = 10'hxxx;
          _0589_ = 10'h000;
        end
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_6 <= _0200_;
      _1947_ <= _0039_;
      _1948_ <= _0040_;
      _1949_ <= _0041_;
  end
  always @* begin
    if (\initial ) begin end
    _0201_ = memdat_7;
    (* src = "ls180.v:5567.2-5568.45" *)
    casez (rx_fifo_rdport_re)
      /* src = "ls180.v:5567.6-5567.23" */
      1'h1:
          _0201_ = _1907_;
      default:
          /* empty */;
    endcase
  end
  always @(posedge sys_clk_1) begin
      memdat_7 <= _0201_;
  end
  always @* begin
    if (\initial ) begin end
    _0853_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_req_wdata_ready <= _0853_;
  end
  always @* begin
    if (\initial ) begin end
    _0852_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_req_rdata_valid <= _0852_;
  end
  always @* begin
    if (\initial ) begin end
    _0851_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_refresh_gnt <= _0851_;
  end
  always @* begin
    if (\initial ) begin end
    _0850_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_valid <= _0850_;
  end
  always @* begin
    if (\initial ) begin end
    _0849_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_ready <= _0849_;
  end
  always @* begin
    if (\initial ) begin end
    _0842_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_a <= _0842_;
  end
  always @* begin
    if (\initial ) begin end
    _0843_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_cas <= _0843_;
  end
  always @* begin
    if (\initial ) begin end
    _0847_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_ras <= _0847_;
  end
  always @* begin
    if (\initial ) begin end
    _0848_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_we <= _0848_;
  end
  always @* begin
    if (\initial ) begin end
    _0844_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_is_cmd <= _0844_;
  end
  always @* begin
    if (\initial ) begin end
    _0845_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_is_read <= _0845_;
  end
  always @* begin
    if (\initial ) begin end
    _0846_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_payload_is_write <= _0846_;
  end
  always @* begin
    if (\initial ) begin end
    _0832_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_auto_precharge <= _0832_;
  end
  always @* begin
    if (\initial ) begin end
    _0327_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine2_cmd_buffer_lookahead_sink_first <= _0327_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0328_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine2_cmd_buffer_lookahead_sink_last <= _0328_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0682_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_dbus_ack <= _0682_;
  end
  always @* begin
    if (\initial ) begin end
    _0834_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_lookahead_level <= _0834_;
  end
  always @* begin
    if (\initial ) begin end
    _0326_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine2_cmd_buffer_lookahead_replace <= _0326_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0835_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_lookahead_produce <= _0835_;
  end
  always @* begin
    if (\initial ) begin end
    _0833_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_lookahead_consume <= _0833_;
  end
  always @* begin
    if (\initial ) begin end
    _0836_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= _0836_;
  end
  always @* begin
    if (\initial ) begin end
    _0144_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_dbus_err <= _0144_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0841_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_source_valid <= _0841_;
  end
  always @* begin
    if (\initial ) begin end
    _0837_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_source_first <= _0837_;
  end
  always @* begin
    if (\initial ) begin end
    _0838_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_source_last <= _0838_;
  end
  always @* begin
    if (\initial ) begin end
    _0840_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_source_payload_we <= _0840_;
  end
  always @* begin
    if (\initial ) begin end
    _0839_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_cmd_buffer_source_payload_addr <= _0839_;
  end
  always @* begin
    if (\initial ) begin end
    _0854_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_row <= _0854_;
  end
  always @* begin
    if (\initial ) begin end
    _0858_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_row_opened <= _0858_;
  end
  always @* begin
    if (\initial ) begin end
    _0857_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_row_open <= _0857_;
  end
  always @* begin
    if (\initial ) begin end
    _0855_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_row_close <= _0855_;
  end
  always @* begin
    if (\initial ) begin end
    _0856_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_row_col_n_addr_sel <= _0856_;
  end
  always @* begin
    if (\initial ) begin end
    _0860_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_twtpcon_ready <= _0860_;
  end
  always @* begin
    if (\initial ) begin end
    _0859_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine2_twtpcon_count <= _0859_;
  end
  always @* begin
    if (\initial ) begin end
    _0353_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine2_trccon_ready <= _0353_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0352_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine2_trascon_ready <= _0352_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0882_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_req_wdata_ready <= _0882_;
  end
  always @* begin
    if (\initial ) begin end
    _0881_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_req_rdata_valid <= _0881_;
  end
  always @* begin
    if (\initial ) begin end
    _0880_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_refresh_gnt <= _0880_;
  end
  always @* begin
    if (\initial ) begin end
    _0879_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_valid <= _0879_;
  end
  always @* begin
    if (\initial ) begin end
    _0878_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_ready <= _0878_;
  end
  always @* begin
    if (\initial ) begin end
    _0871_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_a <= _0871_;
  end
  always @* begin
    if (\initial ) begin end
    _0872_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_cas <= _0872_;
  end
  always @* begin
    if (\initial ) begin end
    _0876_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_ras <= _0876_;
  end
  always @* begin
    if (\initial ) begin end
    _0877_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_we <= _0877_;
  end
  always @* begin
    if (\initial ) begin end
    _0873_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_is_cmd <= _0873_;
  end
  always @* begin
    if (\initial ) begin end
    _0874_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_is_read <= _0874_;
  end
  always @* begin
    if (\initial ) begin end
    _0875_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_payload_is_write <= _0875_;
  end
  always @* begin
    if (\initial ) begin end
    _0861_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_auto_precharge <= _0861_;
  end
  always @* begin
    if (\initial ) begin end
    _0361_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine3_cmd_buffer_lookahead_sink_first <= _0361_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0362_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine3_cmd_buffer_lookahead_sink_last <= _0362_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0863_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_lookahead_level <= _0863_;
  end
  always @* begin
    if (\initial ) begin end
    _0360_ = 1'h0;
  end
  always @* begin
      sdram_bankmachine3_cmd_buffer_lookahead_replace <= _0360_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0864_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_lookahead_produce <= _0864_;
  end
  always @* begin
    if (\initial ) begin end
    _0862_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_lookahead_consume <= _0862_;
  end
  always @* begin
    if (\initial ) begin end
    _0865_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= _0865_;
  end
  always @* begin
    if (\initial ) begin end
    _0683_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_libresoc_ibus_ack <= _0683_;
  end
  always @* begin
    if (\initial ) begin end
    _0870_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_source_valid <= _0870_;
  end
  always @* begin
    if (\initial ) begin end
    _0866_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_source_first <= _0866_;
  end
  always @* begin
    if (\initial ) begin end
    _0146_ = 1'h0;
  end
  always @* begin
      libresocsim_libresoc_ibus_err <= _0146_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0867_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_source_last <= _0867_;
  end
  always @* begin
    if (\initial ) begin end
    _0869_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_source_payload_we <= _0869_;
  end
  always @* begin
    if (\initial ) begin end
    _0868_ = 22'h000000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_cmd_buffer_source_payload_addr <= _0868_;
  end
  always @* begin
    if (\initial ) begin end
    _0883_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_row <= _0883_;
  end
  always @* begin
    if (\initial ) begin end
    _0887_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_row_opened <= _0887_;
  end
  always @* begin
    if (\initial ) begin end
    _0886_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_row_open <= _0886_;
  end
  always @* begin
    if (\initial ) begin end
    _0884_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_row_close <= _0884_;
  end
  always @* begin
    if (\initial ) begin end
    _0885_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_row_col_n_addr_sel <= _0885_;
  end
  always @* begin
    if (\initial ) begin end
    _0889_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_twtpcon_ready <= _0889_;
  end
  always @* begin
    if (\initial ) begin end
    _0888_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_bankmachine3_twtpcon_count <= _0888_;
  end
  always @* begin
    if (\initial ) begin end
    _0387_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine3_trccon_ready <= _0387_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0386_ = 1'h1;
  end
  always @* begin
      sdram_bankmachine3_trascon_ready <= _0386_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0398_ = 1'h0;
  end
  always @* begin
      sdram_choose_cmd_want_reads <= _0398_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0399_ = 1'h0;
  end
  always @* begin
      sdram_choose_cmd_want_writes <= _0399_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0397_ = 1'h0;
  end
  always @* begin
      sdram_choose_cmd_want_cmds <= _0397_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0396_ = 1'h0;
  end
  always @* begin
      sdram_choose_cmd_want_activates <= _0396_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0393_ = 1'h0;
  end
  always @* begin
      sdram_choose_cmd_cmd_ready <= _0393_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0890_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_cmd_cmd_payload_cas <= _0890_;
  end
  always @* begin
    if (\initial ) begin end
    _0891_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_cmd_cmd_payload_ras <= _0891_;
  end
  always @* begin
    if (\initial ) begin end
    _0892_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_cmd_cmd_payload_we <= _0892_;
  end
  always @* begin
    if (\initial ) begin end
    _0894_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_cmd_valids <= _0894_;
  end
  always @* begin
    if (\initial ) begin end
    _0893_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_cmd_grant <= _0893_;
  end
  always @* begin
    if (\initial ) begin end
    _0902_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_want_reads <= _0902_;
  end
  always @* begin
    if (\initial ) begin end
    _0903_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_want_writes <= _0903_;
  end
  always @* begin
    if (\initial ) begin end
    _0901_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_want_activates <= _0901_;
  end
  always @* begin
    if (\initial ) begin end
    _0898_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_cmd_ready <= _0898_;
  end
  always @* begin
    if (\initial ) begin end
    _0895_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_cmd_payload_cas <= _0895_;
  end
  always @* begin
    if (\initial ) begin end
    _0896_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_cmd_payload_ras <= _0896_;
  end
  always @* begin
    if (\initial ) begin end
    _0897_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_cmd_payload_we <= _0897_;
  end
  always @* begin
    if (\initial ) begin end
    _0900_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_valids <= _0900_;
  end
  always @* begin
    if (\initial ) begin end
    _0899_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_choose_req_grant <= _0899_;
  end
  always @* begin
    if (\initial ) begin end
    _0456_ = 13'h0000;
  end
  always @* begin
      sdram_nop_a <= _0456_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0457_ = 2'h0;
  end
  always @* begin
      sdram_nop_ba <= _0457_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0956_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sdram_steerer_sel <= _0956_;
  end
  always @* begin
    if (\initial ) begin end
    _0468_ = 1'h1;
  end
  always @* begin
      sdram_steerer0 <= _0468_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0469_ = 1'h1;
  end
  always @* begin
      sdram_steerer1 <= _0469_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0478_ = 1'h1;
  end
  always @* begin
      sdram_trrdcon_ready <= _0478_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0474_ = 1'h1;
  end
  always @* begin
      sdram_tfawcon_ready <= _0474_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0959_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_tccdcon_ready <= _0959_;
  end
  always @* begin
    if (\initial ) begin end
    _0958_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_tccdcon_count <= _0958_;
  end
  always @* begin
    if (\initial ) begin end
    _0964_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_twtrcon_ready <= _0964_;
  end
  always @* begin
    if (\initial ) begin end
    _0963_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      sdram_twtrcon_count <= _0963_;
  end
  always @* begin
    if (\initial ) begin end
    _0922_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_en0 <= _0922_;
  end
  always @* begin
    if (\initial ) begin end
    _0960_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      sdram_time0 <= _0960_;
  end
  always @* begin
    if (\initial ) begin end
    _0923_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sdram_en1 <= _0923_;
  end
  always @* begin
    if (\initial ) begin end
    _0961_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      sdram_time1 <= _0961_;
  end
  always @* begin
    if (\initial ) begin end
    _1020_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      wb_sdram_ack <= _1020_;
  end
  always @* begin
    if (\initial ) begin end
    _0546_ = 1'h0;
  end
  always @* begin
      wb_sdram_err <= _0546_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0719_ = 30'h00000000;
  end
  always @* begin
  end
  initial begin
      litedram_wb_adr <= _0719_;
  end
  always @* begin
    if (\initial ) begin end
    _0721_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      litedram_wb_dat_w <= _0721_;
  end
  always @* begin
    if (\initial ) begin end
    _0722_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      litedram_wb_sel <= _0722_;
  end
  always @* begin
    if (\initial ) begin end
    _0720_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      litedram_wb_cyc <= _0720_;
  end
  always @* begin
    if (\initial ) begin end
    _0723_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      litedram_wb_stb <= _0723_;
  end
  always @* begin
    if (\initial ) begin end
    _0724_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      litedram_wb_we <= _0724_;
  end
  always @* begin
    if (\initial ) begin end
    _0602_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      converter_skip <= _0602_;
  end
  always @* begin
    if (\initial ) begin end
    _0598_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      converter_counter <= _0598_;
  end
  always @* begin
    if (\initial ) begin end
    _0601_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      converter_dat_r <= _0601_;
  end
  always @* begin
    if (\initial ) begin end
    _0597_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cmd_consumed <= _0597_;
  end
  always @* begin
    if (\initial ) begin end
    _1021_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      wdata_consumed <= _1021_;
  end
  always @* begin
    if (\initial ) begin end
    _1014_ = 32'd9895604;
  end
  always @* begin
  end
  initial begin
      uart_phy_storage <= _1014_;
  end
  always @* begin
    if (\initial ) begin end
    _1006_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_re <= _1006_;
  end
  always @* begin
    if (\initial ) begin end
    _1011_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_sink_ready <= _1011_;
  end
  always @* begin
    if (\initial ) begin end
    _1019_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_uart_clk_txen <= _1019_;
  end
  always @* begin
    if (\initial ) begin end
    _1005_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      uart_phy_phase_accumulator_tx <= _1005_;
  end
  always @* begin
    if (\initial ) begin end
    _1017_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      uart_phy_tx_reg <= _1017_;
  end
  always @* begin
    if (\initial ) begin end
    _1015_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_tx_bitcount <= _1015_;
  end
  always @* begin
    if (\initial ) begin end
    _1016_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_tx_busy <= _1016_;
  end
  always @* begin
    if (\initial ) begin end
    _1013_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_source_valid <= _1013_;
  end
  always @* begin
    if (\initial ) begin end
    _0535_ = 1'h0;
  end
  always @* begin
      uart_phy_source_first <= _0535_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0536_ = 1'h0;
  end
  always @* begin
      uart_phy_source_last <= _0536_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1012_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      uart_phy_source_payload_data <= _1012_;
  end
  always @* begin
    if (\initial ) begin end
    _1018_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_uart_clk_rxen <= _1018_;
  end
  always @* begin
    if (\initial ) begin end
    _1004_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      uart_phy_phase_accumulator_rx <= _1004_;
  end
  always @* begin
    if (\initial ) begin end
    _1009_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_rx_r <= _1009_;
  end
  always @* begin
    if (\initial ) begin end
    _1010_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      uart_phy_rx_reg <= _1010_;
  end
  always @* begin
    if (\initial ) begin end
    _1007_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_rx_bitcount <= _1007_;
  end
  always @* begin
    if (\initial ) begin end
    _1008_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      uart_phy_rx_busy <= _1008_;
  end
  always @* begin
    if (\initial ) begin end
    _1003_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      tx_pending <= _1003_;
  end
  always @* begin
    if (\initial ) begin end
    _0996_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      tx_clear <= _0996_;
  end
  always @* begin
    if (\initial ) begin end
    _1002_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      tx_old_trigger <= _1002_;
  end
  always @* begin
    if (\initial ) begin end
    _0769_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rx_pending <= _0769_;
  end
  always @* begin
    if (\initial ) begin end
    _0762_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rx_clear <= _0762_;
  end
  always @* begin
    if (\initial ) begin end
    _0768_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rx_old_trigger <= _0768_;
  end
  always @* begin
    if (\initial ) begin end
    _0609_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      eventmanager_status_w <= _0609_;
  end
  always @* begin
    if (\initial ) begin end
    _0607_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      eventmanager_pending_w <= _0607_;
  end
  always @* begin
    if (\initial ) begin end
    _0610_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      eventmanager_storage <= _0610_;
  end
  always @* begin
    if (\initial ) begin end
    _0608_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      eventmanager_re <= _0608_;
  end
  always @* begin
    if (\initial ) begin end
    _0522_ = 1'h0;
  end
  always @* begin
      tx_fifo_sink_first <= _0522_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0523_ = 1'h0;
  end
  always @* begin
      tx_fifo_sink_last <= _0523_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1000_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      tx_fifo_readable <= _1000_;
  end
  always @* begin
    if (\initial ) begin end
    _0998_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      tx_fifo_level0 <= _0998_;
  end
  always @* begin
    if (\initial ) begin end
    _0521_ = 1'h0;
  end
  always @* begin
      tx_fifo_replace <= _0521_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0999_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      tx_fifo_produce <= _0999_;
  end
  always @* begin
    if (\initial ) begin end
    _0997_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      tx_fifo_consume <= _0997_;
  end
  always @* begin
    if (\initial ) begin end
    _1001_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      tx_fifo_wrport_adr <= _1001_;
  end
  always @* begin
    if (\initial ) begin end
    _0766_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rx_fifo_readable <= _0766_;
  end
  always @* begin
    if (\initial ) begin end
    _0764_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      rx_fifo_level0 <= _0764_;
  end
  always @* begin
    if (\initial ) begin end
    _0246_ = 1'h0;
  end
  always @* begin
      rx_fifo_replace <= _0246_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0765_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      rx_fifo_produce <= _0765_;
  end
  always @* begin
    if (\initial ) begin end
    _0763_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      rx_fifo_consume <= _0763_;
  end
  always @* begin
    if (\initial ) begin end
    _0767_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      rx_fifo_wrport_adr <= _0767_;
  end
  always @* begin
    if (\initial ) begin end
    _0208_ = 1'h0;
  end
  always @* begin
      reset <= _0208_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0612_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_oe_storage <= _0612_;
  end
  always @* begin
    if (\initial ) begin end
    _0611_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      gpio0_oe_re <= _0611_;
  end
  always @* begin
    if (\initial ) begin end
    _0618_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_status <= _0618_;
  end
  always @* begin
    if (\initial ) begin end
    _0614_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_out_storage <= _0614_;
  end
  always @* begin
    if (\initial ) begin end
    _0613_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      gpio0_out_re <= _0613_;
  end
  always @* begin
    if (\initial ) begin end
    _0615_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_pads_gpio0i <= _0615_;
  end
  always @* begin
    if (\initial ) begin end
    _0616_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_pads_gpio0o <= _0616_;
  end
  always @* begin
    if (\initial ) begin end
    _0617_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio0_pads_gpio0oe <= _0617_;
  end
  always @* begin
    if (\initial ) begin end
    _0620_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_oe_storage <= _0620_;
  end
  always @* begin
    if (\initial ) begin end
    _0619_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      gpio1_oe_re <= _0619_;
  end
  always @* begin
    if (\initial ) begin end
    _0626_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_status <= _0626_;
  end
  always @* begin
    if (\initial ) begin end
    _0622_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_out_storage <= _0622_;
  end
  always @* begin
    if (\initial ) begin end
    _0621_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      gpio1_out_re <= _0621_;
  end
  always @* begin
    if (\initial ) begin end
    _0623_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_pads_gpio1i <= _0623_;
  end
  always @* begin
    if (\initial ) begin end
    _0624_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_pads_gpio1o <= _0624_;
  end
  always @* begin
    if (\initial ) begin end
    _0625_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      gpio1_pads_gpio1oe <= _0625_;
  end
  always @* begin
    if (\initial ) begin end
    _0606_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      eint_tmp <= _0606_;
  end
  always @* begin
    if (\initial ) begin end
    _0605_ = 40'h0000000000;
  end
  always @* begin
  end
  initial begin
      dummy <= _0605_;
  end
  always @* begin
    if (\initial ) begin end
    _0628_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      i2c_storage <= _0628_;
  end
  always @* begin
    if (\initial ) begin end
    _0627_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      i2c_re <= _0627_;
  end
  always @* begin
    if (\initial ) begin end
    _0976_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_converter0_state <= _0976_;
  end
  always @* begin
    if (\initial ) begin end
    _0975_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_converter0_next_state <= _0975_;
  end
  always @* begin
    if (\initial ) begin end
    _0632_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter0_counter_subfragments_converter0_next_value <= _0632_;
  end
  always @* begin
    if (\initial ) begin end
    _0633_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter0_counter_subfragments_converter0_next_value_ce <= _0633_;
  end
  always @* begin
    if (\initial ) begin end
    _0978_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_converter1_state <= _0978_;
  end
  always @* begin
    if (\initial ) begin end
    _0977_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_converter1_next_state <= _0977_;
  end
  always @* begin
    if (\initial ) begin end
    _0637_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter1_counter_subfragments_converter1_next_value <= _0637_;
  end
  always @* begin
    if (\initial ) begin end
    _0638_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      libresocsim_converter1_counter_subfragments_converter1_next_value_ce <= _0638_;
  end
  always @* begin
    if (\initial ) begin end
    _0988_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_refresher_state <= _0988_;
  end
  always @* begin
    if (\initial ) begin end
    _0987_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      subfragments_refresher_next_state <= _0987_;
  end
  assign libresocsim_libresoc_reset = libresocsim_reset;
  assign libresocsim_libresoc_jtag_tck = jtag_tck;
  assign libresocsim_libresoc_jtag_tms = jtag_tms;
  assign libresocsim_libresoc_jtag_tdi = jtag_tdi;
  assign jtag_tdo = libresocsim_libresoc_jtag_tdo;
  assign nc_1 = nc;
  assign libresocsim_bus_error = libresocsim_error;
  assign libresocsim_converter0_reset = _1972_;
  assign libresocsim_libresoc_ibus_dat_r = { libresocsim_interface0_converted_interface_dat_r, libresocsim_converter0_dat_r[63:32] };
  assign libresocsim_converter1_reset = _1975_;
  assign libresocsim_libresoc_dbus_dat_r = { libresocsim_interface1_converted_interface_dat_r, libresocsim_converter1_dat_r[63:32] };
  assign libresocsim_reset = libresocsim_reset_re;
  assign libresocsim_bus_errors_status = libresocsim_bus_errors;
  assign libresocsim_adr = libresocsim_ram_bus_adr[6:0];
  assign libresocsim_ram_bus_dat_r = libresocsim_dat_r;
  assign libresocsim_dat_w = libresocsim_ram_bus_dat_w;
  assign libresocsim_zero_trigger = _1950_;
  assign libresocsim_eventmanager_status_w = libresocsim_zero_status;
  assign libresocsim_eventmanager_pending_w = libresocsim_zero_pending;
  assign libresocsim_irq = _1068_;
  assign libresocsim_zero_status = libresocsim_zero_trigger;
  assign ram_adr = ram_bus_ram_bus_adr[4:0];
  assign ram_bus_ram_bus_dat_r = ram_dat_r;
  assign ram_dat_w = ram_bus_ram_bus_dat_w;
  assign sys_clk_1 = sys_clk;
  assign por_clk = sys_clk;
  assign sys_rst_1 = int_rst;
  assign dfi_p0_address = sdram_master_p0_address;
  assign dfi_p0_bank = sdram_master_p0_bank;
  assign dfi_p0_cas_n = sdram_master_p0_cas_n;
  assign dfi_p0_cs_n = sdram_master_p0_cs_n;
  assign dfi_p0_ras_n = sdram_master_p0_ras_n;
  assign dfi_p0_we_n = sdram_master_p0_we_n;
  assign dfi_p0_cke = sdram_master_p0_cke;
  assign dfi_p0_odt = sdram_master_p0_odt;
  assign dfi_p0_reset_n = sdram_master_p0_reset_n;
  assign dfi_p0_act_n = sdram_master_p0_act_n;
  assign dfi_p0_wrdata = sdram_master_p0_wrdata;
  assign dfi_p0_wrdata_en = sdram_master_p0_wrdata_en;
  assign dfi_p0_wrdata_mask = sdram_master_p0_wrdata_mask;
  assign dfi_p0_rddata_en = sdram_master_p0_rddata_en;
  assign sdram_master_p0_rddata = dfi_p0_rddata;
  assign sdram_master_p0_rddata_valid = dfi_p0_rddata_valid;
  assign sdram_slave_p0_address = sdram_dfi_p0_address;
  assign sdram_slave_p0_bank = sdram_dfi_p0_bank;
  assign sdram_slave_p0_cas_n = sdram_dfi_p0_cas_n;
  assign sdram_slave_p0_cs_n = sdram_dfi_p0_cs_n;
  assign sdram_slave_p0_ras_n = sdram_dfi_p0_ras_n;
  assign sdram_slave_p0_we_n = sdram_dfi_p0_we_n;
  assign sdram_slave_p0_cke = sdram_dfi_p0_cke;
  assign sdram_slave_p0_odt = sdram_dfi_p0_odt;
  assign sdram_slave_p0_reset_n = sdram_dfi_p0_reset_n;
  assign sdram_slave_p0_act_n = sdram_dfi_p0_act_n;
  assign sdram_slave_p0_wrdata = sdram_dfi_p0_wrdata;
  assign sdram_slave_p0_wrdata_en = sdram_dfi_p0_wrdata_en;
  assign sdram_slave_p0_wrdata_mask = sdram_dfi_p0_wrdata_mask;
  assign sdram_slave_p0_rddata_en = sdram_dfi_p0_rddata_en;
  assign sdram_dfi_p0_rddata = sdram_slave_p0_rddata;
  assign sdram_dfi_p0_rddata_valid = sdram_slave_p0_rddata_valid;
  assign sdram_inti_p0_cke = sdram_cke_1;
  assign sdram_inti_p0_odt = sdram_odt;
  assign sdram_inti_p0_reset_n = sdram_reset_n;
  assign sdram_inti_p0_address = sdram_address_storage;
  assign sdram_inti_p0_bank = sdram_baddress_storage;
  assign sdram_inti_p0_wrdata_en = _1081_;
  assign sdram_inti_p0_rddata_en = _1082_;
  assign sdram_inti_p0_wrdata = sdram_wrdata_storage;
  assign sdram_inti_p0_wrdata_mask = 2'h0;
  assign sdram_bankmachine0_req_valid = sdram_interface_bank0_valid;
  assign sdram_interface_bank0_ready = sdram_bankmachine0_req_ready;
  assign sdram_bankmachine0_req_we = sdram_interface_bank0_we;
  assign sdram_bankmachine0_req_addr = sdram_interface_bank0_addr;
  assign sdram_interface_bank0_lock = sdram_bankmachine0_req_lock;
  assign sdram_interface_bank0_wdata_ready = sdram_bankmachine0_req_wdata_ready;
  assign sdram_interface_bank0_rdata_valid = sdram_bankmachine0_req_rdata_valid;
  assign sdram_bankmachine1_req_valid = sdram_interface_bank1_valid;
  assign sdram_interface_bank1_ready = sdram_bankmachine1_req_ready;
  assign sdram_bankmachine1_req_we = sdram_interface_bank1_we;
  assign sdram_bankmachine1_req_addr = sdram_interface_bank1_addr;
  assign sdram_interface_bank1_lock = sdram_bankmachine1_req_lock;
  assign sdram_interface_bank1_wdata_ready = sdram_bankmachine1_req_wdata_ready;
  assign sdram_interface_bank1_rdata_valid = sdram_bankmachine1_req_rdata_valid;
  assign sdram_bankmachine2_req_valid = sdram_interface_bank2_valid;
  assign sdram_interface_bank2_ready = sdram_bankmachine2_req_ready;
  assign sdram_bankmachine2_req_we = sdram_interface_bank2_we;
  assign sdram_bankmachine2_req_addr = sdram_interface_bank2_addr;
  assign sdram_interface_bank2_lock = sdram_bankmachine2_req_lock;
  assign sdram_interface_bank2_wdata_ready = sdram_bankmachine2_req_wdata_ready;
  assign sdram_interface_bank2_rdata_valid = sdram_bankmachine2_req_rdata_valid;
  assign sdram_bankmachine3_req_valid = sdram_interface_bank3_valid;
  assign sdram_interface_bank3_ready = sdram_bankmachine3_req_ready;
  assign sdram_bankmachine3_req_we = sdram_interface_bank3_we;
  assign sdram_bankmachine3_req_addr = sdram_interface_bank3_addr;
  assign sdram_interface_bank3_lock = sdram_bankmachine3_req_lock;
  assign sdram_interface_bank3_wdata_ready = sdram_bankmachine3_req_wdata_ready;
  assign sdram_interface_bank3_rdata_valid = sdram_bankmachine3_req_rdata_valid;
  assign sdram_timer_wait = _1982_;
  assign sdram_postponer_req_i = sdram_timer_done0;
  assign sdram_wants_refresh = sdram_postponer_req_o;
  assign sdram_timer_done1 = _1647_;
  assign sdram_timer_done0 = sdram_timer_done1;
  assign sdram_timer_count0 = sdram_timer_count1;
  assign sdram_sequencer_start1 = _2175_;
  assign sdram_sequencer_done0 = _1083_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = sdram_bankmachine0_req_valid;
  assign sdram_bankmachine0_req_ready = sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
  assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine0_req_we;
  assign sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine0_req_addr;
  assign sdram_bankmachine0_cmd_buffer_sink_valid = sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_ready = sdram_bankmachine0_cmd_buffer_sink_ready;
  assign sdram_bankmachine0_cmd_buffer_sink_first = sdram_bankmachine0_cmd_buffer_lookahead_source_first;
  assign sdram_bankmachine0_cmd_buffer_sink_last = sdram_bankmachine0_cmd_buffer_lookahead_source_last;
  assign sdram_bankmachine0_cmd_buffer_sink_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
  assign sdram_bankmachine0_cmd_buffer_sink_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
  assign sdram_bankmachine0_cmd_buffer_source_ready = _2176_;
  assign sdram_bankmachine0_req_lock = _2177_;
  assign sdram_bankmachine0_row_hit = _1649_;
  assign sdram_bankmachine0_cmd_payload_ba = 2'h0;
  assign sdram_bankmachine0_twtpcon_valid = _1085_;
  assign sdram_bankmachine0_trccon_valid = _1087_;
  assign sdram_bankmachine0_trascon_valid = _1089_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = { sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we };
  assign { sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
  assign sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
  assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
  assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
  assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
  assign sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_valid = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_first = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_last = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
  assign sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
  assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
  assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = _1091_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_do_read = _1092_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine0_cmd_buffer_lookahead_consume;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = _1953_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = _1954_;
  assign sdram_bankmachine0_cmd_buffer_sink_ready = _2180_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = sdram_bankmachine1_req_valid;
  assign sdram_bankmachine1_req_ready = sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
  assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine1_req_we;
  assign sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine1_req_addr;
  assign sdram_bankmachine1_cmd_buffer_sink_valid = sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_ready = sdram_bankmachine1_cmd_buffer_sink_ready;
  assign sdram_bankmachine1_cmd_buffer_sink_first = sdram_bankmachine1_cmd_buffer_lookahead_source_first;
  assign sdram_bankmachine1_cmd_buffer_sink_last = sdram_bankmachine1_cmd_buffer_lookahead_source_last;
  assign sdram_bankmachine1_cmd_buffer_sink_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
  assign sdram_bankmachine1_cmd_buffer_sink_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
  assign sdram_bankmachine1_cmd_buffer_source_ready = _2181_;
  assign sdram_bankmachine1_req_lock = _2182_;
  assign sdram_bankmachine1_row_hit = _1651_;
  assign sdram_bankmachine1_cmd_payload_ba = 2'h1;
  assign sdram_bankmachine1_twtpcon_valid = _1097_;
  assign sdram_bankmachine1_trccon_valid = _1099_;
  assign sdram_bankmachine1_trascon_valid = _1101_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = { sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we };
  assign { sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
  assign sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
  assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
  assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
  assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
  assign sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_valid = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_first = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_last = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
  assign sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
  assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
  assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = _1103_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_do_read = _1104_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine1_cmd_buffer_lookahead_consume;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = _1956_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = _1957_;
  assign sdram_bankmachine1_cmd_buffer_sink_ready = _2185_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = sdram_bankmachine2_req_valid;
  assign sdram_bankmachine2_req_ready = sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
  assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine2_req_we;
  assign sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine2_req_addr;
  assign sdram_bankmachine2_cmd_buffer_sink_valid = sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_ready = sdram_bankmachine2_cmd_buffer_sink_ready;
  assign sdram_bankmachine2_cmd_buffer_sink_first = sdram_bankmachine2_cmd_buffer_lookahead_source_first;
  assign sdram_bankmachine2_cmd_buffer_sink_last = sdram_bankmachine2_cmd_buffer_lookahead_source_last;
  assign sdram_bankmachine2_cmd_buffer_sink_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
  assign sdram_bankmachine2_cmd_buffer_sink_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
  assign sdram_bankmachine2_cmd_buffer_source_ready = _2186_;
  assign sdram_bankmachine2_req_lock = _2187_;
  assign sdram_bankmachine2_row_hit = _1653_;
  assign sdram_bankmachine2_cmd_payload_ba = 2'h2;
  assign sdram_bankmachine2_twtpcon_valid = _1109_;
  assign sdram_bankmachine2_trccon_valid = _1111_;
  assign sdram_bankmachine2_trascon_valid = _1113_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = { sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we };
  assign { sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
  assign sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
  assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
  assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
  assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
  assign sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_valid = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_first = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_last = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
  assign sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
  assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
  assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = _1115_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_do_read = _1116_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine2_cmd_buffer_lookahead_consume;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = _1959_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = _1960_;
  assign sdram_bankmachine2_cmd_buffer_sink_ready = _2190_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = sdram_bankmachine3_req_valid;
  assign sdram_bankmachine3_req_ready = sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
  assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = sdram_bankmachine3_req_we;
  assign sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = sdram_bankmachine3_req_addr;
  assign sdram_bankmachine3_cmd_buffer_sink_valid = sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_ready = sdram_bankmachine3_cmd_buffer_sink_ready;
  assign sdram_bankmachine3_cmd_buffer_sink_first = sdram_bankmachine3_cmd_buffer_lookahead_source_first;
  assign sdram_bankmachine3_cmd_buffer_sink_last = sdram_bankmachine3_cmd_buffer_lookahead_source_last;
  assign sdram_bankmachine3_cmd_buffer_sink_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
  assign sdram_bankmachine3_cmd_buffer_sink_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
  assign sdram_bankmachine3_cmd_buffer_source_ready = _2191_;
  assign sdram_bankmachine3_req_lock = _2192_;
  assign sdram_bankmachine3_row_hit = _1655_;
  assign sdram_bankmachine3_cmd_payload_ba = 2'h3;
  assign sdram_bankmachine3_twtpcon_valid = _1121_;
  assign sdram_bankmachine3_trccon_valid = _1123_;
  assign sdram_bankmachine3_trascon_valid = _1125_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = { sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we };
  assign { sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
  assign sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
  assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
  assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
  assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
  assign sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_valid = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_first = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_last = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
  assign sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
  assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
  assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = _1127_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_do_read = _1128_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = sdram_bankmachine3_cmd_buffer_lookahead_consume;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = _1962_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = _1963_;
  assign sdram_bankmachine3_cmd_buffer_sink_ready = _2195_;
  assign sdram_choose_req_want_cmds = 1'h1;
  assign sdram_trrdcon_valid = _1135_;
  assign sdram_tfawcon_valid = _1139_;
  assign sdram_ras_allowed = _1140_;
  assign sdram_tccdcon_valid = _1142_;
  assign sdram_cas_allowed = sdram_tccdcon_ready;
  assign sdram_twtrcon_valid = _1144_;
  assign sdram_read_available = _2199_;
  assign sdram_write_available = _2202_;
  assign sdram_max_time0 = _1657_;
  assign sdram_max_time1 = _1658_;
  assign sdram_bankmachine0_refresh_req = sdram_cmd_valid;
  assign sdram_bankmachine1_refresh_req = sdram_cmd_valid;
  assign sdram_bankmachine2_refresh_req = sdram_cmd_valid;
  assign sdram_bankmachine3_refresh_req = sdram_cmd_valid;
  assign sdram_go_to_refresh = _1155_;
  assign sdram_interface_rdata = sdram_dfi_p0_rddata;
  assign sdram_dfi_p0_wrdata = sdram_interface_wdata;
  assign sdram_dfi_p0_wrdata_mask = _1995_;
  assign sdram_choose_cmd_request = sdram_choose_cmd_valids;
  assign sdram_choose_cmd_cmd_valid = rhs_array_muxed0;
  assign sdram_choose_cmd_cmd_payload_a = rhs_array_muxed1;
  assign sdram_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
  assign sdram_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
  assign sdram_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
  assign sdram_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
  assign sdram_choose_cmd_ce = _2211_;
  assign sdram_choose_req_request = sdram_choose_req_valids;
  assign sdram_choose_req_cmd_valid = rhs_array_muxed6;
  assign sdram_choose_req_cmd_payload_a = rhs_array_muxed7;
  assign sdram_choose_req_cmd_payload_ba = rhs_array_muxed8;
  assign sdram_choose_req_cmd_payload_is_read = rhs_array_muxed9;
  assign sdram_choose_req_cmd_payload_is_write = rhs_array_muxed10;
  assign sdram_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
  assign sdram_choose_req_ce = _2220_;
  assign sdram_dfi_p0_reset_n = 1'h1;
  assign sdram_dfi_p0_cke = sdram_steerer0;
  assign sdram_dfi_p0_odt = sdram_steerer1;
  assign subfragments_roundrobin0_request = _1230_;
  assign subfragments_roundrobin0_ce = _1231_;
  assign sdram_interface_bank0_addr = rhs_array_muxed12;
  assign sdram_interface_bank0_we = rhs_array_muxed13;
  assign sdram_interface_bank0_valid = rhs_array_muxed14;
  assign subfragments_roundrobin1_request = _1236_;
  assign subfragments_roundrobin1_ce = _1237_;
  assign sdram_interface_bank1_addr = rhs_array_muxed15;
  assign sdram_interface_bank1_we = rhs_array_muxed16;
  assign sdram_interface_bank1_valid = rhs_array_muxed17;
  assign subfragments_roundrobin2_request = _1242_;
  assign subfragments_roundrobin2_ce = _1243_;
  assign sdram_interface_bank2_addr = rhs_array_muxed18;
  assign sdram_interface_bank2_we = rhs_array_muxed19;
  assign sdram_interface_bank2_valid = rhs_array_muxed20;
  assign subfragments_roundrobin3_request = _1248_;
  assign subfragments_roundrobin3_ce = _1249_;
  assign sdram_interface_bank3_addr = rhs_array_muxed21;
  assign sdram_interface_bank3_we = rhs_array_muxed22;
  assign sdram_interface_bank3_valid = rhs_array_muxed23;
  assign port_cmd_ready = _2252_;
  assign port_wdata_ready = subfragments_new_master_wdata_ready;
  assign port_rdata_valid = subfragments_new_master_rdata_valid3;
  assign port_rdata_payload_data = sdram_interface_rdata;
  assign subfragments_roundrobin0_grant = 1'h0;
  assign subfragments_roundrobin1_grant = 1'h0;
  assign subfragments_roundrobin2_grant = 1'h0;
  assign subfragments_roundrobin3_grant = 1'h0;
  assign converter_reset = _2046_;
  assign wb_sdram_dat_r = { litedram_wb_dat_r, converter_dat_r[31:16] };
  assign port_cmd_payload_addr = _2363_[23:0];
  assign port_cmd_payload_we = litedram_wb_we;
  assign port_wdata_payload_data = litedram_wb_dat_w;
  assign port_wdata_payload_we = litedram_wb_sel;
  assign litedram_wb_dat_r = port_rdata_payload_data;
  assign port_flush = _2049_;
  assign port_cmd_last = _2050_;
  assign port_cmd_valid = _1277_;
  assign port_wdata_valid = _1279_;
  assign port_rdata_ready = _1280_;
  assign litedram_wb_ack = _1283_;
  assign ack_cmd = _2257_;
  assign ack_wdata = _2258_;
  assign ack_rdata = _1286_;
  assign uart_sink_valid = uart_phy_source_valid;
  assign uart_phy_source_ready = uart_sink_ready;
  assign uart_sink_first = uart_phy_source_first;
  assign uart_sink_last = uart_phy_source_last;
  assign uart_sink_payload_data = uart_phy_source_payload_data;
  assign uart_phy_sink_valid = uart_source_valid;
  assign uart_source_ready = uart_phy_sink_ready;
  assign uart_phy_sink_first = uart_source_first;
  assign uart_phy_sink_last = uart_source_last;
  assign uart_phy_sink_payload_data = uart_source_payload_data;
  assign tx_fifo_sink_valid = rxtx_re;
  assign tx_fifo_sink_payload_data = rxtx_r;
  assign txfull_status = _2055_;
  assign txempty_status = _2056_;
  assign uart_source_valid = tx_fifo_source_valid;
  assign tx_fifo_source_ready = uart_source_ready;
  assign uart_source_first = tx_fifo_source_first;
  assign uart_source_last = tx_fifo_source_last;
  assign uart_source_payload_data = tx_fifo_source_payload_data;
  assign tx_trigger = _2057_;
  assign rx_fifo_sink_valid = uart_sink_valid;
  assign uart_sink_ready = rx_fifo_sink_ready;
  assign rx_fifo_sink_first = uart_sink_first;
  assign rx_fifo_sink_last = uart_sink_last;
  assign rx_fifo_sink_payload_data = uart_sink_payload_data;
  assign rxempty_status = _2058_;
  assign rxfull_status = _2059_;
  assign rxtx_w = rx_fifo_source_payload_data;
  assign rx_fifo_source_ready = _2259_;
  assign rx_trigger = _2060_;
  assign irq = _2260_;
  assign tx_status = tx_trigger;
  assign rx_status = rx_trigger;
  assign tx_fifo_syncfifo_din = { tx_fifo_fifo_in_last, tx_fifo_fifo_in_first, tx_fifo_fifo_in_payload_data };
  assign { tx_fifo_fifo_out_last, tx_fifo_fifo_out_first, tx_fifo_fifo_out_payload_data } = tx_fifo_syncfifo_dout;
  assign tx_fifo_sink_ready = tx_fifo_syncfifo_writable;
  assign tx_fifo_syncfifo_we = tx_fifo_sink_valid;
  assign tx_fifo_fifo_in_first = tx_fifo_sink_first;
  assign tx_fifo_fifo_in_last = tx_fifo_sink_last;
  assign tx_fifo_fifo_in_payload_data = tx_fifo_sink_payload_data;
  assign tx_fifo_source_valid = tx_fifo_readable;
  assign tx_fifo_source_first = tx_fifo_fifo_out_first;
  assign tx_fifo_source_last = tx_fifo_fifo_out_last;
  assign tx_fifo_source_payload_data = tx_fifo_fifo_out_payload_data;
  assign tx_fifo_re = tx_fifo_source_ready;
  assign tx_fifo_syncfifo_re = _1292_;
  assign tx_fifo_level1 = _1025_;
  assign tx_fifo_wrport_dat_w = tx_fifo_syncfifo_din;
  assign tx_fifo_wrport_we = _1293_;
  assign tx_fifo_do_read = _1294_;
  assign tx_fifo_rdport_adr = tx_fifo_consume;
  assign tx_fifo_syncfifo_dout = tx_fifo_rdport_dat_r;
  assign tx_fifo_rdport_re = tx_fifo_do_read;
  assign tx_fifo_syncfifo_writable = _1964_;
  assign tx_fifo_syncfifo_readable = _1965_;
  assign rx_fifo_syncfifo_din = { rx_fifo_fifo_in_last, rx_fifo_fifo_in_first, rx_fifo_fifo_in_payload_data };
  assign { rx_fifo_fifo_out_last, rx_fifo_fifo_out_first, rx_fifo_fifo_out_payload_data } = rx_fifo_syncfifo_dout;
  assign rx_fifo_sink_ready = rx_fifo_syncfifo_writable;
  assign rx_fifo_syncfifo_we = rx_fifo_sink_valid;
  assign rx_fifo_fifo_in_first = rx_fifo_sink_first;
  assign rx_fifo_fifo_in_last = rx_fifo_sink_last;
  assign rx_fifo_fifo_in_payload_data = rx_fifo_sink_payload_data;
  assign rx_fifo_source_valid = rx_fifo_readable;
  assign rx_fifo_source_first = rx_fifo_fifo_out_first;
  assign rx_fifo_source_last = rx_fifo_fifo_out_last;
  assign rx_fifo_source_payload_data = rx_fifo_fifo_out_payload_data;
  assign rx_fifo_re = rx_fifo_source_ready;
  assign rx_fifo_syncfifo_re = _1295_;
  assign rx_fifo_level1 = _1026_;
  assign rx_fifo_wrport_dat_w = rx_fifo_syncfifo_din;
  assign rx_fifo_wrport_we = _1296_;
  assign rx_fifo_do_read = _1297_;
  assign rx_fifo_rdport_adr = rx_fifo_consume;
  assign rx_fifo_syncfifo_dout = rx_fifo_rdport_dat_r;
  assign rx_fifo_rdport_re = rx_fifo_do_read;
  assign rx_fifo_syncfifo_writable = _1966_;
  assign rx_fifo_syncfifo_readable = _1967_;
  assign libresocsim_libresoc_constraintmanager_i2c_scl = i2c_scl_1;
  assign libresocsim_libresoc_constraintmanager_i2c_sda_oe = i2c_oe;
  assign libresocsim_libresoc_constraintmanager_i2c_sda_o = i2c_sda0;
  assign i2c_sda1 = libresocsim_libresoc_constraintmanager_i2c_sda_i;
  assign libresocsim_shared_adr = rhs_array_muxed24;
  assign libresocsim_shared_dat_w = rhs_array_muxed25;
  assign libresocsim_shared_sel = rhs_array_muxed26;
  assign libresocsim_shared_cyc = rhs_array_muxed27;
  assign libresocsim_shared_stb = rhs_array_muxed28;
  assign libresocsim_shared_we = rhs_array_muxed29;
  assign libresocsim_shared_cti = rhs_array_muxed30;
  assign libresocsim_shared_bte = rhs_array_muxed31;
  assign libresocsim_interface0_converted_interface_dat_r = libresocsim_shared_dat_r;
  assign libresocsim_interface1_converted_interface_dat_r = libresocsim_shared_dat_r;
  assign libresocsim_libresoc_jtag_wb_dat_r = libresocsim_shared_dat_r;
  assign libresocsim_interface0_converted_interface_ack = _1300_;
  assign libresocsim_interface1_converted_interface_ack = _1301_;
  assign libresocsim_libresoc_jtag_wb_ack = _1302_;
  assign libresocsim_interface0_converted_interface_err = _1303_;
  assign libresocsim_interface1_converted_interface_err = _1304_;
  assign libresocsim_libresoc_jtag_wb_err = _1305_;
  assign libresocsim_request = { libresocsim_libresoc_jtag_wb_cyc, libresocsim_interface1_converted_interface_cyc, libresocsim_interface0_converted_interface_cyc };
  assign libresocsim_ram_bus_adr = libresocsim_shared_adr;
  assign libresocsim_ram_bus_dat_w = libresocsim_shared_dat_w;
  assign libresocsim_ram_bus_sel = libresocsim_shared_sel;
  assign libresocsim_ram_bus_stb = libresocsim_shared_stb;
  assign libresocsim_ram_bus_we = libresocsim_shared_we;
  assign libresocsim_ram_bus_cti = libresocsim_shared_cti;
  assign libresocsim_ram_bus_bte = libresocsim_shared_bte;
  assign ram_bus_ram_bus_adr = libresocsim_shared_adr;
  assign ram_bus_ram_bus_dat_w = libresocsim_shared_dat_w;
  assign ram_bus_ram_bus_sel = libresocsim_shared_sel;
  assign ram_bus_ram_bus_stb = libresocsim_shared_stb;
  assign ram_bus_ram_bus_we = libresocsim_shared_we;
  assign ram_bus_ram_bus_cti = libresocsim_shared_cti;
  assign ram_bus_ram_bus_bte = libresocsim_shared_bte;
  assign libresocsim_libresoc_xics_icp_adr = libresocsim_shared_adr;
  assign libresocsim_libresoc_xics_icp_dat_w = libresocsim_shared_dat_w;
  assign libresocsim_libresoc_xics_icp_sel = libresocsim_shared_sel;
  assign libresocsim_libresoc_xics_icp_stb = libresocsim_shared_stb;
  assign libresocsim_libresoc_xics_icp_we = libresocsim_shared_we;
  assign libresocsim_libresoc_xics_icp_cti = libresocsim_shared_cti;
  assign libresocsim_libresoc_xics_icp_bte = libresocsim_shared_bte;
  assign libresocsim_libresoc_xics_ics_adr = libresocsim_shared_adr;
  assign libresocsim_libresoc_xics_ics_dat_w = libresocsim_shared_dat_w;
  assign libresocsim_libresoc_xics_ics_sel = libresocsim_shared_sel;
  assign libresocsim_libresoc_xics_ics_stb = libresocsim_shared_stb;
  assign libresocsim_libresoc_xics_ics_we = libresocsim_shared_we;
  assign libresocsim_libresoc_xics_ics_cti = libresocsim_shared_cti;
  assign libresocsim_libresoc_xics_ics_bte = libresocsim_shared_bte;
  assign wb_sdram_adr = libresocsim_shared_adr;
  assign wb_sdram_dat_w = libresocsim_shared_dat_w;
  assign wb_sdram_sel = libresocsim_shared_sel;
  assign wb_sdram_stb = libresocsim_shared_stb;
  assign wb_sdram_we = libresocsim_shared_we;
  assign wb_sdram_cti = libresocsim_shared_cti;
  assign wb_sdram_bte = libresocsim_shared_bte;
  assign libresocsim_libresocsim_wishbone_adr = libresocsim_shared_adr;
  assign libresocsim_libresocsim_wishbone_dat_w = libresocsim_shared_dat_w;
  assign libresocsim_libresocsim_wishbone_sel = libresocsim_shared_sel;
  assign libresocsim_libresocsim_wishbone_stb = libresocsim_shared_stb;
  assign libresocsim_libresocsim_wishbone_we = libresocsim_shared_we;
  assign libresocsim_libresocsim_wishbone_cti = libresocsim_shared_cti;
  assign libresocsim_libresocsim_wishbone_bte = libresocsim_shared_bte;
  assign libresocsim_ram_bus_cyc = _1306_;
  assign ram_bus_ram_bus_cyc = _1307_;
  assign libresocsim_libresoc_xics_icp_cyc = _1308_;
  assign libresocsim_libresoc_xics_ics_cyc = _1309_;
  assign wb_sdram_cyc = _1310_;
  assign libresocsim_libresocsim_wishbone_cyc = _1311_;
  assign libresocsim_shared_err = _2269_;
  assign libresocsim_wait = _1313_;
  assign libresocsim_done = _1733_;
  assign libresocsim_csrbank0_sel = _1734_;
  assign libresocsim_csrbank0_reset0_r = libresocsim_interface0_bank_bus_dat_w[0];
  assign libresocsim_csrbank0_reset0_re = _1321_;
  assign libresocsim_csrbank0_reset0_we = _1323_;
  assign libresocsim_csrbank0_scratch3_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_scratch3_re = _1325_;
  assign libresocsim_csrbank0_scratch3_we = _1327_;
  assign libresocsim_csrbank0_scratch2_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_scratch2_re = _1329_;
  assign libresocsim_csrbank0_scratch2_we = _1331_;
  assign libresocsim_csrbank0_scratch1_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_scratch1_re = _1333_;
  assign libresocsim_csrbank0_scratch1_we = _1335_;
  assign libresocsim_csrbank0_scratch0_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_scratch0_re = _1337_;
  assign libresocsim_csrbank0_scratch0_we = _1339_;
  assign libresocsim_csrbank0_bus_errors3_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_bus_errors3_re = _1341_;
  assign libresocsim_csrbank0_bus_errors3_we = _1343_;
  assign libresocsim_csrbank0_bus_errors2_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_bus_errors2_re = _1345_;
  assign libresocsim_csrbank0_bus_errors2_we = _1347_;
  assign libresocsim_csrbank0_bus_errors1_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_bus_errors1_re = _1349_;
  assign libresocsim_csrbank0_bus_errors1_we = _1351_;
  assign libresocsim_csrbank0_bus_errors0_r = libresocsim_interface0_bank_bus_dat_w;
  assign libresocsim_csrbank0_bus_errors0_re = _1353_;
  assign libresocsim_csrbank0_bus_errors0_we = _1355_;
  assign libresocsim_csrbank0_reset0_w = libresocsim_reset_storage;
  assign libresocsim_csrbank0_scratch3_w = libresocsim_scratch_storage[31:24];
  assign libresocsim_csrbank0_scratch2_w = libresocsim_scratch_storage[23:16];
  assign libresocsim_csrbank0_scratch1_w = libresocsim_scratch_storage[15:8];
  assign libresocsim_csrbank0_scratch0_w = libresocsim_scratch_storage[7:0];
  assign libresocsim_csrbank0_bus_errors3_w = libresocsim_bus_errors_status[31:24];
  assign libresocsim_csrbank0_bus_errors2_w = libresocsim_bus_errors_status[23:16];
  assign libresocsim_csrbank0_bus_errors1_w = libresocsim_bus_errors_status[15:8];
  assign libresocsim_csrbank0_bus_errors0_w = libresocsim_bus_errors_status[7:0];
  assign libresocsim_bus_errors_we = libresocsim_csrbank0_bus_errors0_we;
  assign libresocsim_csrbank1_sel = _1753_;
  assign libresocsim_csrbank1_oe0_r = libresocsim_interface1_bank_bus_dat_w;
  assign libresocsim_csrbank1_oe0_re = _1357_;
  assign libresocsim_csrbank1_oe0_we = _1359_;
  assign libresocsim_csrbank1_in_r = libresocsim_interface1_bank_bus_dat_w;
  assign libresocsim_csrbank1_in_re = _1361_;
  assign libresocsim_csrbank1_in_we = _1363_;
  assign libresocsim_csrbank1_out0_r = libresocsim_interface1_bank_bus_dat_w;
  assign libresocsim_csrbank1_out0_re = _1365_;
  assign libresocsim_csrbank1_out0_we = _1367_;
  assign libresocsim_csrbank1_oe0_w = gpio0_oe_storage;
  assign libresocsim_csrbank1_in_w = gpio0_status;
  assign gpio0_we = libresocsim_csrbank1_in_we;
  assign libresocsim_csrbank1_out0_w = gpio0_out_storage;
  assign libresocsim_csrbank2_sel = _1760_;
  assign libresocsim_csrbank2_oe0_r = libresocsim_interface2_bank_bus_dat_w;
  assign libresocsim_csrbank2_oe0_re = _1369_;
  assign libresocsim_csrbank2_oe0_we = _1371_;
  assign libresocsim_csrbank2_in_r = libresocsim_interface2_bank_bus_dat_w;
  assign libresocsim_csrbank2_in_re = _1373_;
  assign libresocsim_csrbank2_in_we = _1375_;
  assign libresocsim_csrbank2_out0_r = libresocsim_interface2_bank_bus_dat_w;
  assign libresocsim_csrbank2_out0_re = _1377_;
  assign libresocsim_csrbank2_out0_we = _1379_;
  assign libresocsim_csrbank2_oe0_w = gpio1_oe_storage;
  assign libresocsim_csrbank2_in_w = gpio1_status;
  assign gpio1_we = libresocsim_csrbank2_in_we;
  assign libresocsim_csrbank2_out0_w = gpio1_out_storage;
  assign libresocsim_csrbank3_sel = _1767_;
  assign libresocsim_csrbank3_w0_r = libresocsim_interface3_bank_bus_dat_w[2:0];
  assign libresocsim_csrbank3_w0_re = _1381_;
  assign libresocsim_csrbank3_w0_we = _1383_;
  assign libresocsim_csrbank3_r_r = libresocsim_interface3_bank_bus_dat_w[0];
  assign libresocsim_csrbank3_r_re = _1385_;
  assign libresocsim_csrbank3_r_we = _1387_;
  assign i2c_scl_1 = i2c_storage[0];
  assign i2c_oe = i2c_storage[1];
  assign i2c_sda0 = i2c_storage[2];
  assign libresocsim_csrbank3_w0_w = i2c_storage;
  assign i2c_status = i2c_sda1;
  assign libresocsim_csrbank3_r_w = i2c_status;
  assign i2c_we = libresocsim_csrbank3_r_we;
  assign libresocsim_csrbank4_sel = _1772_;
  assign libresocsim_csrbank4_dfii_control0_r = libresocsim_interface4_bank_bus_dat_w[3:0];
  assign libresocsim_csrbank4_dfii_control0_re = _1389_;
  assign libresocsim_csrbank4_dfii_control0_we = _1391_;
  assign libresocsim_csrbank4_dfii_pi0_command0_r = libresocsim_interface4_bank_bus_dat_w[5:0];
  assign libresocsim_csrbank4_dfii_pi0_command0_re = _1393_;
  assign libresocsim_csrbank4_dfii_pi0_command0_we = _1395_;
  assign sdram_command_issue_r = libresocsim_interface4_bank_bus_dat_w[0];
  assign sdram_command_issue_re = _1397_;
  assign sdram_command_issue_we = _1399_;
  assign libresocsim_csrbank4_dfii_pi0_address1_r = libresocsim_interface4_bank_bus_dat_w[4:0];
  assign libresocsim_csrbank4_dfii_pi0_address1_re = _1401_;
  assign libresocsim_csrbank4_dfii_pi0_address1_we = _1403_;
  assign libresocsim_csrbank4_dfii_pi0_address0_r = libresocsim_interface4_bank_bus_dat_w;
  assign libresocsim_csrbank4_dfii_pi0_address0_re = _1405_;
  assign libresocsim_csrbank4_dfii_pi0_address0_we = _1407_;
  assign libresocsim_csrbank4_dfii_pi0_baddress0_r = libresocsim_interface4_bank_bus_dat_w[1:0];
  assign libresocsim_csrbank4_dfii_pi0_baddress0_re = _1409_;
  assign libresocsim_csrbank4_dfii_pi0_baddress0_we = _1411_;
  assign libresocsim_csrbank4_dfii_pi0_wrdata1_r = libresocsim_interface4_bank_bus_dat_w;
  assign libresocsim_csrbank4_dfii_pi0_wrdata1_re = _1413_;
  assign libresocsim_csrbank4_dfii_pi0_wrdata1_we = _1415_;
  assign libresocsim_csrbank4_dfii_pi0_wrdata0_r = libresocsim_interface4_bank_bus_dat_w;
  assign libresocsim_csrbank4_dfii_pi0_wrdata0_re = _1417_;
  assign libresocsim_csrbank4_dfii_pi0_wrdata0_we = _1419_;
  assign libresocsim_csrbank4_dfii_pi0_rddata1_r = libresocsim_interface4_bank_bus_dat_w;
  assign libresocsim_csrbank4_dfii_pi0_rddata1_re = _1421_;
  assign libresocsim_csrbank4_dfii_pi0_rddata1_we = _1423_;
  assign libresocsim_csrbank4_dfii_pi0_rddata0_r = libresocsim_interface4_bank_bus_dat_w;
  assign libresocsim_csrbank4_dfii_pi0_rddata0_re = _1425_;
  assign libresocsim_csrbank4_dfii_pi0_rddata0_we = _1427_;
  assign sdram_sel = sdram_storage[0];
  assign sdram_cke_1 = sdram_storage[1];
  assign sdram_odt = sdram_storage[2];
  assign sdram_reset_n = sdram_storage[3];
  assign libresocsim_csrbank4_dfii_control0_w = sdram_storage;
  assign libresocsim_csrbank4_dfii_pi0_command0_w = sdram_command_storage;
  assign libresocsim_csrbank4_dfii_pi0_address1_w = sdram_address_storage[12:8];
  assign libresocsim_csrbank4_dfii_pi0_address0_w = sdram_address_storage[7:0];
  assign libresocsim_csrbank4_dfii_pi0_baddress0_w = sdram_baddress_storage;
  assign libresocsim_csrbank4_dfii_pi0_wrdata1_w = sdram_wrdata_storage[15:8];
  assign libresocsim_csrbank4_dfii_pi0_wrdata0_w = sdram_wrdata_storage[7:0];
  assign libresocsim_csrbank4_dfii_pi0_rddata1_w = sdram_status[15:8];
  assign libresocsim_csrbank4_dfii_pi0_rddata0_w = sdram_status[7:0];
  assign sdram_we = libresocsim_csrbank4_dfii_pi0_rddata0_we;
  assign libresocsim_csrbank5_sel = _1793_;
  assign libresocsim_csrbank5_load3_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_load3_re = _1429_;
  assign libresocsim_csrbank5_load3_we = _1431_;
  assign libresocsim_csrbank5_load2_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_load2_re = _1433_;
  assign libresocsim_csrbank5_load2_we = _1435_;
  assign libresocsim_csrbank5_load1_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_load1_re = _1437_;
  assign libresocsim_csrbank5_load1_we = _1439_;
  assign libresocsim_csrbank5_load0_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_load0_re = _1441_;
  assign libresocsim_csrbank5_load0_we = _1443_;
  assign libresocsim_csrbank5_reload3_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_reload3_re = _1445_;
  assign libresocsim_csrbank5_reload3_we = _1447_;
  assign libresocsim_csrbank5_reload2_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_reload2_re = _1449_;
  assign libresocsim_csrbank5_reload2_we = _1451_;
  assign libresocsim_csrbank5_reload1_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_reload1_re = _1453_;
  assign libresocsim_csrbank5_reload1_we = _1455_;
  assign libresocsim_csrbank5_reload0_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_reload0_re = _1457_;
  assign libresocsim_csrbank5_reload0_we = _1459_;
  assign libresocsim_csrbank5_en0_r = libresocsim_interface5_bank_bus_dat_w[0];
  assign libresocsim_csrbank5_en0_re = _1461_;
  assign libresocsim_csrbank5_en0_we = _1463_;
  assign libresocsim_csrbank5_update_value0_r = libresocsim_interface5_bank_bus_dat_w[0];
  assign libresocsim_csrbank5_update_value0_re = _1465_;
  assign libresocsim_csrbank5_update_value0_we = _1467_;
  assign libresocsim_csrbank5_value3_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_value3_re = _1469_;
  assign libresocsim_csrbank5_value3_we = _1471_;
  assign libresocsim_csrbank5_value2_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_value2_re = _1473_;
  assign libresocsim_csrbank5_value2_we = _1475_;
  assign libresocsim_csrbank5_value1_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_value1_re = _1477_;
  assign libresocsim_csrbank5_value1_we = _1479_;
  assign libresocsim_csrbank5_value0_r = libresocsim_interface5_bank_bus_dat_w;
  assign libresocsim_csrbank5_value0_re = _1481_;
  assign libresocsim_csrbank5_value0_we = _1483_;
  assign libresocsim_eventmanager_status_r = libresocsim_interface5_bank_bus_dat_w[0];
  assign libresocsim_eventmanager_status_re = _1485_;
  assign libresocsim_eventmanager_status_we = _1487_;
  assign libresocsim_eventmanager_pending_r = libresocsim_interface5_bank_bus_dat_w[0];
  assign libresocsim_eventmanager_pending_re = _1489_;
  assign libresocsim_eventmanager_pending_we = _1491_;
  assign libresocsim_csrbank5_ev_enable0_r = libresocsim_interface5_bank_bus_dat_w[0];
  assign libresocsim_csrbank5_ev_enable0_re = _1493_;
  assign libresocsim_csrbank5_ev_enable0_we = _1495_;
  assign libresocsim_csrbank5_load3_w = libresocsim_load_storage[31:24];
  assign libresocsim_csrbank5_load2_w = libresocsim_load_storage[23:16];
  assign libresocsim_csrbank5_load1_w = libresocsim_load_storage[15:8];
  assign libresocsim_csrbank5_load0_w = libresocsim_load_storage[7:0];
  assign libresocsim_csrbank5_reload3_w = libresocsim_reload_storage[31:24];
  assign libresocsim_csrbank5_reload2_w = libresocsim_reload_storage[23:16];
  assign libresocsim_csrbank5_reload1_w = libresocsim_reload_storage[15:8];
  assign libresocsim_csrbank5_reload0_w = libresocsim_reload_storage[7:0];
  assign libresocsim_csrbank5_en0_w = libresocsim_en_storage;
  assign libresocsim_csrbank5_update_value0_w = libresocsim_update_value_storage;
  assign libresocsim_csrbank5_value3_w = libresocsim_value_status[31:24];
  assign libresocsim_csrbank5_value2_w = libresocsim_value_status[23:16];
  assign libresocsim_csrbank5_value1_w = libresocsim_value_status[15:8];
  assign libresocsim_csrbank5_value0_w = libresocsim_value_status[7:0];
  assign libresocsim_value_we = libresocsim_csrbank5_value0_we;
  assign libresocsim_csrbank5_ev_enable0_w = libresocsim_eventmanager_storage;
  assign libresocsim_csrbank6_sel = _1828_;
  assign rxtx_r = libresocsim_interface6_bank_bus_dat_w;
  assign rxtx_re = _1497_;
  assign rxtx_we = _1499_;
  assign libresocsim_csrbank6_txfull_r = libresocsim_interface6_bank_bus_dat_w[0];
  assign libresocsim_csrbank6_txfull_re = _1501_;
  assign libresocsim_csrbank6_txfull_we = _1503_;
  assign libresocsim_csrbank6_rxempty_r = libresocsim_interface6_bank_bus_dat_w[0];
  assign libresocsim_csrbank6_rxempty_re = _1505_;
  assign libresocsim_csrbank6_rxempty_we = _1507_;
  assign eventmanager_status_r = libresocsim_interface6_bank_bus_dat_w[1:0];
  assign eventmanager_status_re = _1509_;
  assign eventmanager_status_we = _1511_;
  assign eventmanager_pending_r = libresocsim_interface6_bank_bus_dat_w[1:0];
  assign eventmanager_pending_re = _1513_;
  assign eventmanager_pending_we = _1515_;
  assign libresocsim_csrbank6_ev_enable0_r = libresocsim_interface6_bank_bus_dat_w[1:0];
  assign libresocsim_csrbank6_ev_enable0_re = _1517_;
  assign libresocsim_csrbank6_ev_enable0_we = _1519_;
  assign libresocsim_csrbank6_txempty_r = libresocsim_interface6_bank_bus_dat_w[0];
  assign libresocsim_csrbank6_txempty_re = _1521_;
  assign libresocsim_csrbank6_txempty_we = _1523_;
  assign libresocsim_csrbank6_rxfull_r = libresocsim_interface6_bank_bus_dat_w[0];
  assign libresocsim_csrbank6_rxfull_re = _1525_;
  assign libresocsim_csrbank6_rxfull_we = _1527_;
  assign libresocsim_csrbank6_txfull_w = txfull_status;
  assign txfull_we = libresocsim_csrbank6_txfull_we;
  assign libresocsim_csrbank6_rxempty_w = rxempty_status;
  assign rxempty_we = libresocsim_csrbank6_rxempty_we;
  assign libresocsim_csrbank6_ev_enable0_w = eventmanager_storage;
  assign libresocsim_csrbank6_txempty_w = txempty_status;
  assign txempty_we = libresocsim_csrbank6_txempty_we;
  assign libresocsim_csrbank6_rxfull_w = rxfull_status;
  assign rxfull_we = libresocsim_csrbank6_rxfull_we;
  assign libresocsim_csrbank7_sel = _1845_;
  assign libresocsim_csrbank7_tuning_word3_r = libresocsim_interface7_bank_bus_dat_w;
  assign libresocsim_csrbank7_tuning_word3_re = _1529_;
  assign libresocsim_csrbank7_tuning_word3_we = _1531_;
  assign libresocsim_csrbank7_tuning_word2_r = libresocsim_interface7_bank_bus_dat_w;
  assign libresocsim_csrbank7_tuning_word2_re = _1533_;
  assign libresocsim_csrbank7_tuning_word2_we = _1535_;
  assign libresocsim_csrbank7_tuning_word1_r = libresocsim_interface7_bank_bus_dat_w;
  assign libresocsim_csrbank7_tuning_word1_re = _1537_;
  assign libresocsim_csrbank7_tuning_word1_we = _1539_;
  assign libresocsim_csrbank7_tuning_word0_r = libresocsim_interface7_bank_bus_dat_w;
  assign libresocsim_csrbank7_tuning_word0_re = _1541_;
  assign libresocsim_csrbank7_tuning_word0_we = _1543_;
  assign libresocsim_csrbank7_tuning_word3_w = uart_phy_storage[31:24];
  assign libresocsim_csrbank7_tuning_word2_w = uart_phy_storage[23:16];
  assign libresocsim_csrbank7_tuning_word1_w = uart_phy_storage[15:8];
  assign libresocsim_csrbank7_tuning_word0_w = uart_phy_storage[7:0];
  assign libresocsim_csr_interconnect_adr = libresocsim_libresocsim_adr;
  assign libresocsim_csr_interconnect_we = libresocsim_libresocsim_we;
  assign libresocsim_csr_interconnect_dat_w = libresocsim_libresocsim_dat_w;
  assign libresocsim_libresocsim_dat_r = libresocsim_csr_interconnect_dat_r;
  assign libresocsim_interface0_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface1_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface2_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface3_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface4_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface5_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface6_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface7_bank_bus_adr = libresocsim_csr_interconnect_adr;
  assign libresocsim_interface0_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface1_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface2_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface3_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface4_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface5_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface6_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface7_bank_bus_we = libresocsim_csr_interconnect_we;
  assign libresocsim_interface0_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface1_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface2_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface3_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface4_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface5_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface6_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_interface7_bank_bus_dat_w = libresocsim_csr_interconnect_dat_w;
  assign libresocsim_csr_interconnect_dat_r = _2286_;
  assign sdrio_clk = sys_clk_1;
  assign sdrio_clk_1 = sys_clk_1;
  assign sdrio_clk_2 = sys_clk_1;
  assign sdrio_clk_3 = sys_clk_1;
  assign sdrio_clk_4 = sys_clk_1;
  assign sdrio_clk_5 = sys_clk_1;
  assign sdrio_clk_6 = sys_clk_1;
  assign sdrio_clk_7 = sys_clk_1;
  assign sdrio_clk_8 = sys_clk_1;
  assign sdrio_clk_9 = sys_clk_1;
  assign sdrio_clk_10 = sys_clk_1;
  assign sdrio_clk_11 = sys_clk_1;
  assign sdrio_clk_12 = sys_clk_1;
  assign sdrio_clk_13 = sys_clk_1;
  assign sdrio_clk_14 = sys_clk_1;
  assign sdrio_clk_15 = sys_clk_1;
  assign sdrio_clk_16 = sys_clk_1;
  assign sdrio_clk_17 = sys_clk_1;
  assign sdrio_clk_18 = sys_clk_1;
  assign sdrio_clk_19 = sys_clk_1;
  assign sdrio_clk_20 = sys_clk_1;
  assign sdrio_clk_21 = sys_clk_1;
  assign sdrio_clk_22 = sys_clk_1;
  assign sdrio_clk_23 = sys_clk_1;
  assign sdrio_clk_24 = sys_clk_1;
  assign sdrio_clk_25 = sys_clk_1;
  assign sdrio_clk_26 = sys_clk_1;
  assign sdrio_clk_27 = sys_clk_1;
  assign sdrio_clk_28 = sys_clk_1;
  assign sdrio_clk_29 = sys_clk_1;
  assign sdrio_clk_30 = sys_clk_1;
  assign sdrio_clk_31 = sys_clk_1;
  assign sdrio_clk_32 = sys_clk_1;
  assign sdrio_clk_33 = sys_clk_1;
  assign sdrio_clk_34 = sys_clk_1;
  assign sdrio_clk_35 = sys_clk_1;
  assign sdrio_clk_36 = sys_clk_1;
  assign sdrio_clk_37 = sys_clk_1;
  assign sdrio_clk_38 = sys_clk_1;
  assign sdrio_clk_39 = sys_clk_1;
  assign sdrio_clk_40 = sys_clk_1;
  assign sdrio_clk_41 = sys_clk_1;
  assign sdrio_clk_42 = sys_clk_1;
  assign sdrio_clk_43 = sys_clk_1;
  assign sdrio_clk_44 = sys_clk_1;
  assign sdrio_clk_45 = sys_clk_1;
  assign sdrio_clk_46 = sys_clk_1;
  assign sdrio_clk_47 = sys_clk_1;
  assign sdrio_clk_48 = sys_clk_1;
  assign sdrio_clk_49 = sys_clk_1;
  assign sdrio_clk_50 = sys_clk_1;
  assign sdrio_clk_51 = sys_clk_1;
  assign sdrio_clk_52 = sys_clk_1;
  assign sdrio_clk_53 = sys_clk_1;
  assign sdrio_clk_54 = sys_clk_1;
  assign sdrio_clk_55 = sys_clk_1;
  assign sdrio_clk_56 = sys_clk_1;
  assign sdrio_clk_57 = sys_clk_1;
  assign sdrio_clk_58 = sys_clk_1;
  assign sdrio_clk_59 = sys_clk_1;
  assign sdrio_clk_60 = sys_clk_1;
  assign sdrio_clk_61 = sys_clk_1;
  assign sdrio_clk_62 = sys_clk_1;
  assign sdrio_clk_63 = sys_clk_1;
  assign sdrio_clk_64 = sys_clk_1;
  assign sdrio_clk_65 = sys_clk_1;
  assign sdrio_clk_66 = sys_clk_1;
  assign sdrio_clk_67 = sys_clk_1;
  assign sdrio_clk_68 = sys_clk_1;
  assign sdrio_clk_69 = sys_clk_1;
  assign sdrio_clk_70 = sys_clk_1;
  assign uart_phy_rx = regs1;
  assign sdrio_clk_71 = sys_clk_1;
  assign sdrio_clk_72 = sys_clk_1;
  assign sdrio_clk_73 = sys_clk_1;
  assign sdrio_clk_74 = sys_clk_1;
  assign sdrio_clk_75 = sys_clk_1;
  assign sdrio_clk_76 = sys_clk_1;
  assign sdrio_clk_77 = sys_clk_1;
  assign sdrio_clk_78 = sys_clk_1;
  assign sdrio_clk_79 = sys_clk_1;
  assign sdrio_clk_80 = sys_clk_1;
  assign sdrio_clk_81 = sys_clk_1;
  assign sdrio_clk_82 = sys_clk_1;
  assign sdrio_clk_83 = sys_clk_1;
  assign sdrio_clk_84 = sys_clk_1;
  assign sdrio_clk_85 = sys_clk_1;
  assign sdrio_clk_86 = sys_clk_1;
  assign sdrio_clk_87 = sys_clk_1;
  assign sdrio_clk_88 = sys_clk_1;
  assign sdrio_clk_89 = sys_clk_1;
  assign sdrio_clk_90 = sys_clk_1;
  assign sdrio_clk_91 = sys_clk_1;
  assign sdrio_clk_92 = sys_clk_1;
  assign sdrio_clk_93 = sys_clk_1;
  assign sdrio_clk_94 = sys_clk_1;
  assign sdrio_clk_95 = sys_clk_1;
  assign sdrio_clk_96 = sys_clk_1;
  assign sdrio_clk_97 = sys_clk_1;
  assign sdrio_clk_98 = sys_clk_1;
  assign sdrio_clk_99 = sys_clk_1;
  assign sdrio_clk_100 = sys_clk_1;
  assign sdrio_clk_101 = sys_clk_1;
  assign sdrio_clk_102 = sys_clk_1;
  assign sdrio_clk_103 = sys_clk_1;
  assign sdrio_clk_104 = sys_clk_1;
  assign sdrio_clk_105 = sys_clk_1;
  assign sdrio_clk_106 = sys_clk_1;
  assign sdrio_clk_107 = sys_clk_1;
  assign sdrio_clk_108 = sys_clk_1;
  assign sdrio_clk_109 = sys_clk_1;
  assign sdrio_clk_110 = sys_clk_1;
  assign sdrio_clk_111 = sys_clk_1;
  assign sdrio_clk_112 = sys_clk_1;
  assign sdrio_clk_113 = sys_clk_1;
  assign sdrio_clk_114 = sys_clk_1;
  assign sdrio_clk_115 = sys_clk_1;
  assign sdrio_clk_116 = sys_clk_1;
  assign sdrio_clk_117 = sys_clk_1;
  assign sdrio_clk_118 = sys_clk_1;
  assign libresocsim_dat_r = _1894_;
  assign ram_dat_r = _1895_;
  assign sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
  assign sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = _1897_;
  assign sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
  assign sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = _1899_;
  assign sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
  assign sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = _1901_;
  assign sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
  assign sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = _1903_;
  assign tx_fifo_wrport_dat_r = memdat_4;
  assign tx_fifo_rdport_dat_r = memdat_5;
  assign rx_fifo_wrport_dat_r = memdat_6;
  assign rx_fifo_rdport_dat_r = memdat_7;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.lsd_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:146916.1-146974.10" *)
module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:146917.7-146917.20" *)
  reg _00_;
  (* src = "libresoc.v:146962.3-146970.6" *)
  reg _01_;
  (* src = "libresoc.v:146960.3-146961.27" *)
  reg _02_;
  (* src = "libresoc.v:146962.3-146970.6" *)
  reg _03_;
  (* src = "libresoc.v:146939.7-146939.19" *)
  reg _04_;
  (* src = "libresoc.v:146952.17-146952.96" *)
  wire _05_;
  (* src = "libresoc.v:146957.17-146957.96" *)
  wire _06_;
  (* src = "libresoc.v:146954.18-146954.93" *)
  wire _07_;
  (* src = "libresoc.v:146956.17-146956.92" *)
  wire _08_;
  (* src = "libresoc.v:146959.17-146959.92" *)
  wire _09_;
  (* src = "libresoc.v:146953.18-146953.98" *)
  wire _10_;
  (* src = "libresoc.v:146955.18-146955.99" *)
  wire _11_;
  (* src = "libresoc.v:146958.17-146958.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:146917.7-146917.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_lsd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_lsd;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_lsd;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_lsd;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_lsd;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_lsd;
  assign _11_ = q_lsd | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_lsd;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:146963.5-146963.29" *)
    casez (\initial )
      /* src = "libresoc.v:146963.9-146963.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_lsd = \$15 ;
  assign qn_lsd = \$13 ;
  assign q_lsd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.lsmem" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:146978.1-147512.10" *)
module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_o, x_ld_i, x_st_i, m_valid_i, x_valid_i, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:147366.3-147391.6" *)
  reg [44:0] _000_;
  (* src = "libresoc.v:147216.3-147217.35" *)
  reg [44:0] _001_;
  (* src = "libresoc.v:147226.3-147253.6" *)
  reg _002_;
  (* src = "libresoc.v:147224.3-147225.35" *)
  reg _003_;
  (* src = "libresoc.v:147418.3-147443.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:147212.3-147213.39" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:147310.3-147340.6" *)
  reg [7:0] _006_;
  (* src = "libresoc.v:147220.3-147221.35" *)
  reg [7:0] _007_;
  (* src = "libresoc.v:147254.3-147281.6" *)
  reg _008_;
  (* src = "libresoc.v:147222.3-147223.35" *)
  reg _009_;
  (* src = "libresoc.v:147392.3-147417.6" *)
  reg _010_;
  (* src = "libresoc.v:147214.3-147215.33" *)
  reg _011_;
  (* src = "libresoc.v:146979.7-146979.20" *)
  reg _012_;
  (* src = "libresoc.v:147490.3-147509.6" *)
  reg [44:0] _013_;
  (* src = "libresoc.v:147206.3-147207.39" *)
  reg [44:0] _014_;
  (* src = "libresoc.v:147292.3-147309.6" *)
  reg _015_;
  (* src = "libresoc.v:147341.3-147365.6" *)
  reg [63:0] _016_;
  (* src = "libresoc.v:147218.3-147219.39" *)
  reg [63:0] _017_;
  (* src = "libresoc.v:147444.3-147466.6" *)
  reg _018_;
  (* src = "libresoc.v:147210.3-147211.41" *)
  reg _019_;
  (* src = "libresoc.v:147467.3-147489.6" *)
  reg _020_;
  (* src = "libresoc.v:147208.3-147209.43" *)
  reg _021_;
  (* src = "libresoc.v:147282.3-147291.6" *)
  reg _022_;
  (* src = "libresoc.v:147366.3-147391.6" *)
  reg [44:0] _023_;
  (* src = "libresoc.v:147084.14-147084.42" *)
  reg [44:0] _024_;
  (* src = "libresoc.v:147226.3-147253.6" *)
  reg _025_;
  (* src = "libresoc.v:147089.7-147089.23" *)
  reg _026_;
  (* src = "libresoc.v:147418.3-147443.6" *)
  reg [63:0] _027_;
  (* src = "libresoc.v:147096.14-147096.48" *)
  reg [63:0] _028_;
  (* src = "libresoc.v:147310.3-147340.6" *)
  reg [7:0] _029_;
  (* src = "libresoc.v:147103.13-147103.30" *)
  reg [7:0] _030_;
  (* src = "libresoc.v:147254.3-147281.6" *)
  reg _031_;
  (* src = "libresoc.v:147108.7-147108.23" *)
  reg _032_;
  (* src = "libresoc.v:147392.3-147417.6" *)
  reg _033_;
  (* src = "libresoc.v:147113.7-147113.22" *)
  reg _034_;
  (* src = "libresoc.v:147490.3-147509.6" *)
  reg [44:0] _035_;
  (* src = "libresoc.v:147117.14-147117.44" *)
  reg [44:0] _036_;
  (* src = "libresoc.v:147292.3-147309.6" *)
  reg _037_;
  (* src = "libresoc.v:147341.3-147365.6" *)
  reg [63:0] _038_;
  (* src = "libresoc.v:147124.14-147124.48" *)
  reg [63:0] _039_;
  (* src = "libresoc.v:147444.3-147466.6" *)
  reg _040_;
  (* src = "libresoc.v:147128.7-147128.26" *)
  reg _041_;
  (* src = "libresoc.v:147467.3-147489.6" *)
  reg _042_;
  (* src = "libresoc.v:147134.7-147134.27" *)
  reg _043_;
  (* src = "libresoc.v:147282.3-147291.6" *)
  reg _044_;
  (* src = "libresoc.v:147366.3-147391.6" *)
  reg [44:0] _045_;
  (* src = "libresoc.v:147226.3-147253.6" *)
  reg _046_;
  (* src = "libresoc.v:147418.3-147443.6" *)
  reg [63:0] _047_;
  (* src = "libresoc.v:147310.3-147340.6" *)
  reg [7:0] _048_;
  (* src = "libresoc.v:147254.3-147281.6" *)
  reg _049_;
  (* src = "libresoc.v:147392.3-147417.6" *)
  reg _050_;
  (* src = "libresoc.v:147490.3-147509.6" *)
  reg [44:0] _051_;
  (* src = "libresoc.v:147292.3-147309.6" *)
  reg _052_;
  (* src = "libresoc.v:147341.3-147365.6" *)
  reg [63:0] _053_;
  (* src = "libresoc.v:147444.3-147466.6" *)
  reg _054_;
  (* src = "libresoc.v:147467.3-147489.6" *)
  reg _055_;
  (* src = "libresoc.v:147366.3-147391.6" *)
  reg [44:0] _056_;
  (* src = "libresoc.v:147226.3-147253.6" *)
  reg _057_;
  (* src = "libresoc.v:147418.3-147443.6" *)
  reg [63:0] _058_;
  (* src = "libresoc.v:147310.3-147340.6" *)
  reg [7:0] _059_;
  (* src = "libresoc.v:147254.3-147281.6" *)
  reg _060_;
  (* src = "libresoc.v:147392.3-147417.6" *)
  reg _061_;
  (* src = "libresoc.v:147490.3-147509.6" *)
  reg [44:0] _062_;
  (* src = "libresoc.v:147341.3-147365.6" *)
  reg [63:0] _063_;
  (* src = "libresoc.v:147444.3-147466.6" *)
  reg _064_;
  (* src = "libresoc.v:147467.3-147489.6" *)
  reg _065_;
  (* src = "libresoc.v:147226.3-147253.6" *)
  reg _066_;
  (* src = "libresoc.v:147310.3-147340.6" *)
  reg [7:0] _067_;
  (* src = "libresoc.v:147254.3-147281.6" *)
  reg _068_;
  (* src = "libresoc.v:147341.3-147365.6" *)
  reg [63:0] _069_;
  (* src = "libresoc.v:147162.18-147162.116" *)
  wire _070_;
  (* src = "libresoc.v:147165.18-147165.111" *)
  wire _071_;
  (* src = "libresoc.v:147170.18-147170.116" *)
  wire _072_;
  (* src = "libresoc.v:147172.18-147172.111" *)
  wire _073_;
  (* src = "libresoc.v:147174.17-147174.114" *)
  wire _074_;
  (* src = "libresoc.v:147178.18-147178.116" *)
  wire _075_;
  (* src = "libresoc.v:147180.18-147180.111" *)
  wire _076_;
  (* src = "libresoc.v:147186.18-147186.116" *)
  wire _077_;
  (* src = "libresoc.v:147188.18-147188.111" *)
  wire _078_;
  (* src = "libresoc.v:147190.18-147190.116" *)
  wire _079_;
  (* src = "libresoc.v:147192.18-147192.111" *)
  wire _080_;
  (* src = "libresoc.v:147194.18-147194.116" *)
  wire _081_;
  (* src = "libresoc.v:147196.17-147196.108" *)
  wire _082_;
  (* src = "libresoc.v:147197.18-147197.111" *)
  wire _083_;
  (* src = "libresoc.v:147198.18-147198.120" *)
  wire _084_;
  (* src = "libresoc.v:147201.18-147201.120" *)
  wire _085_;
  (* src = "libresoc.v:147203.18-147203.120" *)
  wire _086_;
  (* src = "libresoc.v:147159.18-147159.110" *)
  wire _087_;
  (* src = "libresoc.v:147164.18-147164.110" *)
  wire _088_;
  (* src = "libresoc.v:147167.18-147167.110" *)
  wire _089_;
  (* src = "libresoc.v:147171.18-147171.110" *)
  wire _090_;
  (* src = "libresoc.v:147175.18-147175.110" *)
  wire _091_;
  (* src = "libresoc.v:147179.18-147179.110" *)
  wire _092_;
  (* src = "libresoc.v:147182.18-147182.110" *)
  wire _093_;
  (* src = "libresoc.v:147185.17-147185.109" *)
  wire _094_;
  (* src = "libresoc.v:147187.18-147187.110" *)
  wire _095_;
  (* src = "libresoc.v:147191.18-147191.110" *)
  wire _096_;
  (* src = "libresoc.v:147195.18-147195.110" *)
  wire _097_;
  (* src = "libresoc.v:147199.18-147199.110" *)
  wire _098_;
  (* src = "libresoc.v:147200.18-147200.109" *)
  wire _099_;
  (* src = "libresoc.v:147202.18-147202.110" *)
  wire _100_;
  (* src = "libresoc.v:147204.18-147204.110" *)
  wire _101_;
  (* src = "libresoc.v:147158.17-147158.119" *)
  wire _102_;
  (* src = "libresoc.v:147160.18-147160.110" *)
  wire _103_;
  (* src = "libresoc.v:147161.18-147161.114" *)
  wire _104_;
  (* src = "libresoc.v:147163.17-147163.113" *)
  wire _105_;
  (* src = "libresoc.v:147166.18-147166.120" *)
  wire _106_;
  (* src = "libresoc.v:147168.18-147168.111" *)
  wire _107_;
  (* src = "libresoc.v:147169.18-147169.114" *)
  wire _108_;
  (* src = "libresoc.v:147173.18-147173.120" *)
  wire _109_;
  (* src = "libresoc.v:147176.18-147176.111" *)
  wire _110_;
  (* src = "libresoc.v:147177.18-147177.114" *)
  wire _111_;
  (* src = "libresoc.v:147181.18-147181.120" *)
  wire _112_;
  (* src = "libresoc.v:147183.18-147183.111" *)
  wire _113_;
  (* src = "libresoc.v:147184.18-147184.114" *)
  wire _114_;
  (* src = "libresoc.v:147189.18-147189.114" *)
  wire _115_;
  (* src = "libresoc.v:147193.18-147193.114" *)
  wire _116_;
  (* src = "libresoc.v:147205.18-147205.127" *)
  wire _117_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [44:0] dbus__adr;
  reg [44:0] dbus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg [44:0] \dbus__adr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__cyc;
  reg dbus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg \dbus__cyc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [63:0] dbus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [63:0] dbus__dat_w;
  reg [63:0] dbus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg [63:0] \dbus__dat_w$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [7:0] dbus__sel;
  reg [7:0] dbus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg [7:0] \dbus__sel$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__stb;
  reg dbus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg \dbus__stb$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__we;
  reg dbus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  reg \dbus__we$next ;
  (* src = "libresoc.v:146979.7-146979.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" *)
  reg [44:0] m_badaddr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" *)
  reg [44:0] \m_badaddr_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" *)
  reg m_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *)
  output [63:0] m_ld_data_o;
  reg [63:0] m_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *)
  reg [63:0] \m_ld_data_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" *)
  reg m_load_err_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:74" *)
  reg \m_load_err_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" *)
  wire m_stall_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" *)
  reg m_store_err_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:75" *)
  reg \m_store_err_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *)
  input m_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  input wb_dcache_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *)
  input [47:0] x_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *)
  output x_busy_o;
  reg x_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *)
  input x_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *)
  input [7:0] x_mask_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *)
  input [63:0] x_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *)
  input x_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:56" *)
  wire x_stall_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *)
  input x_valid_i;
  assign _070_ = \$15  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _071_ = \$17  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$19 ;
  assign _072_ = \$29  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _073_ = \$31  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$33 ;
  assign _074_ = \$1  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _075_ = \$43  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _076_ = \$45  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$47 ;
  assign _077_ = \$57  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _078_ = \$59  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$61 ;
  assign _079_ = \$65  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _080_ = \$67  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$69 ;
  assign _081_ = \$73  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_valid_i;
  assign _082_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$5 ;
  assign _083_ = \$75  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) \$77 ;
  assign _084_ = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err;
  assign _085_ = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err;
  assign _086_ = dbus__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *) dbus__err;
  assign _087_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i;
  assign _088_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _089_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i;
  assign _090_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _091_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i;
  assign _092_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _093_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) m_valid_i;
  assign _094_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _095_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _096_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _097_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_stall_i;
  assign _098_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i;
  assign _099_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" *) dbus__we;
  assign _100_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i;
  assign _101_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" *) m_stall_i;
  assign _102_ = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err;
  assign _103_ = \$9  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$11 ;
  assign _104_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _105_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _106_ = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err;
  assign _107_ = \$23  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$25 ;
  assign _108_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _109_ = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err;
  assign _110_ = \$37  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$39 ;
  assign _111_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _112_ = dbus__ack | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) dbus__err;
  assign _113_ = \$51  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *) \$53 ;
  assign _114_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _115_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _116_ = x_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" *) x_st_i;
  assign _117_ = m_load_err_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) m_store_err_o;
  always @* begin
    if (\initial ) begin end
    _012_ = 1'h0;
  end
  always @* begin
      \initial  <= _012_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _024_ = 45'h000000000000;
  end
  always @* begin
  end
  initial begin
      dbus__adr <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dbus__cyc <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dbus__dat_w <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      dbus__sel <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dbus__stb <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dbus__we <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = 45'h000000000000;
  end
  always @* begin
  end
  initial begin
      m_badaddr_o <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      m_ld_data_o <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      m_load_err_o <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      m_store_err_o <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \m_badaddr_o$next ;
  end
  always @(posedge coresync_clk) begin
      m_badaddr_o <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \m_store_err_o$next ;
  end
  always @(posedge coresync_clk) begin
      m_store_err_o <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \m_load_err_o$next ;
  end
  always @(posedge coresync_clk) begin
      m_load_err_o <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \dbus__dat_w$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__dat_w <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \dbus__we$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__we <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \dbus__adr$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__adr <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \m_ld_data_o$next ;
  end
  always @(posedge coresync_clk) begin
      m_ld_data_o <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \dbus__sel$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__sel <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \dbus__stb$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__stb <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \dbus__cyc$next ;
  end
  always @(posedge coresync_clk) begin
      dbus__cyc <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _066_;
    (* src = "libresoc.v:147227.5-147227.29" *)
    casez (\initial )
      /* src = "libresoc.v:147227.9-147227.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _025_ = _046_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$7 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _046_ = _057_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
                casez (\$13 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _057_ = 1'h0;
                    end
                  default:
                      _057_ = dbus__cyc;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _046_ = 1'h1;
              end
            default:
                _046_ = dbus__cyc;
          endcase
        end
      default:
          _025_ = dbus__cyc;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _066_ = 1'h0;
        end
      default:
          _066_ = _025_;
    endcase
  end
  always @* begin
      \dbus__cyc$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _068_;
    (* src = "libresoc.v:147255.5-147255.29" *)
    casez (\initial )
      /* src = "libresoc.v:147255.9-147255.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _031_ = _049_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$21 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _049_ = _060_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
                casez (\$27 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _060_ = 1'h0;
                    end
                  default:
                      _060_ = dbus__stb;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _049_ = 1'h1;
              end
            default:
                _049_ = dbus__stb;
          endcase
        end
      default:
          _031_ = dbus__stb;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _068_ = 1'h0;
        end
      default:
          _068_ = _031_;
    endcase
  end
  always @* begin
      \dbus__stb$next  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _044_;
    (* src = "libresoc.v:147283.5-147283.29" *)
    casez (\initial )
      /* src = "libresoc.v:147283.9-147283.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _044_ = dbus__cyc;
        end
      default:
          _044_ = 1'h0;
    endcase
  end
  always @* begin
      x_busy_o <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _037_;
    (* src = "libresoc.v:147293.5-147293.29" *)
    casez (\initial )
      /* src = "libresoc.v:147293.9-147293.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _037_ = _052_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *)
          casez (\$95 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _052_ = 1'h0;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _052_ = dbus__cyc;
              end
          endcase
        end
      default:
          _037_ = 1'h0;
    endcase
  end
  always @* begin
      m_busy_o <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _067_;
    (* src = "libresoc.v:147311.5-147311.29" *)
    casez (\initial )
      /* src = "libresoc.v:147311.9-147311.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _029_ = _048_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$35 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _048_ = _059_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
                casez (\$41 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _059_ = 8'h00;
                    end
                  default:
                      _059_ = dbus__sel;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _048_ = x_mask_i;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _048_ = 8'h00;
              end
          endcase
        end
      default:
          _029_ = dbus__sel;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _067_ = 8'h00;
        end
      default:
          _067_ = _029_;
    endcase
  end
  always @* begin
      \dbus__sel$next  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _069_;
    (* src = "libresoc.v:147342.5-147342.29" *)
    casez (\initial )
      /* src = "libresoc.v:147342.9-147342.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _038_ = _053_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$49 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _053_ = _063_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" *)
                casez (\$55 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _063_ = dbus__dat_r;
                    end
                  default:
                      _063_ = m_ld_data_o;
                endcase
              end
            default:
                _053_ = m_ld_data_o;
          endcase
        end
      default:
          _038_ = m_ld_data_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _069_ = 64'h0000000000000000;
        end
      default:
          _069_ = _038_;
    endcase
  end
  always @* begin
      \m_ld_data_o$next  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _056_;
    (* src = "libresoc.v:147367.5-147367.29" *)
    casez (\initial )
      /* src = "libresoc.v:147367.9-147367.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _023_ = _045_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$63 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
                _045_ = dbus__adr;
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _045_ = x_addr_i[47:3];
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _045_ = 45'h000000000000;
              end
          endcase
        end
      default:
          _023_ = dbus__adr;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _056_ = 45'h000000000000;
        end
      default:
          _056_ = _023_;
    endcase
  end
  always @* begin
      \dbus__adr$next  <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _061_;
    (* src = "libresoc.v:147393.5-147393.29" *)
    casez (\initial )
      /* src = "libresoc.v:147393.9-147393.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = _050_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$71 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
                _050_ = dbus__we;
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _050_ = x_st_i;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _050_ = 1'h0;
              end
          endcase
        end
      default:
          _033_ = dbus__we;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _061_ = 1'h0;
        end
      default:
          _061_ = _033_;
    endcase
  end
  always @* begin
      \dbus__we$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _058_;
    (* src = "libresoc.v:147419.5-147419.29" *)
    casez (\initial )
      /* src = "libresoc.v:147419.9-147419.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _027_ = _047_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" *)
          casez ({ \$79 , dbus__cyc })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
                _047_ = dbus__dat_w;
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _047_ = x_st_data_i;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _047_ = 64'h0000000000000000;
              end
          endcase
        end
      default:
          _027_ = dbus__dat_w;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _058_ = 64'h0000000000000000;
        end
      default:
          _058_ = _027_;
    endcase
  end
  always @* begin
      \dbus__dat_w$next  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _064_;
    (* src = "libresoc.v:147445.5-147445.29" *)
    casez (\initial )
      /* src = "libresoc.v:147445.9-147445.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _040_ = _054_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
          casez ({ \$83 , \$81  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _054_ = \$85 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _054_ = 1'h0;
              end
            default:
                _054_ = m_load_err_o;
          endcase
        end
      default:
          _040_ = m_load_err_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _064_ = 1'h0;
        end
      default:
          _064_ = _040_;
    endcase
  end
  always @* begin
      \m_load_err_o$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _065_;
    (* src = "libresoc.v:147468.5-147468.29" *)
    casez (\initial )
      /* src = "libresoc.v:147468.9-147468.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _042_ = _055_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
          casez ({ \$89 , \$87  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _055_ = dbus__we;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _055_ = 1'h0;
              end
            default:
                _055_ = m_store_err_o;
          endcase
        end
      default:
          _042_ = m_store_err_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _065_ = 1'h0;
        end
      default:
          _065_ = _042_;
    endcase
  end
  always @* begin
      \m_store_err_o$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _062_;
    (* src = "libresoc.v:147491.5-147491.29" *)
    casez (\initial )
      /* src = "libresoc.v:147491.9-147491.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111" *)
    casez (wb_dcache_en)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = _051_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" *)
          casez ({ \$93 , \$91  })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _051_ = dbus__adr;
              end
            default:
                _051_ = m_badaddr_o;
          endcase
        end
      default:
          _035_ = m_badaddr_o;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _062_ = 45'h000000000000;
        end
      default:
          _062_ = _035_;
    endcase
  end
  always @* begin
      \m_badaddr_o$next  <= _013_;
  end
  assign \$9  = _102_;
  assign \$11  = _087_;
  assign \$13  = _103_;
  assign \$15  = _104_;
  assign \$17  = _070_;
  assign \$1  = _105_;
  assign \$19  = _088_;
  assign \$21  = _071_;
  assign \$23  = _106_;
  assign \$25  = _089_;
  assign \$27  = _107_;
  assign \$29  = _108_;
  assign \$31  = _072_;
  assign \$33  = _090_;
  assign \$35  = _073_;
  assign \$37  = _109_;
  assign \$3  = _074_;
  assign \$39  = _091_;
  assign \$41  = _110_;
  assign \$43  = _111_;
  assign \$45  = _075_;
  assign \$47  = _092_;
  assign \$49  = _076_;
  assign \$51  = _112_;
  assign \$53  = _093_;
  assign \$55  = _113_;
  assign \$57  = _114_;
  assign \$5  = _094_;
  assign \$59  = _077_;
  assign \$61  = _095_;
  assign \$63  = _078_;
  assign \$65  = _115_;
  assign \$67  = _079_;
  assign \$69  = _096_;
  assign \$71  = _080_;
  assign \$73  = _116_;
  assign \$75  = _081_;
  assign \$77  = _097_;
  assign \$7  = _082_;
  assign \$79  = _083_;
  assign \$81  = _084_;
  assign \$83  = _098_;
  assign \$85  = _099_;
  assign \$87  = _085_;
  assign \$89  = _100_;
  assign \$91  = _086_;
  assign \$93  = _101_;
  assign \$95  = _117_;
  assign x_stall_i = 1'h0;
  assign m_stall_i = 1'h0;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:147516.1-148549.10" *)
module main(alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, ra, rb, xer_so, xer_ca, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , o, o_ok, cr_a, cr_a_ok, \xer_ca$20 , xer_ca_ok, xer_ov, xer_ov_ok, \xer_so$21 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:148049.3-148071.6" *)
  reg [63:0] _000_;
  (* src = "libresoc.v:148148.3-148174.6" *)
  reg _001_;
  (* src = "libresoc.v:148501.3-148511.6" *)
  reg [63:0] _002_;
  (* src = "libresoc.v:148471.3-148480.6" *)
  reg [65:0] _003_;
  (* src = "libresoc.v:148481.3-148490.6" *)
  reg [65:0] _004_;
  (* src = "libresoc.v:148491.3-148500.6" *)
  reg [65:0] _005_;
  (* src = "libresoc.v:148315.3-148337.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:148297.3-148314.6" *)
  reg [1:0] _007_;
  (* src = "libresoc.v:148512.3-148522.6" *)
  reg _008_;
  (* src = "libresoc.v:148523.3-148533.6" *)
  reg _009_;
  (* src = "libresoc.v:148175.3-148208.6" *)
  reg [3:0] _010_;
  (* src = "libresoc.v:148209.3-148231.6" *)
  reg _011_;
  (* src = "libresoc.v:148439.3-148470.6" *)
  reg [7:0] _012_;
  (* src = "libresoc.v:147517.7-147517.20" *)
  reg _013_;
  (* src = "libresoc.v:148039.3-148048.6" *)
  reg _014_;
  (* src = "libresoc.v:148110.3-148128.6" *)
  reg _015_;
  (* src = "libresoc.v:148129.3-148147.6" *)
  reg _016_;
  (* src = "libresoc.v:148232.3-148273.6" *)
  reg [63:0] _017_;
  (* src = "libresoc.v:148274.3-148296.6" *)
  reg _018_;
  (* src = "libresoc.v:148368.3-148385.6" *)
  reg [1:0] _019_;
  (* src = "libresoc.v:148416.3-148438.6" *)
  reg [7:0] _020_;
  (* src = "libresoc.v:148083.3-148109.6" *)
  reg [4:0] _021_;
  (* src = "libresoc.v:148338.3-148352.6" *)
  reg [1:0] _022_;
  (* src = "libresoc.v:148353.3-148367.6" *)
  reg _023_;
  (* src = "libresoc.v:148386.3-148400.6" *)
  reg [1:0] _024_;
  (* src = "libresoc.v:148401.3-148415.6" *)
  reg _025_;
  (* src = "libresoc.v:148072.3-148082.6" *)
  reg _026_;
  (* src = "libresoc.v:148534.3-148544.6" *)
  reg _027_;
  (* src = "libresoc.v:148049.3-148071.6" *)
  reg [63:0] _028_;
  (* src = "libresoc.v:148148.3-148174.6" *)
  reg _029_;
  (* src = "libresoc.v:148501.3-148511.6" *)
  reg [63:0] _030_;
  (* src = "libresoc.v:148471.3-148480.6" *)
  reg [65:0] _031_;
  (* src = "libresoc.v:148481.3-148490.6" *)
  reg [65:0] _032_;
  (* src = "libresoc.v:148491.3-148500.6" *)
  reg [65:0] _033_;
  (* src = "libresoc.v:148315.3-148337.6" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:148297.3-148314.6" *)
  reg [1:0] _035_;
  (* src = "libresoc.v:148512.3-148522.6" *)
  reg _036_;
  (* src = "libresoc.v:148523.3-148533.6" *)
  reg _037_;
  (* src = "libresoc.v:148175.3-148208.6" *)
  reg [3:0] _038_;
  (* src = "libresoc.v:148209.3-148231.6" *)
  reg _039_;
  (* src = "libresoc.v:148439.3-148470.6" *)
  reg [7:0] _040_;
  (* src = "libresoc.v:148039.3-148048.6" *)
  reg _041_;
  (* src = "libresoc.v:148110.3-148128.6" *)
  reg _042_;
  (* src = "libresoc.v:148129.3-148147.6" *)
  reg _043_;
  (* src = "libresoc.v:148232.3-148273.6" *)
  reg [63:0] _044_;
  (* src = "libresoc.v:148274.3-148296.6" *)
  reg _045_;
  (* src = "libresoc.v:148368.3-148385.6" *)
  reg [1:0] _046_;
  (* src = "libresoc.v:148416.3-148438.6" *)
  reg [7:0] _047_;
  (* src = "libresoc.v:148083.3-148109.6" *)
  reg [4:0] _048_;
  (* src = "libresoc.v:148338.3-148352.6" *)
  reg [1:0] _049_;
  (* src = "libresoc.v:148353.3-148367.6" *)
  reg _050_;
  (* src = "libresoc.v:148386.3-148400.6" *)
  reg [1:0] _051_;
  (* src = "libresoc.v:148401.3-148415.6" *)
  reg _052_;
  (* src = "libresoc.v:148072.3-148082.6" *)
  reg _053_;
  (* src = "libresoc.v:148534.3-148544.6" *)
  reg _054_;
  (* src = "libresoc.v:148049.3-148071.6" *)
  reg [63:0] _055_;
  (* src = "libresoc.v:148148.3-148174.6" *)
  reg _056_;
  (* src = "libresoc.v:148315.3-148337.6" *)
  reg [63:0] _057_;
  (* src = "libresoc.v:148175.3-148208.6" *)
  reg [1:0] _058_;
  (* src = "libresoc.v:148110.3-148128.6" *)
  reg _059_;
  (* src = "libresoc.v:148129.3-148147.6" *)
  reg _060_;
  (* src = "libresoc.v:148232.3-148273.6" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:148083.3-148109.6" *)
  reg [4:0] _062_;
  (* src = "libresoc.v:148148.3-148174.6" *)
  reg _063_;
  (* src = "libresoc.v:148232.3-148273.6" *)
  reg [63:0] _064_;
  (* src = "libresoc.v:148083.3-148109.6" *)
  reg [4:0] _065_;
  (* src = "libresoc.v:148232.3-148273.6" *)
  reg [63:0] _066_;
  (* src = "libresoc.v:148014.18-148014.105" *)
  wire [66:0] _067_;
  (* src = "libresoc.v:147988.19-147988.107" *)
  wire _068_;
  (* src = "libresoc.v:147992.19-147992.107" *)
  wire _069_;
  (* src = "libresoc.v:148025.18-148025.106" *)
  wire _070_;
  (* src = "libresoc.v:148030.18-148030.106" *)
  wire _071_;
  (* src = "libresoc.v:148033.18-148033.106" *)
  wire _072_;
  (* src = "libresoc.v:148036.18-148036.106" *)
  wire _073_;
  (* src = "libresoc.v:147979.19-147979.118" *)
  wire _074_;
  (* src = "libresoc.v:147980.19-147980.118" *)
  wire _075_;
  (* src = "libresoc.v:147981.19-147981.118" *)
  wire _076_;
  (* src = "libresoc.v:147993.19-147993.109" *)
  wire _077_;
  (* src = "libresoc.v:147994.19-147994.110" *)
  wire _078_;
  (* src = "libresoc.v:147995.19-147995.111" *)
  wire _079_;
  (* src = "libresoc.v:147996.19-147996.111" *)
  wire _080_;
  (* src = "libresoc.v:147997.19-147997.111" *)
  wire _081_;
  (* src = "libresoc.v:147998.19-147998.111" *)
  wire _082_;
  (* src = "libresoc.v:147999.19-147999.111" *)
  wire _083_;
  (* src = "libresoc.v:148000.19-148000.111" *)
  wire _084_;
  (* src = "libresoc.v:148001.18-148001.118" *)
  wire _085_;
  (* src = "libresoc.v:148003.18-148003.118" *)
  wire _086_;
  (* src = "libresoc.v:148004.18-148004.118" *)
  wire _087_;
  (* src = "libresoc.v:148005.18-148005.118" *)
  wire _088_;
  (* src = "libresoc.v:148006.18-148006.118" *)
  wire _089_;
  (* src = "libresoc.v:148008.18-148008.118" *)
  wire _090_;
  (* src = "libresoc.v:148009.18-148009.118" *)
  wire _091_;
  (* src = "libresoc.v:148011.18-148011.118" *)
  wire _092_;
  (* src = "libresoc.v:148012.18-148012.118" *)
  wire _093_;
  (* src = "libresoc.v:148026.18-148026.107" *)
  wire _094_;
  (* src = "libresoc.v:148037.18-148037.107" *)
  wire _095_;
  (* src = "libresoc.v:147987.19-147987.100" *)
  wire _096_;
  (* src = "libresoc.v:147991.19-147991.100" *)
  wire _097_;
  (* src = "libresoc.v:148002.18-148002.110" *)
  wire _098_;
  (* src = "libresoc.v:148015.18-148015.97" *)
  wire [63:0] _099_;
  (* src = "libresoc.v:148020.18-148020.99" *)
  wire _100_;
  (* src = "libresoc.v:148023.18-148023.99" *)
  wire _101_;
  (* src = "libresoc.v:148027.18-148027.99" *)
  wire _102_;
  (* src = "libresoc.v:148028.18-148028.99" *)
  wire _103_;
  (* src = "libresoc.v:148007.18-148007.104" *)
  wire _104_;
  (* src = "libresoc.v:148010.18-148010.104" *)
  wire _105_;
  (* src = "libresoc.v:148013.18-148013.104" *)
  wire _106_;
  (* src = "libresoc.v:148024.18-148024.110" *)
  wire _107_;
  (* src = "libresoc.v:148029.18-148029.110" *)
  wire _108_;
  (* src = "libresoc.v:148032.18-148032.110" *)
  wire _109_;
  (* src = "libresoc.v:148035.18-148035.110" *)
  wire _110_;
  (* src = "libresoc.v:147978.18-147978.98" *)
  wire _111_;
  (* src = "libresoc.v:147982.19-147982.99" *)
  wire _112_;
  (* src = "libresoc.v:148019.18-148019.99" *)
  wire _113_;
  (* src = "libresoc.v:148022.18-148022.99" *)
  wire _114_;
  (* src = "libresoc.v:148031.18-148031.121" *)
  wire _115_;
  (* src = "libresoc.v:148034.18-148034.119" *)
  wire _116_;
  (* src = "libresoc.v:148038.18-148038.123" *)
  wire _117_;
  (* src = "libresoc.v:147983.19-147983.111" *)
  wire _118_;
  (* src = "libresoc.v:147984.19-147984.111" *)
  wire _119_;
  (* src = "libresoc.v:147985.19-147985.110" *)
  wire _120_;
  (* src = "libresoc.v:147986.19-147986.110" *)
  wire _121_;
  (* src = "libresoc.v:147989.19-147989.110" *)
  wire _122_;
  (* src = "libresoc.v:147990.19-147990.110" *)
  wire _123_;
  (* src = "libresoc.v:148016.18-148016.111" *)
  wire _124_;
  (* src = "libresoc.v:148017.18-148017.107" *)
  wire _125_;
  (* src = "libresoc.v:148018.18-148018.113" *)
  wire [31:0] _126_;
  (* src = "libresoc.v:148021.18-148021.115" *)
  wire [31:0] _127_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *)
  wire \$143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *)
  wire [66:0] \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *)
  wire [66:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *)
  wire [63:0] \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *)
  wire [31:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *)
  wire [31:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:65" *)
  reg [63:0] a_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" *)
  reg a_lt;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" *)
  reg [63:0] a_n;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" *)
  reg [65:0] add_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" *)
  reg [65:0] add_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" *)
  reg [65:0] add_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \alu_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \alu_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \alu_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \alu_op__input_carry$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \alu_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \alu_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_out$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__write_cr0$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" *)
  reg [63:0] b_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:150" *)
  reg [1:0] ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" *)
  reg carry_32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" *)
  reg carry_64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" *)
  reg [7:0] eqs;
  (* src = "libresoc.v:147517.7-147517.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" *)
  reg is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:104" *)
  reg msb_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" *)
  reg msb_b;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:156" *)
  reg [1:0] ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" *)
  reg [7:0] src1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" *)
  reg [4:0] tval;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$20 ;
  reg [1:0] \xer_ca$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  reg xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  reg [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:103" *)
  reg zerohi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" *)
  reg zerolo;
  assign _067_ = add_a + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" *) add_b;
  assign _068_ = \$113  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$115 ;
  assign _069_ = \$121  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$123 ;
  assign _070_ = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$69 ;
  assign _071_ = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$79 ;
  assign _072_ = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$85 ;
  assign _073_ = zerolo & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) \$91 ;
  assign _074_ = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *) 1'h1;
  assign _075_ = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *) 2'h2;
  assign _076_ = alu_op__data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *) 3'h4;
  assign _077_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[7:0];
  assign _078_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[15:8];
  assign _079_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[23:16];
  assign _080_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[31:24];
  assign _081_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[39:32];
  assign _082_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[47:40];
  assign _083_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[55:48];
  assign _084_ = src1 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" *) rb[63:56];
  assign _085_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *) 7'h0a;
  assign _086_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
  assign _087_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *) 7'h0a;
  assign _088_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
  assign _089_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
  assign _090_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
  assign _091_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
  assign _092_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" *) 7'h02;
  assign _093_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) 7'h0a;
  assign _094_ = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
  assign _095_ = msb_a != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *) msb_b;
  assign _096_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$116 ;
  assign _097_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) \$124 ;
  assign _098_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" *) alu_op__insn[21];
  assign _099_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" *) ra;
  assign _100_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$58 ;
  assign _101_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$64 ;
  assign _102_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
  assign _103_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" *) a_lt;
  assign _104_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$32 ;
  assign _105_ = \$36  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$38 ;
  assign _106_ = \$42  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *) \$44 ;
  assign _107_ = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
  assign _108_ = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
  assign _109_ = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
  assign _110_ = is_32bit | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *) zerohi;
  assign _111_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" *) eqs;
  assign _112_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" *) eqs;
  assign _113_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) \$59 ;
  assign _114_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) \$65 ;
  assign _115_ = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" *) a_n[31] : a_n[63];
  assign _116_ = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" *) rb[31] : rb[63];
  assign _117_ = is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" *) carry_32 : carry_64;
  assign _118_ = a_i[32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) b_i[32];
  assign _119_ = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" *) \$109 ;
  assign _120_ = ca[0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[64];
  assign _121_ = a_i[63] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[63];
  assign _122_ = ca[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) add_o[32];
  assign _123_ = a_i[31] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" *) b_i[31];
  assign _124_ = add_o[33] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) ra[32];
  assign _125_ = \$53  ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" *) rb[32];
  assign _126_ = a_n[31:0] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" *) rb[31:0];
  assign _127_ = a_n[63:32] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" *) rb[63:32];
  always @* begin
    if (\initial ) begin end
    _013_ = 1'h0;
  end
  always @* begin
      \initial  <= _013_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _041_;
    (* src = "libresoc.v:148040.5-148040.29" *)
    casez (\initial )
      /* src = "libresoc.v:148040.9-148040.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" *)
    casez (\$22 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _041_ = \$24 ;
        end
      default:
          _041_ = 1'h0;
    endcase
  end
  always @* begin
      is_32bit <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _028_;
    (* src = "libresoc.v:148050.5-148050.29" *)
    casez (\initial )
      /* src = "libresoc.v:148050.9-148050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
    casez ({ is_32bit, \$26  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _028_ = ra;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _028_ = _055_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *)
          casez (alu_op__is_signed)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _055_ = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] };
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _055_ = { 32'h00000000, ra[31:0] };
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _028_ = ra;
        end
    endcase
  end
  always @* begin
      a_i <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _053_;
    (* src = "libresoc.v:148073.5-148073.29" *)
    casez (\initial )
      /* src = "libresoc.v:148073.9-148073.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _053_ = \$63 ;
        end
      default:
          _053_ = 1'h0;
    endcase
  end
  always @* begin
      zerohi <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _048_;
    (* src = "libresoc.v:148084.5-148084.29" *)
    casez (\initial )
      /* src = "libresoc.v:148084.9-148084.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _048_ = _062_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
          casez (\$71 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _062_[4:3], _062_[1:0] } = 4'h0;
                _062_[2] = 1'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _062_ = _065_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
                casez (\$73 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _065_ = { msb_a, msb_b, 1'h0, msb_b, msb_a };
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _065_ = { a_lt, \$77 , 1'h0, a_lt, \$75  };
                    end
                endcase
              end
          endcase
        end
      default:
          _048_ = 5'h00;
    endcase
  end
  always @* begin
      tval <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _042_;
    (* src = "libresoc.v:148111.5-148111.29" *)
    casez (\initial )
      /* src = "libresoc.v:148111.9-148111.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _042_ = _059_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
          casez (\$81 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _059_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _059_ = \$83 ;
              end
          endcase
        end
      default:
          _042_ = 1'h0;
    endcase
  end
  always @* begin
      msb_a <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _043_;
    (* src = "libresoc.v:148130.5-148130.29" *)
    casez (\initial )
      /* src = "libresoc.v:148130.9-148130.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _043_ = _060_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
          casez (\$87 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _060_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _060_ = \$89 ;
              end
          endcase
        end
      default:
          _043_ = 1'h0;
    endcase
  end
  always @* begin
      msb_b <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _029_;
    (* src = "libresoc.v:148149.5-148149.29" *)
    casez (\initial )
      /* src = "libresoc.v:148149.9-148149.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _029_ = _056_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" *)
          casez (\$93 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _056_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _056_ = _063_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" *)
                casez (\$95 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                      _063_ = 1'h0;
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _063_ = \$97 ;
                    end
                endcase
              end
          endcase
        end
      default:
          _029_ = 1'h0;
    endcase
  end
  always @* begin
      a_lt <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _038_;
    (* src = "libresoc.v:148176.5-148176.29" *)
    casez (\initial )
      /* src = "libresoc.v:148176.9-148176.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _038_[1:0] = { tval[2], xer_so };
          _038_[3:2] = _058_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:134" *)
          casez (alu_op__is_signed)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _058_ = tval[4:3];
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _058_ = tval[1:0];
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
          _038_ = 4'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
          _038_ = 4'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _038_ = { 1'h0, \$99 , 2'h0 };
        end
      default:
          _038_ = 4'h0;
    endcase
  end
  always @* begin
      cr_a <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _039_;
    (* src = "libresoc.v:148210.5-148210.29" *)
    casez (\initial )
      /* src = "libresoc.v:148210.9-148210.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _039_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
          _039_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
          _039_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _039_ = 1'h1;
        end
      default:
          _039_ = 1'h0;
    endcase
  end
  always @* begin
      cr_a_ok <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _044_;
    (* src = "libresoc.v:148233.5-148233.29" *)
    casez (\initial )
      /* src = "libresoc.v:148233.9-148233.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _044_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _044_ = add_o[64:1];
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
        begin
          _044_ = _066_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" *)
          casez (\$101 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _061_ = { ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7], ra[7:0] };
              end
            default:
                _061_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" *)
          casez (\$103 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _064_ = { ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15], ra[15:0] };
              end
            default:
                _064_ = _061_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" *)
          casez (\$105 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _066_ = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] };
              end
            default:
                _066_ = _064_;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _044_[63:1] = 63'h0000000000000000;
          _044_[0] = \$107 ;
        end
      default:
          _044_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      o <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _045_;
    (* src = "libresoc.v:148275.5-148275.29" *)
    casez (\initial )
      /* src = "libresoc.v:148275.9-148275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _045_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _045_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
        begin
          _045_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _045_ = 1'h0;
        end
      default:
          _045_ = 1'h0;
    endcase
  end
  always @* begin
      o_ok <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _035_;
    (* src = "libresoc.v:148298.5-148298.29" *)
    casez (\initial )
      /* src = "libresoc.v:148298.9-148298.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _035_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _035_[0] = add_o[65];
          _035_[1] = \$111 ;
        end
      default:
          _035_ = 2'h0;
    endcase
  end
  always @* begin
      ca <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _034_;
    (* src = "libresoc.v:148316.5-148316.29" *)
    casez (\initial )
      /* src = "libresoc.v:148316.9-148316.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" *)
    casez ({ is_32bit, \$28  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _034_ = rb;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _034_ = _057_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:71" *)
          casez (alu_op__is_signed)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _057_ = { rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31:0] };
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _057_ = { 32'h00000000, rb[31:0] };
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _034_ = rb;
        end
    endcase
  end
  always @* begin
      b_i <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _049_;
    (* src = "libresoc.v:148339.5-148339.29" *)
    casez (\initial )
      /* src = "libresoc.v:148339.9-148339.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _049_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _049_ = ca;
        end
      default:
          _049_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ca$20  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = _050_;
    (* src = "libresoc.v:148354.5-148354.29" *)
    casez (\initial )
      /* src = "libresoc.v:148354.9-148354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _050_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _050_ = 1'h1;
        end
      default:
          _050_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ca_ok <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _046_;
    (* src = "libresoc.v:148369.5-148369.29" *)
    casez (\initial )
      /* src = "libresoc.v:148369.9-148369.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _046_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _046_[0] = \$119 ;
          _046_[1] = \$127 ;
        end
      default:
          _046_ = 2'h0;
    endcase
  end
  always @* begin
      ov <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _051_;
    (* src = "libresoc.v:148387.5-148387.29" *)
    casez (\initial )
      /* src = "libresoc.v:148387.9-148387.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _051_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _051_ = ov;
        end
      default:
          _051_ = 2'h0;
    endcase
  end
  always @* begin
      xer_ov <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _052_;
    (* src = "libresoc.v:148402.5-148402.29" *)
    casez (\initial )
      /* src = "libresoc.v:148402.9-148402.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _052_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
        begin
          _052_ = 1'h1;
        end
      default:
          _052_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _047_;
    (* src = "libresoc.v:148417.5-148417.29" *)
    casez (\initial )
      /* src = "libresoc.v:148417.9-148417.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _047_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
          _047_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
          _047_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _047_ = ra[7:0];
        end
      default:
          _047_ = 8'h00;
    endcase
  end
  always @* begin
      src1 <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _040_;
    (* src = "libresoc.v:148440.5-148440.29" *)
    casez (\initial )
      /* src = "libresoc.v:148440.9-148440.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
          _040_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h02:
          _040_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h1f:
          _040_ = 8'h00;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0c:
        begin
          _040_[0] = \$129 ;
          _040_[1] = \$131 ;
          _040_[2] = \$133 ;
          _040_[3] = \$135 ;
          _040_[4] = \$137 ;
          _040_[5] = \$139 ;
          _040_[6] = \$141 ;
          _040_[7] = \$143 ;
        end
      default:
          _040_ = 8'h00;
    endcase
  end
  always @* begin
      eqs <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _031_;
    (* src = "libresoc.v:148472.5-148472.29" *)
    casez (\initial )
      /* src = "libresoc.v:148472.9-148472.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
    casez (\$34 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _031_ = { 1'h0, a_i, xer_ca[0] };
        end
      default:
          _031_ = 66'h00000000000000000;
    endcase
  end
  always @* begin
      add_a <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _032_;
    (* src = "libresoc.v:148482.5-148482.29" *)
    casez (\initial )
      /* src = "libresoc.v:148482.9-148482.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
    casez (\$40 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _032_ = { 1'h0, b_i, 1'h1 };
        end
      default:
          _032_ = 66'h00000000000000000;
    endcase
  end
  always @* begin
      add_b <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _033_;
    (* src = "libresoc.v:148492.5-148492.29" *)
    casez (\initial )
      /* src = "libresoc.v:148492.9-148492.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" *)
    casez (\$46 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = \$48 [65:0];
        end
      default:
          _033_ = 66'h00000000000000000;
    endcase
  end
  always @* begin
      add_o <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _030_;
    (* src = "libresoc.v:148502.5-148502.29" *)
    casez (\initial )
      /* src = "libresoc.v:148502.9-148502.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _030_ = \$51 ;
        end
      default:
          _030_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      a_n <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _036_;
    (* src = "libresoc.v:148513.5-148513.29" *)
    casez (\initial )
      /* src = "libresoc.v:148513.9-148513.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _036_ = \$55 ;
        end
      default:
          _036_ = 1'h0;
    endcase
  end
  always @* begin
      carry_32 <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _037_;
    (* src = "libresoc.v:148524.5-148524.29" *)
    casez (\initial )
      /* src = "libresoc.v:148524.9-148524.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _037_ = add_o[65];
        end
      default:
          _037_ = 1'h0;
    endcase
  end
  always @* begin
      carry_64 <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _054_;
    (* src = "libresoc.v:148535.5-148535.29" *)
    casez (\initial )
      /* src = "libresoc.v:148535.9-148535.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" *)
    casez (alu_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h0a:
        begin
          _054_ = \$57 ;
        end
      default:
          _054_ = 1'h0;
    endcase
  end
  always @* begin
      zerolo <= _027_;
  end
  assign \$99  = _111_;
  assign \$101  = _074_;
  assign \$103  = _075_;
  assign \$105  = _076_;
  assign \$107  = _112_;
  assign \$109  = _118_;
  assign \$111  = _119_;
  assign \$113  = _120_;
  assign \$116  = _121_;
  assign \$115  = _096_;
  assign \$119  = _068_;
  assign \$121  = _122_;
  assign \$124  = _123_;
  assign \$123  = _097_;
  assign \$127  = _069_;
  assign \$129  = _077_;
  assign \$131  = _078_;
  assign \$133  = _079_;
  assign \$135  = _080_;
  assign \$137  = _081_;
  assign \$139  = _082_;
  assign \$141  = _083_;
  assign \$143  = _084_;
  assign \$22  = _085_;
  assign \$24  = _098_;
  assign \$26  = _086_;
  assign \$28  = _087_;
  assign \$30  = _088_;
  assign \$32  = _089_;
  assign \$34  = _104_;
  assign \$36  = _090_;
  assign \$38  = _091_;
  assign \$40  = _105_;
  assign \$42  = _092_;
  assign \$44  = _093_;
  assign \$46  = _106_;
  assign \$49  = _067_;
  assign \$51  = _099_;
  assign \$53  = _124_;
  assign \$55  = _125_;
  assign \$59  = _126_;
  assign \$58  = _113_;
  assign \$57  = _100_;
  assign \$65  = _127_;
  assign \$64  = _114_;
  assign \$63  = _101_;
  assign \$69  = _107_;
  assign \$71  = _070_;
  assign \$73  = _094_;
  assign \$75  = _102_;
  assign \$77  = _103_;
  assign \$79  = _108_;
  assign \$81  = _071_;
  assign \$83  = _115_;
  assign \$85  = _109_;
  assign \$87  = _072_;
  assign \$89  = _116_;
  assign \$91  = _110_;
  assign \$93  = _073_;
  assign \$95  = _095_;
  assign \$97  = _117_;
  assign \$48  = \$49 ;
  assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2  } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$21  = xer_so;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:148553.1-148967.10" *)
module \main$114 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, ra, rb, rc, xer_so, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , o, o_ok, \xer_so$19 , xer_ca, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:148554.7-148554.20" *)
  reg _0_;
  (* src = "libresoc.v:148919.3-148949.6" *)
  reg [3:0] _1_;
  (* src = "libresoc.v:148884.3-148918.6" *)
  reg _2_;
  (* src = "libresoc.v:148919.3-148949.6" *)
  reg [3:0] _3_;
  (* src = "libresoc.v:148884.3-148918.6" *)
  reg _4_;
  (* src = "libresoc.v:148554.7-148554.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" *)
  wire [4:0] mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" *)
  wire mb_extra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" *)
  wire [4:0] me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" *)
  reg [3:0] mode;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" *)
  wire rotator_arith;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" *)
  wire rotator_carry_out_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" *)
  wire rotator_clear_left;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" *)
  wire rotator_clear_right;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" *)
  wire rotator_is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *)
  wire [4:0] rotator_mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" *)
  wire rotator_mb_extra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" *)
  wire [4:0] rotator_me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" *)
  wire [63:0] rotator_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" *)
  wire [63:0] rotator_result_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" *)
  wire rotator_right_shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" *)
  wire [63:0] rotator_rs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" *)
  wire [6:0] rotator_shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" *)
  wire rotator_sign_ext_rs;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \sr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \sr_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \sr_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__input_cr$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \sr_op__insn$18 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \sr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$19 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:148868.11-148883.4" *)
  rotator rotator (
    .arith(rotator_arith),
    .carry_out_o(rotator_carry_out_o),
    .clear_left(rotator_clear_left),
    .clear_right(rotator_clear_right),
    .is_32bit(rotator_is_32bit),
    .mb(rotator_mb),
    .mb_extra(rotator_mb_extra),
    .me(rotator_me),
    .ra(rotator_ra),
    .result_o(rotator_result_o),
    .right_shift(rotator_right_shift),
    .rs(rotator_rs),
    .shift(rotator_shift),
    .sign_ext_rs(rotator_sign_ext_rs)
  );
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _2_ = _4_;
    (* src = "libresoc.v:148885.5-148885.29" *)
    casez (\initial )
      /* src = "libresoc.v:148885.9-148885.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" *)
    casez (sr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3c:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      7'h3d:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      7'h38:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      7'h39:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      7'h3a:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      7'h20:
          _4_ = 1'h1;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _4_ = 1'h0;
        end
    endcase
  end
  always @* begin
      o_ok <= _2_;
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _3_;
    (* src = "libresoc.v:148920.5-148920.29" *)
    casez (\initial )
      /* src = "libresoc.v:148920.9-148920.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" *)
    casez (sr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3c:
        begin
          _3_ = 4'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h3d:
        begin
          _3_ = 4'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h38:
        begin
          _3_ = 4'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h39:
        begin
          _3_ = 4'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h3a:
        begin
          _3_ = 4'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h20:
        begin
          _3_ = 4'h8;
        end
      default:
          _3_ = 4'h0;
    endcase
  end
  always @* begin
      mode <= _1_;
  end
  assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2  } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$19  = xer_so;
  assign xer_ca = { rotator_carry_out_o, rotator_carry_out_o };
  assign o = rotator_result_o;
  assign { rotator_sign_ext_rs, rotator_clear_right, rotator_clear_left, rotator_right_shift } = mode;
  assign rotator_arith = sr_op__is_signed;
  assign rotator_is_32bit = sr_op__is_32bit;
  assign rotator_shift = rb[6:0];
  assign rotator_ra = ra;
  assign rotator_rs = rc;
  assign rotator_mb_extra = mb_extra;
  assign rotator_mb = mb;
  assign rotator_me = me;
  assign mb_extra = sr_op__insn[5];
  assign me = sr_op__insn[5:1];
  assign mb = sr_op__insn[10:6];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:148971.1-149511.10" *)
module \main$22 (br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:149418.3-149441.6" *)
  reg _00_;
  (* src = "libresoc.v:149293.3-149304.6" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:149305.3-149331.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:149332.3-149350.6" *)
  reg _03_;
  (* src = "libresoc.v:149390.3-149404.6" *)
  reg _04_;
  (* src = "libresoc.v:149468.3-149488.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:149442.3-149454.6" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:149405.3-149417.6" *)
  reg _07_;
  (* src = "libresoc.v:149489.3-149501.6" *)
  reg _08_;
  (* src = "libresoc.v:149455.3-149467.6" *)
  reg [63:0] _09_;
  (* src = "libresoc.v:149351.3-149369.6" *)
  reg _10_;
  (* src = "libresoc.v:149370.3-149379.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:149380.3-149389.6" *)
  reg _12_;
  (* src = "libresoc.v:148972.7-148972.20" *)
  reg _13_;
  (* src = "libresoc.v:149418.3-149441.6" *)
  reg _14_;
  (* src = "libresoc.v:149293.3-149304.6" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:149305.3-149331.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:149332.3-149350.6" *)
  reg _17_;
  (* src = "libresoc.v:149390.3-149404.6" *)
  reg _18_;
  (* src = "libresoc.v:149468.3-149488.6" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:149442.3-149454.6" *)
  reg [63:0] _20_;
  (* src = "libresoc.v:149405.3-149417.6" *)
  reg _21_;
  (* src = "libresoc.v:149489.3-149501.6" *)
  reg _22_;
  (* src = "libresoc.v:149455.3-149467.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:149351.3-149369.6" *)
  reg _24_;
  (* src = "libresoc.v:149370.3-149379.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:149380.3-149389.6" *)
  reg _26_;
  (* src = "libresoc.v:149418.3-149441.6" *)
  reg _27_;
  (* src = "libresoc.v:149305.3-149331.6" *)
  reg [63:0] _28_;
  (* src = "libresoc.v:149468.3-149488.6" *)
  reg [63:0] _29_;
  (* src = "libresoc.v:149277.18-149277.119" *)
  wire [64:0] _30_;
  (* src = "libresoc.v:149292.18-149292.113" *)
  wire [64:0] _31_;
  (* src = "libresoc.v:149284.18-149284.115" *)
  wire _32_;
  (* src = "libresoc.v:149285.18-149285.117" *)
  wire _33_;
  (* src = "libresoc.v:149291.18-149291.118" *)
  wire _34_;
  (* src = "libresoc.v:149275.18-149275.120" *)
  wire _35_;
  (* src = "libresoc.v:149278.18-149278.111" *)
  wire _36_;
  (* src = "libresoc.v:149280.18-149280.111" *)
  wire _37_;
  (* src = "libresoc.v:149281.18-149281.111" *)
  wire _38_;
  (* src = "libresoc.v:149282.18-149282.109" *)
  wire _39_;
  (* src = "libresoc.v:149287.18-149287.98" *)
  wire [63:0] _40_;
  (* src = "libresoc.v:149283.18-149283.104" *)
  wire _41_;
  (* src = "libresoc.v:149290.18-149290.112" *)
  wire _42_;
  (* src = "libresoc.v:149276.18-149276.116" *)
  wire _43_;
  (* src = "libresoc.v:149279.18-149279.109" *)
  wire _44_;
  (* src = "libresoc.v:149287.18-149287.98" *)
  wire [63:0] _45_;
  (* src = "libresoc.v:149288.18-149288.103" *)
  wire _46_;
  (* src = "libresoc.v:149286.18-149286.108" *)
  wire [64:0] _47_;
  (* src = "libresoc.v:149289.18-149289.108" *)
  wire _48_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *)
  wire [64:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *)
  wire [64:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *)
  wire [64:0] \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *)
  wire [64:0] \$36 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [63:0] \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *)
  wire [64:0] \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *)
  wire [64:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" *)
  reg bc_taken;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" *)
  wire [1:0] bi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" *)
  wire [4:0] bo;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" *)
  reg [63:0] br_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" *)
  reg [63:0] br_imm_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \br_op__cia$2 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] br_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \br_op__fn_unit$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \br_op__imm_data__data$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__imm_data__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \br_op__insn$5 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] br_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \br_op__insn_type$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__is_32bit$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__lk$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" *)
  reg br_taken;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" *)
  reg cr_bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" *)
  reg [63:0] ctr_m;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" *)
  reg [63:0] ctr_n;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" *)
  reg ctr_write;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" *)
  reg ctr_zero_bo1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$10 ;
  reg [63:0] \fast1$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast2$11 ;
  reg [63:0] \fast2$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  reg fast2_ok;
  (* src = "libresoc.v:148972.7-148972.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  assign _30_ = br_imm_addr + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" *) br_op__cia;
  assign _31_ = br_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" *) 3'h4;
  assign _32_ = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) \$29 ;
  assign _33_ = ctr_zero_bo1 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" *) cr_bit;
  assign _34_ = br_op__insn[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) \$44 ;
  assign _35_ = br_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) 7'h08;
  assign _36_ = cr_bit == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[3];
  assign _37_ = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *) 1'h0;
  assign _38_ = bo[4:3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" *) 1'h1;
  assign _39_ = bo[4] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" *) 1'h1;
  assign _40_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) fast1[31:0];
  assign _41_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" *) cr_bit;
  assign _42_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *) br_op__insn[6];
  assign _43_ = br_op__insn[1] | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *) \$12 ;
  assign _44_ = \$19  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" *) bo[4];
  assign _45_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _40_;
  assign _46_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) ctr_n;
  assign _47_ = fast1 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" *) 1'h1;
  assign _48_ = bo[1] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" *) \$40 ;
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
      \initial  <= _13_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _15_;
    (* src = "libresoc.v:149294.5-149294.29" *)
    casez (\initial )
      /* src = "libresoc.v:149294.9-149294.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" *)
    casez (\$14 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = br_imm_addr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _15_ = \$16 [63:0];
        end
    endcase
  end
  always @* begin
      br_addr <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _16_;
    (* src = "libresoc.v:149306.5-149306.29" *)
    casez (\initial )
      /* src = "libresoc.v:149306.9-149306.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *)
    casez (br_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h06:
        begin
          _16_ = { br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25], br_op__insn[25:2], 2'h0 };
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
        begin
          _16_ = { br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15], br_op__insn[15:2], 2'h0 };
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
        begin
          _16_ = _28_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" *)
          casez (\$46 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _28_ = { fast1[63:2], 2'h0 };
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _28_ = { fast2[63:2], 2'h0 };
              end
          endcase
        end
      default:
          _16_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      br_imm_addr <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _17_;
    (* src = "libresoc.v:149333.5-149333.29" *)
    casez (\initial )
      /* src = "libresoc.v:149333.9-149333.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *)
    casez (br_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h06:
        begin
          _17_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
        begin
          _17_ = bc_taken;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
        begin
          _17_ = bc_taken;
        end
      default:
          _17_ = 1'h0;
    endcase
  end
  always @* begin
      br_taken <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _24_;
    (* src = "libresoc.v:149352.5-149352.29" *)
    casez (\initial )
      /* src = "libresoc.v:149352.9-149352.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" *)
    casez (br_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h06:
          _24_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h07:
        begin
          _24_ = ctr_write;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h08:
        begin
          _24_ = ctr_write;
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      fast1_ok <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:149371.5-149371.29" *)
    casez (\initial )
      /* src = "libresoc.v:149371.9-149371.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *)
    casez (br_op__lk)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = \$48 [63:0];
        end
      default:
          _25_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fast2$11  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:149381.5-149381.29" *)
    casez (\initial )
      /* src = "libresoc.v:149381.9-149381.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" *)
    casez (br_op__lk)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = 1'h1;
        end
      default:
          _26_ = 1'h0;
    endcase
  end
  always @* begin
      fast2_ok <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _18_;
    (* src = "libresoc.v:149391.5-149391.29" *)
    casez (\initial )
      /* src = "libresoc.v:149391.9-149391.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" *)
    casez (bi)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _18_ = cr_a[3];
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _18_ = cr_a[2];
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _18_ = cr_a[1];
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h?:
        begin
          _18_ = cr_a[0];
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bit <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _21_;
    (* src = "libresoc.v:149406.5-149406.29" *)
    casez (\initial )
      /* src = "libresoc.v:149406.9-149406.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
          _21_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _21_ = 1'h1;
        end
    endcase
  end
  always @* begin
      ctr_write <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _14_;
    (* src = "libresoc.v:149419.5-149419.29" *)
    casez (\initial )
      /* src = "libresoc.v:149419.9-149419.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = \$21 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _14_ = _27_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" *)
          casez ({ \$27 , \$25 , \$23  })
            /* src = "libresoc.v:0.0-0.0" */
            3'b??1:
              begin
                _27_ = \$31 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b?1?:
              begin
                _27_ = \$33 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            3'b1??:
              begin
                _27_ = ctr_zero_bo1;
              end
            default:
                _27_ = 1'h0;
          endcase
        end
    endcase
  end
  always @* begin
      bc_taken <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _20_;
    (* src = "libresoc.v:149443.5-149443.29" *)
    casez (\initial )
      /* src = "libresoc.v:149443.9-149443.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
          _20_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _20_ = \$35 [63:0];
        end
    endcase
  end
  always @* begin
      ctr_n <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _23_;
    (* src = "libresoc.v:149456.5-149456.29" *)
    casez (\initial )
      /* src = "libresoc.v:149456.9-149456.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
          _23_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _23_ = ctr_n;
        end
    endcase
  end
  always @* begin
      \fast1$10  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _19_;
    (* src = "libresoc.v:149469.5-149469.29" *)
    casez (\initial )
      /* src = "libresoc.v:149469.9-149469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
          _19_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _19_ = _29_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" *)
          casez (br_op__is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = \$38 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _29_ = fast1;
              end
          endcase
        end
    endcase
  end
  always @* begin
      ctr_m <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _22_;
    (* src = "libresoc.v:149490.5-149490.29" *)
    casez (\initial )
      /* src = "libresoc.v:149490.9-149490.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" *)
    casez (bo[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
          _22_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _22_ = \$42 ;
        end
    endcase
  end
  always @* begin
      ctr_zero_bo1 <= _08_;
  end
  assign \$12  = _35_;
  assign \$14  = _43_;
  assign \$17  = _30_;
  assign \$19  = _36_;
  assign \$21  = _44_;
  assign \$23  = _37_;
  assign \$25  = _38_;
  assign \$27  = _39_;
  assign \$29  = _41_;
  assign \$31  = _32_;
  assign \$33  = _33_;
  assign \$36  = _47_;
  assign \$38  = _45_;
  assign \$40  = _46_;
  assign \$42  = _48_;
  assign \$44  = _42_;
  assign \$46  = _34_;
  assign \$49  = _31_;
  assign \$16  = \$17 ;
  assign \$35  = \$36 ;
  assign \$48  = \$49 ;
  assign { \br_op__is_32bit$9 , \br_op__lk$8 , \br_op__imm_data__ok$7 , \br_op__imm_data__data$6 , \br_op__insn$5 , \br_op__fn_unit$4 , \br_op__insn_type$3 , \br_op__cia$2  } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
  assign \muxid$1  = muxid;
  assign nia_ok = br_taken;
  assign nia = br_addr;
  assign bi = br_op__insn[17:16];
  assign bo = br_op__insn[25:21];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:149515.1-150465.10" *)
module \main$38 (trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:150430.3-150441.6" *)
  reg [63:0] _000_;
  (* src = "libresoc.v:149928.3-149939.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:150442.3-150453.6" *)
  reg [63:0] _002_;
  (* src = "libresoc.v:150211.3-150222.6" *)
  reg [63:0] _003_;
  (* src = "libresoc.v:150004.3-150035.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:150036.3-150067.6" *)
  reg _005_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:150151.3-150182.6" *)
  reg _007_;
  (* src = "libresoc.v:149516.7-149516.20" *)
  reg _008_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [63:0] _009_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _010_;
  (* src = "libresoc.v:149940.3-149971.6" *)
  reg [63:0] _011_;
  (* src = "libresoc.v:149972.3-150003.6" *)
  reg _012_;
  (* src = "libresoc.v:150392.3-150410.6" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:150411.3-150429.6" *)
  reg _014_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _015_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _016_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _017_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _018_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _019_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _020_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _021_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _022_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _023_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [1:0] _024_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _025_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _026_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _027_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _028_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _029_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [1:0] _030_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _031_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [2:0] _032_;
  (* src = "libresoc.v:150430.3-150441.6" *)
  reg [63:0] _033_;
  (* src = "libresoc.v:149928.3-149939.6" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:150442.3-150453.6" *)
  reg [63:0] _035_;
  (* src = "libresoc.v:150211.3-150222.6" *)
  reg [63:0] _036_;
  (* src = "libresoc.v:150004.3-150035.6" *)
  reg [63:0] _037_;
  (* src = "libresoc.v:150036.3-150067.6" *)
  reg _038_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg [63:0] _039_;
  (* src = "libresoc.v:150151.3-150182.6" *)
  reg _040_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [63:0] _041_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _042_;
  (* src = "libresoc.v:149940.3-149971.6" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:149972.3-150003.6" *)
  reg _044_;
  (* src = "libresoc.v:150392.3-150410.6" *)
  reg [63:0] _045_;
  (* src = "libresoc.v:150411.3-150429.6" *)
  reg _046_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _047_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _048_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _049_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _050_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _051_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _052_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _053_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _054_;
  (* src = "libresoc.v:150004.3-150035.6" *)
  reg [63:0] _055_;
  (* src = "libresoc.v:150036.3-150067.6" *)
  reg _056_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg [63:0] _057_;
  (* src = "libresoc.v:150151.3-150182.6" *)
  reg _058_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [63:0] _059_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg _060_;
  (* src = "libresoc.v:149940.3-149971.6" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:149972.3-150003.6" *)
  reg _062_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _063_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _064_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _065_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _066_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _067_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _068_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _069_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _070_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _071_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [10:0] _072_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _073_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _074_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _075_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _076_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _077_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _078_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _079_;
  (* src = "libresoc.v:150183.3-150210.6" *)
  reg _080_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _081_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [46:0] _082_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _083_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [2:0] _084_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _085_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [10:0] _086_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg [1:0] _087_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [46:0] _088_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _089_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [2:0] _090_;
  (* src = "libresoc.v:150068.3-150150.6" *)
  reg _091_;
  (* src = "libresoc.v:150223.3-150391.6" *)
  reg [2:0] _092_;
  (* src = "libresoc.v:149904.18-149904.113" *)
  wire [64:0] _093_;
  (* src = "libresoc.v:149898.18-149898.108" *)
  wire [4:0] _094_;
  (* src = "libresoc.v:149906.18-149906.118" *)
  wire [7:0] _095_;
  (* src = "libresoc.v:149908.18-149908.118" *)
  wire [7:0] _096_;
  (* src = "libresoc.v:149910.18-149910.118" *)
  wire [7:0] _097_;
  (* src = "libresoc.v:149912.18-149912.119" *)
  wire [7:0] _098_;
  (* src = "libresoc.v:149914.18-149914.119" *)
  wire [7:0] _099_;
  (* src = "libresoc.v:149916.18-149916.119" *)
  wire [7:0] _100_;
  (* src = "libresoc.v:149922.18-149922.106" *)
  wire _101_;
  (* src = "libresoc.v:149927.18-149927.106" *)
  wire _102_;
  (* src = "libresoc.v:149897.18-149897.100" *)
  wire _103_;
  (* src = "libresoc.v:149905.18-149905.119" *)
  wire _104_;
  (* src = "libresoc.v:149919.18-149919.121" *)
  wire _105_;
  (* src = "libresoc.v:149920.18-149920.121" *)
  wire _106_;
  (* src = "libresoc.v:149921.18-149921.111" *)
  wire _107_;
  (* src = "libresoc.v:149925.18-149925.121" *)
  wire _108_;
  (* src = "libresoc.v:149926.18-149926.114" *)
  wire _109_;
  (* src = "libresoc.v:149891.18-149891.95" *)
  wire [63:0] _110_;
  (* src = "libresoc.v:149892.18-149892.95" *)
  wire [63:0] _111_;
  (* src = "libresoc.v:149903.18-149903.100" *)
  wire [63:0] _112_;
  (* src = "libresoc.v:149918.18-149918.109" *)
  wire [64:0] _113_;
  (* src = "libresoc.v:149894.18-149894.121" *)
  wire _114_;
  (* src = "libresoc.v:149896.18-149896.99" *)
  wire _115_;
  (* src = "libresoc.v:149893.18-149893.121" *)
  wire _116_;
  (* src = "libresoc.v:149895.18-149895.99" *)
  wire _117_;
  (* src = "libresoc.v:149923.18-149923.112" *)
  wire _118_;
  (* src = "libresoc.v:149924.18-149924.112" *)
  wire _119_;
  (* src = "libresoc.v:149901.18-149901.106" *)
  wire _120_;
  (* src = "libresoc.v:149891.18-149891.95" *)
  wire [63:0] _121_;
  (* src = "libresoc.v:149892.18-149892.95" *)
  wire [63:0] _122_;
  (* src = "libresoc.v:149903.18-149903.100" *)
  wire [63:0] _123_;
  (* src = "libresoc.v:149918.18-149918.109" *)
  wire [64:0] _124_;
  (* src = "libresoc.v:149899.18-149899.100" *)
  wire _125_;
  (* src = "libresoc.v:149900.18-149900.113" *)
  wire _126_;
  (* src = "libresoc.v:149907.18-149907.91" *)
  wire _127_;
  (* src = "libresoc.v:149909.18-149909.91" *)
  wire _128_;
  (* src = "libresoc.v:149911.18-149911.91" *)
  wire _129_;
  (* src = "libresoc.v:149913.18-149913.91" *)
  wire _130_;
  (* src = "libresoc.v:149915.18-149915.91" *)
  wire _131_;
  (* src = "libresoc.v:149917.18-149917.91" *)
  wire _132_;
  (* src = "libresoc.v:149902.18-149902.120" *)
  wire [19:0] _133_;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [63:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [63:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *)
  wire [4:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *)
  wire [63:0] \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *)
  wire [19:0] \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *)
  wire [64:0] \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *)
  wire [64:0] \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *)
  wire [7:0] \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *)
  wire [7:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *)
  wire [7:0] \$53 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *)
  wire [7:0] \$57 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *)
  wire [7:0] \$64 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *)
  wire [7:0] \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [64:0] \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" *)
  reg [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" *)
  reg [63:0] a_s;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:142" *)
  reg [63:0] b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:139" *)
  reg [63:0] b_s;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161" *)
  wire equal;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$11 ;
  reg [63:0] \fast1$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast2$12 ;
  reg [63:0] \fast2$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  reg fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" *)
  wire gt_s;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" *)
  wire gt_u;
  (* src = "libresoc.v:149516.7-149516.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" *)
  wire lt_s;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" *)
  wire lt_u;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] msr;
  reg [63:0] msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output msr_ok;
  reg msr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  reg [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  reg nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" *)
  wire should_trap;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134" *)
  wire [4:0] to;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171" *)
  wire [4:0] trap_bits;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__cia$6 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \trap_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \trap_op__insn$4 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \trap_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \trap_op__is_32bit$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__ldst_exc$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__msr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [12:0] \trap_op__trapaddr$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__traptype$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \trapexc_$signal$70 ;
  assign _093_ = trap_op__cia + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" *) 3'h4;
  assign _094_ = trap_bits & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) to;
  assign _095_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *) 2'h2;
  assign _096_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *) 1'h1;
  assign _097_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *) 4'h8;
  assign _098_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40;
  assign _099_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *) 8'h80;
  assign _100_ = trap_op__traptype & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *) 7'h40;
  assign _101_ = \$79  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) \$81 ;
  assign _102_ = \$89  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) \$91 ;
  assign _103_ = a == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" *) b;
  assign _104_ = trap_op__traptype == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *) 1'h0;
  assign _105_ = trap_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *) 7'h48;
  assign _106_ = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" *) 3'h2;
  assign _107_ = ra[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *) 3'h0;
  assign _108_ = trap_op__msr[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" *) 3'h2;
  assign _109_ = fast2[34:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *) 3'h0;
  assign _110_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ra[31:0];
  assign _111_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) rb[31:0];
  assign _112_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) \$36 ;
  assign _113_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) trap_op__msr;
  assign _114_ = $signed(a_s) > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" *) $signed(b_s);
  assign _115_ = a > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" *) b;
  assign _116_ = $signed(a_s) < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" *) $signed(b_s);
  assign _117_ = a < (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" *) b;
  assign _118_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *) trap_op__msr[60];
  assign _119_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *) trap_op__insn[9];
  assign _120_ = \$27  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$31 ;
  assign _121_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _110_;
  assign _122_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _111_;
  assign _123_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) _112_;
  assign _124_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) _113_;
  assign _125_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) \$28 ;
  assign _126_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" *) trap_op__traptype;
  assign _127_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$45 ;
  assign _128_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$49 ;
  assign _129_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$53 ;
  assign _130_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$57 ;
  assign _131_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$64 ;
  assign _132_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$72 ;
  assign _133_ = trap_op__trapaddr <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" *) 3'h4;
  always @* begin
    if (\initial ) begin end
    _008_ = 1'h0;
  end
  always @* begin
      \initial  <= _008_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _034_;
    (* src = "libresoc.v:149929.5-149929.29" *)
    casez (\initial )
      /* src = "libresoc.v:149929.9-149929.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *)
    casez (trap_op__is_32bit)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _034_ = { ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31], ra[31:0] };
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _034_ = ra;
        end
    endcase
  end
  always @* begin
      a_s <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _043_;
    (* src = "libresoc.v:149941.5-149941.29" *)
    casez (\initial )
      /* src = "libresoc.v:149941.9-149941.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _043_ = _061_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _061_ = \$35 ;
              end
            default:
                _061_ = 64'h0000000000000000;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _043_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _043_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          _043_ = { fast1[63:2], 2'h0 };
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          _043_ = 64'h0000000000000c00;
        end
      default:
          _043_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      nia <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _044_;
    (* src = "libresoc.v:149973.5-149973.29" *)
    casez (\initial )
      /* src = "libresoc.v:149973.9-149973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _044_ = _062_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _062_ = 1'h1;
              end
            default:
                _062_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _044_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _044_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          _044_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          _044_ = 1'h1;
        end
      default:
          _044_ = 1'h0;
    endcase
  end
  always @* begin
      nia_ok <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _037_;
    (* src = "libresoc.v:150005.5-150005.29" *)
    casez (\initial )
      /* src = "libresoc.v:150005.9-150005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _037_ = _055_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _055_ = trap_op__cia;
              end
            default:
                _055_ = 64'h0000000000000000;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _037_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _037_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
          _037_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          _037_ = \$39 [63:0];
        end
      default:
          _037_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fast1$11  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _038_;
    (* src = "libresoc.v:150037.5-150037.29" *)
    casez (\initial )
      /* src = "libresoc.v:150037.9-150037.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _038_ = _056_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _056_ = 1'h1;
              end
            default:
                _056_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _038_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _038_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
          _038_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          _038_ = 1'h1;
        end
      default:
          _038_ = 1'h0;
    endcase
  end
  always @* begin
      fast1_ok <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _039_;
    (* src = "libresoc.v:150069.5-150069.29" *)
    casez (\initial )
      /* src = "libresoc.v:150069.9-150069.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _039_ = _057_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _057_[29], _057_[27], _057_[21] } = 3'h0;
                _057_[15:0] = trap_op__msr[15:0];
                _057_[26:22] = trap_op__msr[26:22];
                _057_[63:31] = trap_op__msr[63:31];
                _057_[17] = _071_;
                _057_[20] = _083_;
                _057_[16] = _085_;
                _057_[18] = _087_[0];
                _057_[28] = _089_;
                _057_[30] = _091_;
                _057_[19] = _023_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" *)
                casez (\$42 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _071_ = 1'h1;
                    end
                  default:
                      _071_ = 1'h0;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" *)
                casez (\$44 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _081_ = 1'h1;
                    end
                  default:
                      _081_ = 1'h0;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" *)
                casez (\$48 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _083_ = 1'h1;
                    end
                  default:
                      _083_ = 1'h0;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" *)
                casez (\$52 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _085_ = 1'h1;
                    end
                  default:
                      _085_ = 1'h0;
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *)
                casez (\$56 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _091_ = \trapexc_$signal ;
                      _089_ = \trapexc_$signal$60 ;
                      _087_[1] = \trapexc_$signal$61 ;
                      _087_[0] = \trapexc_$signal$62 ;
                    end
                  default:
                    begin
                      _087_ = { 1'h0, _081_ };
                      _089_ = 1'h0;
                      _091_ = 1'h0;
                    end
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" *)
                casez (\$63 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _023_ = 1'h1;
                    end
                  default:
                      _023_ = _087_[1];
                endcase
              end
            default:
                _057_ = 64'h0000000000000000;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _039_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _039_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
          _039_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          { _039_[30:27], _039_[21:16] } = 10'h000;
          _039_[15:0] = trap_op__msr[15:0];
          _039_[26:22] = trap_op__msr[26:22];
          _039_[63:31] = trap_op__msr[63:31];
        end
      default:
          _039_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fast2$12  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _040_;
    (* src = "libresoc.v:150152.5-150152.29" *)
    casez (\initial )
      /* src = "libresoc.v:150152.9-150152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _040_ = _058_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _058_ = 1'h1;
              end
            default:
                _058_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _040_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
          _040_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
          _040_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          _040_ = 1'h1;
        end
      default:
          _040_ = 1'h0;
    endcase
  end
  always @* begin
      fast2_ok <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _054_;
    _015_ = _047_;
    _016_ = _048_;
    _017_ = _049_;
    _018_ = _050_;
    _019_ = _051_;
    _020_ = _052_;
    _021_ = _053_;
    (* src = "libresoc.v:150184.5-150184.29" *)
    casez (\initial )
      /* src = "libresoc.v:150184.9-150184.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _054_ = _070_;
          _047_ = _063_;
          _048_ = _064_;
          _049_ = _065_;
          _050_ = _066_;
          _051_ = _067_;
          _052_ = _068_;
          _053_ = _069_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _070_ = _080_;
                _063_ = _073_;
                _064_ = _074_;
                _065_ = _075_;
                _066_ = _076_;
                _067_ = _077_;
                _068_ = _078_;
                _069_ = _079_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" *)
                casez (\$71 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _079_, _075_, _073_, _074_, _080_, _078_, _077_, _076_ } = trap_op__ldst_exc;
                    end
                  default:
                    begin
                      _080_ = 1'h0;
                      _073_ = 1'h0;
                      _074_ = 1'h0;
                      _075_ = 1'h0;
                      _076_ = 1'h0;
                      _077_ = 1'h0;
                      _078_ = 1'h0;
                      _079_ = 1'h0;
                    end
                endcase
              end
            default:
              begin
                _070_ = 1'h0;
                _063_ = 1'h0;
                _064_ = 1'h0;
                _065_ = 1'h0;
                _066_ = 1'h0;
                _067_ = 1'h0;
                _068_ = 1'h0;
                _069_ = 1'h0;
              end
          endcase
        end
      default:
        begin
          _054_ = 1'h0;
          _047_ = 1'h0;
          _048_ = 1'h0;
          _049_ = 1'h0;
          _050_ = 1'h0;
          _051_ = 1'h0;
          _052_ = 1'h0;
          _053_ = 1'h0;
        end
    endcase
  end
  always @* begin
      \trapexc_$signal  <= _022_;
      \trapexc_$signal$60  <= _015_;
      \trapexc_$signal$61  <= _016_;
      \trapexc_$signal$62  <= _017_;
      \trapexc_$signal$67  <= _018_;
      \trapexc_$signal$68  <= _019_;
      \trapexc_$signal$69  <= _020_;
      \trapexc_$signal$70  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _036_;
    (* src = "libresoc.v:150212.5-150212.29" *)
    casez (\initial )
      /* src = "libresoc.v:150212.9-150212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *)
    casez (trap_op__is_32bit)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _036_ = { rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31], rb[31:0] };
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _036_ = rb;
        end
    endcase
  end
  always @* begin
      b_s <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _041_;
    _010_ = _042_;
    (* src = "libresoc.v:150224.5-150224.29" *)
    casez (\initial )
      /* src = "libresoc.v:150224.9-150224.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
        begin
          _041_ = _059_;
          _042_ = _060_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" *)
          casez (should_trap)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _059_[62:59], _059_[57:33], _059_[31:26], _059_[24], _059_[22:16], _059_[12], _059_[7:6], _059_[2] } = { trap_op__msr[62:59], trap_op__msr[57:33], trap_op__msr[31:26], trap_op__msr[24], trap_op__msr[22:16], trap_op__msr[12], trap_op__msr[7:6], trap_op__msr[2] };
                _059_[63] = 1'h1;
                _059_[15] = 1'h0;
                _059_[14] = 1'h0;
                _059_[5] = 1'h0;
                _059_[4] = 1'h0;
                _059_[1] = 1'h0;
                _059_[0] = 1'h1;
                _059_[11] = 1'h0;
                _059_[8] = 1'h0;
                _059_[23] = 1'h0;
                _059_[32] = 1'h0;
                _059_[25] = 1'h0;
                _059_[13] = 1'h0;
                _059_[3] = 1'h0;
                _059_[10] = 1'h0;
                _059_[9] = 1'h0;
                _059_[58] = 1'h0;
                _060_ = 1'h1;
              end
            default:
              begin
                _059_ = 64'h0000000000000000;
                _060_ = 1'h0;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
        begin
          _041_[0] = \$75 [0];
          _041_[11:1] = _072_;
          _041_[59:13] = _082_;
          _041_[63:61] = _084_;
          _041_[12] = _026_;
          _041_[60] = _027_;
          _042_ = 1'h1;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:227" *)
          casez (trap_op__insn[21])
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _072_[10:1] = \$75 [11:2];
                { _082_[46:3], _082_[1:0] } = { \$75 [59:16], \$75 [14:13] };
                _084_ = \$75 [63:61];
                _072_[0] = ra[1];
                _082_[2] = ra[15];
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                { _072_[10:5], _072_[2:0] } = { _086_[10:5], _086_[2:0] };
                { _082_[46:3], _082_[1:0] } = { _088_[46:3], _088_[1:0] };
                _084_ = _090_;
                _072_[4:3] = _024_;
                _082_[2] = _025_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" *)
                casez (\$77 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _086_ = ra[11:1];
                      { _088_[46:22], _088_[18:0] } = { ra[59:35], ra[31:13] };
                      _090_ = ra[63:61];
                      _088_[21:19] = _092_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" *)
                      casez (\$83 )
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _092_ = trap_op__msr[34:32];
                          end
                        default:
                            _092_ = ra[34:32];
                      endcase
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _088_[46:19] = \$75 [59:32];
                      _090_ = \$75 [63:61];
                      _086_ = ra[11:1];
                      _088_[18:0] = ra[31:13];
                    end
                endcase
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" *)
                casez (_088_[1])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _025_ = 1'h1;
                      _024_[1] = 1'h1;
                      _024_[0] = 1'h1;
                    end
                  default:
                    begin
                      _024_ = _086_[4:3];
                      _025_ = _088_[2];
                    end
                endcase
              end
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" *)
          casez (\$85 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _027_ = trap_op__msr[60];
                _026_ = trap_op__msr[12];
              end
            default:
              begin
                _026_ = \$75 [12];
                _027_ = \$75 [60];
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
        begin
          _041_ = 64'h0000000000000000;
          _042_ = 1'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h46:
        begin
          { _041_[30:27], _041_[21:16] } = 10'h000;
          { _041_[14:13], _041_[11:6], _041_[3:0] } = { fast2[14:13], fast2[11:6], fast2[3:0] };
          _041_[26:22] = fast2[26:22];
          { _041_[63:35], _041_[31] } = { fast2[63:35], fast2[31] };
          _041_[12] = _028_;
          _041_[5:4] = _030_;
          _041_[15] = _031_;
          _041_[34:32] = _032_;
          _042_ = 1'h1;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" *)
          casez (\$87 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _028_ = _029_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:283" *)
                casez (trap_op__msr[60])
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _029_ = fast2[12];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _029_ = trap_op__msr[12];
                    end
                endcase
              end
            default:
                _028_ = fast2[12];
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:49" *)
          casez (fast2[14])
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _031_ = 1'h1;
                _030_[1] = 1'h1;
                _030_[0] = 1'h1;
              end
            default:
              begin
                _030_ = fast2[5:4];
                _031_ = fast2[15];
              end
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" *)
          casez (\$93 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _032_ = trap_op__msr[34:32];
              end
            default:
                _032_ = fast2[34:32];
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h49:
        begin
          { _041_[62:59], _041_[57:33], _041_[31:26], _041_[24], _041_[22:16], _041_[12], _041_[7:6], _041_[2] } = { trap_op__msr[62:59], trap_op__msr[57:33], trap_op__msr[31:26], trap_op__msr[24], trap_op__msr[22:16], trap_op__msr[12], trap_op__msr[7:6], trap_op__msr[2] };
          _041_[63] = 1'h1;
          _041_[15] = 1'h0;
          _041_[14] = 1'h0;
          _041_[5] = 1'h0;
          _041_[4] = 1'h0;
          _041_[1] = 1'h0;
          _041_[0] = 1'h1;
          _041_[11] = 1'h0;
          _041_[8] = 1'h0;
          _041_[23] = 1'h0;
          _041_[32] = 1'h0;
          _041_[25] = 1'h0;
          _041_[13] = 1'h0;
          _041_[3] = 1'h0;
          _041_[10] = 1'h0;
          _041_[9] = 1'h0;
          _041_[58] = 1'h0;
          _042_ = 1'h1;
        end
      default:
        begin
          _041_ = 64'h0000000000000000;
          _042_ = 1'h0;
        end
    endcase
  end
  always @* begin
      msr <= _009_;
      msr_ok <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _045_;
    (* src = "libresoc.v:150393.5-150393.29" *)
    casez (\initial )
      /* src = "libresoc.v:150393.9-150393.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
          _045_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _045_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
        begin
          _045_ = trap_op__msr;
        end
      default:
          _045_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      o <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _046_;
    (* src = "libresoc.v:150412.5-150412.29" *)
    casez (\initial )
      /* src = "libresoc.v:150412.9-150412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:180" *)
    casez (trap_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h3f:
          _046_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h48, 7'h4a:
          _046_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h47:
        begin
          _046_ = 1'h1;
        end
      default:
          _046_ = 1'h0;
    endcase
  end
  always @* begin
      o_ok <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _033_;
    (* src = "libresoc.v:150431.5-150431.29" *)
    casez (\initial )
      /* src = "libresoc.v:150431.9-150431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *)
    casez (trap_op__is_32bit)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = \$13 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _033_ = ra;
        end
    endcase
  end
  always @* begin
      a <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _035_;
    (* src = "libresoc.v:150443.5-150443.29" *)
    casez (\initial )
      /* src = "libresoc.v:150443.9-150443.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145" *)
    casez (trap_op__is_32bit)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = \$15 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _035_ = rb;
        end
    endcase
  end
  always @* begin
      b <= _002_;
  end
  assign \$13  = _121_;
  assign \$15  = _122_;
  assign \$17  = _116_;
  assign \$19  = _114_;
  assign \$21  = _117_;
  assign \$23  = _115_;
  assign \$25  = _103_;
  assign \$28  = _094_;
  assign \$27  = _125_;
  assign \$31  = _126_;
  assign \$33  = _120_;
  assign \$36  = _133_;
  assign \$35  = _123_;
  assign \$40  = _093_;
  assign \$42  = _104_;
  assign \$45  = _095_;
  assign \$44  = _127_;
  assign \$49  = _096_;
  assign \$48  = _128_;
  assign \$53  = _097_;
  assign \$52  = _129_;
  assign \$57  = _098_;
  assign \$56  = _130_;
  assign \$64  = _099_;
  assign \$63  = _131_;
  assign \$72  = _100_;
  assign \$71  = _132_;
  assign \$75  = _124_;
  assign \$77  = _105_;
  assign \$79  = _106_;
  assign \$81  = _107_;
  assign \$83  = _101_;
  assign \$85  = _118_;
  assign \$87  = _119_;
  assign \$89  = _108_;
  assign \$91  = _109_;
  assign \$93  = _102_;
  assign \$39  = \$40 ;
  assign { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2  } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
  assign \muxid$1  = muxid;
  assign should_trap = \$33 ;
  assign trap_bits = { lt_s, gt_s, equal, lt_u, gt_u };
  assign equal = \$25 ;
  assign gt_u = \$23 ;
  assign lt_u = \$21 ;
  assign gt_s = \$19 ;
  assign lt_s = \$17 ;
  assign to = trap_op__insn[25:21];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:150469.1-151458.10" *)
module \main$51 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, \xer_so$20 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:151377.3-151411.6" *)
  reg [31:0] _000_;
  (* src = "libresoc.v:151226.3-151252.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:151160.3-151198.6" *)
  reg [63:0] _002_;
  (* src = "libresoc.v:151121.3-151159.6" *)
  reg [63:0] _003_;
  (* src = "libresoc.v:151086.3-151120.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:151412.3-151454.6" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:151342.3-151376.6" *)
  reg _006_;
  (* src = "libresoc.v:150470.7-150470.20" *)
  reg _007_;
  (* src = "libresoc.v:151031.3-151085.6" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:151031.3-151085.6" *)
  reg _009_;
  (* src = "libresoc.v:151280.3-151310.6" *)
  reg _010_;
  (* src = "libresoc.v:151311.3-151341.6" *)
  reg _011_;
  (* src = "libresoc.v:151199.3-151225.6" *)
  reg [63:0] _012_;
  (* src = "libresoc.v:151253.3-151279.6" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:151377.3-151411.6" *)
  reg [31:0] _014_;
  (* src = "libresoc.v:151226.3-151252.6" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:151160.3-151198.6" *)
  reg [63:0] _016_;
  (* src = "libresoc.v:151121.3-151159.6" *)
  reg [63:0] _017_;
  (* src = "libresoc.v:151086.3-151120.6" *)
  reg [63:0] _018_;
  (* src = "libresoc.v:151412.3-151454.6" *)
  reg [63:0] _019_;
  (* src = "libresoc.v:151342.3-151376.6" *)
  reg _020_;
  (* src = "libresoc.v:151031.3-151085.6" *)
  reg [63:0] _021_;
  (* src = "libresoc.v:151031.3-151085.6" *)
  reg _022_;
  (* src = "libresoc.v:151280.3-151310.6" *)
  reg _023_;
  (* src = "libresoc.v:151311.3-151341.6" *)
  reg _024_;
  (* src = "libresoc.v:151199.3-151225.6" *)
  reg [63:0] _025_;
  (* src = "libresoc.v:151253.3-151279.6" *)
  reg [63:0] _026_;
  (* src = "libresoc.v:151412.3-151454.6" *)
  reg [63:0] _027_;
  (* src = "libresoc.v:151031.3-151085.6" *)
  reg [63:0] _028_;
  (* src = "libresoc.v:150978.18-150978.103" *)
  wire [63:0] _029_;
  (* src = "libresoc.v:150937.18-150937.118" *)
  wire _030_;
  (* src = "libresoc.v:150938.19-150938.119" *)
  wire _031_;
  (* src = "libresoc.v:150939.19-150939.119" *)
  wire _032_;
  (* src = "libresoc.v:150940.19-150940.119" *)
  wire _033_;
  (* src = "libresoc.v:150941.19-150941.119" *)
  wire _034_;
  (* src = "libresoc.v:150942.19-150942.119" *)
  wire _035_;
  (* src = "libresoc.v:150943.19-150943.119" *)
  wire _036_;
  (* src = "libresoc.v:150944.19-150944.119" *)
  wire _037_;
  (* src = "libresoc.v:150945.19-150945.119" *)
  wire _038_;
  (* src = "libresoc.v:150946.19-150946.119" *)
  wire _039_;
  (* src = "libresoc.v:150947.19-150947.119" *)
  wire _040_;
  (* src = "libresoc.v:150948.19-150948.119" *)
  wire _041_;
  (* src = "libresoc.v:150949.19-150949.119" *)
  wire _042_;
  (* src = "libresoc.v:150950.19-150950.119" *)
  wire _043_;
  (* src = "libresoc.v:150951.19-150951.119" *)
  wire _044_;
  (* src = "libresoc.v:150952.19-150952.119" *)
  wire _045_;
  (* src = "libresoc.v:150953.19-150953.119" *)
  wire _046_;
  (* src = "libresoc.v:150954.19-150954.119" *)
  wire _047_;
  (* src = "libresoc.v:150955.19-150955.119" *)
  wire _048_;
  (* src = "libresoc.v:150956.19-150956.119" *)
  wire _049_;
  (* src = "libresoc.v:150957.19-150957.119" *)
  wire _050_;
  (* src = "libresoc.v:150958.19-150958.119" *)
  wire _051_;
  (* src = "libresoc.v:150959.19-150959.119" *)
  wire _052_;
  (* src = "libresoc.v:150960.19-150960.119" *)
  wire _053_;
  (* src = "libresoc.v:150961.19-150961.119" *)
  wire _054_;
  (* src = "libresoc.v:150962.19-150962.119" *)
  wire _055_;
  (* src = "libresoc.v:150963.19-150963.119" *)
  wire _056_;
  (* src = "libresoc.v:150964.19-150964.119" *)
  wire _057_;
  (* src = "libresoc.v:150965.19-150965.128" *)
  wire _058_;
  (* src = "libresoc.v:150981.18-150981.114" *)
  wire _059_;
  (* src = "libresoc.v:150982.18-150982.114" *)
  wire _060_;
  (* src = "libresoc.v:150983.18-150983.114" *)
  wire _061_;
  (* src = "libresoc.v:150984.18-150984.114" *)
  wire _062_;
  (* src = "libresoc.v:150985.18-150985.114" *)
  wire _063_;
  (* src = "libresoc.v:150986.18-150986.114" *)
  wire _064_;
  (* src = "libresoc.v:150987.18-150987.114" *)
  wire _065_;
  (* src = "libresoc.v:150988.18-150988.114" *)
  wire _066_;
  (* src = "libresoc.v:150989.18-150989.116" *)
  wire _067_;
  (* src = "libresoc.v:150990.18-150990.116" *)
  wire _068_;
  (* src = "libresoc.v:150991.18-150991.116" *)
  wire _069_;
  (* src = "libresoc.v:150992.18-150992.116" *)
  wire _070_;
  (* src = "libresoc.v:150993.18-150993.116" *)
  wire _071_;
  (* src = "libresoc.v:150994.18-150994.116" *)
  wire _072_;
  (* src = "libresoc.v:150995.18-150995.116" *)
  wire _073_;
  (* src = "libresoc.v:150996.18-150996.116" *)
  wire _074_;
  (* src = "libresoc.v:150997.18-150997.118" *)
  wire _075_;
  (* src = "libresoc.v:150998.18-150998.118" *)
  wire _076_;
  (* src = "libresoc.v:150999.18-150999.118" *)
  wire _077_;
  (* src = "libresoc.v:151000.18-151000.118" *)
  wire _078_;
  (* src = "libresoc.v:151001.18-151001.118" *)
  wire _079_;
  (* src = "libresoc.v:151002.18-151002.118" *)
  wire _080_;
  (* src = "libresoc.v:151003.18-151003.118" *)
  wire _081_;
  (* src = "libresoc.v:151004.18-151004.118" *)
  wire _082_;
  (* src = "libresoc.v:151005.18-151005.118" *)
  wire _083_;
  (* src = "libresoc.v:151006.18-151006.118" *)
  wire _084_;
  (* src = "libresoc.v:151007.18-151007.118" *)
  wire _085_;
  (* src = "libresoc.v:151008.18-151008.118" *)
  wire _086_;
  (* src = "libresoc.v:151009.18-151009.118" *)
  wire _087_;
  (* src = "libresoc.v:151010.18-151010.118" *)
  wire _088_;
  (* src = "libresoc.v:151011.18-151011.118" *)
  wire _089_;
  (* src = "libresoc.v:151012.18-151012.118" *)
  wire _090_;
  (* src = "libresoc.v:151013.18-151013.118" *)
  wire _091_;
  (* src = "libresoc.v:151014.18-151014.118" *)
  wire _092_;
  (* src = "libresoc.v:151015.18-151015.118" *)
  wire _093_;
  (* src = "libresoc.v:151016.18-151016.118" *)
  wire _094_;
  (* src = "libresoc.v:150967.19-150967.104" *)
  wire [63:0] _095_;
  (* src = "libresoc.v:150969.19-150969.93" *)
  wire [7:0] _096_;
  (* src = "libresoc.v:150971.19-150971.105" *)
  wire [63:0] _097_;
  (* src = "libresoc.v:150972.19-150972.118" *)
  wire [63:0] _098_;
  (* src = "libresoc.v:150976.19-150976.105" *)
  wire [63:0] _099_;
  (* src = "libresoc.v:150979.18-150979.103" *)
  wire [63:0] _100_;
  (* src = "libresoc.v:150967.19-150967.104" *)
  wire [63:0] _101_;
  (* src = "libresoc.v:150969.19-150969.93" *)
  wire [7:0] _102_;
  (* src = "libresoc.v:150971.19-150971.105" *)
  wire [63:0] _103_;
  (* src = "libresoc.v:150972.19-150972.118" *)
  wire [63:0] _104_;
  (* src = "libresoc.v:150976.19-150976.105" *)
  wire [63:0] _105_;
  (* src = "libresoc.v:150973.19-150973.131" *)
  wire _106_;
  (* src = "libresoc.v:150974.19-150974.133" *)
  wire _107_;
  (* src = "libresoc.v:150968.19-150968.112" *)
  wire [7:0] _108_;
  (* src = "libresoc.v:150970.19-150970.135" *)
  wire [7:0] _109_;
  (* src = "libresoc.v:150975.19-150975.398" *)
  wire [31:0] _110_;
  (* src = "libresoc.v:150977.19-150977.621" *)
  wire [63:0] _111_;
  (* src = "libresoc.v:150966.19-150966.108" *)
  wire _112_;
  (* src = "libresoc.v:150980.18-150980.103" *)
  wire [63:0] _113_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$147 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$153 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *)
  wire \$155 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *)
  wire [63:0] \$157 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *)
  wire \$158 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
  wire [63:0] \$161 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
  wire [7:0] \$162 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *)
  wire [7:0] \$164 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *)
  wire [7:0] \$166 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \$169 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *)
  wire \$171 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *)
  wire \$173 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *)
  wire [63:0] \$175 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *)
  wire [31:0] \$176 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *)
  wire [63:0] \$179 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *)
  wire [63:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *)
  wire [63:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *)
  wire [63:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" *)
  reg [31:0] a32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" *)
  reg [63:0] b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" *)
  wire [63:0] bpermd_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" *)
  reg [63:0] bpermd_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" *)
  reg [63:0] bpermd_rs;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *)
  wire [6:0] clz_lz;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" *)
  reg [63:0] clz_sig_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" *)
  reg [63:0] cntz_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" *)
  reg count_right;
  (* src = "libresoc.v:150470.7-150470.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" *)
  reg par0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" *)
  reg par1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" *)
  reg [63:0] popcount_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" *)
  reg [63:0] popcount_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" *)
  wire [63:0] popcount_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$20 ;
  assign _029_ = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" *) rb;
  assign _030_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _031_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _032_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _033_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _034_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _035_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _036_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _037_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _038_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _039_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _040_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _041_ = ra[47:40] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[47:40];
  assign _042_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _043_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _044_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _045_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _046_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _047_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _048_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _049_ = ra[55:48] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[55:48];
  assign _050_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _051_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _052_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _053_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _054_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _055_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _056_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _057_ = ra[63:56] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[63:56];
  assign _058_ = logical_op__data_len[3] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *) 1'h1;
  assign _059_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _060_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _061_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _062_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _063_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _064_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _065_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _066_ = ra[7:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[7:0];
  assign _067_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _068_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _069_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _070_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _071_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _072_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _073_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _074_ = ra[15:8] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[15:8];
  assign _075_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _076_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _077_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _078_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _079_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _080_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _081_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _082_ = ra[23:16] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[23:16];
  assign _083_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _084_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _085_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _086_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _087_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _088_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _089_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _090_ = ra[31:24] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[31:24];
  assign _091_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _092_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _093_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _094_ = ra[39:32] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" *) rb[39:32];
  assign _095_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) \$158 ;
  assign _096_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) clz_lz;
  assign _097_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$166 ;
  assign _098_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) logical_op__data_len;
  assign _099_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) \$176 ;
  assign _100_ = ra | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" *) rb;
  assign _101_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) _095_;
  assign _102_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" *) _096_;
  assign _103_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) _097_;
  assign _104_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *) _098_;
  assign _105_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) _099_;
  assign _106_ = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" *) { ra[24], ra[16], ra[8], ra[0] };
  assign _107_ = ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" *) { ra[56], ra[48], ra[40], ra[32] };
  assign _108_ = clz_lz - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) 6'h20;
  assign _109_ = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" *) \$162  : \$164 ;
  assign _110_ = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" *) { a32[0], a32[1], a32[2], a32[3], a32[4], a32[5], a32[6], a32[7], a32[8], a32[9], a32[10], a32[11], a32[12], a32[13], a32[14], a32[15], a32[16], a32[17], a32[18], a32[19], a32[20], a32[21], a32[22], a32[23], a32[24], a32[25], a32[26], a32[27], a32[28], a32[29], a32[30], a32[31] } : a32;
  assign _111_ = count_right ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" *) { ra[0], ra[1], ra[2], ra[3], ra[4], ra[5], ra[6], ra[7], ra[8], ra[9], ra[10], ra[11], ra[12], ra[13], ra[14], ra[15], ra[16], ra[17], ra[18], ra[19], ra[20], ra[21], ra[22], ra[23], ra[24], ra[25], ra[26], ra[27], ra[28], ra[29], ra[30], ra[31], ra[32], ra[33], ra[34], ra[35], ra[36], ra[37], ra[38], ra[39], ra[40], ra[41], ra[42], ra[43], ra[44], ra[45], ra[46], ra[47], ra[48], ra[49], ra[50], ra[51], ra[52], ra[53], ra[54], ra[55], ra[56], ra[57], ra[58], ra[59], ra[60], ra[61], ra[62], ra[63] } : ra;
  assign _112_ = par0 ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" *) par1;
  assign _113_ = ra ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" *) rb;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:151017.10-151021.4" *)
  bpermd bpermd (
    .ra(bpermd_ra),
    .rb(bpermd_rb),
    .rs(bpermd_rs)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:151022.7-151025.4" *)
  clz clz (
    .lz(clz_lz),
    .sig_in(clz_sig_in)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:151026.12-151030.4" *)
  popcount popcount (
    .a(popcount_a),
    .data_len(popcount_data_len),
    .o(popcount_o)
  );
  always @* begin
    if (\initial ) begin end
    _007_ = 1'h0;
  end
  always @* begin
      \initial  <= _007_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _022_;
    _008_ = _021_;
    (* src = "libresoc.v:151032.5-151032.29" *)
    casez (\initial )
      /* src = "libresoc.v:151032.9-151032.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
        begin
          _022_ = 1'h1;
          _021_ = \$21 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
        begin
          _022_ = 1'h1;
          _021_ = \$23 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
        begin
          _022_ = 1'h1;
          _021_ = \$25 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
        begin
          _022_ = 1'h1;
          _021_ = { \$139 , \$141 , \$143 , \$145 , \$147 , \$149 , \$151 , \$153 , \$123 , \$125 , \$127 , \$129 , \$131 , \$133 , \$135 , \$137 , \$107 , \$109 , \$111 , \$113 , \$115 , \$117 , \$119 , \$121 , \$91 , \$93 , \$95 , \$97 , \$99 , \$101 , \$103 , \$105 , \$75 , \$77 , \$79 , \$81 , \$83 , \$85 , \$87 , \$89 , \$59 , \$61 , \$63 , \$65 , \$67 , \$69 , \$71 , \$73 , \$43 , \$45 , \$47 , \$49 , \$51 , \$53 , \$55 , \$57 , \$27 , \$29 , \$31 , \$33 , \$35 , \$37 , \$39 , \$41  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
        begin
          _022_ = 1'h1;
          _021_ = popcount_o;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
        begin
          _022_ = 1'h1;
          _021_ = _028_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" *)
          casez (\$155 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _028_ = \$157 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                { _028_[63:33], _028_[31:1] } = 62'h0000000000000000;
                _028_[0] = par0;
                _028_[32] = par1;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
        begin
          _022_ = 1'h1;
          _021_ = \$161 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h09:
        begin
          _022_ = 1'h1;
          _021_ = bpermd_ra;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _021_ = 64'h0000000000000000;
          _022_ = 1'h0;
        end
    endcase
  end
  always @* begin
      o_ok <= _009_;
      o <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _018_;
    (* src = "libresoc.v:151087.5-151087.29" *)
    casez (\initial )
      /* src = "libresoc.v:151087.9-151087.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _018_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
        begin
          _018_ = cntz_i;
        end
      default:
          _018_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      clz_sig_in <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _017_;
    (* src = "libresoc.v:151122.5-151122.29" *)
    casez (\initial )
      /* src = "libresoc.v:151122.9-151122.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
          _017_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h09:
        begin
          _017_ = ra;
        end
      default:
          _017_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      bpermd_rs <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _016_;
    (* src = "libresoc.v:151161.5-151161.29" *)
    casez (\initial )
      /* src = "libresoc.v:151161.9-151161.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
          _016_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h09:
        begin
          _016_ = rb;
        end
      default:
          _016_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      bpermd_rb <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _025_;
    (* src = "libresoc.v:151200.5-151200.29" *)
    casez (\initial )
      /* src = "libresoc.v:151200.9-151200.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _025_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _025_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _025_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _025_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
        begin
          _025_ = ra;
        end
      default:
          _025_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      popcount_a <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _015_;
    (* src = "libresoc.v:151227.5-151227.29" *)
    casez (\initial )
      /* src = "libresoc.v:151227.9-151227.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _015_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _015_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _015_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _015_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
        begin
          _015_ = rb;
        end
      default:
          _015_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      b <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _026_;
    (* src = "libresoc.v:151254.5-151254.29" *)
    casez (\initial )
      /* src = "libresoc.v:151254.9-151254.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _026_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _026_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _026_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _026_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
        begin
          _026_ = \$169 ;
        end
      default:
          _026_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      popcount_data_len <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _023_;
    (* src = "libresoc.v:151281.5-151281.29" *)
    casez (\initial )
      /* src = "libresoc.v:151281.9-151281.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _023_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _023_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _023_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _023_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _023_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
        begin
          _023_ = \$171 ;
        end
      default:
          _023_ = 1'h0;
    endcase
  end
  always @* begin
      par0 <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _024_;
    (* src = "libresoc.v:151312.5-151312.29" *)
    casez (\initial )
      /* src = "libresoc.v:151312.9-151312.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _024_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _024_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _024_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _024_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _024_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
        begin
          _024_ = \$173 ;
        end
      default:
          _024_ = 1'h0;
    endcase
  end
  always @* begin
      par1 <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _020_;
    (* src = "libresoc.v:151343.5-151343.29" *)
    casez (\initial )
      /* src = "libresoc.v:151343.9-151343.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _020_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
        begin
          _020_ = logical_op__insn[10];
        end
      default:
          _020_ = 1'h0;
    endcase
  end
  always @* begin
      count_right <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _014_;
    (* src = "libresoc.v:151378.5-151378.29" *)
    casez (\initial )
      /* src = "libresoc.v:151378.9-151378.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _014_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
        begin
          _014_ = ra[31:0];
        end
      default:
          _014_ = 32'd0;
    endcase
  end
  always @* begin
      a32 <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _019_;
    (* src = "libresoc.v:151413.5-151413.29" *)
    casez (\initial )
      /* src = "libresoc.v:151413.9-151413.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h04:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h35:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h43:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0b:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h36:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h37:
          _019_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      7'h0e:
        begin
          _019_ = _027_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" *)
          casez (logical_op__is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _027_ = \$175 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _027_ = \$179 ;
              end
          endcase
        end
      default:
          _019_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      cntz_i <= _005_;
  end
  assign \$99  = _030_;
  assign \$101  = _031_;
  assign \$103  = _032_;
  assign \$105  = _033_;
  assign \$107  = _034_;
  assign \$109  = _035_;
  assign \$111  = _036_;
  assign \$113  = _037_;
  assign \$115  = _038_;
  assign \$117  = _039_;
  assign \$119  = _040_;
  assign \$121  = _041_;
  assign \$123  = _042_;
  assign \$125  = _043_;
  assign \$127  = _044_;
  assign \$129  = _045_;
  assign \$131  = _046_;
  assign \$133  = _047_;
  assign \$135  = _048_;
  assign \$137  = _049_;
  assign \$139  = _050_;
  assign \$141  = _051_;
  assign \$143  = _052_;
  assign \$145  = _053_;
  assign \$147  = _054_;
  assign \$149  = _055_;
  assign \$151  = _056_;
  assign \$153  = _057_;
  assign \$155  = _058_;
  assign \$158  = _112_;
  assign \$157  = _101_;
  assign \$162  = _108_;
  assign \$164  = _102_;
  assign \$166  = _109_;
  assign \$161  = _103_;
  assign \$169  = _104_;
  assign \$171  = _106_;
  assign \$173  = _107_;
  assign \$176  = _110_;
  assign \$175  = _105_;
  assign \$179  = _111_;
  assign \$21  = _029_;
  assign \$23  = _100_;
  assign \$25  = _113_;
  assign \$27  = _059_;
  assign \$29  = _060_;
  assign \$31  = _061_;
  assign \$33  = _062_;
  assign \$35  = _063_;
  assign \$37  = _064_;
  assign \$39  = _065_;
  assign \$41  = _066_;
  assign \$43  = _067_;
  assign \$45  = _068_;
  assign \$47  = _069_;
  assign \$49  = _070_;
  assign \$51  = _071_;
  assign \$53  = _072_;
  assign \$55  = _073_;
  assign \$57  = _074_;
  assign \$59  = _075_;
  assign \$61  = _076_;
  assign \$63  = _077_;
  assign \$65  = _078_;
  assign \$67  = _079_;
  assign \$69  = _080_;
  assign \$71  = _081_;
  assign \$73  = _082_;
  assign \$75  = _083_;
  assign \$77  = _084_;
  assign \$79  = _085_;
  assign \$81  = _086_;
  assign \$83  = _087_;
  assign \$85  = _088_;
  assign \$87  = _089_;
  assign \$89  = _090_;
  assign \$91  = _091_;
  assign \$93  = _092_;
  assign \$95  = _093_;
  assign \$97  = _094_;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$20  = xer_so;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:151462.1-152065.10" *)
module \main$9 (cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:151852.3-151878.6" *)
  reg [1:0] _00_;
  (* src = "libresoc.v:151946.3-151960.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:151961.3-151975.6" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:151976.3-152000.6" *)
  reg _03_;
  (* src = "libresoc.v:152001.3-152025.6" *)
  reg _04_;
  (* src = "libresoc.v:152026.3-152040.6" *)
  reg _05_;
  (* src = "libresoc.v:151931.3-151945.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:151744.3-151778.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:151744.3-151778.6" *)
  reg _08_;
  (* src = "libresoc.v:151879.3-151915.6" *)
  reg _09_;
  (* src = "libresoc.v:152041.3-152059.6" *)
  reg [31:0] _10_;
  (* src = "libresoc.v:151779.3-151797.6" *)
  reg _11_;
  (* src = "libresoc.v:151463.7-151463.20" *)
  reg _12_;
  (* src = "libresoc.v:151916.3-151930.6" *)
  reg [3:0] _13_;
  (* src = "libresoc.v:151798.3-151851.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:151798.3-151851.6" *)
  reg _15_;
  (* src = "libresoc.v:151852.3-151878.6" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:151946.3-151960.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:151961.3-151975.6" *)
  reg [1:0] _18_;
  (* src = "libresoc.v:151976.3-152000.6" *)
  reg _19_;
  (* src = "libresoc.v:152001.3-152025.6" *)
  reg _20_;
  (* src = "libresoc.v:152026.3-152040.6" *)
  reg _21_;
  (* src = "libresoc.v:151931.3-151945.6" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:151744.3-151778.6" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:151744.3-151778.6" *)
  reg _24_;
  (* src = "libresoc.v:151879.3-151915.6" *)
  reg _25_;
  (* src = "libresoc.v:152041.3-152059.6" *)
  reg [31:0] _26_;
  (* src = "libresoc.v:151779.3-151797.6" *)
  reg _27_;
  (* src = "libresoc.v:151916.3-151930.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:151798.3-151851.6" *)
  reg [63:0] _29_;
  (* src = "libresoc.v:151798.3-151851.6" *)
  reg _30_;
  (* src = "libresoc.v:151976.3-152000.6" *)
  reg _31_;
  (* src = "libresoc.v:152001.3-152025.6" *)
  reg _32_;
  (* src = "libresoc.v:151744.3-151778.6" *)
  reg [3:0] _33_;
  (* src = "libresoc.v:151879.3-151915.6" *)
  reg _34_;
  (* src = "libresoc.v:151798.3-151851.6" *)
  reg [63:0] _35_;
  (* src = "libresoc.v:151740.18-151740.96" *)
  wire [63:0] _36_;
  (* src = "libresoc.v:151742.18-151742.98" *)
  wire [64:0] _37_;
  (* src = "libresoc.v:151743.17-151743.92" *)
  wire [4:0] _38_;
  (* src = "libresoc.v:151740.18-151740.96" *)
  wire [63:0] _39_;
  (* src = "libresoc.v:151742.18-151742.98" *)
  wire [64:0] _40_;
  (* src = "libresoc.v:151743.17-151743.92" *)
  wire [4:0] _41_;
  (* src = "libresoc.v:151734.18-151734.116" *)
  wire [2:0] _42_;
  (* src = "libresoc.v:151735.18-151735.116" *)
  wire [2:0] _43_;
  (* src = "libresoc.v:151736.18-151736.116" *)
  wire [2:0] _44_;
  (* src = "libresoc.v:151737.18-151737.114" *)
  wire _45_;
  (* src = "libresoc.v:151738.18-151738.115" *)
  wire _46_;
  (* src = "libresoc.v:151739.18-151739.112" *)
  wire _47_;
  (* src = "libresoc.v:151741.18-151741.108" *)
  wire [63:0] _48_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *)
  wire [2:0] \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *)
  wire [2:0] \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *)
  wire [2:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *)
  wire [64:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *)
  wire [63:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [4:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" *)
  reg [1:0] BC;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" *)
  reg [1:0] ba;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" *)
  reg [1:0] bb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" *)
  reg bit_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" *)
  reg bit_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" *)
  reg bit_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" *)
  reg [1:0] bt;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$6 ;
  reg [3:0] \cr_a$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" *)
  reg cr_bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] cr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \cr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \cr_op__insn$4 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] cr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \cr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [31:0] full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [31:0] \full_cr$5 ;
  reg [31:0] \full_cr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output full_cr_ok;
  reg full_cr_ok;
  (* src = "libresoc.v:151463.7-151463.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" *)
  reg [3:0] lut;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  assign _36_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) full_cr;
  assign _37_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) \$27 ;
  assign _38_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) cr_a;
  assign _39_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _36_;
  assign _40_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) _37_;
  assign _41_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _38_;
  assign _42_ = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" *) cr_op__insn[22:21];
  assign _43_ = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" *) cr_op__insn[17:16];
  assign _44_ = 2'h3 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" *) cr_op__insn[12:11];
  assign _45_ = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" *) lut[3] : lut[1];
  assign _46_ = bit_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) lut[2] : lut[0];
  assign _47_ = bit_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" *) \$18  : \$20 ;
  assign _48_ = cr_bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" *) ra : rb;
  always @* begin
    if (\initial ) begin end
    _12_ = 1'h0;
  end
  always @* begin
      \initial  <= _12_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _24_;
    _07_ = _23_;
    (* src = "libresoc.v:151745.5-151745.29" *)
    casez (\initial )
      /* src = "libresoc.v:151745.9-151745.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
        begin
          _23_ = \$7 [3:0];
          _24_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _23_ = _33_;
          _24_ = 1'h1;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" *)
          casez (bt)
            /* src = "libresoc.v:0.0-0.0" */
            2'h0:
              begin
                _33_[3:1] = cr_c[3:1];
                _33_[0] = bit_o;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h1:
              begin
                { _33_[3:2], _33_[0] } = { cr_c[3:2], cr_c[0] };
                _33_[1] = bit_o;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                { _33_[3], _33_[1:0] } = { cr_c[3], cr_c[1:0] };
                _33_[2] = bit_o;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h?:
              begin
                _33_[2:0] = cr_c[2:0];
                _33_[3] = bit_o;
              end
            default:
                _33_ = cr_c;
          endcase
        end
      default:
        begin
          _24_ = 1'h0;
          _23_ = 4'h0;
        end
    endcase
  end
  always @* begin
      cr_a_ok <= _08_;
      \cr_a$6  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _27_;
    (* src = "libresoc.v:151780.5-151780.29" *)
    casez (\initial )
      /* src = "libresoc.v:151780.9-151780.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _27_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
          _27_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h30:
        begin
          _27_ = 1'h1;
        end
      default:
          _27_ = 1'h0;
    endcase
  end
  always @* begin
      full_cr_ok <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _30_;
    _14_ = _29_;
    (* src = "libresoc.v:151799.5-151799.29" *)
    casez (\initial )
      /* src = "libresoc.v:151799.9-151799.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
        begin
          _30_ = 1'h0;
          _29_ = 64'h0000000000000000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _30_ = 1'h0;
          _29_ = 64'h0000000000000000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h30:
        begin
          _30_ = 1'h0;
          _29_ = 64'h0000000000000000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h2d:
        begin
          _29_ = \$24 ;
          _30_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h23:
        begin
          _29_ = \$26 [63:0];
          _30_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h3b:
        begin
          _29_ = _35_;
          _30_ = 1'h1;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" *)
          casez ({ cr_a[2], cr_a[3] })
            /* src = "libresoc.v:0.0-0.0" */
            2'b?1:
              begin
                _35_ = 64'hffffffffffffffff;
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'b1?:
              begin
                _35_ = 64'h0000000000000001;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _35_ = 64'h0000000000000000;
              end
          endcase
        end
      default:
        begin
          _30_ = 1'h0;
          _29_ = 64'h0000000000000000;
        end
    endcase
  end
  always @* begin
      o_ok <= _15_;
      o <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _16_;
    (* src = "libresoc.v:151853.5-151853.29" *)
    casez (\initial )
      /* src = "libresoc.v:151853.9-151853.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _16_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
          _16_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h30:
          _16_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h2d:
          _16_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h23:
        begin
          _16_ = cr_op__insn[7:6];
        end
      default:
          _16_ = 2'h0;
    endcase
  end
  always @* begin
      BC <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _25_;
    (* src = "libresoc.v:151880.5-151880.29" *)
    casez (\initial )
      /* src = "libresoc.v:151880.9-151880.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _25_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
          _25_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h30:
          _25_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h2d:
          _25_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h23:
        begin
          _25_ = _34_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" *)
          casez (BC)
            /* src = "libresoc.v:0.0-0.0" */
            2'h0:
              begin
                _34_ = cr_a[3];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h1:
              begin
                _34_ = cr_a[2];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _34_ = cr_a[1];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h?:
              begin
                _34_ = cr_a[0];
              end
            default:
                _34_ = 1'h0;
          endcase
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      cr_bit <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _28_;
    (* src = "libresoc.v:151917.5-151917.29" *)
    casez (\initial )
      /* src = "libresoc.v:151917.9-151917.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _28_ = 4'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _28_ = cr_op__insn[9:6];
        end
      default:
          _28_ = 4'h0;
    endcase
  end
  always @* begin
      lut <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _22_;
    (* src = "libresoc.v:151932.5-151932.29" *)
    casez (\initial )
      /* src = "libresoc.v:151932.9-151932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _22_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _22_ = \$9 [1:0];
        end
      default:
          _22_ = 2'h0;
    endcase
  end
  always @* begin
      bt <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _17_;
    (* src = "libresoc.v:151947.5-151947.29" *)
    casez (\initial )
      /* src = "libresoc.v:151947.9-151947.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _17_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _17_ = \$12 [1:0];
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      ba <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _18_;
    (* src = "libresoc.v:151962.5-151962.29" *)
    casez (\initial )
      /* src = "libresoc.v:151962.9-151962.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _18_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _18_ = \$15 [1:0];
        end
      default:
          _18_ = 2'h0;
    endcase
  end
  always @* begin
      bb <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _19_;
    (* src = "libresoc.v:151977.5-151977.29" *)
    casez (\initial )
      /* src = "libresoc.v:151977.9-151977.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _19_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _19_ = _31_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" *)
          casez (ba)
            /* src = "libresoc.v:0.0-0.0" */
            2'h0:
              begin
                _31_ = cr_a[0];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h1:
              begin
                _31_ = cr_a[1];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _31_ = cr_a[2];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h?:
              begin
                _31_ = cr_a[3];
              end
            default:
                _31_ = 1'h0;
          endcase
        end
      default:
          _19_ = 1'h0;
    endcase
  end
  always @* begin
      bit_a <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _20_;
    (* src = "libresoc.v:152002.5-152002.29" *)
    casez (\initial )
      /* src = "libresoc.v:152002.9-152002.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _20_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _20_ = _32_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" *)
          casez (bb)
            /* src = "libresoc.v:0.0-0.0" */
            2'h0:
              begin
                _32_ = cr_b[0];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h1:
              begin
                _32_ = cr_b[1];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h2:
              begin
                _32_ = cr_b[2];
              end
            /* src = "libresoc.v:0.0-0.0" */
            2'h?:
              begin
                _32_ = cr_b[3];
              end
            default:
                _32_ = 1'h0;
          endcase
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      bit_b <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _21_;
    (* src = "libresoc.v:152027.5-152027.29" *)
    casez (\initial )
      /* src = "libresoc.v:152027.9-152027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _21_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
        begin
          _21_ = \$22 ;
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      bit_o <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _26_;
    (* src = "libresoc.v:152042.5-152042.29" *)
    casez (\initial )
      /* src = "libresoc.v:152042.9-152042.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" *)
    casez (cr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h2a:
          _26_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h45:
          _26_ = 32'd0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h30:
        begin
          _26_ = ra[31:0];
        end
      default:
          _26_ = 32'd0;
    endcase
  end
  always @* begin
      \full_cr$5  <= _10_;
  end
  assign \$10  = _42_;
  assign \$13  = _43_;
  assign \$16  = _44_;
  assign \$18  = _45_;
  assign \$20  = _46_;
  assign \$22  = _47_;
  assign \$24  = _39_;
  assign \$27  = _48_;
  assign \$26  = _40_;
  assign \$7  = _41_;
  assign \$9  = \$10 ;
  assign \$12  = \$13 ;
  assign \$15  = \$16 ;
  assign { \cr_op__insn$4 , \cr_op__fn_unit$3 , \cr_op__insn_type$2  } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
  assign \muxid$1  = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:152069.1-153230.10" *)
module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ov_ok, dest3_o, xer_so_ok, dest4_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:152801.3-152802.25" *)
  reg _000_;
  (* src = "libresoc.v:152799.3-152800.40" *)
  reg _001_;
  (* src = "libresoc.v:153142.3-153150.6" *)
  reg _002_;
  (* src = "libresoc.v:152727.3-152728.39" *)
  reg _003_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:152755.3-152756.65" *)
  reg [13:0] _005_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:152757.3-152758.79" *)
  reg [63:0] _007_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _008_;
  (* src = "libresoc.v:152759.3-152760.75" *)
  reg _009_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [31:0] _010_;
  (* src = "libresoc.v:152775.3-152776.59" *)
  reg [31:0] _011_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [6:0] _012_;
  (* src = "libresoc.v:152753.3-152754.69" *)
  reg [6:0] _013_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _014_;
  (* src = "libresoc.v:152771.3-152772.67" *)
  reg _015_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _016_;
  (* src = "libresoc.v:152773.3-152774.69" *)
  reg _017_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _018_;
  (* src = "libresoc.v:152765.3-152766.63" *)
  reg _019_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _020_;
  (* src = "libresoc.v:152767.3-152768.63" *)
  reg _021_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _022_;
  (* src = "libresoc.v:152763.3-152764.63" *)
  reg _023_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _024_;
  (* src = "libresoc.v:152761.3-152762.63" *)
  reg _025_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _026_;
  (* src = "libresoc.v:152769.3-152770.69" *)
  reg _027_;
  (* src = "libresoc.v:153133.3-153141.6" *)
  reg _028_;
  (* src = "libresoc.v:152729.3-152730.43" *)
  reg _029_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg [63:0] _030_;
  (* src = "libresoc.v:152749.3-152750.37" *)
  reg [63:0] _031_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg _032_;
  (* src = "libresoc.v:152751.3-152752.43" *)
  reg _033_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg [3:0] _034_;
  (* src = "libresoc.v:152745.3-152746.43" *)
  reg [3:0] _035_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg _036_;
  (* src = "libresoc.v:152747.3-152748.49" *)
  reg _037_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg [1:0] _038_;
  (* src = "libresoc.v:152741.3-152742.47" *)
  reg [1:0] _039_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg _040_;
  (* src = "libresoc.v:152743.3-152744.53" *)
  reg _041_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _042_;
  (* src = "libresoc.v:152737.3-152738.47" *)
  reg _043_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _044_;
  (* src = "libresoc.v:152739.3-152740.53" *)
  reg _045_;
  (* src = "libresoc.v:153151.3-153160.6" *)
  reg [63:0] _046_;
  (* src = "libresoc.v:153161.3-153170.6" *)
  reg [3:0] _047_;
  (* src = "libresoc.v:153171.3-153180.6" *)
  reg [1:0] _048_;
  (* src = "libresoc.v:153181.3-153190.6" *)
  reg _049_;
  (* src = "libresoc.v:152070.7-152070.20" *)
  reg _050_;
  (* src = "libresoc.v:152937.3-152945.6" *)
  reg _051_;
  (* src = "libresoc.v:152785.3-152786.39" *)
  reg _052_;
  (* src = "libresoc.v:152928.3-152936.6" *)
  reg _053_;
  (* src = "libresoc.v:152787.3-152788.39" *)
  reg _054_;
  (* src = "libresoc.v:153191.3-153199.6" *)
  reg [3:0] _055_;
  (* src = "libresoc.v:152797.3-152798.37" *)
  reg [3:0] _056_;
  (* src = "libresoc.v:152882.3-152891.6" *)
  reg _057_;
  (* src = "libresoc.v:152973.3-152981.6" *)
  reg [3:0] _058_;
  (* src = "libresoc.v:152777.3-152778.39" *)
  reg [3:0] _059_;
  (* src = "libresoc.v:152964.3-152972.6" *)
  reg [3:0] _060_;
  (* src = "libresoc.v:152779.3-152780.39" *)
  reg [3:0] _061_;
  (* src = "libresoc.v:152901.3-152909.6" *)
  reg _062_;
  (* src = "libresoc.v:152793.3-152794.41" *)
  reg _063_;
  (* src = "libresoc.v:152892.3-152900.6" *)
  reg _064_;
  (* src = "libresoc.v:152795.3-152796.41" *)
  reg _065_;
  (* src = "libresoc.v:152919.3-152927.6" *)
  reg _066_;
  (* src = "libresoc.v:152789.3-152790.39" *)
  reg _067_;
  (* src = "libresoc.v:152910.3-152918.6" *)
  reg _068_;
  (* src = "libresoc.v:152791.3-152792.39" *)
  reg _069_;
  (* src = "libresoc.v:152955.3-152963.6" *)
  reg [2:0] _070_;
  (* src = "libresoc.v:152781.3-152782.39" *)
  reg [2:0] _071_;
  (* src = "libresoc.v:152946.3-152954.6" *)
  reg [2:0] _072_;
  (* src = "libresoc.v:152783.3-152784.39" *)
  reg [2:0] _073_;
  (* src = "libresoc.v:153103.3-153112.6" *)
  reg [63:0] _074_;
  (* src = "libresoc.v:152735.3-152736.29" *)
  reg [63:0] _075_;
  (* src = "libresoc.v:153113.3-153122.6" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:152733.3-152734.29" *)
  reg [63:0] _077_;
  (* src = "libresoc.v:153123.3-153132.6" *)
  reg _078_;
  (* src = "libresoc.v:152731.3-152732.29" *)
  reg _079_;
  (* src = "libresoc.v:152194.7-152194.24" *)
  reg _080_;
  (* src = "libresoc.v:152204.7-152204.26" *)
  reg _081_;
  (* src = "libresoc.v:153142.3-153150.6" *)
  reg _082_;
  (* src = "libresoc.v:152212.7-152212.25" *)
  reg _083_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [13:0] _084_;
  (* src = "libresoc.v:152235.14-152235.49" *)
  reg [13:0] _085_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [63:0] _086_;
  (* src = "libresoc.v:152239.14-152239.68" *)
  reg [63:0] _087_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _088_;
  (* src = "libresoc.v:152243.7-152243.43" *)
  reg _089_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [31:0] _090_;
  (* src = "libresoc.v:152247.14-152247.43" *)
  reg [31:0] _091_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [6:0] _092_;
  (* src = "libresoc.v:152326.13-152326.47" *)
  reg [6:0] _093_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _094_;
  (* src = "libresoc.v:152330.7-152330.39" *)
  reg _095_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _096_;
  (* src = "libresoc.v:152334.7-152334.40" *)
  reg _097_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _098_;
  (* src = "libresoc.v:152338.7-152338.37" *)
  reg _099_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _100_;
  (* src = "libresoc.v:152342.7-152342.37" *)
  reg _101_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _102_;
  (* src = "libresoc.v:152346.7-152346.37" *)
  reg _103_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _104_;
  (* src = "libresoc.v:152350.7-152350.37" *)
  reg _105_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _106_;
  (* src = "libresoc.v:152354.7-152354.40" *)
  reg _107_;
  (* src = "libresoc.v:153133.3-153141.6" *)
  reg _108_;
  (* src = "libresoc.v:152384.7-152384.27" *)
  reg _109_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg [63:0] _110_;
  (* src = "libresoc.v:152418.14-152418.47" *)
  reg [63:0] _111_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg _112_;
  (* src = "libresoc.v:152422.7-152422.27" *)
  reg _113_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg [3:0] _114_;
  (* src = "libresoc.v:152426.13-152426.33" *)
  reg [3:0] _115_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg _116_;
  (* src = "libresoc.v:152430.7-152430.30" *)
  reg _117_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg [1:0] _118_;
  (* src = "libresoc.v:152434.13-152434.35" *)
  reg [1:0] _119_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg _120_;
  (* src = "libresoc.v:152438.7-152438.32" *)
  reg _121_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _122_;
  (* src = "libresoc.v:152442.7-152442.29" *)
  reg _123_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _124_;
  (* src = "libresoc.v:152446.7-152446.32" *)
  reg _125_;
  (* src = "libresoc.v:153151.3-153160.6" *)
  reg [63:0] _126_;
  (* src = "libresoc.v:153161.3-153170.6" *)
  reg [3:0] _127_;
  (* src = "libresoc.v:153171.3-153180.6" *)
  reg [1:0] _128_;
  (* src = "libresoc.v:153181.3-153190.6" *)
  reg _129_;
  (* src = "libresoc.v:152937.3-152945.6" *)
  reg _130_;
  (* src = "libresoc.v:152466.7-152466.25" *)
  reg _131_;
  (* src = "libresoc.v:152928.3-152936.6" *)
  reg _132_;
  (* src = "libresoc.v:152470.7-152470.25" *)
  reg _133_;
  (* src = "libresoc.v:153191.3-153199.6" *)
  reg [3:0] _134_;
  (* src = "libresoc.v:152588.13-152588.30" *)
  reg [3:0] _135_;
  (* src = "libresoc.v:152882.3-152891.6" *)
  reg _136_;
  (* src = "libresoc.v:152973.3-152981.6" *)
  reg [3:0] _137_;
  (* src = "libresoc.v:152596.13-152596.31" *)
  reg [3:0] _138_;
  (* src = "libresoc.v:152964.3-152972.6" *)
  reg [3:0] _139_;
  (* src = "libresoc.v:152600.13-152600.31" *)
  reg [3:0] _140_;
  (* src = "libresoc.v:152901.3-152909.6" *)
  reg _141_;
  (* src = "libresoc.v:152612.7-152612.26" *)
  reg _142_;
  (* src = "libresoc.v:152892.3-152900.6" *)
  reg _143_;
  (* src = "libresoc.v:152616.7-152616.26" *)
  reg _144_;
  (* src = "libresoc.v:152919.3-152927.6" *)
  reg _145_;
  (* src = "libresoc.v:152620.7-152620.25" *)
  reg _146_;
  (* src = "libresoc.v:152910.3-152918.6" *)
  reg _147_;
  (* src = "libresoc.v:152624.7-152624.25" *)
  reg _148_;
  (* src = "libresoc.v:152955.3-152963.6" *)
  reg [2:0] _149_;
  (* src = "libresoc.v:152638.13-152638.31" *)
  reg [2:0] _150_;
  (* src = "libresoc.v:152946.3-152954.6" *)
  reg [2:0] _151_;
  (* src = "libresoc.v:152642.13-152642.31" *)
  reg [2:0] _152_;
  (* src = "libresoc.v:153103.3-153112.6" *)
  reg [63:0] _153_;
  (* src = "libresoc.v:152648.14-152648.43" *)
  reg [63:0] _154_;
  (* src = "libresoc.v:153113.3-153122.6" *)
  reg [63:0] _155_;
  (* src = "libresoc.v:152652.14-152652.43" *)
  reg [63:0] _156_;
  (* src = "libresoc.v:153123.3-153132.6" *)
  reg _157_;
  (* src = "libresoc.v:152656.7-152656.20" *)
  reg _158_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg [63:0] _159_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _160_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _161_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _162_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _163_;
  (* src = "libresoc.v:152982.3-153014.6" *)
  reg _164_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg [63:0] _165_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg _166_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg [3:0] _167_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg _168_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg [1:0] _169_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg _170_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _171_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _172_;
  (* src = "libresoc.v:153015.3-153036.6" *)
  reg _173_;
  (* src = "libresoc.v:153037.3-153058.6" *)
  reg _174_;
  (* src = "libresoc.v:153059.3-153080.6" *)
  reg _175_;
  (* src = "libresoc.v:153081.3-153102.6" *)
  reg _176_;
  (* src = "libresoc.v:152667.19-152667.113" *)
  wire [2:0] _177_;
  (* src = "libresoc.v:152668.19-152668.125" *)
  wire _178_;
  (* src = "libresoc.v:152669.19-152669.125" *)
  wire _179_;
  (* src = "libresoc.v:152670.19-152670.125" *)
  wire _180_;
  (* src = "libresoc.v:152671.19-152671.125" *)
  wire _181_;
  (* src = "libresoc.v:152672.18-152672.110" *)
  wire _182_;
  (* src = "libresoc.v:152673.19-152673.149" *)
  wire [3:0] _183_;
  (* src = "libresoc.v:152674.19-152674.121" *)
  wire [3:0] _184_;
  (* src = "libresoc.v:152675.19-152675.127" *)
  wire _185_;
  (* src = "libresoc.v:152676.19-152676.127" *)
  wire _186_;
  (* src = "libresoc.v:152677.19-152677.127" *)
  wire _187_;
  (* src = "libresoc.v:152678.19-152678.127" *)
  wire _188_;
  (* src = "libresoc.v:152680.18-152680.98" *)
  wire _189_;
  (* src = "libresoc.v:152682.18-152682.100" *)
  wire _190_;
  (* src = "libresoc.v:152683.18-152683.160" *)
  wire [3:0] _191_;
  (* src = "libresoc.v:152685.18-152685.119" *)
  wire [3:0] _192_;
  (* src = "libresoc.v:152688.17-152688.123" *)
  wire _193_;
  (* src = "libresoc.v:152689.18-152689.116" *)
  wire _194_;
  (* src = "libresoc.v:152694.18-152694.113" *)
  wire _195_;
  (* src = "libresoc.v:152695.18-152695.125" *)
  wire [3:0] _196_;
  (* src = "libresoc.v:152697.18-152697.112" *)
  wire _197_;
  (* src = "libresoc.v:152699.18-152699.126" *)
  wire _198_;
  (* src = "libresoc.v:152700.18-152700.126" *)
  wire _199_;
  (* src = "libresoc.v:152701.18-152701.117" *)
  wire _200_;
  (* src = "libresoc.v:152707.18-152707.130" *)
  wire _201_;
  (* src = "libresoc.v:152708.18-152708.124" *)
  wire [3:0] _202_;
  (* src = "libresoc.v:152710.18-152710.116" *)
  wire _203_;
  (* src = "libresoc.v:152711.18-152711.119" *)
  wire _204_;
  (* src = "libresoc.v:152712.18-152712.121" *)
  wire _205_;
  (* src = "libresoc.v:152713.18-152713.121" *)
  wire _206_;
  (* src = "libresoc.v:152720.18-152720.134" *)
  wire _207_;
  (* src = "libresoc.v:152722.18-152722.132" *)
  wire _208_;
  (* src = "libresoc.v:152723.18-152723.149" *)
  wire [2:0] _209_;
  (* src = "libresoc.v:152725.18-152725.129" *)
  wire [2:0] _210_;
  (* src = "libresoc.v:152696.18-152696.113" *)
  wire _211_;
  (* src = "libresoc.v:152698.18-152698.119" *)
  wire _212_;
  (* src = "libresoc.v:152679.18-152679.97" *)
  wire _213_;
  (* src = "libresoc.v:152681.18-152681.99" *)
  wire _214_;
  (* src = "libresoc.v:152684.18-152684.113" *)
  wire [3:0] _215_;
  (* src = "libresoc.v:152687.18-152687.106" *)
  wire _216_;
  (* src = "libresoc.v:152693.18-152693.120" *)
  wire _217_;
  (* src = "libresoc.v:152704.17-152704.113" *)
  wire [2:0] _218_;
  (* src = "libresoc.v:152724.18-152724.131" *)
  wire _219_;
  (* src = "libresoc.v:152726.18-152726.114" *)
  wire [2:0] _220_;
  (* src = "libresoc.v:152692.18-152692.112" *)
  wire _221_;
  (* src = "libresoc.v:152702.18-152702.122" *)
  wire _222_;
  (* src = "libresoc.v:152703.18-152703.124" *)
  wire _223_;
  (* src = "libresoc.v:152705.18-152705.168" *)
  wire [3:0] _224_;
  (* src = "libresoc.v:152706.18-152706.155" *)
  wire [2:0] _225_;
  (* src = "libresoc.v:152709.18-152709.120" *)
  wire [3:0] _226_;
  (* src = "libresoc.v:152715.17-152715.117" *)
  wire [2:0] _227_;
  (* src = "libresoc.v:152721.17-152721.104" *)
  wire _228_;
  (* src = "libresoc.v:152686.18-152686.106" *)
  wire _229_;
  (* src = "libresoc.v:152690.18-152690.113" *)
  wire _230_;
  (* src = "libresoc.v:152691.18-152691.112" *)
  wire _231_;
  (* src = "libresoc.v:152714.18-152714.160" *)
  wire _232_;
  (* src = "libresoc.v:152716.18-152716.172" *)
  wire [63:0] _233_;
  (* src = "libresoc.v:152717.18-152717.118" *)
  wire [63:0] _234_;
  (* src = "libresoc.v:152718.18-152718.115" *)
  wire [63:0] _235_;
  (* src = "libresoc.v:152719.18-152719.118" *)
  wire _236_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [3:0] \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [3:0] \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [3:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [3:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [3:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [3:0] \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [3:0] \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [2:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [3:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [3:0] \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$80 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$82 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$84 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [2:0] \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_mul0_cr_a;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_mul0_mul_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_mul0_mul_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_mul0_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_mul0_mul_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__imm_data__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_mul0_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_mul0_mul_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_mul0_mul_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_mul0_mul_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_mul0_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_mul0_mul_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_mul0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_mul0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_mul0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_mul0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_mul0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_mul0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_mul0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_mul0_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire alu_mul0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \alu_mul0_xer_so$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [3:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [2:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [3:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r1__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r1__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r2__xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r2__xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest2_o;
  reg [3:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest3_o;
  reg [1:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output dest4_o;
  reg dest4_o;
  (* src = "libresoc.v:152070.7-152070.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_mul0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_mul0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_mul0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_mul0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_mul0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [3:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [3:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [3:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [2:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [3:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src3_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  assign _177_ = \$96  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$98 ;
  assign _178_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _179_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _180_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _181_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _182_ = \$2  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ;
  assign _183_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$102 , \$104 , \$106 , \$108  };
  assign _184_ = \$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _185_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _186_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _187_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _188_ = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _189_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ;
  assign _190_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ;
  assign _191_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _192_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _193_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _194_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ;
  assign _195_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ;
  assign _196_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _197_ = \$40  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ;
  assign _198_ = \$48  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_mul0_n_ready_i;
  assign _199_ = \$50  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_mul0_n_valid_o;
  assign _200_ = \$52  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _201_ = alu_mul0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _202_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _203_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _204_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _205_ = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _206_ = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _207_ = alu_mul0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _208_ = alu_mul0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _209_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _210_ = \$92  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 1'h1, \$94 , 1'h1 };
  assign _211_ = \$42  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _212_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _213_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _214_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _215_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _216_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _217_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_mul0_n_ready_i;
  assign _218_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _219_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_mul0_mul_op__imm_data__ok;
  assign _220_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _221_ = \$32  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ;
  assign _222_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _223_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _224_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _225_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _226_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _227_ = \$5  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _228_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ;
  assign _229_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ;
  assign _230_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _231_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _232_ = alu_mul0_mul_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _233_ = alu_mul0_mul_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_mul0_mul_op__imm_data__data : src2_i;
  assign _234_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _235_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1;
  assign _236_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152803.15-152809.4" *)
  \alu_l$107  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152810.12-152840.4" *)
  alu_mul0 alu_mul0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_mul0_cr_a),
    .cr_a_ok(cr_a_ok),
    .mul_op__fn_unit(alu_mul0_mul_op__fn_unit),
    .mul_op__imm_data__data(alu_mul0_mul_op__imm_data__data),
    .mul_op__imm_data__ok(alu_mul0_mul_op__imm_data__ok),
    .mul_op__insn(alu_mul0_mul_op__insn),
    .mul_op__insn_type(alu_mul0_mul_op__insn_type),
    .mul_op__is_32bit(alu_mul0_mul_op__is_32bit),
    .mul_op__is_signed(alu_mul0_mul_op__is_signed),
    .mul_op__oe__oe(alu_mul0_mul_op__oe__oe),
    .mul_op__oe__ok(alu_mul0_mul_op__oe__ok),
    .mul_op__rc__ok(alu_mul0_mul_op__rc__ok),
    .mul_op__rc__rc(alu_mul0_mul_op__rc__rc),
    .mul_op__write_cr0(alu_mul0_mul_op__write_cr0),
    .n_ready_i(alu_mul0_n_ready_i),
    .n_valid_o(alu_mul0_n_valid_o),
    .o(alu_mul0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_mul0_p_ready_o),
    .p_valid_i(alu_mul0_p_valid_i),
    .ra(alu_mul0_ra),
    .rb(alu_mul0_rb),
    .xer_ov(alu_mul0_xer_ov),
    .xer_ov_ok(xer_ov_ok),
    .xer_so(alu_mul0_xer_so),
    .\xer_so$1 (\alu_mul0_xer_so$1 ),
    .xer_so_ok(xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152841.16-152847.4" *)
  \alui_l$106  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152848.15-152854.4" *)
  \opc_l$102  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152855.15-152861.4" *)
  \req_l$103  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152862.15-152868.4" *)
  \rok_l$105  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152869.15-152874.4" *)
  \rst_l$104  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:152875.15-152881.4" *)
  \src_l$101  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _050_ = 1'h0;
  end
  always @* begin
      \initial  <= _050_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__fn_unit <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__imm_data__data <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__imm_data__ok <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__insn <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__insn_type <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__is_32bit <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__is_signed <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__oe__oe <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__oe__ok <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__rc__ok <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__rc__rc <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_mul0_mul_op__write_cr0 <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a_ok <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ov <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ov_ok <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so_ok <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 4'hf;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r3__xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \data_r3__xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so_ok <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \data_r2__xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ov <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \data_r2__xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ov_ok <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \data_r1__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \data_r1__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a_ok <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_mul0_mul_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__insn_type <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_mul0_mul_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__fn_unit <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_mul0_mul_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__imm_data__data <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_mul0_mul_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__imm_data__ok <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \alu_mul0_mul_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__rc__rc <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \alu_mul0_mul_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__rc__ok <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_mul0_mul_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__oe__oe <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alu_mul0_mul_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__oe__ok <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \alu_mul0_mul_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__write_cr0 <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \alu_mul0_mul_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__is_32bit <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \alu_mul0_mul_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__is_signed <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_mul0_mul_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_mul0_mul_op__insn <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = alu_mul0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$10 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _136_;
    (* src = "libresoc.v:152883.5-152883.29" *)
    casez (\initial )
      /* src = "libresoc.v:152883.9-152883.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$54 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = 1'h1;
        end
      default:
          _136_ = \$46 ;
    endcase
  end
  always @* begin
      req_done <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _143_;
    (* src = "libresoc.v:152893.5-152893.29" *)
    casez (\initial )
      /* src = "libresoc.v:152893.9-152893.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 1'h0;
        end
      default:
          _143_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _141_;
    (* src = "libresoc.v:152902.5-152902.29" *)
    casez (\initial )
      /* src = "libresoc.v:152902.9-152902.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 1'h1;
        end
      default:
          _141_ = \$64 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = _147_;
    (* src = "libresoc.v:152911.5-152911.29" *)
    casez (\initial )
      /* src = "libresoc.v:152911.9-152911.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = 1'h0;
        end
      default:
          _147_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _145_;
    (* src = "libresoc.v:152920.5-152920.29" *)
    casez (\initial )
      /* src = "libresoc.v:152920.9-152920.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 1'h1;
        end
      default:
          _145_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _132_;
    (* src = "libresoc.v:152929.5-152929.29" *)
    casez (\initial )
      /* src = "libresoc.v:152929.9-152929.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h0;
        end
      default:
          _132_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _130_;
    (* src = "libresoc.v:152938.5-152938.29" *)
    casez (\initial )
      /* src = "libresoc.v:152938.9-152938.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h1;
        end
      default:
          _130_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _151_;
    (* src = "libresoc.v:152947.5-152947.29" *)
    casez (\initial )
      /* src = "libresoc.v:152947.9-152947.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = 3'h0;
        end
      default:
          _151_ = { cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _149_;
    (* src = "libresoc.v:152956.5-152956.29" *)
    casez (\initial )
      /* src = "libresoc.v:152956.9-152956.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _149_ = 3'h7;
        end
      default:
          _149_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _139_;
    (* src = "libresoc.v:152965.5-152965.29" *)
    casez (\initial )
      /* src = "libresoc.v:152965.9-152965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _139_ = 4'h0;
        end
      default:
          _139_ = \$66 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _137_;
    (* src = "libresoc.v:152974.5-152974.29" *)
    casez (\initial )
      /* src = "libresoc.v:152974.9-152974.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _137_ = 4'hf;
        end
      default:
          _137_ = \$68 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _084_;
    _010_ = _090_;
    _012_ = _092_;
    _014_ = _094_;
    _016_ = _096_;
    _026_ = _106_;
    _006_ = _159_;
    _008_ = _160_;
    _018_ = _161_;
    _020_ = _162_;
    _022_ = _163_;
    _024_ = _164_;
    (* src = "libresoc.v:152983.5-152983.29" *)
    casez (\initial )
      /* src = "libresoc.v:152983.9-152983.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _090_, _096_, _094_, _106_, _100_, _098_, _102_, _104_, _088_, _086_, _084_, _092_ } = { oper_i_alu_mul0__insn, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__insn_type };
        end
      default:
        begin
          _084_ = alu_mul0_mul_op__fn_unit;
          _086_ = alu_mul0_mul_op__imm_data__data;
          _088_ = alu_mul0_mul_op__imm_data__ok;
          _090_ = alu_mul0_mul_op__insn;
          _092_ = alu_mul0_mul_op__insn_type;
          _094_ = alu_mul0_mul_op__is_32bit;
          _096_ = alu_mul0_mul_op__is_signed;
          _098_ = alu_mul0_mul_op__oe__oe;
          _100_ = alu_mul0_mul_op__oe__ok;
          _102_ = alu_mul0_mul_op__rc__ok;
          _104_ = alu_mul0_mul_op__rc__rc;
          _106_ = alu_mul0_mul_op__write_cr0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _159_ = 64'h0000000000000000;
          _160_ = 1'h0;
          _164_ = 1'h0;
          _163_ = 1'h0;
          _161_ = 1'h0;
          _162_ = 1'h0;
        end
      default:
        begin
          _159_ = _086_;
          _160_ = _088_;
          _161_ = _098_;
          _162_ = _100_;
          _163_ = _102_;
          _164_ = _104_;
        end
    endcase
  end
  always @* begin
      \alu_mul0_mul_op__fn_unit$next  <= _004_;
      \alu_mul0_mul_op__imm_data__data$next  <= _006_;
      \alu_mul0_mul_op__imm_data__ok$next  <= _008_;
      \alu_mul0_mul_op__insn$next  <= _010_;
      \alu_mul0_mul_op__insn_type$next  <= _012_;
      \alu_mul0_mul_op__is_32bit$next  <= _014_;
      \alu_mul0_mul_op__is_signed$next  <= _016_;
      \alu_mul0_mul_op__oe__oe$next  <= _018_;
      \alu_mul0_mul_op__oe__ok$next  <= _020_;
      \alu_mul0_mul_op__rc__ok$next  <= _022_;
      \alu_mul0_mul_op__rc__rc$next  <= _024_;
      \alu_mul0_mul_op__write_cr0$next  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _165_;
    _032_ = _173_;
    (* src = "libresoc.v:153016.5-153016.29" *)
    casez (\initial )
      /* src = "libresoc.v:153016.9-153016.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _112_, _110_ } = { o_ok, alu_mul0_o };
        end
      default:
        begin
          _110_ = data_r0__o;
          _112_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _166_, _165_ } = 65'h00000000000000000;
        end
      default:
        begin
          _165_ = _110_;
          _166_ = _112_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 1'h0;
        end
      default:
          _173_ = _166_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _030_;
      \data_r0__o_ok$next  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _167_;
    _036_ = _174_;
    (* src = "libresoc.v:153038.5-153038.29" *)
    casez (\initial )
      /* src = "libresoc.v:153038.9-153038.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _116_, _114_ } = { cr_a_ok, alu_mul0_cr_a };
        end
      default:
        begin
          _114_ = data_r1__cr_a;
          _116_ = data_r1__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _168_, _167_ } = 5'h00;
        end
      default:
        begin
          _167_ = _114_;
          _168_ = _116_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _174_ = 1'h0;
        end
      default:
          _174_ = _168_;
    endcase
  end
  always @* begin
      \data_r1__cr_a$next  <= _034_;
      \data_r1__cr_a_ok$next  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _169_;
    _040_ = _175_;
    (* src = "libresoc.v:153060.5-153060.29" *)
    casez (\initial )
      /* src = "libresoc.v:153060.9-153060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _120_, _118_ } = { xer_ov_ok, alu_mul0_xer_ov };
        end
      default:
        begin
          _118_ = data_r2__xer_ov;
          _120_ = data_r2__xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _170_, _169_ } = 3'h0;
        end
      default:
        begin
          _169_ = _118_;
          _170_ = _120_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 1'h0;
        end
      default:
          _175_ = _170_;
    endcase
  end
  always @* begin
      \data_r2__xer_ov$next  <= _038_;
      \data_r2__xer_ov_ok$next  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _171_;
    _044_ = _176_;
    (* src = "libresoc.v:153082.5-153082.29" *)
    casez (\initial )
      /* src = "libresoc.v:153082.9-153082.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _124_, _122_ } = { xer_so_ok, alu_mul0_xer_so };
        end
      default:
        begin
          _122_ = data_r3__xer_so;
          _124_ = data_r3__xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _172_, _171_ } = 2'h0;
        end
      default:
        begin
          _171_ = _122_;
          _172_ = _124_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _176_ = 1'h0;
        end
      default:
          _176_ = _172_;
    endcase
  end
  always @* begin
      \data_r3__xer_so$next  <= _042_;
      \data_r3__xer_so_ok$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = _153_;
    (* src = "libresoc.v:153104.5-153104.29" *)
    casez (\initial )
      /* src = "libresoc.v:153104.9-153104.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = src1_i;
        end
      default:
          _153_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = _155_;
    (* src = "libresoc.v:153114.5-153114.29" *)
    casez (\initial )
      /* src = "libresoc.v:153114.9-153114.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _155_ = src_or_imm;
        end
      default:
          _155_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = _157_;
    (* src = "libresoc.v:153124.5-153124.29" *)
    casez (\initial )
      /* src = "libresoc.v:153124.9-153124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = src3_i;
        end
      default:
          _157_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _108_;
    (* src = "libresoc.v:153134.5-153134.29" *)
    casez (\initial )
      /* src = "libresoc.v:153134.9-153134.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _108_ = 1'h1;
        end
      default:
          _108_ = \$88 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _082_;
    (* src = "libresoc.v:153143.5-153143.29" *)
    casez (\initial )
      /* src = "libresoc.v:153143.9-153143.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _082_ = 1'h1;
        end
      default:
          _082_ = \$90 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _126_;
    (* src = "libresoc.v:153152.5-153152.29" *)
    casez (\initial )
      /* src = "libresoc.v:153152.9-153152.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$114 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = data_r0__o;
        end
      default:
          _126_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _127_;
    (* src = "libresoc.v:153162.5-153162.29" *)
    casez (\initial )
      /* src = "libresoc.v:153162.9-153162.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$116 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = data_r1__cr_a;
        end
      default:
          _127_ = 4'h0;
    endcase
  end
  always @* begin
      dest2_o <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = _128_;
    (* src = "libresoc.v:153172.5-153172.29" *)
    casez (\initial )
      /* src = "libresoc.v:153172.9-153172.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$118 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = data_r2__xer_ov;
        end
      default:
          _128_ = 2'h0;
    endcase
  end
  always @* begin
      dest3_o <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _129_;
    (* src = "libresoc.v:153182.5-153182.29" *)
    casez (\initial )
      /* src = "libresoc.v:153182.9-153182.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$120 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = data_r3__xer_so;
        end
      default:
          _129_ = 1'h0;
    endcase
  end
  always @* begin
      dest4_o <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _134_;
    (* src = "libresoc.v:153192.5-153192.29" *)
    casez (\initial )
      /* src = "libresoc.v:153192.9-153192.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = 4'h0;
        end
      default:
          _134_ = \$20 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _055_;
  end
  assign \$100  = _177_;
  assign \$102  = _178_;
  assign \$104  = _179_;
  assign \$106  = _180_;
  assign \$108  = _181_;
  assign \$10  = _182_;
  assign \$110  = _183_;
  assign \$112  = _184_;
  assign \$114  = _185_;
  assign \$116  = _186_;
  assign \$118  = _187_;
  assign \$120  = _188_;
  assign \$12  = _213_;
  assign \$14  = _189_;
  assign \$16  = _214_;
  assign \$18  = _190_;
  assign \$20  = _191_;
  assign \$24  = _215_;
  assign \$26  = _192_;
  assign \$23  = _229_;
  assign \$22  = _216_;
  assign \$2  = _193_;
  assign \$30  = _194_;
  assign \$32  = _230_;
  assign \$34  = _231_;
  assign \$36  = _221_;
  assign \$38  = _217_;
  assign \$40  = _195_;
  assign \$42  = _196_;
  assign \$44  = _211_;
  assign \$46  = _197_;
  assign \$48  = _212_;
  assign \$50  = _198_;
  assign \$52  = _199_;
  assign \$54  = _200_;
  assign \$56  = _222_;
  assign \$58  = _223_;
  assign \$5  = _218_;
  assign \$60  = _224_;
  assign \$62  = _225_;
  assign \$64  = _201_;
  assign \$66  = _202_;
  assign \$68  = _226_;
  assign \$70  = _203_;
  assign \$72  = _204_;
  assign \$74  = _205_;
  assign \$76  = _206_;
  assign \$78  = _232_;
  assign \$7  = _227_;
  assign \$80  = _233_;
  assign \$82  = _234_;
  assign \$84  = _235_;
  assign \$86  = _236_;
  assign \$88  = _207_;
  assign \$4  = _228_;
  assign \$90  = _208_;
  assign \$92  = _209_;
  assign \$94  = _219_;
  assign \$96  = _210_;
  assign \$98  = _220_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$112 ;
  assign cu_rd__rel_o = \$100 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_mul0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_mul0_p_valid_i = alui_l_q_alui;
  assign \alu_mul0_xer_so$1  = \$86 ;
  assign alu_mul0_rb = \$84 ;
  assign alu_mul0_ra = \$82 ;
  assign src_or_imm = \$80 ;
  assign src_sel = \$78 ;
  assign cu_wrmask_o = { \$76 , \$74 , \$72 , \$70  };
  assign reset_r = \$62 ;
  assign reset_w = \$60 ;
  assign rst_r = \$58 ;
  assign reset = \$56 ;
  assign wr_any = \$36 ;
  assign cu_done_o = \$30 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$18 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_mul0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$14 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$10 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:153234.1-153567.10" *)
module mul1(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , neg_res, neg_res32, muxid);
  (* src = "libresoc.v:153534.18-153534.116" *)
  wire _00_;
  (* src = "libresoc.v:153536.18-153536.116" *)
  wire _01_;
  (* src = "libresoc.v:153537.18-153537.117" *)
  wire _02_;
  (* src = "libresoc.v:153538.18-153538.117" *)
  wire _03_;
  (* src = "libresoc.v:153541.18-153541.95" *)
  wire [64:0] _04_;
  (* src = "libresoc.v:153542.18-153542.91" *)
  wire [64:0] _05_;
  (* src = "libresoc.v:153544.18-153544.95" *)
  wire [64:0] _06_;
  (* src = "libresoc.v:153545.18-153545.91" *)
  wire [64:0] _07_;
  (* src = "libresoc.v:153541.18-153541.95" *)
  wire [64:0] _08_;
  (* src = "libresoc.v:153544.18-153544.95" *)
  wire [64:0] _09_;
  (* src = "libresoc.v:153542.18-153542.91" *)
  wire [64:0] _10_;
  (* src = "libresoc.v:153545.18-153545.91" *)
  wire [64:0] _11_;
  (* src = "libresoc.v:153533.18-153533.125" *)
  wire _12_;
  (* src = "libresoc.v:153535.18-153535.125" *)
  wire _13_;
  (* src = "libresoc.v:153543.18-153543.112" *)
  wire [64:0] _14_;
  (* src = "libresoc.v:153546.18-153546.112" *)
  wire [64:0] _15_;
  (* src = "libresoc.v:153547.18-153547.116" *)
  wire [31:0] _16_;
  (* src = "libresoc.v:153548.18-153548.116" *)
  wire [31:0] _17_;
  (* src = "libresoc.v:153539.18-153539.106" *)
  wire _18_;
  (* src = "libresoc.v:153540.18-153540.110" *)
  wire _19_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
  wire [64:0] \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
  wire [64:0] \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [64:0] \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *)
  wire [64:0] \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
  wire [64:0] \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
  wire [64:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [64:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *)
  wire [64:0] \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
  wire [31:0] \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
  wire [31:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" *)
  wire [63:0] abs_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51" *)
  wire [63:0] abs_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" *)
  wire is_32bit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  output neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  output neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" *)
  wire sign32_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" *)
  wire sign32_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" *)
  wire sign_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" *)
  wire sign_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$16 ;
  assign _00_ = \$17  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) mul_op__is_signed;
  assign _01_ = \$21  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) mul_op__is_signed;
  assign _02_ = ra[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" *) mul_op__is_signed;
  assign _03_ = rb[31] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" *) mul_op__is_signed;
  assign _04_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) ra;
  assign _05_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra;
  assign _06_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) rb;
  assign _07_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb;
  assign _08_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) _04_;
  assign _09_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) _06_;
  assign _10_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _05_;
  assign _11_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _07_;
  assign _12_ = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" *) ra[31] : ra[63];
  assign _13_ = mul_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" *) rb[31] : rb[63];
  assign _14_ = sign_a ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" *) \$34  : \$36 ;
  assign _15_ = sign_b ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" *) \$41  : \$43 ;
  assign _16_ = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_a[63:32];
  assign _17_ = is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_b[63:32];
  assign _18_ = sign_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" *) sign_b;
  assign _19_ = sign32_a ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" *) sign32_b;
  assign \$17  = _12_;
  assign \$19  = _00_;
  assign \$21  = _13_;
  assign \$23  = _01_;
  assign \$25  = _02_;
  assign \$27  = _03_;
  assign \$29  = _18_;
  assign \$31  = _19_;
  assign \$34  = _08_;
  assign \$36  = _10_;
  assign \$38  = _14_;
  assign \$41  = _09_;
  assign \$43  = _11_;
  assign \$45  = _15_;
  assign \$47  = _16_;
  assign \$49  = _17_;
  assign \$33  = \$38 ;
  assign \$40  = \$45 ;
  assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$16  = xer_so;
  assign \rb$15 [63:32] = \$49 ;
  assign \rb$15 [31:0] = abs_b[31:0];
  assign \ra$14 [63:32] = \$47 ;
  assign \ra$14 [31:0] = abs_a[31:0];
  assign abs_b = \$45 [63:0];
  assign abs_a = \$38 [63:0];
  assign neg_res32 = \$31 ;
  assign neg_res = \$29 ;
  assign sign32_b = \$27 ;
  assign sign32_a = \$25 ;
  assign sign_b = \$23 ;
  assign sign_a = \$19 ;
  assign is_32bit = mul_op__is_32bit;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:153571.1-153834.10" *)
module mul2(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , muxid);
  (* src = "libresoc.v:153827.18-153827.98" *)
  wire [128:0] _0_;
  (* src = "libresoc.v:153826.18-153826.99" *)
  wire [127:0] _1_;
  (* src = "libresoc.v:153827.18-153827.98" *)
  wire [128:0] _2_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *)
  wire [128:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *)
  wire [127:0] \$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  input neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  output \neg_res$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  input neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  output \neg_res32$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [128:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$14 ;
  assign _0_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) \$18 ;
  assign _1_ = ra * (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) rb;
  assign _2_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" *) _0_;
  assign \$18  = _1_;
  assign \$17  = _2_;
  assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$14  = xer_so;
  assign \neg_res32$16  = neg_res32;
  assign \neg_res$15  = neg_res;
  assign o = \$17 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:153838.1-154247.10" *)
module mul3(mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:153839.7-153839.20" *)
  reg _00_;
  (* src = "libresoc.v:154176.3-154202.6" *)
  reg _01_;
  (* src = "libresoc.v:154138.3-154156.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:154157.3-154175.6" *)
  reg _03_;
  (* src = "libresoc.v:154203.3-154221.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:154222.3-154240.6" *)
  reg _05_;
  (* src = "libresoc.v:154176.3-154202.6" *)
  reg _06_;
  (* src = "libresoc.v:154138.3-154156.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:154157.3-154175.6" *)
  reg _08_;
  (* src = "libresoc.v:154203.3-154221.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:154222.3-154240.6" *)
  reg _10_;
  (* src = "libresoc.v:154176.3-154202.6" *)
  reg _11_;
  (* src = "libresoc.v:154132.18-154132.104" *)
  wire _12_;
  (* src = "libresoc.v:154136.18-154136.104" *)
  wire _13_;
  (* src = "libresoc.v:154126.18-154126.95" *)
  wire [129:0] _14_;
  (* src = "libresoc.v:154127.18-154127.90" *)
  wire [129:0] _15_;
  (* src = "libresoc.v:154137.18-154137.95" *)
  wire [1:0] _16_;
  (* src = "libresoc.v:154126.18-154126.95" *)
  wire [129:0] _17_;
  (* src = "libresoc.v:154131.18-154131.98" *)
  wire _18_;
  (* src = "libresoc.v:154135.18-154135.98" *)
  wire _19_;
  (* src = "libresoc.v:154127.18-154127.90" *)
  wire [129:0] _20_;
  (* src = "libresoc.v:154137.18-154137.95" *)
  wire [1:0] _21_;
  (* src = "libresoc.v:154130.18-154130.106" *)
  wire _22_;
  (* src = "libresoc.v:154134.18-154134.107" *)
  wire _23_;
  (* src = "libresoc.v:154129.18-154129.106" *)
  wire _24_;
  (* src = "libresoc.v:154133.18-154133.107" *)
  wire _25_;
  (* src = "libresoc.v:154128.18-154128.114" *)
  wire [129:0] _26_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
  wire [129:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
  wire [129:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [129:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *)
  wire [129:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \$39 ;
  (* src = "libresoc.v:153839.7-153839.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" *)
  wire is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" *)
  wire [128:0] mul_o;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" *)
  reg mul_ov;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  input neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [128:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$14 ;
  reg [63:0] \o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  reg [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  assign _12_ = \$23  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$25 ;
  assign _13_ = \$31  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$33 ;
  assign _14_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) o;
  assign _15_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) o;
  assign _16_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) xer_so;
  assign _17_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) _14_;
  assign _18_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) \$26 ;
  assign _19_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) \$34 ;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _15_;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _16_;
  assign _22_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
  assign _23_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
  assign _24_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" *) mul_o[63:31];
  assign _25_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" *) mul_o[127:63];
  assign _26_ = neg_res ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" *) \$17  : \$19 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _07_;
    (* src = "libresoc.v:154139.5-154139.29" *)
    casez (\initial )
      /* src = "libresoc.v:154139.9-154139.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
    casez (mul_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h34:
        begin
          _07_ = { mul_o[63:32], mul_o[63:32] };
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h33:
        begin
          _07_ = mul_o[127:64];
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h32:
        begin
          _07_ = mul_o[63:0];
        end
      default:
          _07_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \o$14  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _08_;
    (* src = "libresoc.v:154158.5-154158.29" *)
    casez (\initial )
      /* src = "libresoc.v:154158.9-154158.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
    casez (mul_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h34:
        begin
          _08_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h33:
        begin
          _08_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h32:
        begin
          _08_ = 1'h1;
        end
      default:
          _08_ = 1'h0;
    endcase
  end
  always @* begin
      o_ok <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _06_;
    (* src = "libresoc.v:154177.5-154177.29" *)
    casez (\initial )
      /* src = "libresoc.v:154177.9-154177.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
    casez (mul_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h34:
          _06_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h33:
          _06_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h32:
        begin
          _06_ = _11_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" *)
          casez (is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _11_ = \$29 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _11_ = \$37 ;
              end
          endcase
        end
      default:
          _06_ = 1'h0;
    endcase
  end
  always @* begin
      mul_ov <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _09_;
    (* src = "libresoc.v:154204.5-154204.29" *)
    casez (\initial )
      /* src = "libresoc.v:154204.9-154204.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
    casez (mul_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h34:
          _09_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h33:
          _09_ = 2'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h32:
        begin
          _09_ = { mul_ov, mul_ov };
        end
      default:
          _09_ = 2'h0;
    endcase
  end
  always @* begin
      xer_ov <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _10_;
    (* src = "libresoc.v:154223.5-154223.29" *)
    casez (\initial )
      /* src = "libresoc.v:154223.9-154223.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" *)
    casez (mul_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h34:
          _10_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h33:
          _10_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      7'h32:
        begin
          _10_ = 1'h1;
        end
      default:
          _10_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _05_;
  end
  assign \$17  = _17_;
  assign \$19  = _20_;
  assign \$21  = _26_;
  assign \$23  = _24_;
  assign \$26  = _22_;
  assign \$25  = _18_;
  assign \$29  = _12_;
  assign \$31  = _25_;
  assign \$34  = _23_;
  assign \$33  = _19_;
  assign \$37  = _13_;
  assign \$39  = _21_;
  assign \$16  = \$21 ;
  assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \muxid$1  = muxid;
  assign { xer_so_ok, \xer_so$15  } = \$39 ;
  assign mul_o = \$21 [128:0];
  assign is_32bit = mul_op__is_32bit;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:154251.1-155468.10" *)
module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, p_valid_i, p_ready_o, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \ra$14 , \rb$15 , \xer_so$16 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:154252.7-154252.20" *)
  reg _00_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [13:0] _01_;
  (* src = "libresoc.v:155210.3-155211.47" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:155212.3-155213.61" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _05_;
  (* src = "libresoc.v:155214.3-155215.57" *)
  reg _06_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [31:0] _07_;
  (* src = "libresoc.v:155230.3-155231.41" *)
  reg [31:0] _08_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [6:0] _09_;
  (* src = "libresoc.v:155208.3-155209.51" *)
  reg [6:0] _10_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _11_;
  (* src = "libresoc.v:155226.3-155227.49" *)
  reg _12_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _13_;
  (* src = "libresoc.v:155228.3-155229.51" *)
  reg _14_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _15_;
  (* src = "libresoc.v:155220.3-155221.45" *)
  reg _16_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _17_;
  (* src = "libresoc.v:155222.3-155223.45" *)
  reg _18_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _19_;
  (* src = "libresoc.v:155218.3-155219.45" *)
  reg _20_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _21_;
  (* src = "libresoc.v:155216.3-155217.45" *)
  reg _22_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _23_;
  (* src = "libresoc.v:155224.3-155225.51" *)
  reg _24_;
  (* src = "libresoc.v:155332.3-155344.6" *)
  reg [1:0] _25_;
  (* src = "libresoc.v:155232.3-155233.27" *)
  reg [1:0] _26_;
  (* src = "libresoc.v:155420.3-155432.6" *)
  reg _27_;
  (* src = "libresoc.v:155433.3-155445.6" *)
  reg _28_;
  (* src = "libresoc.v:155198.3-155199.35" *)
  reg _29_;
  (* src = "libresoc.v:155200.3-155201.31" *)
  reg _30_;
  (* src = "libresoc.v:155314.3-155331.6" *)
  reg _31_;
  (* src = "libresoc.v:155234.3-155235.29" *)
  reg _32_;
  (* src = "libresoc.v:155381.3-155393.6" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:155206.3-155207.21" *)
  reg [63:0] _34_;
  (* src = "libresoc.v:155394.3-155406.6" *)
  reg [63:0] _35_;
  (* src = "libresoc.v:155204.3-155205.21" *)
  reg [63:0] _36_;
  (* src = "libresoc.v:155407.3-155419.6" *)
  reg _37_;
  (* src = "libresoc.v:155202.3-155203.29" *)
  reg _38_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [13:0] _39_;
  (* src = "libresoc.v:154768.14-154768.40" *)
  reg [13:0] _40_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [63:0] _41_;
  (* src = "libresoc.v:154807.14-154807.59" *)
  reg [63:0] _42_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _43_;
  (* src = "libresoc.v:154816.7-154816.34" *)
  reg _44_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [31:0] _45_;
  (* src = "libresoc.v:154825.14-154825.34" *)
  reg [31:0] _46_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [6:0] _47_;
  (* src = "libresoc.v:154909.13-154909.38" *)
  reg [6:0] _48_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _49_;
  (* src = "libresoc.v:155068.7-155068.30" *)
  reg _50_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _51_;
  (* src = "libresoc.v:155077.7-155077.31" *)
  reg _52_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _53_;
  (* src = "libresoc.v:155086.7-155086.28" *)
  reg _54_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _55_;
  (* src = "libresoc.v:155095.7-155095.28" *)
  reg _56_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _57_;
  (* src = "libresoc.v:155104.7-155104.28" *)
  reg _58_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _59_;
  (* src = "libresoc.v:155113.7-155113.28" *)
  reg _60_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _61_;
  (* src = "libresoc.v:155122.7-155122.31" *)
  reg _62_;
  (* src = "libresoc.v:155332.3-155344.6" *)
  reg [1:0] _63_;
  (* src = "libresoc.v:155131.13-155131.25" *)
  reg [1:0] _64_;
  (* src = "libresoc.v:155420.3-155432.6" *)
  reg _65_;
  (* src = "libresoc.v:155433.3-155445.6" *)
  reg _66_;
  (* src = "libresoc.v:155153.7-155153.23" *)
  reg _67_;
  (* src = "libresoc.v:155146.7-155146.21" *)
  reg _68_;
  (* src = "libresoc.v:155314.3-155331.6" *)
  reg _69_;
  (* src = "libresoc.v:155167.7-155167.20" *)
  reg _70_;
  (* src = "libresoc.v:155381.3-155393.6" *)
  reg [63:0] _71_;
  (* src = "libresoc.v:155172.14-155172.39" *)
  reg [63:0] _72_;
  (* src = "libresoc.v:155394.3-155406.6" *)
  reg [63:0] _73_;
  (* src = "libresoc.v:155181.14-155181.39" *)
  reg [63:0] _74_;
  (* src = "libresoc.v:155407.3-155419.6" *)
  reg _75_;
  (* src = "libresoc.v:155190.7-155190.20" *)
  reg _76_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg [63:0] _77_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _78_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _79_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _80_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _81_;
  (* src = "libresoc.v:155345.3-155380.6" *)
  reg _82_;
  (* src = "libresoc.v:155314.3-155331.6" *)
  reg _83_;
  (* src = "libresoc.v:155197.18-155197.118" *)
  wire _84_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:154252.7-154252.15" *)
  reg \initial ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] input_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \input_mul_op__fn_unit$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] input_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \input_mul_op__imm_data__data$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__imm_data__ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] input_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \input_mul_op__insn$29 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] input_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \input_mul_op__insn_type$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__is_32bit$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__is_signed$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__oe__oe$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__oe__ok$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__rc__ok$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__rc__rc$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_mul_op__write_cr0$26 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] input_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \input_muxid$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_ra$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rb$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire input_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \input_xer_so$32 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul1_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul1_mul_op__fn_unit$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul1_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul1_mul_op__imm_data__data$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__imm_data__ok$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul1_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul1_mul_op__insn$45 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul1_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul1_mul_op__insn_type$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__is_32bit$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__is_signed$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__oe__oe$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__oe__ok$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__rc__ok$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__rc__rc$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul1_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul1_mul_op__write_cr0$42 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul1_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul1_muxid$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  wire mul1_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  wire mul1_neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul1_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \mul1_ra$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul1_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \mul1_rb$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul1_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \mul1_xer_so$48 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] mul_op__fn_unit;
  reg [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \mul_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_op__fn_unit$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \mul_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] mul_op__imm_data__data;
  reg [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_op__imm_data__data$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \mul_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__imm_data__ok;
  reg mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__imm_data__ok$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__imm_data__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] mul_op__insn;
  reg [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \mul_op__insn$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_op__insn$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \mul_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] mul_op__insn_type;
  reg [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \mul_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_op__insn_type$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \mul_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__is_32bit;
  reg mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_32bit$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__is_signed;
  reg mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_signed$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__oe__oe;
  reg mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__oe$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__oe__ok;
  reg mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__ok$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__rc__ok;
  reg mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__ok$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__rc__rc;
  reg mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__rc$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output mul_op__write_cr0;
  reg mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__write_cr0$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$52 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  output neg_res;
  reg neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  wire \neg_res$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  reg \neg_res$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  output neg_res32;
  reg neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  wire \neg_res32$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  reg \neg_res32$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] ra;
  reg [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \ra$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \ra$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \ra$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] rb;
  reg [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \rb$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \rb$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \rb$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output xer_so;
  reg xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \xer_so$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg \xer_so$next ;
  assign _84_ = \p_valid_i$49  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:155236.14-155269.4" *)
  \input$95  \input  (
    .mul_op__fn_unit(input_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\input_mul_op__fn_unit$19 ),
    .mul_op__imm_data__data(input_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\input_mul_op__imm_data__data$20 ),
    .mul_op__imm_data__ok(input_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\input_mul_op__imm_data__ok$21 ),
    .mul_op__insn(input_mul_op__insn),
    .\mul_op__insn$13 (\input_mul_op__insn$29 ),
    .mul_op__insn_type(input_mul_op__insn_type),
    .\mul_op__insn_type$2 (\input_mul_op__insn_type$18 ),
    .mul_op__is_32bit(input_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\input_mul_op__is_32bit$27 ),
    .mul_op__is_signed(input_mul_op__is_signed),
    .\mul_op__is_signed$12 (\input_mul_op__is_signed$28 ),
    .mul_op__oe__oe(input_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\input_mul_op__oe__oe$24 ),
    .mul_op__oe__ok(input_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\input_mul_op__oe__ok$25 ),
    .mul_op__rc__ok(input_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\input_mul_op__rc__ok$23 ),
    .mul_op__rc__rc(input_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\input_mul_op__rc__rc$22 ),
    .mul_op__write_cr0(input_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\input_mul_op__write_cr0$26 ),
    .muxid(input_muxid),
    .\muxid$1 (\input_muxid$17 ),
    .ra(input_ra),
    .\ra$14 (\input_ra$30 ),
    .rb(input_rb),
    .\rb$15 (\input_rb$31 ),
    .xer_so(input_xer_so),
    .\xer_so$16 (\input_xer_so$32 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:155270.8-155305.4" *)
  mul1 mul1 (
    .mul_op__fn_unit(mul1_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul1_mul_op__fn_unit$35 ),
    .mul_op__imm_data__data(mul1_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul1_mul_op__imm_data__data$36 ),
    .mul_op__imm_data__ok(mul1_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul1_mul_op__imm_data__ok$37 ),
    .mul_op__insn(mul1_mul_op__insn),
    .\mul_op__insn$13 (\mul1_mul_op__insn$45 ),
    .mul_op__insn_type(mul1_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul1_mul_op__insn_type$34 ),
    .mul_op__is_32bit(mul1_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul1_mul_op__is_32bit$43 ),
    .mul_op__is_signed(mul1_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul1_mul_op__is_signed$44 ),
    .mul_op__oe__oe(mul1_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul1_mul_op__oe__oe$40 ),
    .mul_op__oe__ok(mul1_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul1_mul_op__oe__ok$41 ),
    .mul_op__rc__ok(mul1_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul1_mul_op__rc__ok$39 ),
    .mul_op__rc__rc(mul1_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul1_mul_op__rc__rc$38 ),
    .mul_op__write_cr0(mul1_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul1_mul_op__write_cr0$42 ),
    .muxid(mul1_muxid),
    .\muxid$1 (\mul1_muxid$33 ),
    .neg_res(mul1_neg_res),
    .neg_res32(mul1_neg_res32),
    .ra(mul1_ra),
    .\ra$14 (\mul1_ra$46 ),
    .rb(mul1_rb),
    .\rb$15 (\mul1_rb$47 ),
    .xer_so(mul1_xer_so),
    .\xer_so$16 (\mul1_xer_so$48 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:155306.10-155309.4" *)
  \n$94  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:155310.10-155313.4" *)
  \p$93  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _40_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      mul_op__fn_unit <= _40_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      mul_op__imm_data__data <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__imm_data__ok <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _46_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      mul_op__insn <= _46_;
  end
  always @* begin
    if (\initial ) begin end
    _48_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      mul_op__insn_type <= _48_;
  end
  always @* begin
    if (\initial ) begin end
    _50_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__is_32bit <= _50_;
  end
  always @* begin
    if (\initial ) begin end
    _52_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__is_signed <= _52_;
  end
  always @* begin
    if (\initial ) begin end
    _54_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__oe__oe <= _54_;
  end
  always @* begin
    if (\initial ) begin end
    _56_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__oe__ok <= _56_;
  end
  always @* begin
    if (\initial ) begin end
    _58_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__rc__ok <= _58_;
  end
  always @* begin
    if (\initial ) begin end
    _60_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__rc__rc <= _60_;
  end
  always @* begin
    if (\initial ) begin end
    _62_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      mul_op__write_cr0 <= _62_;
  end
  always @* begin
    if (\initial ) begin end
    _64_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _64_;
  end
  always @* begin
    if (\initial ) begin end
    _68_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      neg_res <= _68_;
  end
  always @* begin
    if (\initial ) begin end
    _67_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      neg_res32 <= _67_;
  end
  always @* begin
    if (\initial ) begin end
    _70_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _70_;
  end
  always @* begin
    if (\initial ) begin end
    _72_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ra <= _72_;
  end
  always @* begin
    if (\initial ) begin end
    _74_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      rb <= _74_;
  end
  always @* begin
    if (\initial ) begin end
    _76_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so <= _76_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = \neg_res32$next ;
  end
  always @(posedge coresync_clk) begin
      neg_res32 <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = \neg_res$next ;
  end
  always @(posedge coresync_clk) begin
      neg_res <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = \xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = \rb$next ;
  end
  always @(posedge coresync_clk) begin
      rb <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _34_ = \ra$next ;
  end
  always @(posedge coresync_clk) begin
      ra <= _34_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \mul_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__insn_type <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \mul_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__fn_unit <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \mul_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__imm_data__data <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \mul_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__imm_data__ok <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = \mul_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__rc__rc <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = \mul_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__rc__ok <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \mul_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__oe__oe <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = \mul_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__oe__ok <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = \mul_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__write_cr0 <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \mul_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__is_32bit <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = \mul_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__is_signed <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \mul_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      mul_op__insn <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = _83_;
    (* src = "libresoc.v:155315.5-155315.29" *)
    casez (\initial )
      /* src = "libresoc.v:155315.9-155315.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _69_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _69_ = 1'h0;
        end
      default:
          _69_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _83_ = 1'h0;
        end
      default:
          _83_ = _69_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = _63_;
    (* src = "libresoc.v:155333.5-155333.29" *)
    casez (\initial )
      /* src = "libresoc.v:155333.9-155333.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _63_ = \muxid$52 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _63_ = \muxid$52 ;
        end
      default:
          _63_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _39_;
    _07_ = _45_;
    _09_ = _47_;
    _11_ = _49_;
    _13_ = _51_;
    _23_ = _61_;
    _03_ = _77_;
    _05_ = _78_;
    _15_ = _79_;
    _17_ = _80_;
    _19_ = _81_;
    _21_ = _82_;
    (* src = "libresoc.v:155346.5-155346.29" *)
    casez (\initial )
      /* src = "libresoc.v:155346.9-155346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _45_, _51_, _49_, _61_, _55_, _53_, _57_, _59_, _43_, _41_, _39_, _47_ } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _45_, _51_, _49_, _61_, _55_, _53_, _57_, _59_, _43_, _41_, _39_, _47_ } = { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53  };
        end
      default:
        begin
          _39_ = mul_op__fn_unit;
          _41_ = mul_op__imm_data__data;
          _43_ = mul_op__imm_data__ok;
          _45_ = mul_op__insn;
          _47_ = mul_op__insn_type;
          _49_ = mul_op__is_32bit;
          _51_ = mul_op__is_signed;
          _53_ = mul_op__oe__oe;
          _55_ = mul_op__oe__ok;
          _57_ = mul_op__rc__ok;
          _59_ = mul_op__rc__rc;
          _61_ = mul_op__write_cr0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 64'h0000000000000000;
          _78_ = 1'h0;
          _82_ = 1'h0;
          _81_ = 1'h0;
          _79_ = 1'h0;
          _80_ = 1'h0;
        end
      default:
        begin
          _77_ = _41_;
          _78_ = _43_;
          _79_ = _53_;
          _80_ = _55_;
          _81_ = _57_;
          _82_ = _59_;
        end
    endcase
  end
  always @* begin
      \mul_op__fn_unit$next  <= _01_;
      \mul_op__imm_data__data$next  <= _03_;
      \mul_op__imm_data__ok$next  <= _05_;
      \mul_op__insn$next  <= _07_;
      \mul_op__insn_type$next  <= _09_;
      \mul_op__is_32bit$next  <= _11_;
      \mul_op__is_signed$next  <= _13_;
      \mul_op__oe__oe$next  <= _15_;
      \mul_op__oe__ok$next  <= _17_;
      \mul_op__rc__ok$next  <= _19_;
      \mul_op__rc__rc$next  <= _21_;
      \mul_op__write_cr0$next  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = _71_;
    (* src = "libresoc.v:155382.5-155382.29" *)
    casez (\initial )
      /* src = "libresoc.v:155382.9-155382.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _71_ = \ra$65 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _71_ = \ra$65 ;
        end
      default:
          _71_ = ra;
    endcase
  end
  always @* begin
      \ra$next  <= _33_;
  end
  always @* begin
    if (\initial ) begin end
    _35_ = _73_;
    (* src = "libresoc.v:155395.5-155395.29" *)
    casez (\initial )
      /* src = "libresoc.v:155395.9-155395.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _73_ = \rb$66 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _73_ = \rb$66 ;
        end
      default:
          _73_ = rb;
    endcase
  end
  always @* begin
      \rb$next  <= _35_;
  end
  always @* begin
    if (\initial ) begin end
    _37_ = _75_;
    (* src = "libresoc.v:155408.5-155408.29" *)
    casez (\initial )
      /* src = "libresoc.v:155408.9-155408.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _75_ = \xer_so$67 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _75_ = \xer_so$67 ;
        end
      default:
          _75_ = xer_so;
    endcase
  end
  always @* begin
      \xer_so$next  <= _37_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _65_;
    (* src = "libresoc.v:155421.5-155421.29" *)
    casez (\initial )
      /* src = "libresoc.v:155421.9-155421.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _65_ = \neg_res$68 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _65_ = \neg_res$68 ;
        end
      default:
          _65_ = neg_res;
    endcase
  end
  always @* begin
      \neg_res$next  <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _66_;
    (* src = "libresoc.v:155434.5-155434.29" *)
    casez (\initial )
      /* src = "libresoc.v:155434.9-155434.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _66_ = \neg_res32$69 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _66_ = \neg_res32$69 ;
        end
      default:
          _66_ = neg_res32;
    endcase
  end
  always @* begin
      \neg_res32$next  <= _28_;
  end
  assign \$50  = _84_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign \neg_res32$69  = mul1_neg_res32;
  assign \neg_res$68  = mul1_neg_res;
  assign \xer_so$67  = \mul1_xer_so$48 ;
  assign \rb$66  = \mul1_rb$47 ;
  assign \ra$65  = \mul1_ra$46 ;
  assign { \mul_op__insn$64 , \mul_op__is_signed$63 , \mul_op__is_32bit$62 , \mul_op__write_cr0$61 , \mul_op__oe__ok$60 , \mul_op__oe__oe$59 , \mul_op__rc__ok$58 , \mul_op__rc__rc$57 , \mul_op__imm_data__ok$56 , \mul_op__imm_data__data$55 , \mul_op__fn_unit$54 , \mul_op__insn_type$53  } = { \mul1_mul_op__insn$45 , \mul1_mul_op__is_signed$44 , \mul1_mul_op__is_32bit$43 , \mul1_mul_op__write_cr0$42 , \mul1_mul_op__oe__ok$41 , \mul1_mul_op__oe__oe$40 , \mul1_mul_op__rc__ok$39 , \mul1_mul_op__rc__rc$38 , \mul1_mul_op__imm_data__ok$37 , \mul1_mul_op__imm_data__data$36 , \mul1_mul_op__fn_unit$35 , \mul1_mul_op__insn_type$34  };
  assign \muxid$52  = \mul1_muxid$33 ;
  assign p_valid_i_p_ready_o = \$50 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$49  = p_valid_i;
  assign mul1_xer_so = \input_xer_so$32 ;
  assign mul1_rb = \input_rb$31 ;
  assign mul1_ra = \input_ra$30 ;
  assign { mul1_mul_op__insn, mul1_mul_op__is_signed, mul1_mul_op__is_32bit, mul1_mul_op__write_cr0, mul1_mul_op__oe__ok, mul1_mul_op__oe__oe, mul1_mul_op__rc__ok, mul1_mul_op__rc__rc, mul1_mul_op__imm_data__ok, mul1_mul_op__imm_data__data, mul1_mul_op__fn_unit, mul1_mul_op__insn_type } = { \input_mul_op__insn$29 , \input_mul_op__is_signed$28 , \input_mul_op__is_32bit$27 , \input_mul_op__write_cr0$26 , \input_mul_op__oe__ok$25 , \input_mul_op__oe__oe$24 , \input_mul_op__rc__ok$23 , \input_mul_op__rc__rc$22 , \input_mul_op__imm_data__ok$21 , \input_mul_op__imm_data__data$20 , \input_mul_op__fn_unit$19 , \input_mul_op__insn_type$18  };
  assign mul1_muxid = \input_muxid$17 ;
  assign input_xer_so = \xer_so$16 ;
  assign input_rb = \rb$15 ;
  assign input_ra = \ra$14 ;
  assign { input_mul_op__insn, input_mul_op__is_signed, input_mul_op__is_32bit, input_mul_op__write_cr0, input_mul_op__oe__ok, input_mul_op__oe__oe, input_mul_op__rc__ok, input_mul_op__rc__rc, input_mul_op__imm_data__ok, input_mul_op__imm_data__data, input_mul_op__fn_unit, input_mul_op__insn_type } = { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  };
  assign input_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:155472.1-156392.10" *)
module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, ra, rb, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , o, \xer_so$14 , \neg_res$15 , \neg_res32$16 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:155473.7-155473.20" *)
  reg _00_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [13:0] _01_;
  (* src = "libresoc.v:156184.3-156185.53" *)
  reg [13:0] _02_;
  (* src = "libresoc.v:155764.14-155764.44" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:156186.3-156187.67" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:155790.14-155790.63" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _07_;
  (* src = "libresoc.v:156188.3-156189.63" *)
  reg _08_;
  (* src = "libresoc.v:155799.7-155799.38" *)
  reg _09_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [31:0] _10_;
  (* src = "libresoc.v:156204.3-156205.49" *)
  reg [31:0] _11_;
  (* src = "libresoc.v:155806.14-155806.39" *)
  reg [31:0] _12_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:156182.3-156183.57" *)
  reg [6:0] _14_;
  (* src = "libresoc.v:155965.13-155965.42" *)
  reg [6:0] _15_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _16_;
  (* src = "libresoc.v:156200.3-156201.57" *)
  reg _17_;
  (* src = "libresoc.v:156049.7-156049.35" *)
  reg _18_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _19_;
  (* src = "libresoc.v:156202.3-156203.59" *)
  reg _20_;
  (* src = "libresoc.v:156058.7-156058.36" *)
  reg _21_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _22_;
  (* src = "libresoc.v:156194.3-156195.51" *)
  reg _23_;
  (* src = "libresoc.v:156069.7-156069.32" *)
  reg _24_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _25_;
  (* src = "libresoc.v:156196.3-156197.51" *)
  reg _26_;
  (* src = "libresoc.v:156078.7-156078.32" *)
  reg _27_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _28_;
  (* src = "libresoc.v:156192.3-156193.51" *)
  reg _29_;
  (* src = "libresoc.v:156087.7-156087.32" *)
  reg _30_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _31_;
  (* src = "libresoc.v:156190.3-156191.51" *)
  reg _32_;
  (* src = "libresoc.v:156096.7-156096.32" *)
  reg _33_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _34_;
  (* src = "libresoc.v:156198.3-156199.59" *)
  reg _35_;
  (* src = "libresoc.v:156103.7-156103.36" *)
  reg _36_;
  (* src = "libresoc.v:156273.3-156285.6" *)
  reg [1:0] _37_;
  (* src = "libresoc.v:156206.3-156207.33" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:156112.13-156112.29" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:156348.3-156360.6" *)
  reg _40_;
  (* src = "libresoc.v:156176.3-156177.39" *)
  reg _41_;
  (* src = "libresoc.v:156127.7-156127.26" *)
  reg _42_;
  (* src = "libresoc.v:156361.3-156373.6" *)
  reg _43_;
  (* src = "libresoc.v:156174.3-156175.43" *)
  reg _44_;
  (* src = "libresoc.v:156136.7-156136.28" *)
  reg _45_;
  (* src = "libresoc.v:156322.3-156334.6" *)
  reg [128:0] _46_;
  (* src = "libresoc.v:156180.3-156181.19" *)
  reg [128:0] _47_;
  (* src = "libresoc.v:156255.3-156272.6" *)
  reg _48_;
  (* src = "libresoc.v:156208.3-156209.29" *)
  reg _49_;
  (* src = "libresoc.v:156335.3-156347.6" *)
  reg _50_;
  (* src = "libresoc.v:156178.3-156179.37" *)
  reg _51_;
  (* src = "libresoc.v:156168.7-156168.25" *)
  reg _52_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [13:0] _53_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [63:0] _54_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _55_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [31:0] _56_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [6:0] _57_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _58_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _59_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _60_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _61_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _62_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _63_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _64_;
  (* src = "libresoc.v:156273.3-156285.6" *)
  reg [1:0] _65_;
  (* src = "libresoc.v:156348.3-156360.6" *)
  reg _66_;
  (* src = "libresoc.v:156361.3-156373.6" *)
  reg _67_;
  (* src = "libresoc.v:156322.3-156334.6" *)
  reg [128:0] _68_;
  (* src = "libresoc.v:156143.15-156143.57" *)
  reg [128:0] _69_;
  (* src = "libresoc.v:156255.3-156272.6" *)
  reg _70_;
  (* src = "libresoc.v:156157.7-156157.20" *)
  reg _71_;
  (* src = "libresoc.v:156335.3-156347.6" *)
  reg _72_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg [63:0] _73_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _74_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _75_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _76_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _77_;
  (* src = "libresoc.v:156286.3-156321.6" *)
  reg _78_;
  (* src = "libresoc.v:156255.3-156272.6" *)
  reg _79_;
  (* src = "libresoc.v:156173.18-156173.118" *)
  wire _80_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:155473.7-155473.15" *)
  reg \initial ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul2_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul2_mul_op__fn_unit$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul2_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul2_mul_op__imm_data__data$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__imm_data__ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul2_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul2_mul_op__insn$29 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul2_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul2_mul_op__insn_type$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__is_32bit$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__is_signed$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__oe__oe$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__oe__ok$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__rc__ok$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__rc__rc$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul2_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul2_mul_op__write_cr0$26 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul2_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul2_muxid$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  wire mul2_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  wire \mul2_neg_res$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  wire mul2_neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  wire \mul2_neg_res32$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [128:0] mul2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul2_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] mul2_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul2_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \mul2_xer_so$30 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  reg [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \mul_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_op__fn_unit$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_op__imm_data__data$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  reg [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \mul_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__imm_data__ok$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  reg \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  reg [31:0] \mul_op__insn$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \mul_op__insn$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_op__insn$48 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  reg [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \mul_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_op__insn_type$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  reg \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_32bit$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_32bit$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  reg \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_signed$12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_signed$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__oe$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  reg \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__ok$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  reg \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__ok$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  reg \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__rc$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  reg \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  reg \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__write_cr0$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__write_cr0$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$36 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" *)
  input neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  output \neg_res$15 ;
  reg \neg_res$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  reg \neg_res$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  wire \neg_res$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" *)
  input neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  output \neg_res32$16 ;
  reg \neg_res32$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  reg \neg_res32$16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  wire \neg_res32$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [128:0] o;
  reg [128:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [128:0] \o$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [128:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$33 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$14 ;
  reg \xer_so$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg \xer_so$14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \xer_so$50 ;
  assign _80_ = \p_valid_i$33  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:156210.8-156246.4" *)
  mul2 mul2 (
    .mul_op__fn_unit(mul2_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul2_mul_op__fn_unit$19 ),
    .mul_op__imm_data__data(mul2_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul2_mul_op__imm_data__data$20 ),
    .mul_op__imm_data__ok(mul2_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul2_mul_op__imm_data__ok$21 ),
    .mul_op__insn(mul2_mul_op__insn),
    .\mul_op__insn$13 (\mul2_mul_op__insn$29 ),
    .mul_op__insn_type(mul2_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul2_mul_op__insn_type$18 ),
    .mul_op__is_32bit(mul2_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul2_mul_op__is_32bit$27 ),
    .mul_op__is_signed(mul2_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul2_mul_op__is_signed$28 ),
    .mul_op__oe__oe(mul2_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul2_mul_op__oe__oe$24 ),
    .mul_op__oe__ok(mul2_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul2_mul_op__oe__ok$25 ),
    .mul_op__rc__ok(mul2_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul2_mul_op__rc__ok$23 ),
    .mul_op__rc__rc(mul2_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul2_mul_op__rc__rc$22 ),
    .mul_op__write_cr0(mul2_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul2_mul_op__write_cr0$26 ),
    .muxid(mul2_muxid),
    .\muxid$1 (\mul2_muxid$17 ),
    .neg_res(mul2_neg_res),
    .\neg_res$15 (\mul2_neg_res$31 ),
    .neg_res32(mul2_neg_res32),
    .\neg_res32$16 (\mul2_neg_res32$32 ),
    .o(mul2_o),
    .ra(mul2_ra),
    .rb(mul2_rb),
    .xer_so(mul2_xer_so),
    .\xer_so$14 (\mul2_xer_so$30 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:156247.10-156250.4" *)
  \n$97  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:156251.10-156254.4" *)
  \p$96  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \mul_op__fn_unit$3  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \mul_op__imm_data__data$4  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__imm_data__ok$5  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \mul_op__insn$13  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \mul_op__insn_type$2  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__is_32bit$11  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__is_signed$12  <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__oe__oe$8  <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__oe__ok$9  <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__rc__ok$7  <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__rc__rc$6  <= _33_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__write_cr0$10  <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _39_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _39_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \neg_res$15  <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _45_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \neg_res32$16  <= _45_;
  end
  always @* begin
    if (\initial ) begin end
    _69_ = 129'h000000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _69_;
  end
  always @* begin
    if (\initial ) begin end
    _71_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _71_;
  end
  always @* begin
    if (\initial ) begin end
    _52_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$14  <= _52_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = \neg_res32$16$next ;
  end
  always @(posedge coresync_clk) begin
      \neg_res32$16  <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _41_ = \neg_res$15$next ;
  end
  always @(posedge coresync_clk) begin
      \neg_res$15  <= _41_;
  end
  always @* begin
    if (\initial ) begin end
    _51_ = \xer_so$14$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$14  <= _51_;
  end
  always @* begin
    if (\initial ) begin end
    _47_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _47_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = \mul_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__insn_type$2  <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \mul_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__fn_unit$3  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = \mul_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__imm_data__data$4  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \mul_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__imm_data__ok$5  <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = \mul_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__rc__rc$6  <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = \mul_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__rc__ok$7  <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = \mul_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__oe__oe$8  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = \mul_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__oe__ok$9  <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _35_ = \mul_op__write_cr0$10$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__write_cr0$10  <= _35_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = \mul_op__is_32bit$11$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__is_32bit$11  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = \mul_op__is_signed$12$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__is_signed$12  <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = \mul_op__insn$13$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__insn$13  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _49_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _49_;
  end
  always @* begin
    if (\initial ) begin end
    _48_ = _79_;
    (* src = "libresoc.v:156256.5-156256.29" *)
    casez (\initial )
      /* src = "libresoc.v:156256.9-156256.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _70_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _70_ = 1'h0;
        end
      default:
          _70_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _79_ = 1'h0;
        end
      default:
          _79_ = _70_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _48_;
  end
  always @* begin
    if (\initial ) begin end
    _37_ = _65_;
    (* src = "libresoc.v:156274.5-156274.29" *)
    casez (\initial )
      /* src = "libresoc.v:156274.9-156274.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _65_ = \muxid$36 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _65_ = \muxid$36 ;
        end
      default:
          _65_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _37_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _53_;
    _10_ = _56_;
    _13_ = _57_;
    _16_ = _58_;
    _19_ = _59_;
    _34_ = _64_;
    _04_ = _73_;
    _07_ = _74_;
    _22_ = _75_;
    _25_ = _76_;
    _28_ = _77_;
    _31_ = _78_;
    (* src = "libresoc.v:156287.5-156287.29" *)
    casez (\initial )
      /* src = "libresoc.v:156287.9-156287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _56_, _59_, _58_, _64_, _61_, _60_, _62_, _63_, _55_, _54_, _53_, _57_ } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _56_, _59_, _58_, _64_, _61_, _60_, _62_, _63_, _55_, _54_, _53_, _57_ } = { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37  };
        end
      default:
        begin
          _53_ = \mul_op__fn_unit$3 ;
          _54_ = \mul_op__imm_data__data$4 ;
          _55_ = \mul_op__imm_data__ok$5 ;
          _56_ = \mul_op__insn$13 ;
          _57_ = \mul_op__insn_type$2 ;
          _58_ = \mul_op__is_32bit$11 ;
          _59_ = \mul_op__is_signed$12 ;
          _60_ = \mul_op__oe__oe$8 ;
          _61_ = \mul_op__oe__ok$9 ;
          _62_ = \mul_op__rc__ok$7 ;
          _63_ = \mul_op__rc__rc$6 ;
          _64_ = \mul_op__write_cr0$10 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 64'h0000000000000000;
          _74_ = 1'h0;
          _78_ = 1'h0;
          _77_ = 1'h0;
          _75_ = 1'h0;
          _76_ = 1'h0;
        end
      default:
        begin
          _73_ = _54_;
          _74_ = _55_;
          _75_ = _60_;
          _76_ = _61_;
          _77_ = _62_;
          _78_ = _63_;
        end
    endcase
  end
  always @* begin
      \mul_op__fn_unit$3$next  <= _01_;
      \mul_op__imm_data__data$4$next  <= _04_;
      \mul_op__imm_data__ok$5$next  <= _07_;
      \mul_op__insn$13$next  <= _10_;
      \mul_op__insn_type$2$next  <= _13_;
      \mul_op__is_32bit$11$next  <= _16_;
      \mul_op__is_signed$12$next  <= _19_;
      \mul_op__oe__oe$8$next  <= _22_;
      \mul_op__oe__ok$9$next  <= _25_;
      \mul_op__rc__ok$7$next  <= _28_;
      \mul_op__rc__rc$6$next  <= _31_;
      \mul_op__write_cr0$10$next  <= _34_;
  end
  always @* begin
    if (\initial ) begin end
    _46_ = _68_;
    (* src = "libresoc.v:156323.5-156323.29" *)
    casez (\initial )
      /* src = "libresoc.v:156323.9-156323.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _68_ = \o$49 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _68_ = \o$49 ;
        end
      default:
          _68_ = o;
    endcase
  end
  always @* begin
      \o$next  <= _46_;
  end
  always @* begin
    if (\initial ) begin end
    _50_ = _72_;
    (* src = "libresoc.v:156336.5-156336.29" *)
    casez (\initial )
      /* src = "libresoc.v:156336.9-156336.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _72_ = \xer_so$50 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _72_ = \xer_so$50 ;
        end
      default:
          _72_ = \xer_so$14 ;
    endcase
  end
  always @* begin
      \xer_so$14$next  <= _50_;
  end
  always @* begin
    if (\initial ) begin end
    _40_ = _66_;
    (* src = "libresoc.v:156349.5-156349.29" *)
    casez (\initial )
      /* src = "libresoc.v:156349.9-156349.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _66_ = \neg_res$51 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _66_ = \neg_res$51 ;
        end
      default:
          _66_ = \neg_res$15 ;
    endcase
  end
  always @* begin
      \neg_res$15$next  <= _40_;
  end
  always @* begin
    if (\initial ) begin end
    _43_ = _67_;
    (* src = "libresoc.v:156362.5-156362.29" *)
    casez (\initial )
      /* src = "libresoc.v:156362.9-156362.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _67_ = \neg_res32$52 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _67_ = \neg_res32$52 ;
        end
      default:
          _67_ = \neg_res32$16 ;
    endcase
  end
  always @* begin
      \neg_res32$16$next  <= _43_;
  end
  assign \$34  = _80_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign \neg_res32$52  = \mul2_neg_res32$32 ;
  assign \neg_res$51  = \mul2_neg_res$31 ;
  assign \xer_so$50  = \mul2_xer_so$30 ;
  assign \o$49  = mul2_o;
  assign { \mul_op__insn$48 , \mul_op__is_signed$47 , \mul_op__is_32bit$46 , \mul_op__write_cr0$45 , \mul_op__oe__ok$44 , \mul_op__oe__oe$43 , \mul_op__rc__ok$42 , \mul_op__rc__rc$41 , \mul_op__imm_data__ok$40 , \mul_op__imm_data__data$39 , \mul_op__fn_unit$38 , \mul_op__insn_type$37  } = { \mul2_mul_op__insn$29 , \mul2_mul_op__is_signed$28 , \mul2_mul_op__is_32bit$27 , \mul2_mul_op__write_cr0$26 , \mul2_mul_op__oe__ok$25 , \mul2_mul_op__oe__oe$24 , \mul2_mul_op__rc__ok$23 , \mul2_mul_op__rc__rc$22 , \mul2_mul_op__imm_data__ok$21 , \mul2_mul_op__imm_data__data$20 , \mul2_mul_op__fn_unit$19 , \mul2_mul_op__insn_type$18  };
  assign \muxid$36  = \mul2_muxid$17 ;
  assign p_valid_i_p_ready_o = \$34 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$33  = p_valid_i;
  assign mul2_neg_res32 = neg_res32;
  assign mul2_neg_res = neg_res;
  assign mul2_xer_so = xer_so;
  assign mul2_rb = rb;
  assign mul2_ra = ra;
  assign { mul2_mul_op__insn, mul2_mul_op__is_signed, mul2_mul_op__is_32bit, mul2_mul_op__write_cr0, mul2_mul_op__oe__ok, mul2_mul_op__oe__oe, mul2_mul_op__rc__ok, mul2_mul_op__rc__rc, mul2_mul_op__imm_data__ok, mul2_mul_op__imm_data__data, mul2_mul_op__fn_unit, mul2_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign mul2_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:156396.1-157692.10" *)
module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, xer_so, neg_res, neg_res32, n_valid_o, n_ready_i, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$15 , xer_so_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:157610.3-157628.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:157402.3-157403.25" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:157610.3-157628.6" *)
  reg _002_;
  (* src = "libresoc.v:157404.3-157405.31" *)
  reg _003_;
  (* src = "libresoc.v:156397.7-156397.20" *)
  reg _004_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [13:0] _005_;
  (* src = "libresoc.v:157412.3-157413.53" *)
  reg [13:0] _006_;
  (* src = "libresoc.v:156708.14-156708.44" *)
  reg [13:0] _007_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:157414.3-157415.67" *)
  reg [63:0] _009_;
  (* src = "libresoc.v:156732.14-156732.63" *)
  reg [63:0] _010_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _011_;
  (* src = "libresoc.v:157416.3-157417.63" *)
  reg _012_;
  (* src = "libresoc.v:156741.7-156741.38" *)
  reg _013_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [31:0] _014_;
  (* src = "libresoc.v:157432.3-157433.49" *)
  reg [31:0] _015_;
  (* src = "libresoc.v:156750.14-156750.39" *)
  reg [31:0] _016_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [6:0] _017_;
  (* src = "libresoc.v:157410.3-157411.57" *)
  reg [6:0] _018_;
  (* src = "libresoc.v:156909.13-156909.42" *)
  reg [6:0] _019_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _020_;
  (* src = "libresoc.v:157428.3-157429.57" *)
  reg _021_;
  (* src = "libresoc.v:156993.7-156993.35" *)
  reg _022_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _023_;
  (* src = "libresoc.v:157430.3-157431.59" *)
  reg _024_;
  (* src = "libresoc.v:157002.7-157002.36" *)
  reg _025_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _026_;
  (* src = "libresoc.v:157422.3-157423.51" *)
  reg _027_;
  (* src = "libresoc.v:157013.7-157013.32" *)
  reg _028_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _029_;
  (* src = "libresoc.v:157424.3-157425.51" *)
  reg _030_;
  (* src = "libresoc.v:157022.7-157022.32" *)
  reg _031_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _032_;
  (* src = "libresoc.v:157420.3-157421.51" *)
  reg _033_;
  (* src = "libresoc.v:157031.7-157031.32" *)
  reg _034_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _035_;
  (* src = "libresoc.v:157418.3-157419.51" *)
  reg _036_;
  (* src = "libresoc.v:157038.7-157038.32" *)
  reg _037_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _038_;
  (* src = "libresoc.v:157426.3-157427.59" *)
  reg _039_;
  (* src = "libresoc.v:157047.7-157047.36" *)
  reg _040_;
  (* src = "libresoc.v:157542.3-157554.6" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:157434.3-157435.33" *)
  reg [1:0] _042_;
  (* src = "libresoc.v:157056.13-157056.29" *)
  reg [1:0] _043_;
  (* src = "libresoc.v:157591.3-157609.6" *)
  reg [63:0] _044_;
  (* src = "libresoc.v:157406.3-157407.27" *)
  reg [63:0] _045_;
  (* src = "libresoc.v:157077.14-157077.43" *)
  reg [63:0] _046_;
  (* src = "libresoc.v:157591.3-157609.6" *)
  reg _047_;
  (* src = "libresoc.v:157408.3-157409.25" *)
  reg _048_;
  (* src = "libresoc.v:157524.3-157541.6" *)
  reg _049_;
  (* src = "libresoc.v:157436.3-157437.29" *)
  reg _050_;
  (* src = "libresoc.v:157629.3-157647.6" *)
  reg [1:0] _051_;
  (* src = "libresoc.v:157398.3-157399.29" *)
  reg [1:0] _052_;
  (* src = "libresoc.v:157629.3-157647.6" *)
  reg _053_;
  (* src = "libresoc.v:157400.3-157401.35" *)
  reg _054_;
  (* src = "libresoc.v:157648.3-157666.6" *)
  reg _055_;
  (* src = "libresoc.v:157394.3-157395.37" *)
  reg _056_;
  (* src = "libresoc.v:157379.7-157379.25" *)
  reg _057_;
  (* src = "libresoc.v:157648.3-157666.6" *)
  reg _058_;
  (* src = "libresoc.v:157396.3-157397.35" *)
  reg _059_;
  (* src = "libresoc.v:157610.3-157628.6" *)
  reg [3:0] _060_;
  (* src = "libresoc.v:156406.13-156406.24" *)
  reg [3:0] _061_;
  (* src = "libresoc.v:157610.3-157628.6" *)
  reg _062_;
  (* src = "libresoc.v:156415.7-156415.21" *)
  reg _063_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [13:0] _064_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [63:0] _065_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _066_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [31:0] _067_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [6:0] _068_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _069_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _070_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _071_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _072_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _073_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _074_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _075_;
  (* src = "libresoc.v:157542.3-157554.6" *)
  reg [1:0] _076_;
  (* src = "libresoc.v:157591.3-157609.6" *)
  reg [63:0] _077_;
  (* src = "libresoc.v:157591.3-157609.6" *)
  reg _078_;
  (* src = "libresoc.v:157084.7-157084.18" *)
  reg _079_;
  (* src = "libresoc.v:157524.3-157541.6" *)
  reg _080_;
  (* src = "libresoc.v:157356.7-157356.20" *)
  reg _081_;
  (* src = "libresoc.v:157629.3-157647.6" *)
  reg [1:0] _082_;
  (* src = "libresoc.v:157361.13-157361.26" *)
  reg [1:0] _083_;
  (* src = "libresoc.v:157629.3-157647.6" *)
  reg _084_;
  (* src = "libresoc.v:157368.7-157368.23" *)
  reg _085_;
  (* src = "libresoc.v:157648.3-157666.6" *)
  reg _086_;
  (* src = "libresoc.v:157648.3-157666.6" *)
  reg _087_;
  (* src = "libresoc.v:157386.7-157386.23" *)
  reg _088_;
  (* src = "libresoc.v:157610.3-157628.6" *)
  reg _089_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg [63:0] _090_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _091_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _092_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _093_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _094_;
  (* src = "libresoc.v:157555.3-157590.6" *)
  reg _095_;
  (* src = "libresoc.v:157591.3-157609.6" *)
  reg _096_;
  (* src = "libresoc.v:157524.3-157541.6" *)
  reg _097_;
  (* src = "libresoc.v:157629.3-157647.6" *)
  reg _098_;
  (* src = "libresoc.v:157648.3-157666.6" *)
  reg _099_;
  (* src = "libresoc.v:157393.18-157393.118" *)
  wire _100_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "libresoc.v:156397.7-156397.15" *)
  reg \initial ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] mul3_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul3_mul_op__fn_unit$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] mul3_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul3_mul_op__imm_data__data$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__imm_data__ok$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] mul3_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul3_mul_op__insn$28 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] mul3_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul3_mul_op__insn_type$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__is_32bit$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__is_signed$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__oe__oe$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__oe__ok$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__rc__ok$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__rc__rc$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire mul3_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul3_mul_op__write_cr0$25 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] mul3_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \mul3_muxid$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  wire mul3_neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [128:0] mul3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \mul3_o$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul3_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] mul3_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul3_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire mul3_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \mul3_xer_so$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire mul3_xer_so_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  reg [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \mul_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \mul_op__fn_unit$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  reg [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \mul_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \mul_op__imm_data__data$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  reg \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__imm_data__ok$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  reg [31:0] \mul_op__insn$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \mul_op__insn$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \mul_op__insn$70 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  reg [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \mul_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \mul_op__insn_type$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  reg \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_32bit$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_32bit$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  reg \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__is_signed$12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__is_signed$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__oe$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  reg \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__oe__ok$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  reg \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__ok$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  reg \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  reg \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__rc__rc$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  reg \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \mul_op__write_cr0$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \mul_op__write_cr0$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$58 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" *)
  input neg_res;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  input neg_res32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" *)
  wire \neg_res32$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [128:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$14 ;
  reg [63:0] \o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] output_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \output_cr_a$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_cr_a_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_mul_op__fn_unit$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_mul_op__imm_data__data$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__imm_data__ok$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_mul_op__insn$43 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_mul_op__insn_type$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__is_32bit$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__is_signed$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__oe__oe$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__oe__ok$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__rc__ok$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__rc__rc$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_mul_op__write_cr0$40 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_muxid$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \output_o$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_o_ok$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \output_xer_ov$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_xer_so$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  reg [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ov$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$15 ;
  reg \xer_so$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _100_ = \p_valid_i$55  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:157438.8-157474.4" *)
  mul3 mul3 (
    .mul_op__fn_unit(mul3_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\mul3_mul_op__fn_unit$18 ),
    .mul_op__imm_data__data(mul3_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\mul3_mul_op__imm_data__data$19 ),
    .mul_op__imm_data__ok(mul3_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\mul3_mul_op__imm_data__ok$20 ),
    .mul_op__insn(mul3_mul_op__insn),
    .\mul_op__insn$13 (\mul3_mul_op__insn$28 ),
    .mul_op__insn_type(mul3_mul_op__insn_type),
    .\mul_op__insn_type$2 (\mul3_mul_op__insn_type$17 ),
    .mul_op__is_32bit(mul3_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\mul3_mul_op__is_32bit$26 ),
    .mul_op__is_signed(mul3_mul_op__is_signed),
    .\mul_op__is_signed$12 (\mul3_mul_op__is_signed$27 ),
    .mul_op__oe__oe(mul3_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\mul3_mul_op__oe__oe$23 ),
    .mul_op__oe__ok(mul3_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\mul3_mul_op__oe__ok$24 ),
    .mul_op__rc__ok(mul3_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\mul3_mul_op__rc__ok$22 ),
    .mul_op__rc__rc(mul3_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\mul3_mul_op__rc__rc$21 ),
    .mul_op__write_cr0(mul3_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\mul3_mul_op__write_cr0$25 ),
    .muxid(mul3_muxid),
    .\muxid$1 (\mul3_muxid$16 ),
    .neg_res(mul3_neg_res),
    .o(mul3_o),
    .\o$14 (\mul3_o$29 ),
    .o_ok(mul3_o_ok),
    .xer_ov(mul3_xer_ov),
    .xer_ov_ok(mul3_xer_ov_ok),
    .xer_so(mul3_xer_so),
    .\xer_so$15 (\mul3_xer_so$30 ),
    .xer_so_ok(mul3_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:157475.10-157478.4" *)
  \n$99  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:157479.16-157519.4" *)
  \output$100  \output  (
    .cr_a(output_cr_a),
    .\cr_a$16 (\output_cr_a$46 ),
    .cr_a_ok(output_cr_a_ok),
    .mul_op__fn_unit(output_mul_op__fn_unit),
    .\mul_op__fn_unit$3 (\output_mul_op__fn_unit$33 ),
    .mul_op__imm_data__data(output_mul_op__imm_data__data),
    .\mul_op__imm_data__data$4 (\output_mul_op__imm_data__data$34 ),
    .mul_op__imm_data__ok(output_mul_op__imm_data__ok),
    .\mul_op__imm_data__ok$5 (\output_mul_op__imm_data__ok$35 ),
    .mul_op__insn(output_mul_op__insn),
    .\mul_op__insn$13 (\output_mul_op__insn$43 ),
    .mul_op__insn_type(output_mul_op__insn_type),
    .\mul_op__insn_type$2 (\output_mul_op__insn_type$32 ),
    .mul_op__is_32bit(output_mul_op__is_32bit),
    .\mul_op__is_32bit$11 (\output_mul_op__is_32bit$41 ),
    .mul_op__is_signed(output_mul_op__is_signed),
    .\mul_op__is_signed$12 (\output_mul_op__is_signed$42 ),
    .mul_op__oe__oe(output_mul_op__oe__oe),
    .\mul_op__oe__oe$8 (\output_mul_op__oe__oe$38 ),
    .mul_op__oe__ok(output_mul_op__oe__ok),
    .\mul_op__oe__ok$9 (\output_mul_op__oe__ok$39 ),
    .mul_op__rc__ok(output_mul_op__rc__ok),
    .\mul_op__rc__ok$7 (\output_mul_op__rc__ok$37 ),
    .mul_op__rc__rc(output_mul_op__rc__rc),
    .\mul_op__rc__rc$6 (\output_mul_op__rc__rc$36 ),
    .mul_op__write_cr0(output_mul_op__write_cr0),
    .\mul_op__write_cr0$10 (\output_mul_op__write_cr0$40 ),
    .muxid(output_muxid),
    .\muxid$1 (\output_muxid$31 ),
    .o(output_o),
    .\o$14 (\output_o$44 ),
    .o_ok(output_o_ok),
    .\o_ok$15 (\output_o_ok$45 ),
    .xer_ov(output_xer_ov),
    .\xer_ov$17 (\output_xer_ov$47 ),
    .xer_ov_ok(output_xer_ov_ok),
    .xer_so(output_xer_so),
    .\xer_so$18 (\output_xer_so$48 ),
    .xer_so_ok(output_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:157520.10-157523.4" *)
  \p$98  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _004_ = 1'h0;
  end
  always @* begin
      \initial  <= _004_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _061_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      cr_a <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \mul_op__fn_unit$3  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \mul_op__imm_data__data$4  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__imm_data__ok$5  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \mul_op__insn$13  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \mul_op__insn_type$2  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__is_32bit$11  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__is_signed$12  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__oe__oe$8  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__oe__ok$9  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__rc__ok$7  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__rc__rc$6  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \mul_op__write_cr0$10  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \o$14  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov_ok <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$15  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \xer_so$15$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$15  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov_ok <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \o$14$next ;
  end
  always @(posedge coresync_clk) begin
      \o$14  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \mul_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__insn_type$2  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \mul_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__fn_unit$3  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \mul_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__imm_data__data$4  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \mul_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__imm_data__ok$5  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \mul_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__rc__rc$6  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \mul_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__rc__ok$7  <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \mul_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__oe__oe$8  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \mul_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__oe__ok$9  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \mul_op__write_cr0$10$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__write_cr0$10  <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \mul_op__is_32bit$11$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__is_32bit$11  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \mul_op__is_signed$12$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__is_signed$12  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \mul_op__insn$13$next ;
  end
  always @(posedge coresync_clk) begin
      \mul_op__insn$13  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _097_;
    (* src = "libresoc.v:157525.5-157525.29" *)
    casez (\initial )
      /* src = "libresoc.v:157525.9-157525.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _080_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _080_ = 1'h0;
        end
      default:
          _080_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = 1'h0;
        end
      default:
          _097_ = _080_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _076_;
    (* src = "libresoc.v:157543.5-157543.29" *)
    casez (\initial )
      /* src = "libresoc.v:157543.9-157543.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _076_ = \muxid$58 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _076_ = \muxid$58 ;
        end
      default:
          _076_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _064_;
    _014_ = _067_;
    _017_ = _068_;
    _020_ = _069_;
    _023_ = _070_;
    _038_ = _075_;
    _008_ = _090_;
    _011_ = _091_;
    _026_ = _092_;
    _029_ = _093_;
    _032_ = _094_;
    _035_ = _095_;
    (* src = "libresoc.v:157556.5-157556.29" *)
    casez (\initial )
      /* src = "libresoc.v:157556.9-157556.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _067_, _070_, _069_, _075_, _072_, _071_, _073_, _074_, _066_, _065_, _064_, _068_ } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _067_, _070_, _069_, _075_, _072_, _071_, _073_, _074_, _066_, _065_, _064_, _068_ } = { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59  };
        end
      default:
        begin
          _064_ = \mul_op__fn_unit$3 ;
          _065_ = \mul_op__imm_data__data$4 ;
          _066_ = \mul_op__imm_data__ok$5 ;
          _067_ = \mul_op__insn$13 ;
          _068_ = \mul_op__insn_type$2 ;
          _069_ = \mul_op__is_32bit$11 ;
          _070_ = \mul_op__is_signed$12 ;
          _071_ = \mul_op__oe__oe$8 ;
          _072_ = \mul_op__oe__ok$9 ;
          _073_ = \mul_op__rc__ok$7 ;
          _074_ = \mul_op__rc__rc$6 ;
          _075_ = \mul_op__write_cr0$10 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _090_ = 64'h0000000000000000;
          _091_ = 1'h0;
          _095_ = 1'h0;
          _094_ = 1'h0;
          _092_ = 1'h0;
          _093_ = 1'h0;
        end
      default:
        begin
          _090_ = _065_;
          _091_ = _066_;
          _092_ = _071_;
          _093_ = _072_;
          _094_ = _073_;
          _095_ = _074_;
        end
    endcase
  end
  always @* begin
      \mul_op__fn_unit$3$next  <= _005_;
      \mul_op__imm_data__data$4$next  <= _008_;
      \mul_op__imm_data__ok$5$next  <= _011_;
      \mul_op__insn$13$next  <= _014_;
      \mul_op__insn_type$2$next  <= _017_;
      \mul_op__is_32bit$11$next  <= _020_;
      \mul_op__is_signed$12$next  <= _023_;
      \mul_op__oe__oe$8$next  <= _026_;
      \mul_op__oe__ok$9$next  <= _029_;
      \mul_op__rc__ok$7$next  <= _032_;
      \mul_op__rc__rc$6$next  <= _035_;
      \mul_op__write_cr0$10$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _077_;
    _047_ = _096_;
    (* src = "libresoc.v:157592.5-157592.29" *)
    casez (\initial )
      /* src = "libresoc.v:157592.9-157592.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _078_, _077_ } = { \o_ok$72 , \o$71  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _078_, _077_ } = { \o_ok$72 , \o$71  };
        end
      default:
        begin
          _078_ = o_ok;
          _077_ = \o$14 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _096_ = 1'h0;
        end
      default:
          _096_ = _078_;
    endcase
  end
  always @* begin
      \o_ok$next  <= _047_;
      \o$14$next  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _060_;
    _002_ = _089_;
    (* src = "libresoc.v:157611.5-157611.29" *)
    casez (\initial )
      /* src = "libresoc.v:157611.9-157611.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _062_, _060_ } = { \cr_a_ok$74 , \cr_a$73  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _062_, _060_ } = { \cr_a_ok$74 , \cr_a$73  };
        end
      default:
        begin
          _060_ = cr_a;
          _062_ = cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _089_ = 1'h0;
        end
      default:
          _089_ = _062_;
    endcase
  end
  always @* begin
      \cr_a$next  <= _000_;
      \cr_a_ok$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _082_;
    _053_ = _098_;
    (* src = "libresoc.v:157630.5-157630.29" *)
    casez (\initial )
      /* src = "libresoc.v:157630.9-157630.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _084_, _082_ } = { \xer_ov_ok$76 , \xer_ov$75  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _084_, _082_ } = { \xer_ov_ok$76 , \xer_ov$75  };
        end
      default:
        begin
          _082_ = xer_ov;
          _084_ = xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _098_ = 1'h0;
        end
      default:
          _098_ = _084_;
    endcase
  end
  always @* begin
      \xer_ov$next  <= _051_;
      \xer_ov_ok$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _086_;
    _058_ = _099_;
    (* src = "libresoc.v:157649.5-157649.29" *)
    casez (\initial )
      /* src = "libresoc.v:157649.9-157649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _087_, _086_ } = { \xer_so_ok$78 , \xer_so$77  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _087_, _086_ } = { \xer_so_ok$78 , \xer_so$77  };
        end
      default:
        begin
          _087_ = xer_so_ok;
          _086_ = \xer_so$15 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _099_ = 1'h0;
        end
      default:
          _099_ = _087_;
    endcase
  end
  always @* begin
      \xer_so_ok$next  <= _058_;
      \xer_so$15$next  <= _055_;
  end
  assign \$56  = _100_;
  assign \cr_a$51  = 4'h0;
  assign \cr_a_ok$52  = 1'h0;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_so_ok$78 , \xer_so$77  } = { output_xer_so_ok, \output_xer_so$48  };
  assign { \xer_ov_ok$76 , \xer_ov$75  } = { output_xer_ov_ok, \output_xer_ov$47  };
  assign { \cr_a_ok$74 , \cr_a$73  } = { output_cr_a_ok, \output_cr_a$46  };
  assign { \o_ok$72 , \o$71  } = { \output_o_ok$45 , \output_o$44  };
  assign { \mul_op__insn$70 , \mul_op__is_signed$69 , \mul_op__is_32bit$68 , \mul_op__write_cr0$67 , \mul_op__oe__ok$66 , \mul_op__oe__oe$65 , \mul_op__rc__ok$64 , \mul_op__rc__rc$63 , \mul_op__imm_data__ok$62 , \mul_op__imm_data__data$61 , \mul_op__fn_unit$60 , \mul_op__insn_type$59  } = { \output_mul_op__insn$43 , \output_mul_op__is_signed$42 , \output_mul_op__is_32bit$41 , \output_mul_op__write_cr0$40 , \output_mul_op__oe__ok$39 , \output_mul_op__oe__oe$38 , \output_mul_op__rc__ok$37 , \output_mul_op__rc__rc$36 , \output_mul_op__imm_data__ok$35 , \output_mul_op__imm_data__data$34 , \output_mul_op__fn_unit$33 , \output_mul_op__insn_type$32  };
  assign \muxid$58  = \output_muxid$31 ;
  assign p_valid_i_p_ready_o = \$56 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$55  = p_valid_i;
  assign { \xer_so_ok$54 , output_xer_so } = { mul3_xer_so_ok, \mul3_xer_so$30  };
  assign { \xer_ov_ok$53 , output_xer_ov } = { mul3_xer_ov_ok, mul3_xer_ov };
  assign { \cr_a_ok$50 , output_cr_a } = 5'h00;
  assign { output_o_ok, output_o } = { mul3_o_ok, \mul3_o$29  };
  assign { output_mul_op__insn, output_mul_op__is_signed, output_mul_op__is_32bit, output_mul_op__write_cr0, output_mul_op__oe__ok, output_mul_op__oe__oe, output_mul_op__rc__ok, output_mul_op__rc__rc, output_mul_op__imm_data__ok, output_mul_op__imm_data__data, output_mul_op__fn_unit, output_mul_op__insn_type } = { \mul3_mul_op__insn$28 , \mul3_mul_op__is_signed$27 , \mul3_mul_op__is_32bit$26 , \mul3_mul_op__write_cr0$25 , \mul3_mul_op__oe__ok$24 , \mul3_mul_op__oe__oe$23 , \mul3_mul_op__rc__ok$22 , \mul3_mul_op__rc__rc$21 , \mul3_mul_op__imm_data__ok$20 , \mul3_mul_op__imm_data__data$19 , \mul3_mul_op__fn_unit$18 , \mul3_mul_op__insn_type$17  };
  assign output_muxid = \mul3_muxid$16 ;
  assign \neg_res32$49  = neg_res32;
  assign mul3_neg_res = neg_res;
  assign mul3_xer_so = xer_so;
  assign mul3_o = o;
  assign { mul3_mul_op__insn, mul3_mul_op__is_signed, mul3_mul_op__is_32bit, mul3_mul_op__write_cr0, mul3_mul_op__oe__ok, mul3_mul_op__oe__oe, mul3_mul_op__rc__ok, mul3_mul_op__rc__rc, mul3_mul_op__imm_data__ok, mul3_mul_op__imm_data__data, mul3_mul_op__fn_unit, mul3_mul_op__insn_type } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign mul3_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157696.1-157707.10" *)
module n(n_ready_i, n_valid_o);
  (* src = "libresoc.v:157705.17-157705.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157711.1-157722.10" *)
module \n$109 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157720.17-157720.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157726.1-157737.10" *)
module \n$112 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157735.17-157735.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157741.1-157752.10" *)
module \n$117 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157750.17-157750.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157756.1-157767.10" *)
module \n$18 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157765.17-157765.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157771.1-157782.10" *)
module \n$2 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157780.17-157780.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157786.1-157797.10" *)
module \n$21 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157795.17-157795.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157801.1-157812.10" *)
module \n$31 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157810.17-157810.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157816.1-157827.10" *)
module \n$34 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157825.17-157825.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157831.1-157842.10" *)
module \n$37 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157840.17-157840.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157846.1-157857.10" *)
module \n$4 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157855.17-157855.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157861.1-157872.10" *)
module \n$47 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157870.17-157870.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157876.1-157887.10" *)
module \n$49 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157885.17-157885.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157891.1-157902.10" *)
module \n$53 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157900.17-157900.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157906.1-157917.10" *)
module \n$6 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157915.17-157915.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157921.1-157932.10" *)
module \n$63 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157930.17-157930.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157936.1-157947.10" *)
module \n$66 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157945.17-157945.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157951.1-157962.10" *)
module \n$75 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157960.17-157960.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157966.1-157977.10" *)
module \n$77 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157975.17-157975.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157981.1-157992.10" *)
module \n$8 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:157990.17-157990.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:157996.1-158007.10" *)
module \n$80 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158005.17-158005.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158011.1-158022.10" *)
module \n$82 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158020.17-158020.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158026.1-158037.10" *)
module \n$92 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158035.17-158035.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158041.1-158052.10" *)
module \n$94 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158050.17-158050.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158056.1-158067.10" *)
module \n$97 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158065.17-158065.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158071.1-158082.10" *)
module \n$99 (n_ready_i, n_valid_o);
  (* src = "libresoc.v:158080.17-158080.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  input n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" *)
  wire trigger;
  assign _0_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" *) n_valid_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158086.1-158144.10" *)
module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158087.7-158087.20" *)
  reg _00_;
  (* src = "libresoc.v:158132.3-158140.6" *)
  reg _01_;
  (* src = "libresoc.v:158130.3-158131.27" *)
  reg _02_;
  (* src = "libresoc.v:158132.3-158140.6" *)
  reg _03_;
  (* src = "libresoc.v:158109.7-158109.19" *)
  reg _04_;
  (* src = "libresoc.v:158122.17-158122.96" *)
  wire _05_;
  (* src = "libresoc.v:158127.17-158127.96" *)
  wire _06_;
  (* src = "libresoc.v:158124.18-158124.93" *)
  wire _07_;
  (* src = "libresoc.v:158126.17-158126.92" *)
  wire _08_;
  (* src = "libresoc.v:158129.17-158129.92" *)
  wire _09_;
  (* src = "libresoc.v:158123.18-158123.98" *)
  wire _10_;
  (* src = "libresoc.v:158125.18-158125.99" *)
  wire _11_;
  (* src = "libresoc.v:158128.17-158128.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158087.7-158087.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158133.5-158133.29" *)
    casez (\initial )
      /* src = "libresoc.v:158133.9-158133.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158148.1-158206.10" *)
module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158149.7-158149.20" *)
  reg _00_;
  (* src = "libresoc.v:158194.3-158202.6" *)
  reg _01_;
  (* src = "libresoc.v:158192.3-158193.27" *)
  reg _02_;
  (* src = "libresoc.v:158194.3-158202.6" *)
  reg _03_;
  (* src = "libresoc.v:158171.7-158171.19" *)
  reg _04_;
  (* src = "libresoc.v:158184.17-158184.96" *)
  wire _05_;
  (* src = "libresoc.v:158189.17-158189.96" *)
  wire _06_;
  (* src = "libresoc.v:158186.18-158186.93" *)
  wire _07_;
  (* src = "libresoc.v:158188.17-158188.92" *)
  wire _08_;
  (* src = "libresoc.v:158191.17-158191.92" *)
  wire _09_;
  (* src = "libresoc.v:158185.18-158185.98" *)
  wire _10_;
  (* src = "libresoc.v:158187.18-158187.99" *)
  wire _11_;
  (* src = "libresoc.v:158190.17-158190.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158149.7-158149.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158195.5-158195.29" *)
    casez (\initial )
      /* src = "libresoc.v:158195.9-158195.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158210.1-158268.10" *)
module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158211.7-158211.20" *)
  reg _00_;
  (* src = "libresoc.v:158256.3-158264.6" *)
  reg _01_;
  (* src = "libresoc.v:158254.3-158255.27" *)
  reg _02_;
  (* src = "libresoc.v:158256.3-158264.6" *)
  reg _03_;
  (* src = "libresoc.v:158233.7-158233.19" *)
  reg _04_;
  (* src = "libresoc.v:158246.17-158246.96" *)
  wire _05_;
  (* src = "libresoc.v:158251.17-158251.96" *)
  wire _06_;
  (* src = "libresoc.v:158248.18-158248.93" *)
  wire _07_;
  (* src = "libresoc.v:158250.17-158250.92" *)
  wire _08_;
  (* src = "libresoc.v:158253.17-158253.92" *)
  wire _09_;
  (* src = "libresoc.v:158247.18-158247.98" *)
  wire _10_;
  (* src = "libresoc.v:158249.18-158249.99" *)
  wire _11_;
  (* src = "libresoc.v:158252.17-158252.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158211.7-158211.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158257.5-158257.29" *)
    casez (\initial )
      /* src = "libresoc.v:158257.9-158257.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158272.1-158330.10" *)
module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158273.7-158273.20" *)
  reg _00_;
  (* src = "libresoc.v:158318.3-158326.6" *)
  reg _01_;
  (* src = "libresoc.v:158316.3-158317.27" *)
  reg _02_;
  (* src = "libresoc.v:158318.3-158326.6" *)
  reg _03_;
  (* src = "libresoc.v:158295.7-158295.19" *)
  reg _04_;
  (* src = "libresoc.v:158308.17-158308.96" *)
  wire _05_;
  (* src = "libresoc.v:158313.17-158313.96" *)
  wire _06_;
  (* src = "libresoc.v:158310.18-158310.93" *)
  wire _07_;
  (* src = "libresoc.v:158312.17-158312.92" *)
  wire _08_;
  (* src = "libresoc.v:158315.17-158315.92" *)
  wire _09_;
  (* src = "libresoc.v:158309.18-158309.98" *)
  wire _10_;
  (* src = "libresoc.v:158311.18-158311.99" *)
  wire _11_;
  (* src = "libresoc.v:158314.17-158314.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158273.7-158273.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158319.5-158319.29" *)
    casez (\initial )
      /* src = "libresoc.v:158319.9-158319.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158334.1-158392.10" *)
module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158335.7-158335.20" *)
  reg _00_;
  (* src = "libresoc.v:158380.3-158388.6" *)
  reg _01_;
  (* src = "libresoc.v:158378.3-158379.27" *)
  reg _02_;
  (* src = "libresoc.v:158380.3-158388.6" *)
  reg _03_;
  (* src = "libresoc.v:158357.7-158357.19" *)
  reg _04_;
  (* src = "libresoc.v:158370.17-158370.96" *)
  wire _05_;
  (* src = "libresoc.v:158375.17-158375.96" *)
  wire _06_;
  (* src = "libresoc.v:158372.18-158372.93" *)
  wire _07_;
  (* src = "libresoc.v:158374.17-158374.92" *)
  wire _08_;
  (* src = "libresoc.v:158377.17-158377.92" *)
  wire _09_;
  (* src = "libresoc.v:158371.18-158371.98" *)
  wire _10_;
  (* src = "libresoc.v:158373.18-158373.99" *)
  wire _11_;
  (* src = "libresoc.v:158376.17-158376.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158335.7-158335.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158381.5-158381.29" *)
    casez (\initial )
      /* src = "libresoc.v:158381.9-158381.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158396.1-158454.10" *)
module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158397.7-158397.20" *)
  reg _00_;
  (* src = "libresoc.v:158442.3-158450.6" *)
  reg _01_;
  (* src = "libresoc.v:158440.3-158441.27" *)
  reg _02_;
  (* src = "libresoc.v:158442.3-158450.6" *)
  reg _03_;
  (* src = "libresoc.v:158419.7-158419.19" *)
  reg _04_;
  (* src = "libresoc.v:158432.17-158432.96" *)
  wire _05_;
  (* src = "libresoc.v:158437.17-158437.96" *)
  wire _06_;
  (* src = "libresoc.v:158434.18-158434.93" *)
  wire _07_;
  (* src = "libresoc.v:158436.17-158436.92" *)
  wire _08_;
  (* src = "libresoc.v:158439.17-158439.92" *)
  wire _09_;
  (* src = "libresoc.v:158433.18-158433.98" *)
  wire _10_;
  (* src = "libresoc.v:158435.18-158435.99" *)
  wire _11_;
  (* src = "libresoc.v:158438.17-158438.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158397.7-158397.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158443.5-158443.29" *)
    casez (\initial )
      /* src = "libresoc.v:158443.9-158443.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158458.1-158516.10" *)
module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158459.7-158459.20" *)
  reg _00_;
  (* src = "libresoc.v:158504.3-158512.6" *)
  reg _01_;
  (* src = "libresoc.v:158502.3-158503.27" *)
  reg _02_;
  (* src = "libresoc.v:158504.3-158512.6" *)
  reg _03_;
  (* src = "libresoc.v:158481.7-158481.19" *)
  reg _04_;
  (* src = "libresoc.v:158494.17-158494.96" *)
  wire _05_;
  (* src = "libresoc.v:158499.17-158499.96" *)
  wire _06_;
  (* src = "libresoc.v:158496.18-158496.93" *)
  wire _07_;
  (* src = "libresoc.v:158498.17-158498.92" *)
  wire _08_;
  (* src = "libresoc.v:158501.17-158501.92" *)
  wire _09_;
  (* src = "libresoc.v:158495.18-158495.98" *)
  wire _10_;
  (* src = "libresoc.v:158497.18-158497.99" *)
  wire _11_;
  (* src = "libresoc.v:158500.17-158500.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158459.7-158459.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158505.5-158505.29" *)
    casez (\initial )
      /* src = "libresoc.v:158505.9-158505.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158520.1-158578.10" *)
module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158521.7-158521.20" *)
  reg _00_;
  (* src = "libresoc.v:158566.3-158574.6" *)
  reg _01_;
  (* src = "libresoc.v:158564.3-158565.27" *)
  reg _02_;
  (* src = "libresoc.v:158566.3-158574.6" *)
  reg _03_;
  (* src = "libresoc.v:158543.7-158543.19" *)
  reg _04_;
  (* src = "libresoc.v:158556.17-158556.96" *)
  wire _05_;
  (* src = "libresoc.v:158561.17-158561.96" *)
  wire _06_;
  (* src = "libresoc.v:158558.18-158558.93" *)
  wire _07_;
  (* src = "libresoc.v:158560.17-158560.92" *)
  wire _08_;
  (* src = "libresoc.v:158563.17-158563.92" *)
  wire _09_;
  (* src = "libresoc.v:158557.18-158557.98" *)
  wire _10_;
  (* src = "libresoc.v:158559.18-158559.99" *)
  wire _11_;
  (* src = "libresoc.v:158562.17-158562.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158521.7-158521.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158567.5-158567.29" *)
    casez (\initial )
      /* src = "libresoc.v:158567.9-158567.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158582.1-158640.10" *)
module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158583.7-158583.20" *)
  reg _00_;
  (* src = "libresoc.v:158628.3-158636.6" *)
  reg _01_;
  (* src = "libresoc.v:158626.3-158627.27" *)
  reg _02_;
  (* src = "libresoc.v:158628.3-158636.6" *)
  reg _03_;
  (* src = "libresoc.v:158605.7-158605.19" *)
  reg _04_;
  (* src = "libresoc.v:158618.17-158618.96" *)
  wire _05_;
  (* src = "libresoc.v:158623.17-158623.96" *)
  wire _06_;
  (* src = "libresoc.v:158620.18-158620.93" *)
  wire _07_;
  (* src = "libresoc.v:158622.17-158622.92" *)
  wire _08_;
  (* src = "libresoc.v:158625.17-158625.92" *)
  wire _09_;
  (* src = "libresoc.v:158619.18-158619.98" *)
  wire _10_;
  (* src = "libresoc.v:158621.18-158621.99" *)
  wire _11_;
  (* src = "libresoc.v:158624.17-158624.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158583.7-158583.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158629.5-158629.29" *)
    casez (\initial )
      /* src = "libresoc.v:158629.9-158629.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.opc_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158644.1-158702.10" *)
module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:158645.7-158645.20" *)
  reg _00_;
  (* src = "libresoc.v:158690.3-158698.6" *)
  reg _01_;
  (* src = "libresoc.v:158688.3-158689.27" *)
  reg _02_;
  (* src = "libresoc.v:158690.3-158698.6" *)
  reg _03_;
  (* src = "libresoc.v:158667.7-158667.19" *)
  reg _04_;
  (* src = "libresoc.v:158680.17-158680.96" *)
  wire _05_;
  (* src = "libresoc.v:158685.17-158685.96" *)
  wire _06_;
  (* src = "libresoc.v:158682.18-158682.93" *)
  wire _07_;
  (* src = "libresoc.v:158684.17-158684.92" *)
  wire _08_;
  (* src = "libresoc.v:158687.17-158687.92" *)
  wire _09_;
  (* src = "libresoc.v:158681.18-158681.98" *)
  wire _10_;
  (* src = "libresoc.v:158683.18-158683.99" *)
  wire _11_;
  (* src = "libresoc.v:158686.17-158686.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:158645.7-158645.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_opc;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_opc;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_opc;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_opc;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_opc;
  assign _11_ = q_opc | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_opc;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:158691.5-158691.29" *)
    casez (\initial )
      /* src = "libresoc.v:158691.9-158691.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_opc = \$15 ;
  assign qn_opc = \$13 ;
  assign q_opc = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:158706.1-159164.10" *)
module \output (alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, xer_ca, xer_ov, xer_so, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ca$23 , xer_ca_ok, \xer_ov$24 , xer_ov_ok, \xer_so$25 , xer_so_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:159083.3-159094.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:158707.7-158707.20" *)
  reg _01_;
  (* src = "libresoc.v:159095.3-159106.6" *)
  reg [64:0] _02_;
  (* src = "libresoc.v:159071.3-159082.6" *)
  reg _03_;
  (* src = "libresoc.v:159127.3-159136.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:159137.3-159146.6" *)
  reg _05_;
  (* src = "libresoc.v:159107.3-159116.6" *)
  reg _06_;
  (* src = "libresoc.v:159117.3-159126.6" *)
  reg _07_;
  (* src = "libresoc.v:159083.3-159094.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:159095.3-159106.6" *)
  reg [64:0] _09_;
  (* src = "libresoc.v:159071.3-159082.6" *)
  reg _10_;
  (* src = "libresoc.v:159127.3-159136.6" *)
  reg [1:0] _11_;
  (* src = "libresoc.v:159137.3-159146.6" *)
  reg _12_;
  (* src = "libresoc.v:159107.3-159116.6" *)
  reg _13_;
  (* src = "libresoc.v:159117.3-159126.6" *)
  reg _14_;
  (* src = "libresoc.v:159058.18-159058.128" *)
  wire _15_;
  (* src = "libresoc.v:159066.18-159066.112" *)
  wire _16_;
  (* src = "libresoc.v:159069.18-159069.125" *)
  wire _17_;
  (* src = "libresoc.v:159062.18-159062.123" *)
  wire _18_;
  (* src = "libresoc.v:159063.18-159063.123" *)
  wire _19_;
  (* src = "libresoc.v:159060.18-159060.103" *)
  wire [64:0] _20_;
  (* src = "libresoc.v:159061.18-159061.101" *)
  wire [64:0] _21_;
  (* src = "libresoc.v:159059.18-159059.100" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:159065.18-159065.107" *)
  wire _23_;
  (* src = "libresoc.v:159068.18-159068.107" *)
  wire _24_;
  (* src = "libresoc.v:159067.18-159067.115" *)
  wire _25_;
  (* src = "libresoc.v:159070.18-159070.112" *)
  wire _26_;
  (* src = "libresoc.v:159060.18-159060.103" *)
  wire [64:0] _27_;
  (* src = "libresoc.v:159061.18-159061.101" *)
  wire [64:0] _28_;
  (* src = "libresoc.v:159064.18-159064.105" *)
  wire _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [64:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [63:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [64:0] \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \alu_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \alu_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \alu_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \alu_op__input_carry$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \alu_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \alu_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_out$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__write_cr0$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
  reg [3:0] cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "libresoc.v:158707.7-158707.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *)
  wire is_cmp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *)
  wire is_cmpeqb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *)
  wire is_negative;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *)
  wire is_nzero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *)
  wire is_positive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *)
  wire msb_test;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *)
  reg [64:0] \o$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
  wire oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
  wire \oe$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
  reg so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *)
  wire [63:0] target;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$24 ;
  reg [1:0] \xer_ov$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$25 ;
  reg \xer_so$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  assign _15_ = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) alu_op__oe__ok;
  assign _16_ = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$41 ;
  assign _17_ = alu_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) alu_op__oe__ok;
  assign _18_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a;
  assign _19_ = alu_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$30 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o;
  assign _22_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o;
  assign _23_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test;
  assign _24_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero;
  assign _25_ = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp;
  assign _26_ = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
  assign _27_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) _20_;
  assign _28_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _21_;
  assign _29_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _10_;
    (* src = "libresoc.v:159072.5-159072.29" *)
    casez (\initial )
      /* src = "libresoc.v:159072.9-159072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *)
    casez (oe)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _10_ = \xer_so$25 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _10_ = xer_so;
        end
    endcase
  end
  always @* begin
      so <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _08_;
    (* src = "libresoc.v:159084.5-159084.29" *)
    casez (\initial )
      /* src = "libresoc.v:159084.9-159084.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
    casez (\$45 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _08_ = cr_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _08_ = { is_negative, is_positive, \$47 , so };
        end
    endcase
  end
  always @* begin
      cr0 <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _09_;
    (* src = "libresoc.v:159096.5-159096.29" *)
    casez (\initial )
      /* src = "libresoc.v:159096.9-159096.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *)
    casez (alu_op__invert_out)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _09_ = \$29 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _09_ = \$33 ;
        end
    endcase
  end
  always @* begin
      \o$28  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _13_;
    (* src = "libresoc.v:159108.5-159108.29" *)
    casez (\initial )
      /* src = "libresoc.v:159108.9-159108.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = \$52 ;
        end
      default:
          _13_ = 1'h0;
    endcase
  end
  always @* begin
      \xer_so$25  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _14_;
    (* src = "libresoc.v:159118.5-159118.29" *)
    casez (\initial )
      /* src = "libresoc.v:159118.9-159118.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = 1'h1;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      xer_so_ok <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _11_;
    (* src = "libresoc.v:159128.5-159128.29" *)
    casez (\initial )
      /* src = "libresoc.v:159128.9-159128.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _11_ = xer_ov;
        end
      default:
          _11_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ov$24  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:159138.5-159138.29" *)
    casez (\initial )
      /* src = "libresoc.v:159138.9-159138.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _05_;
  end
  assign \$26  = _15_;
  assign \$30  = _22_;
  assign \$29  = _27_;
  assign \$33  = _28_;
  assign \$35  = _18_;
  assign \$37  = _19_;
  assign \$39  = _29_;
  assign \$41  = _23_;
  assign \$43  = _16_;
  assign \$45  = _25_;
  assign \$47  = _24_;
  assign \$50  = _17_;
  assign \$52  = _26_;
  assign \oe$49  = \$50 ;
  assign { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2  } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
  assign \muxid$1  = muxid;
  assign cr_a_ok = alu_op__write_cr0;
  assign \cr_a$22  = cr0;
  assign \o_ok$21  = o_ok;
  assign \o$20  = \o$28 [63:0];
  assign is_positive = \$43 ;
  assign is_negative = msb_test;
  assign is_nzero = \$39 ;
  assign msb_test = target[63];
  assign is_cmpeqb = \$37 ;
  assign is_cmp = \$35 ;
  assign xer_ca_ok = alu_op__output_carry;
  assign \xer_ca$23  = xer_ca;
  assign target = \o$28 [63:0];
  assign oe = \$26 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:159168.1-159569.10" *)
module \output$100 (mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \mul_op__insn_type$2 , \mul_op__fn_unit$3 , \mul_op__imm_data__data$4 , \mul_op__imm_data__ok$5 , \mul_op__rc__rc$6 , \mul_op__rc__ok$7 , \mul_op__oe__oe$8 , \mul_op__oe__ok$9 , \mul_op__write_cr0$10 , \mul_op__is_32bit$11 , \mul_op__is_signed$12 , \mul_op__insn$13 , \o$14 , \o_ok$15 , \cr_a$16 , cr_a_ok, \xer_ov$17 , xer_ov_ok, \xer_so$18 , xer_so_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:159501.3-159512.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:159169.7-159169.20" *)
  reg _01_;
  (* src = "libresoc.v:159489.3-159500.6" *)
  reg _02_;
  (* src = "libresoc.v:159533.3-159542.6" *)
  reg [1:0] _03_;
  (* src = "libresoc.v:159543.3-159552.6" *)
  reg _04_;
  (* src = "libresoc.v:159513.3-159522.6" *)
  reg _05_;
  (* src = "libresoc.v:159523.3-159532.6" *)
  reg _06_;
  (* src = "libresoc.v:159501.3-159512.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:159489.3-159500.6" *)
  reg _08_;
  (* src = "libresoc.v:159533.3-159542.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:159543.3-159552.6" *)
  reg _10_;
  (* src = "libresoc.v:159513.3-159522.6" *)
  reg _11_;
  (* src = "libresoc.v:159523.3-159532.6" *)
  reg _12_;
  (* src = "libresoc.v:159478.18-159478.128" *)
  wire _13_;
  (* src = "libresoc.v:159484.18-159484.112" *)
  wire _14_;
  (* src = "libresoc.v:159487.18-159487.125" *)
  wire _15_;
  (* src = "libresoc.v:159480.18-159480.123" *)
  wire _16_;
  (* src = "libresoc.v:159481.18-159481.123" *)
  wire _17_;
  (* src = "libresoc.v:159479.18-159479.101" *)
  wire [64:0] _18_;
  (* src = "libresoc.v:159483.18-159483.107" *)
  wire _19_;
  (* src = "libresoc.v:159486.18-159486.107" *)
  wire _20_;
  (* src = "libresoc.v:159485.18-159485.115" *)
  wire _21_;
  (* src = "libresoc.v:159488.18-159488.112" *)
  wire _22_;
  (* src = "libresoc.v:159479.18-159479.101" *)
  wire [64:0] _23_;
  (* src = "libresoc.v:159482.18-159482.105" *)
  wire _24_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [64:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
  reg [3:0] cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "libresoc.v:159169.7-159169.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *)
  wire is_cmp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *)
  wire is_cmpeqb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *)
  wire is_negative;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *)
  wire is_nzero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *)
  wire is_positive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *)
  wire msb_test;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] mul_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \mul_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] mul_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \mul_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] mul_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \mul_op__insn$13 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] mul_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \mul_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_32bit$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__is_signed$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input mul_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \mul_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *)
  wire [64:0] \o$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
  wire oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
  wire \oe$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
  reg so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *)
  wire [63:0] target;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$17 ;
  reg [1:0] \xer_ov$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$18 ;
  reg \xer_so$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  assign _13_ = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) mul_op__oe__ok;
  assign _14_ = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$30 ;
  assign _15_ = mul_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) mul_op__oe__ok;
  assign _16_ = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a;
  assign _17_ = mul_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c;
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o;
  assign _19_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test;
  assign _20_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero;
  assign _21_ = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp;
  assign _22_ = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _18_;
  assign _24_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _08_;
    (* src = "libresoc.v:159490.5-159490.29" *)
    casez (\initial )
      /* src = "libresoc.v:159490.9-159490.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *)
    casez (oe)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _08_ = \xer_so$18 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _08_ = xer_so;
        end
    endcase
  end
  always @* begin
      so <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _07_;
    (* src = "libresoc.v:159502.5-159502.29" *)
    casez (\initial )
      /* src = "libresoc.v:159502.9-159502.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
    casez (\$34 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _07_ = cr_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _07_ = { is_negative, is_positive, \$36 , so };
        end
    endcase
  end
  always @* begin
      cr0 <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _11_;
    (* src = "libresoc.v:159514.5-159514.29" *)
    casez (\initial )
      /* src = "libresoc.v:159514.9-159514.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$38 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _11_ = \$41 ;
        end
      default:
          _11_ = 1'h0;
    endcase
  end
  always @* begin
      \xer_so$18  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _12_;
    (* src = "libresoc.v:159524.5-159524.29" *)
    casez (\initial )
      /* src = "libresoc.v:159524.9-159524.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$38 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      xer_so_ok <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _09_;
    (* src = "libresoc.v:159534.5-159534.29" *)
    casez (\initial )
      /* src = "libresoc.v:159534.9-159534.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$38 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _09_ = xer_ov;
        end
      default:
          _09_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ov$17  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _10_;
    (* src = "libresoc.v:159544.5-159544.29" *)
    casez (\initial )
      /* src = "libresoc.v:159544.9-159544.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$38 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _10_ = 1'h1;
        end
      default:
          _10_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _04_;
  end
  assign \$19  = _13_;
  assign \$22  = _23_;
  assign \$24  = _16_;
  assign \$26  = _17_;
  assign \$28  = _24_;
  assign \$30  = _19_;
  assign \$32  = _14_;
  assign \$34  = _21_;
  assign \$36  = _20_;
  assign \$39  = _15_;
  assign \$41  = _22_;
  assign \oe$38  = \$39 ;
  assign { \mul_op__insn$13 , \mul_op__is_signed$12 , \mul_op__is_32bit$11 , \mul_op__write_cr0$10 , \mul_op__oe__ok$9 , \mul_op__oe__oe$8 , \mul_op__rc__ok$7 , \mul_op__rc__rc$6 , \mul_op__imm_data__ok$5 , \mul_op__imm_data__data$4 , \mul_op__fn_unit$3 , \mul_op__insn_type$2  } = { mul_op__insn, mul_op__is_signed, mul_op__is_32bit, mul_op__write_cr0, mul_op__oe__ok, mul_op__oe__oe, mul_op__rc__ok, mul_op__rc__rc, mul_op__imm_data__ok, mul_op__imm_data__data, mul_op__fn_unit, mul_op__insn_type };
  assign \muxid$1  = muxid;
  assign cr_a_ok = mul_op__write_cr0;
  assign \cr_a$16  = cr0;
  assign \o_ok$15  = o_ok;
  assign \o$14  = \o$21 [63:0];
  assign is_positive = \$32 ;
  assign is_negative = msb_test;
  assign is_nzero = \$28 ;
  assign msb_test = target[63];
  assign is_cmpeqb = \$26 ;
  assign is_cmp = \$24 ;
  assign target = \o$21 [63:0];
  assign \o$21  = \$22 ;
  assign oe = \$19 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:159573.1-159927.10" *)
module \output$118 (sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, xer_so, xer_ca, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , cr_a_ok, \xer_ca$22 , xer_ca_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:159899.3-159910.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:159574.7-159574.20" *)
  reg _01_;
  (* src = "libresoc.v:159899.3-159910.6" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:159896.18-159896.112" *)
  wire _03_;
  (* src = "libresoc.v:159892.18-159892.122" *)
  wire _04_;
  (* src = "libresoc.v:159893.18-159893.122" *)
  wire _05_;
  (* src = "libresoc.v:159891.18-159891.101" *)
  wire [64:0] _06_;
  (* src = "libresoc.v:159895.18-159895.107" *)
  wire _07_;
  (* src = "libresoc.v:159898.18-159898.107" *)
  wire _08_;
  (* src = "libresoc.v:159897.18-159897.115" *)
  wire _09_;
  (* src = "libresoc.v:159891.18-159891.101" *)
  wire [64:0] _10_;
  (* src = "libresoc.v:159894.18-159894.105" *)
  wire _11_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [64:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
  reg [3:0] cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "libresoc.v:159574.7-159574.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *)
  wire is_cmp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *)
  wire is_cmpeqb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *)
  wire is_negative;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *)
  wire is_nzero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *)
  wire is_positive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *)
  wire msb_test;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *)
  wire [64:0] \o$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$20 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \sr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \sr_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \sr_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__input_cr$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \sr_op__insn$18 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \sr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *)
  wire [63:0] target;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  assign _03_ = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$32 ;
  assign _04_ = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a;
  assign _05_ = sr_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c;
  assign _06_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero;
  assign _09_ = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp;
  assign _10_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _06_;
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:159900.5-159900.29" *)
    casez (\initial )
      /* src = "libresoc.v:159900.9-159900.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
    casez (\$36 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _02_ = cr_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _02_ = { is_negative, is_positive, \$38 , xer_so };
        end
    endcase
  end
  always @* begin
      cr0 <= _00_;
  end
  assign \$24  = _10_;
  assign \$26  = _04_;
  assign \$28  = _05_;
  assign \$30  = _11_;
  assign \$32  = _07_;
  assign \$34  = _03_;
  assign \$36  = _09_;
  assign \$38  = _08_;
  assign { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2  } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
  assign \muxid$1  = muxid;
  assign cr_a_ok = sr_op__write_cr0;
  assign \cr_a$21  = cr0;
  assign \o_ok$20  = o_ok;
  assign \o$19  = \o$23 [63:0];
  assign is_positive = \$34 ;
  assign is_negative = msb_test;
  assign is_nzero = \$30 ;
  assign msb_test = target[63];
  assign is_cmpeqb = \$28 ;
  assign is_cmp = \$26 ;
  assign xer_ca_ok = sr_op__output_carry;
  assign \xer_ca$22  = xer_ca;
  assign target = \o$23 [63:0];
  assign \o$23  = \$24 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:159931.1-160298.10" *)
module \output$54 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:160273.3-160284.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:159932.7-159932.20" *)
  reg _01_;
  (* src = "libresoc.v:160261.3-160272.6" *)
  reg [64:0] _02_;
  (* src = "libresoc.v:160273.3-160284.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:160261.3-160272.6" *)
  reg [64:0] _04_;
  (* src = "libresoc.v:160258.18-160258.112" *)
  wire _05_;
  (* src = "libresoc.v:160254.18-160254.127" *)
  wire _06_;
  (* src = "libresoc.v:160255.18-160255.127" *)
  wire _07_;
  (* src = "libresoc.v:160252.18-160252.103" *)
  wire [64:0] _08_;
  (* src = "libresoc.v:160253.18-160253.101" *)
  wire [64:0] _09_;
  (* src = "libresoc.v:160251.18-160251.100" *)
  wire [63:0] _10_;
  (* src = "libresoc.v:160257.18-160257.107" *)
  wire _11_;
  (* src = "libresoc.v:160260.18-160260.107" *)
  wire _12_;
  (* src = "libresoc.v:160259.18-160259.115" *)
  wire _13_;
  (* src = "libresoc.v:160252.18-160252.103" *)
  wire [64:0] _14_;
  (* src = "libresoc.v:160253.18-160253.101" *)
  wire [64:0] _15_;
  (* src = "libresoc.v:160256.18-160256.105" *)
  wire _16_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [64:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [63:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [64:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
  reg [3:0] cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "libresoc.v:159932.7-159932.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *)
  wire is_cmp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *)
  wire is_cmpeqb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *)
  wire is_negative;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *)
  wire is_nzero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *)
  wire is_positive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *)
  wire msb_test;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *)
  reg [64:0] \o$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *)
  wire [63:0] target;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  assign _05_ = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$36 ;
  assign _06_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a;
  assign _07_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c;
  assign _08_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$25 ;
  assign _09_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o;
  assign _10_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o;
  assign _11_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test;
  assign _12_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero;
  assign _13_ = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp;
  assign _14_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) _08_;
  assign _15_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _09_;
  assign _16_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _04_;
    (* src = "libresoc.v:160262.5-160262.29" *)
    casez (\initial )
      /* src = "libresoc.v:160262.9-160262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *)
    casez (logical_op__invert_out)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _04_ = \$24 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = \$28 ;
        end
    endcase
  end
  always @* begin
      \o$23  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _03_;
    (* src = "libresoc.v:160274.5-160274.29" *)
    casez (\initial )
      /* src = "libresoc.v:160274.9-160274.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
    casez (\$40 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = cr_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _03_ = { is_negative, is_positive, \$42 , xer_so };
        end
    endcase
  end
  always @* begin
      cr0 <= _00_;
  end
  assign \$25  = _10_;
  assign \$24  = _14_;
  assign \$28  = _15_;
  assign \$30  = _06_;
  assign \$32  = _07_;
  assign \$34  = _16_;
  assign \$36  = _11_;
  assign \$38  = _05_;
  assign \$40  = _13_;
  assign \$42  = _12_;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign cr_a_ok = logical_op__write_cr0;
  assign \cr_a$22  = cr0;
  assign \o_ok$21  = o_ok;
  assign \o$20  = \o$23 [63:0];
  assign is_positive = \$38 ;
  assign is_negative = msb_test;
  assign is_nzero = \$34 ;
  assign msb_test = target[63];
  assign is_cmpeqb = \$32 ;
  assign is_cmp = \$30 ;
  assign target = \o$23 [63:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:160302.1-160752.10" *)
module \output$83 (logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, o, o_ok, cr_a, xer_ov, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , cr_a_ok, \xer_ov$23 , xer_ov_ok, \xer_so$24 , xer_so_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:160673.3-160684.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:160303.7-160303.20" *)
  reg _01_;
  (* src = "libresoc.v:160685.3-160696.6" *)
  reg [64:0] _02_;
  (* src = "libresoc.v:160661.3-160672.6" *)
  reg _03_;
  (* src = "libresoc.v:160717.3-160726.6" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:160727.3-160736.6" *)
  reg _05_;
  (* src = "libresoc.v:160697.3-160706.6" *)
  reg _06_;
  (* src = "libresoc.v:160707.3-160716.6" *)
  reg _07_;
  (* src = "libresoc.v:160673.3-160684.6" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:160685.3-160696.6" *)
  reg [64:0] _09_;
  (* src = "libresoc.v:160661.3-160672.6" *)
  reg _10_;
  (* src = "libresoc.v:160717.3-160726.6" *)
  reg [1:0] _11_;
  (* src = "libresoc.v:160727.3-160736.6" *)
  reg _12_;
  (* src = "libresoc.v:160697.3-160706.6" *)
  reg _13_;
  (* src = "libresoc.v:160707.3-160716.6" *)
  reg _14_;
  (* src = "libresoc.v:160648.18-160648.136" *)
  wire _15_;
  (* src = "libresoc.v:160656.18-160656.112" *)
  wire _16_;
  (* src = "libresoc.v:160659.18-160659.133" *)
  wire _17_;
  (* src = "libresoc.v:160652.18-160652.127" *)
  wire _18_;
  (* src = "libresoc.v:160653.18-160653.127" *)
  wire _19_;
  (* src = "libresoc.v:160650.18-160650.103" *)
  wire [64:0] _20_;
  (* src = "libresoc.v:160651.18-160651.101" *)
  wire [64:0] _21_;
  (* src = "libresoc.v:160649.18-160649.100" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:160655.18-160655.107" *)
  wire _23_;
  (* src = "libresoc.v:160658.18-160658.107" *)
  wire _24_;
  (* src = "libresoc.v:160657.18-160657.115" *)
  wire _25_;
  (* src = "libresoc.v:160660.18-160660.112" *)
  wire _26_;
  (* src = "libresoc.v:160650.18-160650.103" *)
  wire [64:0] _27_;
  (* src = "libresoc.v:160651.18-160651.101" *)
  wire [64:0] _28_;
  (* src = "libresoc.v:160654.18-160654.105" *)
  wire _29_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [64:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *)
  wire [63:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [64:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" *)
  reg [3:0] cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "libresoc.v:160303.7-160303.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" *)
  wire is_cmp;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" *)
  wire is_cmpeqb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" *)
  wire is_negative;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" *)
  wire is_nzero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" *)
  wire is_positive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" *)
  wire msb_test;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" *)
  reg [64:0] \o$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" *)
  wire oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" *)
  wire \oe$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" *)
  reg so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" *)
  wire [63:0] target;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$23 ;
  reg [1:0] \xer_ov$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$24 ;
  reg \xer_so$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  assign _15_ = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" *) logical_op__oe__ok;
  assign _16_ = is_nzero & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) \$40 ;
  assign _17_ = logical_op__oe__oe & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" *) logical_op__oe__ok;
  assign _18_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" *) 7'h0a;
  assign _19_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" *) 7'h0c;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) \$29 ;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) o;
  assign _22_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) o;
  assign _23_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" *) msb_test;
  assign _24_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" *) is_nzero;
  assign _25_ = is_cmpeqb | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *) is_cmp;
  assign _26_ = xer_so | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" *) xer_ov[0];
  assign _27_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" *) _20_;
  assign _28_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _21_;
  assign _29_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" *) target;
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _10_;
    (* src = "libresoc.v:160662.5-160662.29" *)
    casez (\initial )
      /* src = "libresoc.v:160662.9-160662.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" *)
    casez (oe)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _10_ = \xer_so$24 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _10_ = xer_so;
        end
    endcase
  end
  always @* begin
      so <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _08_;
    (* src = "libresoc.v:160674.5-160674.29" *)
    casez (\initial )
      /* src = "libresoc.v:160674.9-160674.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" *)
    casez (\$44 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _08_ = cr_a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _08_ = { is_negative, is_positive, \$46 , so };
        end
    endcase
  end
  always @* begin
      cr0 <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _09_;
    (* src = "libresoc.v:160686.5-160686.29" *)
    casez (\initial )
      /* src = "libresoc.v:160686.9-160686.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" *)
    casez (logical_op__invert_out)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _09_ = \$28 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _09_ = \$32 ;
        end
    endcase
  end
  always @* begin
      \o$27  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _13_;
    (* src = "libresoc.v:160698.5-160698.29" *)
    casez (\initial )
      /* src = "libresoc.v:160698.9-160698.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = \$51 ;
        end
      default:
          _13_ = 1'h0;
    endcase
  end
  always @* begin
      \xer_so$24  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _14_;
    (* src = "libresoc.v:160708.5-160708.29" *)
    casez (\initial )
      /* src = "libresoc.v:160708.9-160708.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = 1'h1;
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      xer_so_ok <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _11_;
    (* src = "libresoc.v:160718.5-160718.29" *)
    casez (\initial )
      /* src = "libresoc.v:160718.9-160718.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _11_ = xer_ov;
        end
      default:
          _11_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ov$23  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _12_;
    (* src = "libresoc.v:160728.5-160728.29" *)
    casez (\initial )
      /* src = "libresoc.v:160728.9-160728.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" *)
    casez (\oe$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 1'h1;
        end
      default:
          _12_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _05_;
  end
  assign \$25  = _15_;
  assign \$29  = _22_;
  assign \$28  = _27_;
  assign \$32  = _28_;
  assign \$34  = _18_;
  assign \$36  = _19_;
  assign \$38  = _29_;
  assign \$40  = _23_;
  assign \$42  = _16_;
  assign \$44  = _25_;
  assign \$46  = _24_;
  assign \$49  = _17_;
  assign \$51  = _26_;
  assign \oe$48  = \$49 ;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign cr_a_ok = logical_op__write_cr0;
  assign \cr_a$22  = cr0;
  assign \o_ok$21  = o_ok;
  assign \o$20  = \o$27 [63:0];
  assign is_positive = \$42 ;
  assign is_negative = msb_test;
  assign is_nzero = \$38 ;
  assign msb_test = target[63];
  assign is_cmpeqb = \$36 ;
  assign is_cmp = \$34 ;
  assign target = \o$27 [63:0];
  assign oe = \$25 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:160756.1-161238.10" *)
module output_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, xer_ov, xer_ov_ok, \xer_so$20 , muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:160757.7-160757.20" *)
  reg _00_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:161191.3-161224.6" *)
  reg _02_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:161191.3-161224.6" *)
  reg _04_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:161191.3-161224.6" *)
  reg _06_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:161191.3-161224.6" *)
  reg _08_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _09_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _10_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:161119.3-161190.6" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:161110.18-161110.122" *)
  wire _14_;
  (* src = "libresoc.v:161102.18-161102.109" *)
  wire [64:0] _15_;
  (* src = "libresoc.v:161103.18-161103.100" *)
  wire [64:0] _16_;
  (* src = "libresoc.v:161105.18-161105.113" *)
  wire [64:0] _17_;
  (* src = "libresoc.v:161106.18-161106.104" *)
  wire [64:0] _18_;
  (* src = "libresoc.v:161114.18-161114.114" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:161115.18-161115.114" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:161116.18-161116.114" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:161117.18-161117.114" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:161118.18-161118.115" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:161111.18-161111.128" *)
  wire _24_;
  (* src = "libresoc.v:161102.18-161102.109" *)
  wire [64:0] _25_;
  (* src = "libresoc.v:161105.18-161105.113" *)
  wire [64:0] _26_;
  (* src = "libresoc.v:161108.18-161108.116" *)
  wire _27_;
  (* src = "libresoc.v:161113.18-161113.99" *)
  wire _28_;
  (* src = "libresoc.v:161103.18-161103.100" *)
  wire [64:0] _29_;
  (* src = "libresoc.v:161106.18-161106.104" *)
  wire [64:0] _30_;
  (* src = "libresoc.v:161112.18-161112.118" *)
  wire [63:0] _31_;
  (* src = "libresoc.v:161114.18-161114.114" *)
  wire [63:0] _32_;
  (* src = "libresoc.v:161115.18-161115.114" *)
  wire [63:0] _33_;
  (* src = "libresoc.v:161116.18-161116.114" *)
  wire [63:0] _34_;
  (* src = "libresoc.v:161117.18-161117.114" *)
  wire [63:0] _35_;
  (* src = "libresoc.v:161118.18-161118.115" *)
  wire [63:0] _36_;
  (* src = "libresoc.v:161104.18-161104.121" *)
  wire [64:0] _37_;
  (* src = "libresoc.v:161107.18-161107.122" *)
  wire [64:0] _38_;
  (* src = "libresoc.v:161101.18-161101.120" *)
  wire _39_;
  (* src = "libresoc.v:161109.18-161109.127" *)
  wire _40_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *)
  wire [64:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  wire [64:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *)
  wire [64:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
  wire [64:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
  wire [64:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [64:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *)
  wire [64:0] \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *)
  wire [63:0] \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *)
  wire [63:0] \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *)
  wire [63:0] \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *)
  wire [63:0] \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *)
  wire [63:0] \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *)
  wire [63:0] \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  input div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  input dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  input dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  input dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  input divisor_neg;
  (* src = "libresoc.v:160757.7-160757.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" *)
  reg ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" *)
  wire [64:0] quotient_65;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" *)
  wire quotient_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  input [63:0] quotient_root;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  input [191:0] remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" *)
  wire [63:0] remainder_64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" *)
  wire remainder_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *)
  wire [31:0] remainder_s32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" *)
  wire [63:0] remainder_s32_as_s64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$20 ;
  assign _14_ = logical_op__is_signed & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) \$38 ;
  assign _15_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) quotient_root;
  assign _16_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) quotient_root;
  assign _17_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) remainder[127:64];
  assign _18_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) remainder[127:64];
  assign _19_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) quotient_65[31:0];
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) quotient_65[31:0];
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) quotient_65[31:0];
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) quotient_65[31:0];
  assign _23_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) remainder_64[31:0];
  assign _24_ = quotient_65[32] != (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *) quotient_65[31];
  assign _25_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) _15_;
  assign _26_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) _17_;
  assign _27_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" *) logical_op__is_32bit;
  assign _28_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *) ov;
  assign _29_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *) _16_;
  assign _30_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _18_;
  assign _31_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" *) $signed({ remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32[31], remainder_s32 });
  assign _32_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" *) _19_;
  assign _33_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" *) _20_;
  assign _34_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" *) _21_;
  assign _35_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" *) _22_;
  assign _36_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" *) _23_;
  assign _37_ = quotient_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" *) \$23  : \$25 ;
  assign _38_ = remainder_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" *) \$30  : \$32 ;
  assign _39_ = dividend_neg ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" *) divisor_neg;
  assign _40_ = quotient_65[64] ^ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *) quotient_65[63];
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:161120.5-161120.29" *)
    casez (\initial )
      /* src = "libresoc.v:161120.9-161120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" *)
    casez (\$46 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = _05_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" *)
          casez (logical_op__insn_type)
            /* src = "libresoc.v:0.0-0.0" */
            7'h1e:
              begin
                _05_ = _07_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" *)
                casez (logical_op__is_32bit)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _07_ = _09_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:106" *)
                      casez (logical_op__is_signed)
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _09_ = \$48 ;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _09_ = \$50 ;
                          end
                      endcase
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _07_ = quotient_65[63:0];
                    end
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h1d:
              begin
                _05_ = _10_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114" *)
                casez (logical_op__is_32bit)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _10_ = _11_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:115" *)
                      casez (logical_op__is_signed)
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _11_ = \$52 ;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _11_ = \$54 ;
                          end
                      endcase
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _10_ = quotient_65[63:0];
                    end
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            7'h2f:
              begin
                _05_ = _12_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" *)
                casez (logical_op__is_32bit)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _12_ = _13_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:124" *)
                      casez (logical_op__is_signed)
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _13_ = remainder_s32_as_s64;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _13_ = \$56 ;
                          end
                      endcase
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _12_ = remainder_64;
                    end
                endcase
              end
            default:
                _05_ = 64'h0000000000000000;
          endcase
        end
      default:
          _03_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      o <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _04_;
    (* src = "libresoc.v:161192.5-161192.29" *)
    casez (\initial )
      /* src = "libresoc.v:161192.9-161192.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" *)
    casez ({ logical_op__is_signed, \$36 , div_by_zero })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _04_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
        begin
          _04_ = _06_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" *)
          casez (\$40 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _06_ = 1'h1;
              end
            default:
                _06_ = dive_abs_ov64;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b1??:
        begin
          _04_ = _08_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" *)
          casez (\$42 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _08_ = 1'h1;
              end
            default:
                _08_ = dive_abs_ov32;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _04_ = dive_abs_ov32;
        end
    endcase
  end
  always @* begin
      ov <= _02_;
  end
  assign \$21  = _39_;
  assign \$23  = _25_;
  assign \$25  = _29_;
  assign \$27  = _37_;
  assign \$30  = _26_;
  assign \$32  = _30_;
  assign \$34  = _38_;
  assign \$36  = _27_;
  assign \$38  = _40_;
  assign \$40  = _14_;
  assign \$42  = _24_;
  assign \$44  = _31_;
  assign \$46  = _28_;
  assign \$48  = _32_;
  assign \$50  = _33_;
  assign \$52  = _34_;
  assign \$54  = _35_;
  assign \$56  = _36_;
  assign \$29  = \$34 ;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$20  = xer_so;
  assign remainder_s32_as_s64 = \$44 ;
  assign remainder_s32 = remainder_64[31:0];
  assign o_ok = 1'h1;
  assign xer_ov = { ov, ov };
  assign xer_ov_ok = 1'h1;
  assign remainder_64 = \$34 [63:0];
  assign quotient_65 = \$27 ;
  assign remainder_neg = dividend_neg;
  assign quotient_neg = \$21 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161242.1-161253.10" *)
module p(p_ready_o, p_valid_i);
  (* src = "libresoc.v:161251.17-161251.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161257.1-161268.10" *)
module \p$1 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161266.17-161266.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161272.1-161283.10" *)
module \p$108 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161281.17-161281.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161287.1-161298.10" *)
module \p$111 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161296.17-161296.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161302.1-161313.10" *)
module \p$116 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161311.17-161311.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161317.1-161328.10" *)
module \p$17 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161326.17-161326.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161332.1-161343.10" *)
module \p$20 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161341.17-161341.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161347.1-161358.10" *)
module \p$3 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161356.17-161356.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161362.1-161373.10" *)
module \p$30 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161371.17-161371.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161377.1-161388.10" *)
module \p$33 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161386.17-161386.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161392.1-161403.10" *)
module \p$36 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161401.17-161401.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161407.1-161418.10" *)
module \p$46 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161416.17-161416.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161422.1-161433.10" *)
module \p$48 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161431.17-161431.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161437.1-161448.10" *)
module \p$5 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161446.17-161446.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161452.1-161463.10" *)
module \p$52 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161461.17-161461.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161467.1-161478.10" *)
module \p$62 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161476.17-161476.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161482.1-161493.10" *)
module \p$65 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161491.17-161491.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161497.1-161508.10" *)
module \p$7 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161506.17-161506.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161512.1-161523.10" *)
module \p$74 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161521.17-161521.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161527.1-161538.10" *)
module \p$76 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161536.17-161536.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161542.1-161553.10" *)
module \p$79 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161551.17-161551.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161557.1-161568.10" *)
module \p$81 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161566.17-161566.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161572.1-161583.10" *)
module \p$91 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161581.17-161581.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161587.1-161598.10" *)
module \p$93 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161596.17-161596.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161602.1-161613.10" *)
module \p$96 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161611.17-161611.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161617.1-161628.10" *)
module \p$98 (p_ready_o, p_valid_i);
  (* src = "libresoc.v:161626.17-161626.111" *)
  wire _0_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  input p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" *)
  wire trigger;
  assign _0_ = p_valid_i & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" *) p_ready_o;
  assign \$1  = _0_;
  assign trigger = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.l0.pick" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161632.1-161655.10" *)
module pick(o, n, i);
  reg \initial  = 0;
  (* src = "libresoc.v:161633.7-161633.20" *)
  reg _0_;
  (* src = "libresoc.v:161644.3-161653.6" *)
  reg _1_;
  (* src = "libresoc.v:161644.3-161653.6" *)
  reg _2_;
  (* src = "libresoc.v:161643.17-161643.95" *)
  wire _3_;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" *)
  input i;
  (* src = "libresoc.v:161633.7-161633.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" *)
  output n;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" *)
  output o;
  reg o;
  assign _3_ = i == (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" *) 1'h0;
  always @* begin
    if (\initial ) begin end
    _0_ = 1'h0;
  end
  always @* begin
      \initial  <= _0_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _2_;
    (* src = "libresoc.v:161645.5-161645.29" *)
    casez (\initial )
      /* src = "libresoc.v:161645.9-161645.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" *)
    casez (i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _2_ = 1'h0;
        end
      default:
          _2_ = 1'h0;
    endcase
  end
  always @* begin
      o <= _1_;
  end
  assign \$1  = _3_;
  assign n = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:161659.1-162473.10" *)
module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_busy_o, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, x_mask_i, x_addr_i, ldst_port0_addr_ok_o, m_ld_data_o, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i_ok, ldst_port0_st_data_i, x_st_data_i, x_busy_o, \ldst_port0_exc_$signal , x_ld_i, x_st_i, m_valid_i, x_valid_i, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:162436.3-162451.6" *)
  reg _000_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _001_;
  (* src = "libresoc.v:161958.3-161959.57" *)
  reg _002_;
  (* src = "libresoc.v:162050.3-162058.6" *)
  reg _003_;
  (* src = "libresoc.v:161956.3-161957.37" *)
  reg _004_;
  (* src = "libresoc.v:162384.3-162399.6" *)
  reg _005_;
  (* src = "libresoc.v:162374.3-162383.6" *)
  reg _006_;
  (* src = "libresoc.v:162364.3-162373.6" *)
  reg _007_;
  (* src = "libresoc.v:162345.3-162354.6" *)
  reg _008_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:161948.3-161949.35" *)
  reg [1:0] _010_;
  (* src = "libresoc.v:161660.7-161660.20" *)
  reg _011_;
  (* src = "libresoc.v:162246.3-162255.6" *)
  reg _012_;
  (* src = "libresoc.v:161954.3-161955.35" *)
  reg _013_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _014_;
  (* src = "libresoc.v:162236.3-162245.6" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:162256.3-162265.6" *)
  reg _016_;
  (* src = "libresoc.v:162085.3-162100.6" *)
  reg [3:0] _017_;
  (* src = "libresoc.v:162069.3-162084.6" *)
  reg [3:0] _018_;
  (* src = "libresoc.v:162355.3-162363.6" *)
  reg _019_;
  (* src = "libresoc.v:161946.3-161947.47" *)
  reg _020_;
  (* src = "libresoc.v:162286.3-162305.6" *)
  reg _021_;
  (* src = "libresoc.v:161950.3-161951.36" *)
  reg _022_;
  (* src = "libresoc.v:162226.3-162235.6" *)
  reg _023_;
  (* src = "libresoc.v:162210.3-162225.6" *)
  reg _024_;
  (* src = "libresoc.v:162059.3-162068.6" *)
  reg _025_;
  (* src = "libresoc.v:162040.3-162049.6" *)
  reg _026_;
  (* src = "libresoc.v:162025.3-162039.6" *)
  reg _027_;
  (* src = "libresoc.v:161960.3-161961.51" *)
  reg _028_;
  (* src = "libresoc.v:162266.3-162275.6" *)
  reg [63:0] _029_;
  (* src = "libresoc.v:161952.3-161953.35" *)
  reg _030_;
  (* src = "libresoc.v:162101.3-162126.6" *)
  reg _031_;
  (* src = "libresoc.v:162153.3-162178.6" *)
  reg [47:0] _032_;
  (* src = "libresoc.v:162127.3-162152.6" *)
  reg [7:0] _033_;
  (* src = "libresoc.v:162276.3-162285.6" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:162436.3-162451.6" *)
  reg _035_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _036_;
  (* src = "libresoc.v:161754.7-161754.34" *)
  reg _037_;
  (* src = "libresoc.v:162050.3-162058.6" *)
  reg _038_;
  (* src = "libresoc.v:161758.7-161758.24" *)
  reg _039_;
  (* src = "libresoc.v:162384.3-162399.6" *)
  reg _040_;
  (* src = "libresoc.v:162374.3-162383.6" *)
  reg _041_;
  (* src = "libresoc.v:162364.3-162373.6" *)
  reg _042_;
  (* src = "libresoc.v:162345.3-162354.6" *)
  reg _043_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _044_;
  (* src = "libresoc.v:161780.13-161780.29" *)
  reg [1:0] _045_;
  (* src = "libresoc.v:162246.3-162255.6" *)
  reg _046_;
  (* src = "libresoc.v:161794.7-161794.21" *)
  reg _047_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _048_;
  (* src = "libresoc.v:162236.3-162245.6" *)
  reg [63:0] _049_;
  (* src = "libresoc.v:162256.3-162265.6" *)
  reg _050_;
  (* src = "libresoc.v:162085.3-162100.6" *)
  reg [3:0] _051_;
  (* src = "libresoc.v:162069.3-162084.6" *)
  reg [3:0] _052_;
  (* src = "libresoc.v:162355.3-162363.6" *)
  reg _053_;
  (* src = "libresoc.v:161837.7-161837.29" *)
  reg _054_;
  (* src = "libresoc.v:162286.3-162305.6" *)
  reg _055_;
  (* src = "libresoc.v:161849.7-161849.25" *)
  reg _056_;
  (* src = "libresoc.v:162226.3-162235.6" *)
  reg _057_;
  (* src = "libresoc.v:162210.3-162225.6" *)
  reg _058_;
  (* src = "libresoc.v:162059.3-162068.6" *)
  reg _059_;
  (* src = "libresoc.v:162040.3-162049.6" *)
  reg _060_;
  (* src = "libresoc.v:162025.3-162039.6" *)
  reg _061_;
  (* src = "libresoc.v:161869.7-161869.31" *)
  reg _062_;
  (* src = "libresoc.v:162266.3-162275.6" *)
  reg [63:0] _063_;
  (* src = "libresoc.v:161877.7-161877.21" *)
  reg _064_;
  (* src = "libresoc.v:162101.3-162126.6" *)
  reg _065_;
  (* src = "libresoc.v:162153.3-162178.6" *)
  reg [47:0] _066_;
  (* src = "libresoc.v:162127.3-162152.6" *)
  reg [7:0] _067_;
  (* src = "libresoc.v:162276.3-162285.6" *)
  reg [63:0] _068_;
  (* src = "libresoc.v:162436.3-162451.6" *)
  reg _069_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _070_;
  (* src = "libresoc.v:162384.3-162399.6" *)
  reg _071_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _072_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _073_;
  (* src = "libresoc.v:162085.3-162100.6" *)
  reg [3:0] _074_;
  (* src = "libresoc.v:162069.3-162084.6" *)
  reg [3:0] _075_;
  (* src = "libresoc.v:162286.3-162305.6" *)
  reg _076_;
  (* src = "libresoc.v:162210.3-162225.6" *)
  reg _077_;
  (* src = "libresoc.v:162025.3-162039.6" *)
  reg _078_;
  (* src = "libresoc.v:162101.3-162126.6" *)
  reg _079_;
  (* src = "libresoc.v:162153.3-162178.6" *)
  reg [47:0] _080_;
  (* src = "libresoc.v:162127.3-162152.6" *)
  reg [7:0] _081_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _082_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _083_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _084_;
  (* src = "libresoc.v:162101.3-162126.6" *)
  reg _085_;
  (* src = "libresoc.v:162153.3-162178.6" *)
  reg [47:0] _086_;
  (* src = "libresoc.v:162127.3-162152.6" *)
  reg [7:0] _087_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _088_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _089_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _090_;
  (* src = "libresoc.v:162101.3-162126.6" *)
  reg _091_;
  (* src = "libresoc.v:162153.3-162178.6" *)
  reg [47:0] _092_;
  (* src = "libresoc.v:162127.3-162152.6" *)
  reg [7:0] _093_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _094_;
  (* src = "libresoc.v:162306.3-162344.6" *)
  reg [1:0] _095_;
  (* src = "libresoc.v:162179.3-162209.6" *)
  reg _096_;
  (* src = "libresoc.v:162400.3-162435.6" *)
  reg _097_;
  (* src = "libresoc.v:161906.18-161906.115" *)
  wire _098_;
  (* src = "libresoc.v:161908.18-161908.95" *)
  wire _099_;
  (* src = "libresoc.v:161910.17-161910.138" *)
  wire _100_;
  (* src = "libresoc.v:161911.18-161911.95" *)
  wire _101_;
  (* src = "libresoc.v:161914.18-161914.136" *)
  wire _102_;
  (* src = "libresoc.v:161915.18-161915.136" *)
  wire _103_;
  (* src = "libresoc.v:161916.18-161916.136" *)
  wire _104_;
  (* src = "libresoc.v:161917.18-161917.136" *)
  wire _105_;
  (* src = "libresoc.v:161918.18-161918.136" *)
  wire _106_;
  (* src = "libresoc.v:161923.18-161923.119" *)
  wire [175:0] _107_;
  (* src = "libresoc.v:161926.18-161926.136" *)
  wire _108_;
  (* src = "libresoc.v:161927.18-161927.136" *)
  wire _109_;
  (* src = "libresoc.v:161929.18-161929.139" *)
  wire _110_;
  (* src = "libresoc.v:161933.18-161933.139" *)
  wire _111_;
  (* src = "libresoc.v:161935.18-161935.114" *)
  wire _112_;
  (* src = "libresoc.v:161937.18-161937.114" *)
  wire _113_;
  (* src = "libresoc.v:161941.18-161941.103" *)
  wire _114_;
  (* src = "libresoc.v:161942.17-161942.135" *)
  wire _115_;
  (* src = "libresoc.v:161945.18-161945.103" *)
  wire _116_;
  (* src = "libresoc.v:161912.18-161912.109" *)
  wire [3:0] _117_;
  (* src = "libresoc.v:161913.18-161913.109" *)
  wire [3:0] _118_;
  (* src = "libresoc.v:161924.18-161924.112" *)
  wire [7:0] _119_;
  (* src = "libresoc.v:161930.18-161930.112" *)
  wire [7:0] _120_;
  (* src = "libresoc.v:161905.17-161905.103" *)
  wire _121_;
  (* src = "libresoc.v:161907.18-161907.94" *)
  wire _122_;
  (* src = "libresoc.v:161909.18-161909.94" *)
  wire _123_;
  (* src = "libresoc.v:161919.18-161919.102" *)
  wire _124_;
  (* src = "libresoc.v:161922.18-161922.97" *)
  wire _125_;
  (* src = "libresoc.v:161928.18-161928.102" *)
  wire _126_;
  (* src = "libresoc.v:161931.17-161931.103" *)
  wire _127_;
  (* src = "libresoc.v:161938.18-161938.101" *)
  wire _128_;
  (* src = "libresoc.v:161939.18-161939.111" *)
  wire _129_;
  (* src = "libresoc.v:161940.18-161940.110" *)
  wire _130_;
  (* src = "libresoc.v:161943.18-161943.102" *)
  wire _131_;
  (* src = "libresoc.v:161944.18-161944.102" *)
  wire _132_;
  (* src = "libresoc.v:161920.18-161920.111" *)
  wire _133_;
  (* src = "libresoc.v:161921.17-161921.130" *)
  wire _134_;
  (* src = "libresoc.v:161934.18-161934.130" *)
  wire _135_;
  (* src = "libresoc.v:161936.18-161936.130" *)
  wire _136_;
  (* src = "libresoc.v:161912.18-161912.109" *)
  wire [3:0] _137_;
  (* src = "libresoc.v:161913.18-161913.109" *)
  wire [3:0] _138_;
  (* src = "libresoc.v:161932.18-161932.121" *)
  wire [318:0] _139_;
  (* src = "libresoc.v:161925.18-161925.106" *)
  wire [175:0] _140_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [3:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *)
  wire [3:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *)
  wire [175:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *)
  wire [175:0] \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *)
  wire [7:0] \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *)
  wire [175:0] \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
  wire \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *)
  wire [318:0] \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *)
  wire [7:0] \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *)
  wire [318:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire adrok_l_q_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire adrok_l_qn_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg adrok_l_r_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg adrok_l_s_addr_acked;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \adrok_l_s_addr_acked$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *)
  reg busy_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:213" *)
  reg \busy_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:214" *)
  wire busy_edge;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire busy_l_q_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg busy_l_r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg busy_l_s_busy;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire cyc_l_q_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg cyc_l_r_cyc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg cyc_l_s_cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *)
  reg [1:0] fsm_state;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *)
  reg [1:0] \fsm_state$next ;
  (* src = "libresoc.v:161660.7-161660.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire ld_active_q_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg ld_active_r_ld_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire ld_active_s_ld_active;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:255" *)
  wire [63:0] lddata;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" *)
  wire lds;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg lds_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \lds_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire lds_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [47:0] ldst_port0_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_addr_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" *)
  output ldst_port0_addr_ok_o;
  reg ldst_port0_addr_ok_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" *)
  output ldst_port0_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" *)
  input [3:0] ldst_port0_data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  input \ldst_port0_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" *)
  input ldst_port0_is_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" *)
  input ldst_port0_is_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] ldst_port0_ld_data_o;
  reg [63:0] ldst_port0_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output ldst_port0_ld_data_o_ok;
  reg ldst_port0_ld_data_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] ldst_port0_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input ldst_port0_st_data_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" *)
  reg [3:0] lenexp_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" *)
  reg [3:0] lenexp_len_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" *)
  wire [63:0] lenexp_lexp_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" *)
  wire [175:0] lenexp_rexp_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" *)
  wire lsui_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg lsui_active_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg \lsui_active_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire lsui_active_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" *)
  reg lsui_busy;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:69" *)
  input [63:0] m_ld_data_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:61" *)
  output m_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *)
  reg reset_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:280" *)
  wire \reset_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire reset_l_q_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg reset_l_r_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg reset_l_s_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire st_active_q_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg st_active_r_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire st_active_s_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire st_done_q_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg st_done_r_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg st_done_s_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \st_done_s_st_done$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:270" *)
  reg [63:0] stdata;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" *)
  wire sts;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg sts_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \sts_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire sts_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire valid_l_q_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  wire valid_l_r_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg valid_l_s_valid;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" *)
  output [47:0] x_addr_i;
  reg [47:0] x_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:66" *)
  input x_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52" *)
  output x_ld_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51" *)
  output [7:0] x_mask_i;
  reg [7:0] x_mask_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" *)
  output [63:0] x_st_data_i;
  reg [63:0] x_st_data_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" *)
  output x_st_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" *)
  output x_valid_i;
  assign _098_ = ldst_port0_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) \$9 ;
  assign _099_ = lds & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ;
  assign _100_ = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok;
  assign _101_ = sts & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ;
  assign _102_ = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked;
  assign _103_ = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked;
  assign _104_ = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked;
  assign _105_ = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked;
  assign _106_ = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked;
  assign _107_ = m_ld_data_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" *) lenexp_rexp_o;
  assign _108_ = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked;
  assign _109_ = ld_active_q_ld_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *) adrok_l_q_addr_acked;
  assign _110_ = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok;
  assign _111_ = st_active_q_st_active & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *) ldst_port0_st_data_i_ok;
  assign _112_ = \$63  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid;
  assign _113_ = \$67  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) valid_l_q_valid;
  assign _114_ = \$73  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) \$75 ;
  assign _115_ = ldst_port0_addr_i_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *) adrok_l_qn_addr_acked;
  assign _116_ = lsui_active & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$81 ;
  assign _117_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ldst_port0_addr_i[2:0];
  assign _118_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) ldst_port0_addr_i[2:0];
  assign _119_ = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) 4'h8;
  assign _120_ = lenexp_addr_i * (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) 4'h8;
  assign _121_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" *) busy_delay;
  assign _122_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lds_dly;
  assign _123_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) sts_dly;
  assign _124_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy;
  assign _125_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) \$38 ;
  assign _126_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" *) lsui_busy;
  assign _127_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" *) busy_delay;
  assign _128_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *) x_busy_o;
  assign _129_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_is_st_i;
  assign _130_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *) ldst_port0_busy_o;
  assign _131_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" *) x_busy_o;
  assign _132_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) lsui_active_dly;
  assign _133_ = x_busy_o | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" *) lsui_busy;
  assign _134_ = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *) ldst_port0_is_st_i;
  assign _135_ = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i;
  assign _136_ = ldst_port0_is_ld_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *) ldst_port0_is_st_i;
  assign _137_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _117_;
  assign _138_ = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" *) _118_;
  assign _139_ = ldst_port0_st_data_i <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" *) \$57 ;
  assign _140_ = \$42  >>> (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" *) \$44 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161962.11-161969.4" *)
  adrok_l adrok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_addr_acked(adrok_l_q_addr_acked),
    .qn_addr_acked(adrok_l_qn_addr_acked),
    .r_addr_acked(adrok_l_r_addr_acked),
    .s_addr_acked(adrok_l_s_addr_acked)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161970.10-161976.4" *)
  busy_l busy_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_busy(busy_l_q_busy),
    .r_busy(busy_l_r_busy),
    .s_busy(busy_l_s_busy)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161977.9-161983.4" *)
  cyc_l cyc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_cyc(cyc_l_q_cyc),
    .r_cyc(cyc_l_r_cyc),
    .s_cyc(cyc_l_s_cyc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161984.13-161990.4" *)
  ld_active ld_active (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_ld_active(ld_active_q_ld_active),
    .r_ld_active(ld_active_r_ld_active),
    .s_ld_active(ld_active_s_ld_active)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161991.10-161996.4" *)
  lenexp lenexp (
    .addr_i(lenexp_addr_i),
    .len_i(lenexp_len_i),
    .lexp_o(lenexp_lexp_o),
    .rexp_o(lenexp_rexp_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:161997.11-162003.4" *)
  reset_l reset_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_reset(reset_l_q_reset),
    .r_reset(reset_l_r_reset),
    .s_reset(reset_l_s_reset)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:162004.13-162010.4" *)
  st_active st_active (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_st_active(st_active_q_st_active),
    .r_st_active(st_active_r_st_active),
    .s_st_active(st_active_s_st_active)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:162011.11-162017.4" *)
  st_done st_done (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_st_done(st_done_q_st_done),
    .r_st_done(st_done_r_st_done),
    .s_st_done(st_done_s_st_done)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:162018.11-162024.4" *)
  valid_l valid_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_valid(valid_l_q_valid),
    .r_valid(valid_l_r_valid),
    .s_valid(valid_l_s_valid)
  );
  always @* begin
    if (\initial ) begin end
    _011_ = 1'h0;
  end
  always @* begin
      \initial  <= _011_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      adrok_l_s_addr_acked <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      busy_delay <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      fsm_state <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      lds_dly <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      lsui_active_dly <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      reset_delay <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      st_done_s_st_done <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sts_dly <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \lsui_active_dly$next ;
  end
  always @(posedge coresync_clk) begin
      lsui_active_dly <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \fsm_state$next ;
  end
  always @(posedge coresync_clk) begin
      fsm_state <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = reset_l_q_reset;
  end
  always @(posedge coresync_clk) begin
      reset_delay <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = ldst_port0_is_st_i;
  end
  always @(posedge coresync_clk) begin
      sts_dly <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = ldst_port0_is_ld_i;
  end
  always @(posedge coresync_clk) begin
      lds_dly <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \busy_delay$next ;
  end
  always @(posedge coresync_clk) begin
      busy_delay <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \adrok_l_s_addr_acked$next ;
  end
  always @(posedge coresync_clk) begin
      adrok_l_s_addr_acked <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \st_done_s_st_done$next ;
  end
  always @(posedge coresync_clk) begin
      st_done_s_st_done <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _078_;
    (* src = "libresoc.v:162026.5-162026.29" *)
    casez (\initial )
      /* src = "libresoc.v:162026.9-162026.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _061_ = 1'h1;
        end
      default:
          _061_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _078_ = 1'h0;
        end
      default:
          _078_ = _061_;
    endcase
  end
  always @* begin
      \st_done_s_st_done$next  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _060_;
    (* src = "libresoc.v:162041.5-162041.29" *)
    casez (\initial )
      /* src = "libresoc.v:162041.9-162041.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _060_ = 1'h1;
        end
      default:
          _060_ = 1'h0;
    endcase
  end
  always @* begin
      st_done_r_st_done <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _038_;
    (* src = "libresoc.v:162051.5-162051.29" *)
    casez (\initial )
      /* src = "libresoc.v:162051.9-162051.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _038_ = 1'h0;
        end
      default:
          _038_ = ldst_port0_busy_o;
    endcase
  end
  always @* begin
      \busy_delay$next  <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _059_;
    (* src = "libresoc.v:162060.5-162060.29" *)
    casez (\initial )
      /* src = "libresoc.v:162060.9-162060.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _059_ = 1'h1;
        end
      default:
          _059_ = 1'h0;
    endcase
  end
  always @* begin
      st_active_r_st_active <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _075_;
    (* src = "libresoc.v:162070.5-162070.29" *)
    casez (\initial )
      /* src = "libresoc.v:162070.9-162070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _052_ = ldst_port0_data_len;
        end
      default:
          _052_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _075_ = ldst_port0_data_len;
        end
      default:
          _075_ = _052_;
    endcase
  end
  always @* begin
      lenexp_len_i <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _074_;
    (* src = "libresoc.v:162086.5-162086.29" *)
    casez (\initial )
      /* src = "libresoc.v:162086.9-162086.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _051_ = \$21 ;
        end
      default:
          _051_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _074_ = \$23 ;
        end
      default:
          _074_ = _051_;
    endcase
  end
  always @* begin
      lenexp_addr_i <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = _085_;
    (* src = "libresoc.v:162102.5-162102.29" *)
    casez (\initial )
      /* src = "libresoc.v:162102.9-162102.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _065_ = _079_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
          casez (\$25 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _079_ = 1'h1;
              end
            default:
                _079_ = 1'h0;
          endcase
        end
      default:
          _065_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _085_ = _091_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *)
          casez (ldst_port0_addr_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _091_ = 1'h1;
              end
            default:
                _091_ = _065_;
          endcase
        end
      default:
          _085_ = _065_;
    endcase
  end
  always @* begin
      valid_l_s_valid <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = _087_;
    (* src = "libresoc.v:162128.5-162128.29" *)
    casez (\initial )
      /* src = "libresoc.v:162128.9-162128.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _067_ = _081_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
          casez (\$27 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _081_ = lenexp_lexp_o[7:0];
              end
            default:
                _081_ = 8'h00;
          endcase
        end
      default:
          _067_ = 8'h00;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = _093_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *)
          casez (ldst_port0_addr_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _093_ = lenexp_lexp_o[7:0];
              end
            default:
                _093_ = _067_;
          endcase
        end
      default:
          _087_ = _067_;
    endcase
  end
  always @* begin
      x_mask_i <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _086_;
    (* src = "libresoc.v:162154.5-162154.29" *)
    casez (\initial )
      /* src = "libresoc.v:162154.9-162154.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _066_ = _080_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
          casez (\$29 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _080_ = ldst_port0_addr_i;
              end
            default:
                _080_ = 48'h000000000000;
          endcase
        end
      default:
          _066_ = 48'h000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _086_ = _092_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *)
          casez (ldst_port0_addr_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _092_ = ldst_port0_addr_i;
              end
            default:
                _092_ = _066_;
          endcase
        end
      default:
          _086_ = _066_;
    endcase
  end
  always @* begin
      x_addr_i <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _084_;
    (* src = "libresoc.v:162180.5-162180.29" *)
    casez (\initial )
      /* src = "libresoc.v:162180.9-162180.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _048_ = _073_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
          casez (\$31 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _073_ = 1'h1;
              end
            default:
                _073_ = 1'h0;
          endcase
        end
      default:
          _048_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _084_ = _090_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *)
          casez (ldst_port0_addr_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _090_ = _096_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *)
                casez (adrok_l_qn_addr_acked)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _096_ = 1'h1;
                    end
                  default:
                      _096_ = _048_;
                endcase
              end
            default:
                _090_ = _048_;
          endcase
        end
      default:
          _084_ = _048_;
    endcase
  end
  always @* begin
      ldst_port0_addr_ok_o <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _077_;
    (* src = "libresoc.v:162211.5-162211.29" *)
    casez (\initial )
      /* src = "libresoc.v:162211.9-162211.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
    casez (\$33 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _058_ = \$35 ;
        end
      default:
          _058_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:276" *)
    casez (st_done_q_st_done)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _077_ = \$37 ;
        end
      default:
          _077_ = _058_;
    endcase
  end
  always @* begin
      reset_l_s_reset <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = _057_;
    (* src = "libresoc.v:162227.5-162227.29" *)
    casez (\initial )
      /* src = "libresoc.v:162227.9-162227.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _057_ = 1'h1;
        end
      default:
          _057_ = 1'h0;
    endcase
  end
  always @* begin
      reset_l_r_reset <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _049_;
    (* src = "libresoc.v:162237.5-162237.29" *)
    casez (\initial )
      /* src = "libresoc.v:162237.9-162237.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
    casez (\$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _049_ = lddata;
        end
      default:
          _049_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      ldst_port0_ld_data_o <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _046_;
    (* src = "libresoc.v:162247.5-162247.29" *)
    casez (\initial )
      /* src = "libresoc.v:162247.9-162247.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _046_ = 1'h1;
        end
      default:
          _046_ = 1'h0;
    endcase
  end
  always @* begin
      ld_active_r_ld_active <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _050_;
    (* src = "libresoc.v:162257.5-162257.29" *)
    casez (\initial )
      /* src = "libresoc.v:162257.9-162257.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" *)
    casez (\$50 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _050_ = \$52 ;
        end
      default:
          _050_ = 1'h0;
    endcase
  end
  always @* begin
      ldst_port0_ld_data_o_ok <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = _063_;
    (* src = "libresoc.v:162267.5-162267.29" *)
    casez (\initial )
      /* src = "libresoc.v:162267.9-162267.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
    casez (\$54 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _063_ = \$56 [63:0];
        end
      default:
          _063_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      stdata <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _068_;
    (* src = "libresoc.v:162277.5-162277.29" *)
    casez (\initial )
      /* src = "libresoc.v:162277.9-162277.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" *)
    casez (\$61 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _068_ = stdata;
        end
      default:
          _068_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      x_st_data_i <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _055_;
    (* src = "libresoc.v:162287.5-162287.29" *)
    casez (\initial )
      /* src = "libresoc.v:162287.9-162287.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _055_ = _076_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
          casez (\$65 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _076_ = 1'h1;
              end
            default:
                _076_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _055_ = 1'h1;
        end
      default:
          _055_ = 1'h0;
    endcase
  end
  always @* begin
      lsui_busy <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _095_;
    (* src = "libresoc.v:162307.5-162307.29" *)
    casez (\initial )
      /* src = "libresoc.v:162307.9-162307.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _044_ = _072_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" *)
          casez (\$69 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _072_ = 2'h1;
              end
            default:
                _072_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _044_ = _083_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" *)
          casez (\$71 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _083_ = 2'h2;
              end
            default:
                _083_ = fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _044_ = _089_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" *)
          casez (\$77 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _089_ = 2'h0;
              end
            default:
                _089_ = fsm_state;
          endcase
        end
      default:
          _044_ = fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _095_ = 2'h0;
        end
      default:
          _095_ = _044_;
    endcase
  end
  always @* begin
      \fsm_state$next  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _043_;
    (* src = "libresoc.v:162346.5-162346.29" *)
    casez (\initial )
      /* src = "libresoc.v:162346.9-162346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:299" *)
    casez (reset_l_s_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _043_ = 1'h1;
        end
      default:
          _043_ = 1'h0;
    endcase
  end
  always @* begin
      cyc_l_s_cyc <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _053_;
    (* src = "libresoc.v:162356.5-162356.29" *)
    casez (\initial )
      /* src = "libresoc.v:162356.9-162356.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _053_ = 1'h0;
        end
      default:
          _053_ = lsui_active;
    endcase
  end
  always @* begin
      \lsui_active_dly$next  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _042_;
    (* src = "libresoc.v:162365.5-162365.29" *)
    casez (\initial )
      /* src = "libresoc.v:162365.9-162365.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *)
    casez (cyc_l_q_cyc)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _042_ = 1'h1;
        end
      default:
          _042_ = 1'h0;
    endcase
  end
  always @* begin
      cyc_l_r_cyc <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _041_;
    (* src = "libresoc.v:162375.5-162375.29" *)
    casez (\initial )
      /* src = "libresoc.v:162375.9-162375.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" *)
    casez (\$3 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _041_ = \$5 ;
        end
      default:
          _041_ = 1'h0;
    endcase
  end
  always @* begin
      busy_l_s_busy <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _071_;
    (* src = "libresoc.v:162385.5-162385.29" *)
    casez (\initial )
      /* src = "libresoc.v:162385.9-162385.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:294" *)
    casez (\ldst_port0_exc_$signal )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _040_ = 1'h1;
        end
      default:
          _040_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:302" *)
    casez (cyc_l_q_cyc)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _071_ = 1'h1;
        end
      default:
          _071_ = _040_;
    endcase
  end
  always @* begin
      busy_l_r_busy <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _097_;
    (* src = "libresoc.v:162401.5-162401.29" *)
    casez (\initial )
      /* src = "libresoc.v:162401.9-162401.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" *)
    casez (ld_active_q_ld_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _036_ = _070_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" *)
          casez (\$7 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _070_ = 1'h1;
              end
            default:
                _070_ = 1'h0;
          endcase
        end
      default:
          _036_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" *)
    casez (st_active_q_st_active)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _082_ = _088_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" *)
          casez (ldst_port0_addr_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _088_ = _094_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" *)
                casez (adrok_l_qn_addr_acked)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _094_ = 1'h1;
                    end
                  default:
                      _094_ = _036_;
                endcase
              end
            default:
                _088_ = _036_;
          endcase
        end
      default:
          _082_ = _036_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = 1'h0;
        end
      default:
          _097_ = _082_;
    endcase
  end
  always @* begin
      \adrok_l_s_addr_acked$next  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _069_;
    (* src = "libresoc.v:162437.5-162437.29" *)
    casez (\initial )
      /* src = "libresoc.v:162437.9-162437.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" *)
    casez (reset_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = 1'h1;
        end
      default:
          _035_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:286" *)
    casez (reset_l_q_reset)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _069_ = 1'h1;
        end
      default:
          _069_ = _035_;
    endcase
  end
  always @* begin
      adrok_l_r_addr_acked <= _000_;
  end
  assign \$9  = _121_;
  assign \$11  = _098_;
  assign \$13  = _122_;
  assign \$15  = _099_;
  assign \$17  = _123_;
  assign \$1  = _100_;
  assign \$19  = _101_;
  assign \$21  = _137_;
  assign \$23  = _138_;
  assign \$25  = _102_;
  assign \$27  = _103_;
  assign \$29  = _104_;
  assign \$31  = _105_;
  assign \$33  = _106_;
  assign \$35  = _124_;
  assign \$38  = _133_;
  assign \$3  = _134_;
  assign \$37  = _125_;
  assign \$42  = _107_;
  assign \$44  = _119_;
  assign \$46  = _140_;
  assign \$48  = _108_;
  assign \$50  = _109_;
  assign \$52  = _126_;
  assign \$54  = _110_;
  assign \$57  = _120_;
  assign \$5  = _127_;
  assign \$59  = _139_;
  assign \$61  = _111_;
  assign \$63  = _135_;
  assign \$65  = _112_;
  assign \$67  = _136_;
  assign \$69  = _113_;
  assign \$71  = _128_;
  assign \$73  = _129_;
  assign \$75  = _130_;
  assign \$77  = _114_;
  assign \$7  = _115_;
  assign \$79  = _131_;
  assign \$81  = _132_;
  assign \$83  = _116_;
  assign \$41  = \$46 ;
  assign \$56  = \$59 ;
  assign valid_l_r_valid = lsui_active_rise;
  assign lsui_active_rise = \$83 ;
  assign lsui_active = \$79 ;
  assign x_valid_i = valid_l_q_valid;
  assign m_valid_i = valid_l_q_valid;
  assign x_st_i = ldst_port0_is_st_i;
  assign x_ld_i = ldst_port0_is_ld_i;
  assign ldst_port0_busy_o = busy_l_q_busy;
  assign \reset_delay$next  = reset_l_q_reset;
  assign lddata = \$46 [63:0];
  assign st_active_s_st_active = sts_rise;
  assign sts_rise = \$19 ;
  assign \sts_dly$next  = sts;
  assign ld_active_s_ld_active = lds_rise;
  assign lds_rise = \$15 ;
  assign \lds_dly$next  = lds;
  assign busy_edge = \$11 ;
  assign sts = ldst_port0_is_st_i;
  assign lds = ldst_port0_is_ld_i;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:162477.1-163257.10" *)
module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, ra, rb, full_cr, cr_a, cr_b, cr_c, n_valid_o, n_ready_i, \muxid$1 , \cr_op__insn_type$2 , \cr_op__fn_unit$3 , \cr_op__insn$4 , o, o_ok, \full_cr$5 , full_cr_ok, \cr_a$6 , cr_a_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:163220.3-163238.6" *)
  reg [3:0] _00_;
  (* src = "libresoc.v:163084.3-163085.31" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:162491.13-162491.28" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:163220.3-163238.6" *)
  reg _03_;
  (* src = "libresoc.v:163086.3-163087.31" *)
  reg _04_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [13:0] _05_;
  (* src = "libresoc.v:163098.3-163099.51" *)
  reg [13:0] _06_;
  (* src = "libresoc.v:162556.14-162556.43" *)
  reg [13:0] _07_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [31:0] _08_;
  (* src = "libresoc.v:163100.3-163101.45" *)
  reg [31:0] _09_;
  (* src = "libresoc.v:162565.14-162565.37" *)
  reg [31:0] _10_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [6:0] _11_;
  (* src = "libresoc.v:163096.3-163097.55" *)
  reg [6:0] _12_;
  (* src = "libresoc.v:162799.13-162799.41" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:163201.3-163219.6" *)
  reg [31:0] _14_;
  (* src = "libresoc.v:163088.3-163089.37" *)
  reg [31:0] _15_;
  (* src = "libresoc.v:162808.14-162808.33" *)
  reg [31:0] _16_;
  (* src = "libresoc.v:163201.3-163219.6" *)
  reg _17_;
  (* src = "libresoc.v:163090.3-163091.37" *)
  reg _18_;
  (* src = "libresoc.v:162478.7-162478.20" *)
  reg _19_;
  (* src = "libresoc.v:163154.3-163166.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:163102.3-163103.33" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:163042.13-163042.29" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:163182.3-163200.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:163092.3-163093.19" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:163182.3-163200.6" *)
  reg _25_;
  (* src = "libresoc.v:163094.3-163095.25" *)
  reg _26_;
  (* src = "libresoc.v:163136.3-163153.6" *)
  reg _27_;
  (* src = "libresoc.v:163104.3-163105.29" *)
  reg _28_;
  (* src = "libresoc.v:163220.3-163238.6" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:163220.3-163238.6" *)
  reg _30_;
  (* src = "libresoc.v:162496.7-162496.21" *)
  reg _31_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [13:0] _32_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [31:0] _33_;
  (* src = "libresoc.v:163167.3-163181.6" *)
  reg [6:0] _34_;
  (* src = "libresoc.v:163201.3-163219.6" *)
  reg [31:0] _35_;
  (* src = "libresoc.v:163201.3-163219.6" *)
  reg _36_;
  (* src = "libresoc.v:162813.7-162813.24" *)
  reg _37_;
  (* src = "libresoc.v:163154.3-163166.6" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:163182.3-163200.6" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:163055.14-163055.38" *)
  reg [63:0] _40_;
  (* src = "libresoc.v:163182.3-163200.6" *)
  reg _41_;
  (* src = "libresoc.v:163062.7-163062.18" *)
  reg _42_;
  (* src = "libresoc.v:163136.3-163153.6" *)
  reg _43_;
  (* src = "libresoc.v:163076.7-163076.20" *)
  reg _44_;
  (* src = "libresoc.v:163220.3-163238.6" *)
  reg _45_;
  (* src = "libresoc.v:163201.3-163219.6" *)
  reg _46_;
  (* src = "libresoc.v:163182.3-163200.6" *)
  reg _47_;
  (* src = "libresoc.v:163136.3-163153.6" *)
  reg _48_;
  (* src = "libresoc.v:163083.18-163083.118" *)
  wire _49_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$6 ;
  reg [3:0] \cr_a$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] cr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \cr_op__fn_unit$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \cr_op__fn_unit$3 ;
  reg [13:0] \cr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \cr_op__fn_unit$3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \cr_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \cr_op__insn$4 ;
  reg [31:0] \cr_op__insn$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \cr_op__insn$4$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] cr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \cr_op__insn_type$17 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \cr_op__insn_type$2 ;
  reg [6:0] \cr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \cr_op__insn_type$2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [31:0] full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [31:0] \full_cr$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [31:0] \full_cr$5 ;
  reg [31:0] \full_cr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [31:0] \full_cr$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output full_cr_ok;
  reg full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \full_cr_ok$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \full_cr_ok$next ;
  (* src = "libresoc.v:162478.7-162478.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] main_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \main_cr_a$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] main_cr_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] main_cr_c;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_cr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_cr_op__fn_unit$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_cr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_cr_op__insn$10 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_cr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_cr_op__insn_type$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [31:0] main_full_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [31:0] \main_full_cr$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_full_cr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rb;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  assign _49_ = \p_valid_i$13  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163106.12-163127.4" *)
  \main$9  main (
    .cr_a(main_cr_a),
    .\cr_a$6 (\main_cr_a$12 ),
    .cr_a_ok(main_cr_a_ok),
    .cr_b(main_cr_b),
    .cr_c(main_cr_c),
    .cr_op__fn_unit(main_cr_op__fn_unit),
    .\cr_op__fn_unit$3 (\main_cr_op__fn_unit$9 ),
    .cr_op__insn(main_cr_op__insn),
    .\cr_op__insn$4 (\main_cr_op__insn$10 ),
    .cr_op__insn_type(main_cr_op__insn_type),
    .\cr_op__insn_type$2 (\main_cr_op__insn_type$8 ),
    .full_cr(main_full_cr),
    .\full_cr$5 (\main_full_cr$11 ),
    .full_cr_ok(main_full_cr_ok),
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$7 ),
    .o(main_o),
    .o_ok(main_o_ok),
    .ra(main_ra),
    .rb(main_rb)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163128.9-163131.4" *)
  \n$8  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163132.9-163135.4" *)
  \p$7  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _19_ = 1'h0;
  end
  always @* begin
      \initial  <= _19_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a$6  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \cr_op__fn_unit$3  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \cr_op__insn$4  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \cr_op__insn_type$2  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \full_cr$5  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _37_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      full_cr_ok <= _37_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _40_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _40_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \cr_a$6$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a$6  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = \full_cr$5$next ;
  end
  always @(posedge coresync_clk) begin
      \full_cr$5  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = \full_cr_ok$next ;
  end
  always @(posedge coresync_clk) begin
      full_cr_ok <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \cr_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_op__insn_type$2  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \cr_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_op__fn_unit$3  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = \cr_op__insn$4$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_op__insn$4  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = _48_;
    (* src = "libresoc.v:163137.5-163137.29" *)
    casez (\initial )
      /* src = "libresoc.v:163137.9-163137.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _43_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _43_ = 1'h0;
        end
      default:
          _43_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = 1'h0;
        end
      default:
          _48_ = _43_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _38_;
    (* src = "libresoc.v:163155.5-163155.29" *)
    casez (\initial )
      /* src = "libresoc.v:163155.9-163155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _38_ = \muxid$16 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _38_ = \muxid$16 ;
        end
      default:
          _38_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _32_;
    _08_ = _33_;
    _11_ = _34_;
    (* src = "libresoc.v:163168.5-163168.29" *)
    casez (\initial )
      /* src = "libresoc.v:163168.9-163168.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _33_, _32_, _34_ } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _33_, _32_, _34_ } = { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17  };
        end
      default:
        begin
          _32_ = \cr_op__fn_unit$3 ;
          _33_ = \cr_op__insn$4 ;
          _34_ = \cr_op__insn_type$2 ;
        end
    endcase
  end
  always @* begin
      \cr_op__fn_unit$3$next  <= _05_;
      \cr_op__insn$4$next  <= _08_;
      \cr_op__insn_type$2$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = _39_;
    _25_ = _47_;
    (* src = "libresoc.v:163183.5-163183.29" *)
    casez (\initial )
      /* src = "libresoc.v:163183.9-163183.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _41_, _39_ } = { \o_ok$21 , \o$20  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _41_, _39_ } = { \o_ok$21 , \o$20  };
        end
      default:
        begin
          _39_ = o;
          _41_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _47_ = 1'h0;
        end
      default:
          _47_ = _41_;
    endcase
  end
  always @* begin
      \o$next  <= _23_;
      \o_ok$next  <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _35_;
    _17_ = _46_;
    (* src = "libresoc.v:163202.5-163202.29" *)
    casez (\initial )
      /* src = "libresoc.v:163202.9-163202.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _36_, _35_ } = { \full_cr_ok$23 , \full_cr$22  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _36_, _35_ } = { \full_cr_ok$23 , \full_cr$22  };
        end
      default:
        begin
          _35_ = \full_cr$5 ;
          _36_ = full_cr_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _46_ = 1'h0;
        end
      default:
          _46_ = _36_;
    endcase
  end
  always @* begin
      \full_cr$5$next  <= _14_;
      \full_cr_ok$next  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _29_;
    _03_ = _45_;
    (* src = "libresoc.v:163221.5-163221.29" *)
    casez (\initial )
      /* src = "libresoc.v:163221.9-163221.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _30_, _29_ } = { \cr_a_ok$25 , \cr_a$24  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _30_, _29_ } = { \cr_a_ok$25 , \cr_a$24  };
        end
      default:
        begin
          _30_ = cr_a_ok;
          _29_ = \cr_a$6 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _45_ = 1'h0;
        end
      default:
          _45_ = _30_;
    endcase
  end
  always @* begin
      \cr_a_ok$next  <= _03_;
      \cr_a$6$next  <= _00_;
  end
  assign \$14  = _49_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \cr_a_ok$25 , \cr_a$24  } = { main_cr_a_ok, \main_cr_a$12  };
  assign { \full_cr_ok$23 , \full_cr$22  } = { main_full_cr_ok, \main_full_cr$11  };
  assign { \o_ok$21 , \o$20  } = { main_o_ok, main_o };
  assign { \cr_op__insn$19 , \cr_op__fn_unit$18 , \cr_op__insn_type$17  } = { \main_cr_op__insn$10 , \main_cr_op__fn_unit$9 , \main_cr_op__insn_type$8  };
  assign \muxid$16  = \main_muxid$7 ;
  assign p_valid_i_p_ready_o = \$14 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$13  = p_valid_i;
  assign main_cr_c = cr_c;
  assign main_cr_b = cr_b;
  assign main_cr_a = cr_a;
  assign main_full_cr = full_cr;
  assign main_rb = rb;
  assign main_ra = ra;
  assign { main_cr_op__insn, main_cr_op__fn_unit, main_cr_op__insn_type } = { cr_op__insn, cr_op__fn_unit, cr_op__insn_type };
  assign main_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:163261.1-164121.10" *)
module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__insn_type, br_op__fn_unit, br_op__insn, br_op__imm_data__data, br_op__imm_data__ok, br_op__lk, br_op__is_32bit, fast1, fast2, cr_a, n_valid_o, n_ready_i, \muxid$1 , \br_op__cia$2 , \br_op__insn_type$3 , \br_op__fn_unit$4 , \br_op__insn$5 , \br_op__imm_data__data$6 , \br_op__imm_data__ok$7 , \br_op__lk$8 , \br_op__is_32bit$9 , \fast1$10 , fast1_ok, \fast2$11 , fast2_ok, nia, nia_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:163933.3-163934.43" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:163269.14-163269.51" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [13:0] _03_;
  (* src = "libresoc.v:163937.3-163938.51" *)
  reg [13:0] _04_;
  (* src = "libresoc.v:163325.14-163325.43" *)
  reg [13:0] _05_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:163941.3-163942.65" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:163334.14-163334.62" *)
  reg [63:0] _08_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _09_;
  (* src = "libresoc.v:163943.3-163944.61" *)
  reg _10_;
  (* src = "libresoc.v:163343.7-163343.37" *)
  reg _11_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [31:0] _12_;
  (* src = "libresoc.v:163939.3-163940.45" *)
  reg [31:0] _13_;
  (* src = "libresoc.v:163352.14-163352.37" *)
  reg [31:0] _14_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [6:0] _15_;
  (* src = "libresoc.v:163935.3-163936.55" *)
  reg [6:0] _16_;
  (* src = "libresoc.v:163586.13-163586.41" *)
  reg [6:0] _17_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _18_;
  (* src = "libresoc.v:163947.3-163948.53" *)
  reg _19_;
  (* src = "libresoc.v:163595.7-163595.33" *)
  reg _20_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _21_;
  (* src = "libresoc.v:163945.3-163946.41" *)
  reg _22_;
  (* src = "libresoc.v:163604.7-163604.27" *)
  reg _23_;
  (* src = "libresoc.v:164049.3-164067.6" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:163929.3-163930.35" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:163617.14-163617.47" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:164049.3-164067.6" *)
  reg _27_;
  (* src = "libresoc.v:163931.3-163932.33" *)
  reg _28_;
  (* src = "libresoc.v:164068.3-164086.6" *)
  reg [63:0] _29_;
  (* src = "libresoc.v:163925.3-163926.35" *)
  reg [63:0] _30_;
  (* src = "libresoc.v:163633.14-163633.47" *)
  reg [63:0] _31_;
  (* src = "libresoc.v:164068.3-164086.6" *)
  reg _32_;
  (* src = "libresoc.v:163927.3-163928.33" *)
  reg _33_;
  (* src = "libresoc.v:163262.7-163262.20" *)
  reg _34_;
  (* src = "libresoc.v:164008.3-164020.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:163949.3-163950.33" *)
  reg [1:0] _36_;
  (* src = "libresoc.v:163883.13-163883.29" *)
  reg [1:0] _37_;
  (* src = "libresoc.v:164087.3-164105.6" *)
  reg [63:0] _38_;
  (* src = "libresoc.v:163921.3-163922.23" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:164087.3-164105.6" *)
  reg _40_;
  (* src = "libresoc.v:163923.3-163924.29" *)
  reg _41_;
  (* src = "libresoc.v:163990.3-164007.6" *)
  reg _42_;
  (* src = "libresoc.v:163951.3-163952.29" *)
  reg _43_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [63:0] _44_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [13:0] _45_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [63:0] _46_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _47_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [31:0] _48_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [6:0] _49_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _50_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _51_;
  (* src = "libresoc.v:164049.3-164067.6" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:164049.3-164067.6" *)
  reg _53_;
  (* src = "libresoc.v:163624.7-163624.22" *)
  reg _54_;
  (* src = "libresoc.v:164068.3-164086.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:164068.3-164086.6" *)
  reg _56_;
  (* src = "libresoc.v:163640.7-163640.22" *)
  reg _57_;
  (* src = "libresoc.v:164008.3-164020.6" *)
  reg [1:0] _58_;
  (* src = "libresoc.v:164087.3-164105.6" *)
  reg [63:0] _59_;
  (* src = "libresoc.v:163896.14-163896.40" *)
  reg [63:0] _60_;
  (* src = "libresoc.v:164087.3-164105.6" *)
  reg _61_;
  (* src = "libresoc.v:163903.7-163903.20" *)
  reg _62_;
  (* src = "libresoc.v:163990.3-164007.6" *)
  reg _63_;
  (* src = "libresoc.v:163917.7-163917.20" *)
  reg _64_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg [63:0] _65_;
  (* src = "libresoc.v:164021.3-164048.6" *)
  reg _66_;
  (* src = "libresoc.v:164049.3-164067.6" *)
  reg _67_;
  (* src = "libresoc.v:164068.3-164086.6" *)
  reg _68_;
  (* src = "libresoc.v:164087.3-164105.6" *)
  reg _69_;
  (* src = "libresoc.v:163990.3-164007.6" *)
  reg _70_;
  (* src = "libresoc.v:163920.18-163920.118" *)
  wire _71_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \br_op__cia$2 ;
  reg [63:0] \br_op__cia$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \br_op__cia$2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \br_op__cia$27 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] br_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \br_op__fn_unit$29 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \br_op__fn_unit$4 ;
  reg [13:0] \br_op__fn_unit$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \br_op__fn_unit$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \br_op__imm_data__data$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \br_op__imm_data__data$6 ;
  reg [63:0] \br_op__imm_data__data$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \br_op__imm_data__data$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__imm_data__ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__imm_data__ok$7 ;
  reg \br_op__imm_data__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \br_op__imm_data__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \br_op__insn$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \br_op__insn$5 ;
  reg [31:0] \br_op__insn$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \br_op__insn$5$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] br_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \br_op__insn_type$28 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \br_op__insn_type$3 ;
  reg [6:0] \br_op__insn_type$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \br_op__insn_type$3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__is_32bit$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__is_32bit$9 ;
  reg \br_op__is_32bit$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \br_op__is_32bit$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \br_op__lk$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \br_op__lk$8 ;
  reg \br_op__lk$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \br_op__lk$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$10 ;
  reg [63:0] \fast1$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \fast1$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \fast1$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fast1_ok$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast2$11 ;
  reg [63:0] \fast2$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \fast2$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \fast2$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  reg fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fast2_ok$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \fast2_ok$next ;
  (* src = "libresoc.v:163262.7-163262.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_br_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_br_op__cia$13 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_br_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_br_op__fn_unit$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_br_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_br_op__imm_data__data$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_br_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_br_op__imm_data__ok$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_br_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_br_op__insn$16 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_br_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_br_op__insn_type$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_br_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_br_op__is_32bit$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_br_op__lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_br_op__lk$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [3:0] main_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \main_fast1$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \main_fast2$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_nia_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$26 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  reg [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \nia$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \nia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  reg nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \nia_ok$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \nia_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  assign _71_ = \p_valid_i$23  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163953.13-163981.4" *)
  \main$22  main (
    .br_op__cia(main_br_op__cia),
    .\br_op__cia$2 (\main_br_op__cia$13 ),
    .br_op__fn_unit(main_br_op__fn_unit),
    .\br_op__fn_unit$4 (\main_br_op__fn_unit$15 ),
    .br_op__imm_data__data(main_br_op__imm_data__data),
    .\br_op__imm_data__data$6 (\main_br_op__imm_data__data$17 ),
    .br_op__imm_data__ok(main_br_op__imm_data__ok),
    .\br_op__imm_data__ok$7 (\main_br_op__imm_data__ok$18 ),
    .br_op__insn(main_br_op__insn),
    .\br_op__insn$5 (\main_br_op__insn$16 ),
    .br_op__insn_type(main_br_op__insn_type),
    .\br_op__insn_type$3 (\main_br_op__insn_type$14 ),
    .br_op__is_32bit(main_br_op__is_32bit),
    .\br_op__is_32bit$9 (\main_br_op__is_32bit$20 ),
    .br_op__lk(main_br_op__lk),
    .\br_op__lk$8 (\main_br_op__lk$19 ),
    .cr_a(main_cr_a),
    .fast1(main_fast1),
    .\fast1$10 (\main_fast1$21 ),
    .fast1_ok(main_fast1_ok),
    .fast2(main_fast2),
    .\fast2$11 (\main_fast2$22 ),
    .fast2_ok(main_fast2_ok),
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$12 ),
    .nia(main_nia),
    .nia_ok(main_nia_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163982.10-163985.4" *)
  \n$21  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:163986.10-163989.4" *)
  \p$20  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _34_ = 1'h0;
  end
  always @* begin
      \initial  <= _34_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \br_op__cia$2  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \br_op__fn_unit$4  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \br_op__imm_data__data$6  <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \br_op__imm_data__ok$7  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \br_op__insn$5  <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \br_op__insn_type$3  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \br_op__is_32bit$9  <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \br_op__lk$8  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \fast1$10  <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _54_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      fast1_ok <= _54_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \fast2$11  <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _57_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      fast2_ok <= _57_;
  end
  always @* begin
    if (\initial ) begin end
    _37_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _37_;
  end
  always @* begin
    if (\initial ) begin end
    _60_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      nia <= _60_;
  end
  always @* begin
    if (\initial ) begin end
    _62_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      nia_ok <= _62_;
  end
  always @* begin
    if (\initial ) begin end
    _64_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _64_;
  end
  always @* begin
    if (\initial ) begin end
    _39_ = \nia$next ;
  end
  always @(posedge coresync_clk) begin
      nia <= _39_;
  end
  always @* begin
    if (\initial ) begin end
    _41_ = \nia_ok$next ;
  end
  always @(posedge coresync_clk) begin
      nia_ok <= _41_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = \fast2$11$next ;
  end
  always @(posedge coresync_clk) begin
      \fast2$11  <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = \fast2_ok$next ;
  end
  always @(posedge coresync_clk) begin
      fast2_ok <= _33_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = \fast1$10$next ;
  end
  always @(posedge coresync_clk) begin
      \fast1$10  <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = \fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      fast1_ok <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \br_op__cia$2$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__cia$2  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \br_op__insn_type$3$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__insn_type$3  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \br_op__fn_unit$4$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__fn_unit$4  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = \br_op__insn$5$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__insn$5  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = \br_op__imm_data__data$6$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__imm_data__data$6  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \br_op__imm_data__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__imm_data__ok$7  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = \br_op__lk$8$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__lk$8  <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = \br_op__is_32bit$9$next ;
  end
  always @(posedge coresync_clk) begin
      \br_op__is_32bit$9  <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _43_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _43_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = _70_;
    (* src = "libresoc.v:163991.5-163991.29" *)
    casez (\initial )
      /* src = "libresoc.v:163991.9-163991.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _63_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _63_ = 1'h0;
        end
      default:
          _63_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _70_ = 1'h0;
        end
      default:
          _70_ = _63_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _35_ = _58_;
    (* src = "libresoc.v:164009.5-164009.29" *)
    casez (\initial )
      /* src = "libresoc.v:164009.9-164009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _58_ = \muxid$26 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _58_ = \muxid$26 ;
        end
      default:
          _58_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _35_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _44_;
    _03_ = _45_;
    _12_ = _48_;
    _15_ = _49_;
    _18_ = _50_;
    _21_ = _51_;
    _06_ = _65_;
    _09_ = _66_;
    (* src = "libresoc.v:164022.5-164022.29" *)
    casez (\initial )
      /* src = "libresoc.v:164022.9-164022.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _50_, _51_, _47_, _46_, _48_, _45_, _49_, _44_ } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _50_, _51_, _47_, _46_, _48_, _45_, _49_, _44_ } = { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27  };
        end
      default:
        begin
          _44_ = \br_op__cia$2 ;
          _45_ = \br_op__fn_unit$4 ;
          _46_ = \br_op__imm_data__data$6 ;
          _47_ = \br_op__imm_data__ok$7 ;
          _48_ = \br_op__insn$5 ;
          _49_ = \br_op__insn_type$3 ;
          _50_ = \br_op__is_32bit$9 ;
          _51_ = \br_op__lk$8 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _65_ = 64'h0000000000000000;
          _66_ = 1'h0;
        end
      default:
        begin
          _65_ = _46_;
          _66_ = _47_;
        end
    endcase
  end
  always @* begin
      \br_op__cia$2$next  <= _00_;
      \br_op__fn_unit$4$next  <= _03_;
      \br_op__imm_data__data$6$next  <= _06_;
      \br_op__imm_data__ok$7$next  <= _09_;
      \br_op__insn$5$next  <= _12_;
      \br_op__insn_type$3$next  <= _15_;
      \br_op__is_32bit$9$next  <= _18_;
      \br_op__lk$8$next  <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = _52_;
    _27_ = _67_;
    (* src = "libresoc.v:164050.5-164050.29" *)
    casez (\initial )
      /* src = "libresoc.v:164050.9-164050.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _53_, _52_ } = { \fast1_ok$36 , \fast1$35  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _53_, _52_ } = { \fast1_ok$36 , \fast1$35  };
        end
      default:
        begin
          _52_ = \fast1$10 ;
          _53_ = fast1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _67_ = 1'h0;
        end
      default:
          _67_ = _53_;
    endcase
  end
  always @* begin
      \fast1$10$next  <= _24_;
      \fast1_ok$next  <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = _55_;
    _32_ = _68_;
    (* src = "libresoc.v:164069.5-164069.29" *)
    casez (\initial )
      /* src = "libresoc.v:164069.9-164069.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _56_, _55_ } = { \fast2_ok$38 , \fast2$37  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _56_, _55_ } = { \fast2_ok$38 , \fast2$37  };
        end
      default:
        begin
          _55_ = \fast2$11 ;
          _56_ = fast2_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _68_ = 1'h0;
        end
      default:
          _68_ = _56_;
    endcase
  end
  always @* begin
      \fast2$11$next  <= _29_;
      \fast2_ok$next  <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = _59_;
    _40_ = _69_;
    (* src = "libresoc.v:164088.5-164088.29" *)
    casez (\initial )
      /* src = "libresoc.v:164088.9-164088.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _61_, _59_ } = { \nia_ok$40 , \nia$39  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _61_, _59_ } = { \nia_ok$40 , \nia$39  };
        end
      default:
        begin
          _59_ = nia;
          _61_ = nia_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _69_ = 1'h0;
        end
      default:
          _69_ = _61_;
    endcase
  end
  always @* begin
      \nia$next  <= _38_;
      \nia_ok$next  <= _40_;
  end
  assign \$24  = _71_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \nia_ok$40 , \nia$39  } = { main_nia_ok, main_nia };
  assign { \fast2_ok$38 , \fast2$37  } = { main_fast2_ok, \main_fast2$22  };
  assign { \fast1_ok$36 , \fast1$35  } = { main_fast1_ok, \main_fast1$21  };
  assign { \br_op__is_32bit$34 , \br_op__lk$33 , \br_op__imm_data__ok$32 , \br_op__imm_data__data$31 , \br_op__insn$30 , \br_op__fn_unit$29 , \br_op__insn_type$28 , \br_op__cia$27  } = { \main_br_op__is_32bit$20 , \main_br_op__lk$19 , \main_br_op__imm_data__ok$18 , \main_br_op__imm_data__data$17 , \main_br_op__insn$16 , \main_br_op__fn_unit$15 , \main_br_op__insn_type$14 , \main_br_op__cia$13  };
  assign \muxid$26  = \main_muxid$12 ;
  assign p_valid_i_p_ready_o = \$24 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$23  = p_valid_i;
  assign main_cr_a = cr_a;
  assign main_fast2 = fast2;
  assign main_fast1 = fast1;
  assign { main_br_op__is_32bit, main_br_op__lk, main_br_op__imm_data__ok, main_br_op__imm_data__data, main_br_op__insn, main_br_op__fn_unit, main_br_op__insn_type, main_br_op__cia } = { br_op__is_32bit, br_op__lk, br_op__imm_data__ok, br_op__imm_data__data, br_op__insn, br_op__fn_unit, br_op__insn_type, br_op__cia };
  assign main_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:164125.1-165055.10" *)
module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, n_valid_o, n_ready_i, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:164958.3-164976.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:164811.3-164812.33" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:164139.14-164139.46" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:164958.3-164976.6" *)
  reg _03_;
  (* src = "libresoc.v:164813.3-164814.33" *)
  reg _04_;
  (* src = "libresoc.v:164126.7-164126.20" *)
  reg _05_;
  (* src = "libresoc.v:164891.3-164903.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:164831.3-164832.33" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:164153.13-164153.29" *)
  reg [1:0] _08_;
  (* src = "libresoc.v:164920.3-164938.6" *)
  reg [63:0] _09_;
  (* src = "libresoc.v:164819.3-164820.19" *)
  reg [63:0] _10_;
  (* src = "libresoc.v:164920.3-164938.6" *)
  reg _11_;
  (* src = "libresoc.v:164821.3-164822.25" *)
  reg _12_;
  (* src = "libresoc.v:164873.3-164890.6" *)
  reg _13_;
  (* src = "libresoc.v:164833.3-164834.29" *)
  reg _14_;
  (* src = "libresoc.v:164939.3-164957.6" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:164815.3-164816.31" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:164198.14-164198.45" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:164939.3-164957.6" *)
  reg _18_;
  (* src = "libresoc.v:164817.3-164818.31" *)
  reg _19_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [13:0] _20_;
  (* src = "libresoc.v:164825.3-164826.53" *)
  reg [13:0] _21_;
  (* src = "libresoc.v:164495.14-164495.44" *)
  reg [13:0] _22_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [31:0] _23_;
  (* src = "libresoc.v:164827.3-164828.47" *)
  reg [31:0] _24_;
  (* src = "libresoc.v:164504.14-164504.38" *)
  reg [31:0] _25_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [6:0] _26_;
  (* src = "libresoc.v:164823.3-164824.57" *)
  reg [6:0] _27_;
  (* src = "libresoc.v:164661.13-164661.42" *)
  reg [6:0] _28_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg _29_;
  (* src = "libresoc.v:164829.3-164830.55" *)
  reg _30_;
  (* src = "libresoc.v:164747.7-164747.34" *)
  reg _31_;
  (* src = "libresoc.v:165015.3-165033.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:164799.3-164800.37" *)
  reg [1:0] _33_;
  (* src = "libresoc.v:164754.13-164754.31" *)
  reg [1:0] _34_;
  (* src = "libresoc.v:165015.3-165033.6" *)
  reg _35_;
  (* src = "libresoc.v:164801.3-164802.35" *)
  reg _36_;
  (* src = "libresoc.v:164996.3-165014.6" *)
  reg [1:0] _37_;
  (* src = "libresoc.v:164803.3-164804.35" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:164772.13-164772.30" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:164996.3-165014.6" *)
  reg _40_;
  (* src = "libresoc.v:164805.3-164806.35" *)
  reg _41_;
  (* src = "libresoc.v:164977.3-164995.6" *)
  reg _42_;
  (* src = "libresoc.v:164807.3-164808.35" *)
  reg _43_;
  (* src = "libresoc.v:164788.7-164788.24" *)
  reg _44_;
  (* src = "libresoc.v:164977.3-164995.6" *)
  reg _45_;
  (* src = "libresoc.v:164809.3-164810.35" *)
  reg _46_;
  (* src = "libresoc.v:164958.3-164976.6" *)
  reg [63:0] _47_;
  (* src = "libresoc.v:164958.3-164976.6" *)
  reg _48_;
  (* src = "libresoc.v:164144.7-164144.22" *)
  reg _49_;
  (* src = "libresoc.v:164891.3-164903.6" *)
  reg [1:0] _50_;
  (* src = "libresoc.v:164920.3-164938.6" *)
  reg [63:0] _51_;
  (* src = "libresoc.v:164166.14-164166.38" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:164920.3-164938.6" *)
  reg _53_;
  (* src = "libresoc.v:164173.7-164173.18" *)
  reg _54_;
  (* src = "libresoc.v:164873.3-164890.6" *)
  reg _55_;
  (* src = "libresoc.v:164187.7-164187.20" *)
  reg _56_;
  (* src = "libresoc.v:164939.3-164957.6" *)
  reg [63:0] _57_;
  (* src = "libresoc.v:164939.3-164957.6" *)
  reg _58_;
  (* src = "libresoc.v:164203.7-164203.21" *)
  reg _59_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [13:0] _60_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [31:0] _61_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg [6:0] _62_;
  (* src = "libresoc.v:164904.3-164919.6" *)
  reg _63_;
  (* src = "libresoc.v:165015.3-165033.6" *)
  reg [1:0] _64_;
  (* src = "libresoc.v:165015.3-165033.6" *)
  reg _65_;
  (* src = "libresoc.v:164761.7-164761.23" *)
  reg _66_;
  (* src = "libresoc.v:164996.3-165014.6" *)
  reg [1:0] _67_;
  (* src = "libresoc.v:164996.3-165014.6" *)
  reg _68_;
  (* src = "libresoc.v:164777.7-164777.23" *)
  reg _69_;
  (* src = "libresoc.v:164977.3-164995.6" *)
  reg _70_;
  (* src = "libresoc.v:164977.3-164995.6" *)
  reg _71_;
  (* src = "libresoc.v:164793.7-164793.23" *)
  reg _72_;
  (* src = "libresoc.v:164958.3-164976.6" *)
  reg _73_;
  (* src = "libresoc.v:164920.3-164938.6" *)
  reg _74_;
  (* src = "libresoc.v:164873.3-164890.6" *)
  reg _75_;
  (* src = "libresoc.v:164939.3-164957.6" *)
  reg _76_;
  (* src = "libresoc.v:165015.3-165033.6" *)
  reg _77_;
  (* src = "libresoc.v:164996.3-165014.6" *)
  reg _78_;
  (* src = "libresoc.v:164977.3-164995.6" *)
  reg _79_;
  (* src = "libresoc.v:164798.18-164798.118" *)
  wire _80_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \fast1$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$7 ;
  reg [63:0] \fast1$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \fast1$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fast1_ok$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \fast1_ok$next ;
  (* src = "libresoc.v:164126.7-164126.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \spr1$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \spr1$6 ;
  reg [63:0] \spr1$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \spr1$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  reg spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \spr1_ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \spr1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] spr_main_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \spr_main_fast1$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] spr_main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \spr_main_muxid$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] spr_main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] spr_main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] spr_main_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \spr_main_spr1$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_spr1_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] spr_main_spr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \spr_main_spr_op__fn_unit$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] spr_main_spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \spr_main_spr_op__insn$14 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] spr_main_spr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \spr_main_spr_op__insn_type$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire spr_main_spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \spr_main_spr_op__is_32bit$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] spr_main_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \spr_main_xer_ca$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] spr_main_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \spr_main_xer_ov$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire spr_main_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \spr_main_xer_so$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire spr_main_xer_so_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] spr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \spr_op__fn_unit$26 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \spr_op__fn_unit$3 ;
  reg [13:0] \spr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \spr_op__fn_unit$3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \spr_op__insn$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \spr_op__insn$4 ;
  reg [31:0] \spr_op__insn$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \spr_op__insn$4$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] spr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \spr_op__insn_type$2 ;
  reg [6:0] \spr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \spr_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \spr_op__insn_type$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \spr_op__is_32bit$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \spr_op__is_32bit$5 ;
  reg \spr_op__is_32bit$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \spr_op__is_32bit$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$10 ;
  reg [1:0] \xer_ca$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ca$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ca$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  reg xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ov$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$9 ;
  reg [1:0] \xer_ov$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ov$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$8 ;
  reg \xer_so$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _80_ = \p_valid_i$21  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:164835.10-164838.4" *)
  \n$66  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:164839.10-164842.4" *)
  \p$65  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:164843.12-164872.4" *)
  spr_main spr_main (
    .fast1(spr_main_fast1),
    .\fast1$7 (\spr_main_fast1$17 ),
    .fast1_ok(spr_main_fast1_ok),
    .muxid(spr_main_muxid),
    .\muxid$1 (\spr_main_muxid$11 ),
    .o(spr_main_o),
    .o_ok(spr_main_o_ok),
    .ra(spr_main_ra),
    .spr1(spr_main_spr1),
    .\spr1$6 (\spr_main_spr1$16 ),
    .spr1_ok(spr_main_spr1_ok),
    .spr_op__fn_unit(spr_main_spr_op__fn_unit),
    .\spr_op__fn_unit$3 (\spr_main_spr_op__fn_unit$13 ),
    .spr_op__insn(spr_main_spr_op__insn),
    .\spr_op__insn$4 (\spr_main_spr_op__insn$14 ),
    .spr_op__insn_type(spr_main_spr_op__insn_type),
    .\spr_op__insn_type$2 (\spr_main_spr_op__insn_type$12 ),
    .spr_op__is_32bit(spr_main_spr_op__is_32bit),
    .\spr_op__is_32bit$5 (\spr_main_spr_op__is_32bit$15 ),
    .xer_ca(spr_main_xer_ca),
    .\xer_ca$10 (\spr_main_xer_ca$20 ),
    .xer_ca_ok(spr_main_xer_ca_ok),
    .xer_ov(spr_main_xer_ov),
    .\xer_ov$9 (\spr_main_xer_ov$19 ),
    .xer_ov_ok(spr_main_xer_ov_ok),
    .xer_so(spr_main_xer_so),
    .\xer_so$8 (\spr_main_xer_so$18 ),
    .xer_so_ok(spr_main_xer_so_ok)
  );
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \fast1$7  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _49_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      fast1_ok <= _49_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _52_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _52_;
  end
  always @* begin
    if (\initial ) begin end
    _54_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _54_;
  end
  always @* begin
    if (\initial ) begin end
    _56_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _56_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \spr1$6  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _59_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      spr1_ok <= _59_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \spr_op__fn_unit$3  <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \spr_op__insn$4  <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \spr_op__insn_type$2  <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \spr_op__is_32bit$5  <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _34_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ca$10  <= _34_;
  end
  always @* begin
    if (\initial ) begin end
    _66_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ca_ok <= _66_;
  end
  always @* begin
    if (\initial ) begin end
    _39_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ov$9  <= _39_;
  end
  always @* begin
    if (\initial ) begin end
    _69_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov_ok <= _69_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$8  <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _72_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _72_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = \xer_ca$10$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ca$10  <= _33_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = \xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ca_ok <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = \xer_ov$9$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ov$9  <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _41_ = \xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov_ok <= _41_;
  end
  always @* begin
    if (\initial ) begin end
    _43_ = \xer_so$8$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$8  <= _43_;
  end
  always @* begin
    if (\initial ) begin end
    _46_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _46_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \fast1$7$next ;
  end
  always @(posedge coresync_clk) begin
      \fast1$7  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      fast1_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \spr1$6$next ;
  end
  always @(posedge coresync_clk) begin
      \spr1$6  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = \spr1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      spr1_ok <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = \spr_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \spr_op__insn_type$2  <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = \spr_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \spr_op__fn_unit$3  <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = \spr_op__insn$4$next ;
  end
  always @(posedge coresync_clk) begin
      \spr_op__insn$4  <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = \spr_op__is_32bit$5$next ;
  end
  always @(posedge coresync_clk) begin
      \spr_op__is_32bit$5  <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _75_;
    (* src = "libresoc.v:164874.5-164874.29" *)
    casez (\initial )
      /* src = "libresoc.v:164874.9-164874.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _55_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _55_ = 1'h0;
        end
      default:
          _55_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 1'h0;
        end
      default:
          _75_ = _55_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _50_;
    (* src = "libresoc.v:164892.5-164892.29" *)
    casez (\initial )
      /* src = "libresoc.v:164892.9-164892.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _50_ = \muxid$24 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _50_ = \muxid$24 ;
        end
      default:
          _50_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = _60_;
    _23_ = _61_;
    _26_ = _62_;
    _29_ = _63_;
    (* src = "libresoc.v:164905.5-164905.29" *)
    casez (\initial )
      /* src = "libresoc.v:164905.9-164905.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _63_, _61_, _60_, _62_ } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _63_, _61_, _60_, _62_ } = { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25  };
        end
      default:
        begin
          _60_ = \spr_op__fn_unit$3 ;
          _61_ = \spr_op__insn$4 ;
          _62_ = \spr_op__insn_type$2 ;
          _63_ = \spr_op__is_32bit$5 ;
        end
    endcase
  end
  always @* begin
      \spr_op__fn_unit$3$next  <= _20_;
      \spr_op__insn$4$next  <= _23_;
      \spr_op__insn_type$2$next  <= _26_;
      \spr_op__is_32bit$5$next  <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _51_;
    _11_ = _74_;
    (* src = "libresoc.v:164921.5-164921.29" *)
    casez (\initial )
      /* src = "libresoc.v:164921.9-164921.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _53_, _51_ } = { \o_ok$30 , \o$29  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _53_, _51_ } = { \o_ok$30 , \o$29  };
        end
      default:
        begin
          _51_ = o;
          _53_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 1'h0;
        end
      default:
          _74_ = _53_;
    endcase
  end
  always @* begin
      \o$next  <= _09_;
      \o_ok$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _57_;
    _18_ = _76_;
    (* src = "libresoc.v:164940.5-164940.29" *)
    casez (\initial )
      /* src = "libresoc.v:164940.9-164940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _58_, _57_ } = { \spr1_ok$32 , \spr1$31  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _58_, _57_ } = { \spr1_ok$32 , \spr1$31  };
        end
      default:
        begin
          _57_ = \spr1$6 ;
          _58_ = spr1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 1'h0;
        end
      default:
          _76_ = _58_;
    endcase
  end
  always @* begin
      \spr1$6$next  <= _15_;
      \spr1_ok$next  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _47_;
    _03_ = _73_;
    (* src = "libresoc.v:164959.5-164959.29" *)
    casez (\initial )
      /* src = "libresoc.v:164959.9-164959.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _48_, _47_ } = { \fast1_ok$34 , \fast1$33  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _48_, _47_ } = { \fast1_ok$34 , \fast1$33  };
        end
      default:
        begin
          _48_ = fast1_ok;
          _47_ = \fast1$7 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 1'h0;
        end
      default:
          _73_ = _48_;
    endcase
  end
  always @* begin
      \fast1_ok$next  <= _03_;
      \fast1$7$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = _70_;
    _45_ = _79_;
    (* src = "libresoc.v:164978.5-164978.29" *)
    casez (\initial )
      /* src = "libresoc.v:164978.9-164978.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _71_, _70_ } = { \xer_so_ok$36 , \xer_so$35  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _71_, _70_ } = { \xer_so_ok$36 , \xer_so$35  };
        end
      default:
        begin
          _71_ = xer_so_ok;
          _70_ = \xer_so$8 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _79_ = 1'h0;
        end
      default:
          _79_ = _71_;
    endcase
  end
  always @* begin
      \xer_so_ok$next  <= _45_;
      \xer_so$8$next  <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _37_ = _67_;
    _40_ = _78_;
    (* src = "libresoc.v:164997.5-164997.29" *)
    casez (\initial )
      /* src = "libresoc.v:164997.9-164997.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _68_, _67_ } = { \xer_ov_ok$38 , \xer_ov$37  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _68_, _67_ } = { \xer_ov_ok$38 , \xer_ov$37  };
        end
      default:
        begin
          _68_ = xer_ov_ok;
          _67_ = \xer_ov$9 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _78_ = 1'h0;
        end
      default:
          _78_ = _68_;
    endcase
  end
  always @* begin
      \xer_ov_ok$next  <= _40_;
      \xer_ov$9$next  <= _37_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = _64_;
    _35_ = _77_;
    (* src = "libresoc.v:165016.5-165016.29" *)
    casez (\initial )
      /* src = "libresoc.v:165016.9-165016.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _65_, _64_ } = { \xer_ca_ok$40 , \xer_ca$39  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _65_, _64_ } = { \xer_ca_ok$40 , \xer_ca$39  };
        end
      default:
        begin
          _64_ = \xer_ca$10 ;
          _65_ = xer_ca_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 1'h0;
        end
      default:
          _77_ = _65_;
    endcase
  end
  always @* begin
      \xer_ca$10$next  <= _32_;
      \xer_ca_ok$next  <= _35_;
  end
  assign \$22  = _80_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_ca_ok$40 , \xer_ca$39  } = { spr_main_xer_ca_ok, \spr_main_xer_ca$20  };
  assign { \xer_ov_ok$38 , \xer_ov$37  } = { spr_main_xer_ov_ok, \spr_main_xer_ov$19  };
  assign { \xer_so_ok$36 , \xer_so$35  } = { spr_main_xer_so_ok, \spr_main_xer_so$18  };
  assign { \fast1_ok$34 , \fast1$33  } = { spr_main_fast1_ok, \spr_main_fast1$17  };
  assign { \spr1_ok$32 , \spr1$31  } = { spr_main_spr1_ok, \spr_main_spr1$16  };
  assign { \o_ok$30 , \o$29  } = { spr_main_o_ok, spr_main_o };
  assign { \spr_op__is_32bit$28 , \spr_op__insn$27 , \spr_op__fn_unit$26 , \spr_op__insn_type$25  } = { \spr_main_spr_op__is_32bit$15 , \spr_main_spr_op__insn$14 , \spr_main_spr_op__fn_unit$13 , \spr_main_spr_op__insn_type$12  };
  assign \muxid$24  = \spr_main_muxid$11 ;
  assign p_valid_i_p_ready_o = \$22 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$21  = p_valid_i;
  assign spr_main_xer_ca = xer_ca;
  assign spr_main_xer_ov = xer_ov;
  assign spr_main_xer_so = xer_so;
  assign spr_main_fast1 = fast1;
  assign spr_main_spr1 = spr1;
  assign spr_main_ra = ra;
  assign { spr_main_spr_op__is_32bit, spr_main_spr_op__insn, spr_main_spr_op__fn_unit, spr_main_spr_op__insn_type } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
  assign spr_main_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:165059.1-166551.10" *)
module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, p_valid_i, p_ready_o, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , ra, rb, \xer_so$20 , \xer_ca$21 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:166241.3-166242.49" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [13:0] _002_;
  (* src = "libresoc.v:166211.3-166212.47" *)
  reg [13:0] _003_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:166213.3-166214.61" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _006_;
  (* src = "libresoc.v:166215.3-166216.57" *)
  reg _007_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [1:0] _008_;
  (* src = "libresoc.v:166233.3-166234.55" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [31:0] _010_;
  (* src = "libresoc.v:166243.3-166244.41" *)
  reg [31:0] _011_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [6:0] _012_;
  (* src = "libresoc.v:166209.3-166210.51" *)
  reg [6:0] _013_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _014_;
  (* src = "libresoc.v:166225.3-166226.51" *)
  reg _015_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _016_;
  (* src = "libresoc.v:166229.3-166230.53" *)
  reg _017_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _018_;
  (* src = "libresoc.v:166237.3-166238.49" *)
  reg _019_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _020_;
  (* src = "libresoc.v:166239.3-166240.51" *)
  reg _021_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _022_;
  (* src = "libresoc.v:166221.3-166222.45" *)
  reg _023_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _024_;
  (* src = "libresoc.v:166223.3-166224.45" *)
  reg _025_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _026_;
  (* src = "libresoc.v:166235.3-166236.57" *)
  reg _027_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _028_;
  (* src = "libresoc.v:166219.3-166220.45" *)
  reg _029_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _030_;
  (* src = "libresoc.v:166217.3-166218.45" *)
  reg _031_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _032_;
  (* src = "libresoc.v:166231.3-166232.51" *)
  reg _033_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _034_;
  (* src = "libresoc.v:166227.3-166228.45" *)
  reg _035_;
  (* src = "libresoc.v:166358.3-166376.6" *)
  reg [3:0] _036_;
  (* src = "libresoc.v:166201.3-166202.25" *)
  reg [3:0] _037_;
  (* src = "libresoc.v:166358.3-166376.6" *)
  reg _038_;
  (* src = "libresoc.v:166203.3-166204.31" *)
  reg _039_;
  (* src = "libresoc.v:165060.7-165060.20" *)
  reg _040_;
  (* src = "libresoc.v:166452.3-166464.6" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:166245.3-166246.27" *)
  reg [1:0] _042_;
  (* src = "libresoc.v:166507.3-166525.6" *)
  reg [63:0] _043_;
  (* src = "libresoc.v:166205.3-166206.19" *)
  reg [63:0] _044_;
  (* src = "libresoc.v:166507.3-166525.6" *)
  reg _045_;
  (* src = "libresoc.v:166207.3-166208.25" *)
  reg _046_;
  (* src = "libresoc.v:166434.3-166451.6" *)
  reg _047_;
  (* src = "libresoc.v:166247.3-166248.29" *)
  reg _048_;
  (* src = "libresoc.v:166377.3-166395.6" *)
  reg [1:0] _049_;
  (* src = "libresoc.v:166197.3-166198.29" *)
  reg [1:0] _050_;
  (* src = "libresoc.v:166377.3-166395.6" *)
  reg _051_;
  (* src = "libresoc.v:166199.3-166200.35" *)
  reg _052_;
  (* src = "libresoc.v:166396.3-166414.6" *)
  reg [1:0] _053_;
  (* src = "libresoc.v:166193.3-166194.29" *)
  reg [1:0] _054_;
  (* src = "libresoc.v:166396.3-166414.6" *)
  reg _055_;
  (* src = "libresoc.v:166195.3-166196.35" *)
  reg _056_;
  (* src = "libresoc.v:166415.3-166433.6" *)
  reg _057_;
  (* src = "libresoc.v:166189.3-166190.29" *)
  reg _058_;
  (* src = "libresoc.v:166415.3-166433.6" *)
  reg _059_;
  (* src = "libresoc.v:166191.3-166192.35" *)
  reg _060_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [3:0] _061_;
  (* src = "libresoc.v:165065.13-165065.36" *)
  reg [3:0] _062_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [13:0] _063_;
  (* src = "libresoc.v:165089.14-165089.40" *)
  reg [13:0] _064_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [63:0] _065_;
  (* src = "libresoc.v:165128.14-165128.59" *)
  reg [63:0] _066_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _067_;
  (* src = "libresoc.v:165137.7-165137.34" *)
  reg _068_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [1:0] _069_;
  (* src = "libresoc.v:165150.13-165150.39" *)
  reg [1:0] _070_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [31:0] _071_;
  (* src = "libresoc.v:165167.14-165167.34" *)
  reg [31:0] _072_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [6:0] _073_;
  (* src = "libresoc.v:165251.13-165251.38" *)
  reg [6:0] _074_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _075_;
  (* src = "libresoc.v:165410.7-165410.31" *)
  reg _076_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _077_;
  (* src = "libresoc.v:165419.7-165419.32" *)
  reg _078_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _079_;
  (* src = "libresoc.v:165428.7-165428.30" *)
  reg _080_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _081_;
  (* src = "libresoc.v:165437.7-165437.31" *)
  reg _082_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _083_;
  (* src = "libresoc.v:165446.7-165446.28" *)
  reg _084_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _085_;
  (* src = "libresoc.v:165455.7-165455.28" *)
  reg _086_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _087_;
  (* src = "libresoc.v:165464.7-165464.34" *)
  reg _088_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _089_;
  (* src = "libresoc.v:165473.7-165473.28" *)
  reg _090_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _091_;
  (* src = "libresoc.v:165482.7-165482.28" *)
  reg _092_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _093_;
  (* src = "libresoc.v:165491.7-165491.31" *)
  reg _094_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _095_;
  (* src = "libresoc.v:165500.7-165500.28" *)
  reg _096_;
  (* src = "libresoc.v:166358.3-166376.6" *)
  reg [3:0] _097_;
  (* src = "libresoc.v:165513.13-165513.24" *)
  reg [3:0] _098_;
  (* src = "libresoc.v:166358.3-166376.6" *)
  reg _099_;
  (* src = "libresoc.v:165520.7-165520.21" *)
  reg _100_;
  (* src = "libresoc.v:166452.3-166464.6" *)
  reg [1:0] _101_;
  (* src = "libresoc.v:166097.13-166097.25" *)
  reg [1:0] _102_;
  (* src = "libresoc.v:166507.3-166525.6" *)
  reg [63:0] _103_;
  (* src = "libresoc.v:166112.14-166112.38" *)
  reg [63:0] _104_;
  (* src = "libresoc.v:166507.3-166525.6" *)
  reg _105_;
  (* src = "libresoc.v:166119.7-166119.18" *)
  reg _106_;
  (* src = "libresoc.v:166434.3-166451.6" *)
  reg _107_;
  (* src = "libresoc.v:166133.7-166133.20" *)
  reg _108_;
  (* src = "libresoc.v:166377.3-166395.6" *)
  reg [1:0] _109_;
  (* src = "libresoc.v:166142.13-166142.26" *)
  reg [1:0] _110_;
  (* src = "libresoc.v:166377.3-166395.6" *)
  reg _111_;
  (* src = "libresoc.v:166151.7-166151.23" *)
  reg _112_;
  (* src = "libresoc.v:166396.3-166414.6" *)
  reg [1:0] _113_;
  (* src = "libresoc.v:166158.13-166158.26" *)
  reg [1:0] _114_;
  (* src = "libresoc.v:166396.3-166414.6" *)
  reg _115_;
  (* src = "libresoc.v:166165.7-166165.23" *)
  reg _116_;
  (* src = "libresoc.v:166415.3-166433.6" *)
  reg _117_;
  (* src = "libresoc.v:166172.7-166172.20" *)
  reg _118_;
  (* src = "libresoc.v:166415.3-166433.6" *)
  reg _119_;
  (* src = "libresoc.v:166181.7-166181.23" *)
  reg _120_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg [63:0] _121_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _122_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _123_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _124_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _125_;
  (* src = "libresoc.v:166465.3-166506.6" *)
  reg _126_;
  (* src = "libresoc.v:166358.3-166376.6" *)
  reg _127_;
  (* src = "libresoc.v:166507.3-166525.6" *)
  reg _128_;
  (* src = "libresoc.v:166434.3-166451.6" *)
  reg _129_;
  (* src = "libresoc.v:166377.3-166395.6" *)
  reg _130_;
  (* src = "libresoc.v:166396.3-166414.6" *)
  reg _131_;
  (* src = "libresoc.v:166415.3-166433.6" *)
  reg _132_;
  (* src = "libresoc.v:166188.18-166188.118" *)
  wire _133_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] alu_op__data_len;
  reg [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] \alu_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \alu_op__data_len$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \alu_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] alu_op__fn_unit;
  reg [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \alu_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \alu_op__fn_unit$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] alu_op__imm_data__data;
  reg [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \alu_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \alu_op__imm_data__data$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__imm_data__ok;
  reg alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__imm_data__ok$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] alu_op__input_carry;
  reg [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] \alu_op__input_carry$14 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \alu_op__input_carry$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] alu_op__insn;
  reg [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \alu_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \alu_op__insn$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] alu_op__insn_type;
  reg [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \alu_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \alu_op__insn_type$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__invert_in;
  reg alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_in$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__invert_out;
  reg alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__invert_out$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_out$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__is_32bit;
  reg alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_32bit$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__is_signed;
  reg alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_signed$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__oe__oe;
  reg alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__oe$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__oe__ok;
  reg alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__ok$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__output_carry;
  reg alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__output_carry$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__rc__ok;
  reg alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__ok$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__rc__rc;
  reg alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__rc$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__write_cr0;
  reg alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__write_cr0$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__write_cr0$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output alu_op__zero_a;
  reg alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \alu_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__zero_a$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "libresoc.v:165060.7-165060.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] input_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \input_alu_op__data_len$39 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] input_alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \input_alu_op__fn_unit$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] input_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \input_alu_op__imm_data__data$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__imm_data__ok$26 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] input_alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \input_alu_op__input_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] input_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \input_alu_op__insn$40 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] input_alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \input_alu_op__insn_type$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__invert_in$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__invert_out$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__is_32bit$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__is_signed$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__oe__oe$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__oe__ok$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__output_carry$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__rc__ok$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__rc__rc$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__write_cr0$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_alu_op__zero_a$32 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] input_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \input_muxid$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_ra$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rb$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] input_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \input_xer_ca$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire input_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \input_xer_so$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] main_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \main_alu_op__data_len$62 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_alu_op__fn_unit$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_alu_op__imm_data__data$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__imm_data__ok$49 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] main_alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \main_alu_op__input_carry$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_alu_op__insn$63 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_alu_op__insn_type$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__invert_in$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__invert_out$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__is_32bit$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__is_signed$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__oe__oe$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__oe__ok$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__output_carry$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__rc__ok$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__rc__rc$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__write_cr0$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_alu_op__zero_a$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] main_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] main_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \main_xer_ca$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] main_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire main_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \main_xer_so$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$69 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$66 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  reg [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ca$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ca$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ca$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  reg xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  reg [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ov$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  reg xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _133_ = \p_valid_i$66  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:166249.11-166296.4" *)
  \input  \input  (
    .alu_op__data_len(input_alu_op__data_len),
    .\alu_op__data_len$18 (\input_alu_op__data_len$39 ),
    .alu_op__fn_unit(input_alu_op__fn_unit),
    .\alu_op__fn_unit$3 (\input_alu_op__fn_unit$24 ),
    .alu_op__imm_data__data(input_alu_op__imm_data__data),
    .\alu_op__imm_data__data$4 (\input_alu_op__imm_data__data$25 ),
    .alu_op__imm_data__ok(input_alu_op__imm_data__ok),
    .\alu_op__imm_data__ok$5 (\input_alu_op__imm_data__ok$26 ),
    .alu_op__input_carry(input_alu_op__input_carry),
    .\alu_op__input_carry$14 (\input_alu_op__input_carry$35 ),
    .alu_op__insn(input_alu_op__insn),
    .\alu_op__insn$19 (\input_alu_op__insn$40 ),
    .alu_op__insn_type(input_alu_op__insn_type),
    .\alu_op__insn_type$2 (\input_alu_op__insn_type$23 ),
    .alu_op__invert_in(input_alu_op__invert_in),
    .\alu_op__invert_in$10 (\input_alu_op__invert_in$31 ),
    .alu_op__invert_out(input_alu_op__invert_out),
    .\alu_op__invert_out$12 (\input_alu_op__invert_out$33 ),
    .alu_op__is_32bit(input_alu_op__is_32bit),
    .\alu_op__is_32bit$16 (\input_alu_op__is_32bit$37 ),
    .alu_op__is_signed(input_alu_op__is_signed),
    .\alu_op__is_signed$17 (\input_alu_op__is_signed$38 ),
    .alu_op__oe__oe(input_alu_op__oe__oe),
    .\alu_op__oe__oe$8 (\input_alu_op__oe__oe$29 ),
    .alu_op__oe__ok(input_alu_op__oe__ok),
    .\alu_op__oe__ok$9 (\input_alu_op__oe__ok$30 ),
    .alu_op__output_carry(input_alu_op__output_carry),
    .\alu_op__output_carry$15 (\input_alu_op__output_carry$36 ),
    .alu_op__rc__ok(input_alu_op__rc__ok),
    .\alu_op__rc__ok$7 (\input_alu_op__rc__ok$28 ),
    .alu_op__rc__rc(input_alu_op__rc__rc),
    .\alu_op__rc__rc$6 (\input_alu_op__rc__rc$27 ),
    .alu_op__write_cr0(input_alu_op__write_cr0),
    .\alu_op__write_cr0$13 (\input_alu_op__write_cr0$34 ),
    .alu_op__zero_a(input_alu_op__zero_a),
    .\alu_op__zero_a$11 (\input_alu_op__zero_a$32 ),
    .muxid(input_muxid),
    .\muxid$1 (\input_muxid$22 ),
    .ra(input_ra),
    .\ra$20 (\input_ra$41 ),
    .rb(input_rb),
    .\rb$21 (\input_rb$42 ),
    .xer_ca(input_xer_ca),
    .\xer_ca$23 (\input_xer_ca$44 ),
    .xer_so(input_xer_so),
    .\xer_so$22 (\input_xer_so$43 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:166297.8-166349.4" *)
  main main (
    .alu_op__data_len(main_alu_op__data_len),
    .\alu_op__data_len$18 (\main_alu_op__data_len$62 ),
    .alu_op__fn_unit(main_alu_op__fn_unit),
    .\alu_op__fn_unit$3 (\main_alu_op__fn_unit$47 ),
    .alu_op__imm_data__data(main_alu_op__imm_data__data),
    .\alu_op__imm_data__data$4 (\main_alu_op__imm_data__data$48 ),
    .alu_op__imm_data__ok(main_alu_op__imm_data__ok),
    .\alu_op__imm_data__ok$5 (\main_alu_op__imm_data__ok$49 ),
    .alu_op__input_carry(main_alu_op__input_carry),
    .\alu_op__input_carry$14 (\main_alu_op__input_carry$58 ),
    .alu_op__insn(main_alu_op__insn),
    .\alu_op__insn$19 (\main_alu_op__insn$63 ),
    .alu_op__insn_type(main_alu_op__insn_type),
    .\alu_op__insn_type$2 (\main_alu_op__insn_type$46 ),
    .alu_op__invert_in(main_alu_op__invert_in),
    .\alu_op__invert_in$10 (\main_alu_op__invert_in$54 ),
    .alu_op__invert_out(main_alu_op__invert_out),
    .\alu_op__invert_out$12 (\main_alu_op__invert_out$56 ),
    .alu_op__is_32bit(main_alu_op__is_32bit),
    .\alu_op__is_32bit$16 (\main_alu_op__is_32bit$60 ),
    .alu_op__is_signed(main_alu_op__is_signed),
    .\alu_op__is_signed$17 (\main_alu_op__is_signed$61 ),
    .alu_op__oe__oe(main_alu_op__oe__oe),
    .\alu_op__oe__oe$8 (\main_alu_op__oe__oe$52 ),
    .alu_op__oe__ok(main_alu_op__oe__ok),
    .\alu_op__oe__ok$9 (\main_alu_op__oe__ok$53 ),
    .alu_op__output_carry(main_alu_op__output_carry),
    .\alu_op__output_carry$15 (\main_alu_op__output_carry$59 ),
    .alu_op__rc__ok(main_alu_op__rc__ok),
    .\alu_op__rc__ok$7 (\main_alu_op__rc__ok$51 ),
    .alu_op__rc__rc(main_alu_op__rc__rc),
    .\alu_op__rc__rc$6 (\main_alu_op__rc__rc$50 ),
    .alu_op__write_cr0(main_alu_op__write_cr0),
    .\alu_op__write_cr0$13 (\main_alu_op__write_cr0$57 ),
    .alu_op__zero_a(main_alu_op__zero_a),
    .\alu_op__zero_a$11 (\main_alu_op__zero_a$55 ),
    .cr_a(main_cr_a),
    .cr_a_ok(main_cr_a_ok),
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$45 ),
    .o(main_o),
    .o_ok(main_o_ok),
    .ra(main_ra),
    .rb(main_rb),
    .xer_ca(main_xer_ca),
    .\xer_ca$20 (\main_xer_ca$64 ),
    .xer_ca_ok(main_xer_ca_ok),
    .xer_ov(main_xer_ov),
    .xer_ov_ok(main_xer_ov_ok),
    .xer_so(main_xer_so),
    .\xer_so$21 (\main_xer_so$65 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:166350.9-166353.4" *)
  \n$2  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:166354.9-166357.4" *)
  \p$1  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _040_ = 1'h0;
  end
  always @* begin
      \initial  <= _040_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _062_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__data_len <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_op__fn_unit <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_op__imm_data__data <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__imm_data__ok <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__input_carry <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_op__insn <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_op__insn_type <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__invert_in <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__invert_out <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__is_32bit <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__is_signed <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__oe__oe <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__oe__ok <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__output_carry <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__rc__ok <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__rc__rc <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__write_cr0 <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_op__zero_a <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      cr_a <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      xer_ca <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ca_ok <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov_ok <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov_ok <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \xer_ca$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ca <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ca_ok <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__insn_type <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__fn_unit <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__imm_data__data <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__imm_data__ok <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \alu_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__rc__rc <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \alu_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__rc__ok <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \alu_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__oe__oe <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \alu_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__oe__ok <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \alu_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__invert_in <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \alu_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__zero_a <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \alu_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__invert_out <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \alu_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__write_cr0 <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__input_carry <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \alu_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__output_carry <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__is_32bit <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alu_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__is_signed <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \alu_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__data_len <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_op__insn <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _097_;
    _038_ = _127_;
    (* src = "libresoc.v:166359.5-166359.29" *)
    casez (\initial )
      /* src = "libresoc.v:166359.9-166359.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _099_, _097_ } = { \cr_a_ok$91 , \cr_a$90  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _099_, _097_ } = { \cr_a_ok$91 , \cr_a$90  };
        end
      default:
        begin
          _097_ = cr_a;
          _099_ = cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = 1'h0;
        end
      default:
          _127_ = _099_;
    endcase
  end
  always @* begin
      \cr_a$next  <= _036_;
      \cr_a_ok$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _109_;
    _051_ = _130_;
    (* src = "libresoc.v:166378.5-166378.29" *)
    casez (\initial )
      /* src = "libresoc.v:166378.9-166378.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _111_, _109_ } = { \xer_ca_ok$93 , \xer_ca$92  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _111_, _109_ } = { \xer_ca_ok$93 , \xer_ca$92  };
        end
      default:
        begin
          _111_ = xer_ca_ok;
          _109_ = xer_ca;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h0;
        end
      default:
          _130_ = _111_;
    endcase
  end
  always @* begin
      \xer_ca_ok$next  <= _051_;
      \xer_ca$next  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _113_;
    _055_ = _131_;
    (* src = "libresoc.v:166397.5-166397.29" *)
    casez (\initial )
      /* src = "libresoc.v:166397.9-166397.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _115_, _113_ } = { \xer_ov_ok$95 , \xer_ov$94  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _115_, _113_ } = { \xer_ov_ok$95 , \xer_ov$94  };
        end
      default:
        begin
          _113_ = xer_ov;
          _115_ = xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = 1'h0;
        end
      default:
          _131_ = _115_;
    endcase
  end
  always @* begin
      \xer_ov$next  <= _053_;
      \xer_ov_ok$next  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _117_;
    _059_ = _132_;
    (* src = "libresoc.v:166416.5-166416.29" *)
    casez (\initial )
      /* src = "libresoc.v:166416.9-166416.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _119_, _117_ } = { \xer_so_ok$97 , \xer_so$96  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _119_, _117_ } = { \xer_so_ok$97 , \xer_so$96  };
        end
      default:
        begin
          _117_ = xer_so;
          _119_ = xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h0;
        end
      default:
          _132_ = _119_;
    endcase
  end
  always @* begin
      \xer_so$next  <= _057_;
      \xer_so_ok$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _129_;
    (* src = "libresoc.v:166435.5-166435.29" *)
    casez (\initial )
      /* src = "libresoc.v:166435.9-166435.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _107_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _107_ = 1'h0;
        end
      default:
          _107_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = 1'h0;
        end
      default:
          _129_ = _107_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _101_;
    (* src = "libresoc.v:166453.5-166453.29" *)
    casez (\initial )
      /* src = "libresoc.v:166453.9-166453.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _101_ = \muxid$69 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _101_ = \muxid$69 ;
        end
      default:
          _101_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _061_;
    _002_ = _063_;
    _008_ = _069_;
    _010_ = _071_;
    _012_ = _073_;
    _014_ = _075_;
    _016_ = _077_;
    _018_ = _079_;
    _020_ = _081_;
    _026_ = _087_;
    _032_ = _093_;
    _034_ = _095_;
    _004_ = _121_;
    _006_ = _122_;
    _022_ = _123_;
    _024_ = _124_;
    _028_ = _125_;
    _030_ = _126_;
    (* src = "libresoc.v:166466.5-166466.29" *)
    casez (\initial )
      /* src = "libresoc.v:166466.9-166466.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _071_, _061_, _081_, _079_, _087_, _069_, _093_, _077_, _095_, _075_, _085_, _083_, _089_, _091_, _067_, _065_, _063_, _073_ } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _071_, _061_, _081_, _079_, _087_, _069_, _093_, _077_, _095_, _075_, _085_, _083_, _089_, _091_, _067_, _065_, _063_, _073_ } = { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70  };
        end
      default:
        begin
          _061_ = alu_op__data_len;
          _063_ = alu_op__fn_unit;
          _065_ = alu_op__imm_data__data;
          _067_ = alu_op__imm_data__ok;
          _069_ = alu_op__input_carry;
          _071_ = alu_op__insn;
          _073_ = alu_op__insn_type;
          _075_ = alu_op__invert_in;
          _077_ = alu_op__invert_out;
          _079_ = alu_op__is_32bit;
          _081_ = alu_op__is_signed;
          _083_ = alu_op__oe__oe;
          _085_ = alu_op__oe__ok;
          _087_ = alu_op__output_carry;
          _089_ = alu_op__rc__ok;
          _091_ = alu_op__rc__rc;
          _093_ = alu_op__write_cr0;
          _095_ = alu_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = 64'h0000000000000000;
          _122_ = 1'h0;
          _126_ = 1'h0;
          _125_ = 1'h0;
          _123_ = 1'h0;
          _124_ = 1'h0;
        end
      default:
        begin
          _121_ = _065_;
          _122_ = _067_;
          _123_ = _083_;
          _124_ = _085_;
          _125_ = _089_;
          _126_ = _091_;
        end
    endcase
  end
  always @* begin
      \alu_op__data_len$next  <= _000_;
      \alu_op__fn_unit$next  <= _002_;
      \alu_op__imm_data__data$next  <= _004_;
      \alu_op__imm_data__ok$next  <= _006_;
      \alu_op__input_carry$next  <= _008_;
      \alu_op__insn$next  <= _010_;
      \alu_op__insn_type$next  <= _012_;
      \alu_op__invert_in$next  <= _014_;
      \alu_op__invert_out$next  <= _016_;
      \alu_op__is_32bit$next  <= _018_;
      \alu_op__is_signed$next  <= _020_;
      \alu_op__oe__oe$next  <= _022_;
      \alu_op__oe__ok$next  <= _024_;
      \alu_op__output_carry$next  <= _026_;
      \alu_op__rc__ok$next  <= _028_;
      \alu_op__rc__rc$next  <= _030_;
      \alu_op__write_cr0$next  <= _032_;
      \alu_op__zero_a$next  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _103_;
    _045_ = _128_;
    (* src = "libresoc.v:166508.5-166508.29" *)
    casez (\initial )
      /* src = "libresoc.v:166508.9-166508.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _105_, _103_ } = { \o_ok$89 , \o$88  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _105_, _103_ } = { \o_ok$89 , \o$88  };
        end
      default:
        begin
          _103_ = o;
          _105_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = 1'h0;
        end
      default:
          _128_ = _105_;
    endcase
  end
  always @* begin
      \o$next  <= _043_;
      \o_ok$next  <= _045_;
  end
  assign \$67  = _133_;
  assign \xer_so_ok$98  = 1'h0;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_so_ok$97 , \xer_so$96  } = { 1'h0, \main_xer_so$65  };
  assign { \xer_ov_ok$95 , \xer_ov$94  } = { main_xer_ov_ok, main_xer_ov };
  assign { \xer_ca_ok$93 , \xer_ca$92  } = { main_xer_ca_ok, \main_xer_ca$64  };
  assign { \cr_a_ok$91 , \cr_a$90  } = { main_cr_a_ok, main_cr_a };
  assign { \o_ok$89 , \o$88  } = { main_o_ok, main_o };
  assign { \alu_op__insn$87 , \alu_op__data_len$86 , \alu_op__is_signed$85 , \alu_op__is_32bit$84 , \alu_op__output_carry$83 , \alu_op__input_carry$82 , \alu_op__write_cr0$81 , \alu_op__invert_out$80 , \alu_op__zero_a$79 , \alu_op__invert_in$78 , \alu_op__oe__ok$77 , \alu_op__oe__oe$76 , \alu_op__rc__ok$75 , \alu_op__rc__rc$74 , \alu_op__imm_data__ok$73 , \alu_op__imm_data__data$72 , \alu_op__fn_unit$71 , \alu_op__insn_type$70  } = { \main_alu_op__insn$63 , \main_alu_op__data_len$62 , \main_alu_op__is_signed$61 , \main_alu_op__is_32bit$60 , \main_alu_op__output_carry$59 , \main_alu_op__input_carry$58 , \main_alu_op__write_cr0$57 , \main_alu_op__invert_out$56 , \main_alu_op__zero_a$55 , \main_alu_op__invert_in$54 , \main_alu_op__oe__ok$53 , \main_alu_op__oe__oe$52 , \main_alu_op__rc__ok$51 , \main_alu_op__rc__rc$50 , \main_alu_op__imm_data__ok$49 , \main_alu_op__imm_data__data$48 , \main_alu_op__fn_unit$47 , \main_alu_op__insn_type$46  };
  assign \muxid$69  = \main_muxid$45 ;
  assign p_valid_i_p_ready_o = \$67 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$66  = p_valid_i;
  assign main_xer_ca = \input_xer_ca$44 ;
  assign main_xer_so = \input_xer_so$43 ;
  assign main_rb = \input_rb$42 ;
  assign main_ra = \input_ra$41 ;
  assign { main_alu_op__insn, main_alu_op__data_len, main_alu_op__is_signed, main_alu_op__is_32bit, main_alu_op__output_carry, main_alu_op__input_carry, main_alu_op__write_cr0, main_alu_op__invert_out, main_alu_op__zero_a, main_alu_op__invert_in, main_alu_op__oe__ok, main_alu_op__oe__oe, main_alu_op__rc__ok, main_alu_op__rc__rc, main_alu_op__imm_data__ok, main_alu_op__imm_data__data, main_alu_op__fn_unit, main_alu_op__insn_type } = { \input_alu_op__insn$40 , \input_alu_op__data_len$39 , \input_alu_op__is_signed$38 , \input_alu_op__is_32bit$37 , \input_alu_op__output_carry$36 , \input_alu_op__input_carry$35 , \input_alu_op__write_cr0$34 , \input_alu_op__invert_out$33 , \input_alu_op__zero_a$32 , \input_alu_op__invert_in$31 , \input_alu_op__oe__ok$30 , \input_alu_op__oe__oe$29 , \input_alu_op__rc__ok$28 , \input_alu_op__rc__rc$27 , \input_alu_op__imm_data__ok$26 , \input_alu_op__imm_data__data$25 , \input_alu_op__fn_unit$24 , \input_alu_op__insn_type$23  };
  assign main_muxid = \input_muxid$22 ;
  assign input_xer_ca = \xer_ca$21 ;
  assign input_xer_so = \xer_so$20 ;
  assign input_rb = rb;
  assign input_ra = ra;
  assign { input_alu_op__insn, input_alu_op__data_len, input_alu_op__is_signed, input_alu_op__is_32bit, input_alu_op__output_carry, input_alu_op__input_carry, input_alu_op__write_cr0, input_alu_op__invert_out, input_alu_op__zero_a, input_alu_op__invert_in, input_alu_op__oe__ok, input_alu_op__oe__oe, input_alu_op__rc__ok, input_alu_op__rc__rc, input_alu_op__imm_data__ok, input_alu_op__imm_data__data, input_alu_op__fn_unit, input_alu_op__insn_type } = { \alu_op__insn$19 , \alu_op__data_len$18 , \alu_op__is_signed$17 , \alu_op__is_32bit$16 , \alu_op__output_carry$15 , \alu_op__input_carry$14 , \alu_op__write_cr0$13 , \alu_op__invert_out$12 , \alu_op__zero_a$11 , \alu_op__invert_in$10 , \alu_op__oe__ok$9 , \alu_op__oe__oe$8 , \alu_op__rc__ok$7 , \alu_op__rc__rc$6 , \alu_op__imm_data__ok$5 , \alu_op__imm_data__data$4 , \alu_op__fn_unit$3 , \alu_op__insn_type$2  };
  assign input_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:166555.1-167991.10" *)
module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, p_valid_i, p_ready_o, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , ra, rb, rc, \xer_so$19 , \xer_ca$20 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:167924.3-167942.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:167666.3-167667.25" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:167924.3-167942.6" *)
  reg _002_;
  (* src = "libresoc.v:167668.3-167669.31" *)
  reg _003_;
  (* src = "libresoc.v:166556.7-166556.20" *)
  reg _004_;
  (* src = "libresoc.v:167851.3-167863.6" *)
  reg [1:0] _005_;
  (* src = "libresoc.v:167708.3-167709.27" *)
  reg [1:0] _006_;
  (* src = "libresoc.v:167905.3-167923.6" *)
  reg [63:0] _007_;
  (* src = "libresoc.v:167670.3-167671.19" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:167905.3-167923.6" *)
  reg _009_;
  (* src = "libresoc.v:167672.3-167673.25" *)
  reg _010_;
  (* src = "libresoc.v:167833.3-167850.6" *)
  reg _011_;
  (* src = "libresoc.v:167710.3-167711.29" *)
  reg _012_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [13:0] _013_;
  (* src = "libresoc.v:167676.3-167677.45" *)
  reg [13:0] _014_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:167678.3-167679.59" *)
  reg [63:0] _016_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _017_;
  (* src = "libresoc.v:167680.3-167681.55" *)
  reg _018_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [1:0] _019_;
  (* src = "libresoc.v:167694.3-167695.53" *)
  reg [1:0] _020_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _021_;
  (* src = "libresoc.v:167698.3-167699.47" *)
  reg _022_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [31:0] _023_;
  (* src = "libresoc.v:167706.3-167707.39" *)
  reg [31:0] _024_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [6:0] _025_;
  (* src = "libresoc.v:167674.3-167675.49" *)
  reg [6:0] _026_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _027_;
  (* src = "libresoc.v:167692.3-167693.49" *)
  reg _028_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _029_;
  (* src = "libresoc.v:167702.3-167703.47" *)
  reg _030_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _031_;
  (* src = "libresoc.v:167704.3-167705.49" *)
  reg _032_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _033_;
  (* src = "libresoc.v:167686.3-167687.43" *)
  reg _034_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _035_;
  (* src = "libresoc.v:167688.3-167689.43" *)
  reg _036_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _037_;
  (* src = "libresoc.v:167696.3-167697.55" *)
  reg _038_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _039_;
  (* src = "libresoc.v:167700.3-167701.49" *)
  reg _040_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _041_;
  (* src = "libresoc.v:167684.3-167685.43" *)
  reg _042_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _043_;
  (* src = "libresoc.v:167682.3-167683.43" *)
  reg _044_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _045_;
  (* src = "libresoc.v:167690.3-167691.49" *)
  reg _046_;
  (* src = "libresoc.v:167814.3-167832.6" *)
  reg [1:0] _047_;
  (* src = "libresoc.v:167658.3-167659.29" *)
  reg [1:0] _048_;
  (* src = "libresoc.v:167814.3-167832.6" *)
  reg _049_;
  (* src = "libresoc.v:167660.3-167661.35" *)
  reg _050_;
  (* src = "libresoc.v:167943.3-167961.6" *)
  reg _051_;
  (* src = "libresoc.v:167662.3-167663.29" *)
  reg _052_;
  (* src = "libresoc.v:167943.3-167961.6" *)
  reg _053_;
  (* src = "libresoc.v:167664.3-167665.35" *)
  reg _054_;
  (* src = "libresoc.v:167924.3-167942.6" *)
  reg [3:0] _055_;
  (* src = "libresoc.v:166565.13-166565.24" *)
  reg [3:0] _056_;
  (* src = "libresoc.v:167924.3-167942.6" *)
  reg _057_;
  (* src = "libresoc.v:166574.7-166574.21" *)
  reg _058_;
  (* src = "libresoc.v:167851.3-167863.6" *)
  reg [1:0] _059_;
  (* src = "libresoc.v:167139.13-167139.25" *)
  reg [1:0] _060_;
  (* src = "libresoc.v:167905.3-167923.6" *)
  reg [63:0] _061_;
  (* src = "libresoc.v:167154.14-167154.38" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:167905.3-167923.6" *)
  reg _063_;
  (* src = "libresoc.v:167161.7-167161.18" *)
  reg _064_;
  (* src = "libresoc.v:167833.3-167850.6" *)
  reg _065_;
  (* src = "libresoc.v:167175.7-167175.20" *)
  reg _066_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [13:0] _067_;
  (* src = "libresoc.v:167201.14-167201.39" *)
  reg [13:0] _068_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [63:0] _069_;
  (* src = "libresoc.v:167240.14-167240.58" *)
  reg [63:0] _070_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _071_;
  (* src = "libresoc.v:167249.7-167249.33" *)
  reg _072_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [1:0] _073_;
  (* src = "libresoc.v:167262.13-167262.38" *)
  reg [1:0] _074_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _075_;
  (* src = "libresoc.v:167279.7-167279.29" *)
  reg _076_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [31:0] _077_;
  (* src = "libresoc.v:167288.14-167288.33" *)
  reg [31:0] _078_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [6:0] _079_;
  (* src = "libresoc.v:167372.13-167372.37" *)
  reg [6:0] _080_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _081_;
  (* src = "libresoc.v:167531.7-167531.30" *)
  reg _082_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _083_;
  (* src = "libresoc.v:167540.7-167540.29" *)
  reg _084_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _085_;
  (* src = "libresoc.v:167549.7-167549.30" *)
  reg _086_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _087_;
  (* src = "libresoc.v:167558.7-167558.27" *)
  reg _088_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _089_;
  (* src = "libresoc.v:167567.7-167567.27" *)
  reg _090_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _091_;
  (* src = "libresoc.v:167576.7-167576.33" *)
  reg _092_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _093_;
  (* src = "libresoc.v:167585.7-167585.30" *)
  reg _094_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _095_;
  (* src = "libresoc.v:167594.7-167594.27" *)
  reg _096_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _097_;
  (* src = "libresoc.v:167603.7-167603.27" *)
  reg _098_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _099_;
  (* src = "libresoc.v:167612.7-167612.30" *)
  reg _100_;
  (* src = "libresoc.v:167814.3-167832.6" *)
  reg [1:0] _101_;
  (* src = "libresoc.v:167621.13-167621.26" *)
  reg [1:0] _102_;
  (* src = "libresoc.v:167814.3-167832.6" *)
  reg _103_;
  (* src = "libresoc.v:167632.7-167632.23" *)
  reg _104_;
  (* src = "libresoc.v:167943.3-167961.6" *)
  reg _105_;
  (* src = "libresoc.v:167641.7-167641.20" *)
  reg _106_;
  (* src = "libresoc.v:167943.3-167961.6" *)
  reg _107_;
  (* src = "libresoc.v:167650.7-167650.23" *)
  reg _108_;
  (* src = "libresoc.v:167924.3-167942.6" *)
  reg _109_;
  (* src = "libresoc.v:167905.3-167923.6" *)
  reg _110_;
  (* src = "libresoc.v:167833.3-167850.6" *)
  reg _111_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg [63:0] _112_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _113_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _114_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _115_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _116_;
  (* src = "libresoc.v:167864.3-167904.6" *)
  reg _117_;
  (* src = "libresoc.v:167814.3-167832.6" *)
  reg _118_;
  (* src = "libresoc.v:167943.3-167961.6" *)
  reg _119_;
  (* src = "libresoc.v:167657.18-167657.118" *)
  wire _120_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "libresoc.v:166556.7-166556.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] input_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \input_muxid$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_ra$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rb$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rc$41 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] input_sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \input_sr_op__fn_unit$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] input_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \input_sr_op__imm_data__data$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__imm_data__ok$25 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] input_sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \input_sr_op__input_carry$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__input_cr$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] input_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \input_sr_op__insn$38 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] input_sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \input_sr_op__insn_type$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__invert_in$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__is_32bit$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__is_signed$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__oe__oe$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__oe__ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__output_carry$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__output_cr$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__rc__ok$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__rc__rc$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_sr_op__write_cr0$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] input_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \input_xer_ca$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire input_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \input_xer_so$42 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rc;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_sr_op__fn_unit$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_sr_op__imm_data__data$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__imm_data__ok$48 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] main_sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \main_sr_op__input_carry$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__input_cr$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_sr_op__insn$61 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_sr_op__insn_type$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__invert_in$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__is_32bit$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__is_signed$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__oe__oe$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__oe__ok$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__output_carry$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__output_cr$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__rc__ok$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__rc__rc$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_sr_op__write_cr0$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] main_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire main_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \main_xer_so$62 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$64 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rc;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] sr_op__fn_unit;
  reg [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \sr_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \sr_op__fn_unit$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \sr_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] sr_op__imm_data__data;
  reg [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \sr_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \sr_op__imm_data__data$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \sr_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__imm_data__ok;
  reg sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__imm_data__ok$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] sr_op__input_carry;
  reg [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] \sr_op__input_carry$12 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \sr_op__input_carry$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \sr_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__input_cr;
  reg sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__input_cr$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__input_cr$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__input_cr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] sr_op__insn;
  reg [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \sr_op__insn$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \sr_op__insn$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \sr_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] sr_op__insn_type;
  reg [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \sr_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \sr_op__insn_type$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \sr_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__invert_in;
  reg sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__invert_in$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__is_32bit;
  reg sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_32bit$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__is_signed;
  reg sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_signed$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__oe__oe;
  reg sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__oe$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__oe__ok;
  reg sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__ok$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__output_carry;
  reg sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__output_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_carry$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__output_cr;
  reg sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__output_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_cr$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__output_cr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__rc__ok;
  reg sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__ok$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__rc__rc;
  reg sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__rc$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output sr_op__write_cr0;
  reg sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \sr_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__write_cr0$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ca;
  reg [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] \xer_ca$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \xer_ca$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ca$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ca$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  reg xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so;
  reg xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _120_ = \p_valid_i$64  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:167712.15-167759.4" *)
  \input$113  \input  (
    .muxid(input_muxid),
    .\muxid$1 (\input_muxid$21 ),
    .ra(input_ra),
    .\ra$19 (\input_ra$39 ),
    .rb(input_rb),
    .\rb$20 (\input_rb$40 ),
    .rc(input_rc),
    .\rc$21 (\input_rc$41 ),
    .sr_op__fn_unit(input_sr_op__fn_unit),
    .\sr_op__fn_unit$3 (\input_sr_op__fn_unit$23 ),
    .sr_op__imm_data__data(input_sr_op__imm_data__data),
    .\sr_op__imm_data__data$4 (\input_sr_op__imm_data__data$24 ),
    .sr_op__imm_data__ok(input_sr_op__imm_data__ok),
    .\sr_op__imm_data__ok$5 (\input_sr_op__imm_data__ok$25 ),
    .sr_op__input_carry(input_sr_op__input_carry),
    .\sr_op__input_carry$12 (\input_sr_op__input_carry$32 ),
    .sr_op__input_cr(input_sr_op__input_cr),
    .\sr_op__input_cr$14 (\input_sr_op__input_cr$34 ),
    .sr_op__insn(input_sr_op__insn),
    .\sr_op__insn$18 (\input_sr_op__insn$38 ),
    .sr_op__insn_type(input_sr_op__insn_type),
    .\sr_op__insn_type$2 (\input_sr_op__insn_type$22 ),
    .sr_op__invert_in(input_sr_op__invert_in),
    .\sr_op__invert_in$11 (\input_sr_op__invert_in$31 ),
    .sr_op__is_32bit(input_sr_op__is_32bit),
    .\sr_op__is_32bit$16 (\input_sr_op__is_32bit$36 ),
    .sr_op__is_signed(input_sr_op__is_signed),
    .\sr_op__is_signed$17 (\input_sr_op__is_signed$37 ),
    .sr_op__oe__oe(input_sr_op__oe__oe),
    .\sr_op__oe__oe$8 (\input_sr_op__oe__oe$28 ),
    .sr_op__oe__ok(input_sr_op__oe__ok),
    .\sr_op__oe__ok$9 (\input_sr_op__oe__ok$29 ),
    .sr_op__output_carry(input_sr_op__output_carry),
    .\sr_op__output_carry$13 (\input_sr_op__output_carry$33 ),
    .sr_op__output_cr(input_sr_op__output_cr),
    .\sr_op__output_cr$15 (\input_sr_op__output_cr$35 ),
    .sr_op__rc__ok(input_sr_op__rc__ok),
    .\sr_op__rc__ok$7 (\input_sr_op__rc__ok$27 ),
    .sr_op__rc__rc(input_sr_op__rc__rc),
    .\sr_op__rc__rc$6 (\input_sr_op__rc__rc$26 ),
    .sr_op__write_cr0(input_sr_op__write_cr0),
    .\sr_op__write_cr0$10 (\input_sr_op__write_cr0$30 ),
    .xer_ca(input_xer_ca),
    .\xer_ca$23 (\input_xer_ca$43 ),
    .xer_so(input_xer_so),
    .\xer_so$22 (\input_xer_so$42 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:167760.14-167805.4" *)
  \main$114  main (
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$44 ),
    .o(main_o),
    .o_ok(main_o_ok),
    .ra(main_ra),
    .rb(main_rb),
    .rc(main_rc),
    .sr_op__fn_unit(main_sr_op__fn_unit),
    .\sr_op__fn_unit$3 (\main_sr_op__fn_unit$46 ),
    .sr_op__imm_data__data(main_sr_op__imm_data__data),
    .\sr_op__imm_data__data$4 (\main_sr_op__imm_data__data$47 ),
    .sr_op__imm_data__ok(main_sr_op__imm_data__ok),
    .\sr_op__imm_data__ok$5 (\main_sr_op__imm_data__ok$48 ),
    .sr_op__input_carry(main_sr_op__input_carry),
    .\sr_op__input_carry$12 (\main_sr_op__input_carry$55 ),
    .sr_op__input_cr(main_sr_op__input_cr),
    .\sr_op__input_cr$14 (\main_sr_op__input_cr$57 ),
    .sr_op__insn(main_sr_op__insn),
    .\sr_op__insn$18 (\main_sr_op__insn$61 ),
    .sr_op__insn_type(main_sr_op__insn_type),
    .\sr_op__insn_type$2 (\main_sr_op__insn_type$45 ),
    .sr_op__invert_in(main_sr_op__invert_in),
    .\sr_op__invert_in$11 (\main_sr_op__invert_in$54 ),
    .sr_op__is_32bit(main_sr_op__is_32bit),
    .\sr_op__is_32bit$16 (\main_sr_op__is_32bit$59 ),
    .sr_op__is_signed(main_sr_op__is_signed),
    .\sr_op__is_signed$17 (\main_sr_op__is_signed$60 ),
    .sr_op__oe__oe(main_sr_op__oe__oe),
    .\sr_op__oe__oe$8 (\main_sr_op__oe__oe$51 ),
    .sr_op__oe__ok(main_sr_op__oe__ok),
    .\sr_op__oe__ok$9 (\main_sr_op__oe__ok$52 ),
    .sr_op__output_carry(main_sr_op__output_carry),
    .\sr_op__output_carry$13 (\main_sr_op__output_carry$56 ),
    .sr_op__output_cr(main_sr_op__output_cr),
    .\sr_op__output_cr$15 (\main_sr_op__output_cr$58 ),
    .sr_op__rc__ok(main_sr_op__rc__ok),
    .\sr_op__rc__ok$7 (\main_sr_op__rc__ok$50 ),
    .sr_op__rc__rc(main_sr_op__rc__rc),
    .\sr_op__rc__rc$6 (\main_sr_op__rc__rc$49 ),
    .sr_op__write_cr0(main_sr_op__write_cr0),
    .\sr_op__write_cr0$10 (\main_sr_op__write_cr0$53 ),
    .xer_ca(main_xer_ca),
    .xer_so(main_xer_so),
    .\xer_so$19 (\main_xer_so$62 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:167806.11-167809.4" *)
  \n$112  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:167810.11-167813.4" *)
  \p$111  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _004_ = 1'h0;
  end
  always @* begin
      \initial  <= _004_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      cr_a <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      sr_op__fn_unit <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      sr_op__imm_data__data <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__imm_data__ok <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__input_carry <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__input_cr <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      sr_op__insn <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      sr_op__insn_type <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__invert_in <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__is_32bit <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__is_signed <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__oe__oe <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__oe__ok <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__output_carry <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__output_cr <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__rc__ok <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__rc__rc <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sr_op__write_cr0 <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      xer_ca <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ca_ok <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \xer_ca$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ca <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ca_ok <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \sr_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__insn_type <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \sr_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__fn_unit <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \sr_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__imm_data__data <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \sr_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__imm_data__ok <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \sr_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__rc__rc <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \sr_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__rc__ok <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \sr_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__oe__oe <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \sr_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__oe__ok <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \sr_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__write_cr0 <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \sr_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__invert_in <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \sr_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__input_carry <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \sr_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__output_carry <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \sr_op__input_cr$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__input_cr <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \sr_op__output_cr$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__output_cr <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \sr_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__is_32bit <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \sr_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__is_signed <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \sr_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      sr_op__insn <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _101_;
    _049_ = _118_;
    (* src = "libresoc.v:167815.5-167815.29" *)
    casez (\initial )
      /* src = "libresoc.v:167815.9-167815.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _103_, _101_ } = { \xer_ca_ok$95 , \xer_ca$94  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _103_, _101_ } = { \xer_ca_ok$95 , \xer_ca$94  };
        end
      default:
        begin
          _103_ = xer_ca_ok;
          _101_ = xer_ca;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _118_ = 1'h0;
        end
      default:
          _118_ = _103_;
    endcase
  end
  always @* begin
      \xer_ca_ok$next  <= _049_;
      \xer_ca$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _111_;
    (* src = "libresoc.v:167834.5-167834.29" *)
    casez (\initial )
      /* src = "libresoc.v:167834.9-167834.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _065_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _065_ = 1'h0;
        end
      default:
          _065_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _111_ = 1'h0;
        end
      default:
          _111_ = _065_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _059_;
    (* src = "libresoc.v:167852.5-167852.29" *)
    casez (\initial )
      /* src = "libresoc.v:167852.9-167852.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _059_ = \muxid$67 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _059_ = \muxid$67 ;
        end
      default:
          _059_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _067_;
    _019_ = _073_;
    _021_ = _075_;
    _023_ = _077_;
    _025_ = _079_;
    _027_ = _081_;
    _029_ = _083_;
    _031_ = _085_;
    _037_ = _091_;
    _039_ = _093_;
    _045_ = _099_;
    _015_ = _112_;
    _017_ = _113_;
    _033_ = _114_;
    _035_ = _115_;
    _041_ = _116_;
    _043_ = _117_;
    (* src = "libresoc.v:167865.5-167865.29" *)
    casez (\initial )
      /* src = "libresoc.v:167865.9-167865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _077_, _085_, _083_, _093_, _075_, _091_, _073_, _081_, _099_, _089_, _087_, _095_, _097_, _071_, _069_, _067_, _079_ } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _077_, _085_, _083_, _093_, _075_, _091_, _073_, _081_, _099_, _089_, _087_, _095_, _097_, _071_, _069_, _067_, _079_ } = { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68  };
        end
      default:
        begin
          _067_ = sr_op__fn_unit;
          _069_ = sr_op__imm_data__data;
          _071_ = sr_op__imm_data__ok;
          _073_ = sr_op__input_carry;
          _075_ = sr_op__input_cr;
          _077_ = sr_op__insn;
          _079_ = sr_op__insn_type;
          _081_ = sr_op__invert_in;
          _083_ = sr_op__is_32bit;
          _085_ = sr_op__is_signed;
          _087_ = sr_op__oe__oe;
          _089_ = sr_op__oe__ok;
          _091_ = sr_op__output_carry;
          _093_ = sr_op__output_cr;
          _095_ = sr_op__rc__ok;
          _097_ = sr_op__rc__rc;
          _099_ = sr_op__write_cr0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _112_ = 64'h0000000000000000;
          _113_ = 1'h0;
          _117_ = 1'h0;
          _116_ = 1'h0;
          _114_ = 1'h0;
          _115_ = 1'h0;
        end
      default:
        begin
          _112_ = _069_;
          _113_ = _071_;
          _114_ = _087_;
          _115_ = _089_;
          _116_ = _095_;
          _117_ = _097_;
        end
    endcase
  end
  always @* begin
      \sr_op__fn_unit$next  <= _013_;
      \sr_op__imm_data__data$next  <= _015_;
      \sr_op__imm_data__ok$next  <= _017_;
      \sr_op__input_carry$next  <= _019_;
      \sr_op__input_cr$next  <= _021_;
      \sr_op__insn$next  <= _023_;
      \sr_op__insn_type$next  <= _025_;
      \sr_op__invert_in$next  <= _027_;
      \sr_op__is_32bit$next  <= _029_;
      \sr_op__is_signed$next  <= _031_;
      \sr_op__oe__oe$next  <= _033_;
      \sr_op__oe__ok$next  <= _035_;
      \sr_op__output_carry$next  <= _037_;
      \sr_op__output_cr$next  <= _039_;
      \sr_op__rc__ok$next  <= _041_;
      \sr_op__rc__rc$next  <= _043_;
      \sr_op__write_cr0$next  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _061_;
    _009_ = _110_;
    (* src = "libresoc.v:167906.5-167906.29" *)
    casez (\initial )
      /* src = "libresoc.v:167906.9-167906.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _063_, _061_ } = { \o_ok$86 , \o$85  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _063_, _061_ } = { \o_ok$86 , \o$85  };
        end
      default:
        begin
          _061_ = o;
          _063_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _110_ = 1'h0;
        end
      default:
          _110_ = _063_;
    endcase
  end
  always @* begin
      \o$next  <= _007_;
      \o_ok$next  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _055_;
    _002_ = _109_;
    (* src = "libresoc.v:167925.5-167925.29" *)
    casez (\initial )
      /* src = "libresoc.v:167925.9-167925.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _057_, _055_ } = { \cr_a_ok$88 , \cr_a$87  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _057_, _055_ } = { \cr_a_ok$88 , \cr_a$87  };
        end
      default:
        begin
          _055_ = cr_a;
          _057_ = cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _109_ = 1'h0;
        end
      default:
          _109_ = _057_;
    endcase
  end
  always @* begin
      \cr_a$next  <= _000_;
      \cr_a_ok$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _105_;
    _053_ = _119_;
    (* src = "libresoc.v:167944.5-167944.29" *)
    casez (\initial )
      /* src = "libresoc.v:167944.9-167944.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _107_, _105_ } = { \xer_so_ok$92 , \xer_so$91  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _107_, _105_ } = { \xer_so_ok$92 , \xer_so$91  };
        end
      default:
        begin
          _105_ = xer_so;
          _107_ = xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _119_ = 1'h0;
        end
      default:
          _119_ = _107_;
    endcase
  end
  always @* begin
      \xer_so$next  <= _051_;
      \xer_so_ok$next  <= _053_;
  end
  assign \$65  = _120_;
  assign \cr_a$89  = 4'h0;
  assign \cr_a_ok$90  = 1'h0;
  assign \xer_so_ok$93  = 1'h0;
  assign \xer_ca_ok$96  = 1'h0;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_ca_ok$95 , \xer_ca$94  } = { 1'h0, main_xer_ca };
  assign { \xer_so_ok$92 , \xer_so$91  } = { 1'h0, \main_xer_so$62  };
  assign { \cr_a_ok$88 , \cr_a$87  } = 5'h00;
  assign { \o_ok$86 , \o$85  } = { main_o_ok, main_o };
  assign { \sr_op__insn$84 , \sr_op__is_signed$83 , \sr_op__is_32bit$82 , \sr_op__output_cr$81 , \sr_op__input_cr$80 , \sr_op__output_carry$79 , \sr_op__input_carry$78 , \sr_op__invert_in$77 , \sr_op__write_cr0$76 , \sr_op__oe__ok$75 , \sr_op__oe__oe$74 , \sr_op__rc__ok$73 , \sr_op__rc__rc$72 , \sr_op__imm_data__ok$71 , \sr_op__imm_data__data$70 , \sr_op__fn_unit$69 , \sr_op__insn_type$68  } = { \main_sr_op__insn$61 , \main_sr_op__is_signed$60 , \main_sr_op__is_32bit$59 , \main_sr_op__output_cr$58 , \main_sr_op__input_cr$57 , \main_sr_op__output_carry$56 , \main_sr_op__input_carry$55 , \main_sr_op__invert_in$54 , \main_sr_op__write_cr0$53 , \main_sr_op__oe__ok$52 , \main_sr_op__oe__oe$51 , \main_sr_op__rc__ok$50 , \main_sr_op__rc__rc$49 , \main_sr_op__imm_data__ok$48 , \main_sr_op__imm_data__data$47 , \main_sr_op__fn_unit$46 , \main_sr_op__insn_type$45  };
  assign \muxid$67  = \main_muxid$44 ;
  assign p_valid_i_p_ready_o = \$65 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$64  = p_valid_i;
  assign \xer_ca$63  = \input_xer_ca$43 ;
  assign main_xer_so = \input_xer_so$42 ;
  assign main_rc = \input_rc$41 ;
  assign main_rb = \input_rb$40 ;
  assign main_ra = \input_ra$39 ;
  assign { main_sr_op__insn, main_sr_op__is_signed, main_sr_op__is_32bit, main_sr_op__output_cr, main_sr_op__input_cr, main_sr_op__output_carry, main_sr_op__input_carry, main_sr_op__invert_in, main_sr_op__write_cr0, main_sr_op__oe__ok, main_sr_op__oe__oe, main_sr_op__rc__ok, main_sr_op__rc__rc, main_sr_op__imm_data__ok, main_sr_op__imm_data__data, main_sr_op__fn_unit, main_sr_op__insn_type } = { \input_sr_op__insn$38 , \input_sr_op__is_signed$37 , \input_sr_op__is_32bit$36 , \input_sr_op__output_cr$35 , \input_sr_op__input_cr$34 , \input_sr_op__output_carry$33 , \input_sr_op__input_carry$32 , \input_sr_op__invert_in$31 , \input_sr_op__write_cr0$30 , \input_sr_op__oe__ok$29 , \input_sr_op__oe__oe$28 , \input_sr_op__rc__ok$27 , \input_sr_op__rc__rc$26 , \input_sr_op__imm_data__ok$25 , \input_sr_op__imm_data__data$24 , \input_sr_op__fn_unit$23 , \input_sr_op__insn_type$22  };
  assign main_muxid = \input_muxid$21 ;
  assign input_xer_ca = \xer_ca$20 ;
  assign input_xer_so = \xer_so$19 ;
  assign input_rc = rc;
  assign input_rb = rb;
  assign input_ra = ra;
  assign { input_sr_op__insn, input_sr_op__is_signed, input_sr_op__is_32bit, input_sr_op__output_cr, input_sr_op__input_cr, input_sr_op__output_carry, input_sr_op__input_carry, input_sr_op__invert_in, input_sr_op__write_cr0, input_sr_op__oe__ok, input_sr_op__oe__oe, input_sr_op__rc__ok, input_sr_op__rc__rc, input_sr_op__imm_data__ok, input_sr_op__imm_data__data, input_sr_op__fn_unit, input_sr_op__insn_type } = { \sr_op__insn$18 , \sr_op__is_signed$17 , \sr_op__is_32bit$16 , \sr_op__output_cr$15 , \sr_op__input_cr$14 , \sr_op__output_carry$13 , \sr_op__input_carry$12 , \sr_op__invert_in$11 , \sr_op__write_cr0$10 , \sr_op__oe__ok$9 , \sr_op__oe__oe$8 , \sr_op__rc__ok$7 , \sr_op__rc__rc$6 , \sr_op__imm_data__ok$5 , \sr_op__imm_data__data$4 , \sr_op__fn_unit$3 , \sr_op__insn_type$2  };
  assign input_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:167995.1-168843.10" *)
module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, p_valid_i, p_ready_o, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , \ra$11 , \rb$12 , \fast1$13 , \fast2$14 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:168800.3-168812.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:168656.3-168657.27" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:168813.3-168825.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:168654.3-168655.27" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:167996.7-167996.20" *)
  reg _04_;
  (* src = "libresoc.v:168740.3-168752.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:168680.3-168681.27" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:168722.3-168739.6" *)
  reg _07_;
  (* src = "libresoc.v:168682.3-168683.29" *)
  reg _08_;
  (* src = "libresoc.v:168774.3-168786.6" *)
  reg [63:0] _09_;
  (* src = "libresoc.v:168660.3-168661.21" *)
  reg [63:0] _10_;
  (* src = "libresoc.v:168787.3-168799.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:168658.3-168659.21" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:168670.3-168671.41" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [13:0] _15_;
  (* src = "libresoc.v:168664.3-168665.49" *)
  reg [13:0] _16_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [31:0] _17_;
  (* src = "libresoc.v:168666.3-168667.43" *)
  reg [31:0] _18_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [6:0] _19_;
  (* src = "libresoc.v:168662.3-168663.53" *)
  reg [6:0] _20_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg _21_;
  (* src = "libresoc.v:168672.3-168673.51" *)
  reg _22_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [7:0] _23_;
  (* src = "libresoc.v:168678.3-168679.51" *)
  reg [7:0] _24_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:168668.3-168669.41" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [12:0] _27_;
  (* src = "libresoc.v:168676.3-168677.51" *)
  reg [12:0] _28_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [7:0] _29_;
  (* src = "libresoc.v:168674.3-168675.51" *)
  reg [7:0] _30_;
  (* src = "libresoc.v:168800.3-168812.6" *)
  reg [63:0] _31_;
  (* src = "libresoc.v:168241.14-168241.42" *)
  reg [63:0] _32_;
  (* src = "libresoc.v:168813.3-168825.6" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:168250.14-168250.42" *)
  reg [63:0] _34_;
  (* src = "libresoc.v:168740.3-168752.6" *)
  reg [1:0] _35_;
  (* src = "libresoc.v:168259.13-168259.25" *)
  reg [1:0] _36_;
  (* src = "libresoc.v:168722.3-168739.6" *)
  reg _37_;
  (* src = "libresoc.v:168281.7-168281.20" *)
  reg _38_;
  (* src = "libresoc.v:168774.3-168786.6" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:168286.14-168286.39" *)
  reg [63:0] _40_;
  (* src = "libresoc.v:168787.3-168799.6" *)
  reg [63:0] _41_;
  (* src = "libresoc.v:168295.14-168295.39" *)
  reg [63:0] _42_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [63:0] _43_;
  (* src = "libresoc.v:168304.14-168304.49" *)
  reg [63:0] _44_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [13:0] _45_;
  (* src = "libresoc.v:168328.14-168328.41" *)
  reg [13:0] _46_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [31:0] _47_;
  (* src = "libresoc.v:168367.14-168367.35" *)
  reg [31:0] _48_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [6:0] _49_;
  (* src = "libresoc.v:168451.13-168451.39" *)
  reg [6:0] _50_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg _51_;
  (* src = "libresoc.v:168610.7-168610.31" *)
  reg _52_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [7:0] _53_;
  (* src = "libresoc.v:168619.13-168619.38" *)
  reg [7:0] _54_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:168628.14-168628.49" *)
  reg [63:0] _56_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [12:0] _57_;
  (* src = "libresoc.v:168637.14-168637.42" *)
  reg [12:0] _58_;
  (* src = "libresoc.v:168753.3-168773.6" *)
  reg [7:0] _59_;
  (* src = "libresoc.v:168646.13-168646.38" *)
  reg [7:0] _60_;
  (* src = "libresoc.v:168722.3-168739.6" *)
  reg _61_;
  (* src = "libresoc.v:168653.18-168653.118" *)
  wire _62_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] dummy_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \dummy_fast1$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] dummy_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \dummy_fast2$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] dummy_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \dummy_muxid$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] dummy_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \dummy_ra$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] dummy_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \dummy_rb$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dummy_trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \dummy_trap_op__cia$20 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] dummy_trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \dummy_trap_op__fn_unit$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] dummy_trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \dummy_trap_op__insn$18 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] dummy_trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \dummy_trap_op__insn_type$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire dummy_trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \dummy_trap_op__is_32bit$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] dummy_trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \dummy_trap_op__ldst_exc$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] dummy_trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \dummy_trap_op__msr$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] dummy_trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \dummy_trap_op__trapaddr$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] dummy_trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \dummy_trap_op__traptype$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] fast1;
  reg [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast1$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \fast1$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \fast1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] fast2;
  reg [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \fast2$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \fast2$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \fast2$next ;
  (* src = "libresoc.v:167996.7-167996.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$32 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] ra;
  reg [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \ra$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \ra$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \ra$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] rb;
  reg [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \rb$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \rb$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \rb$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] trap_op__cia;
  reg [63:0] trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__cia$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \trap_op__cia$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \trap_op__cia$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] trap_op__fn_unit;
  reg [13:0] trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \trap_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \trap_op__fn_unit$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \trap_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] trap_op__insn;
  reg [31:0] trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \trap_op__insn$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \trap_op__insn$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \trap_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] trap_op__insn_type;
  reg [6:0] trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \trap_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \trap_op__insn_type$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \trap_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output trap_op__is_32bit;
  reg trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \trap_op__is_32bit$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \trap_op__is_32bit$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \trap_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] trap_op__ldst_exc;
  reg [7:0] trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] \trap_op__ldst_exc$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__ldst_exc$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \trap_op__ldst_exc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] trap_op__msr;
  reg [63:0] trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__msr$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \trap_op__msr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \trap_op__msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [12:0] trap_op__trapaddr;
  reg [12:0] trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \trap_op__trapaddr$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] \trap_op__trapaddr$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [12:0] \trap_op__trapaddr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] trap_op__traptype;
  reg [7:0] trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__traptype$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] \trap_op__traptype$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \trap_op__traptype$next ;
  assign _62_ = \p_valid_i$29  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:168684.9-168713.4" *)
  dummy dummy (
    .fast1(dummy_fast1),
    .\fast1$13 (\dummy_fast1$27 ),
    .fast2(dummy_fast2),
    .\fast2$14 (\dummy_fast2$28 ),
    .muxid(dummy_muxid),
    .\muxid$1 (\dummy_muxid$15 ),
    .ra(dummy_ra),
    .\ra$11 (\dummy_ra$25 ),
    .rb(dummy_rb),
    .\rb$12 (\dummy_rb$26 ),
    .trap_op__cia(dummy_trap_op__cia),
    .\trap_op__cia$6 (\dummy_trap_op__cia$20 ),
    .trap_op__fn_unit(dummy_trap_op__fn_unit),
    .\trap_op__fn_unit$3 (\dummy_trap_op__fn_unit$17 ),
    .trap_op__insn(dummy_trap_op__insn),
    .\trap_op__insn$4 (\dummy_trap_op__insn$18 ),
    .trap_op__insn_type(dummy_trap_op__insn_type),
    .\trap_op__insn_type$2 (\dummy_trap_op__insn_type$16 ),
    .trap_op__is_32bit(dummy_trap_op__is_32bit),
    .\trap_op__is_32bit$7 (\dummy_trap_op__is_32bit$21 ),
    .trap_op__ldst_exc(dummy_trap_op__ldst_exc),
    .\trap_op__ldst_exc$10 (\dummy_trap_op__ldst_exc$24 ),
    .trap_op__msr(dummy_trap_op__msr),
    .\trap_op__msr$5 (\dummy_trap_op__msr$19 ),
    .trap_op__trapaddr(dummy_trap_op__trapaddr),
    .\trap_op__trapaddr$9 (\dummy_trap_op__trapaddr$23 ),
    .trap_op__traptype(dummy_trap_op__traptype),
    .\trap_op__traptype$8 (\dummy_trap_op__traptype$22 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:168714.10-168717.4" *)
  \n$34  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:168718.10-168721.4" *)
  \p$33  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
      \initial  <= _04_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _32_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      fast1 <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _34_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      fast2 <= _34_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _40_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ra <= _40_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      rb <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      trap_op__cia <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _46_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      trap_op__fn_unit <= _46_;
  end
  always @* begin
    if (\initial ) begin end
    _48_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      trap_op__insn <= _48_;
  end
  always @* begin
    if (\initial ) begin end
    _50_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      trap_op__insn_type <= _50_;
  end
  always @* begin
    if (\initial ) begin end
    _52_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      trap_op__is_32bit <= _52_;
  end
  always @* begin
    if (\initial ) begin end
    _54_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      trap_op__ldst_exc <= _54_;
  end
  always @* begin
    if (\initial ) begin end
    _56_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      trap_op__msr <= _56_;
  end
  always @* begin
    if (\initial ) begin end
    _58_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      trap_op__trapaddr <= _58_;
  end
  always @* begin
    if (\initial ) begin end
    _60_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      trap_op__traptype <= _60_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = \fast2$next ;
  end
  always @(posedge coresync_clk) begin
      fast2 <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \fast1$next ;
  end
  always @(posedge coresync_clk) begin
      fast1 <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \rb$next ;
  end
  always @(posedge coresync_clk) begin
      rb <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \ra$next ;
  end
  always @(posedge coresync_clk) begin
      ra <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = \trap_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__insn_type <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \trap_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__fn_unit <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = \trap_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__insn <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = \trap_op__msr$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__msr <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = \trap_op__cia$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__cia <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = \trap_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__is_32bit <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = \trap_op__traptype$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__traptype <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = \trap_op__trapaddr$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__trapaddr <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = \trap_op__ldst_exc$next ;
  end
  always @(posedge coresync_clk) begin
      trap_op__ldst_exc <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _61_;
    (* src = "libresoc.v:168723.5-168723.29" *)
    casez (\initial )
      /* src = "libresoc.v:168723.9-168723.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _37_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _37_ = 1'h0;
        end
      default:
          _37_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _61_ = 1'h0;
        end
      default:
          _61_ = _37_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _35_;
    (* src = "libresoc.v:168741.5-168741.29" *)
    casez (\initial )
      /* src = "libresoc.v:168741.9-168741.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _35_ = \muxid$32 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _35_ = \muxid$32 ;
        end
      default:
          _35_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _43_;
    _15_ = _45_;
    _17_ = _47_;
    _19_ = _49_;
    _21_ = _51_;
    _23_ = _53_;
    _25_ = _55_;
    _27_ = _57_;
    _29_ = _59_;
    (* src = "libresoc.v:168754.5-168754.29" *)
    casez (\initial )
      /* src = "libresoc.v:168754.9-168754.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _53_, _57_, _59_, _51_, _43_, _55_, _47_, _45_, _49_ } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _53_, _57_, _59_, _51_, _43_, _55_, _47_, _45_, _49_ } = { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33  };
        end
      default:
        begin
          _43_ = trap_op__cia;
          _45_ = trap_op__fn_unit;
          _47_ = trap_op__insn;
          _49_ = trap_op__insn_type;
          _51_ = trap_op__is_32bit;
          _53_ = trap_op__ldst_exc;
          _55_ = trap_op__msr;
          _57_ = trap_op__trapaddr;
          _59_ = trap_op__traptype;
        end
    endcase
  end
  always @* begin
      \trap_op__cia$next  <= _13_;
      \trap_op__fn_unit$next  <= _15_;
      \trap_op__insn$next  <= _17_;
      \trap_op__insn_type$next  <= _19_;
      \trap_op__is_32bit$next  <= _21_;
      \trap_op__ldst_exc$next  <= _23_;
      \trap_op__msr$next  <= _25_;
      \trap_op__trapaddr$next  <= _27_;
      \trap_op__traptype$next  <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _39_;
    (* src = "libresoc.v:168775.5-168775.29" *)
    casez (\initial )
      /* src = "libresoc.v:168775.9-168775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _39_ = \ra$42 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _39_ = \ra$42 ;
        end
      default:
          _39_ = ra;
    endcase
  end
  always @* begin
      \ra$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _41_;
    (* src = "libresoc.v:168788.5-168788.29" *)
    casez (\initial )
      /* src = "libresoc.v:168788.9-168788.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _41_ = \rb$43 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _41_ = \rb$43 ;
        end
      default:
          _41_ = rb;
    endcase
  end
  always @* begin
      \rb$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _31_;
    (* src = "libresoc.v:168801.5-168801.29" *)
    casez (\initial )
      /* src = "libresoc.v:168801.9-168801.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _31_ = \fast1$44 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _31_ = \fast1$44 ;
        end
      default:
          _31_ = fast1;
    endcase
  end
  always @* begin
      \fast1$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _33_;
    (* src = "libresoc.v:168814.5-168814.29" *)
    casez (\initial )
      /* src = "libresoc.v:168814.9-168814.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _33_ = \fast2$45 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _33_ = \fast2$45 ;
        end
      default:
          _33_ = fast2;
    endcase
  end
  always @* begin
      \fast2$next  <= _02_;
  end
  assign \$30  = _62_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign \fast2$45  = \dummy_fast2$28 ;
  assign \fast1$44  = \dummy_fast1$27 ;
  assign \rb$43  = \dummy_rb$26 ;
  assign \ra$42  = \dummy_ra$25 ;
  assign { \trap_op__ldst_exc$41 , \trap_op__trapaddr$40 , \trap_op__traptype$39 , \trap_op__is_32bit$38 , \trap_op__cia$37 , \trap_op__msr$36 , \trap_op__insn$35 , \trap_op__fn_unit$34 , \trap_op__insn_type$33  } = { \dummy_trap_op__ldst_exc$24 , \dummy_trap_op__trapaddr$23 , \dummy_trap_op__traptype$22 , \dummy_trap_op__is_32bit$21 , \dummy_trap_op__cia$20 , \dummy_trap_op__msr$19 , \dummy_trap_op__insn$18 , \dummy_trap_op__fn_unit$17 , \dummy_trap_op__insn_type$16  };
  assign \muxid$32  = \dummy_muxid$15 ;
  assign p_valid_i_p_ready_o = \$30 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$29  = p_valid_i;
  assign dummy_fast2 = \fast2$14 ;
  assign dummy_fast1 = \fast1$13 ;
  assign dummy_rb = \rb$12 ;
  assign dummy_ra = \ra$11 ;
  assign { dummy_trap_op__ldst_exc, dummy_trap_op__trapaddr, dummy_trap_op__traptype, dummy_trap_op__is_32bit, dummy_trap_op__cia, dummy_trap_op__msr, dummy_trap_op__insn, dummy_trap_op__fn_unit, dummy_trap_op__insn_type } = { \trap_op__ldst_exc$10 , \trap_op__trapaddr$9 , \trap_op__traptype$8 , \trap_op__is_32bit$7 , \trap_op__cia$6 , \trap_op__msr$5 , \trap_op__insn$4 , \trap_op__fn_unit$3 , \trap_op__insn_type$2  };
  assign dummy_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:168847.1-170032.10" *)
module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_op__fn_unit, alu_op__imm_data__data, alu_op__imm_data__ok, alu_op__rc__rc, alu_op__rc__ok, alu_op__oe__oe, alu_op__oe__ok, alu_op__invert_in, alu_op__zero_a, alu_op__invert_out, alu_op__write_cr0, alu_op__input_carry, alu_op__output_carry, alu_op__is_32bit, alu_op__is_signed, alu_op__data_len, alu_op__insn, o, o_ok, cr_a, cr_a_ok, xer_ca, xer_ca_ok, xer_ov, xer_ov_ok, xer_so, xer_so_ok, n_valid_o, n_ready_i, \muxid$1 , \alu_op__insn_type$2 , \alu_op__fn_unit$3 , \alu_op__imm_data__data$4 , \alu_op__imm_data__ok$5 , \alu_op__rc__rc$6 , \alu_op__rc__ok$7 , \alu_op__oe__oe$8 , \alu_op__oe__ok$9 , \alu_op__invert_in$10 , \alu_op__zero_a$11 , \alu_op__invert_out$12 , \alu_op__write_cr0$13 , \alu_op__input_carry$14 , \alu_op__output_carry$15 , \alu_op__is_32bit$16 , \alu_op__is_signed$17 , \alu_op__data_len$18 , \alu_op__insn$19 , \o$20 , \o_ok$21 , \cr_a$22 , \cr_a_ok$23 , \xer_ca$24 , \xer_ca_ok$25 , \xer_ov$26 , \xer_ov_ok$27 , \xer_so$28 , \xer_so_ok$29 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:169773.3-169774.57" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:168855.13-168855.41" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [13:0] _003_;
  (* src = "libresoc.v:169743.3-169744.53" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:168894.14-168894.44" *)
  reg [13:0] _005_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:169745.3-169746.67" *)
  reg [63:0] _007_;
  (* src = "libresoc.v:168918.14-168918.63" *)
  reg [63:0] _008_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _009_;
  (* src = "libresoc.v:169747.3-169748.63" *)
  reg _010_;
  (* src = "libresoc.v:168927.7-168927.38" *)
  reg _011_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [1:0] _012_;
  (* src = "libresoc.v:169765.3-169766.63" *)
  reg [1:0] _013_;
  (* src = "libresoc.v:168944.13-168944.44" *)
  reg [1:0] _014_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [31:0] _015_;
  (* src = "libresoc.v:169775.3-169776.49" *)
  reg [31:0] _016_;
  (* src = "libresoc.v:168957.14-168957.39" *)
  reg [31:0] _017_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [6:0] _018_;
  (* src = "libresoc.v:169741.3-169742.57" *)
  reg [6:0] _019_;
  (* src = "libresoc.v:169116.13-169116.42" *)
  reg [6:0] _020_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _021_;
  (* src = "libresoc.v:169757.3-169758.59" *)
  reg _022_;
  (* src = "libresoc.v:169200.7-169200.36" *)
  reg _023_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _024_;
  (* src = "libresoc.v:169761.3-169762.61" *)
  reg _025_;
  (* src = "libresoc.v:169209.7-169209.37" *)
  reg _026_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _027_;
  (* src = "libresoc.v:169769.3-169770.57" *)
  reg _028_;
  (* src = "libresoc.v:169218.7-169218.35" *)
  reg _029_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _030_;
  (* src = "libresoc.v:169771.3-169772.59" *)
  reg _031_;
  (* src = "libresoc.v:169227.7-169227.36" *)
  reg _032_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _033_;
  (* src = "libresoc.v:169753.3-169754.51" *)
  reg _034_;
  (* src = "libresoc.v:169238.7-169238.32" *)
  reg _035_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _036_;
  (* src = "libresoc.v:169755.3-169756.51" *)
  reg _037_;
  (* src = "libresoc.v:169247.7-169247.32" *)
  reg _038_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _039_;
  (* src = "libresoc.v:169767.3-169768.65" *)
  reg _040_;
  (* src = "libresoc.v:169254.7-169254.39" *)
  reg _041_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _042_;
  (* src = "libresoc.v:169751.3-169752.51" *)
  reg _043_;
  (* src = "libresoc.v:169265.7-169265.32" *)
  reg _044_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _045_;
  (* src = "libresoc.v:169749.3-169750.51" *)
  reg _046_;
  (* src = "libresoc.v:169272.7-169272.32" *)
  reg _047_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _048_;
  (* src = "libresoc.v:169763.3-169764.59" *)
  reg _049_;
  (* src = "libresoc.v:169281.7-169281.36" *)
  reg _050_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _051_;
  (* src = "libresoc.v:169759.3-169760.53" *)
  reg _052_;
  (* src = "libresoc.v:169290.7-169290.33" *)
  reg _053_;
  (* src = "libresoc.v:169937.3-169955.6" *)
  reg [3:0] _054_;
  (* src = "libresoc.v:169733.3-169734.33" *)
  reg [3:0] _055_;
  (* src = "libresoc.v:169303.13-169303.29" *)
  reg [3:0] _056_;
  (* src = "libresoc.v:169937.3-169955.6" *)
  reg _057_;
  (* src = "libresoc.v:169735.3-169736.39" *)
  reg _058_;
  (* src = "libresoc.v:169312.7-169312.26" *)
  reg _059_;
  (* src = "libresoc.v:168848.7-168848.20" *)
  reg _060_;
  (* src = "libresoc.v:169863.3-169875.6" *)
  reg [1:0] _061_;
  (* src = "libresoc.v:169777.3-169778.33" *)
  reg [1:0] _062_;
  (* src = "libresoc.v:169323.13-169323.29" *)
  reg [1:0] _063_;
  (* src = "libresoc.v:169918.3-169936.6" *)
  reg [63:0] _064_;
  (* src = "libresoc.v:169737.3-169738.27" *)
  reg [63:0] _065_;
  (* src = "libresoc.v:169338.14-169338.43" *)
  reg [63:0] _066_;
  (* src = "libresoc.v:169918.3-169936.6" *)
  reg _067_;
  (* src = "libresoc.v:169739.3-169740.33" *)
  reg _068_;
  (* src = "libresoc.v:169347.7-169347.23" *)
  reg _069_;
  (* src = "libresoc.v:169845.3-169862.6" *)
  reg _070_;
  (* src = "libresoc.v:169779.3-169780.29" *)
  reg _071_;
  (* src = "libresoc.v:169956.3-169974.6" *)
  reg [1:0] _072_;
  (* src = "libresoc.v:169729.3-169730.37" *)
  reg [1:0] _073_;
  (* src = "libresoc.v:169664.13-169664.31" *)
  reg [1:0] _074_;
  (* src = "libresoc.v:169956.3-169974.6" *)
  reg _075_;
  (* src = "libresoc.v:169731.3-169732.43" *)
  reg _076_;
  (* src = "libresoc.v:169673.7-169673.28" *)
  reg _077_;
  (* src = "libresoc.v:169975.3-169993.6" *)
  reg [1:0] _078_;
  (* src = "libresoc.v:169725.3-169726.37" *)
  reg [1:0] _079_;
  (* src = "libresoc.v:169684.13-169684.31" *)
  reg [1:0] _080_;
  (* src = "libresoc.v:169975.3-169993.6" *)
  reg _081_;
  (* src = "libresoc.v:169727.3-169728.43" *)
  reg _082_;
  (* src = "libresoc.v:169693.7-169693.28" *)
  reg _083_;
  (* src = "libresoc.v:169994.3-170012.6" *)
  reg _084_;
  (* src = "libresoc.v:169721.3-169722.37" *)
  reg _085_;
  (* src = "libresoc.v:169704.7-169704.25" *)
  reg _086_;
  (* src = "libresoc.v:169994.3-170012.6" *)
  reg _087_;
  (* src = "libresoc.v:169723.3-169724.43" *)
  reg _088_;
  (* src = "libresoc.v:169713.7-169713.28" *)
  reg _089_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [3:0] _090_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [13:0] _091_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [63:0] _092_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _093_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [1:0] _094_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [31:0] _095_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [6:0] _096_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _097_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _098_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _099_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _100_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _101_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _102_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _103_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _104_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _105_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _106_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _107_;
  (* src = "libresoc.v:169937.3-169955.6" *)
  reg [3:0] _108_;
  (* src = "libresoc.v:169937.3-169955.6" *)
  reg _109_;
  (* src = "libresoc.v:169863.3-169875.6" *)
  reg [1:0] _110_;
  (* src = "libresoc.v:169918.3-169936.6" *)
  reg [63:0] _111_;
  (* src = "libresoc.v:169918.3-169936.6" *)
  reg _112_;
  (* src = "libresoc.v:169845.3-169862.6" *)
  reg _113_;
  (* src = "libresoc.v:169657.7-169657.20" *)
  reg _114_;
  (* src = "libresoc.v:169956.3-169974.6" *)
  reg [1:0] _115_;
  (* src = "libresoc.v:169956.3-169974.6" *)
  reg _116_;
  (* src = "libresoc.v:169975.3-169993.6" *)
  reg [1:0] _117_;
  (* src = "libresoc.v:169975.3-169993.6" *)
  reg _118_;
  (* src = "libresoc.v:169994.3-170012.6" *)
  reg _119_;
  (* src = "libresoc.v:169994.3-170012.6" *)
  reg _120_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg [63:0] _121_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _122_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _123_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _124_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _125_;
  (* src = "libresoc.v:169876.3-169917.6" *)
  reg _126_;
  (* src = "libresoc.v:169937.3-169955.6" *)
  reg _127_;
  (* src = "libresoc.v:169918.3-169936.6" *)
  reg _128_;
  (* src = "libresoc.v:169845.3-169862.6" *)
  reg _129_;
  (* src = "libresoc.v:169956.3-169974.6" *)
  reg _130_;
  (* src = "libresoc.v:169975.3-169993.6" *)
  reg _131_;
  (* src = "libresoc.v:169994.3-170012.6" *)
  reg _132_;
  (* src = "libresoc.v:169720.18-169720.118" *)
  wire _133_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \alu_op__data_len$18 ;
  reg [3:0] \alu_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \alu_op__data_len$18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \alu_op__data_len$79 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \alu_op__fn_unit$3 ;
  reg [13:0] \alu_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \alu_op__fn_unit$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \alu_op__imm_data__data$4 ;
  reg [63:0] \alu_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \alu_op__imm_data__data$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__imm_data__ok$5 ;
  reg \alu_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__imm_data__ok$66 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \alu_op__input_carry$14 ;
  reg [1:0] \alu_op__input_carry$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_op__input_carry$14$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \alu_op__input_carry$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \alu_op__insn$19 ;
  reg [31:0] \alu_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_op__insn$19$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \alu_op__insn$80 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \alu_op__insn_type$2 ;
  reg [6:0] \alu_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \alu_op__insn_type$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_in$10 ;
  reg \alu_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__invert_in$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_in$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__invert_out$12 ;
  reg \alu_op__invert_out$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__invert_out$12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__invert_out$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_32bit$16 ;
  reg \alu_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__is_32bit$16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_32bit$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__is_signed$17 ;
  reg \alu_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__is_signed$17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__is_signed$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__oe$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__oe$8 ;
  reg \alu_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__oe__ok$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__oe__ok$9 ;
  reg \alu_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__output_carry$15 ;
  reg \alu_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__output_carry$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__output_carry$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__ok$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__ok$7 ;
  reg \alu_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__rc__rc$6 ;
  reg \alu_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__rc__rc$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__write_cr0$13 ;
  reg \alu_op__write_cr0$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__write_cr0$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__write_cr0$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \alu_op__zero_a$11 ;
  reg \alu_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_op__zero_a$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \alu_op__zero_a$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$22 ;
  reg [3:0] \cr_a$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$22$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$23 ;
  reg \cr_a_ok$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$23$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$84 ;
  (* src = "libresoc.v:168848.7-168848.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$62 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$20 ;
  reg [63:0] \o$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$20$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$21 ;
  reg \o_ok$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$21$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] output_alu_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \output_alu_op__data_len$47 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_alu_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_alu_op__fn_unit$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_alu_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_alu_op__imm_data__data$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__imm_data__ok$34 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] output_alu_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \output_alu_op__input_carry$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_alu_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_alu_op__insn$48 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_alu_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_alu_op__insn_type$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__invert_in$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__invert_out$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__is_32bit$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__is_signed$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__oe__oe$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__oe__ok$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__output_carry$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__rc__ok$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__rc__rc$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__write_cr0$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_alu_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_alu_op__zero_a$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] output_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \output_cr_a$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_muxid$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \output_o$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_o_ok$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \output_xer_ca$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \output_xer_ov$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_xer_so$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$59 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$24 ;
  reg [1:0] \xer_ca$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ca$24$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ca$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ca_ok$25 ;
  reg \xer_ca_ok$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ca_ok$25$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$26 ;
  reg [1:0] \xer_ov$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ov$26$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ov$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ov_ok$27 ;
  reg \xer_ov_ok$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ov_ok$27$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$28 ;
  reg \xer_so$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$28$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so_ok$29 ;
  reg \xer_so_ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$29$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$90 ;
  assign _133_ = \p_valid_i$59  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:169781.9-169784.4" *)
  \n$4  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:169785.12-169840.4" *)
  \output  \output  (
    .alu_op__data_len(output_alu_op__data_len),
    .\alu_op__data_len$18 (\output_alu_op__data_len$47 ),
    .alu_op__fn_unit(output_alu_op__fn_unit),
    .\alu_op__fn_unit$3 (\output_alu_op__fn_unit$32 ),
    .alu_op__imm_data__data(output_alu_op__imm_data__data),
    .\alu_op__imm_data__data$4 (\output_alu_op__imm_data__data$33 ),
    .alu_op__imm_data__ok(output_alu_op__imm_data__ok),
    .\alu_op__imm_data__ok$5 (\output_alu_op__imm_data__ok$34 ),
    .alu_op__input_carry(output_alu_op__input_carry),
    .\alu_op__input_carry$14 (\output_alu_op__input_carry$43 ),
    .alu_op__insn(output_alu_op__insn),
    .\alu_op__insn$19 (\output_alu_op__insn$48 ),
    .alu_op__insn_type(output_alu_op__insn_type),
    .\alu_op__insn_type$2 (\output_alu_op__insn_type$31 ),
    .alu_op__invert_in(output_alu_op__invert_in),
    .\alu_op__invert_in$10 (\output_alu_op__invert_in$39 ),
    .alu_op__invert_out(output_alu_op__invert_out),
    .\alu_op__invert_out$12 (\output_alu_op__invert_out$41 ),
    .alu_op__is_32bit(output_alu_op__is_32bit),
    .\alu_op__is_32bit$16 (\output_alu_op__is_32bit$45 ),
    .alu_op__is_signed(output_alu_op__is_signed),
    .\alu_op__is_signed$17 (\output_alu_op__is_signed$46 ),
    .alu_op__oe__oe(output_alu_op__oe__oe),
    .\alu_op__oe__oe$8 (\output_alu_op__oe__oe$37 ),
    .alu_op__oe__ok(output_alu_op__oe__ok),
    .\alu_op__oe__ok$9 (\output_alu_op__oe__ok$38 ),
    .alu_op__output_carry(output_alu_op__output_carry),
    .\alu_op__output_carry$15 (\output_alu_op__output_carry$44 ),
    .alu_op__rc__ok(output_alu_op__rc__ok),
    .\alu_op__rc__ok$7 (\output_alu_op__rc__ok$36 ),
    .alu_op__rc__rc(output_alu_op__rc__rc),
    .\alu_op__rc__rc$6 (\output_alu_op__rc__rc$35 ),
    .alu_op__write_cr0(output_alu_op__write_cr0),
    .\alu_op__write_cr0$13 (\output_alu_op__write_cr0$42 ),
    .alu_op__zero_a(output_alu_op__zero_a),
    .\alu_op__zero_a$11 (\output_alu_op__zero_a$40 ),
    .cr_a(output_cr_a),
    .\cr_a$22 (\output_cr_a$51 ),
    .cr_a_ok(output_cr_a_ok),
    .muxid(output_muxid),
    .\muxid$1 (\output_muxid$30 ),
    .o(output_o),
    .\o$20 (\output_o$49 ),
    .o_ok(output_o_ok),
    .\o_ok$21 (\output_o_ok$50 ),
    .xer_ca(output_xer_ca),
    .\xer_ca$23 (\output_xer_ca$52 ),
    .xer_ca_ok(output_xer_ca_ok),
    .xer_ov(output_xer_ov),
    .\xer_ov$24 (\output_xer_ov$53 ),
    .xer_ov_ok(output_xer_ov_ok),
    .xer_so(output_xer_so),
    .\xer_so$25 (\output_xer_so$54 ),
    .xer_so_ok(output_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:169841.9-169844.4" *)
  \p$3  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _060_ = 1'h0;
  end
  always @* begin
      \initial  <= _060_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _002_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__data_len$18  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \alu_op__fn_unit$3  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \alu_op__imm_data__data$4  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__imm_data__ok$5  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__input_carry$14  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \alu_op__insn$19  <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \alu_op__insn_type$2  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__invert_in$10  <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__invert_out$12  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__is_32bit$16  <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__is_signed$17  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__oe__oe$8  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__oe__ok$9  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__output_carry$15  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__rc__ok$7  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__rc__rc$6  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__write_cr0$13  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \alu_op__zero_a$11  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a$22  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a_ok$23  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \o$20  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \o_ok$21  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ca$24  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ca_ok$25  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ov$26  <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ov_ok$27  <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$28  <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so_ok$29  <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = \xer_so$28$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$28  <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = \xer_so_ok$29$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so_ok$29  <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \xer_ov$26$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ov$26  <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = \xer_ov_ok$27$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ov_ok$27  <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \xer_ca$24$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ca$24  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \xer_ca_ok$25$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ca_ok$25  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \cr_a$22$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a$22  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \cr_a_ok$23$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a_ok$23  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \o$20$next ;
  end
  always @(posedge coresync_clk) begin
      \o$20  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \o_ok$21$next ;
  end
  always @(posedge coresync_clk) begin
      \o_ok$21  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__insn_type$2  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \alu_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__fn_unit$3  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__imm_data__data$4  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = \alu_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__imm_data__ok$5  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \alu_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__rc__rc$6  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \alu_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__rc__ok$7  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \alu_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__oe__oe$8  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \alu_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__oe__ok$9  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \alu_op__invert_in$10$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__invert_in$10  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \alu_op__zero_a$11$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__zero_a$11  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \alu_op__invert_out$12$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__invert_out$12  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \alu_op__write_cr0$13$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__write_cr0$13  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_op__input_carry$14$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__input_carry$14  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \alu_op__output_carry$15$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__output_carry$15  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \alu_op__is_32bit$16$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__is_32bit$16  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \alu_op__is_signed$17$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__is_signed$17  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \alu_op__data_len$18$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__data_len$18  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \alu_op__insn$19$next ;
  end
  always @(posedge coresync_clk) begin
      \alu_op__insn$19  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _129_;
    (* src = "libresoc.v:169846.5-169846.29" *)
    casez (\initial )
      /* src = "libresoc.v:169846.9-169846.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _113_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _113_ = 1'h0;
        end
      default:
          _113_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = 1'h0;
        end
      default:
          _129_ = _113_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _110_;
    (* src = "libresoc.v:169864.5-169864.29" *)
    casez (\initial )
      /* src = "libresoc.v:169864.9-169864.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _110_ = \muxid$62 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _110_ = \muxid$62 ;
        end
      default:
          _110_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _090_;
    _003_ = _091_;
    _012_ = _094_;
    _015_ = _095_;
    _018_ = _096_;
    _021_ = _097_;
    _024_ = _098_;
    _027_ = _099_;
    _030_ = _100_;
    _039_ = _103_;
    _048_ = _106_;
    _051_ = _107_;
    _006_ = _121_;
    _009_ = _122_;
    _033_ = _123_;
    _036_ = _124_;
    _042_ = _125_;
    _045_ = _126_;
    (* src = "libresoc.v:169877.5-169877.29" *)
    casez (\initial )
      /* src = "libresoc.v:169877.9-169877.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _095_, _090_, _100_, _099_, _103_, _094_, _106_, _098_, _107_, _097_, _102_, _101_, _104_, _105_, _093_, _092_, _091_, _096_ } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _095_, _090_, _100_, _099_, _103_, _094_, _106_, _098_, _107_, _097_, _102_, _101_, _104_, _105_, _093_, _092_, _091_, _096_ } = { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63  };
        end
      default:
        begin
          _090_ = \alu_op__data_len$18 ;
          _091_ = \alu_op__fn_unit$3 ;
          _092_ = \alu_op__imm_data__data$4 ;
          _093_ = \alu_op__imm_data__ok$5 ;
          _094_ = \alu_op__input_carry$14 ;
          _095_ = \alu_op__insn$19 ;
          _096_ = \alu_op__insn_type$2 ;
          _097_ = \alu_op__invert_in$10 ;
          _098_ = \alu_op__invert_out$12 ;
          _099_ = \alu_op__is_32bit$16 ;
          _100_ = \alu_op__is_signed$17 ;
          _101_ = \alu_op__oe__oe$8 ;
          _102_ = \alu_op__oe__ok$9 ;
          _103_ = \alu_op__output_carry$15 ;
          _104_ = \alu_op__rc__ok$7 ;
          _105_ = \alu_op__rc__rc$6 ;
          _106_ = \alu_op__write_cr0$13 ;
          _107_ = \alu_op__zero_a$11 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = 64'h0000000000000000;
          _122_ = 1'h0;
          _126_ = 1'h0;
          _125_ = 1'h0;
          _123_ = 1'h0;
          _124_ = 1'h0;
        end
      default:
        begin
          _121_ = _092_;
          _122_ = _093_;
          _123_ = _101_;
          _124_ = _102_;
          _125_ = _104_;
          _126_ = _105_;
        end
    endcase
  end
  always @* begin
      \alu_op__data_len$18$next  <= _000_;
      \alu_op__fn_unit$3$next  <= _003_;
      \alu_op__imm_data__data$4$next  <= _006_;
      \alu_op__imm_data__ok$5$next  <= _009_;
      \alu_op__input_carry$14$next  <= _012_;
      \alu_op__insn$19$next  <= _015_;
      \alu_op__insn_type$2$next  <= _018_;
      \alu_op__invert_in$10$next  <= _021_;
      \alu_op__invert_out$12$next  <= _024_;
      \alu_op__is_32bit$16$next  <= _027_;
      \alu_op__is_signed$17$next  <= _030_;
      \alu_op__oe__oe$8$next  <= _033_;
      \alu_op__oe__ok$9$next  <= _036_;
      \alu_op__output_carry$15$next  <= _039_;
      \alu_op__rc__ok$7$next  <= _042_;
      \alu_op__rc__rc$6$next  <= _045_;
      \alu_op__write_cr0$13$next  <= _048_;
      \alu_op__zero_a$11$next  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _111_;
    _067_ = _128_;
    (* src = "libresoc.v:169919.5-169919.29" *)
    casez (\initial )
      /* src = "libresoc.v:169919.9-169919.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _112_, _111_ } = { \o_ok$82 , \o$81  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _112_, _111_ } = { \o_ok$82 , \o$81  };
        end
      default:
        begin
          _111_ = \o$20 ;
          _112_ = \o_ok$21 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = 1'h0;
        end
      default:
          _128_ = _112_;
    endcase
  end
  always @* begin
      \o$20$next  <= _064_;
      \o_ok$21$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _108_;
    _057_ = _127_;
    (* src = "libresoc.v:169938.5-169938.29" *)
    casez (\initial )
      /* src = "libresoc.v:169938.9-169938.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _109_, _108_ } = { \cr_a_ok$84 , \cr_a$83  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _109_, _108_ } = { \cr_a_ok$84 , \cr_a$83  };
        end
      default:
        begin
          _108_ = \cr_a$22 ;
          _109_ = \cr_a_ok$23 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = 1'h0;
        end
      default:
          _127_ = _109_;
    endcase
  end
  always @* begin
      \cr_a$22$next  <= _054_;
      \cr_a_ok$23$next  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _115_;
    _075_ = _130_;
    (* src = "libresoc.v:169957.5-169957.29" *)
    casez (\initial )
      /* src = "libresoc.v:169957.9-169957.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _116_, _115_ } = { \xer_ca_ok$86 , \xer_ca$85  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _116_, _115_ } = { \xer_ca_ok$86 , \xer_ca$85  };
        end
      default:
        begin
          _115_ = \xer_ca$24 ;
          _116_ = \xer_ca_ok$25 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h0;
        end
      default:
          _130_ = _116_;
    endcase
  end
  always @* begin
      \xer_ca$24$next  <= _072_;
      \xer_ca_ok$25$next  <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = _117_;
    _081_ = _131_;
    (* src = "libresoc.v:169976.5-169976.29" *)
    casez (\initial )
      /* src = "libresoc.v:169976.9-169976.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _118_, _117_ } = { \xer_ov_ok$88 , \xer_ov$87  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _118_, _117_ } = { \xer_ov_ok$88 , \xer_ov$87  };
        end
      default:
        begin
          _117_ = \xer_ov$26 ;
          _118_ = \xer_ov_ok$27 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = 1'h0;
        end
      default:
          _131_ = _118_;
    endcase
  end
  always @* begin
      \xer_ov$26$next  <= _078_;
      \xer_ov_ok$27$next  <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = _119_;
    _087_ = _132_;
    (* src = "libresoc.v:169995.5-169995.29" *)
    casez (\initial )
      /* src = "libresoc.v:169995.9-169995.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _120_, _119_ } = { \xer_so_ok$90 , \xer_so$89  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _120_, _119_ } = { \xer_so_ok$90 , \xer_so$89  };
        end
      default:
        begin
          _119_ = \xer_so$28 ;
          _120_ = \xer_so_ok$29 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h0;
        end
      default:
          _132_ = _120_;
    endcase
  end
  always @* begin
      \xer_so$28$next  <= _084_;
      \xer_so_ok$29$next  <= _087_;
  end
  assign \$60  = _133_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_so_ok$90 , \xer_so$89  } = { output_xer_so_ok, \output_xer_so$54  };
  assign { \xer_ov_ok$88 , \xer_ov$87  } = { output_xer_ov_ok, \output_xer_ov$53  };
  assign { \xer_ca_ok$86 , \xer_ca$85  } = { output_xer_ca_ok, \output_xer_ca$52  };
  assign { \cr_a_ok$84 , \cr_a$83  } = { output_cr_a_ok, \output_cr_a$51  };
  assign { \o_ok$82 , \o$81  } = { \output_o_ok$50 , \output_o$49  };
  assign { \alu_op__insn$80 , \alu_op__data_len$79 , \alu_op__is_signed$78 , \alu_op__is_32bit$77 , \alu_op__output_carry$76 , \alu_op__input_carry$75 , \alu_op__write_cr0$74 , \alu_op__invert_out$73 , \alu_op__zero_a$72 , \alu_op__invert_in$71 , \alu_op__oe__ok$70 , \alu_op__oe__oe$69 , \alu_op__rc__ok$68 , \alu_op__rc__rc$67 , \alu_op__imm_data__ok$66 , \alu_op__imm_data__data$65 , \alu_op__fn_unit$64 , \alu_op__insn_type$63  } = { \output_alu_op__insn$48 , \output_alu_op__data_len$47 , \output_alu_op__is_signed$46 , \output_alu_op__is_32bit$45 , \output_alu_op__output_carry$44 , \output_alu_op__input_carry$43 , \output_alu_op__write_cr0$42 , \output_alu_op__invert_out$41 , \output_alu_op__zero_a$40 , \output_alu_op__invert_in$39 , \output_alu_op__oe__ok$38 , \output_alu_op__oe__oe$37 , \output_alu_op__rc__ok$36 , \output_alu_op__rc__rc$35 , \output_alu_op__imm_data__ok$34 , \output_alu_op__imm_data__data$33 , \output_alu_op__fn_unit$32 , \output_alu_op__insn_type$31  };
  assign \muxid$62  = \output_muxid$30 ;
  assign p_valid_i_p_ready_o = \$60 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$59  = p_valid_i;
  assign { \xer_so_ok$58 , output_xer_so } = { xer_so_ok, xer_so };
  assign { \xer_ov_ok$57 , output_xer_ov } = { xer_ov_ok, xer_ov };
  assign { \xer_ca_ok$56 , output_xer_ca } = { xer_ca_ok, xer_ca };
  assign { \cr_a_ok$55 , output_cr_a } = { cr_a_ok, cr_a };
  assign { output_o_ok, output_o } = { o_ok, o };
  assign { output_alu_op__insn, output_alu_op__data_len, output_alu_op__is_signed, output_alu_op__is_32bit, output_alu_op__output_carry, output_alu_op__input_carry, output_alu_op__write_cr0, output_alu_op__invert_out, output_alu_op__zero_a, output_alu_op__invert_in, output_alu_op__oe__ok, output_alu_op__oe__oe, output_alu_op__rc__ok, output_alu_op__rc__rc, output_alu_op__imm_data__ok, output_alu_op__imm_data__data, output_alu_op__fn_unit, output_alu_op__insn_type } = { alu_op__insn, alu_op__data_len, alu_op__is_signed, alu_op__is_32bit, alu_op__output_carry, alu_op__input_carry, alu_op__write_cr0, alu_op__invert_out, alu_op__zero_a, alu_op__invert_in, alu_op__oe__ok, alu_op__oe__oe, alu_op__rc__ok, alu_op__rc__rc, alu_op__imm_data__ok, alu_op__imm_data__data, alu_op__fn_unit, alu_op__insn_type };
  assign output_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:170036.1-171105.10" *)
module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, o, o_ok, cr_a, cr_a_ok, xer_so, xer_so_ok, xer_ca, xer_ca_ok, n_valid_o, n_ready_i, \muxid$1 , \sr_op__insn_type$2 , \sr_op__fn_unit$3 , \sr_op__imm_data__data$4 , \sr_op__imm_data__ok$5 , \sr_op__rc__rc$6 , \sr_op__rc__ok$7 , \sr_op__oe__oe$8 , \sr_op__oe__ok$9 , \sr_op__write_cr0$10 , \sr_op__invert_in$11 , \sr_op__input_carry$12 , \sr_op__output_carry$13 , \sr_op__input_cr$14 , \sr_op__output_cr$15 , \sr_op__is_32bit$16 , \sr_op__is_signed$17 , \sr_op__insn$18 , \o$19 , \o_ok$20 , \cr_a$21 , \cr_a_ok$22 , \xer_ca$23 , \xer_ca_ok$24 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:171051.3-171069.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:170857.3-170858.33" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:170048.13-170048.29" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:171051.3-171069.6" *)
  reg _003_;
  (* src = "libresoc.v:170859.3-170860.39" *)
  reg _004_;
  (* src = "libresoc.v:170057.7-170057.26" *)
  reg _005_;
  (* src = "libresoc.v:170037.7-170037.20" *)
  reg _006_;
  (* src = "libresoc.v:170978.3-170990.6" *)
  reg [1:0] _007_;
  (* src = "libresoc.v:170899.3-170900.33" *)
  reg [1:0] _008_;
  (* src = "libresoc.v:170068.13-170068.29" *)
  reg [1:0] _009_;
  (* src = "libresoc.v:171032.3-171050.6" *)
  reg [63:0] _010_;
  (* src = "libresoc.v:170861.3-170862.27" *)
  reg [63:0] _011_;
  (* src = "libresoc.v:170083.14-170083.43" *)
  reg [63:0] _012_;
  (* src = "libresoc.v:171032.3-171050.6" *)
  reg _013_;
  (* src = "libresoc.v:170863.3-170864.33" *)
  reg _014_;
  (* src = "libresoc.v:170092.7-170092.23" *)
  reg _015_;
  (* src = "libresoc.v:170960.3-170977.6" *)
  reg _016_;
  (* src = "libresoc.v:170901.3-170902.29" *)
  reg _017_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [13:0] _018_;
  (* src = "libresoc.v:170867.3-170868.51" *)
  reg [13:0] _019_;
  (* src = "libresoc.v:170425.14-170425.43" *)
  reg [13:0] _020_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [63:0] _021_;
  (* src = "libresoc.v:170869.3-170870.65" *)
  reg [63:0] _022_;
  (* src = "libresoc.v:170449.14-170449.62" *)
  reg [63:0] _023_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _024_;
  (* src = "libresoc.v:170871.3-170872.61" *)
  reg _025_;
  (* src = "libresoc.v:170458.7-170458.37" *)
  reg _026_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [1:0] _027_;
  (* src = "libresoc.v:170885.3-170886.61" *)
  reg [1:0] _028_;
  (* src = "libresoc.v:170475.13-170475.43" *)
  reg [1:0] _029_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _030_;
  (* src = "libresoc.v:170889.3-170890.55" *)
  reg _031_;
  (* src = "libresoc.v:170488.7-170488.34" *)
  reg _032_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [31:0] _033_;
  (* src = "libresoc.v:170897.3-170898.47" *)
  reg [31:0] _034_;
  (* src = "libresoc.v:170497.14-170497.38" *)
  reg [31:0] _035_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [6:0] _036_;
  (* src = "libresoc.v:170865.3-170866.55" *)
  reg [6:0] _037_;
  (* src = "libresoc.v:170656.13-170656.41" *)
  reg [6:0] _038_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _039_;
  (* src = "libresoc.v:170883.3-170884.57" *)
  reg _040_;
  (* src = "libresoc.v:170740.7-170740.35" *)
  reg _041_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _042_;
  (* src = "libresoc.v:170893.3-170894.55" *)
  reg _043_;
  (* src = "libresoc.v:170749.7-170749.34" *)
  reg _044_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _045_;
  (* src = "libresoc.v:170895.3-170896.57" *)
  reg _046_;
  (* src = "libresoc.v:170758.7-170758.35" *)
  reg _047_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _048_;
  (* src = "libresoc.v:170877.3-170878.49" *)
  reg _049_;
  (* src = "libresoc.v:170769.7-170769.31" *)
  reg _050_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _051_;
  (* src = "libresoc.v:170879.3-170880.49" *)
  reg _052_;
  (* src = "libresoc.v:170778.7-170778.31" *)
  reg _053_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _054_;
  (* src = "libresoc.v:170887.3-170888.63" *)
  reg _055_;
  (* src = "libresoc.v:170785.7-170785.38" *)
  reg _056_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _057_;
  (* src = "libresoc.v:170891.3-170892.57" *)
  reg _058_;
  (* src = "libresoc.v:170794.7-170794.35" *)
  reg _059_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _060_;
  (* src = "libresoc.v:170875.3-170876.49" *)
  reg _061_;
  (* src = "libresoc.v:170805.7-170805.31" *)
  reg _062_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _063_;
  (* src = "libresoc.v:170873.3-170874.49" *)
  reg _064_;
  (* src = "libresoc.v:170814.7-170814.31" *)
  reg _065_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _066_;
  (* src = "libresoc.v:170881.3-170882.57" *)
  reg _067_;
  (* src = "libresoc.v:170821.7-170821.35" *)
  reg _068_;
  (* src = "libresoc.v:171070.3-171088.6" *)
  reg [1:0] _069_;
  (* src = "libresoc.v:170853.3-170854.37" *)
  reg [1:0] _070_;
  (* src = "libresoc.v:170830.13-170830.31" *)
  reg [1:0] _071_;
  (* src = "libresoc.v:171070.3-171088.6" *)
  reg _072_;
  (* src = "libresoc.v:170855.3-170856.43" *)
  reg _073_;
  (* src = "libresoc.v:170839.7-170839.28" *)
  reg _074_;
  (* src = "libresoc.v:171051.3-171069.6" *)
  reg [3:0] _075_;
  (* src = "libresoc.v:171051.3-171069.6" *)
  reg _076_;
  (* src = "libresoc.v:170978.3-170990.6" *)
  reg [1:0] _077_;
  (* src = "libresoc.v:171032.3-171050.6" *)
  reg [63:0] _078_;
  (* src = "libresoc.v:171032.3-171050.6" *)
  reg _079_;
  (* src = "libresoc.v:170960.3-170977.6" *)
  reg _080_;
  (* src = "libresoc.v:170388.7-170388.20" *)
  reg _081_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [13:0] _082_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [63:0] _083_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _084_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [1:0] _085_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _086_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [31:0] _087_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [6:0] _088_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _089_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _090_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _091_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _092_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _093_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _094_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _095_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _096_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _097_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _098_;
  (* src = "libresoc.v:171070.3-171088.6" *)
  reg [1:0] _099_;
  (* src = "libresoc.v:171070.3-171088.6" *)
  reg _100_;
  (* src = "libresoc.v:171051.3-171069.6" *)
  reg _101_;
  (* src = "libresoc.v:171032.3-171050.6" *)
  reg _102_;
  (* src = "libresoc.v:170960.3-170977.6" *)
  reg _103_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg [63:0] _104_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _105_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _106_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _107_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _108_;
  (* src = "libresoc.v:170991.3-171031.6" *)
  reg _109_;
  (* src = "libresoc.v:171070.3-171088.6" *)
  reg _110_;
  (* src = "libresoc.v:170852.18-170852.118" *)
  wire _111_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] \cr_a$21 ;
  reg [3:0] \cr_a$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$21$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \cr_a_ok$22 ;
  reg \cr_a_ok$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$22$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$74 ;
  (* src = "libresoc.v:170037.7-170037.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \o$19 ;
  reg [63:0] \o$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$19$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \o_ok$20 ;
  reg \o_ok$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$20$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] output_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \output_cr_a$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_muxid$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \output_o$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_o_ok$44 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_sr_op__fn_unit$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_sr_op__imm_data__data$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__imm_data__ok$29 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] output_sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \output_sr_op__input_carry$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__input_cr$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_sr_op__insn$42 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_sr_op__insn_type$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__invert_in$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__is_32bit$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__is_signed$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__oe__oe$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__oe__ok$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__output_carry$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__output_cr$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__rc__ok$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__rc__rc$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_sr_op__write_cr0$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \output_xer_ca$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$50 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] sr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \sr_op__fn_unit$3 ;
  reg [13:0] \sr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \sr_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \sr_op__fn_unit$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \sr_op__imm_data__data$4 ;
  reg [63:0] \sr_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \sr_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \sr_op__imm_data__data$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__imm_data__ok$5 ;
  reg \sr_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__imm_data__ok$57 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] sr_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \sr_op__input_carry$12 ;
  reg [1:0] \sr_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \sr_op__input_carry$12$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \sr_op__input_carry$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__input_cr$14 ;
  reg \sr_op__input_cr$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__input_cr$14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__input_cr$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \sr_op__insn$18 ;
  reg [31:0] \sr_op__insn$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \sr_op__insn$18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \sr_op__insn$70 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] sr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \sr_op__insn_type$2 ;
  reg [6:0] \sr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \sr_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \sr_op__insn_type$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__invert_in$11 ;
  reg \sr_op__invert_in$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__invert_in$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__invert_in$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_32bit$16 ;
  reg \sr_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__is_32bit$16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_32bit$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__is_signed$17 ;
  reg \sr_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__is_signed$17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__is_signed$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__oe$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__oe$8 ;
  reg \sr_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__oe__ok$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__oe__ok$9 ;
  reg \sr_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_carry$13 ;
  reg \sr_op__output_carry$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__output_carry$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_carry$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__output_cr$15 ;
  reg \sr_op__output_cr$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__output_cr$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__output_cr$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__ok$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__ok$7 ;
  reg \sr_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__rc__rc$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__rc__rc$6 ;
  reg \sr_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \sr_op__write_cr0$10 ;
  reg \sr_op__write_cr0$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \sr_op__write_cr0$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \sr_op__write_cr0$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$23 ;
  reg [1:0] \xer_ca$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ca$23$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ca$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_ca_ok$24 ;
  reg \xer_ca_ok$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ca_ok$24$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ca_ok$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$48 ;
  assign _111_ = \p_valid_i$50  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:170903.11-170906.4" *)
  \n$117  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:170907.16-170955.4" *)
  \output$118  \output  (
    .cr_a(output_cr_a),
    .\cr_a$21 (\output_cr_a$45 ),
    .cr_a_ok(output_cr_a_ok),
    .muxid(output_muxid),
    .\muxid$1 (\output_muxid$25 ),
    .o(output_o),
    .\o$19 (\output_o$43 ),
    .o_ok(output_o_ok),
    .\o_ok$20 (\output_o_ok$44 ),
    .sr_op__fn_unit(output_sr_op__fn_unit),
    .\sr_op__fn_unit$3 (\output_sr_op__fn_unit$27 ),
    .sr_op__imm_data__data(output_sr_op__imm_data__data),
    .\sr_op__imm_data__data$4 (\output_sr_op__imm_data__data$28 ),
    .sr_op__imm_data__ok(output_sr_op__imm_data__ok),
    .\sr_op__imm_data__ok$5 (\output_sr_op__imm_data__ok$29 ),
    .sr_op__input_carry(output_sr_op__input_carry),
    .\sr_op__input_carry$12 (\output_sr_op__input_carry$36 ),
    .sr_op__input_cr(output_sr_op__input_cr),
    .\sr_op__input_cr$14 (\output_sr_op__input_cr$38 ),
    .sr_op__insn(output_sr_op__insn),
    .\sr_op__insn$18 (\output_sr_op__insn$42 ),
    .sr_op__insn_type(output_sr_op__insn_type),
    .\sr_op__insn_type$2 (\output_sr_op__insn_type$26 ),
    .sr_op__invert_in(output_sr_op__invert_in),
    .\sr_op__invert_in$11 (\output_sr_op__invert_in$35 ),
    .sr_op__is_32bit(output_sr_op__is_32bit),
    .\sr_op__is_32bit$16 (\output_sr_op__is_32bit$40 ),
    .sr_op__is_signed(output_sr_op__is_signed),
    .\sr_op__is_signed$17 (\output_sr_op__is_signed$41 ),
    .sr_op__oe__oe(output_sr_op__oe__oe),
    .\sr_op__oe__oe$8 (\output_sr_op__oe__oe$32 ),
    .sr_op__oe__ok(output_sr_op__oe__ok),
    .\sr_op__oe__ok$9 (\output_sr_op__oe__ok$33 ),
    .sr_op__output_carry(output_sr_op__output_carry),
    .\sr_op__output_carry$13 (\output_sr_op__output_carry$37 ),
    .sr_op__output_cr(output_sr_op__output_cr),
    .\sr_op__output_cr$15 (\output_sr_op__output_cr$39 ),
    .sr_op__rc__ok(output_sr_op__rc__ok),
    .\sr_op__rc__ok$7 (\output_sr_op__rc__ok$31 ),
    .sr_op__rc__rc(output_sr_op__rc__rc),
    .\sr_op__rc__rc$6 (\output_sr_op__rc__rc$30 ),
    .sr_op__write_cr0(output_sr_op__write_cr0),
    .\sr_op__write_cr0$10 (\output_sr_op__write_cr0$34 ),
    .xer_ca(output_xer_ca),
    .\xer_ca$22 (\output_xer_ca$46 ),
    .xer_ca_ok(output_xer_ca_ok),
    .xer_so(output_xer_so)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:170956.11-170959.4" *)
  \p$116  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _006_ = 1'h0;
  end
  always @* begin
      \initial  <= _006_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _002_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a$21  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \cr_a_ok$22  <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \o$19  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \o_ok$20  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \sr_op__fn_unit$3  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \sr_op__imm_data__data$4  <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__imm_data__ok$5  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__input_carry$12  <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__input_cr$14  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \sr_op__insn$18  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \sr_op__insn_type$2  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__invert_in$11  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__is_32bit$16  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__is_signed$17  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__oe__oe$8  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__oe__ok$9  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__output_carry$13  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__output_cr$15  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__rc__ok$7  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__rc__rc$6  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \sr_op__write_cr0$10  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ca$23  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_ca_ok$24  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \xer_ca$23$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ca$23  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \xer_ca_ok$24$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_ca_ok$24  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$21$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a$21  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = \cr_a_ok$22$next ;
  end
  always @(posedge coresync_clk) begin
      \cr_a_ok$22  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \o$19$next ;
  end
  always @(posedge coresync_clk) begin
      \o$19  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \o_ok$20$next ;
  end
  always @(posedge coresync_clk) begin
      \o_ok$20  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \sr_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__insn_type$2  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \sr_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__fn_unit$3  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \sr_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__imm_data__data$4  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \sr_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__imm_data__ok$5  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \sr_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__rc__rc$6  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \sr_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__rc__ok$7  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \sr_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__oe__oe$8  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \sr_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__oe__ok$9  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \sr_op__write_cr0$10$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__write_cr0$10  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \sr_op__invert_in$11$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__invert_in$11  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \sr_op__input_carry$12$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__input_carry$12  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \sr_op__output_carry$13$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__output_carry$13  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \sr_op__input_cr$14$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__input_cr$14  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \sr_op__output_cr$15$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__output_cr$15  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \sr_op__is_32bit$16$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__is_32bit$16  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \sr_op__is_signed$17$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__is_signed$17  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \sr_op__insn$18$next ;
  end
  always @(posedge coresync_clk) begin
      \sr_op__insn$18  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _103_;
    (* src = "libresoc.v:170961.5-170961.29" *)
    casez (\initial )
      /* src = "libresoc.v:170961.9-170961.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _080_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _080_ = 1'h0;
        end
      default:
          _080_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = 1'h0;
        end
      default:
          _103_ = _080_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _077_;
    (* src = "libresoc.v:170979.5-170979.29" *)
    casez (\initial )
      /* src = "libresoc.v:170979.9-170979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _077_ = \muxid$53 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _077_ = \muxid$53 ;
        end
      default:
          _077_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _082_;
    _027_ = _085_;
    _030_ = _086_;
    _033_ = _087_;
    _036_ = _088_;
    _039_ = _089_;
    _042_ = _090_;
    _045_ = _091_;
    _054_ = _094_;
    _057_ = _095_;
    _066_ = _098_;
    _021_ = _104_;
    _024_ = _105_;
    _048_ = _106_;
    _051_ = _107_;
    _060_ = _108_;
    _063_ = _109_;
    (* src = "libresoc.v:170992.5-170992.29" *)
    casez (\initial )
      /* src = "libresoc.v:170992.9-170992.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _087_, _091_, _090_, _095_, _086_, _094_, _085_, _089_, _098_, _093_, _092_, _096_, _097_, _084_, _083_, _082_, _088_ } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _087_, _091_, _090_, _095_, _086_, _094_, _085_, _089_, _098_, _093_, _092_, _096_, _097_, _084_, _083_, _082_, _088_ } = { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54  };
        end
      default:
        begin
          _082_ = \sr_op__fn_unit$3 ;
          _083_ = \sr_op__imm_data__data$4 ;
          _084_ = \sr_op__imm_data__ok$5 ;
          _085_ = \sr_op__input_carry$12 ;
          _086_ = \sr_op__input_cr$14 ;
          _087_ = \sr_op__insn$18 ;
          _088_ = \sr_op__insn_type$2 ;
          _089_ = \sr_op__invert_in$11 ;
          _090_ = \sr_op__is_32bit$16 ;
          _091_ = \sr_op__is_signed$17 ;
          _092_ = \sr_op__oe__oe$8 ;
          _093_ = \sr_op__oe__ok$9 ;
          _094_ = \sr_op__output_carry$13 ;
          _095_ = \sr_op__output_cr$15 ;
          _096_ = \sr_op__rc__ok$7 ;
          _097_ = \sr_op__rc__rc$6 ;
          _098_ = \sr_op__write_cr0$10 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = 64'h0000000000000000;
          _105_ = 1'h0;
          _109_ = 1'h0;
          _108_ = 1'h0;
          _106_ = 1'h0;
          _107_ = 1'h0;
        end
      default:
        begin
          _104_ = _083_;
          _105_ = _084_;
          _106_ = _092_;
          _107_ = _093_;
          _108_ = _096_;
          _109_ = _097_;
        end
    endcase
  end
  always @* begin
      \sr_op__fn_unit$3$next  <= _018_;
      \sr_op__imm_data__data$4$next  <= _021_;
      \sr_op__imm_data__ok$5$next  <= _024_;
      \sr_op__input_carry$12$next  <= _027_;
      \sr_op__input_cr$14$next  <= _030_;
      \sr_op__insn$18$next  <= _033_;
      \sr_op__insn_type$2$next  <= _036_;
      \sr_op__invert_in$11$next  <= _039_;
      \sr_op__is_32bit$16$next  <= _042_;
      \sr_op__is_signed$17$next  <= _045_;
      \sr_op__oe__oe$8$next  <= _048_;
      \sr_op__oe__ok$9$next  <= _051_;
      \sr_op__output_carry$13$next  <= _054_;
      \sr_op__output_cr$15$next  <= _057_;
      \sr_op__rc__ok$7$next  <= _060_;
      \sr_op__rc__rc$6$next  <= _063_;
      \sr_op__write_cr0$10$next  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _078_;
    _013_ = _102_;
    (* src = "libresoc.v:171033.5-171033.29" *)
    casez (\initial )
      /* src = "libresoc.v:171033.9-171033.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _079_, _078_ } = { \o_ok$72 , \o$71  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _079_, _078_ } = { \o_ok$72 , \o$71  };
        end
      default:
        begin
          _078_ = \o$19 ;
          _079_ = \o_ok$20 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _102_ = 1'h0;
        end
      default:
          _102_ = _079_;
    endcase
  end
  always @* begin
      \o$19$next  <= _010_;
      \o_ok$20$next  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _075_;
    _003_ = _101_;
    (* src = "libresoc.v:171052.5-171052.29" *)
    casez (\initial )
      /* src = "libresoc.v:171052.9-171052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _076_, _075_ } = { \cr_a_ok$74 , \cr_a$73  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _076_, _075_ } = { \cr_a_ok$74 , \cr_a$73  };
        end
      default:
        begin
          _075_ = \cr_a$21 ;
          _076_ = \cr_a_ok$22 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = 1'h0;
        end
      default:
          _101_ = _076_;
    endcase
  end
  always @* begin
      \cr_a$21$next  <= _000_;
      \cr_a_ok$22$next  <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _099_;
    _072_ = _110_;
    (* src = "libresoc.v:171071.5-171071.29" *)
    casez (\initial )
      /* src = "libresoc.v:171071.9-171071.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _100_, _099_ } = { \xer_ca_ok$76 , \xer_ca$75  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _100_, _099_ } = { \xer_ca_ok$76 , \xer_ca$75  };
        end
      default:
        begin
          _099_ = \xer_ca$23 ;
          _100_ = \xer_ca_ok$24 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _110_ = 1'h0;
        end
      default:
          _110_ = _100_;
    endcase
  end
  always @* begin
      \xer_ca$23$next  <= _069_;
      \xer_ca_ok$24$next  <= _072_;
  end
  assign \$51  = _111_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_ca_ok$76 , \xer_ca$75  } = { output_xer_ca_ok, \output_xer_ca$46  };
  assign { \cr_a_ok$74 , \cr_a$73  } = { output_cr_a_ok, \output_cr_a$45  };
  assign { \o_ok$72 , \o$71  } = { \output_o_ok$44 , \output_o$43  };
  assign { \sr_op__insn$70 , \sr_op__is_signed$69 , \sr_op__is_32bit$68 , \sr_op__output_cr$67 , \sr_op__input_cr$66 , \sr_op__output_carry$65 , \sr_op__input_carry$64 , \sr_op__invert_in$63 , \sr_op__write_cr0$62 , \sr_op__oe__ok$61 , \sr_op__oe__oe$60 , \sr_op__rc__ok$59 , \sr_op__rc__rc$58 , \sr_op__imm_data__ok$57 , \sr_op__imm_data__data$56 , \sr_op__fn_unit$55 , \sr_op__insn_type$54  } = { \output_sr_op__insn$42 , \output_sr_op__is_signed$41 , \output_sr_op__is_32bit$40 , \output_sr_op__output_cr$39 , \output_sr_op__input_cr$38 , \output_sr_op__output_carry$37 , \output_sr_op__input_carry$36 , \output_sr_op__invert_in$35 , \output_sr_op__write_cr0$34 , \output_sr_op__oe__ok$33 , \output_sr_op__oe__oe$32 , \output_sr_op__rc__ok$31 , \output_sr_op__rc__rc$30 , \output_sr_op__imm_data__ok$29 , \output_sr_op__imm_data__data$28 , \output_sr_op__fn_unit$27 , \output_sr_op__insn_type$26  };
  assign \muxid$53  = \output_muxid$25 ;
  assign p_valid_i_p_ready_o = \$51 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$50  = p_valid_i;
  assign { \xer_ca_ok$49 , output_xer_ca } = { xer_ca_ok, xer_ca };
  assign { \xer_so_ok$48 , output_xer_so } = { xer_so_ok, xer_so };
  assign { \cr_a_ok$47 , output_cr_a } = { cr_a_ok, cr_a };
  assign { output_o_ok, output_o } = { o_ok, o };
  assign { output_sr_op__insn, output_sr_op__is_signed, output_sr_op__is_32bit, output_sr_op__output_cr, output_sr_op__input_cr, output_sr_op__output_carry, output_sr_op__input_carry, output_sr_op__invert_in, output_sr_op__write_cr0, output_sr_op__oe__ok, output_sr_op__oe__oe, output_sr_op__rc__ok, output_sr_op__rc__rc, output_sr_op__imm_data__ok, output_sr_op__imm_data__data, output_sr_op__fn_unit, output_sr_op__insn_type } = { sr_op__insn, sr_op__is_signed, sr_op__is_32bit, sr_op__output_cr, sr_op__input_cr, sr_op__output_carry, sr_op__input_carry, sr_op__invert_in, sr_op__write_cr0, sr_op__oe__ok, sr_op__oe__oe, sr_op__rc__ok, sr_op__rc__rc, sr_op__imm_data__ok, sr_op__imm_data__data, sr_op__fn_unit, sr_op__insn_type };
  assign output_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:171109.1-172073.10" *)
module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, ra, rb, fast1, fast2, n_valid_o, n_ready_i, \muxid$1 , \trap_op__insn_type$2 , \trap_op__fn_unit$3 , \trap_op__insn$4 , \trap_op__msr$5 , \trap_op__cia$6 , \trap_op__is_32bit$7 , \trap_op__traptype$8 , \trap_op__trapaddr$9 , \trap_op__ldst_exc$10 , o, o_ok, \fast1$11 , fast1_ok, \fast2$12 , fast2_ok, nia, nia_ok, msr, msr_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:171979.3-171997.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:171856.3-171857.35" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:171121.14-171121.47" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:171979.3-171997.6" *)
  reg _03_;
  (* src = "libresoc.v:171858.3-171859.33" *)
  reg _04_;
  (* src = "libresoc.v:171998.3-172016.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:171852.3-171853.35" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:171137.14-171137.47" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:171998.3-172016.6" *)
  reg _08_;
  (* src = "libresoc.v:171854.3-171855.33" *)
  reg _09_;
  (* src = "libresoc.v:171110.7-171110.20" *)
  reg _10_;
  (* src = "libresoc.v:172036.3-172054.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:171844.3-171845.23" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:172036.3-172054.6" *)
  reg _13_;
  (* src = "libresoc.v:171846.3-171847.29" *)
  reg _14_;
  (* src = "libresoc.v:171926.3-171938.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:171840.3-171841.33" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:171415.13-171415.29" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:172017.3-172035.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:171848.3-171849.23" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:172017.3-172035.6" *)
  reg _20_;
  (* src = "libresoc.v:171850.3-171851.29" *)
  reg _21_;
  (* src = "libresoc.v:171960.3-171978.6" *)
  reg [63:0] _22_;
  (* src = "libresoc.v:171860.3-171861.19" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:171960.3-171978.6" *)
  reg _24_;
  (* src = "libresoc.v:171862.3-171863.25" *)
  reg _25_;
  (* src = "libresoc.v:171908.3-171925.6" *)
  reg _26_;
  (* src = "libresoc.v:171842.3-171843.29" *)
  reg _27_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [63:0] _28_;
  (* src = "libresoc.v:171830.3-171831.47" *)
  reg [63:0] _29_;
  (* src = "libresoc.v:171476.14-171476.53" *)
  reg [63:0] _30_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [13:0] _31_;
  (* src = "libresoc.v:171824.3-171825.55" *)
  reg [13:0] _32_;
  (* src = "libresoc.v:171513.14-171513.45" *)
  reg [13:0] _33_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [31:0] _34_;
  (* src = "libresoc.v:171826.3-171827.49" *)
  reg [31:0] _35_;
  (* src = "libresoc.v:171539.14-171539.39" *)
  reg [31:0] _36_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [6:0] _37_;
  (* src = "libresoc.v:171822.3-171823.59" *)
  reg [6:0] _38_;
  (* src = "libresoc.v:171696.13-171696.43" *)
  reg [6:0] _39_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg _40_;
  (* src = "libresoc.v:171832.3-171833.57" *)
  reg _41_;
  (* src = "libresoc.v:171782.7-171782.35" *)
  reg _42_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [7:0] _43_;
  (* src = "libresoc.v:171838.3-171839.59" *)
  reg [7:0] _44_;
  (* src = "libresoc.v:171789.13-171789.43" *)
  reg [7:0] _45_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [63:0] _46_;
  (* src = "libresoc.v:171828.3-171829.47" *)
  reg [63:0] _47_;
  (* src = "libresoc.v:171800.14-171800.53" *)
  reg [63:0] _48_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [12:0] _49_;
  (* src = "libresoc.v:171836.3-171837.57" *)
  reg [12:0] _50_;
  (* src = "libresoc.v:171809.14-171809.46" *)
  reg [12:0] _51_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [7:0] _52_;
  (* src = "libresoc.v:171834.3-171835.57" *)
  reg [7:0] _53_;
  (* src = "libresoc.v:171818.13-171818.42" *)
  reg [7:0] _54_;
  (* src = "libresoc.v:171979.3-171997.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:171979.3-171997.6" *)
  reg _56_;
  (* src = "libresoc.v:171128.7-171128.22" *)
  reg _57_;
  (* src = "libresoc.v:171998.3-172016.6" *)
  reg [63:0] _58_;
  (* src = "libresoc.v:171998.3-172016.6" *)
  reg _59_;
  (* src = "libresoc.v:171144.7-171144.22" *)
  reg _60_;
  (* src = "libresoc.v:172036.3-172054.6" *)
  reg [63:0] _61_;
  (* src = "libresoc.v:171399.14-171399.40" *)
  reg [63:0] _62_;
  (* src = "libresoc.v:172036.3-172054.6" *)
  reg _63_;
  (* src = "libresoc.v:171406.7-171406.20" *)
  reg _64_;
  (* src = "libresoc.v:171926.3-171938.6" *)
  reg [1:0] _65_;
  (* src = "libresoc.v:172017.3-172035.6" *)
  reg [63:0] _66_;
  (* src = "libresoc.v:171428.14-171428.40" *)
  reg [63:0] _67_;
  (* src = "libresoc.v:172017.3-172035.6" *)
  reg _68_;
  (* src = "libresoc.v:171435.7-171435.20" *)
  reg _69_;
  (* src = "libresoc.v:171960.3-171978.6" *)
  reg [63:0] _70_;
  (* src = "libresoc.v:171442.14-171442.38" *)
  reg [63:0] _71_;
  (* src = "libresoc.v:171960.3-171978.6" *)
  reg _72_;
  (* src = "libresoc.v:171449.7-171449.18" *)
  reg _73_;
  (* src = "libresoc.v:171908.3-171925.6" *)
  reg _74_;
  (* src = "libresoc.v:171463.7-171463.20" *)
  reg _75_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [63:0] _76_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [13:0] _77_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [31:0] _78_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [6:0] _79_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg _80_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [7:0] _81_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [63:0] _82_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [12:0] _83_;
  (* src = "libresoc.v:171939.3-171959.6" *)
  reg [7:0] _84_;
  (* src = "libresoc.v:171979.3-171997.6" *)
  reg _85_;
  (* src = "libresoc.v:171998.3-172016.6" *)
  reg _86_;
  (* src = "libresoc.v:172036.3-172054.6" *)
  reg _87_;
  (* src = "libresoc.v:172017.3-172035.6" *)
  reg _88_;
  (* src = "libresoc.v:171960.3-171978.6" *)
  reg _89_;
  (* src = "libresoc.v:171908.3-171925.6" *)
  reg _90_;
  (* src = "libresoc.v:171821.18-171821.118" *)
  wire _91_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$11 ;
  reg [63:0] \fast1$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \fast1$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \fast1$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fast1_ok$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast2$12 ;
  reg [63:0] \fast2$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \fast2$12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \fast2$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  reg fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \fast2_ok$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \fast2_ok$next ;
  (* src = "libresoc.v:171110.7-171110.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \main_fast1$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \main_fast2$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_msr_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] main_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \main_muxid$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] main_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire main_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] main_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_trap_op__cia$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] main_trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \main_trap_op__fn_unit$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] main_trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \main_trap_op__insn$16 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] main_trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \main_trap_op__insn_type$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire main_trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \main_trap_op__is_32bit$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] main_trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \main_trap_op__ldst_exc$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] main_trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \main_trap_op__msr$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] main_trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \main_trap_op__trapaddr$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] main_trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \main_trap_op__traptype$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] msr;
  reg [63:0] msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \msr$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output msr_ok;
  reg msr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \msr_ok$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \msr_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] nia;
  reg [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \nia$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \nia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  reg nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \nia_ok$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \nia_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$25 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__cia$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__cia$6 ;
  reg [63:0] \trap_op__cia$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \trap_op__cia$6$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] trap_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \trap_op__fn_unit$3 ;
  reg [13:0] \trap_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \trap_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \trap_op__fn_unit$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \trap_op__insn$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \trap_op__insn$4 ;
  reg [31:0] \trap_op__insn$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \trap_op__insn$4$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] trap_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \trap_op__insn_type$2 ;
  reg [6:0] \trap_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \trap_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \trap_op__insn_type$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \trap_op__is_32bit$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \trap_op__is_32bit$7 ;
  reg \trap_op__is_32bit$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \trap_op__is_32bit$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__ldst_exc$10 ;
  reg [7:0] \trap_op__ldst_exc$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \trap_op__ldst_exc$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__ldst_exc$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \trap_op__msr$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \trap_op__msr$5 ;
  reg [63:0] \trap_op__msr$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \trap_op__msr$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [12:0] \trap_op__trapaddr$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [12:0] \trap_op__trapaddr$9 ;
  reg [12:0] \trap_op__trapaddr$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [12:0] \trap_op__trapaddr$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [7:0] \trap_op__traptype$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [7:0] \trap_op__traptype$8 ;
  reg [7:0] \trap_op__traptype$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \trap_op__traptype$8$next ;
  assign _91_ = \p_valid_i$25  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:171864.13-171899.4" *)
  \main$38  main (
    .fast1(main_fast1),
    .\fast1$11 (\main_fast1$23 ),
    .fast1_ok(main_fast1_ok),
    .fast2(main_fast2),
    .\fast2$12 (\main_fast2$24 ),
    .fast2_ok(main_fast2_ok),
    .msr(main_msr),
    .msr_ok(main_msr_ok),
    .muxid(main_muxid),
    .\muxid$1 (\main_muxid$13 ),
    .nia(main_nia),
    .nia_ok(main_nia_ok),
    .o(main_o),
    .o_ok(main_o_ok),
    .ra(main_ra),
    .rb(main_rb),
    .trap_op__cia(main_trap_op__cia),
    .\trap_op__cia$6 (\main_trap_op__cia$18 ),
    .trap_op__fn_unit(main_trap_op__fn_unit),
    .\trap_op__fn_unit$3 (\main_trap_op__fn_unit$15 ),
    .trap_op__insn(main_trap_op__insn),
    .\trap_op__insn$4 (\main_trap_op__insn$16 ),
    .trap_op__insn_type(main_trap_op__insn_type),
    .\trap_op__insn_type$2 (\main_trap_op__insn_type$14 ),
    .trap_op__is_32bit(main_trap_op__is_32bit),
    .\trap_op__is_32bit$7 (\main_trap_op__is_32bit$19 ),
    .trap_op__ldst_exc(main_trap_op__ldst_exc),
    .\trap_op__ldst_exc$10 (\main_trap_op__ldst_exc$22 ),
    .trap_op__msr(main_trap_op__msr),
    .\trap_op__msr$5 (\main_trap_op__msr$17 ),
    .trap_op__trapaddr(main_trap_op__trapaddr),
    .\trap_op__trapaddr$9 (\main_trap_op__trapaddr$21 ),
    .trap_op__traptype(main_trap_op__traptype),
    .\trap_op__traptype$8 (\main_trap_op__traptype$20 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:171900.10-171903.4" *)
  \n$37  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:171904.10-171907.4" *)
  \p$36  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _10_ = 1'h0;
  end
  always @* begin
      \initial  <= _10_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _02_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \fast1$11  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _57_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      fast1_ok <= _57_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \fast2$12  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _60_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      fast2_ok <= _60_;
  end
  always @* begin
    if (\initial ) begin end
    _62_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      msr <= _62_;
  end
  always @* begin
    if (\initial ) begin end
    _64_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      msr_ok <= _64_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _67_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      nia <= _67_;
  end
  always @* begin
    if (\initial ) begin end
    _69_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      nia_ok <= _69_;
  end
  always @* begin
    if (\initial ) begin end
    _71_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _71_;
  end
  always @* begin
    if (\initial ) begin end
    _73_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _73_;
  end
  always @* begin
    if (\initial ) begin end
    _75_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _75_;
  end
  always @* begin
    if (\initial ) begin end
    _30_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \trap_op__cia$6  <= _30_;
  end
  always @* begin
    if (\initial ) begin end
    _33_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \trap_op__fn_unit$3  <= _33_;
  end
  always @* begin
    if (\initial ) begin end
    _36_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \trap_op__insn$4  <= _36_;
  end
  always @* begin
    if (\initial ) begin end
    _39_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \trap_op__insn_type$2  <= _39_;
  end
  always @* begin
    if (\initial ) begin end
    _42_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \trap_op__is_32bit$7  <= _42_;
  end
  always @* begin
    if (\initial ) begin end
    _45_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      \trap_op__ldst_exc$10  <= _45_;
  end
  always @* begin
    if (\initial ) begin end
    _48_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \trap_op__msr$5  <= _48_;
  end
  always @* begin
    if (\initial ) begin end
    _51_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      \trap_op__trapaddr$9  <= _51_;
  end
  always @* begin
    if (\initial ) begin end
    _54_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      \trap_op__traptype$8  <= _54_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = \trap_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__insn_type$2  <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _32_ = \trap_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__fn_unit$3  <= _32_;
  end
  always @* begin
    if (\initial ) begin end
    _35_ = \trap_op__insn$4$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__insn$4  <= _35_;
  end
  always @* begin
    if (\initial ) begin end
    _47_ = \trap_op__msr$5$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__msr$5  <= _47_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = \trap_op__cia$6$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__cia$6  <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _41_ = \trap_op__is_32bit$7$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__is_32bit$7  <= _41_;
  end
  always @* begin
    if (\initial ) begin end
    _53_ = \trap_op__traptype$8$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__traptype$8  <= _53_;
  end
  always @* begin
    if (\initial ) begin end
    _50_ = \trap_op__trapaddr$9$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__trapaddr$9  <= _50_;
  end
  always @* begin
    if (\initial ) begin end
    _44_ = \trap_op__ldst_exc$10$next ;
  end
  always @(posedge coresync_clk) begin
      \trap_op__ldst_exc$10  <= _44_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \msr$next ;
  end
  always @(posedge coresync_clk) begin
      msr <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = \msr_ok$next ;
  end
  always @(posedge coresync_clk) begin
      msr_ok <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = \nia$next ;
  end
  always @(posedge coresync_clk) begin
      nia <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = \nia_ok$next ;
  end
  always @(posedge coresync_clk) begin
      nia_ok <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \fast2$12$next ;
  end
  always @(posedge coresync_clk) begin
      \fast2$12  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = \fast2_ok$next ;
  end
  always @(posedge coresync_clk) begin
      fast2_ok <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \fast1$11$next ;
  end
  always @(posedge coresync_clk) begin
      \fast1$11  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      fast1_ok <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _26_ = _90_;
    (* src = "libresoc.v:171909.5-171909.29" *)
    casez (\initial )
      /* src = "libresoc.v:171909.9-171909.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _74_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _74_ = 1'h0;
        end
      default:
          _74_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _90_ = 1'h0;
        end
      default:
          _90_ = _74_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _26_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _65_;
    (* src = "libresoc.v:171927.5-171927.29" *)
    casez (\initial )
      /* src = "libresoc.v:171927.9-171927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _65_ = \muxid$28 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _65_ = \muxid$28 ;
        end
      default:
          _65_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _28_ = _76_;
    _31_ = _77_;
    _34_ = _78_;
    _37_ = _79_;
    _40_ = _80_;
    _43_ = _81_;
    _46_ = _82_;
    _49_ = _83_;
    _52_ = _84_;
    (* src = "libresoc.v:171940.5-171940.29" *)
    casez (\initial )
      /* src = "libresoc.v:171940.9-171940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _81_, _83_, _84_, _80_, _76_, _82_, _78_, _77_, _79_ } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _81_, _83_, _84_, _80_, _76_, _82_, _78_, _77_, _79_ } = { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29  };
        end
      default:
        begin
          _76_ = \trap_op__cia$6 ;
          _77_ = \trap_op__fn_unit$3 ;
          _78_ = \trap_op__insn$4 ;
          _79_ = \trap_op__insn_type$2 ;
          _80_ = \trap_op__is_32bit$7 ;
          _81_ = \trap_op__ldst_exc$10 ;
          _82_ = \trap_op__msr$5 ;
          _83_ = \trap_op__trapaddr$9 ;
          _84_ = \trap_op__traptype$8 ;
        end
    endcase
  end
  always @* begin
      \trap_op__cia$6$next  <= _28_;
      \trap_op__fn_unit$3$next  <= _31_;
      \trap_op__insn$4$next  <= _34_;
      \trap_op__insn_type$2$next  <= _37_;
      \trap_op__is_32bit$7$next  <= _40_;
      \trap_op__ldst_exc$10$next  <= _43_;
      \trap_op__msr$5$next  <= _46_;
      \trap_op__trapaddr$9$next  <= _49_;
      \trap_op__traptype$8$next  <= _52_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _70_;
    _24_ = _89_;
    (* src = "libresoc.v:171961.5-171961.29" *)
    casez (\initial )
      /* src = "libresoc.v:171961.9-171961.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _72_, _70_ } = { \o_ok$39 , \o$38  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _72_, _70_ } = { \o_ok$39 , \o$38  };
        end
      default:
        begin
          _70_ = o;
          _72_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _89_ = 1'h0;
        end
      default:
          _89_ = _72_;
    endcase
  end
  always @* begin
      \o$next  <= _22_;
      \o_ok$next  <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _55_;
    _03_ = _85_;
    (* src = "libresoc.v:171980.5-171980.29" *)
    casez (\initial )
      /* src = "libresoc.v:171980.9-171980.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _56_, _55_ } = { \fast1_ok$41 , \fast1$40  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _56_, _55_ } = { \fast1_ok$41 , \fast1$40  };
        end
      default:
        begin
          _56_ = fast1_ok;
          _55_ = \fast1$11 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _85_ = 1'h0;
        end
      default:
          _85_ = _56_;
    endcase
  end
  always @* begin
      \fast1_ok$next  <= _03_;
      \fast1$11$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _58_;
    _08_ = _86_;
    (* src = "libresoc.v:171999.5-171999.29" *)
    casez (\initial )
      /* src = "libresoc.v:171999.9-171999.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _59_, _58_ } = { \fast2_ok$43 , \fast2$42  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _59_, _58_ } = { \fast2_ok$43 , \fast2$42  };
        end
      default:
        begin
          _59_ = fast2_ok;
          _58_ = \fast2$12 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _86_ = 1'h0;
        end
      default:
          _86_ = _59_;
    endcase
  end
  always @* begin
      \fast2_ok$next  <= _08_;
      \fast2$12$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = _66_;
    _20_ = _88_;
    (* src = "libresoc.v:172018.5-172018.29" *)
    casez (\initial )
      /* src = "libresoc.v:172018.9-172018.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _68_, _66_ } = { \nia_ok$45 , \nia$44  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _68_, _66_ } = { \nia_ok$45 , \nia$44  };
        end
      default:
        begin
          _66_ = nia;
          _68_ = nia_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _88_ = 1'h0;
        end
      default:
          _88_ = _68_;
    endcase
  end
  always @* begin
      \nia$next  <= _18_;
      \nia_ok$next  <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _61_;
    _13_ = _87_;
    (* src = "libresoc.v:172037.5-172037.29" *)
    casez (\initial )
      /* src = "libresoc.v:172037.9-172037.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _63_, _61_ } = { \msr_ok$47 , \msr$46  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _63_, _61_ } = { \msr_ok$47 , \msr$46  };
        end
      default:
        begin
          _61_ = msr;
          _63_ = msr_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _87_ = 1'h0;
        end
      default:
          _87_ = _63_;
    endcase
  end
  always @* begin
      \msr$next  <= _11_;
      \msr_ok$next  <= _13_;
  end
  assign \$26  = _91_;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \msr_ok$47 , \msr$46  } = { main_msr_ok, main_msr };
  assign { \nia_ok$45 , \nia$44  } = { main_nia_ok, main_nia };
  assign { \fast2_ok$43 , \fast2$42  } = { main_fast2_ok, \main_fast2$24  };
  assign { \fast1_ok$41 , \fast1$40  } = { main_fast1_ok, \main_fast1$23  };
  assign { \o_ok$39 , \o$38  } = { main_o_ok, main_o };
  assign { \trap_op__ldst_exc$37 , \trap_op__trapaddr$36 , \trap_op__traptype$35 , \trap_op__is_32bit$34 , \trap_op__cia$33 , \trap_op__msr$32 , \trap_op__insn$31 , \trap_op__fn_unit$30 , \trap_op__insn_type$29  } = { \main_trap_op__ldst_exc$22 , \main_trap_op__trapaddr$21 , \main_trap_op__traptype$20 , \main_trap_op__is_32bit$19 , \main_trap_op__cia$18 , \main_trap_op__msr$17 , \main_trap_op__insn$16 , \main_trap_op__fn_unit$15 , \main_trap_op__insn_type$14  };
  assign \muxid$28  = \main_muxid$13 ;
  assign p_valid_i_p_ready_o = \$26 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$25  = p_valid_i;
  assign main_fast2 = fast2;
  assign main_fast1 = fast1;
  assign main_rb = rb;
  assign main_ra = ra;
  assign { main_trap_op__ldst_exc, main_trap_op__trapaddr, main_trap_op__traptype, main_trap_op__is_32bit, main_trap_op__cia, main_trap_op__msr, main_trap_op__insn, main_trap_op__fn_unit, main_trap_op__insn_type } = { trap_op__ldst_exc, trap_op__trapaddr, trap_op__traptype, trap_op__is_32bit, trap_op__cia, trap_op__msr, trap_op__insn, trap_op__fn_unit, trap_op__insn_type };
  assign main_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:172077.1-173580.10" *)
module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, quotient_root, remainder, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , o, o_ok, cr_a, cr_a_ok, xer_ov, xer_ov_ok, \xer_so$20 , xer_so_ok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:173418.3-173436.6" *)
  reg [3:0] _000_;
  (* src = "libresoc.v:173237.3-173238.25" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:173418.3-173436.6" *)
  reg _002_;
  (* src = "libresoc.v:173239.3-173240.31" *)
  reg _003_;
  (* src = "libresoc.v:172078.7-172078.20" *)
  reg _004_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [3:0] _005_;
  (* src = "libresoc.v:173277.3-173278.65" *)
  reg [3:0] _006_;
  (* src = "libresoc.v:172119.13-172119.45" *)
  reg [3:0] _007_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [13:0] _008_;
  (* src = "libresoc.v:173247.3-173248.61" *)
  reg [13:0] _009_;
  (* src = "libresoc.v:172158.14-172158.48" *)
  reg [13:0] _010_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [63:0] _011_;
  (* src = "libresoc.v:173249.3-173250.75" *)
  reg [63:0] _012_;
  (* src = "libresoc.v:172182.14-172182.67" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _014_;
  (* src = "libresoc.v:173251.3-173252.71" *)
  reg _015_;
  (* src = "libresoc.v:172191.7-172191.42" *)
  reg _016_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [1:0] _017_;
  (* src = "libresoc.v:173265.3-173266.71" *)
  reg [1:0] _018_;
  (* src = "libresoc.v:172208.13-172208.48" *)
  reg [1:0] _019_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [31:0] _020_;
  (* src = "libresoc.v:173279.3-173280.57" *)
  reg [31:0] _021_;
  (* src = "libresoc.v:172221.14-172221.43" *)
  reg [31:0] _022_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [6:0] _023_;
  (* src = "libresoc.v:173245.3-173246.65" *)
  reg [6:0] _024_;
  (* src = "libresoc.v:172380.13-172380.46" *)
  reg [6:0] _025_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _026_;
  (* src = "libresoc.v:173261.3-173262.67" *)
  reg _027_;
  (* src = "libresoc.v:172464.7-172464.40" *)
  reg _028_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _029_;
  (* src = "libresoc.v:173267.3-173268.69" *)
  reg _030_;
  (* src = "libresoc.v:172473.7-172473.41" *)
  reg _031_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _032_;
  (* src = "libresoc.v:173273.3-173274.65" *)
  reg _033_;
  (* src = "libresoc.v:172482.7-172482.39" *)
  reg _034_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _035_;
  (* src = "libresoc.v:173275.3-173276.67" *)
  reg _036_;
  (* src = "libresoc.v:172491.7-172491.40" *)
  reg _037_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _038_;
  (* src = "libresoc.v:173257.3-173258.59" *)
  reg _039_;
  (* src = "libresoc.v:172500.7-172500.36" *)
  reg _040_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _041_;
  (* src = "libresoc.v:173259.3-173260.59" *)
  reg _042_;
  (* src = "libresoc.v:172511.7-172511.36" *)
  reg _043_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _044_;
  (* src = "libresoc.v:173271.3-173272.73" *)
  reg _045_;
  (* src = "libresoc.v:172518.7-172518.43" *)
  reg _046_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _047_;
  (* src = "libresoc.v:173255.3-173256.59" *)
  reg _048_;
  (* src = "libresoc.v:172527.7-172527.36" *)
  reg _049_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _050_;
  (* src = "libresoc.v:173253.3-173254.59" *)
  reg _051_;
  (* src = "libresoc.v:172536.7-172536.36" *)
  reg _052_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _053_;
  (* src = "libresoc.v:173269.3-173270.67" *)
  reg _054_;
  (* src = "libresoc.v:172545.7-172545.40" *)
  reg _055_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _056_;
  (* src = "libresoc.v:173263.3-173264.61" *)
  reg _057_;
  (* src = "libresoc.v:172554.7-172554.37" *)
  reg _058_;
  (* src = "libresoc.v:173493.3-173505.6" *)
  reg [1:0] _059_;
  (* src = "libresoc.v:173281.3-173282.33" *)
  reg [1:0] _060_;
  (* src = "libresoc.v:172563.13-172563.29" *)
  reg [1:0] _061_;
  (* src = "libresoc.v:173399.3-173417.6" *)
  reg [63:0] _062_;
  (* src = "libresoc.v:173241.3-173242.19" *)
  reg [63:0] _063_;
  (* src = "libresoc.v:173399.3-173417.6" *)
  reg _064_;
  (* src = "libresoc.v:173243.3-173244.25" *)
  reg _065_;
  (* src = "libresoc.v:173475.3-173492.6" *)
  reg _066_;
  (* src = "libresoc.v:173283.3-173284.29" *)
  reg _067_;
  (* src = "libresoc.v:173437.3-173455.6" *)
  reg [1:0] _068_;
  (* src = "libresoc.v:173233.3-173234.29" *)
  reg [1:0] _069_;
  (* src = "libresoc.v:173437.3-173455.6" *)
  reg _070_;
  (* src = "libresoc.v:173235.3-173236.35" *)
  reg _071_;
  (* src = "libresoc.v:173456.3-173474.6" *)
  reg _072_;
  (* src = "libresoc.v:173229.3-173230.37" *)
  reg _073_;
  (* src = "libresoc.v:173214.7-173214.25" *)
  reg _074_;
  (* src = "libresoc.v:173456.3-173474.6" *)
  reg _075_;
  (* src = "libresoc.v:173231.3-173232.35" *)
  reg _076_;
  (* src = "libresoc.v:173418.3-173436.6" *)
  reg [3:0] _077_;
  (* src = "libresoc.v:172087.13-172087.24" *)
  reg [3:0] _078_;
  (* src = "libresoc.v:173418.3-173436.6" *)
  reg _079_;
  (* src = "libresoc.v:172096.7-172096.21" *)
  reg _080_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [3:0] _081_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [13:0] _082_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [63:0] _083_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _084_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [1:0] _085_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [31:0] _086_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [6:0] _087_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _088_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _089_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _090_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _091_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _092_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _093_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _094_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _095_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _096_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _097_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _098_;
  (* src = "libresoc.v:173493.3-173505.6" *)
  reg [1:0] _099_;
  (* src = "libresoc.v:173399.3-173417.6" *)
  reg [63:0] _100_;
  (* src = "libresoc.v:172576.14-172576.38" *)
  reg [63:0] _101_;
  (* src = "libresoc.v:173399.3-173417.6" *)
  reg _102_;
  (* src = "libresoc.v:172583.7-172583.18" *)
  reg _103_;
  (* src = "libresoc.v:173475.3-173492.6" *)
  reg _104_;
  (* src = "libresoc.v:173179.7-173179.20" *)
  reg _105_;
  (* src = "libresoc.v:173437.3-173455.6" *)
  reg [1:0] _106_;
  (* src = "libresoc.v:173194.13-173194.26" *)
  reg [1:0] _107_;
  (* src = "libresoc.v:173437.3-173455.6" *)
  reg _108_;
  (* src = "libresoc.v:173201.7-173201.23" *)
  reg _109_;
  (* src = "libresoc.v:173456.3-173474.6" *)
  reg _110_;
  (* src = "libresoc.v:173456.3-173474.6" *)
  reg _111_;
  (* src = "libresoc.v:173219.7-173219.23" *)
  reg _112_;
  (* src = "libresoc.v:173418.3-173436.6" *)
  reg _113_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg [63:0] _114_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _115_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _116_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _117_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _118_;
  (* src = "libresoc.v:173506.3-173547.6" *)
  reg _119_;
  (* src = "libresoc.v:173399.3-173417.6" *)
  reg _120_;
  (* src = "libresoc.v:173475.3-173492.6" *)
  reg _121_;
  (* src = "libresoc.v:173437.3-173455.6" *)
  reg _122_;
  (* src = "libresoc.v:173456.3-173474.6" *)
  reg _123_;
  (* src = "libresoc.v:173228.18-173228.118" *)
  wire _124_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [3:0] cr_a;
  reg [3:0] cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \cr_a$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [3:0] \cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  reg cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \cr_a_ok$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  input div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  input dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  input dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  input dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  input divisor_neg;
  (* src = "libresoc.v:172078.7-172078.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  reg [3:0] \logical_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$93 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  reg [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$3$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  reg [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  reg \logical_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$80 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  reg [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$12$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  reg [31:0] \logical_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$19$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$94 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  reg [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$2$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  reg \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$10$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  reg \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$13$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  reg \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$16$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  reg \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$17$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  reg \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  reg \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  reg \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$15$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  reg \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  reg \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  reg \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$14$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  reg \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$86 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  reg [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$76 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \o$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [63:0] \o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \o_ok$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] output_cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] \output_cr_a$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] output_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \output_logical_op__data_len$58 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_logical_op__fn_unit$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_logical_op__imm_data__data$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__imm_data__ok$45 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] output_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \output_logical_op__input_carry$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_logical_op__insn$59 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_logical_op__insn_type$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__invert_in$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__invert_out$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__is_32bit$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__is_signed$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__oe__oe$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__oe__ok$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__output_carry$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__rc__ok$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__rc__rc$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__write_cr0$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_logical_op__zero_a$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_muxid$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \output_o$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_o_ok$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire output_stage_div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire output_stage_dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire output_stage_dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire output_stage_dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire output_stage_divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] output_stage_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \output_stage_logical_op__data_len$38 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] output_stage_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \output_stage_logical_op__fn_unit$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] output_stage_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \output_stage_logical_op__imm_data__data$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__imm_data__ok$25 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] output_stage_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \output_stage_logical_op__input_carry$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] output_stage_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \output_stage_logical_op__insn$39 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] output_stage_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \output_stage_logical_op__insn_type$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__invert_in$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__invert_out$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__is_32bit$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__is_signed$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__oe__oe$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__oe__ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__output_carry$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__rc__ok$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__rc__rc$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__write_cr0$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire output_stage_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \output_stage_logical_op__zero_a$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] output_stage_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \output_stage_muxid$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] output_stage_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_stage_o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  wire [63:0] output_stage_quotient_root;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  wire [191:0] output_stage_remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_stage_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_stage_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire output_stage_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_stage_xer_so$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] output_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \output_xer_ov$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \output_xer_so$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire output_xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$73 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  input [63:0] quotient_root;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \ra$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \rb$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  input [191:0] remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] xer_ov;
  reg [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] \xer_ov$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [1:0] \xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_ov_ok$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$20 ;
  reg \xer_so$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so$20$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \xer_so_ok$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \xer_so_ok$next ;
  assign _124_ = \p_valid_i$73  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:173285.10-173288.4" *)
  \n$82  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:173289.15-173341.4" *)
  \output$83  \output  (
    .cr_a(output_cr_a),
    .\cr_a$22 (\output_cr_a$62 ),
    .cr_a_ok(output_cr_a_ok),
    .logical_op__data_len(output_logical_op__data_len),
    .\logical_op__data_len$18 (\output_logical_op__data_len$58 ),
    .logical_op__fn_unit(output_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\output_logical_op__fn_unit$43 ),
    .logical_op__imm_data__data(output_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\output_logical_op__imm_data__data$44 ),
    .logical_op__imm_data__ok(output_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\output_logical_op__imm_data__ok$45 ),
    .logical_op__input_carry(output_logical_op__input_carry),
    .\logical_op__input_carry$12 (\output_logical_op__input_carry$52 ),
    .logical_op__insn(output_logical_op__insn),
    .\logical_op__insn$19 (\output_logical_op__insn$59 ),
    .logical_op__insn_type(output_logical_op__insn_type),
    .\logical_op__insn_type$2 (\output_logical_op__insn_type$42 ),
    .logical_op__invert_in(output_logical_op__invert_in),
    .\logical_op__invert_in$10 (\output_logical_op__invert_in$50 ),
    .logical_op__invert_out(output_logical_op__invert_out),
    .\logical_op__invert_out$13 (\output_logical_op__invert_out$53 ),
    .logical_op__is_32bit(output_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\output_logical_op__is_32bit$56 ),
    .logical_op__is_signed(output_logical_op__is_signed),
    .\logical_op__is_signed$17 (\output_logical_op__is_signed$57 ),
    .logical_op__oe__oe(output_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\output_logical_op__oe__oe$48 ),
    .logical_op__oe__ok(output_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\output_logical_op__oe__ok$49 ),
    .logical_op__output_carry(output_logical_op__output_carry),
    .\logical_op__output_carry$15 (\output_logical_op__output_carry$55 ),
    .logical_op__rc__ok(output_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\output_logical_op__rc__ok$47 ),
    .logical_op__rc__rc(output_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\output_logical_op__rc__rc$46 ),
    .logical_op__write_cr0(output_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\output_logical_op__write_cr0$54 ),
    .logical_op__zero_a(output_logical_op__zero_a),
    .\logical_op__zero_a$11 (\output_logical_op__zero_a$51 ),
    .muxid(output_muxid),
    .\muxid$1 (\output_muxid$41 ),
    .o(output_o),
    .\o$20 (\output_o$60 ),
    .o_ok(output_o_ok),
    .\o_ok$21 (\output_o_ok$61 ),
    .xer_ov(output_xer_ov),
    .\xer_ov$23 (\output_xer_ov$63 ),
    .xer_ov_ok(output_xer_ov_ok),
    .xer_so(output_xer_so),
    .\xer_so$24 (\output_xer_so$64 ),
    .xer_so_ok(output_xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:173342.16-173394.4" *)
  output_stage output_stage (
    .div_by_zero(output_stage_div_by_zero),
    .dive_abs_ov32(output_stage_dive_abs_ov32),
    .dive_abs_ov64(output_stage_dive_abs_ov64),
    .dividend_neg(output_stage_dividend_neg),
    .divisor_neg(output_stage_divisor_neg),
    .logical_op__data_len(output_stage_logical_op__data_len),
    .\logical_op__data_len$18 (\output_stage_logical_op__data_len$38 ),
    .logical_op__fn_unit(output_stage_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\output_stage_logical_op__fn_unit$23 ),
    .logical_op__imm_data__data(output_stage_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\output_stage_logical_op__imm_data__data$24 ),
    .logical_op__imm_data__ok(output_stage_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\output_stage_logical_op__imm_data__ok$25 ),
    .logical_op__input_carry(output_stage_logical_op__input_carry),
    .\logical_op__input_carry$12 (\output_stage_logical_op__input_carry$32 ),
    .logical_op__insn(output_stage_logical_op__insn),
    .\logical_op__insn$19 (\output_stage_logical_op__insn$39 ),
    .logical_op__insn_type(output_stage_logical_op__insn_type),
    .\logical_op__insn_type$2 (\output_stage_logical_op__insn_type$22 ),
    .logical_op__invert_in(output_stage_logical_op__invert_in),
    .\logical_op__invert_in$10 (\output_stage_logical_op__invert_in$30 ),
    .logical_op__invert_out(output_stage_logical_op__invert_out),
    .\logical_op__invert_out$13 (\output_stage_logical_op__invert_out$33 ),
    .logical_op__is_32bit(output_stage_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\output_stage_logical_op__is_32bit$36 ),
    .logical_op__is_signed(output_stage_logical_op__is_signed),
    .\logical_op__is_signed$17 (\output_stage_logical_op__is_signed$37 ),
    .logical_op__oe__oe(output_stage_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\output_stage_logical_op__oe__oe$28 ),
    .logical_op__oe__ok(output_stage_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\output_stage_logical_op__oe__ok$29 ),
    .logical_op__output_carry(output_stage_logical_op__output_carry),
    .\logical_op__output_carry$15 (\output_stage_logical_op__output_carry$35 ),
    .logical_op__rc__ok(output_stage_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\output_stage_logical_op__rc__ok$27 ),
    .logical_op__rc__rc(output_stage_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\output_stage_logical_op__rc__rc$26 ),
    .logical_op__write_cr0(output_stage_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\output_stage_logical_op__write_cr0$34 ),
    .logical_op__zero_a(output_stage_logical_op__zero_a),
    .\logical_op__zero_a$11 (\output_stage_logical_op__zero_a$31 ),
    .muxid(output_stage_muxid),
    .\muxid$1 (\output_stage_muxid$21 ),
    .o(output_stage_o),
    .o_ok(output_stage_o_ok),
    .quotient_root(output_stage_quotient_root),
    .remainder(output_stage_remainder),
    .xer_ov(output_stage_xer_ov),
    .xer_ov_ok(output_stage_xer_ov_ok),
    .xer_so(output_stage_xer_so),
    .\xer_so$20 (\output_stage_xer_so$40 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:173395.10-173398.4" *)
  \p$81  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _004_ = 1'h0;
  end
  always @* begin
      \initial  <= _004_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      cr_a <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cr_a_ok <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__data_len$18  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \logical_op__fn_unit$3  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__data$4  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__ok$5  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__input_carry$12  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn$19  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn_type$2  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_in$10  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_out$13  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_32bit$16  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_signed$17  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__oe$8  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__ok$9  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__output_carry$15  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__ok$7  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__rc$6  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__write_cr0$14  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__zero_a$11  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$1  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      o <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      o_ok <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_ov_ok <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$20  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so_ok <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \xer_so$20$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$20  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so_ok <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = \xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      xer_ov_ok <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      cr_a_ok <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \o$next ;
  end
  always @(posedge coresync_clk) begin
      o <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      o_ok <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \logical_op__insn_type$2$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn_type$2  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \logical_op__fn_unit$3$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__fn_unit$3  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = \logical_op__imm_data__data$4$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__data$4  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \logical_op__imm_data__ok$5$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__ok$5  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \logical_op__rc__rc$6$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__rc$6  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \logical_op__rc__ok$7$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__ok$7  <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \logical_op__oe__oe$8$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__oe$8  <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \logical_op__oe__ok$9$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__ok$9  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \logical_op__invert_in$10$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_in$10  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \logical_op__zero_a$11$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__zero_a$11  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \logical_op__input_carry$12$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__input_carry$12  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \logical_op__invert_out$13$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_out$13  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \logical_op__write_cr0$14$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__write_cr0$14  <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \logical_op__output_carry$15$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__output_carry$15  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \logical_op__is_32bit$16$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_32bit$16  <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \logical_op__is_signed$17$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_signed$17  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = \logical_op__data_len$18$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__data_len$18  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \logical_op__insn$19$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn$19  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \muxid$1$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$1  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _100_;
    _064_ = _120_;
    (* src = "libresoc.v:173400.5-173400.29" *)
    casez (\initial )
      /* src = "libresoc.v:173400.9-173400.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _102_, _100_ } = { \o_ok$96 , \o$95  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _102_, _100_ } = { \o_ok$96 , \o$95  };
        end
      default:
        begin
          _100_ = o;
          _102_ = o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _120_ = 1'h0;
        end
      default:
          _120_ = _102_;
    endcase
  end
  always @* begin
      \o$next  <= _062_;
      \o_ok$next  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _077_;
    _002_ = _113_;
    (* src = "libresoc.v:173419.5-173419.29" *)
    casez (\initial )
      /* src = "libresoc.v:173419.9-173419.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _079_, _077_ } = { \cr_a_ok$98 , \cr_a$97  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _079_, _077_ } = { \cr_a_ok$98 , \cr_a$97  };
        end
      default:
        begin
          _077_ = cr_a;
          _079_ = cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = 1'h0;
        end
      default:
          _113_ = _079_;
    endcase
  end
  always @* begin
      \cr_a$next  <= _000_;
      \cr_a_ok$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = _106_;
    _070_ = _122_;
    (* src = "libresoc.v:173438.5-173438.29" *)
    casez (\initial )
      /* src = "libresoc.v:173438.9-173438.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _108_, _106_ } = { \xer_ov_ok$100 , \xer_ov$99  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _108_, _106_ } = { \xer_ov_ok$100 , \xer_ov$99  };
        end
      default:
        begin
          _106_ = xer_ov;
          _108_ = xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _122_ = 1'h0;
        end
      default:
          _122_ = _108_;
    endcase
  end
  always @* begin
      \xer_ov$next  <= _068_;
      \xer_ov_ok$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _110_;
    _075_ = _123_;
    (* src = "libresoc.v:173457.5-173457.29" *)
    casez (\initial )
      /* src = "libresoc.v:173457.9-173457.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _111_, _110_ } = { \xer_so_ok$102 , \xer_so$101  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _111_, _110_ } = { \xer_so_ok$102 , \xer_so$101  };
        end
      default:
        begin
          _111_ = xer_so_ok;
          _110_ = \xer_so$20 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _123_ = 1'h0;
        end
      default:
          _123_ = _111_;
    endcase
  end
  always @* begin
      \xer_so_ok$next  <= _075_;
      \xer_so$20$next  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _121_;
    (* src = "libresoc.v:173476.5-173476.29" *)
    casez (\initial )
      /* src = "libresoc.v:173476.9-173476.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _104_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _104_ = 1'h0;
        end
      default:
          _104_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = 1'h0;
        end
      default:
          _121_ = _104_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _099_;
    (* src = "libresoc.v:173494.5-173494.29" *)
    casez (\initial )
      /* src = "libresoc.v:173494.9-173494.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _099_ = \muxid$76 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _099_ = \muxid$76 ;
        end
      default:
          _099_ = \muxid$1 ;
    endcase
  end
  always @* begin
      \muxid$1$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _081_;
    _008_ = _082_;
    _017_ = _085_;
    _020_ = _086_;
    _023_ = _087_;
    _026_ = _088_;
    _029_ = _089_;
    _032_ = _090_;
    _035_ = _091_;
    _044_ = _094_;
    _053_ = _097_;
    _056_ = _098_;
    _011_ = _114_;
    _014_ = _115_;
    _038_ = _116_;
    _041_ = _117_;
    _047_ = _118_;
    _050_ = _119_;
    (* src = "libresoc.v:173507.5-173507.29" *)
    casez (\initial )
      /* src = "libresoc.v:173507.9-173507.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _086_, _081_, _091_, _090_, _094_, _097_, _089_, _085_, _098_, _088_, _093_, _092_, _095_, _096_, _084_, _083_, _082_, _087_ } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _086_, _081_, _091_, _090_, _094_, _097_, _089_, _085_, _098_, _088_, _093_, _092_, _095_, _096_, _084_, _083_, _082_, _087_ } = { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77  };
        end
      default:
        begin
          _081_ = \logical_op__data_len$18 ;
          _082_ = \logical_op__fn_unit$3 ;
          _083_ = \logical_op__imm_data__data$4 ;
          _084_ = \logical_op__imm_data__ok$5 ;
          _085_ = \logical_op__input_carry$12 ;
          _086_ = \logical_op__insn$19 ;
          _087_ = \logical_op__insn_type$2 ;
          _088_ = \logical_op__invert_in$10 ;
          _089_ = \logical_op__invert_out$13 ;
          _090_ = \logical_op__is_32bit$16 ;
          _091_ = \logical_op__is_signed$17 ;
          _092_ = \logical_op__oe__oe$8 ;
          _093_ = \logical_op__oe__ok$9 ;
          _094_ = \logical_op__output_carry$15 ;
          _095_ = \logical_op__rc__ok$7 ;
          _096_ = \logical_op__rc__rc$6 ;
          _097_ = \logical_op__write_cr0$14 ;
          _098_ = \logical_op__zero_a$11 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _114_ = 64'h0000000000000000;
          _115_ = 1'h0;
          _119_ = 1'h0;
          _118_ = 1'h0;
          _116_ = 1'h0;
          _117_ = 1'h0;
        end
      default:
        begin
          _114_ = _083_;
          _115_ = _084_;
          _116_ = _092_;
          _117_ = _093_;
          _118_ = _095_;
          _119_ = _096_;
        end
    endcase
  end
  always @* begin
      \logical_op__data_len$18$next  <= _005_;
      \logical_op__fn_unit$3$next  <= _008_;
      \logical_op__imm_data__data$4$next  <= _011_;
      \logical_op__imm_data__ok$5$next  <= _014_;
      \logical_op__input_carry$12$next  <= _017_;
      \logical_op__insn$19$next  <= _020_;
      \logical_op__insn_type$2$next  <= _023_;
      \logical_op__invert_in$10$next  <= _026_;
      \logical_op__invert_out$13$next  <= _029_;
      \logical_op__is_32bit$16$next  <= _032_;
      \logical_op__is_signed$17$next  <= _035_;
      \logical_op__oe__oe$8$next  <= _038_;
      \logical_op__oe__ok$9$next  <= _041_;
      \logical_op__output_carry$15$next  <= _044_;
      \logical_op__rc__ok$7$next  <= _047_;
      \logical_op__rc__rc$6$next  <= _050_;
      \logical_op__write_cr0$14$next  <= _053_;
      \logical_op__zero_a$11$next  <= _056_;
  end
  assign \$74  = _124_;
  assign \cr_a$68  = 4'h0;
  assign \cr_a_ok$69  = 1'h0;
  assign \xer_so_ok$72  = 1'h0;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign { \xer_so_ok$102 , \xer_so$101  } = { output_xer_so_ok, \output_xer_so$64  };
  assign { \xer_ov_ok$100 , \xer_ov$99  } = { output_xer_ov_ok, \output_xer_ov$63  };
  assign { \cr_a_ok$98 , \cr_a$97  } = { output_cr_a_ok, \output_cr_a$62  };
  assign { \o_ok$96 , \o$95  } = { \output_o_ok$61 , \output_o$60  };
  assign { \logical_op__insn$94 , \logical_op__data_len$93 , \logical_op__is_signed$92 , \logical_op__is_32bit$91 , \logical_op__output_carry$90 , \logical_op__write_cr0$89 , \logical_op__invert_out$88 , \logical_op__input_carry$87 , \logical_op__zero_a$86 , \logical_op__invert_in$85 , \logical_op__oe__ok$84 , \logical_op__oe__oe$83 , \logical_op__rc__ok$82 , \logical_op__rc__rc$81 , \logical_op__imm_data__ok$80 , \logical_op__imm_data__data$79 , \logical_op__fn_unit$78 , \logical_op__insn_type$77  } = { \output_logical_op__insn$59 , \output_logical_op__data_len$58 , \output_logical_op__is_signed$57 , \output_logical_op__is_32bit$56 , \output_logical_op__output_carry$55 , \output_logical_op__write_cr0$54 , \output_logical_op__invert_out$53 , \output_logical_op__input_carry$52 , \output_logical_op__zero_a$51 , \output_logical_op__invert_in$50 , \output_logical_op__oe__ok$49 , \output_logical_op__oe__oe$48 , \output_logical_op__rc__ok$47 , \output_logical_op__rc__rc$46 , \output_logical_op__imm_data__ok$45 , \output_logical_op__imm_data__data$44 , \output_logical_op__fn_unit$43 , \output_logical_op__insn_type$42  };
  assign \muxid$76  = \output_muxid$41 ;
  assign p_valid_i_p_ready_o = \$74 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$73  = p_valid_i;
  assign { \xer_so_ok$71 , output_xer_so } = { 1'h0, \output_stage_xer_so$40  };
  assign { \xer_ov_ok$70 , output_xer_ov } = { output_stage_xer_ov_ok, output_stage_xer_ov };
  assign { \cr_a_ok$67 , output_cr_a } = 5'h00;
  assign { output_o_ok, output_o } = { output_stage_o_ok, output_stage_o };
  assign { output_logical_op__insn, output_logical_op__data_len, output_logical_op__is_signed, output_logical_op__is_32bit, output_logical_op__output_carry, output_logical_op__write_cr0, output_logical_op__invert_out, output_logical_op__input_carry, output_logical_op__zero_a, output_logical_op__invert_in, output_logical_op__oe__ok, output_logical_op__oe__oe, output_logical_op__rc__ok, output_logical_op__rc__rc, output_logical_op__imm_data__ok, output_logical_op__imm_data__data, output_logical_op__fn_unit, output_logical_op__insn_type } = { \output_stage_logical_op__insn$39 , \output_stage_logical_op__data_len$38 , \output_stage_logical_op__is_signed$37 , \output_stage_logical_op__is_32bit$36 , \output_stage_logical_op__output_carry$35 , \output_stage_logical_op__write_cr0$34 , \output_stage_logical_op__invert_out$33 , \output_stage_logical_op__input_carry$32 , \output_stage_logical_op__zero_a$31 , \output_stage_logical_op__invert_in$30 , \output_stage_logical_op__oe__ok$29 , \output_stage_logical_op__oe__oe$28 , \output_stage_logical_op__rc__ok$27 , \output_stage_logical_op__rc__rc$26 , \output_stage_logical_op__imm_data__ok$25 , \output_stage_logical_op__imm_data__data$24 , \output_stage_logical_op__fn_unit$23 , \output_stage_logical_op__insn_type$22  };
  assign output_muxid = \output_stage_muxid$21 ;
  assign output_stage_remainder = remainder;
  assign output_stage_quotient_root = quotient_root;
  assign output_stage_div_by_zero = div_by_zero;
  assign output_stage_dive_abs_ov64 = dive_abs_ov64;
  assign output_stage_dive_abs_ov32 = dive_abs_ov32;
  assign output_stage_dividend_neg = dividend_neg;
  assign output_stage_divisor_neg = divisor_neg;
  assign output_stage_xer_so = xer_so;
  assign \rb$66  = rb;
  assign \ra$65  = ra;
  assign { output_stage_logical_op__insn, output_stage_logical_op__data_len, output_stage_logical_op__is_signed, output_stage_logical_op__is_32bit, output_stage_logical_op__output_carry, output_stage_logical_op__write_cr0, output_stage_logical_op__invert_out, output_stage_logical_op__input_carry, output_stage_logical_op__zero_a, output_stage_logical_op__invert_in, output_stage_logical_op__oe__ok, output_stage_logical_op__oe__oe, output_stage_logical_op__rc__ok, output_stage_logical_op__rc__rc, output_stage_logical_op__imm_data__ok, output_stage_logical_op__imm_data__data, output_stage_logical_op__fn_unit, output_stage_logical_op__insn_type } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign output_stage_muxid = muxid;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:173584.1-174571.10" *)
module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, n_valid_o, n_ready_i, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , \divisor_neg$23 , \dividend_neg$24 , \dive_abs_ov32$25 , \dive_abs_ov64$26 , \div_by_zero$27 , quotient_root, remainder, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:174496.3-174510.6" *)
  reg _000_;
  (* src = "libresoc.v:173607.7-173607.30" *)
  reg _001_;
  (* src = "libresoc.v:174170.3-174171.47" *)
  reg _002_;
  (* src = "libresoc.v:174292.3-174303.6" *)
  reg [63:0] _003_;
  (* src = "libresoc.v:174280.3-174291.6" *)
  reg [127:0] _004_;
  (* src = "libresoc.v:174268.3-174279.6" *)
  reg [6:0] _005_;
  (* src = "libresoc.v:174466.3-174480.6" *)
  reg _006_;
  (* src = "libresoc.v:173631.7-173631.32" *)
  reg _007_;
  (* src = "libresoc.v:174174.3-174175.51" *)
  reg _008_;
  (* src = "libresoc.v:174481.3-174495.6" *)
  reg _009_;
  (* src = "libresoc.v:173639.7-173639.32" *)
  reg _010_;
  (* src = "libresoc.v:174172.3-174173.51" *)
  reg _011_;
  (* src = "libresoc.v:174511.3-174525.6" *)
  reg [127:0] _012_;
  (* src = "libresoc.v:173645.15-173645.68" *)
  reg [127:0] _013_;
  (* src = "libresoc.v:174168.3-174169.41" *)
  reg [127:0] _014_;
  (* src = "libresoc.v:174451.3-174465.6" *)
  reg _015_;
  (* src = "libresoc.v:173653.7-173653.31" *)
  reg _016_;
  (* src = "libresoc.v:174176.3-174177.49" *)
  reg _017_;
  (* src = "libresoc.v:174436.3-174450.6" *)
  reg _018_;
  (* src = "libresoc.v:173661.7-173661.30" *)
  reg _019_;
  (* src = "libresoc.v:174178.3-174179.47" *)
  reg _020_;
  (* src = "libresoc.v:174526.3-174540.6" *)
  reg [63:0] _021_;
  (* src = "libresoc.v:173667.14-173667.58" *)
  reg [63:0] _022_;
  (* src = "libresoc.v:174166.3-174167.57" *)
  reg [63:0] _023_;
  (* src = "libresoc.v:174304.3-174331.6" *)
  reg _024_;
  (* src = "libresoc.v:174224.3-174225.27" *)
  reg _025_;
  (* src = "libresoc.v:173585.7-173585.20" *)
  reg _026_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [3:0] _027_;
  (* src = "libresoc.v:174218.3-174219.65" *)
  reg [3:0] _028_;
  (* src = "libresoc.v:173679.13-173679.45" *)
  reg [3:0] _029_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [13:0] _030_;
  (* src = "libresoc.v:173732.14-173732.49" *)
  reg [13:0] _031_;
  (* src = "libresoc.v:174188.3-174189.63" *)
  reg [13:0] _032_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [63:0] _033_;
  (* src = "libresoc.v:173738.14-173738.68" *)
  reg [63:0] _034_;
  (* src = "libresoc.v:174190.3-174191.77" *)
  reg [63:0] _035_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _036_;
  (* src = "libresoc.v:173746.7-173746.43" *)
  reg _037_;
  (* src = "libresoc.v:174192.3-174193.73" *)
  reg _038_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [1:0] _039_;
  (* src = "libresoc.v:173768.13-173768.48" *)
  reg [1:0] _040_;
  (* src = "libresoc.v:174206.3-174207.71" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [31:0] _042_;
  (* src = "libresoc.v:174220.3-174221.57" *)
  reg [31:0] _043_;
  (* src = "libresoc.v:173776.14-173776.43" *)
  reg [31:0] _044_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [6:0] _045_;
  (* src = "libresoc.v:174009.13-174009.47" *)
  reg [6:0] _046_;
  (* src = "libresoc.v:174186.3-174187.67" *)
  reg [6:0] _047_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _048_;
  (* src = "libresoc.v:174017.7-174017.40" *)
  reg _049_;
  (* src = "libresoc.v:174202.3-174203.67" *)
  reg _050_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _051_;
  (* src = "libresoc.v:174025.7-174025.41" *)
  reg _052_;
  (* src = "libresoc.v:174208.3-174209.69" *)
  reg _053_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _054_;
  (* src = "libresoc.v:174214.3-174215.65" *)
  reg _055_;
  (* src = "libresoc.v:174033.7-174033.39" *)
  reg _056_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _057_;
  (* src = "libresoc.v:174216.3-174217.67" *)
  reg _058_;
  (* src = "libresoc.v:174041.7-174041.40" *)
  reg _059_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _060_;
  (* src = "libresoc.v:174047.7-174047.37" *)
  reg _061_;
  (* src = "libresoc.v:174198.3-174199.61" *)
  reg _062_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _063_;
  (* src = "libresoc.v:174055.7-174055.37" *)
  reg _064_;
  (* src = "libresoc.v:174200.3-174201.61" *)
  reg _065_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _066_;
  (* src = "libresoc.v:174212.3-174213.73" *)
  reg _067_;
  (* src = "libresoc.v:174065.7-174065.43" *)
  reg _068_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _069_;
  (* src = "libresoc.v:174071.7-174071.37" *)
  reg _070_;
  (* src = "libresoc.v:174196.3-174197.61" *)
  reg _071_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _072_;
  (* src = "libresoc.v:174079.7-174079.37" *)
  reg _073_;
  (* src = "libresoc.v:174194.3-174195.61" *)
  reg _074_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _075_;
  (* src = "libresoc.v:174210.3-174211.67" *)
  reg _076_;
  (* src = "libresoc.v:174089.7-174089.40" *)
  reg _077_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _078_;
  (* src = "libresoc.v:174097.7-174097.37" *)
  reg _079_;
  (* src = "libresoc.v:174204.3-174205.61" *)
  reg _080_;
  (* src = "libresoc.v:174332.3-174346.6" *)
  reg [1:0] _081_;
  (* src = "libresoc.v:174222.3-174223.35" *)
  reg [1:0] _082_;
  (* src = "libresoc.v:174105.13-174105.30" *)
  reg [1:0] _083_;
  (* src = "libresoc.v:174541.3-174555.6" *)
  reg [1:0] _084_;
  (* src = "libresoc.v:174115.13-174115.34" *)
  reg [1:0] _085_;
  (* src = "libresoc.v:174164.3-174165.43" *)
  reg [1:0] _086_;
  (* src = "libresoc.v:174391.3-174405.6" *)
  reg [63:0] _087_;
  (* src = "libresoc.v:174129.14-174129.44" *)
  reg [63:0] _088_;
  (* src = "libresoc.v:174184.3-174185.29" *)
  reg [63:0] _089_;
  (* src = "libresoc.v:174406.3-174420.6" *)
  reg [63:0] _090_;
  (* src = "libresoc.v:174137.14-174137.44" *)
  reg [63:0] _091_;
  (* src = "libresoc.v:174182.3-174183.29" *)
  reg [63:0] _092_;
  (* src = "libresoc.v:174259.3-174267.6" *)
  reg [127:0] _093_;
  (* src = "libresoc.v:174226.3-174227.75" *)
  reg [127:0] _094_;
  (* src = "libresoc.v:174250.3-174258.6" *)
  reg [6:0] _095_;
  (* src = "libresoc.v:174228.3-174229.65" *)
  reg [6:0] _096_;
  (* src = "libresoc.v:174421.3-174435.6" *)
  reg _097_;
  (* src = "libresoc.v:174155.7-174155.25" *)
  reg _098_;
  (* src = "libresoc.v:174180.3-174181.37" *)
  reg _099_;
  (* src = "libresoc.v:174496.3-174510.6" *)
  reg _100_;
  (* src = "libresoc.v:174292.3-174303.6" *)
  reg [63:0] _101_;
  (* src = "libresoc.v:174280.3-174291.6" *)
  reg [127:0] _102_;
  (* src = "libresoc.v:174268.3-174279.6" *)
  reg [6:0] _103_;
  (* src = "libresoc.v:174466.3-174480.6" *)
  reg _104_;
  (* src = "libresoc.v:174481.3-174495.6" *)
  reg _105_;
  (* src = "libresoc.v:174511.3-174525.6" *)
  reg [127:0] _106_;
  (* src = "libresoc.v:174451.3-174465.6" *)
  reg _107_;
  (* src = "libresoc.v:174436.3-174450.6" *)
  reg _108_;
  (* src = "libresoc.v:174526.3-174540.6" *)
  reg [63:0] _109_;
  (* src = "libresoc.v:174304.3-174331.6" *)
  reg _110_;
  (* src = "libresoc.v:173671.7-173671.19" *)
  reg _111_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [3:0] _112_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [13:0] _113_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [63:0] _114_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _115_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [1:0] _116_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [31:0] _117_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [6:0] _118_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _119_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _120_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _121_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _122_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _123_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _124_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _125_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _126_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _127_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _128_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _129_;
  (* src = "libresoc.v:174332.3-174346.6" *)
  reg [1:0] _130_;
  (* src = "libresoc.v:174541.3-174555.6" *)
  reg [1:0] _131_;
  (* src = "libresoc.v:174391.3-174405.6" *)
  reg [63:0] _132_;
  (* src = "libresoc.v:174406.3-174420.6" *)
  reg [63:0] _133_;
  (* src = "libresoc.v:174259.3-174267.6" *)
  reg [127:0] _134_;
  (* src = "libresoc.v:174143.15-174143.84" *)
  reg [127:0] _135_;
  (* src = "libresoc.v:174250.3-174258.6" *)
  reg [6:0] _136_;
  (* src = "libresoc.v:174147.13-174147.45" *)
  reg [6:0] _137_;
  (* src = "libresoc.v:174421.3-174435.6" *)
  reg _138_;
  (* src = "libresoc.v:174496.3-174510.6" *)
  reg _139_;
  (* src = "libresoc.v:174466.3-174480.6" *)
  reg _140_;
  (* src = "libresoc.v:174481.3-174495.6" *)
  reg _141_;
  (* src = "libresoc.v:174511.3-174525.6" *)
  reg [127:0] _142_;
  (* src = "libresoc.v:174451.3-174465.6" *)
  reg _143_;
  (* src = "libresoc.v:174436.3-174450.6" *)
  reg _144_;
  (* src = "libresoc.v:174526.3-174540.6" *)
  reg [63:0] _145_;
  (* src = "libresoc.v:174304.3-174331.6" *)
  reg _146_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [3:0] _147_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [13:0] _148_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [63:0] _149_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _150_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [1:0] _151_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [31:0] _152_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [6:0] _153_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _154_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _155_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _156_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _157_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _158_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _159_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _160_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _161_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _162_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _163_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _164_;
  (* src = "libresoc.v:174332.3-174346.6" *)
  reg [1:0] _165_;
  (* src = "libresoc.v:174541.3-174555.6" *)
  reg [1:0] _166_;
  (* src = "libresoc.v:174391.3-174405.6" *)
  reg [63:0] _167_;
  (* src = "libresoc.v:174406.3-174420.6" *)
  reg [63:0] _168_;
  (* src = "libresoc.v:174421.3-174435.6" *)
  reg _169_;
  (* src = "libresoc.v:174304.3-174331.6" *)
  reg _170_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg [63:0] _171_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _172_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _173_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _174_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _175_;
  (* src = "libresoc.v:174347.3-174390.6" *)
  reg _176_;
  (* src = "libresoc.v:174304.3-174331.6" *)
  reg _177_;
  (* src = "libresoc.v:174162.18-174162.98" *)
  wire _178_;
  (* src = "libresoc.v:174163.18-174163.107" *)
  wire _179_;
  (* src = "libresoc.v:174159.18-174159.92" *)
  wire [191:0] _180_;
  (* src = "libresoc.v:174161.18-174161.119" *)
  wire _181_;
  (* src = "libresoc.v:174160.18-174160.93" *)
  wire _182_;
  (* src = "libresoc.v:174159.18-174159.92" *)
  wire [191:0] _183_;
  (* src = "libresoc.v:174158.18-174158.138" *)
  wire [190:0] _184_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *)
  wire [191:0] \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *)
  wire [190:0] \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
  wire \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  input div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  output \div_by_zero$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  reg \div_by_zero$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  reg \div_by_zero$54$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" *)
  wire [127:0] div_state_init_dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  wire [127:0] div_state_init_o_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  wire [6:0] div_state_init_o_q_bits_known;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" *)
  reg [63:0] div_state_next_divisor;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  reg [127:0] div_state_next_i_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  reg [6:0] div_state_next_i_q_bits_known;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  wire [127:0] div_state_next_o_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  wire [6:0] div_state_next_o_q_bits_known;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  input dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  output \dive_abs_ov32$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  reg \dive_abs_ov32$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  reg \dive_abs_ov32$52$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  input dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  output \dive_abs_ov64$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  reg \dive_abs_ov64$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  reg \dive_abs_ov64$53$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  input [127:0] dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  reg [127:0] \dividend$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  reg [127:0] \dividend$68$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  input dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  output \dividend_neg$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  reg \dividend_neg$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  reg \dividend_neg$51$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  input divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  output \divisor_neg$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  reg \divisor_neg$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  reg \divisor_neg$50$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  input [63:0] divisor_radicand;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  reg [63:0] \divisor_radicand$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  reg [63:0] \divisor_radicand$65$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *)
  reg empty;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" *)
  reg \empty$next ;
  (* src = "libresoc.v:173585.7-173585.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$45$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$30$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$31$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$32$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$39$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$46$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$29$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$37$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$40$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$43$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$44$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$35$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$36$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$42$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$34$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$33$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$41$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$38$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$28$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  input [1:0] operation;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  reg [1:0] \operation$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  reg [1:0] \operation$69$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" *)
  output [63:0] quotient_root;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \ra$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \ra$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \ra$47$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] \rb$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \rb$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \rb$48$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" *)
  output [191:0] remainder;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  reg [127:0] saved_state_dividend_quotient;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" *)
  reg [127:0] \saved_state_dividend_quotient$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  reg [6:0] saved_state_q_bits_known;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" *)
  reg [6:0] \saved_state_q_bits_known$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg \xer_so$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg \xer_so$49$next ;
  assign _178_ = \$59  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) \$61 ;
  assign _179_ = n_ready_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) n_valid_o;
  assign _180_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) \$56 ;
  assign _181_ = saved_state_q_bits_known >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" *) 6'h3f;
  assign _182_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" *) empty;
  assign _183_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) _180_;
  assign _184_ = div_state_next_o_dividend_quotient[127:64] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" *) 7'h40;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:174230.18-174234.4" *)
  div_state_init div_state_init (
    .dividend(div_state_init_dividend),
    .o_dividend_quotient(div_state_init_o_dividend_quotient),
    .o_q_bits_known(div_state_init_o_q_bits_known)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:174235.18-174241.4" *)
  div_state_next div_state_next (
    .divisor(div_state_next_divisor),
    .i_dividend_quotient(div_state_next_i_dividend_quotient),
    .i_q_bits_known(div_state_next_i_q_bits_known),
    .o_dividend_quotient(div_state_next_o_dividend_quotient),
    .o_q_bits_known(div_state_next_o_q_bits_known)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:174242.10-174245.4" *)
  \n$80  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:174246.10-174249.4" *)
  \p$79  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  always @* begin
    if (\initial ) begin end
    _026_ = 1'h0;
  end
  always @* begin
      \initial  <= _026_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _001_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \div_by_zero$54  <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \dive_abs_ov32$52  <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \dive_abs_ov64$53  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = 128'h00000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      \dividend$68  <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \dividend_neg$51  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \divisor_neg$50  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \divisor_radicand$65  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      empty <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__data_len$45  <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      \logical_op__fn_unit$30  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__data$31  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__imm_data__ok$32  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__input_carry$39  <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn$46  <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \logical_op__insn_type$29  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_in$37  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__invert_out$40  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_32bit$43  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__is_signed$44  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__oe$35  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__oe__ok$36  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__output_carry$42  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__ok$34  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__rc__rc$33  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__write_cr0$41  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \logical_op__zero_a$38  <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \muxid$28  <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \operation$69  <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \ra$47  <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \rb$48  <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 128'h00000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      saved_state_dividend_quotient <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      saved_state_q_bits_known <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \xer_so$49  <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = \operation$69$next ;
  end
  always @(posedge coresync_clk) begin
      \operation$69  <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \divisor_radicand$65$next ;
  end
  always @(posedge coresync_clk) begin
      \divisor_radicand$65  <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = \dividend$68$next ;
  end
  always @(posedge coresync_clk) begin
      \dividend$68  <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = \div_by_zero$54$next ;
  end
  always @(posedge coresync_clk) begin
      \div_by_zero$54  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \dive_abs_ov64$53$next ;
  end
  always @(posedge coresync_clk) begin
      \dive_abs_ov64$53  <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = \dive_abs_ov32$52$next ;
  end
  always @(posedge coresync_clk) begin
      \dive_abs_ov32$52  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \dividend_neg$51$next ;
  end
  always @(posedge coresync_clk) begin
      \dividend_neg$51  <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \divisor_neg$50$next ;
  end
  always @(posedge coresync_clk) begin
      \divisor_neg$50  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = \xer_so$49$next ;
  end
  always @(posedge coresync_clk) begin
      \xer_so$49  <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = \rb$48$next ;
  end
  always @(posedge coresync_clk) begin
      \rb$48  <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = \ra$47$next ;
  end
  always @(posedge coresync_clk) begin
      \ra$47  <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \logical_op__insn_type$29$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn_type$29  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \logical_op__fn_unit$30$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__fn_unit$30  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \logical_op__imm_data__data$31$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__data$31  <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \logical_op__imm_data__ok$32$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__imm_data__ok$32  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \logical_op__rc__rc$33$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__rc$33  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \logical_op__rc__ok$34$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__rc__ok$34  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \logical_op__oe__oe$35$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__oe$35  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \logical_op__oe__ok$36$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__oe__ok$36  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \logical_op__invert_in$37$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_in$37  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = \logical_op__zero_a$38$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__zero_a$38  <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \logical_op__input_carry$39$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__input_carry$39  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \logical_op__invert_out$40$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__invert_out$40  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \logical_op__write_cr0$41$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__write_cr0$41  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \logical_op__output_carry$42$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__output_carry$42  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \logical_op__is_32bit$43$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_32bit$43  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \logical_op__is_signed$44$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__is_signed$44  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \logical_op__data_len$45$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__data_len$45  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \logical_op__insn$46$next ;
  end
  always @(posedge coresync_clk) begin
      \logical_op__insn$46  <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = \muxid$28$next ;
  end
  always @(posedge coresync_clk) begin
      \muxid$28  <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \empty$next ;
  end
  always @(posedge coresync_clk) begin
      empty <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = \saved_state_dividend_quotient$next ;
  end
  always @(posedge coresync_clk) begin
      saved_state_dividend_quotient <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = \saved_state_q_bits_known$next ;
  end
  always @(posedge coresync_clk) begin
      saved_state_q_bits_known <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = _136_;
    (* src = "libresoc.v:174251.5-174251.29" *)
    casez (\initial )
      /* src = "libresoc.v:174251.9-174251.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = 7'h00;
        end
      default:
          _136_ = div_state_next_o_q_bits_known;
    endcase
  end
  always @* begin
      \saved_state_q_bits_known$next  <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = _134_;
    (* src = "libresoc.v:174260.5-174260.29" *)
    casez (\initial )
      /* src = "libresoc.v:174260.9-174260.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = 128'h00000000000000000000000000000000;
        end
      default:
          _134_ = div_state_next_o_dividend_quotient;
    endcase
  end
  always @* begin
      \saved_state_dividend_quotient$next  <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _103_;
    (* src = "libresoc.v:174269.5-174269.29" *)
    casez (\initial )
      /* src = "libresoc.v:174269.9-174269.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = div_state_init_o_q_bits_known;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _103_ = saved_state_q_bits_known;
        end
    endcase
  end
  always @* begin
      div_state_next_i_q_bits_known <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _102_;
    (* src = "libresoc.v:174281.5-174281.29" *)
    casez (\initial )
      /* src = "libresoc.v:174281.9-174281.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _102_ = div_state_init_o_dividend_quotient;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _102_ = saved_state_dividend_quotient;
        end
    endcase
  end
  always @* begin
      div_state_next_i_dividend_quotient <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _101_;
    (* src = "libresoc.v:174293.5-174293.29" *)
    casez (\initial )
      /* src = "libresoc.v:174293.9-174293.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = divisor_radicand;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _101_ = \divisor_radicand$65 ;
        end
    endcase
  end
  always @* begin
      div_state_next_divisor <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _177_;
    (* src = "libresoc.v:174305.5-174305.29" *)
    casez (\initial )
      /* src = "libresoc.v:174305.9-174305.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _110_ = _146_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _146_ = 1'h0;
              end
            default:
                _146_ = empty;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _110_ = _170_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *)
          casez (\$66 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _170_ = 1'h1;
              end
            default:
                _170_ = empty;
          endcase
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _177_ = 1'h1;
        end
      default:
          _177_ = _110_;
    endcase
  end
  always @* begin
      \empty$next  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = _130_;
    (* src = "libresoc.v:174333.5-174333.29" *)
    casez (\initial )
      /* src = "libresoc.v:174333.9-174333.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = _165_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _165_ = muxid;
              end
            default:
                _165_ = \muxid$28 ;
          endcase
        end
      default:
          _130_ = \muxid$28 ;
    endcase
  end
  always @* begin
      \muxid$28$next  <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _112_;
    _030_ = _113_;
    _039_ = _116_;
    _042_ = _117_;
    _045_ = _118_;
    _048_ = _119_;
    _051_ = _120_;
    _054_ = _121_;
    _057_ = _122_;
    _066_ = _125_;
    _075_ = _128_;
    _078_ = _129_;
    _033_ = _171_;
    _036_ = _172_;
    _060_ = _173_;
    _063_ = _174_;
    _069_ = _175_;
    _072_ = _176_;
    (* src = "libresoc.v:174348.5-174348.29" *)
    casez (\initial )
      /* src = "libresoc.v:174348.9-174348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _112_ = _147_;
          _113_ = _148_;
          _114_ = _149_;
          _115_ = _150_;
          _116_ = _151_;
          _117_ = _152_;
          _118_ = _153_;
          _119_ = _154_;
          _120_ = _155_;
          _121_ = _156_;
          _122_ = _157_;
          _123_ = _158_;
          _124_ = _159_;
          _125_ = _160_;
          _126_ = _161_;
          _127_ = _162_;
          _128_ = _163_;
          _129_ = _164_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                { _152_, _147_, _157_, _156_, _160_, _163_, _155_, _151_, _164_, _154_, _159_, _158_, _161_, _162_, _150_, _149_, _148_, _153_ } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
              end
            default:
              begin
                _147_ = \logical_op__data_len$45 ;
                _148_ = \logical_op__fn_unit$30 ;
                _149_ = \logical_op__imm_data__data$31 ;
                _150_ = \logical_op__imm_data__ok$32 ;
                _151_ = \logical_op__input_carry$39 ;
                _152_ = \logical_op__insn$46 ;
                _153_ = \logical_op__insn_type$29 ;
                _154_ = \logical_op__invert_in$37 ;
                _155_ = \logical_op__invert_out$40 ;
                _156_ = \logical_op__is_32bit$43 ;
                _157_ = \logical_op__is_signed$44 ;
                _158_ = \logical_op__oe__oe$35 ;
                _159_ = \logical_op__oe__ok$36 ;
                _160_ = \logical_op__output_carry$42 ;
                _161_ = \logical_op__rc__ok$34 ;
                _162_ = \logical_op__rc__rc$33 ;
                _163_ = \logical_op__write_cr0$41 ;
                _164_ = \logical_op__zero_a$38 ;
              end
          endcase
        end
      default:
        begin
          _112_ = \logical_op__data_len$45 ;
          _113_ = \logical_op__fn_unit$30 ;
          _114_ = \logical_op__imm_data__data$31 ;
          _115_ = \logical_op__imm_data__ok$32 ;
          _116_ = \logical_op__input_carry$39 ;
          _117_ = \logical_op__insn$46 ;
          _118_ = \logical_op__insn_type$29 ;
          _119_ = \logical_op__invert_in$37 ;
          _120_ = \logical_op__invert_out$40 ;
          _121_ = \logical_op__is_32bit$43 ;
          _122_ = \logical_op__is_signed$44 ;
          _123_ = \logical_op__oe__oe$35 ;
          _124_ = \logical_op__oe__ok$36 ;
          _125_ = \logical_op__output_carry$42 ;
          _126_ = \logical_op__rc__ok$34 ;
          _127_ = \logical_op__rc__rc$33 ;
          _128_ = \logical_op__write_cr0$41 ;
          _129_ = \logical_op__zero_a$38 ;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 64'h0000000000000000;
          _172_ = 1'h0;
          _176_ = 1'h0;
          _175_ = 1'h0;
          _173_ = 1'h0;
          _174_ = 1'h0;
        end
      default:
        begin
          _171_ = _114_;
          _172_ = _115_;
          _173_ = _123_;
          _174_ = _124_;
          _175_ = _126_;
          _176_ = _127_;
        end
    endcase
  end
  always @* begin
      \logical_op__data_len$45$next  <= _027_;
      \logical_op__fn_unit$30$next  <= _030_;
      \logical_op__imm_data__data$31$next  <= _033_;
      \logical_op__imm_data__ok$32$next  <= _036_;
      \logical_op__input_carry$39$next  <= _039_;
      \logical_op__insn$46$next  <= _042_;
      \logical_op__insn_type$29$next  <= _045_;
      \logical_op__invert_in$37$next  <= _048_;
      \logical_op__invert_out$40$next  <= _051_;
      \logical_op__is_32bit$43$next  <= _054_;
      \logical_op__is_signed$44$next  <= _057_;
      \logical_op__oe__oe$35$next  <= _060_;
      \logical_op__oe__ok$36$next  <= _063_;
      \logical_op__output_carry$42$next  <= _066_;
      \logical_op__rc__ok$34$next  <= _069_;
      \logical_op__rc__rc$33$next  <= _072_;
      \logical_op__write_cr0$41$next  <= _075_;
      \logical_op__zero_a$38$next  <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = _132_;
    (* src = "libresoc.v:174392.5-174392.29" *)
    casez (\initial )
      /* src = "libresoc.v:174392.9-174392.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = _167_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _167_ = ra;
              end
            default:
                _167_ = \ra$47 ;
          endcase
        end
      default:
          _132_ = \ra$47 ;
    endcase
  end
  always @* begin
      \ra$47$next  <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = _133_;
    (* src = "libresoc.v:174407.5-174407.29" *)
    casez (\initial )
      /* src = "libresoc.v:174407.9-174407.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _133_ = _168_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _168_ = rb;
              end
            default:
                _168_ = \rb$48 ;
          endcase
        end
      default:
          _133_ = \rb$48 ;
    endcase
  end
  always @* begin
      \rb$48$next  <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = _138_;
    (* src = "libresoc.v:174422.5-174422.29" *)
    casez (\initial )
      /* src = "libresoc.v:174422.9-174422.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _138_ = _169_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _169_ = xer_so;
              end
            default:
                _169_ = \xer_so$49 ;
          endcase
        end
      default:
          _138_ = \xer_so$49 ;
    endcase
  end
  always @* begin
      \xer_so$49$next  <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _108_;
    (* src = "libresoc.v:174437.5-174437.29" *)
    casez (\initial )
      /* src = "libresoc.v:174437.9-174437.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _108_ = _144_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _144_ = divisor_neg;
              end
            default:
                _144_ = \divisor_neg$50 ;
          endcase
        end
      default:
          _108_ = \divisor_neg$50 ;
    endcase
  end
  always @* begin
      \divisor_neg$50$next  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _107_;
    (* src = "libresoc.v:174452.5-174452.29" *)
    casez (\initial )
      /* src = "libresoc.v:174452.9-174452.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _107_ = _143_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _143_ = dividend_neg;
              end
            default:
                _143_ = \dividend_neg$51 ;
          endcase
        end
      default:
          _107_ = \dividend_neg$51 ;
    endcase
  end
  always @* begin
      \dividend_neg$51$next  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _104_;
    (* src = "libresoc.v:174467.5-174467.29" *)
    casez (\initial )
      /* src = "libresoc.v:174467.9-174467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = _140_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _140_ = dive_abs_ov32;
              end
            default:
                _140_ = \dive_abs_ov32$52 ;
          endcase
        end
      default:
          _104_ = \dive_abs_ov32$52 ;
    endcase
  end
  always @* begin
      \dive_abs_ov32$52$next  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _105_;
    (* src = "libresoc.v:174482.5-174482.29" *)
    casez (\initial )
      /* src = "libresoc.v:174482.9-174482.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = _141_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _141_ = dive_abs_ov64;
              end
            default:
                _141_ = \dive_abs_ov64$53 ;
          endcase
        end
      default:
          _105_ = \dive_abs_ov64$53 ;
    endcase
  end
  always @* begin
      \dive_abs_ov64$53$next  <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _100_;
    (* src = "libresoc.v:174497.5-174497.29" *)
    casez (\initial )
      /* src = "libresoc.v:174497.9-174497.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _100_ = _139_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _139_ = div_by_zero;
              end
            default:
                _139_ = \div_by_zero$54 ;
          endcase
        end
      default:
          _100_ = \div_by_zero$54 ;
    endcase
  end
  always @* begin
      \div_by_zero$54$next  <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _106_;
    (* src = "libresoc.v:174512.5-174512.29" *)
    casez (\initial )
      /* src = "libresoc.v:174512.9-174512.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _106_ = _142_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _142_ = dividend;
              end
            default:
                _142_ = \dividend$68 ;
          endcase
        end
      default:
          _106_ = \dividend$68 ;
    endcase
  end
  always @* begin
      \dividend$68$next  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _109_;
    (* src = "libresoc.v:174527.5-174527.29" *)
    casez (\initial )
      /* src = "libresoc.v:174527.9-174527.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _109_ = _145_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _145_ = divisor_radicand;
              end
            default:
                _145_ = \divisor_radicand$65 ;
          endcase
        end
      default:
          _109_ = \divisor_radicand$65 ;
    endcase
  end
  always @* begin
      \divisor_radicand$65$next  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = _131_;
    (* src = "libresoc.v:174542.5-174542.29" *)
    casez (\initial )
      /* src = "libresoc.v:174542.9-174542.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175" *)
    casez (empty)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = _166_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" *)
          casez (p_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _166_ = operation;
              end
            default:
                _166_ = \operation$69 ;
          endcase
        end
      default:
          _131_ = \operation$69 ;
    endcase
  end
  always @* begin
      \operation$69$next  <= _084_;
  end
  assign \$56  = _184_;
  assign \$55  = _183_;
  assign \$59  = _182_;
  assign \$61  = _181_;
  assign \$63  = _178_;
  assign \$66  = _179_;
  assign p_ready_o = empty;
  assign n_valid_o = \$63 ;
  assign remainder = \$55 ;
  assign quotient_root = div_state_next_o_dividend_quotient[63:0];
  assign \div_by_zero$27  = \div_by_zero$54 ;
  assign \dive_abs_ov64$26  = \dive_abs_ov64$53 ;
  assign \dive_abs_ov32$25  = \dive_abs_ov32$52 ;
  assign \dividend_neg$24  = \dividend_neg$51 ;
  assign \divisor_neg$23  = \divisor_neg$50 ;
  assign \xer_so$22  = \xer_so$49 ;
  assign \rb$21  = \rb$48 ;
  assign \ra$20  = \ra$47 ;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { \logical_op__insn$46 , \logical_op__data_len$45 , \logical_op__is_signed$44 , \logical_op__is_32bit$43 , \logical_op__output_carry$42 , \logical_op__write_cr0$41 , \logical_op__invert_out$40 , \logical_op__input_carry$39 , \logical_op__zero_a$38 , \logical_op__invert_in$37 , \logical_op__oe__ok$36 , \logical_op__oe__oe$35 , \logical_op__rc__ok$34 , \logical_op__rc__rc$33 , \logical_op__imm_data__ok$32 , \logical_op__imm_data__data$31 , \logical_op__fn_unit$30 , \logical_op__insn_type$29  };
  assign \muxid$1  = \muxid$28 ;
  assign div_state_init_dividend = dividend;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:174575.1-176120.10" *)
module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, p_valid_i, p_ready_o, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \ra$20 , \rb$21 , \xer_so$22 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:175926.3-175938.6" *)
  reg _000_;
  (* src = "libresoc.v:175712.3-175713.39" *)
  reg _001_;
  (* src = "libresoc.v:175900.3-175912.6" *)
  reg _002_;
  (* src = "libresoc.v:175716.3-175717.43" *)
  reg _003_;
  (* src = "libresoc.v:175913.3-175925.6" *)
  reg _004_;
  (* src = "libresoc.v:175714.3-175715.43" *)
  reg _005_;
  (* src = "libresoc.v:175939.3-175951.6" *)
  reg [127:0] _006_;
  (* src = "libresoc.v:175710.3-175711.33" *)
  reg [127:0] _007_;
  (* src = "libresoc.v:175887.3-175899.6" *)
  reg _008_;
  (* src = "libresoc.v:175718.3-175719.41" *)
  reg _009_;
  (* src = "libresoc.v:175874.3-175886.6" *)
  reg _010_;
  (* src = "libresoc.v:175720.3-175721.39" *)
  reg _011_;
  (* src = "libresoc.v:175952.3-175964.6" *)
  reg [63:0] _012_;
  (* src = "libresoc.v:175708.3-175709.49" *)
  reg [63:0] _013_;
  (* src = "libresoc.v:174576.7-174576.20" *)
  reg _014_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [3:0] _015_;
  (* src = "libresoc.v:175760.3-175761.57" *)
  reg [3:0] _016_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [13:0] _017_;
  (* src = "libresoc.v:175730.3-175731.55" *)
  reg [13:0] _018_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [63:0] _019_;
  (* src = "libresoc.v:175732.3-175733.69" *)
  reg [63:0] _020_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _021_;
  (* src = "libresoc.v:175734.3-175735.65" *)
  reg _022_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [1:0] _023_;
  (* src = "libresoc.v:175748.3-175749.63" *)
  reg [1:0] _024_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [31:0] _025_;
  (* src = "libresoc.v:175762.3-175763.49" *)
  reg [31:0] _026_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [6:0] _027_;
  (* src = "libresoc.v:175728.3-175729.59" *)
  reg [6:0] _028_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _029_;
  (* src = "libresoc.v:175744.3-175745.59" *)
  reg _030_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _031_;
  (* src = "libresoc.v:175750.3-175751.61" *)
  reg _032_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _033_;
  (* src = "libresoc.v:175756.3-175757.57" *)
  reg _034_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _035_;
  (* src = "libresoc.v:175758.3-175759.59" *)
  reg _036_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _037_;
  (* src = "libresoc.v:175740.3-175741.53" *)
  reg _038_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _039_;
  (* src = "libresoc.v:175742.3-175743.53" *)
  reg _040_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _041_;
  (* src = "libresoc.v:175754.3-175755.65" *)
  reg _042_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _043_;
  (* src = "libresoc.v:175738.3-175739.53" *)
  reg _044_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _045_;
  (* src = "libresoc.v:175736.3-175737.53" *)
  reg _046_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _047_;
  (* src = "libresoc.v:175752.3-175753.59" *)
  reg _048_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _049_;
  (* src = "libresoc.v:175746.3-175747.53" *)
  reg _050_;
  (* src = "libresoc.v:175996.3-176008.6" *)
  reg [1:0] _051_;
  (* src = "libresoc.v:175764.3-175765.27" *)
  reg [1:0] _052_;
  (* src = "libresoc.v:175965.3-175977.6" *)
  reg [1:0] _053_;
  (* src = "libresoc.v:175706.3-175707.35" *)
  reg [1:0] _054_;
  (* src = "libresoc.v:175978.3-175995.6" *)
  reg _055_;
  (* src = "libresoc.v:175766.3-175767.29" *)
  reg _056_;
  (* src = "libresoc.v:176051.3-176063.6" *)
  reg [63:0] _057_;
  (* src = "libresoc.v:175726.3-175727.21" *)
  reg [63:0] _058_;
  (* src = "libresoc.v:176064.3-176076.6" *)
  reg [63:0] _059_;
  (* src = "libresoc.v:175724.3-175725.21" *)
  reg [63:0] _060_;
  (* src = "libresoc.v:176077.3-176089.6" *)
  reg _061_;
  (* src = "libresoc.v:175722.3-175723.29" *)
  reg _062_;
  (* src = "libresoc.v:175926.3-175938.6" *)
  reg _063_;
  (* src = "libresoc.v:174585.7-174585.25" *)
  reg _064_;
  (* src = "libresoc.v:175900.3-175912.6" *)
  reg _065_;
  (* src = "libresoc.v:174592.7-174592.27" *)
  reg _066_;
  (* src = "libresoc.v:175913.3-175925.6" *)
  reg _067_;
  (* src = "libresoc.v:174599.7-174599.27" *)
  reg _068_;
  (* src = "libresoc.v:175939.3-175951.6" *)
  reg [127:0] _069_;
  (* src = "libresoc.v:174606.15-174606.63" *)
  reg [127:0] _070_;
  (* src = "libresoc.v:175887.3-175899.6" *)
  reg _071_;
  (* src = "libresoc.v:174613.7-174613.26" *)
  reg _072_;
  (* src = "libresoc.v:175874.3-175886.6" *)
  reg _073_;
  (* src = "libresoc.v:174620.7-174620.25" *)
  reg _074_;
  (* src = "libresoc.v:175952.3-175964.6" *)
  reg [63:0] _075_;
  (* src = "libresoc.v:174627.14-174627.53" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [3:0] _077_;
  (* src = "libresoc.v:174910.13-174910.40" *)
  reg [3:0] _078_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [13:0] _079_;
  (* src = "libresoc.v:174934.14-174934.44" *)
  reg [13:0] _080_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [63:0] _081_;
  (* src = "libresoc.v:174973.14-174973.63" *)
  reg [63:0] _082_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _083_;
  (* src = "libresoc.v:174982.7-174982.38" *)
  reg _084_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [1:0] _085_;
  (* src = "libresoc.v:174995.13-174995.43" *)
  reg [1:0] _086_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [31:0] _087_;
  (* src = "libresoc.v:175012.14-175012.38" *)
  reg [31:0] _088_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [6:0] _089_;
  (* src = "libresoc.v:175096.13-175096.42" *)
  reg [6:0] _090_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _091_;
  (* src = "libresoc.v:175255.7-175255.35" *)
  reg _092_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _093_;
  (* src = "libresoc.v:175264.7-175264.36" *)
  reg _094_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _095_;
  (* src = "libresoc.v:175273.7-175273.34" *)
  reg _096_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _097_;
  (* src = "libresoc.v:175282.7-175282.35" *)
  reg _098_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _099_;
  (* src = "libresoc.v:175291.7-175291.32" *)
  reg _100_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _101_;
  (* src = "libresoc.v:175300.7-175300.32" *)
  reg _102_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _103_;
  (* src = "libresoc.v:175309.7-175309.38" *)
  reg _104_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _105_;
  (* src = "libresoc.v:175318.7-175318.32" *)
  reg _106_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _107_;
  (* src = "libresoc.v:175327.7-175327.32" *)
  reg _108_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _109_;
  (* src = "libresoc.v:175336.7-175336.35" *)
  reg _110_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _111_;
  (* src = "libresoc.v:175345.7-175345.32" *)
  reg _112_;
  (* src = "libresoc.v:175996.3-176008.6" *)
  reg [1:0] _113_;
  (* src = "libresoc.v:175354.13-175354.25" *)
  reg [1:0] _114_;
  (* src = "libresoc.v:175965.3-175977.6" *)
  reg [1:0] _115_;
  (* src = "libresoc.v:175369.13-175369.29" *)
  reg [1:0] _116_;
  (* src = "libresoc.v:175978.3-175995.6" *)
  reg _117_;
  (* src = "libresoc.v:175383.7-175383.20" *)
  reg _118_;
  (* src = "libresoc.v:176051.3-176063.6" *)
  reg [63:0] _119_;
  (* src = "libresoc.v:175388.14-175388.39" *)
  reg [63:0] _120_;
  (* src = "libresoc.v:176064.3-176076.6" *)
  reg [63:0] _121_;
  (* src = "libresoc.v:175399.14-175399.39" *)
  reg [63:0] _122_;
  (* src = "libresoc.v:176077.3-176089.6" *)
  reg _123_;
  (* src = "libresoc.v:175698.7-175698.20" *)
  reg _124_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg [63:0] _125_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _126_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _127_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _128_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _129_;
  (* src = "libresoc.v:176009.3-176050.6" *)
  reg _130_;
  (* src = "libresoc.v:175978.3-175995.6" *)
  reg _131_;
  (* src = "libresoc.v:175705.18-175705.118" *)
  wire _132_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *)
  wire \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  output div_by_zero;
  reg div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire \div_by_zero$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  reg \div_by_zero$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  output dive_abs_ov32;
  reg dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire \dive_abs_ov32$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  reg \dive_abs_ov32$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  output dive_abs_ov64;
  reg dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire \dive_abs_ov64$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  reg \dive_abs_ov64$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  output [127:0] dividend;
  reg [127:0] dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  wire [127:0] \dividend$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  reg [127:0] \dividend$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  output dividend_neg;
  reg dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire \dividend_neg$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  reg \dividend_neg$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  output divisor_neg;
  reg divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire \divisor_neg$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  reg \divisor_neg$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  output [63:0] divisor_radicand;
  reg [63:0] divisor_radicand;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  wire [63:0] \divisor_radicand$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  reg [63:0] \divisor_radicand$next ;
  (* src = "libresoc.v:174576.7-174576.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] input_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \input_logical_op__data_len$40 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] input_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \input_logical_op__fn_unit$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] input_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \input_logical_op__imm_data__data$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__imm_data__ok$27 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] input_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \input_logical_op__input_carry$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] input_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \input_logical_op__insn$41 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] input_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \input_logical_op__insn_type$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__invert_in$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__invert_out$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__is_32bit$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__is_signed$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__oe__oe$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__oe__ok$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__output_carry$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__rc__ok$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__rc__rc$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__write_cr0$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire input_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \input_logical_op__zero_a$33 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] input_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \input_muxid$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_ra$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] input_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \input_rb$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire input_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \input_xer_so$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] logical_op__data_len;
  reg [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] \logical_op__data_len$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \logical_op__data_len$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [3:0] \logical_op__data_len$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] logical_op__fn_unit;
  reg [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] \logical_op__fn_unit$3 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \logical_op__fn_unit$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \logical_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] logical_op__imm_data__data;
  reg [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \logical_op__imm_data__data$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \logical_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__imm_data__ok;
  reg logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__imm_data__ok$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__imm_data__ok$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] logical_op__input_carry;
  reg [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] \logical_op__input_carry$12 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \logical_op__input_carry$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \logical_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] logical_op__insn;
  reg [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] \logical_op__insn$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \logical_op__insn$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \logical_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] logical_op__insn_type;
  reg [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] \logical_op__insn_type$2 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \logical_op__insn_type$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \logical_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__invert_in;
  reg logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_in$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__invert_out;
  reg logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__invert_out$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__invert_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__is_32bit;
  reg logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_32bit$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__is_signed;
  reg logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__is_signed$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__oe__oe;
  reg logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__oe$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__oe__ok;
  reg logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__oe__ok$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__output_carry;
  reg logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__output_carry$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__rc__ok;
  reg logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__ok$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__rc__rc;
  reg logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__rc__rc$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__write_cr0;
  reg logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__write_cr0$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output logical_op__zero_a;
  reg logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \logical_op__zero_a$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \logical_op__zero_a$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] muxid;
  reg [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \muxid$68 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  reg [1:0] \muxid$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" *)
  wire n_i_rdy_data;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  input n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  output n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  output [1:0] operation;
  reg [1:0] operation;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  wire [1:0] \operation$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  reg [1:0] \operation$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  output p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  input p_valid_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:626" *)
  wire \p_valid_i$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:625" *)
  wire p_valid_i_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg r_busy;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" *)
  reg \r_busy$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] ra;
  reg [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \ra$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \ra$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \ra$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \ra$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output [63:0] rb;
  reg [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] \rb$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \rb$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \rb$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg [63:0] \rb$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  wire setup_stage_div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  wire setup_stage_dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  wire setup_stage_dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  wire [127:0] setup_stage_dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  wire setup_stage_dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  wire setup_stage_divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  wire [63:0] setup_stage_divisor_radicand;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] setup_stage_logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [3:0] \setup_stage_logical_op__data_len$62 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] setup_stage_logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [13:0] \setup_stage_logical_op__fn_unit$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] setup_stage_logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [63:0] \setup_stage_logical_op__imm_data__data$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__imm_data__ok$49 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] setup_stage_logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [1:0] \setup_stage_logical_op__input_carry$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] setup_stage_logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [31:0] \setup_stage_logical_op__insn$63 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] setup_stage_logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire [6:0] \setup_stage_logical_op__insn_type$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__invert_in$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__invert_out$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__is_32bit$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__is_signed$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__oe__oe$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__oe__ok$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__output_carry$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__rc__ok$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__rc__rc$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__write_cr0$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire setup_stage_logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  wire \setup_stage_logical_op__zero_a$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] setup_stage_muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  wire [1:0] \setup_stage_muxid$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  wire [1:0] setup_stage_operation;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] setup_stage_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] setup_stage_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire setup_stage_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \setup_stage_xer_so$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output xer_so;
  reg xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input \xer_so$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \xer_so$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  reg \xer_so$next ;
  assign _132_ = \p_valid_i$65  & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) p_ready_o;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:175768.14-175813.4" *)
  \input$78  \input  (
    .logical_op__data_len(input_logical_op__data_len),
    .\logical_op__data_len$18 (\input_logical_op__data_len$40 ),
    .logical_op__fn_unit(input_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\input_logical_op__fn_unit$25 ),
    .logical_op__imm_data__data(input_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\input_logical_op__imm_data__data$26 ),
    .logical_op__imm_data__ok(input_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\input_logical_op__imm_data__ok$27 ),
    .logical_op__input_carry(input_logical_op__input_carry),
    .\logical_op__input_carry$12 (\input_logical_op__input_carry$34 ),
    .logical_op__insn(input_logical_op__insn),
    .\logical_op__insn$19 (\input_logical_op__insn$41 ),
    .logical_op__insn_type(input_logical_op__insn_type),
    .\logical_op__insn_type$2 (\input_logical_op__insn_type$24 ),
    .logical_op__invert_in(input_logical_op__invert_in),
    .\logical_op__invert_in$10 (\input_logical_op__invert_in$32 ),
    .logical_op__invert_out(input_logical_op__invert_out),
    .\logical_op__invert_out$13 (\input_logical_op__invert_out$35 ),
    .logical_op__is_32bit(input_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\input_logical_op__is_32bit$38 ),
    .logical_op__is_signed(input_logical_op__is_signed),
    .\logical_op__is_signed$17 (\input_logical_op__is_signed$39 ),
    .logical_op__oe__oe(input_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\input_logical_op__oe__oe$30 ),
    .logical_op__oe__ok(input_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\input_logical_op__oe__ok$31 ),
    .logical_op__output_carry(input_logical_op__output_carry),
    .\logical_op__output_carry$15 (\input_logical_op__output_carry$37 ),
    .logical_op__rc__ok(input_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\input_logical_op__rc__ok$29 ),
    .logical_op__rc__rc(input_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\input_logical_op__rc__rc$28 ),
    .logical_op__write_cr0(input_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\input_logical_op__write_cr0$36 ),
    .logical_op__zero_a(input_logical_op__zero_a),
    .\logical_op__zero_a$11 (\input_logical_op__zero_a$33 ),
    .muxid(input_muxid),
    .\muxid$1 (\input_muxid$23 ),
    .ra(input_ra),
    .\ra$20 (\input_ra$42 ),
    .rb(input_rb),
    .\rb$21 (\input_rb$43 ),
    .xer_so(input_xer_so),
    .\xer_so$22 (\input_xer_so$44 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:175814.10-175817.4" *)
  \n$77  n (
    .n_ready_i(n_ready_i),
    .n_valid_o(n_valid_o)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:175818.10-175821.4" *)
  \p$76  p (
    .p_ready_o(p_ready_o),
    .p_valid_i(p_valid_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:175822.15-175873.4" *)
  setup_stage setup_stage (
    .div_by_zero(setup_stage_div_by_zero),
    .dive_abs_ov32(setup_stage_dive_abs_ov32),
    .dive_abs_ov64(setup_stage_dive_abs_ov64),
    .dividend(setup_stage_dividend),
    .dividend_neg(setup_stage_dividend_neg),
    .divisor_neg(setup_stage_divisor_neg),
    .divisor_radicand(setup_stage_divisor_radicand),
    .logical_op__data_len(setup_stage_logical_op__data_len),
    .\logical_op__data_len$18 (\setup_stage_logical_op__data_len$62 ),
    .logical_op__fn_unit(setup_stage_logical_op__fn_unit),
    .\logical_op__fn_unit$3 (\setup_stage_logical_op__fn_unit$47 ),
    .logical_op__imm_data__data(setup_stage_logical_op__imm_data__data),
    .\logical_op__imm_data__data$4 (\setup_stage_logical_op__imm_data__data$48 ),
    .logical_op__imm_data__ok(setup_stage_logical_op__imm_data__ok),
    .\logical_op__imm_data__ok$5 (\setup_stage_logical_op__imm_data__ok$49 ),
    .logical_op__input_carry(setup_stage_logical_op__input_carry),
    .\logical_op__input_carry$12 (\setup_stage_logical_op__input_carry$56 ),
    .logical_op__insn(setup_stage_logical_op__insn),
    .\logical_op__insn$19 (\setup_stage_logical_op__insn$63 ),
    .logical_op__insn_type(setup_stage_logical_op__insn_type),
    .\logical_op__insn_type$2 (\setup_stage_logical_op__insn_type$46 ),
    .logical_op__invert_in(setup_stage_logical_op__invert_in),
    .\logical_op__invert_in$10 (\setup_stage_logical_op__invert_in$54 ),
    .logical_op__invert_out(setup_stage_logical_op__invert_out),
    .\logical_op__invert_out$13 (\setup_stage_logical_op__invert_out$57 ),
    .logical_op__is_32bit(setup_stage_logical_op__is_32bit),
    .\logical_op__is_32bit$16 (\setup_stage_logical_op__is_32bit$60 ),
    .logical_op__is_signed(setup_stage_logical_op__is_signed),
    .\logical_op__is_signed$17 (\setup_stage_logical_op__is_signed$61 ),
    .logical_op__oe__oe(setup_stage_logical_op__oe__oe),
    .\logical_op__oe__oe$8 (\setup_stage_logical_op__oe__oe$52 ),
    .logical_op__oe__ok(setup_stage_logical_op__oe__ok),
    .\logical_op__oe__ok$9 (\setup_stage_logical_op__oe__ok$53 ),
    .logical_op__output_carry(setup_stage_logical_op__output_carry),
    .\logical_op__output_carry$15 (\setup_stage_logical_op__output_carry$59 ),
    .logical_op__rc__ok(setup_stage_logical_op__rc__ok),
    .\logical_op__rc__ok$7 (\setup_stage_logical_op__rc__ok$51 ),
    .logical_op__rc__rc(setup_stage_logical_op__rc__rc),
    .\logical_op__rc__rc$6 (\setup_stage_logical_op__rc__rc$50 ),
    .logical_op__write_cr0(setup_stage_logical_op__write_cr0),
    .\logical_op__write_cr0$14 (\setup_stage_logical_op__write_cr0$58 ),
    .logical_op__zero_a(setup_stage_logical_op__zero_a),
    .\logical_op__zero_a$11 (\setup_stage_logical_op__zero_a$55 ),
    .muxid(setup_stage_muxid),
    .\muxid$1 (\setup_stage_muxid$45 ),
    .operation(setup_stage_operation),
    .ra(setup_stage_ra),
    .rb(setup_stage_rb),
    .xer_so(setup_stage_xer_so),
    .\xer_so$20 (\setup_stage_xer_so$64 )
  );
  always @* begin
    if (\initial ) begin end
    _014_ = 1'h0;
  end
  always @* begin
      \initial  <= _014_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _064_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      div_by_zero <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dive_abs_ov32 <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dive_abs_ov64 <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = 128'h00000000000000000000000000000000;
  end
  always @* begin
  end
  initial begin
      dividend <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dividend_neg <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      divisor_neg <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      divisor_radicand <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__data_len <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      logical_op__fn_unit <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      logical_op__imm_data__data <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__imm_data__ok <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__input_carry <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      logical_op__insn <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      logical_op__insn_type <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__invert_in <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__invert_out <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__is_32bit <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__is_signed <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__oe__oe <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__oe__ok <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__output_carry <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__rc__ok <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__rc__rc <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__write_cr0 <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      logical_op__zero_a <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      muxid <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      operation <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      r_busy <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      ra <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      rb <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      xer_so <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \operation$next ;
  end
  always @(posedge coresync_clk) begin
      operation <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \divisor_radicand$next ;
  end
  always @(posedge coresync_clk) begin
      divisor_radicand <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \dividend$next ;
  end
  always @(posedge coresync_clk) begin
      dividend <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \div_by_zero$next ;
  end
  always @(posedge coresync_clk) begin
      div_by_zero <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \dive_abs_ov64$next ;
  end
  always @(posedge coresync_clk) begin
      dive_abs_ov64 <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \dive_abs_ov32$next ;
  end
  always @(posedge coresync_clk) begin
      dive_abs_ov32 <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \dividend_neg$next ;
  end
  always @(posedge coresync_clk) begin
      dividend_neg <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \divisor_neg$next ;
  end
  always @(posedge coresync_clk) begin
      divisor_neg <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      xer_so <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \rb$next ;
  end
  always @(posedge coresync_clk) begin
      rb <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \ra$next ;
  end
  always @(posedge coresync_clk) begin
      ra <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = \logical_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__insn_type <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \logical_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__fn_unit <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = \logical_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__imm_data__data <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = \logical_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__imm_data__ok <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \logical_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__rc__rc <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \logical_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__rc__ok <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = \logical_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__oe__oe <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = \logical_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__oe__ok <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \logical_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__invert_in <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \logical_op__zero_a$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__zero_a <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \logical_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__input_carry <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = \logical_op__invert_out$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__invert_out <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \logical_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__write_cr0 <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \logical_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__output_carry <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \logical_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__is_32bit <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \logical_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__is_signed <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = \logical_op__data_len$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__data_len <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = \logical_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      logical_op__insn <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \muxid$next ;
  end
  always @(posedge coresync_clk) begin
      muxid <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \r_busy$next ;
  end
  always @(posedge coresync_clk) begin
      r_busy <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _073_;
    (* src = "libresoc.v:175875.5-175875.29" *)
    casez (\initial )
      /* src = "libresoc.v:175875.9-175875.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _073_ = \divisor_neg$92 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _073_ = \divisor_neg$92 ;
        end
      default:
          _073_ = divisor_neg;
    endcase
  end
  always @* begin
      \divisor_neg$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _071_;
    (* src = "libresoc.v:175888.5-175888.29" *)
    casez (\initial )
      /* src = "libresoc.v:175888.9-175888.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _071_ = \dividend_neg$93 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _071_ = \dividend_neg$93 ;
        end
      default:
          _071_ = dividend_neg;
    endcase
  end
  always @* begin
      \dividend_neg$next  <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _065_;
    (* src = "libresoc.v:175901.5-175901.29" *)
    casez (\initial )
      /* src = "libresoc.v:175901.9-175901.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _065_ = \dive_abs_ov32$94 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _065_ = \dive_abs_ov32$94 ;
        end
      default:
          _065_ = dive_abs_ov32;
    endcase
  end
  always @* begin
      \dive_abs_ov32$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _067_;
    (* src = "libresoc.v:175914.5-175914.29" *)
    casez (\initial )
      /* src = "libresoc.v:175914.9-175914.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _067_ = \dive_abs_ov64$95 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _067_ = \dive_abs_ov64$95 ;
        end
      default:
          _067_ = dive_abs_ov64;
    endcase
  end
  always @* begin
      \dive_abs_ov64$next  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _063_;
    (* src = "libresoc.v:175927.5-175927.29" *)
    casez (\initial )
      /* src = "libresoc.v:175927.9-175927.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _063_ = \div_by_zero$96 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _063_ = \div_by_zero$96 ;
        end
      default:
          _063_ = div_by_zero;
    endcase
  end
  always @* begin
      \div_by_zero$next  <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _069_;
    (* src = "libresoc.v:175940.5-175940.29" *)
    casez (\initial )
      /* src = "libresoc.v:175940.9-175940.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _069_ = \dividend$97 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _069_ = \dividend$97 ;
        end
      default:
          _069_ = dividend;
    endcase
  end
  always @* begin
      \dividend$next  <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _075_;
    (* src = "libresoc.v:175953.5-175953.29" *)
    casez (\initial )
      /* src = "libresoc.v:175953.9-175953.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _075_ = \divisor_radicand$98 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _075_ = \divisor_radicand$98 ;
        end
      default:
          _075_ = divisor_radicand;
    endcase
  end
  always @* begin
      \divisor_radicand$next  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _115_;
    (* src = "libresoc.v:175966.5-175966.29" *)
    casez (\initial )
      /* src = "libresoc.v:175966.9-175966.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _115_ = \operation$99 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _115_ = \operation$99 ;
        end
      default:
          _115_ = operation;
    endcase
  end
  always @* begin
      \operation$next  <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = _131_;
    (* src = "libresoc.v:175979.5-175979.29" *)
    casez (\initial )
      /* src = "libresoc.v:175979.9-175979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _117_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _117_ = 1'h0;
        end
      default:
          _117_ = r_busy;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = 1'h0;
        end
      default:
          _131_ = _117_;
    endcase
  end
  always @* begin
      \r_busy$next  <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _113_;
    (* src = "libresoc.v:175997.5-175997.29" *)
    casez (\initial )
      /* src = "libresoc.v:175997.9-175997.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _113_ = \muxid$68 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _113_ = \muxid$68 ;
        end
      default:
          _113_ = muxid;
    endcase
  end
  always @* begin
      \muxid$next  <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _077_;
    _017_ = _079_;
    _023_ = _085_;
    _025_ = _087_;
    _027_ = _089_;
    _029_ = _091_;
    _031_ = _093_;
    _033_ = _095_;
    _035_ = _097_;
    _041_ = _103_;
    _047_ = _109_;
    _049_ = _111_;
    _019_ = _125_;
    _021_ = _126_;
    _037_ = _127_;
    _039_ = _128_;
    _043_ = _129_;
    _045_ = _130_;
    (* src = "libresoc.v:176010.5-176010.29" *)
    casez (\initial )
      /* src = "libresoc.v:176010.9-176010.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          { _087_, _077_, _097_, _095_, _103_, _109_, _093_, _085_, _111_, _091_, _101_, _099_, _105_, _107_, _083_, _081_, _079_, _089_ } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          { _087_, _077_, _097_, _095_, _103_, _109_, _093_, _085_, _111_, _091_, _101_, _099_, _105_, _107_, _083_, _081_, _079_, _089_ } = { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69  };
        end
      default:
        begin
          _077_ = logical_op__data_len;
          _079_ = logical_op__fn_unit;
          _081_ = logical_op__imm_data__data;
          _083_ = logical_op__imm_data__ok;
          _085_ = logical_op__input_carry;
          _087_ = logical_op__insn;
          _089_ = logical_op__insn_type;
          _091_ = logical_op__invert_in;
          _093_ = logical_op__invert_out;
          _095_ = logical_op__is_32bit;
          _097_ = logical_op__is_signed;
          _099_ = logical_op__oe__oe;
          _101_ = logical_op__oe__ok;
          _103_ = logical_op__output_carry;
          _105_ = logical_op__rc__ok;
          _107_ = logical_op__rc__rc;
          _109_ = logical_op__write_cr0;
          _111_ = logical_op__zero_a;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _125_ = 64'h0000000000000000;
          _126_ = 1'h0;
          _130_ = 1'h0;
          _129_ = 1'h0;
          _127_ = 1'h0;
          _128_ = 1'h0;
        end
      default:
        begin
          _125_ = _081_;
          _126_ = _083_;
          _127_ = _099_;
          _128_ = _101_;
          _129_ = _105_;
          _130_ = _107_;
        end
    endcase
  end
  always @* begin
      \logical_op__data_len$next  <= _015_;
      \logical_op__fn_unit$next  <= _017_;
      \logical_op__imm_data__data$next  <= _019_;
      \logical_op__imm_data__ok$next  <= _021_;
      \logical_op__input_carry$next  <= _023_;
      \logical_op__insn$next  <= _025_;
      \logical_op__insn_type$next  <= _027_;
      \logical_op__invert_in$next  <= _029_;
      \logical_op__invert_out$next  <= _031_;
      \logical_op__is_32bit$next  <= _033_;
      \logical_op__is_signed$next  <= _035_;
      \logical_op__oe__oe$next  <= _037_;
      \logical_op__oe__ok$next  <= _039_;
      \logical_op__output_carry$next  <= _041_;
      \logical_op__rc__ok$next  <= _043_;
      \logical_op__rc__rc$next  <= _045_;
      \logical_op__write_cr0$next  <= _047_;
      \logical_op__zero_a$next  <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _119_;
    (* src = "libresoc.v:176052.5-176052.29" *)
    casez (\initial )
      /* src = "libresoc.v:176052.9-176052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _119_ = \ra$87 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _119_ = \ra$87 ;
        end
      default:
          _119_ = ra;
    endcase
  end
  always @* begin
      \ra$next  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _121_;
    (* src = "libresoc.v:176065.5-176065.29" *)
    casez (\initial )
      /* src = "libresoc.v:176065.9-176065.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _121_ = \rb$89 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _121_ = \rb$89 ;
        end
      default:
          _121_ = rb;
    endcase
  end
  always @* begin
      \rb$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _123_;
    (* src = "libresoc.v:176078.5-176078.29" *)
    casez (\initial )
      /* src = "libresoc.v:176078.9-176078.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:636" *)
    casez ({ n_i_rdy_data, p_valid_i_p_ready_o })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _123_ = \xer_so$91 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _123_ = \xer_so$91 ;
        end
      default:
          _123_ = xer_so;
    endcase
  end
  always @* begin
      \xer_so$next  <= _061_;
  end
  assign \$66  = _132_;
  assign \ra$88  = 64'h0000000000000000;
  assign \rb$90  = 64'h0000000000000000;
  assign p_ready_o = n_i_rdy_data;
  assign n_valid_o = r_busy;
  assign \operation$99  = setup_stage_operation;
  assign \divisor_radicand$98  = setup_stage_divisor_radicand;
  assign \dividend$97  = setup_stage_dividend;
  assign \div_by_zero$96  = setup_stage_div_by_zero;
  assign \dive_abs_ov64$95  = setup_stage_dive_abs_ov64;
  assign \dive_abs_ov32$94  = setup_stage_dive_abs_ov32;
  assign \dividend_neg$93  = setup_stage_dividend_neg;
  assign \divisor_neg$92  = setup_stage_divisor_neg;
  assign \xer_so$91  = \setup_stage_xer_so$64 ;
  assign \rb$89  = 64'h0000000000000000;
  assign \ra$87  = 64'h0000000000000000;
  assign { \logical_op__insn$86 , \logical_op__data_len$85 , \logical_op__is_signed$84 , \logical_op__is_32bit$83 , \logical_op__output_carry$82 , \logical_op__write_cr0$81 , \logical_op__invert_out$80 , \logical_op__input_carry$79 , \logical_op__zero_a$78 , \logical_op__invert_in$77 , \logical_op__oe__ok$76 , \logical_op__oe__oe$75 , \logical_op__rc__ok$74 , \logical_op__rc__rc$73 , \logical_op__imm_data__ok$72 , \logical_op__imm_data__data$71 , \logical_op__fn_unit$70 , \logical_op__insn_type$69  } = { \setup_stage_logical_op__insn$63 , \setup_stage_logical_op__data_len$62 , \setup_stage_logical_op__is_signed$61 , \setup_stage_logical_op__is_32bit$60 , \setup_stage_logical_op__output_carry$59 , \setup_stage_logical_op__write_cr0$58 , \setup_stage_logical_op__invert_out$57 , \setup_stage_logical_op__input_carry$56 , \setup_stage_logical_op__zero_a$55 , \setup_stage_logical_op__invert_in$54 , \setup_stage_logical_op__oe__ok$53 , \setup_stage_logical_op__oe__oe$52 , \setup_stage_logical_op__rc__ok$51 , \setup_stage_logical_op__rc__rc$50 , \setup_stage_logical_op__imm_data__ok$49 , \setup_stage_logical_op__imm_data__data$48 , \setup_stage_logical_op__fn_unit$47 , \setup_stage_logical_op__insn_type$46  };
  assign \muxid$68  = \setup_stage_muxid$45 ;
  assign p_valid_i_p_ready_o = \$66 ;
  assign n_i_rdy_data = n_ready_i;
  assign \p_valid_i$65  = p_valid_i;
  assign setup_stage_xer_so = \input_xer_so$44 ;
  assign setup_stage_rb = \input_rb$43 ;
  assign setup_stage_ra = \input_ra$42 ;
  assign { setup_stage_logical_op__insn, setup_stage_logical_op__data_len, setup_stage_logical_op__is_signed, setup_stage_logical_op__is_32bit, setup_stage_logical_op__output_carry, setup_stage_logical_op__write_cr0, setup_stage_logical_op__invert_out, setup_stage_logical_op__input_carry, setup_stage_logical_op__zero_a, setup_stage_logical_op__invert_in, setup_stage_logical_op__oe__ok, setup_stage_logical_op__oe__oe, setup_stage_logical_op__rc__ok, setup_stage_logical_op__rc__rc, setup_stage_logical_op__imm_data__ok, setup_stage_logical_op__imm_data__data, setup_stage_logical_op__fn_unit, setup_stage_logical_op__insn_type } = { \input_logical_op__insn$41 , \input_logical_op__data_len$40 , \input_logical_op__is_signed$39 , \input_logical_op__is_32bit$38 , \input_logical_op__output_carry$37 , \input_logical_op__write_cr0$36 , \input_logical_op__invert_out$35 , \input_logical_op__input_carry$34 , \input_logical_op__zero_a$33 , \input_logical_op__invert_in$32 , \input_logical_op__oe__ok$31 , \input_logical_op__oe__oe$30 , \input_logical_op__rc__ok$29 , \input_logical_op__rc__rc$28 , \input_logical_op__imm_data__ok$27 , \input_logical_op__imm_data__data$26 , \input_logical_op__fn_unit$25 , \input_logical_op__insn_type$24  };
  assign setup_stage_muxid = \input_muxid$23 ;
  assign input_xer_so = \xer_so$22 ;
  assign input_rb = \rb$21 ;
  assign input_ra = \ra$20 ;
  assign { input_logical_op__insn, input_logical_op__data_len, input_logical_op__is_signed, input_logical_op__is_32bit, input_logical_op__output_carry, input_logical_op__write_cr0, input_logical_op__invert_out, input_logical_op__input_carry, input_logical_op__zero_a, input_logical_op__invert_in, input_logical_op__oe__ok, input_logical_op__oe__oe, input_logical_op__rc__ok, input_logical_op__rc__rc, input_logical_op__imm_data__ok, input_logical_op__imm_data__data, input_logical_op__fn_unit, input_logical_op__insn_type } = { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  };
  assign input_muxid = \muxid$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:176124.1-176766.10" *)
module popcount(data_len, o, a);
  reg \initial  = 0;
  (* src = "libresoc.v:176125.7-176125.20" *)
  reg _000_;
  (* src = "libresoc.v:176613.3-176639.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:176613.3-176639.6" *)
  reg [63:0] _002_;
  (* src = "libresoc.v:176537.19-176537.132" *)
  wire [3:0] _003_;
  (* src = "libresoc.v:176538.19-176538.132" *)
  wire [3:0] _004_;
  (* src = "libresoc.v:176539.19-176539.132" *)
  wire [3:0] _005_;
  (* src = "libresoc.v:176540.19-176540.132" *)
  wire [3:0] _006_;
  (* src = "libresoc.v:176541.19-176541.134" *)
  wire [3:0] _007_;
  (* src = "libresoc.v:176542.19-176542.134" *)
  wire [3:0] _008_;
  (* src = "libresoc.v:176543.18-176543.125" *)
  wire [2:0] _009_;
  (* src = "libresoc.v:176544.19-176544.134" *)
  wire [3:0] _010_;
  (* src = "libresoc.v:176545.19-176545.134" *)
  wire [3:0] _011_;
  (* src = "libresoc.v:176546.19-176546.134" *)
  wire [3:0] _012_;
  (* src = "libresoc.v:176547.19-176547.134" *)
  wire [3:0] _013_;
  (* src = "libresoc.v:176548.19-176548.134" *)
  wire [3:0] _014_;
  (* src = "libresoc.v:176549.19-176549.134" *)
  wire [3:0] _015_;
  (* src = "libresoc.v:176550.19-176550.134" *)
  wire [3:0] _016_;
  (* src = "libresoc.v:176551.19-176551.134" *)
  wire [3:0] _017_;
  (* src = "libresoc.v:176552.19-176552.134" *)
  wire [3:0] _018_;
  (* src = "libresoc.v:176553.19-176553.132" *)
  wire [4:0] _019_;
  (* src = "libresoc.v:176554.18-176554.125" *)
  wire [2:0] _020_;
  (* src = "libresoc.v:176555.19-176555.132" *)
  wire [4:0] _021_;
  (* src = "libresoc.v:176556.19-176556.132" *)
  wire [4:0] _022_;
  (* src = "libresoc.v:176557.19-176557.132" *)
  wire [4:0] _023_;
  (* src = "libresoc.v:176558.19-176558.132" *)
  wire [4:0] _024_;
  (* src = "libresoc.v:176559.19-176559.134" *)
  wire [4:0] _025_;
  (* src = "libresoc.v:176560.19-176560.134" *)
  wire [4:0] _026_;
  (* src = "libresoc.v:176561.19-176561.134" *)
  wire [4:0] _027_;
  (* src = "libresoc.v:176562.19-176562.132" *)
  wire [5:0] _028_;
  (* src = "libresoc.v:176563.19-176563.132" *)
  wire [5:0] _029_;
  (* src = "libresoc.v:176564.19-176564.132" *)
  wire [5:0] _030_;
  (* src = "libresoc.v:176565.18-176565.127" *)
  wire [2:0] _031_;
  (* src = "libresoc.v:176566.19-176566.132" *)
  wire [5:0] _032_;
  (* src = "libresoc.v:176567.19-176567.132" *)
  wire [6:0] _033_;
  (* src = "libresoc.v:176568.19-176568.132" *)
  wire [6:0] _034_;
  (* src = "libresoc.v:176569.19-176569.132" *)
  wire [7:0] _035_;
  (* src = "libresoc.v:176580.18-176580.127" *)
  wire [2:0] _036_;
  (* src = "libresoc.v:176584.18-176584.127" *)
  wire [2:0] _037_;
  (* src = "libresoc.v:176585.18-176585.127" *)
  wire [2:0] _038_;
  (* src = "libresoc.v:176586.17-176586.124" *)
  wire [2:0] _039_;
  (* src = "libresoc.v:176587.18-176587.127" *)
  wire [2:0] _040_;
  (* src = "libresoc.v:176588.18-176588.127" *)
  wire [2:0] _041_;
  (* src = "libresoc.v:176589.18-176589.127" *)
  wire [2:0] _042_;
  (* src = "libresoc.v:176590.18-176590.127" *)
  wire [2:0] _043_;
  (* src = "libresoc.v:176591.18-176591.127" *)
  wire [2:0] _044_;
  (* src = "libresoc.v:176592.18-176592.127" *)
  wire [2:0] _045_;
  (* src = "libresoc.v:176593.18-176593.127" *)
  wire [2:0] _046_;
  (* src = "libresoc.v:176594.18-176594.127" *)
  wire [2:0] _047_;
  (* src = "libresoc.v:176595.18-176595.127" *)
  wire [2:0] _048_;
  (* src = "libresoc.v:176596.18-176596.127" *)
  wire [2:0] _049_;
  (* src = "libresoc.v:176597.17-176597.124" *)
  wire [2:0] _050_;
  (* src = "libresoc.v:176598.18-176598.127" *)
  wire [2:0] _051_;
  (* src = "libresoc.v:176599.18-176599.127" *)
  wire [2:0] _052_;
  (* src = "libresoc.v:176600.18-176600.127" *)
  wire [2:0] _053_;
  (* src = "libresoc.v:176601.18-176601.127" *)
  wire [2:0] _054_;
  (* src = "libresoc.v:176602.18-176602.127" *)
  wire [2:0] _055_;
  (* src = "libresoc.v:176603.18-176603.127" *)
  wire [2:0] _056_;
  (* src = "libresoc.v:176604.18-176604.127" *)
  wire [2:0] _057_;
  (* src = "libresoc.v:176605.18-176605.127" *)
  wire [2:0] _058_;
  (* src = "libresoc.v:176606.18-176606.127" *)
  wire [2:0] _059_;
  (* src = "libresoc.v:176607.18-176607.127" *)
  wire [2:0] _060_;
  (* src = "libresoc.v:176608.17-176608.124" *)
  wire [2:0] _061_;
  (* src = "libresoc.v:176609.18-176609.127" *)
  wire [2:0] _062_;
  (* src = "libresoc.v:176610.18-176610.127" *)
  wire [2:0] _063_;
  (* src = "libresoc.v:176611.18-176611.127" *)
  wire [2:0] _064_;
  (* src = "libresoc.v:176612.18-176612.131" *)
  wire [3:0] _065_;
  (* src = "libresoc.v:176570.19-176570.111" *)
  wire _066_;
  (* src = "libresoc.v:176571.19-176571.111" *)
  wire _067_;
  (* src = "libresoc.v:176572.19-176572.104" *)
  wire [7:0] _068_;
  (* src = "libresoc.v:176573.19-176573.104" *)
  wire [7:0] _069_;
  (* src = "libresoc.v:176574.19-176574.104" *)
  wire [7:0] _070_;
  (* src = "libresoc.v:176575.19-176575.104" *)
  wire [7:0] _071_;
  (* src = "libresoc.v:176576.19-176576.104" *)
  wire [7:0] _072_;
  (* src = "libresoc.v:176577.19-176577.104" *)
  wire [7:0] _073_;
  (* src = "libresoc.v:176578.19-176578.104" *)
  wire [7:0] _074_;
  (* src = "libresoc.v:176579.19-176579.104" *)
  wire [7:0] _075_;
  (* src = "libresoc.v:176581.19-176581.104" *)
  wire [31:0] _076_;
  (* src = "libresoc.v:176582.19-176582.104" *)
  wire [31:0] _077_;
  (* src = "libresoc.v:176583.19-176583.104" *)
  wire [63:0] _078_;
  (* src = "libresoc.v:176572.19-176572.104" *)
  wire [7:0] _079_;
  (* src = "libresoc.v:176573.19-176573.104" *)
  wire [7:0] _080_;
  (* src = "libresoc.v:176574.19-176574.104" *)
  wire [7:0] _081_;
  (* src = "libresoc.v:176575.19-176575.104" *)
  wire [7:0] _082_;
  (* src = "libresoc.v:176576.19-176576.104" *)
  wire [7:0] _083_;
  (* src = "libresoc.v:176577.19-176577.104" *)
  wire [7:0] _084_;
  (* src = "libresoc.v:176578.19-176578.104" *)
  wire [7:0] _085_;
  (* src = "libresoc.v:176579.19-176579.104" *)
  wire [7:0] _086_;
  (* src = "libresoc.v:176581.19-176581.104" *)
  wire [31:0] _087_;
  (* src = "libresoc.v:176582.19-176582.104" *)
  wire [31:0] _088_;
  (* src = "libresoc.v:176583.19-176583.104" *)
  wire [63:0] _089_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$140 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$142 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$146 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$148 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$155 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$157 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$158 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$160 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$161 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$163 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$164 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$166 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [4:0] \$167 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$169 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$170 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$172 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$173 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$175 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$176 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$178 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [5:0] \$179 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [6:0] \$181 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [6:0] \$182 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [6:0] \$184 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [6:0] \$185 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [7:0] \$187 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [7:0] \$188 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *)
  wire \$190 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" *)
  wire \$192 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$194 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$196 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$198 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$200 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$202 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$204 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$206 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [7:0] \$208 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [31:0] \$210 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [31:0] \$212 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [63:0] \$214 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [2:0] \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *)
  wire [3:0] \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" *)
  input [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" *)
  input [63:0] data_len;
  (* src = "libresoc.v:176125.7-176125.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_16;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_17;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_18;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_19;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_20;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_21;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_22;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_23;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_24;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_25;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_26;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_27;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_28;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_29;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_30;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_31;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [1:0] pop_2_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [2:0] pop_3_9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [3:0] pop_4_7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [4:0] pop_5_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [4:0] pop_5_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [4:0] pop_5_2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [4:0] pop_5_3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [5:0] pop_6_0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [5:0] pop_6_1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *)
  wire [6:0] pop_7_0;
  assign _003_ = { 2'h0, pop_2_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_3 };
  assign _004_ = { 2'h0, pop_2_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_5 };
  assign _005_ = { 2'h0, pop_2_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_7 };
  assign _006_ = { 2'h0, pop_2_8 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_9 };
  assign _007_ = { 2'h0, pop_2_10 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_11 };
  assign _008_ = { 2'h0, pop_2_12 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_13 };
  assign _009_ = { 2'h0, a[6] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[7] };
  assign _010_ = { 2'h0, pop_2_14 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_15 };
  assign _011_ = { 2'h0, pop_2_16 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_17 };
  assign _012_ = { 2'h0, pop_2_18 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_19 };
  assign _013_ = { 2'h0, pop_2_20 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_21 };
  assign _014_ = { 2'h0, pop_2_22 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_23 };
  assign _015_ = { 2'h0, pop_2_24 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_25 };
  assign _016_ = { 2'h0, pop_2_26 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_27 };
  assign _017_ = { 2'h0, pop_2_28 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_29 };
  assign _018_ = { 2'h0, pop_2_30 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_31 };
  assign _019_ = { 2'h0, pop_3_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_1 };
  assign _020_ = { 2'h0, a[8] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[9] };
  assign _021_ = { 2'h0, pop_3_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_3 };
  assign _022_ = { 2'h0, pop_3_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_5 };
  assign _023_ = { 2'h0, pop_3_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_7 };
  assign _024_ = { 2'h0, pop_3_8 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_9 };
  assign _025_ = { 2'h0, pop_3_10 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_11 };
  assign _026_ = { 2'h0, pop_3_12 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_13 };
  assign _027_ = { 2'h0, pop_3_14 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_3_15 };
  assign _028_ = { 2'h0, pop_4_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_4_1 };
  assign _029_ = { 2'h0, pop_4_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_4_3 };
  assign _030_ = { 2'h0, pop_4_4 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_4_5 };
  assign _031_ = { 2'h0, a[10] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[11] };
  assign _032_ = { 2'h0, pop_4_6 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_4_7 };
  assign _033_ = { 2'h0, pop_5_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_5_1 };
  assign _034_ = { 2'h0, pop_5_2 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_5_3 };
  assign _035_ = { 2'h0, pop_6_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_6_1 };
  assign _036_ = { 2'h0, a[12] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[13] };
  assign _037_ = { 2'h0, a[14] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[15] };
  assign _038_ = { 2'h0, a[16] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[17] };
  assign _039_ = { 2'h0, a[0] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[1] };
  assign _040_ = { 2'h0, a[18] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[19] };
  assign _041_ = { 2'h0, a[20] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[21] };
  assign _042_ = { 2'h0, a[22] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[23] };
  assign _043_ = { 2'h0, a[24] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[25] };
  assign _044_ = { 2'h0, a[26] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[27] };
  assign _045_ = { 2'h0, a[28] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[29] };
  assign _046_ = { 2'h0, a[30] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[31] };
  assign _047_ = { 2'h0, a[32] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[33] };
  assign _048_ = { 2'h0, a[34] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[35] };
  assign _049_ = { 2'h0, a[36] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[37] };
  assign _050_ = { 2'h0, a[2] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[3] };
  assign _051_ = { 2'h0, a[38] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[39] };
  assign _052_ = { 2'h0, a[40] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[41] };
  assign _053_ = { 2'h0, a[42] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[43] };
  assign _054_ = { 2'h0, a[44] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[45] };
  assign _055_ = { 2'h0, a[46] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[47] };
  assign _056_ = { 2'h0, a[48] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[49] };
  assign _057_ = { 2'h0, a[50] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[51] };
  assign _058_ = { 2'h0, a[52] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[53] };
  assign _059_ = { 2'h0, a[54] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[55] };
  assign _060_ = { 2'h0, a[56] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[57] };
  assign _061_ = { 2'h0, a[4] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[5] };
  assign _062_ = { 2'h0, a[58] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[59] };
  assign _063_ = { 2'h0, a[60] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[61] };
  assign _064_ = { 2'h0, a[62] } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, a[63] };
  assign _065_ = { 2'h0, pop_2_0 } + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" *) { 2'h0, pop_2_1 };
  assign _066_ = data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *) 1'h1;
  assign _067_ = data_len == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" *) 3'h4;
  assign _068_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_0;
  assign _069_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_1;
  assign _070_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_2;
  assign _071_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_3;
  assign _072_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_4;
  assign _073_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_5;
  assign _074_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_6;
  assign _075_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_4_7;
  assign _076_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_6_0;
  assign _077_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_6_1;
  assign _078_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) pop_7_0;
  assign _079_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _068_;
  assign _080_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _069_;
  assign _081_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _070_;
  assign _082_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _071_;
  assign _083_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _072_;
  assign _084_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _073_;
  assign _085_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _074_;
  assign _086_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _075_;
  assign _087_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _076_;
  assign _088_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _077_;
  assign _089_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" *) _078_;
  always @* begin
    if (\initial ) begin end
    _000_ = 1'h0;
  end
  always @* begin
      \initial  <= _000_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _002_;
    (* src = "libresoc.v:176614.5-176614.29" *)
    casez (\initial )
      /* src = "libresoc.v:176614.9-176614.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" *)
    casez ({ \$192 , \$190  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _002_[7:0] = \$194 ;
          _002_[15:8] = \$196 ;
          _002_[23:16] = \$198 ;
          _002_[31:24] = \$200 ;
          _002_[39:32] = \$202 ;
          _002_[47:40] = \$204 ;
          _002_[55:48] = \$206 ;
          _002_[63:56] = \$208 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _002_[31:0] = \$210 ;
          _002_[63:32] = \$212 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _002_ = \$214 ;
        end
    endcase
  end
  always @* begin
      o <= _001_;
  end
  assign \$101  = _003_;
  assign \$104  = _004_;
  assign \$107  = _005_;
  assign \$110  = _006_;
  assign \$113  = _007_;
  assign \$116  = _008_;
  assign \$11  = _009_;
  assign \$119  = _010_;
  assign \$122  = _011_;
  assign \$125  = _012_;
  assign \$128  = _013_;
  assign \$131  = _014_;
  assign \$134  = _015_;
  assign \$137  = _016_;
  assign \$140  = _017_;
  assign \$143  = _018_;
  assign \$146  = _019_;
  assign \$14  = _020_;
  assign \$149  = _021_;
  assign \$152  = _022_;
  assign \$155  = _023_;
  assign \$158  = _024_;
  assign \$161  = _025_;
  assign \$164  = _026_;
  assign \$167  = _027_;
  assign \$170  = _028_;
  assign \$173  = _029_;
  assign \$176  = _030_;
  assign \$17  = _031_;
  assign \$179  = _032_;
  assign \$182  = _033_;
  assign \$185  = _034_;
  assign \$188  = _035_;
  assign \$190  = _066_;
  assign \$192  = _067_;
  assign \$194  = _079_;
  assign \$196  = _080_;
  assign \$198  = _081_;
  assign \$200  = _082_;
  assign \$202  = _083_;
  assign \$204  = _084_;
  assign \$206  = _085_;
  assign \$208  = _086_;
  assign \$20  = _036_;
  assign \$210  = _087_;
  assign \$212  = _088_;
  assign \$214  = _089_;
  assign \$23  = _037_;
  assign \$26  = _038_;
  assign \$2  = _039_;
  assign \$29  = _040_;
  assign \$32  = _041_;
  assign \$35  = _042_;
  assign \$38  = _043_;
  assign \$41  = _044_;
  assign \$44  = _045_;
  assign \$47  = _046_;
  assign \$50  = _047_;
  assign \$53  = _048_;
  assign \$56  = _049_;
  assign \$5  = _050_;
  assign \$59  = _051_;
  assign \$62  = _052_;
  assign \$65  = _053_;
  assign \$68  = _054_;
  assign \$71  = _055_;
  assign \$74  = _056_;
  assign \$77  = _057_;
  assign \$80  = _058_;
  assign \$83  = _059_;
  assign \$86  = _060_;
  assign \$8  = _061_;
  assign \$89  = _062_;
  assign \$92  = _063_;
  assign \$95  = _064_;
  assign \$98  = _065_;
  assign \$1  = \$2 ;
  assign \$4  = \$5 ;
  assign \$7  = \$8 ;
  assign \$10  = \$11 ;
  assign \$13  = \$14 ;
  assign \$16  = \$17 ;
  assign \$19  = \$20 ;
  assign \$22  = \$23 ;
  assign \$25  = \$26 ;
  assign \$28  = \$29 ;
  assign \$31  = \$32 ;
  assign \$34  = \$35 ;
  assign \$37  = \$38 ;
  assign \$40  = \$41 ;
  assign \$43  = \$44 ;
  assign \$46  = \$47 ;
  assign \$49  = \$50 ;
  assign \$52  = \$53 ;
  assign \$55  = \$56 ;
  assign \$58  = \$59 ;
  assign \$61  = \$62 ;
  assign \$64  = \$65 ;
  assign \$67  = \$68 ;
  assign \$70  = \$71 ;
  assign \$73  = \$74 ;
  assign \$76  = \$77 ;
  assign \$79  = \$80 ;
  assign \$82  = \$83 ;
  assign \$85  = \$86 ;
  assign \$88  = \$89 ;
  assign \$91  = \$92 ;
  assign \$94  = \$95 ;
  assign \$97  = \$98 ;
  assign \$100  = \$101 ;
  assign \$103  = \$104 ;
  assign \$106  = \$107 ;
  assign \$109  = \$110 ;
  assign \$112  = \$113 ;
  assign \$115  = \$116 ;
  assign \$118  = \$119 ;
  assign \$121  = \$122 ;
  assign \$124  = \$125 ;
  assign \$127  = \$128 ;
  assign \$130  = \$131 ;
  assign \$133  = \$134 ;
  assign \$136  = \$137 ;
  assign \$139  = \$140 ;
  assign \$142  = \$143 ;
  assign \$145  = \$146 ;
  assign \$148  = \$149 ;
  assign \$151  = \$152 ;
  assign \$154  = \$155 ;
  assign \$157  = \$158 ;
  assign \$160  = \$161 ;
  assign \$163  = \$164 ;
  assign \$166  = \$167 ;
  assign \$169  = \$170 ;
  assign \$172  = \$173 ;
  assign \$175  = \$176 ;
  assign \$178  = \$179 ;
  assign \$181  = \$182 ;
  assign \$184  = \$185 ;
  assign \$187  = \$188 ;
  assign pop_7_0 = \$188 [6:0];
  assign pop_6_1 = \$185 [5:0];
  assign pop_6_0 = \$182 [5:0];
  assign pop_5_3 = \$179 [4:0];
  assign pop_5_2 = \$176 [4:0];
  assign pop_5_1 = \$173 [4:0];
  assign pop_5_0 = \$170 [4:0];
  assign pop_4_7 = \$167 [3:0];
  assign pop_4_6 = \$164 [3:0];
  assign pop_4_5 = \$161 [3:0];
  assign pop_4_4 = \$158 [3:0];
  assign pop_4_3 = \$155 [3:0];
  assign pop_4_2 = \$152 [3:0];
  assign pop_4_1 = \$149 [3:0];
  assign pop_4_0 = \$146 [3:0];
  assign pop_3_15 = \$143 [2:0];
  assign pop_3_14 = \$140 [2:0];
  assign pop_3_13 = \$137 [2:0];
  assign pop_3_12 = \$134 [2:0];
  assign pop_3_11 = \$131 [2:0];
  assign pop_3_10 = \$128 [2:0];
  assign pop_3_9 = \$125 [2:0];
  assign pop_3_8 = \$122 [2:0];
  assign pop_3_7 = \$119 [2:0];
  assign pop_3_6 = \$116 [2:0];
  assign pop_3_5 = \$113 [2:0];
  assign pop_3_4 = \$110 [2:0];
  assign pop_3_3 = \$107 [2:0];
  assign pop_3_2 = \$104 [2:0];
  assign pop_3_1 = \$101 [2:0];
  assign pop_3_0 = \$98 [2:0];
  assign pop_2_31 = \$95 [1:0];
  assign pop_2_30 = \$92 [1:0];
  assign pop_2_29 = \$89 [1:0];
  assign pop_2_28 = \$86 [1:0];
  assign pop_2_27 = \$83 [1:0];
  assign pop_2_26 = \$80 [1:0];
  assign pop_2_25 = \$77 [1:0];
  assign pop_2_24 = \$74 [1:0];
  assign pop_2_23 = \$71 [1:0];
  assign pop_2_22 = \$68 [1:0];
  assign pop_2_21 = \$65 [1:0];
  assign pop_2_20 = \$62 [1:0];
  assign pop_2_19 = \$59 [1:0];
  assign pop_2_18 = \$56 [1:0];
  assign pop_2_17 = \$53 [1:0];
  assign pop_2_16 = \$50 [1:0];
  assign pop_2_15 = \$47 [1:0];
  assign pop_2_14 = \$44 [1:0];
  assign pop_2_13 = \$41 [1:0];
  assign pop_2_12 = \$38 [1:0];
  assign pop_2_11 = \$35 [1:0];
  assign pop_2_10 = \$32 [1:0];
  assign pop_2_9 = \$29 [1:0];
  assign pop_2_8 = \$26 [1:0];
  assign pop_2_7 = \$23 [1:0];
  assign pop_2_6 = \$20 [1:0];
  assign pop_2_5 = \$17 [1:0];
  assign pop_2_4 = \$14 [1:0];
  assign pop_2_3 = \$11 [1:0];
  assign pop_2_2 = \$8 [1:0];
  assign pop_2_1 = \$5 [1:0];
  assign pop_2_0 = \$2 [1:0];
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_cr_in.ppick" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:176770.1-176854.10" *)
module ppick(o, i);
  (* src = "libresoc.v:176827.17-176827.91" *)
  wire _00_;
  (* src = "libresoc.v:176829.18-176829.93" *)
  wire _01_;
  (* src = "libresoc.v:176831.18-176831.93" *)
  wire _02_;
  (* src = "libresoc.v:176832.17-176832.138" *)
  wire [7:0] _03_;
  (* src = "libresoc.v:176834.18-176834.93" *)
  wire _04_;
  (* src = "libresoc.v:176836.18-176836.93" *)
  wire _05_;
  (* src = "libresoc.v:176838.18-176838.93" *)
  wire _06_;
  (* src = "libresoc.v:176841.17-176841.91" *)
  wire _07_;
  (* src = "libresoc.v:176828.18-176828.116" *)
  wire _08_;
  (* src = "libresoc.v:176830.18-176830.122" *)
  wire _09_;
  (* src = "libresoc.v:176833.18-176833.128" *)
  wire _10_;
  (* src = "libresoc.v:176835.18-176835.134" *)
  wire _11_;
  (* src = "libresoc.v:176837.18-176837.140" *)
  wire _12_;
  (* src = "libresoc.v:176839.18-176839.90" *)
  wire _13_;
  (* src = "libresoc.v:176840.17-176840.103" *)
  wire _14_;
  (* src = "libresoc.v:176842.17-176842.109" *)
  wire _15_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [7:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  wire en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [7:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [7:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [7:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t7;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) { i[0], i[1], i[2], i[3], i[4], i[5], i[6], i[7] };
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5], i[6], i[7], ni[3] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4], i[5], i[6], i[7], ni[4] };
  assign _10_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3], i[4], i[5], i[6], i[7], ni[5] };
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2], i[3], i[4], i[5], i[6], i[7], ni[6] };
  assign _12_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1], i[2], i[3], i[4], i[5], i[6], i[7], ni[7] };
  assign _13_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _14_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7], ni[1] };
  assign _15_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6], i[7], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _08_;
  assign \$11  = _01_;
  assign \$16  = _09_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _10_;
  assign \$19  = _04_;
  assign \$24  = _11_;
  assign \$23  = _05_;
  assign \$28  = _12_;
  assign \$27  = _06_;
  assign \$31  = _13_;
  assign \$4  = _14_;
  assign \$3  = _07_;
  assign \$8  = _15_;
  assign en_o = \$31 ;
  assign o = { t0, t1, t2, t3, t4, t5, t6, t7 };
  assign t7 = \$27 ;
  assign t6 = \$23 ;
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[7];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_cr_out.ppick" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:176858.1-176942.10" *)
module \ppick$175 (en_o, o, i);
  (* src = "libresoc.v:176915.17-176915.91" *)
  wire _00_;
  (* src = "libresoc.v:176917.18-176917.93" *)
  wire _01_;
  (* src = "libresoc.v:176919.18-176919.93" *)
  wire _02_;
  (* src = "libresoc.v:176920.17-176920.138" *)
  wire [7:0] _03_;
  (* src = "libresoc.v:176922.18-176922.93" *)
  wire _04_;
  (* src = "libresoc.v:176924.18-176924.93" *)
  wire _05_;
  (* src = "libresoc.v:176926.18-176926.93" *)
  wire _06_;
  (* src = "libresoc.v:176929.17-176929.91" *)
  wire _07_;
  (* src = "libresoc.v:176916.18-176916.116" *)
  wire _08_;
  (* src = "libresoc.v:176918.18-176918.122" *)
  wire _09_;
  (* src = "libresoc.v:176921.18-176921.128" *)
  wire _10_;
  (* src = "libresoc.v:176923.18-176923.134" *)
  wire _11_;
  (* src = "libresoc.v:176925.18-176925.140" *)
  wire _12_;
  (* src = "libresoc.v:176927.18-176927.90" *)
  wire _13_;
  (* src = "libresoc.v:176928.17-176928.103" *)
  wire _14_;
  (* src = "libresoc.v:176930.17-176930.109" *)
  wire _15_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [7:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [7:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [7:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [7:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t7;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) { i[0], i[1], i[2], i[3], i[4], i[5], i[6], i[7] };
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5], i[6], i[7], ni[3] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4], i[5], i[6], i[7], ni[4] };
  assign _10_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3], i[4], i[5], i[6], i[7], ni[5] };
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2], i[3], i[4], i[5], i[6], i[7], ni[6] };
  assign _12_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1], i[2], i[3], i[4], i[5], i[6], i[7], ni[7] };
  assign _13_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _14_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7], ni[1] };
  assign _15_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6], i[7], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _08_;
  assign \$11  = _01_;
  assign \$16  = _09_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _10_;
  assign \$19  = _04_;
  assign \$24  = _11_;
  assign \$23  = _05_;
  assign \$28  = _12_;
  assign \$27  = _06_;
  assign \$31  = _13_;
  assign \$4  = _14_;
  assign \$3  = _07_;
  assign \$8  = _15_;
  assign en_o = \$31 ;
  assign o = { t0, t1, t2, t3, t4, t5, t6, t7 };
  assign t7 = \$27 ;
  assign t6 = \$23 ;
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[7];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_CR_cr_a" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:176946.1-176976.10" *)
module rdpick_CR_cr_a(o, en_o, i);
  (* src = "libresoc.v:176967.17-176967.89" *)
  wire [1:0] _0_;
  (* src = "libresoc.v:176969.17-176969.91" *)
  wire _1_;
  (* src = "libresoc.v:176968.17-176968.103" *)
  wire _2_;
  (* src = "libresoc.v:176970.17-176970.89" *)
  wire _3_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [1:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [1:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [1:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [1:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _2_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _3_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$4  = _2_;
  assign \$3  = _1_;
  assign \$7  = _3_;
  assign en_o = \$7 ;
  assign o = { t1, t0 };
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_CR_cr_b" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:176980.1-177001.10" *)
module rdpick_CR_cr_b(o, en_o, i);
  (* src = "libresoc.v:176995.17-176995.89" *)
  wire _0_;
  (* src = "libresoc.v:176996.17-176996.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_CR_cr_c" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177005.1-177026.10" *)
module rdpick_CR_cr_c(o, en_o, i);
  (* src = "libresoc.v:177020.17-177020.89" *)
  wire _0_;
  (* src = "libresoc.v:177021.17-177021.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_CR_full_cr" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177030.1-177051.10" *)
module rdpick_CR_full_cr(o, en_o, i);
  (* src = "libresoc.v:177045.17-177045.89" *)
  wire _0_;
  (* src = "libresoc.v:177046.17-177046.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_FAST_fast1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177055.1-177112.10" *)
module rdpick_FAST_fast1(o, en_o, i);
  (* src = "libresoc.v:177094.17-177094.91" *)
  wire _00_;
  (* src = "libresoc.v:177096.18-177096.93" *)
  wire _01_;
  (* src = "libresoc.v:177098.18-177098.93" *)
  wire _02_;
  (* src = "libresoc.v:177099.17-177099.89" *)
  wire [4:0] _03_;
  (* src = "libresoc.v:177102.17-177102.91" *)
  wire _04_;
  (* src = "libresoc.v:177095.18-177095.106" *)
  wire _05_;
  (* src = "libresoc.v:177097.18-177097.106" *)
  wire _06_;
  (* src = "libresoc.v:177100.18-177100.90" *)
  wire _07_;
  (* src = "libresoc.v:177101.17-177101.103" *)
  wire _08_;
  (* src = "libresoc.v:177103.17-177103.105" *)
  wire _09_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [4:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [4:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [4:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [4:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _05_;
  assign \$11  = _01_;
  assign \$16  = _06_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$19  = _07_;
  assign \$4  = _08_;
  assign \$3  = _04_;
  assign \$8  = _09_;
  assign en_o = \$19 ;
  assign o = { t4, t3, t2, t1, t0 };
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_INT_rabc" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177116.1-177299.10" *)
module rdpick_INT_rabc(o, en_o, i);
  (* src = "libresoc.v:177239.17-177239.91" *)
  wire _00_;
  (* src = "libresoc.v:177241.18-177241.93" *)
  wire _01_;
  (* src = "libresoc.v:177243.18-177243.93" *)
  wire _02_;
  (* src = "libresoc.v:177244.17-177244.89" *)
  wire [18:0] _03_;
  (* src = "libresoc.v:177246.18-177246.93" *)
  wire _04_;
  (* src = "libresoc.v:177248.18-177248.93" *)
  wire _05_;
  (* src = "libresoc.v:177250.18-177250.93" *)
  wire _06_;
  (* src = "libresoc.v:177252.18-177252.93" *)
  wire _07_;
  (* src = "libresoc.v:177254.18-177254.93" *)
  wire _08_;
  (* src = "libresoc.v:177256.18-177256.93" *)
  wire _09_;
  (* src = "libresoc.v:177258.18-177258.93" *)
  wire _10_;
  (* src = "libresoc.v:177261.18-177261.93" *)
  wire _11_;
  (* src = "libresoc.v:177263.18-177263.93" *)
  wire _12_;
  (* src = "libresoc.v:177265.18-177265.93" *)
  wire _13_;
  (* src = "libresoc.v:177266.17-177266.91" *)
  wire _14_;
  (* src = "libresoc.v:177268.18-177268.93" *)
  wire _15_;
  (* src = "libresoc.v:177270.18-177270.93" *)
  wire _16_;
  (* src = "libresoc.v:177272.18-177272.93" *)
  wire _17_;
  (* src = "libresoc.v:177274.18-177274.93" *)
  wire _18_;
  (* src = "libresoc.v:177240.18-177240.106" *)
  wire _19_;
  (* src = "libresoc.v:177242.18-177242.106" *)
  wire _20_;
  (* src = "libresoc.v:177245.18-177245.106" *)
  wire _21_;
  (* src = "libresoc.v:177247.18-177247.106" *)
  wire _22_;
  (* src = "libresoc.v:177249.18-177249.106" *)
  wire _23_;
  (* src = "libresoc.v:177251.18-177251.106" *)
  wire _24_;
  (* src = "libresoc.v:177253.18-177253.106" *)
  wire _25_;
  (* src = "libresoc.v:177255.18-177255.107" *)
  wire _26_;
  (* src = "libresoc.v:177257.18-177257.108" *)
  wire _27_;
  (* src = "libresoc.v:177259.18-177259.108" *)
  wire _28_;
  (* src = "libresoc.v:177260.17-177260.103" *)
  wire _29_;
  (* src = "libresoc.v:177262.18-177262.108" *)
  wire _30_;
  (* src = "libresoc.v:177264.18-177264.108" *)
  wire _31_;
  (* src = "libresoc.v:177267.18-177267.108" *)
  wire _32_;
  (* src = "libresoc.v:177269.18-177269.108" *)
  wire _33_;
  (* src = "libresoc.v:177271.18-177271.108" *)
  wire _34_;
  (* src = "libresoc.v:177273.18-177273.108" *)
  wire _35_;
  (* src = "libresoc.v:177275.18-177275.90" *)
  wire _36_;
  (* src = "libresoc.v:177276.17-177276.105" *)
  wire _37_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [18:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$60 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$68 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$72 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [18:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [18:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [18:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t10;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t11;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t12;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t13;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t14;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t15;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t16;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t17;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t18;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t7;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t9;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$32 ;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$36 ;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$40 ;
  assign _10_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$44 ;
  assign _11_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$48 ;
  assign _12_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$52 ;
  assign _13_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$56 ;
  assign _14_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _15_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$60 ;
  assign _16_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$64 ;
  assign _17_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$68 ;
  assign _18_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$72 ;
  assign _19_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _20_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _21_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] };
  assign _22_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5:0], ni[6] };
  assign _23_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6:0], ni[7] };
  assign _24_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7:0], ni[8] };
  assign _25_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[8:0], ni[9] };
  assign _26_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[9:0], ni[10] };
  assign _27_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[10:0], ni[11] };
  assign _28_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[11:0], ni[12] };
  assign _29_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _30_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[12:0], ni[13] };
  assign _31_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[13:0], ni[14] };
  assign _32_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[14:0], ni[15] };
  assign _33_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[15:0], ni[16] };
  assign _34_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[16:0], ni[17] };
  assign _35_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[17:0], ni[18] };
  assign _36_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _37_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _19_;
  assign \$11  = _01_;
  assign \$16  = _20_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _21_;
  assign \$19  = _04_;
  assign \$24  = _22_;
  assign \$23  = _05_;
  assign \$28  = _23_;
  assign \$27  = _06_;
  assign \$32  = _24_;
  assign \$31  = _07_;
  assign \$36  = _25_;
  assign \$35  = _08_;
  assign \$40  = _26_;
  assign \$39  = _09_;
  assign \$44  = _27_;
  assign \$43  = _10_;
  assign \$48  = _28_;
  assign \$4  = _29_;
  assign \$47  = _11_;
  assign \$52  = _30_;
  assign \$51  = _12_;
  assign \$56  = _31_;
  assign \$55  = _13_;
  assign \$3  = _14_;
  assign \$60  = _32_;
  assign \$59  = _15_;
  assign \$64  = _33_;
  assign \$63  = _16_;
  assign \$68  = _34_;
  assign \$67  = _17_;
  assign \$72  = _35_;
  assign \$71  = _18_;
  assign \$75  = _36_;
  assign \$8  = _37_;
  assign en_o = \$75 ;
  assign o = { t18, t17, t16, t15, t14, t13, t12, t11, t10, t9, t8, t7, t6, t5, t4, t3, t2, t1, t0 };
  assign t18 = \$71 ;
  assign t17 = \$67 ;
  assign t16 = \$63 ;
  assign t15 = \$59 ;
  assign t14 = \$55 ;
  assign t13 = \$51 ;
  assign t12 = \$47 ;
  assign t11 = \$43 ;
  assign t10 = \$39 ;
  assign t9 = \$35 ;
  assign t8 = \$31 ;
  assign t7 = \$27 ;
  assign t6 = \$23 ;
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_SPR_spr1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177303.1-177324.10" *)
module rdpick_SPR_spr1(o, en_o, i);
  (* src = "libresoc.v:177318.17-177318.89" *)
  wire _0_;
  (* src = "libresoc.v:177319.17-177319.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_XER_xer_ca" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177328.1-177367.10" *)
module rdpick_XER_xer_ca(o, en_o, i);
  (* src = "libresoc.v:177355.17-177355.91" *)
  wire _00_;
  (* src = "libresoc.v:177357.17-177357.89" *)
  wire [2:0] _01_;
  (* src = "libresoc.v:177359.17-177359.91" *)
  wire _02_;
  (* src = "libresoc.v:177356.18-177356.90" *)
  wire _03_;
  (* src = "libresoc.v:177358.17-177358.103" *)
  wire _04_;
  (* src = "libresoc.v:177360.17-177360.105" *)
  wire _05_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [2:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [2:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [2:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _03_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _04_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$11  = _03_;
  assign \$1  = _01_;
  assign \$4  = _04_;
  assign \$3  = _02_;
  assign \$8  = _05_;
  assign en_o = \$11 ;
  assign o = { t2, t1, t0 };
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_XER_xer_ov" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177371.1-177392.10" *)
module rdpick_XER_xer_ov(o, en_o, i);
  (* src = "libresoc.v:177386.17-177386.89" *)
  wire _0_;
  (* src = "libresoc.v:177387.17-177387.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.rdpick_XER_xer_so" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177396.1-177462.10" *)
module rdpick_XER_xer_so(o, en_o, i);
  (* src = "libresoc.v:177441.17-177441.91" *)
  wire _00_;
  (* src = "libresoc.v:177443.18-177443.93" *)
  wire _01_;
  (* src = "libresoc.v:177445.18-177445.93" *)
  wire _02_;
  (* src = "libresoc.v:177446.17-177446.89" *)
  wire [5:0] _03_;
  (* src = "libresoc.v:177448.18-177448.93" *)
  wire _04_;
  (* src = "libresoc.v:177451.17-177451.91" *)
  wire _05_;
  (* src = "libresoc.v:177442.18-177442.106" *)
  wire _06_;
  (* src = "libresoc.v:177444.18-177444.106" *)
  wire _07_;
  (* src = "libresoc.v:177447.18-177447.106" *)
  wire _08_;
  (* src = "libresoc.v:177449.18-177449.90" *)
  wire _09_;
  (* src = "libresoc.v:177450.17-177450.103" *)
  wire _10_;
  (* src = "libresoc.v:177452.17-177452.105" *)
  wire _11_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [5:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [5:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [5:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [5:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _10_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _06_;
  assign \$11  = _01_;
  assign \$16  = _07_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _08_;
  assign \$19  = _04_;
  assign \$23  = _09_;
  assign \$4  = _10_;
  assign \$3  = _05_;
  assign \$8  = _11_;
  assign en_o = \$23 ;
  assign o = { t5, t4, t3, t2, t1, t0 };
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177466.1-177937.10" *)
module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, src30__ren, src30__data_o, dest10__wen, dest10__data_i, dest20__wen, dest20__data_i, r0__data_o, r0__ren, r20__data_o, r20__ren, w0__data_i, w0__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:177467.7-177467.20" *)
  reg _00_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:177552.3-177553.37" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:177550.3-177551.39" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:177630.3-177656.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:177548.3-177549.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:177558.3-177559.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:177556.3-177557.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:177554.3-177555.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:177837.3-177866.6" *)
  reg _13_;
  (* src = "libresoc.v:177907.3-177936.6" *)
  reg _14_;
  (* src = "libresoc.v:177697.3-177726.6" *)
  reg _15_;
  (* src = "libresoc.v:177767.3-177796.6" *)
  reg _16_;
  (* src = "libresoc.v:177600.3-177629.6" *)
  reg _17_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:177492.13-177492.30" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:177499.13-177499.31" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:177630.3-177656.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:177505.13-177505.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:177510.13-177510.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:177517.13-177517.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:177524.13-177524.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:177837.3-177866.6" *)
  reg _30_;
  (* src = "libresoc.v:177907.3-177936.6" *)
  reg _31_;
  (* src = "libresoc.v:177697.3-177726.6" *)
  reg _32_;
  (* src = "libresoc.v:177767.3-177796.6" *)
  reg _33_;
  (* src = "libresoc.v:177600.3-177629.6" *)
  reg _34_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:177630.3-177656.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:177837.3-177866.6" *)
  reg _41_;
  (* src = "libresoc.v:177907.3-177936.6" *)
  reg _42_;
  (* src = "libresoc.v:177697.3-177726.6" *)
  reg _43_;
  (* src = "libresoc.v:177767.3-177796.6" *)
  reg _44_;
  (* src = "libresoc.v:177600.3-177629.6" *)
  reg _45_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:177630.3-177656.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:177837.3-177866.6" *)
  reg _52_;
  (* src = "libresoc.v:177907.3-177936.6" *)
  reg _53_;
  (* src = "libresoc.v:177697.3-177726.6" *)
  reg _54_;
  (* src = "libresoc.v:177767.3-177796.6" *)
  reg _55_;
  (* src = "libresoc.v:177600.3-177629.6" *)
  reg _56_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:177630.3-177656.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:177837.3-177866.6" *)
  reg _63_;
  (* src = "libresoc.v:177907.3-177936.6" *)
  reg _64_;
  (* src = "libresoc.v:177697.3-177726.6" *)
  reg _65_;
  (* src = "libresoc.v:177767.3-177796.6" *)
  reg _66_;
  (* src = "libresoc.v:177600.3-177629.6" *)
  reg _67_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:177797.3-177836.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:177867.3-177906.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:177560.3-177599.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:177657.3-177696.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:177727.3-177766.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:177543.17-177543.104" *)
  wire _78_;
  (* src = "libresoc.v:177544.18-177544.105" *)
  wire _79_;
  (* src = "libresoc.v:177545.17-177545.100" *)
  wire _80_;
  (* src = "libresoc.v:177546.17-177546.103" *)
  wire _81_;
  (* src = "libresoc.v:177547.17-177547.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest10__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest20__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest20__wen;
  (* src = "libresoc.v:177467.7-177467.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r0__data_o;
  reg [3:0] r0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r0__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r20__data_o;
  reg [3:0] r20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r20__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r20__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src10__data_o;
  reg [3:0] src10__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src10__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src10__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src20__data_o;
  reg [3:0] src20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src20__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src20__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src30__data_o;
  reg [3:0] src30__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src30__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src30__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w0__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r0__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r20__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src10__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src20__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src30__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r20__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r20__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r0__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r0__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src30__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src30__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src20__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src20__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src10__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src10__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:177561.5-177561.29" *)
    casez (\initial )
      /* src = "libresoc.v:177561.9-177561.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src10__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest10__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest20__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w0__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src10__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:177601.5-177601.29" *)
    casez (\initial )
      /* src = "libresoc.v:177601.9-177601.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src10__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:177631.5-177631.29" *)
    casez (\initial )
      /* src = "libresoc.v:177631.9-177631.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest10__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest10__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest20__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest20__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w0__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w0__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:177658.5-177658.29" *)
    casez (\initial )
      /* src = "libresoc.v:177658.9-177658.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest10__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest20__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w0__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src20__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:177698.5-177698.29" *)
    casez (\initial )
      /* src = "libresoc.v:177698.9-177698.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:177728.5-177728.29" *)
    casez (\initial )
      /* src = "libresoc.v:177728.9-177728.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src30__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest10__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest20__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w0__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src30__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:177768.5-177768.29" *)
    casez (\initial )
      /* src = "libresoc.v:177768.9-177768.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src30__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:177798.5-177798.29" *)
    casez (\initial )
      /* src = "libresoc.v:177798.9-177798.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest10__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest20__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w0__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r0__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:177838.5-177838.29" *)
    casez (\initial )
      /* src = "libresoc.v:177838.9-177838.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:177868.5-177868.29" *)
    casez (\initial )
      /* src = "libresoc.v:177868.9-177868.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest10__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest20__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w0__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r20__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:177908.5-177908.29" *)
    casez (\initial )
      /* src = "libresoc.v:177908.9-177908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.xer.reg_0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:177941.1-178386.10" *)
module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, src30__ren, src30__data_o, dest10__wen, dest10__data_i, dest20__wen, dest20__data_i, dest30__wen, dest30__data_i, r0__data_o, r0__ren, w0__data_i, w0__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:177942.7-177942.20" *)
  reg _00_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:178017.3-178018.37" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _03_;
  (* src = "libresoc.v:178015.3-178016.25" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:178023.3-178024.43" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:178021.3-178022.43" *)
  reg [1:0] _08_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:178019.3-178020.43" *)
  reg [1:0] _10_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _11_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _12_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _13_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _14_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:177969.13-177969.30" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:177975.13-177975.25" *)
  reg [1:0] _18_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _19_;
  (* src = "libresoc.v:177980.13-177980.33" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:177987.13-177987.33" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:177994.13-177994.33" *)
  reg [1:0] _24_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _25_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _26_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _27_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _28_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _29_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _30_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _31_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _33_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _34_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _35_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _36_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _37_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _41_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _42_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _43_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _44_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _45_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _46_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _47_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _48_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _49_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _50_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _51_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _52_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _53_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _54_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _55_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _56_;
  (* src = "libresoc.v:178353.3-178385.6" *)
  reg [1:0] _57_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _58_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _59_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _60_;
  (* src = "libresoc.v:178317.3-178352.6" *)
  reg _61_;
  (* src = "libresoc.v:178153.3-178188.6" *)
  reg _62_;
  (* src = "libresoc.v:178235.3-178270.6" *)
  reg _63_;
  (* src = "libresoc.v:178071.3-178106.6" *)
  reg _64_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _65_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _66_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _67_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _68_;
  (* src = "libresoc.v:178271.3-178316.6" *)
  reg [1:0] _69_;
  (* src = "libresoc.v:178025.3-178070.6" *)
  reg [1:0] _70_;
  (* src = "libresoc.v:178107.3-178152.6" *)
  reg [1:0] _71_;
  (* src = "libresoc.v:178189.3-178234.6" *)
  reg [1:0] _72_;
  (* src = "libresoc.v:178011.17-178011.104" *)
  wire _73_;
  (* src = "libresoc.v:178012.17-178012.100" *)
  wire _74_;
  (* src = "libresoc.v:178013.17-178013.103" *)
  wire _75_;
  (* src = "libresoc.v:178014.17-178014.103" *)
  wire _76_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest10__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest20__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest20__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest30__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest30__wen;
  (* src = "libresoc.v:177942.7-177942.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] r0__data_o;
  reg [1:0] r0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \r0__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r0__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src10__data_o;
  reg [1:0] src10__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src10__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src10__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src20__data_o;
  reg [1:0] src20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src20__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src20__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src30__data_o;
  reg [1:0] src30__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src30__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src30__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] w0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w0__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _73_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _74_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _75_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _76_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _16_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      r0__data_o <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src10__data_o <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src20__data_o <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src30__data_o <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r0__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r0__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src30__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src30__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src20__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src20__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \src10__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src10__data_o <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _70_;
    (* src = "libresoc.v:178026.5-178026.29" *)
    casez (\initial )
      /* src = "libresoc.v:178026.9-178026.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src10__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _19_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = dest10__data_i;
              end
            default:
                _31_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest20__data_i;
              end
            default:
                _40_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest30__data_i;
              end
            default:
                _49_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w0__data_i;
              end
            default:
                _58_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = \reg ;
              end
            default:
                _66_ = _58_;
          endcase
        end
      default:
          _19_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _70_ = 2'h0;
        end
      default:
          _70_ = _19_;
    endcase
  end
  always @* begin
      \src10__data_o$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _28_;
    (* src = "libresoc.v:178072.5-178072.29" *)
    casez (\initial )
      /* src = "libresoc.v:178072.9-178072.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src10__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = 1'h1;
              end
            default:
                _37_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = 1'h1;
              end
            default:
                _46_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _55_;
          endcase
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _71_;
    (* src = "libresoc.v:178108.5-178108.29" *)
    casez (\initial )
      /* src = "libresoc.v:178108.9-178108.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _32_ = dest10__data_i;
              end
            default:
                _32_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = dest20__data_i;
              end
            default:
                _41_ = _32_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest30__data_i;
              end
            default:
                _50_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _59_ = w0__data_i;
              end
            default:
                _59_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = \reg ;
              end
            default:
                _67_ = _59_;
          endcase
        end
      default:
          _21_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _71_ = 2'h0;
        end
      default:
          _71_ = _21_;
    endcase
  end
  always @* begin
      \src20__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:178154.5-178154.29" *)
    casez (\initial )
      /* src = "libresoc.v:178154.9-178154.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src20__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _62_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = 1'h1;
              end
            default:
                _62_ = _53_;
          endcase
        end
      default:
          _26_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _72_;
    (* src = "libresoc.v:178190.5-178190.29" *)
    casez (\initial )
      /* src = "libresoc.v:178190.9-178190.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src30__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _23_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = dest10__data_i;
              end
            default:
                _33_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = dest20__data_i;
              end
            default:
                _42_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest30__data_i;
              end
            default:
                _51_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w0__data_i;
              end
            default:
                _60_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _60_;
          endcase
        end
      default:
          _23_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _72_ = 2'h0;
        end
      default:
          _72_ = _23_;
    endcase
  end
  always @* begin
      \src30__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _27_;
    (* src = "libresoc.v:178236.5-178236.29" *)
    casez (\initial )
      /* src = "libresoc.v:178236.9-178236.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src30__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _27_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _54_;
          endcase
        end
      default:
          _27_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _69_;
    (* src = "libresoc.v:178272.5-178272.29" *)
    casez (\initial )
      /* src = "libresoc.v:178272.9-178272.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = dest10__data_i;
              end
            default:
                _29_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest20__data_i;
              end
            default:
                _38_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest30__data_i;
              end
            default:
                _47_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = w0__data_i;
              end
            default:
                _56_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = \reg ;
              end
            default:
                _65_ = _56_;
          endcase
        end
      default:
          _15_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _69_ = 2'h0;
        end
      default:
          _69_ = _15_;
    endcase
  end
  always @* begin
      \r0__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:178318.5-178318.29" *)
    casez (\initial )
      /* src = "libresoc.v:178318.9-178318.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = _61_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest20__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest30__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = 1'h1;
              end
            default:
                _61_ = _52_;
          endcase
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _57_;
    (* src = "libresoc.v:178354.5-178354.29" *)
    casez (\initial )
      /* src = "libresoc.v:178354.9-178354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest10__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = dest10__data_i;
        end
      default:
          _17_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest20__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = dest20__data_i;
        end
      default:
          _30_ = _17_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest30__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = dest30__data_i;
        end
      default:
          _39_ = _30_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w0__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w0__data_i;
        end
      default:
          _48_ = _39_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _57_ = 2'h0;
        end
      default:
          _57_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _03_;
  end
  assign \$9  = _73_;
  assign \$1  = _74_;
  assign \$3  = _75_;
  assign \$6  = _76_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.state.reg_0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:178390.1-178739.10" *)
module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_o, sv0__ren, sv0__data_o, nia0__wen, nia0__data_i, msr0__wen, msr0__data_i, sv0__wen, sv0__data_i, d_wr10__wen, d_wr10__data_i, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:178458.3-178459.41" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:178391.7-178391.20" *)
  reg _02_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:178456.3-178457.41" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:178452.3-178453.25" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:178454.3-178455.39" *)
  reg [63:0] _08_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _09_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _10_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _11_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:178400.14-178400.49" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:178417.14-178417.49" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:178429.14-178429.42" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:178436.14-178436.48" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _20_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _21_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _22_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _27_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _28_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _29_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _30_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _31_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _32_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _34_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _35_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _36_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _37_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _38_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _40_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _41_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _42_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _43_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _44_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _45_;
  (* src = "libresoc.v:178706.3-178738.6" *)
  reg [63:0] _46_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _47_;
  (* src = "libresoc.v:178588.3-178623.6" *)
  reg _48_;
  (* src = "libresoc.v:178670.3-178705.6" *)
  reg _49_;
  (* src = "libresoc.v:178506.3-178541.6" *)
  reg _50_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _51_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _53_;
  (* src = "libresoc.v:178460.3-178505.6" *)
  reg [63:0] _54_;
  (* src = "libresoc.v:178542.3-178587.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:178624.3-178669.6" *)
  reg [63:0] _56_;
  (* src = "libresoc.v:178449.17-178449.100" *)
  wire _57_;
  (* src = "libresoc.v:178450.17-178450.103" *)
  wire _58_;
  (* src = "libresoc.v:178451.17-178451.103" *)
  wire _59_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] cia0__data_o;
  reg [63:0] cia0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \cia0__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input cia0__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] d_wr10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input d_wr10__wen;
  (* src = "libresoc.v:178391.7-178391.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] msr0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] msr0__data_o;
  reg [63:0] msr0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \msr0__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] nia0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input nia0__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] sv0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] sv0__data_o;
  reg [63:0] sv0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \sv0__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv0__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _57_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _58_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _59_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      cia0__data_o <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      msr0__data_o <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \reg  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      sv0__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \sv0__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      sv0__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \msr0__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      msr0__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \cia0__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      cia0__data_o <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _54_;
    (* src = "libresoc.v:178461.5-178461.29" *)
    casez (\initial )
      /* src = "libresoc.v:178461.9-178461.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = _51_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _23_ = nia0__data_i;
              end
            default:
                _23_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _30_ = msr0__data_i;
              end
            default:
                _30_ = _23_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = sv0__data_i;
              end
            default:
                _37_ = _30_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = d_wr10__data_i;
              end
            default:
                _44_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = \reg ;
              end
            default:
                _51_ = _44_;
          endcase
        end
      default:
          _12_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _54_ = 64'h0000000000000000;
        end
      default:
          _54_ = _12_;
    endcase
  end
  always @* begin
      \cia0__data_o$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _22_;
    (* src = "libresoc.v:178507.5-178507.29" *)
    casez (\initial )
      /* src = "libresoc.v:178507.9-178507.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = _50_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = 1'h1;
              end
            default:
                _29_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = 1'h1;
              end
            default:
                _50_ = _43_;
          endcase
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _55_;
    (* src = "libresoc.v:178543.5-178543.29" *)
    casez (\initial )
      /* src = "libresoc.v:178543.9-178543.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = _52_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = nia0__data_i;
              end
            default:
                _24_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = msr0__data_i;
              end
            default:
                _31_ = _24_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = sv0__data_i;
              end
            default:
                _38_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = d_wr10__data_i;
              end
            default:
                _45_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = \reg ;
              end
            default:
                _52_ = _45_;
          endcase
        end
      default:
          _14_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _55_ = 64'h0000000000000000;
        end
      default:
          _55_ = _14_;
    endcase
  end
  always @* begin
      \msr0__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _20_;
    (* src = "libresoc.v:178589.5-178589.29" *)
    casez (\initial )
      /* src = "libresoc.v:178589.9-178589.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _48_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _27_ = 1'h1;
              end
            default:
                _27_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = _27_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _48_ = 1'h1;
              end
            default:
                _48_ = _41_;
          endcase
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _56_;
    (* src = "libresoc.v:178625.5-178625.29" *)
    casez (\initial )
      /* src = "libresoc.v:178625.9-178625.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _53_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _26_ = nia0__data_i;
              end
            default:
                _26_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = msr0__data_i;
              end
            default:
                _33_ = _26_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = sv0__data_i;
              end
            default:
                _40_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = d_wr10__data_i;
              end
            default:
                _47_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = \reg ;
              end
            default:
                _53_ = _47_;
          endcase
        end
      default:
          _18_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _56_ = 64'h0000000000000000;
        end
      default:
          _56_ = _18_;
    endcase
  end
  always @* begin
      \sv0__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _21_;
    (* src = "libresoc.v:178671.5-178671.29" *)
    casez (\initial )
      /* src = "libresoc.v:178671.9-178671.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv0__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _49_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _28_ = 1'h1;
              end
            default:
                _28_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = _28_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv0__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr10__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = 1'h1;
              end
            default:
                _49_ = _42_;
          endcase
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _46_;
    (* src = "libresoc.v:178707.5-178707.29" *)
    casez (\initial )
      /* src = "libresoc.v:178707.9-178707.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (nia0__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = nia0__data_i;
        end
      default:
          _16_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (msr0__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = msr0__data_i;
        end
      default:
          _25_ = _16_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (sv0__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = sv0__data_i;
        end
      default:
          _32_ = _25_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (d_wr10__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = d_wr10__data_i;
        end
      default:
          _39_ = _32_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _46_ = 64'h0000000000000000;
        end
      default:
          _46_ = _39_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  assign \$1  = _57_;
  assign \$3  = _58_;
  assign \$6  = _59_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:178743.1-179214.10" *)
module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, src31__ren, src31__data_o, dest11__wen, dest11__data_i, dest21__wen, dest21__data_i, r1__data_o, r1__ren, r21__data_o, r21__ren, w1__data_i, w1__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:178744.7-178744.20" *)
  reg _00_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:178829.3-178830.37" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:178827.3-178828.39" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:178907.3-178933.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:178825.3-178826.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:178835.3-178836.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:178833.3-178834.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:178831.3-178832.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:179114.3-179143.6" *)
  reg _13_;
  (* src = "libresoc.v:179184.3-179213.6" *)
  reg _14_;
  (* src = "libresoc.v:178974.3-179003.6" *)
  reg _15_;
  (* src = "libresoc.v:179044.3-179073.6" *)
  reg _16_;
  (* src = "libresoc.v:178877.3-178906.6" *)
  reg _17_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:178769.13-178769.30" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:178776.13-178776.31" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:178907.3-178933.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:178782.13-178782.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:178787.13-178787.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:178794.13-178794.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:178801.13-178801.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:179114.3-179143.6" *)
  reg _30_;
  (* src = "libresoc.v:179184.3-179213.6" *)
  reg _31_;
  (* src = "libresoc.v:178974.3-179003.6" *)
  reg _32_;
  (* src = "libresoc.v:179044.3-179073.6" *)
  reg _33_;
  (* src = "libresoc.v:178877.3-178906.6" *)
  reg _34_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:178907.3-178933.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:179114.3-179143.6" *)
  reg _41_;
  (* src = "libresoc.v:179184.3-179213.6" *)
  reg _42_;
  (* src = "libresoc.v:178974.3-179003.6" *)
  reg _43_;
  (* src = "libresoc.v:179044.3-179073.6" *)
  reg _44_;
  (* src = "libresoc.v:178877.3-178906.6" *)
  reg _45_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:178907.3-178933.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:179114.3-179143.6" *)
  reg _52_;
  (* src = "libresoc.v:179184.3-179213.6" *)
  reg _53_;
  (* src = "libresoc.v:178974.3-179003.6" *)
  reg _54_;
  (* src = "libresoc.v:179044.3-179073.6" *)
  reg _55_;
  (* src = "libresoc.v:178877.3-178906.6" *)
  reg _56_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:178907.3-178933.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:179114.3-179143.6" *)
  reg _63_;
  (* src = "libresoc.v:179184.3-179213.6" *)
  reg _64_;
  (* src = "libresoc.v:178974.3-179003.6" *)
  reg _65_;
  (* src = "libresoc.v:179044.3-179073.6" *)
  reg _66_;
  (* src = "libresoc.v:178877.3-178906.6" *)
  reg _67_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:179074.3-179113.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:179144.3-179183.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:178837.3-178876.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:178934.3-178973.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:179004.3-179043.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:178820.17-178820.104" *)
  wire _78_;
  (* src = "libresoc.v:178821.18-178821.105" *)
  wire _79_;
  (* src = "libresoc.v:178822.17-178822.100" *)
  wire _80_;
  (* src = "libresoc.v:178823.17-178823.103" *)
  wire _81_;
  (* src = "libresoc.v:178824.17-178824.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest11__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest21__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest21__wen;
  (* src = "libresoc.v:178744.7-178744.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r1__data_o;
  reg [3:0] r1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r1__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r21__data_o;
  reg [3:0] r21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r21__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r21__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src11__data_o;
  reg [3:0] src11__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src11__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src11__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src21__data_o;
  reg [3:0] src21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src21__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src21__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src31__data_o;
  reg [3:0] src31__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src31__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src31__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w1__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r1__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r21__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src11__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src21__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src31__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r21__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r21__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r1__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r1__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src31__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src31__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src21__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src21__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src11__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src11__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:178838.5-178838.29" *)
    casez (\initial )
      /* src = "libresoc.v:178838.9-178838.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src11__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest11__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest21__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w1__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src11__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:178878.5-178878.29" *)
    casez (\initial )
      /* src = "libresoc.v:178878.9-178878.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src11__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:178908.5-178908.29" *)
    casez (\initial )
      /* src = "libresoc.v:178908.9-178908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest11__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest11__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest21__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest21__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w1__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w1__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:178935.5-178935.29" *)
    casez (\initial )
      /* src = "libresoc.v:178935.9-178935.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest11__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest21__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w1__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src21__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:178975.5-178975.29" *)
    casez (\initial )
      /* src = "libresoc.v:178975.9-178975.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:179005.5-179005.29" *)
    casez (\initial )
      /* src = "libresoc.v:179005.9-179005.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src31__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest11__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest21__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w1__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src31__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:179045.5-179045.29" *)
    casez (\initial )
      /* src = "libresoc.v:179045.9-179045.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src31__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:179075.5-179075.29" *)
    casez (\initial )
      /* src = "libresoc.v:179075.9-179075.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest11__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest21__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w1__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r1__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:179115.5-179115.29" *)
    casez (\initial )
      /* src = "libresoc.v:179115.9-179115.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:179145.5-179145.29" *)
    casez (\initial )
      /* src = "libresoc.v:179145.9-179145.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest11__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest21__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w1__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r21__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:179185.5-179185.29" *)
    casez (\initial )
      /* src = "libresoc.v:179185.9-179185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.xer.reg_1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:179218.1-179663.10" *)
module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, src31__ren, src31__data_o, dest11__wen, dest11__data_i, dest21__wen, dest21__data_i, dest31__wen, dest31__data_i, r1__data_o, r1__ren, w1__data_i, w1__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:179219.7-179219.20" *)
  reg _00_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:179294.3-179295.37" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _03_;
  (* src = "libresoc.v:179292.3-179293.25" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:179300.3-179301.43" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:179298.3-179299.43" *)
  reg [1:0] _08_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:179296.3-179297.43" *)
  reg [1:0] _10_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _11_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _12_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _13_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _14_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:179246.13-179246.30" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:179252.13-179252.25" *)
  reg [1:0] _18_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _19_;
  (* src = "libresoc.v:179257.13-179257.33" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:179264.13-179264.33" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:179271.13-179271.33" *)
  reg [1:0] _24_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _25_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _26_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _27_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _28_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _29_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _30_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _31_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _33_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _34_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _35_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _36_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _37_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _41_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _42_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _43_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _44_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _45_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _46_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _47_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _48_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _49_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _50_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _51_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _52_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _53_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _54_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _55_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _56_;
  (* src = "libresoc.v:179630.3-179662.6" *)
  reg [1:0] _57_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _58_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _59_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _60_;
  (* src = "libresoc.v:179594.3-179629.6" *)
  reg _61_;
  (* src = "libresoc.v:179430.3-179465.6" *)
  reg _62_;
  (* src = "libresoc.v:179512.3-179547.6" *)
  reg _63_;
  (* src = "libresoc.v:179348.3-179383.6" *)
  reg _64_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _65_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _66_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _67_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _68_;
  (* src = "libresoc.v:179548.3-179593.6" *)
  reg [1:0] _69_;
  (* src = "libresoc.v:179302.3-179347.6" *)
  reg [1:0] _70_;
  (* src = "libresoc.v:179384.3-179429.6" *)
  reg [1:0] _71_;
  (* src = "libresoc.v:179466.3-179511.6" *)
  reg [1:0] _72_;
  (* src = "libresoc.v:179288.17-179288.104" *)
  wire _73_;
  (* src = "libresoc.v:179289.17-179289.100" *)
  wire _74_;
  (* src = "libresoc.v:179290.17-179290.103" *)
  wire _75_;
  (* src = "libresoc.v:179291.17-179291.103" *)
  wire _76_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest11__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest21__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest21__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest31__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest31__wen;
  (* src = "libresoc.v:179219.7-179219.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] r1__data_o;
  reg [1:0] r1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \r1__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r1__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src11__data_o;
  reg [1:0] src11__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src11__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src11__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src21__data_o;
  reg [1:0] src21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src21__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src21__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src31__data_o;
  reg [1:0] src31__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src31__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src31__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] w1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w1__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _73_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _74_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _75_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _76_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _16_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      r1__data_o <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src11__data_o <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src21__data_o <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src31__data_o <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r1__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r1__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src31__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src31__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src21__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src21__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \src11__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src11__data_o <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _70_;
    (* src = "libresoc.v:179303.5-179303.29" *)
    casez (\initial )
      /* src = "libresoc.v:179303.9-179303.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src11__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _19_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = dest11__data_i;
              end
            default:
                _31_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest21__data_i;
              end
            default:
                _40_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest31__data_i;
              end
            default:
                _49_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w1__data_i;
              end
            default:
                _58_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = \reg ;
              end
            default:
                _66_ = _58_;
          endcase
        end
      default:
          _19_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _70_ = 2'h0;
        end
      default:
          _70_ = _19_;
    endcase
  end
  always @* begin
      \src11__data_o$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _28_;
    (* src = "libresoc.v:179349.5-179349.29" *)
    casez (\initial )
      /* src = "libresoc.v:179349.9-179349.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src11__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = 1'h1;
              end
            default:
                _37_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = 1'h1;
              end
            default:
                _46_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _55_;
          endcase
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _71_;
    (* src = "libresoc.v:179385.5-179385.29" *)
    casez (\initial )
      /* src = "libresoc.v:179385.9-179385.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _32_ = dest11__data_i;
              end
            default:
                _32_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = dest21__data_i;
              end
            default:
                _41_ = _32_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest31__data_i;
              end
            default:
                _50_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _59_ = w1__data_i;
              end
            default:
                _59_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = \reg ;
              end
            default:
                _67_ = _59_;
          endcase
        end
      default:
          _21_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _71_ = 2'h0;
        end
      default:
          _71_ = _21_;
    endcase
  end
  always @* begin
      \src21__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:179431.5-179431.29" *)
    casez (\initial )
      /* src = "libresoc.v:179431.9-179431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src21__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _62_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = 1'h1;
              end
            default:
                _62_ = _53_;
          endcase
        end
      default:
          _26_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _72_;
    (* src = "libresoc.v:179467.5-179467.29" *)
    casez (\initial )
      /* src = "libresoc.v:179467.9-179467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src31__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _23_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = dest11__data_i;
              end
            default:
                _33_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = dest21__data_i;
              end
            default:
                _42_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest31__data_i;
              end
            default:
                _51_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w1__data_i;
              end
            default:
                _60_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _60_;
          endcase
        end
      default:
          _23_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _72_ = 2'h0;
        end
      default:
          _72_ = _23_;
    endcase
  end
  always @* begin
      \src31__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _27_;
    (* src = "libresoc.v:179513.5-179513.29" *)
    casez (\initial )
      /* src = "libresoc.v:179513.9-179513.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src31__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _27_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _54_;
          endcase
        end
      default:
          _27_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _69_;
    (* src = "libresoc.v:179549.5-179549.29" *)
    casez (\initial )
      /* src = "libresoc.v:179549.9-179549.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = dest11__data_i;
              end
            default:
                _29_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest21__data_i;
              end
            default:
                _38_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest31__data_i;
              end
            default:
                _47_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = w1__data_i;
              end
            default:
                _56_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = \reg ;
              end
            default:
                _65_ = _56_;
          endcase
        end
      default:
          _15_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _69_ = 2'h0;
        end
      default:
          _69_ = _15_;
    endcase
  end
  always @* begin
      \r1__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:179595.5-179595.29" *)
    casez (\initial )
      /* src = "libresoc.v:179595.9-179595.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = _61_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest21__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest31__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = 1'h1;
              end
            default:
                _61_ = _52_;
          endcase
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _57_;
    (* src = "libresoc.v:179631.5-179631.29" *)
    casez (\initial )
      /* src = "libresoc.v:179631.9-179631.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest11__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = dest11__data_i;
        end
      default:
          _17_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest21__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = dest21__data_i;
        end
      default:
          _30_ = _17_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest31__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = dest31__data_i;
        end
      default:
          _39_ = _30_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w1__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w1__data_i;
        end
      default:
          _48_ = _39_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _57_ = 2'h0;
        end
      default:
          _57_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _03_;
  end
  assign \$9  = _73_;
  assign \$1  = _74_;
  assign \$3  = _75_;
  assign \$6  = _76_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.state.reg_1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:179667.1-180016.10" *)
module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_o, sv1__ren, sv1__data_o, nia1__wen, nia1__data_i, msr1__wen, msr1__data_i, sv1__wen, sv1__data_i, d_wr11__wen, d_wr11__data_i, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:179735.3-179736.41" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:179668.7-179668.20" *)
  reg _02_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:179733.3-179734.41" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:179729.3-179730.25" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:179731.3-179732.39" *)
  reg [63:0] _08_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _09_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _10_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _11_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:179677.14-179677.49" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:179694.14-179694.49" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:179706.14-179706.42" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:179713.14-179713.48" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _20_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _21_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _22_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _27_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _28_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _29_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _30_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _31_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _32_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _34_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _35_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _36_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _37_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _38_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _40_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _41_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _42_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _43_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _44_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _45_;
  (* src = "libresoc.v:179983.3-180015.6" *)
  reg [63:0] _46_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _47_;
  (* src = "libresoc.v:179865.3-179900.6" *)
  reg _48_;
  (* src = "libresoc.v:179947.3-179982.6" *)
  reg _49_;
  (* src = "libresoc.v:179783.3-179818.6" *)
  reg _50_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _51_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _53_;
  (* src = "libresoc.v:179737.3-179782.6" *)
  reg [63:0] _54_;
  (* src = "libresoc.v:179819.3-179864.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:179901.3-179946.6" *)
  reg [63:0] _56_;
  (* src = "libresoc.v:179726.17-179726.100" *)
  wire _57_;
  (* src = "libresoc.v:179727.17-179727.103" *)
  wire _58_;
  (* src = "libresoc.v:179728.17-179728.103" *)
  wire _59_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] cia1__data_o;
  reg [63:0] cia1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \cia1__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input cia1__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] d_wr11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input d_wr11__wen;
  (* src = "libresoc.v:179668.7-179668.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] msr1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] msr1__data_o;
  reg [63:0] msr1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \msr1__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] nia1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input nia1__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] sv1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] sv1__data_o;
  reg [63:0] sv1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \sv1__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv1__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _57_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _58_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _59_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      cia1__data_o <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      msr1__data_o <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \reg  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      sv1__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \sv1__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      sv1__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \msr1__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      msr1__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \cia1__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      cia1__data_o <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _54_;
    (* src = "libresoc.v:179738.5-179738.29" *)
    casez (\initial )
      /* src = "libresoc.v:179738.9-179738.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = _51_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _23_ = nia1__data_i;
              end
            default:
                _23_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _30_ = msr1__data_i;
              end
            default:
                _30_ = _23_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = sv1__data_i;
              end
            default:
                _37_ = _30_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = d_wr11__data_i;
              end
            default:
                _44_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = \reg ;
              end
            default:
                _51_ = _44_;
          endcase
        end
      default:
          _12_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _54_ = 64'h0000000000000000;
        end
      default:
          _54_ = _12_;
    endcase
  end
  always @* begin
      \cia1__data_o$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _22_;
    (* src = "libresoc.v:179784.5-179784.29" *)
    casez (\initial )
      /* src = "libresoc.v:179784.9-179784.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = _50_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = 1'h1;
              end
            default:
                _29_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = 1'h1;
              end
            default:
                _50_ = _43_;
          endcase
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _55_;
    (* src = "libresoc.v:179820.5-179820.29" *)
    casez (\initial )
      /* src = "libresoc.v:179820.9-179820.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = _52_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = nia1__data_i;
              end
            default:
                _24_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = msr1__data_i;
              end
            default:
                _31_ = _24_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = sv1__data_i;
              end
            default:
                _38_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = d_wr11__data_i;
              end
            default:
                _45_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = \reg ;
              end
            default:
                _52_ = _45_;
          endcase
        end
      default:
          _14_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _55_ = 64'h0000000000000000;
        end
      default:
          _55_ = _14_;
    endcase
  end
  always @* begin
      \msr1__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _20_;
    (* src = "libresoc.v:179866.5-179866.29" *)
    casez (\initial )
      /* src = "libresoc.v:179866.9-179866.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _48_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _27_ = 1'h1;
              end
            default:
                _27_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = _27_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _48_ = 1'h1;
              end
            default:
                _48_ = _41_;
          endcase
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _56_;
    (* src = "libresoc.v:179902.5-179902.29" *)
    casez (\initial )
      /* src = "libresoc.v:179902.9-179902.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _53_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _26_ = nia1__data_i;
              end
            default:
                _26_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = msr1__data_i;
              end
            default:
                _33_ = _26_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = sv1__data_i;
              end
            default:
                _40_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = d_wr11__data_i;
              end
            default:
                _47_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = \reg ;
              end
            default:
                _53_ = _47_;
          endcase
        end
      default:
          _18_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _56_ = 64'h0000000000000000;
        end
      default:
          _56_ = _18_;
    endcase
  end
  always @* begin
      \sv1__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _21_;
    (* src = "libresoc.v:179948.5-179948.29" *)
    casez (\initial )
      /* src = "libresoc.v:179948.9-179948.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv1__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _49_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _28_ = 1'h1;
              end
            default:
                _28_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = _28_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv1__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr11__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = 1'h1;
              end
            default:
                _49_ = _42_;
          endcase
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _46_;
    (* src = "libresoc.v:179984.5-179984.29" *)
    casez (\initial )
      /* src = "libresoc.v:179984.9-179984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (nia1__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = nia1__data_i;
        end
      default:
          _16_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (msr1__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = msr1__data_i;
        end
      default:
          _25_ = _16_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (sv1__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = sv1__data_i;
        end
      default:
          _32_ = _25_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (d_wr11__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = d_wr11__data_i;
        end
      default:
          _39_ = _32_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _46_ = 64'h0000000000000000;
        end
      default:
          _46_ = _39_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  assign \$1  = _57_;
  assign \$3  = _58_;
  assign \$6  = _59_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:180020.1-180491.10" *)
module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, src32__ren, src32__data_o, dest12__wen, dest12__data_i, dest22__wen, dest22__data_i, r2__data_o, r2__ren, r22__data_o, r22__ren, w2__data_i, w2__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:180021.7-180021.20" *)
  reg _00_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:180104.3-180105.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:180106.3-180107.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:180184.3-180210.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:180102.3-180103.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:180112.3-180113.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:180110.3-180111.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:180108.3-180109.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:180391.3-180420.6" *)
  reg _13_;
  (* src = "libresoc.v:180461.3-180490.6" *)
  reg _14_;
  (* src = "libresoc.v:180251.3-180280.6" *)
  reg _15_;
  (* src = "libresoc.v:180321.3-180350.6" *)
  reg _16_;
  (* src = "libresoc.v:180154.3-180183.6" *)
  reg _17_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:180046.13-180046.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:180053.13-180053.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:180184.3-180210.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:180059.13-180059.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:180064.13-180064.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:180071.13-180071.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:180078.13-180078.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:180391.3-180420.6" *)
  reg _30_;
  (* src = "libresoc.v:180461.3-180490.6" *)
  reg _31_;
  (* src = "libresoc.v:180251.3-180280.6" *)
  reg _32_;
  (* src = "libresoc.v:180321.3-180350.6" *)
  reg _33_;
  (* src = "libresoc.v:180154.3-180183.6" *)
  reg _34_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:180184.3-180210.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:180391.3-180420.6" *)
  reg _41_;
  (* src = "libresoc.v:180461.3-180490.6" *)
  reg _42_;
  (* src = "libresoc.v:180251.3-180280.6" *)
  reg _43_;
  (* src = "libresoc.v:180321.3-180350.6" *)
  reg _44_;
  (* src = "libresoc.v:180154.3-180183.6" *)
  reg _45_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:180184.3-180210.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:180391.3-180420.6" *)
  reg _52_;
  (* src = "libresoc.v:180461.3-180490.6" *)
  reg _53_;
  (* src = "libresoc.v:180251.3-180280.6" *)
  reg _54_;
  (* src = "libresoc.v:180321.3-180350.6" *)
  reg _55_;
  (* src = "libresoc.v:180154.3-180183.6" *)
  reg _56_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:180184.3-180210.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:180391.3-180420.6" *)
  reg _63_;
  (* src = "libresoc.v:180461.3-180490.6" *)
  reg _64_;
  (* src = "libresoc.v:180251.3-180280.6" *)
  reg _65_;
  (* src = "libresoc.v:180321.3-180350.6" *)
  reg _66_;
  (* src = "libresoc.v:180154.3-180183.6" *)
  reg _67_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:180421.3-180460.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:180351.3-180390.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:180114.3-180153.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:180211.3-180250.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:180281.3-180320.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:180097.17-180097.104" *)
  wire _78_;
  (* src = "libresoc.v:180098.18-180098.105" *)
  wire _79_;
  (* src = "libresoc.v:180099.17-180099.100" *)
  wire _80_;
  (* src = "libresoc.v:180100.17-180100.103" *)
  wire _81_;
  (* src = "libresoc.v:180101.17-180101.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest12__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest22__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest22__wen;
  (* src = "libresoc.v:180021.7-180021.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r22__data_o;
  reg [3:0] r22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r22__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r2__data_o;
  reg [3:0] r2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r2__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r2__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src12__data_o;
  reg [3:0] src12__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src12__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src12__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src22__data_o;
  reg [3:0] src22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src22__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src32__data_o;
  reg [3:0] src32__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src32__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src32__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r22__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r2__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src12__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src22__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src32__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r22__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r22__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r2__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r2__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src32__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src32__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src22__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src22__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src12__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src12__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:180115.5-180115.29" *)
    casez (\initial )
      /* src = "libresoc.v:180115.9-180115.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src12__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest12__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest22__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w2__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src12__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:180155.5-180155.29" *)
    casez (\initial )
      /* src = "libresoc.v:180155.9-180155.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src12__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:180185.5-180185.29" *)
    casez (\initial )
      /* src = "libresoc.v:180185.9-180185.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest12__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest12__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest22__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest22__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w2__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w2__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:180212.5-180212.29" *)
    casez (\initial )
      /* src = "libresoc.v:180212.9-180212.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest12__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest22__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w2__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src22__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:180252.5-180252.29" *)
    casez (\initial )
      /* src = "libresoc.v:180252.9-180252.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:180282.5-180282.29" *)
    casez (\initial )
      /* src = "libresoc.v:180282.9-180282.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src32__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest12__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest22__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w2__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src32__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:180322.5-180322.29" *)
    casez (\initial )
      /* src = "libresoc.v:180322.9-180322.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src32__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:180352.5-180352.29" *)
    casez (\initial )
      /* src = "libresoc.v:180352.9-180352.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest12__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest22__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w2__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r2__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:180392.5-180392.29" *)
    casez (\initial )
      /* src = "libresoc.v:180392.9-180392.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:180422.5-180422.29" *)
    casez (\initial )
      /* src = "libresoc.v:180422.9-180422.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest12__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest22__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w2__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r22__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:180462.5-180462.29" *)
    casez (\initial )
      /* src = "libresoc.v:180462.9-180462.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.xer.reg_2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:180495.1-180940.10" *)
module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, src32__ren, src32__data_o, dest12__wen, dest12__data_i, dest22__wen, dest22__data_i, dest32__wen, dest32__data_i, r2__data_o, r2__ren, w2__data_i, w2__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:180496.7-180496.20" *)
  reg _00_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:180571.3-180572.37" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _03_;
  (* src = "libresoc.v:180569.3-180570.25" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _05_;
  (* src = "libresoc.v:180577.3-180578.43" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:180575.3-180576.43" *)
  reg [1:0] _08_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:180573.3-180574.43" *)
  reg [1:0] _10_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _11_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _12_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _13_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _14_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:180523.13-180523.30" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:180529.13-180529.25" *)
  reg [1:0] _18_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _19_;
  (* src = "libresoc.v:180534.13-180534.33" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:180541.13-180541.33" *)
  reg [1:0] _22_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _23_;
  (* src = "libresoc.v:180548.13-180548.33" *)
  reg [1:0] _24_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _25_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _26_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _27_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _28_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _29_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _30_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _31_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _33_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _34_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _35_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _36_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _37_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _38_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _40_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _41_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _42_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _43_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _44_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _45_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _46_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _47_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _48_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _49_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _50_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _51_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _52_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _53_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _54_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _55_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _56_;
  (* src = "libresoc.v:180907.3-180939.6" *)
  reg [1:0] _57_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _58_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _59_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _60_;
  (* src = "libresoc.v:180871.3-180906.6" *)
  reg _61_;
  (* src = "libresoc.v:180707.3-180742.6" *)
  reg _62_;
  (* src = "libresoc.v:180789.3-180824.6" *)
  reg _63_;
  (* src = "libresoc.v:180625.3-180660.6" *)
  reg _64_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _65_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _66_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _67_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _68_;
  (* src = "libresoc.v:180825.3-180870.6" *)
  reg [1:0] _69_;
  (* src = "libresoc.v:180579.3-180624.6" *)
  reg [1:0] _70_;
  (* src = "libresoc.v:180661.3-180706.6" *)
  reg [1:0] _71_;
  (* src = "libresoc.v:180743.3-180788.6" *)
  reg [1:0] _72_;
  (* src = "libresoc.v:180565.17-180565.104" *)
  wire _73_;
  (* src = "libresoc.v:180566.17-180566.100" *)
  wire _74_;
  (* src = "libresoc.v:180567.17-180567.103" *)
  wire _75_;
  (* src = "libresoc.v:180568.17-180568.103" *)
  wire _76_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest12__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest22__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest22__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] dest32__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest32__wen;
  (* src = "libresoc.v:180496.7-180496.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] r2__data_o;
  reg [1:0] r2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \r2__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r2__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [1:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src12__data_o;
  reg [1:0] src12__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src12__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src12__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src22__data_o;
  reg [1:0] src22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src22__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src32__data_o;
  reg [1:0] src32__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [1:0] \src32__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src32__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] w2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _73_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _74_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _75_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _76_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _16_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      r2__data_o <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _20_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src12__data_o <= _20_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src22__data_o <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _24_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src32__data_o <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r2__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r2__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src32__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src32__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src22__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src22__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \src12__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src12__data_o <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _70_;
    (* src = "libresoc.v:180580.5-180580.29" *)
    casez (\initial )
      /* src = "libresoc.v:180580.9-180580.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src12__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _19_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = dest12__data_i;
              end
            default:
                _31_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest22__data_i;
              end
            default:
                _40_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest32__data_i;
              end
            default:
                _49_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w2__data_i;
              end
            default:
                _58_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = \reg ;
              end
            default:
                _66_ = _58_;
          endcase
        end
      default:
          _19_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _70_ = 2'h0;
        end
      default:
          _70_ = _19_;
    endcase
  end
  always @* begin
      \src12__data_o$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _28_;
    (* src = "libresoc.v:180626.5-180626.29" *)
    casez (\initial )
      /* src = "libresoc.v:180626.9-180626.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src12__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = 1'h1;
              end
            default:
                _37_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = 1'h1;
              end
            default:
                _46_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _55_;
          endcase
        end
      default:
          _28_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _71_;
    (* src = "libresoc.v:180662.5-180662.29" *)
    casez (\initial )
      /* src = "libresoc.v:180662.9-180662.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _32_ = dest12__data_i;
              end
            default:
                _32_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = dest22__data_i;
              end
            default:
                _41_ = _32_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest32__data_i;
              end
            default:
                _50_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _59_ = w2__data_i;
              end
            default:
                _59_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = \reg ;
              end
            default:
                _67_ = _59_;
          endcase
        end
      default:
          _21_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _71_ = 2'h0;
        end
      default:
          _71_ = _21_;
    endcase
  end
  always @* begin
      \src22__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _26_;
    (* src = "libresoc.v:180708.5-180708.29" *)
    casez (\initial )
      /* src = "libresoc.v:180708.9-180708.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src22__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _62_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = 1'h1;
              end
            default:
                _62_ = _53_;
          endcase
        end
      default:
          _26_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _72_;
    (* src = "libresoc.v:180744.5-180744.29" *)
    casez (\initial )
      /* src = "libresoc.v:180744.9-180744.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src32__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _23_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = dest12__data_i;
              end
            default:
                _33_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = dest22__data_i;
              end
            default:
                _42_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest32__data_i;
              end
            default:
                _51_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w2__data_i;
              end
            default:
                _60_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _60_;
          endcase
        end
      default:
          _23_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _72_ = 2'h0;
        end
      default:
          _72_ = _23_;
    endcase
  end
  always @* begin
      \src32__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _27_;
    (* src = "libresoc.v:180790.5-180790.29" *)
    casez (\initial )
      /* src = "libresoc.v:180790.9-180790.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src32__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _27_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _54_;
          endcase
        end
      default:
          _27_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _69_;
    (* src = "libresoc.v:180826.5-180826.29" *)
    casez (\initial )
      /* src = "libresoc.v:180826.9-180826.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = dest12__data_i;
              end
            default:
                _29_ = 2'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest22__data_i;
              end
            default:
                _38_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest32__data_i;
              end
            default:
                _47_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = w2__data_i;
              end
            default:
                _56_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = \reg ;
              end
            default:
                _65_ = _56_;
          endcase
        end
      default:
          _15_ = 2'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _69_ = 2'h0;
        end
      default:
          _69_ = _15_;
    endcase
  end
  always @* begin
      \r2__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _25_;
    (* src = "libresoc.v:180872.5-180872.29" *)
    casez (\initial )
      /* src = "libresoc.v:180872.9-180872.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = _61_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest22__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest32__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = 1'h1;
              end
            default:
                _61_ = _52_;
          endcase
        end
      default:
          _25_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _57_;
    (* src = "libresoc.v:180908.5-180908.29" *)
    casez (\initial )
      /* src = "libresoc.v:180908.9-180908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest12__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = dest12__data_i;
        end
      default:
          _17_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest22__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = dest22__data_i;
        end
      default:
          _30_ = _17_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest32__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = dest32__data_i;
        end
      default:
          _39_ = _30_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w2__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w2__data_i;
        end
      default:
          _48_ = _39_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _57_ = 2'h0;
        end
      default:
          _57_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _03_;
  end
  assign \$9  = _73_;
  assign \$1  = _74_;
  assign \$3  = _75_;
  assign \$6  = _76_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.state.reg_2" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:180944.1-181293.10" *)
module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_o, sv2__ren, sv2__data_o, nia2__wen, nia2__data_i, msr2__wen, msr2__data_i, sv2__wen, sv2__data_i, d_wr12__wen, d_wr12__data_i, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:181012.3-181013.41" *)
  reg [63:0] _01_;
  (* src = "libresoc.v:180945.7-180945.20" *)
  reg _02_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:181010.3-181011.41" *)
  reg [63:0] _04_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:181006.3-181007.25" *)
  reg [63:0] _06_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:181008.3-181009.39" *)
  reg [63:0] _08_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _09_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _10_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _11_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:180954.14-180954.49" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:180971.14-180971.49" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:180983.14-180983.42" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:180990.14-180990.48" *)
  reg [63:0] _19_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _20_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _21_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _22_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _23_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _24_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _26_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _27_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _28_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _29_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _30_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _31_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _32_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _33_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _34_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _35_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _36_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _37_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _38_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _39_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _40_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _41_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _42_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _43_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _44_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _45_;
  (* src = "libresoc.v:181260.3-181292.6" *)
  reg [63:0] _46_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _47_;
  (* src = "libresoc.v:181142.3-181177.6" *)
  reg _48_;
  (* src = "libresoc.v:181224.3-181259.6" *)
  reg _49_;
  (* src = "libresoc.v:181060.3-181095.6" *)
  reg _50_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _51_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _52_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _53_;
  (* src = "libresoc.v:181014.3-181059.6" *)
  reg [63:0] _54_;
  (* src = "libresoc.v:181096.3-181141.6" *)
  reg [63:0] _55_;
  (* src = "libresoc.v:181178.3-181223.6" *)
  reg [63:0] _56_;
  (* src = "libresoc.v:181003.17-181003.100" *)
  wire _57_;
  (* src = "libresoc.v:181004.17-181004.103" *)
  wire _58_;
  (* src = "libresoc.v:181005.17-181005.103" *)
  wire _59_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] cia2__data_o;
  reg [63:0] cia2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \cia2__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input cia2__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] d_wr12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input d_wr12__wen;
  (* src = "libresoc.v:180945.7-180945.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] msr2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] msr2__data_o;
  reg [63:0] msr2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \msr2__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input msr2__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] nia2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input nia2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [63:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] sv2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] sv2__data_o;
  reg [63:0] sv2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \sv2__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input sv2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _57_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _58_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _59_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      cia2__data_o <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      msr2__data_o <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      \reg  <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      sv2__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \sv2__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      sv2__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \msr2__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      msr2__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = \cia2__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      cia2__data_o <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _54_;
    (* src = "libresoc.v:181015.5-181015.29" *)
    casez (\initial )
      /* src = "libresoc.v:181015.9-181015.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = _51_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _23_ = nia2__data_i;
              end
            default:
                _23_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _30_ = msr2__data_i;
              end
            default:
                _30_ = _23_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _37_ = sv2__data_i;
              end
            default:
                _37_ = _30_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = d_wr12__data_i;
              end
            default:
                _44_ = _37_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = \reg ;
              end
            default:
                _51_ = _44_;
          endcase
        end
      default:
          _12_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _54_ = 64'h0000000000000000;
        end
      default:
          _54_ = _12_;
    endcase
  end
  always @* begin
      \cia2__data_o$next  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _22_;
    (* src = "libresoc.v:181061.5-181061.29" *)
    casez (\initial )
      /* src = "libresoc.v:181061.9-181061.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (cia2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = _50_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _29_ = 1'h1;
              end
            default:
                _29_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = 1'h1;
              end
            default:
                _36_ = _29_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = 1'h1;
              end
            default:
                _50_ = _43_;
          endcase
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _55_;
    (* src = "libresoc.v:181097.5-181097.29" *)
    casez (\initial )
      /* src = "libresoc.v:181097.9-181097.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = _52_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _24_ = nia2__data_i;
              end
            default:
                _24_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _31_ = msr2__data_i;
              end
            default:
                _31_ = _24_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = sv2__data_i;
              end
            default:
                _38_ = _31_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = d_wr12__data_i;
              end
            default:
                _45_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = \reg ;
              end
            default:
                _52_ = _45_;
          endcase
        end
      default:
          _14_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _55_ = 64'h0000000000000000;
        end
      default:
          _55_ = _14_;
    endcase
  end
  always @* begin
      \msr2__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _20_;
    (* src = "libresoc.v:181143.5-181143.29" *)
    casez (\initial )
      /* src = "libresoc.v:181143.9-181143.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (msr2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _48_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _27_ = 1'h1;
              end
            default:
                _27_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _34_ = 1'h1;
              end
            default:
                _34_ = _27_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = _34_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _48_ = 1'h1;
              end
            default:
                _48_ = _41_;
          endcase
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _56_;
    (* src = "libresoc.v:181179.5-181179.29" *)
    casez (\initial )
      /* src = "libresoc.v:181179.9-181179.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _53_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _26_ = nia2__data_i;
              end
            default:
                _26_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _33_ = msr2__data_i;
              end
            default:
                _33_ = _26_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = sv2__data_i;
              end
            default:
                _40_ = _33_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = d_wr12__data_i;
              end
            default:
                _47_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = \reg ;
              end
            default:
                _53_ = _47_;
          endcase
        end
      default:
          _18_ = 64'h0000000000000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _56_ = 64'h0000000000000000;
        end
      default:
          _56_ = _18_;
    endcase
  end
  always @* begin
      \sv2__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _21_;
    (* src = "libresoc.v:181225.5-181225.29" *)
    casez (\initial )
      /* src = "libresoc.v:181225.9-181225.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (sv2__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _21_ = _49_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (nia2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _28_ = 1'h1;
              end
            default:
                _28_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (msr2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = 1'h1;
              end
            default:
                _35_ = _28_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (sv2__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (d_wr12__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = 1'h1;
              end
            default:
                _49_ = _42_;
          endcase
        end
      default:
          _21_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _46_;
    (* src = "libresoc.v:181261.5-181261.29" *)
    casez (\initial )
      /* src = "libresoc.v:181261.9-181261.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (nia2__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = nia2__data_i;
        end
      default:
          _16_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (msr2__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _25_ = msr2__data_i;
        end
      default:
          _25_ = _16_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (sv2__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = sv2__data_i;
        end
      default:
          _32_ = _25_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (d_wr12__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = d_wr12__data_i;
        end
      default:
          _39_ = _32_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _46_ = 64'h0000000000000000;
        end
      default:
          _46_ = _39_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  assign \$1  = _57_;
  assign \$3  = _58_;
  assign \$6  = _59_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_3" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:181297.1-181768.10" *)
module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, src33__ren, src33__data_o, dest13__wen, dest13__data_i, dest23__wen, dest23__data_i, r3__data_o, r3__ren, r23__data_o, r23__ren, w3__data_i, w3__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:181298.7-181298.20" *)
  reg _00_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:181381.3-181382.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:181383.3-181384.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:181461.3-181487.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:181379.3-181380.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:181389.3-181390.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:181387.3-181388.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:181385.3-181386.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:181668.3-181697.6" *)
  reg _13_;
  (* src = "libresoc.v:181738.3-181767.6" *)
  reg _14_;
  (* src = "libresoc.v:181528.3-181557.6" *)
  reg _15_;
  (* src = "libresoc.v:181598.3-181627.6" *)
  reg _16_;
  (* src = "libresoc.v:181431.3-181460.6" *)
  reg _17_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:181323.13-181323.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:181330.13-181330.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:181461.3-181487.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:181336.13-181336.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:181341.13-181341.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:181348.13-181348.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:181355.13-181355.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:181668.3-181697.6" *)
  reg _30_;
  (* src = "libresoc.v:181738.3-181767.6" *)
  reg _31_;
  (* src = "libresoc.v:181528.3-181557.6" *)
  reg _32_;
  (* src = "libresoc.v:181598.3-181627.6" *)
  reg _33_;
  (* src = "libresoc.v:181431.3-181460.6" *)
  reg _34_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:181461.3-181487.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:181668.3-181697.6" *)
  reg _41_;
  (* src = "libresoc.v:181738.3-181767.6" *)
  reg _42_;
  (* src = "libresoc.v:181528.3-181557.6" *)
  reg _43_;
  (* src = "libresoc.v:181598.3-181627.6" *)
  reg _44_;
  (* src = "libresoc.v:181431.3-181460.6" *)
  reg _45_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:181461.3-181487.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:181668.3-181697.6" *)
  reg _52_;
  (* src = "libresoc.v:181738.3-181767.6" *)
  reg _53_;
  (* src = "libresoc.v:181528.3-181557.6" *)
  reg _54_;
  (* src = "libresoc.v:181598.3-181627.6" *)
  reg _55_;
  (* src = "libresoc.v:181431.3-181460.6" *)
  reg _56_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:181461.3-181487.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:181668.3-181697.6" *)
  reg _63_;
  (* src = "libresoc.v:181738.3-181767.6" *)
  reg _64_;
  (* src = "libresoc.v:181528.3-181557.6" *)
  reg _65_;
  (* src = "libresoc.v:181598.3-181627.6" *)
  reg _66_;
  (* src = "libresoc.v:181431.3-181460.6" *)
  reg _67_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:181698.3-181737.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:181628.3-181667.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:181391.3-181430.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:181488.3-181527.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:181558.3-181597.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:181374.17-181374.104" *)
  wire _78_;
  (* src = "libresoc.v:181375.18-181375.105" *)
  wire _79_;
  (* src = "libresoc.v:181376.17-181376.100" *)
  wire _80_;
  (* src = "libresoc.v:181377.17-181377.103" *)
  wire _81_;
  (* src = "libresoc.v:181378.17-181378.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest13__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest13__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest23__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest23__wen;
  (* src = "libresoc.v:181298.7-181298.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r23__data_o;
  reg [3:0] r23__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r23__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r23__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r3__data_o;
  reg [3:0] r3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r3__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r3__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src13__data_o;
  reg [3:0] src13__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src13__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src13__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src23__data_o;
  reg [3:0] src23__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src23__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src23__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src33__data_o;
  reg [3:0] src33__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src33__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src33__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w3__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w3__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r23__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r3__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src13__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src23__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src33__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r23__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r23__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r3__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r3__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src33__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src33__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src23__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src23__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src13__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src13__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:181392.5-181392.29" *)
    casez (\initial )
      /* src = "libresoc.v:181392.9-181392.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src13__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest13__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest23__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w3__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src13__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:181432.5-181432.29" *)
    casez (\initial )
      /* src = "libresoc.v:181432.9-181432.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src13__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:181462.5-181462.29" *)
    casez (\initial )
      /* src = "libresoc.v:181462.9-181462.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest13__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest13__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest23__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest23__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w3__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w3__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:181489.5-181489.29" *)
    casez (\initial )
      /* src = "libresoc.v:181489.9-181489.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src23__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest13__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest23__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w3__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src23__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:181529.5-181529.29" *)
    casez (\initial )
      /* src = "libresoc.v:181529.9-181529.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src23__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:181559.5-181559.29" *)
    casez (\initial )
      /* src = "libresoc.v:181559.9-181559.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src33__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest13__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest23__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w3__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src33__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:181599.5-181599.29" *)
    casez (\initial )
      /* src = "libresoc.v:181599.9-181599.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src33__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:181629.5-181629.29" *)
    casez (\initial )
      /* src = "libresoc.v:181629.9-181629.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r3__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest13__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest23__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w3__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r3__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:181669.5-181669.29" *)
    casez (\initial )
      /* src = "libresoc.v:181669.9-181669.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r3__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:181699.5-181699.29" *)
    casez (\initial )
      /* src = "libresoc.v:181699.9-181699.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r23__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest13__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest23__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w3__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r23__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:181739.5-181739.29" *)
    casez (\initial )
      /* src = "libresoc.v:181739.9-181739.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r23__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest13__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest23__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w3__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_4" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:181772.1-182243.10" *)
module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, src34__ren, src34__data_o, dest14__wen, dest14__data_i, dest24__wen, dest24__data_i, r4__data_o, r4__ren, r24__data_o, r24__ren, w4__data_i, w4__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:181773.7-181773.20" *)
  reg _00_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:181856.3-181857.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:181858.3-181859.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:181936.3-181962.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:181854.3-181855.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:181864.3-181865.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:181862.3-181863.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:181860.3-181861.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:182143.3-182172.6" *)
  reg _13_;
  (* src = "libresoc.v:182213.3-182242.6" *)
  reg _14_;
  (* src = "libresoc.v:182003.3-182032.6" *)
  reg _15_;
  (* src = "libresoc.v:182073.3-182102.6" *)
  reg _16_;
  (* src = "libresoc.v:181906.3-181935.6" *)
  reg _17_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:181798.13-181798.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:181805.13-181805.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:181936.3-181962.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:181811.13-181811.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:181816.13-181816.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:181823.13-181823.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:181830.13-181830.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:182143.3-182172.6" *)
  reg _30_;
  (* src = "libresoc.v:182213.3-182242.6" *)
  reg _31_;
  (* src = "libresoc.v:182003.3-182032.6" *)
  reg _32_;
  (* src = "libresoc.v:182073.3-182102.6" *)
  reg _33_;
  (* src = "libresoc.v:181906.3-181935.6" *)
  reg _34_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:181936.3-181962.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:182143.3-182172.6" *)
  reg _41_;
  (* src = "libresoc.v:182213.3-182242.6" *)
  reg _42_;
  (* src = "libresoc.v:182003.3-182032.6" *)
  reg _43_;
  (* src = "libresoc.v:182073.3-182102.6" *)
  reg _44_;
  (* src = "libresoc.v:181906.3-181935.6" *)
  reg _45_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:181936.3-181962.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:182143.3-182172.6" *)
  reg _52_;
  (* src = "libresoc.v:182213.3-182242.6" *)
  reg _53_;
  (* src = "libresoc.v:182003.3-182032.6" *)
  reg _54_;
  (* src = "libresoc.v:182073.3-182102.6" *)
  reg _55_;
  (* src = "libresoc.v:181906.3-181935.6" *)
  reg _56_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:181936.3-181962.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:182143.3-182172.6" *)
  reg _63_;
  (* src = "libresoc.v:182213.3-182242.6" *)
  reg _64_;
  (* src = "libresoc.v:182003.3-182032.6" *)
  reg _65_;
  (* src = "libresoc.v:182073.3-182102.6" *)
  reg _66_;
  (* src = "libresoc.v:181906.3-181935.6" *)
  reg _67_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:182173.3-182212.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:182103.3-182142.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:181866.3-181905.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:181963.3-182002.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:182033.3-182072.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:181849.17-181849.104" *)
  wire _78_;
  (* src = "libresoc.v:181850.18-181850.105" *)
  wire _79_;
  (* src = "libresoc.v:181851.17-181851.100" *)
  wire _80_;
  (* src = "libresoc.v:181852.17-181852.103" *)
  wire _81_;
  (* src = "libresoc.v:181853.17-181853.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest14__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest14__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest24__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest24__wen;
  (* src = "libresoc.v:181773.7-181773.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r24__data_o;
  reg [3:0] r24__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r24__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r24__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r4__data_o;
  reg [3:0] r4__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r4__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r4__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src14__data_o;
  reg [3:0] src14__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src14__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src14__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src24__data_o;
  reg [3:0] src24__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src24__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src24__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src34__data_o;
  reg [3:0] src34__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src34__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src34__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w4__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w4__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r24__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r4__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src14__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src24__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src34__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r24__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r24__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r4__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r4__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src34__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src34__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src24__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src24__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src14__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src14__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:181867.5-181867.29" *)
    casez (\initial )
      /* src = "libresoc.v:181867.9-181867.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src14__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest14__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest24__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w4__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src14__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:181907.5-181907.29" *)
    casez (\initial )
      /* src = "libresoc.v:181907.9-181907.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src14__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:181937.5-181937.29" *)
    casez (\initial )
      /* src = "libresoc.v:181937.9-181937.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest14__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest14__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest24__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest24__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w4__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w4__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:181964.5-181964.29" *)
    casez (\initial )
      /* src = "libresoc.v:181964.9-181964.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src24__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest14__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest24__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w4__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src24__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:182004.5-182004.29" *)
    casez (\initial )
      /* src = "libresoc.v:182004.9-182004.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src24__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:182034.5-182034.29" *)
    casez (\initial )
      /* src = "libresoc.v:182034.9-182034.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src34__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest14__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest24__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w4__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src34__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:182074.5-182074.29" *)
    casez (\initial )
      /* src = "libresoc.v:182074.9-182074.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src34__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:182104.5-182104.29" *)
    casez (\initial )
      /* src = "libresoc.v:182104.9-182104.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r4__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest14__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest24__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w4__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r4__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:182144.5-182144.29" *)
    casez (\initial )
      /* src = "libresoc.v:182144.9-182144.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r4__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:182174.5-182174.29" *)
    casez (\initial )
      /* src = "libresoc.v:182174.9-182174.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r24__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest14__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest24__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w4__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r24__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:182214.5-182214.29" *)
    casez (\initial )
      /* src = "libresoc.v:182214.9-182214.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r24__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest14__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest24__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w4__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_5" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:182247.1-182718.10" *)
module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, src35__ren, src35__data_o, dest15__wen, dest15__data_i, dest25__wen, dest25__data_i, r5__data_o, r5__ren, r25__data_o, r25__ren, w5__data_i, w5__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:182248.7-182248.20" *)
  reg _00_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:182331.3-182332.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:182333.3-182334.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:182411.3-182437.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:182329.3-182330.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:182339.3-182340.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:182337.3-182338.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:182335.3-182336.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:182618.3-182647.6" *)
  reg _13_;
  (* src = "libresoc.v:182688.3-182717.6" *)
  reg _14_;
  (* src = "libresoc.v:182478.3-182507.6" *)
  reg _15_;
  (* src = "libresoc.v:182548.3-182577.6" *)
  reg _16_;
  (* src = "libresoc.v:182381.3-182410.6" *)
  reg _17_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:182273.13-182273.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:182280.13-182280.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:182411.3-182437.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:182286.13-182286.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:182291.13-182291.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:182298.13-182298.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:182305.13-182305.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:182618.3-182647.6" *)
  reg _30_;
  (* src = "libresoc.v:182688.3-182717.6" *)
  reg _31_;
  (* src = "libresoc.v:182478.3-182507.6" *)
  reg _32_;
  (* src = "libresoc.v:182548.3-182577.6" *)
  reg _33_;
  (* src = "libresoc.v:182381.3-182410.6" *)
  reg _34_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:182411.3-182437.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:182618.3-182647.6" *)
  reg _41_;
  (* src = "libresoc.v:182688.3-182717.6" *)
  reg _42_;
  (* src = "libresoc.v:182478.3-182507.6" *)
  reg _43_;
  (* src = "libresoc.v:182548.3-182577.6" *)
  reg _44_;
  (* src = "libresoc.v:182381.3-182410.6" *)
  reg _45_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:182411.3-182437.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:182618.3-182647.6" *)
  reg _52_;
  (* src = "libresoc.v:182688.3-182717.6" *)
  reg _53_;
  (* src = "libresoc.v:182478.3-182507.6" *)
  reg _54_;
  (* src = "libresoc.v:182548.3-182577.6" *)
  reg _55_;
  (* src = "libresoc.v:182381.3-182410.6" *)
  reg _56_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:182411.3-182437.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:182618.3-182647.6" *)
  reg _63_;
  (* src = "libresoc.v:182688.3-182717.6" *)
  reg _64_;
  (* src = "libresoc.v:182478.3-182507.6" *)
  reg _65_;
  (* src = "libresoc.v:182548.3-182577.6" *)
  reg _66_;
  (* src = "libresoc.v:182381.3-182410.6" *)
  reg _67_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:182648.3-182687.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:182578.3-182617.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:182341.3-182380.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:182438.3-182477.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:182508.3-182547.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:182324.17-182324.104" *)
  wire _78_;
  (* src = "libresoc.v:182325.18-182325.105" *)
  wire _79_;
  (* src = "libresoc.v:182326.17-182326.100" *)
  wire _80_;
  (* src = "libresoc.v:182327.17-182327.103" *)
  wire _81_;
  (* src = "libresoc.v:182328.17-182328.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest15__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest15__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest25__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest25__wen;
  (* src = "libresoc.v:182248.7-182248.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r25__data_o;
  reg [3:0] r25__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r25__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r25__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r5__data_o;
  reg [3:0] r5__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r5__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r5__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src15__data_o;
  reg [3:0] src15__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src15__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src15__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src25__data_o;
  reg [3:0] src25__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src25__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src25__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src35__data_o;
  reg [3:0] src35__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src35__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src35__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w5__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w5__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r25__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r5__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src15__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src25__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src35__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r25__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r25__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r5__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r5__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src35__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src35__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src25__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src25__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src15__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src15__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:182342.5-182342.29" *)
    casez (\initial )
      /* src = "libresoc.v:182342.9-182342.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src15__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest15__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest25__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w5__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src15__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:182382.5-182382.29" *)
    casez (\initial )
      /* src = "libresoc.v:182382.9-182382.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src15__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:182412.5-182412.29" *)
    casez (\initial )
      /* src = "libresoc.v:182412.9-182412.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest15__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest15__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest25__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest25__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w5__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w5__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:182439.5-182439.29" *)
    casez (\initial )
      /* src = "libresoc.v:182439.9-182439.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src25__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest15__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest25__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w5__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src25__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:182479.5-182479.29" *)
    casez (\initial )
      /* src = "libresoc.v:182479.9-182479.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src25__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:182509.5-182509.29" *)
    casez (\initial )
      /* src = "libresoc.v:182509.9-182509.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src35__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest15__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest25__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w5__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src35__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:182549.5-182549.29" *)
    casez (\initial )
      /* src = "libresoc.v:182549.9-182549.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src35__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:182579.5-182579.29" *)
    casez (\initial )
      /* src = "libresoc.v:182579.9-182579.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r5__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest15__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest25__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w5__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r5__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:182619.5-182619.29" *)
    casez (\initial )
      /* src = "libresoc.v:182619.9-182619.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r5__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:182649.5-182649.29" *)
    casez (\initial )
      /* src = "libresoc.v:182649.9-182649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r25__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest15__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest25__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w5__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r25__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:182689.5-182689.29" *)
    casez (\initial )
      /* src = "libresoc.v:182689.9-182689.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r25__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest15__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest25__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w5__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_6" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:182722.1-183193.10" *)
module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, src36__ren, src36__data_o, dest16__wen, dest16__data_i, dest26__wen, dest26__data_i, r6__data_o, r6__ren, r26__data_o, r26__ren, w6__data_i, w6__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:182723.7-182723.20" *)
  reg _00_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:182806.3-182807.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:182808.3-182809.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:182886.3-182912.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:182804.3-182805.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:182814.3-182815.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:182812.3-182813.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:182810.3-182811.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:183093.3-183122.6" *)
  reg _13_;
  (* src = "libresoc.v:183163.3-183192.6" *)
  reg _14_;
  (* src = "libresoc.v:182953.3-182982.6" *)
  reg _15_;
  (* src = "libresoc.v:183023.3-183052.6" *)
  reg _16_;
  (* src = "libresoc.v:182856.3-182885.6" *)
  reg _17_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:182748.13-182748.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:182755.13-182755.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:182886.3-182912.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:182761.13-182761.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:182766.13-182766.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:182773.13-182773.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:182780.13-182780.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:183093.3-183122.6" *)
  reg _30_;
  (* src = "libresoc.v:183163.3-183192.6" *)
  reg _31_;
  (* src = "libresoc.v:182953.3-182982.6" *)
  reg _32_;
  (* src = "libresoc.v:183023.3-183052.6" *)
  reg _33_;
  (* src = "libresoc.v:182856.3-182885.6" *)
  reg _34_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:182886.3-182912.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:183093.3-183122.6" *)
  reg _41_;
  (* src = "libresoc.v:183163.3-183192.6" *)
  reg _42_;
  (* src = "libresoc.v:182953.3-182982.6" *)
  reg _43_;
  (* src = "libresoc.v:183023.3-183052.6" *)
  reg _44_;
  (* src = "libresoc.v:182856.3-182885.6" *)
  reg _45_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:182886.3-182912.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:183093.3-183122.6" *)
  reg _52_;
  (* src = "libresoc.v:183163.3-183192.6" *)
  reg _53_;
  (* src = "libresoc.v:182953.3-182982.6" *)
  reg _54_;
  (* src = "libresoc.v:183023.3-183052.6" *)
  reg _55_;
  (* src = "libresoc.v:182856.3-182885.6" *)
  reg _56_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:182886.3-182912.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:183093.3-183122.6" *)
  reg _63_;
  (* src = "libresoc.v:183163.3-183192.6" *)
  reg _64_;
  (* src = "libresoc.v:182953.3-182982.6" *)
  reg _65_;
  (* src = "libresoc.v:183023.3-183052.6" *)
  reg _66_;
  (* src = "libresoc.v:182856.3-182885.6" *)
  reg _67_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:183123.3-183162.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:183053.3-183092.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:182816.3-182855.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:182913.3-182952.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:182983.3-183022.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:182799.17-182799.104" *)
  wire _78_;
  (* src = "libresoc.v:182800.18-182800.105" *)
  wire _79_;
  (* src = "libresoc.v:182801.17-182801.100" *)
  wire _80_;
  (* src = "libresoc.v:182802.17-182802.103" *)
  wire _81_;
  (* src = "libresoc.v:182803.17-182803.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest16__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest16__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest26__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest26__wen;
  (* src = "libresoc.v:182723.7-182723.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r26__data_o;
  reg [3:0] r26__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r26__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r26__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r6__data_o;
  reg [3:0] r6__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r6__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r6__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src16__data_o;
  reg [3:0] src16__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src16__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src16__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src26__data_o;
  reg [3:0] src26__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src26__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src26__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src36__data_o;
  reg [3:0] src36__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src36__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src36__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w6__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w6__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r26__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r6__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src16__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src26__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src36__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r26__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r26__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r6__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r6__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src36__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src36__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src26__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src26__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src16__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src16__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:182817.5-182817.29" *)
    casez (\initial )
      /* src = "libresoc.v:182817.9-182817.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src16__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest16__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest26__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w6__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src16__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:182857.5-182857.29" *)
    casez (\initial )
      /* src = "libresoc.v:182857.9-182857.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src16__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:182887.5-182887.29" *)
    casez (\initial )
      /* src = "libresoc.v:182887.9-182887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest16__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest16__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest26__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest26__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w6__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w6__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:182914.5-182914.29" *)
    casez (\initial )
      /* src = "libresoc.v:182914.9-182914.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src26__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest16__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest26__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w6__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src26__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:182954.5-182954.29" *)
    casez (\initial )
      /* src = "libresoc.v:182954.9-182954.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src26__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:182984.5-182984.29" *)
    casez (\initial )
      /* src = "libresoc.v:182984.9-182984.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src36__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest16__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest26__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w6__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src36__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:183024.5-183024.29" *)
    casez (\initial )
      /* src = "libresoc.v:183024.9-183024.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src36__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:183054.5-183054.29" *)
    casez (\initial )
      /* src = "libresoc.v:183054.9-183054.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r6__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest16__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest26__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w6__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r6__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:183094.5-183094.29" *)
    casez (\initial )
      /* src = "libresoc.v:183094.9-183094.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r6__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:183124.5-183124.29" *)
    casez (\initial )
      /* src = "libresoc.v:183124.9-183124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r26__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest16__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest26__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w6__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r26__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:183164.5-183164.29" *)
    casez (\initial )
      /* src = "libresoc.v:183164.9-183164.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r26__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest16__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest26__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w6__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.cr.reg_7" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183197.1-183668.10" *)
module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, src37__ren, src37__data_o, dest17__wen, dest17__data_i, dest27__wen, dest27__data_i, r7__data_o, r7__ren, r27__data_o, r27__ren, w7__data_i, w7__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183198.7-183198.20" *)
  reg _00_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:183281.3-183282.39" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:183283.3-183284.37" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:183361.3-183387.6" *)
  reg [3:0] _05_;
  (* src = "libresoc.v:183279.3-183280.25" *)
  reg [3:0] _06_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _07_;
  (* src = "libresoc.v:183289.3-183290.43" *)
  reg [3:0] _08_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:183287.3-183288.43" *)
  reg [3:0] _10_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _11_;
  (* src = "libresoc.v:183285.3-183286.43" *)
  reg [3:0] _12_;
  (* src = "libresoc.v:183568.3-183597.6" *)
  reg _13_;
  (* src = "libresoc.v:183638.3-183667.6" *)
  reg _14_;
  (* src = "libresoc.v:183428.3-183457.6" *)
  reg _15_;
  (* src = "libresoc.v:183498.3-183527.6" *)
  reg _16_;
  (* src = "libresoc.v:183331.3-183360.6" *)
  reg _17_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _18_;
  (* src = "libresoc.v:183223.13-183223.31" *)
  reg [3:0] _19_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _20_;
  (* src = "libresoc.v:183230.13-183230.30" *)
  reg [3:0] _21_;
  (* src = "libresoc.v:183361.3-183387.6" *)
  reg [3:0] _22_;
  (* src = "libresoc.v:183236.13-183236.25" *)
  reg [3:0] _23_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _24_;
  (* src = "libresoc.v:183241.13-183241.33" *)
  reg [3:0] _25_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _26_;
  (* src = "libresoc.v:183248.13-183248.33" *)
  reg [3:0] _27_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _28_;
  (* src = "libresoc.v:183255.13-183255.33" *)
  reg [3:0] _29_;
  (* src = "libresoc.v:183568.3-183597.6" *)
  reg _30_;
  (* src = "libresoc.v:183638.3-183667.6" *)
  reg _31_;
  (* src = "libresoc.v:183428.3-183457.6" *)
  reg _32_;
  (* src = "libresoc.v:183498.3-183527.6" *)
  reg _33_;
  (* src = "libresoc.v:183331.3-183360.6" *)
  reg _34_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _35_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _36_;
  (* src = "libresoc.v:183361.3-183387.6" *)
  reg [3:0] _37_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _38_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _39_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _40_;
  (* src = "libresoc.v:183568.3-183597.6" *)
  reg _41_;
  (* src = "libresoc.v:183638.3-183667.6" *)
  reg _42_;
  (* src = "libresoc.v:183428.3-183457.6" *)
  reg _43_;
  (* src = "libresoc.v:183498.3-183527.6" *)
  reg _44_;
  (* src = "libresoc.v:183331.3-183360.6" *)
  reg _45_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _46_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _47_;
  (* src = "libresoc.v:183361.3-183387.6" *)
  reg [3:0] _48_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _49_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _50_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _51_;
  (* src = "libresoc.v:183568.3-183597.6" *)
  reg _52_;
  (* src = "libresoc.v:183638.3-183667.6" *)
  reg _53_;
  (* src = "libresoc.v:183428.3-183457.6" *)
  reg _54_;
  (* src = "libresoc.v:183498.3-183527.6" *)
  reg _55_;
  (* src = "libresoc.v:183331.3-183360.6" *)
  reg _56_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _57_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _58_;
  (* src = "libresoc.v:183361.3-183387.6" *)
  reg [3:0] _59_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _60_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _61_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _62_;
  (* src = "libresoc.v:183568.3-183597.6" *)
  reg _63_;
  (* src = "libresoc.v:183638.3-183667.6" *)
  reg _64_;
  (* src = "libresoc.v:183428.3-183457.6" *)
  reg _65_;
  (* src = "libresoc.v:183498.3-183527.6" *)
  reg _66_;
  (* src = "libresoc.v:183331.3-183360.6" *)
  reg _67_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _68_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _69_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _70_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _71_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _72_;
  (* src = "libresoc.v:183598.3-183637.6" *)
  reg [3:0] _73_;
  (* src = "libresoc.v:183528.3-183567.6" *)
  reg [3:0] _74_;
  (* src = "libresoc.v:183291.3-183330.6" *)
  reg [3:0] _75_;
  (* src = "libresoc.v:183388.3-183427.6" *)
  reg [3:0] _76_;
  (* src = "libresoc.v:183458.3-183497.6" *)
  reg [3:0] _77_;
  (* src = "libresoc.v:183274.17-183274.104" *)
  wire _78_;
  (* src = "libresoc.v:183275.18-183275.105" *)
  wire _79_;
  (* src = "libresoc.v:183276.17-183276.100" *)
  wire _80_;
  (* src = "libresoc.v:183277.17-183277.103" *)
  wire _81_;
  (* src = "libresoc.v:183278.17-183278.103" *)
  wire _82_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest17__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest17__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] dest27__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input dest27__wen;
  (* src = "libresoc.v:183198.7-183198.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r27__data_o;
  reg [3:0] r27__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r27__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r27__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] r7__data_o;
  reg [3:0] r7__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \r7__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input r7__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" *)
  reg [3:0] \reg$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src17__data_o;
  reg [3:0] src17__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src17__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src17__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src27__data_o;
  reg [3:0] src27__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src27__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src27__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [3:0] src37__data_o;
  reg [3:0] src37__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [3:0] \src37__data_o$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input src37__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] w7__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input w7__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg wr_detect;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" *)
  reg \wr_detect$7 ;
  assign _78_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$10 ;
  assign _79_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$13 ;
  assign _80_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wr_detect;
  assign _81_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$4 ;
  assign _82_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) \wr_detect$7 ;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _19_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r27__data_o <= _19_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      r7__data_o <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _23_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      \reg  <= _23_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src17__data_o <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _27_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src27__data_o <= _27_;
  end
  always @* begin
    if (\initial ) begin end
    _29_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src37__data_o <= _29_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = \reg$next ;
  end
  always @(posedge coresync_clk) begin
      \reg  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \r27__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r27__data_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \r7__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      r7__data_o <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = \src37__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src37__data_o <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \src27__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src27__data_o <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \src17__data_o$next ;
  end
  always @(posedge coresync_clk) begin
      src17__data_o <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _75_;
    (* src = "libresoc.v:183292.5-183292.29" *)
    casez (\initial )
      /* src = "libresoc.v:183292.9-183292.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src17__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _24_ = _70_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _38_ = dest17__data_i;
              end
            default:
                _38_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _49_ = dest27__data_i;
              end
            default:
                _49_ = _38_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _60_ = w7__data_i;
              end
            default:
                _60_ = _49_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$1 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _70_ = \reg ;
              end
            default:
                _70_ = _60_;
          endcase
        end
      default:
          _24_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _75_ = 4'h0;
        end
      default:
          _75_ = _24_;
    endcase
  end
  always @* begin
      \src17__data_o$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _17_ = _34_;
    (* src = "libresoc.v:183332.5-183332.29" *)
    casez (\initial )
      /* src = "libresoc.v:183332.9-183332.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src17__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _34_ = _67_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _45_ = 1'h1;
              end
            default:
                _45_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _56_ = 1'h1;
              end
            default:
                _56_ = _45_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _67_ = 1'h1;
              end
            default:
                _67_ = _56_;
          endcase
        end
      default:
          _34_ = 1'h0;
    endcase
  end
  always @* begin
      wr_detect <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _59_;
    (* src = "libresoc.v:183362.5-183362.29" *)
    casez (\initial )
      /* src = "libresoc.v:183362.9-183362.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest17__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _22_ = dest17__data_i;
        end
      default:
          _22_ = \reg ;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (dest27__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _37_ = dest27__data_i;
        end
      default:
          _37_ = _22_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" *)
    casez (w7__wen)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = w7__data_i;
        end
      default:
          _48_ = _37_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = 4'h0;
        end
      default:
          _59_ = _48_;
    endcase
  end
  always @* begin
      \reg$next  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _76_;
    (* src = "libresoc.v:183389.5-183389.29" *)
    casez (\initial )
      /* src = "libresoc.v:183389.9-183389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src27__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _71_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _39_ = dest17__data_i;
              end
            default:
                _39_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _50_ = dest27__data_i;
              end
            default:
                _50_ = _39_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _61_ = w7__data_i;
              end
            default:
                _61_ = _50_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$3 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _71_ = \reg ;
              end
            default:
                _71_ = _61_;
          endcase
        end
      default:
          _26_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _76_ = 4'h0;
        end
      default:
          _76_ = _26_;
    endcase
  end
  always @* begin
      \src27__data_o$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _32_;
    (* src = "libresoc.v:183429.5-183429.29" *)
    casez (\initial )
      /* src = "libresoc.v:183429.9-183429.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src27__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = _65_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _43_ = 1'h1;
              end
            default:
                _43_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _54_ = 1'h1;
              end
            default:
                _54_ = _43_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _65_ = 1'h1;
              end
            default:
                _65_ = _54_;
          endcase
        end
      default:
          _32_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$4  <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _77_;
    (* src = "libresoc.v:183459.5-183459.29" *)
    casez (\initial )
      /* src = "libresoc.v:183459.9-183459.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src37__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _28_ = _72_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _40_ = dest17__data_i;
              end
            default:
                _40_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = dest27__data_i;
              end
            default:
                _51_ = _40_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _62_ = w7__data_i;
              end
            default:
                _62_ = _51_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$6 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _72_ = \reg ;
              end
            default:
                _72_ = _62_;
          endcase
        end
      default:
          _28_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _77_ = 4'h0;
        end
      default:
          _77_ = _28_;
    endcase
  end
  always @* begin
      \src37__data_o$next  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _16_ = _33_;
    (* src = "libresoc.v:183499.5-183499.29" *)
    casez (\initial )
      /* src = "libresoc.v:183499.9-183499.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (src37__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _33_ = _66_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _44_ = 1'h1;
              end
            default:
                _44_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _55_ = 1'h1;
              end
            default:
                _55_ = _44_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _66_ = 1'h1;
              end
            default:
                _66_ = _55_;
          endcase
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$7  <= _16_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _74_;
    (* src = "libresoc.v:183529.5-183529.29" *)
    casez (\initial )
      /* src = "libresoc.v:183529.9-183529.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r7__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _20_ = _69_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _36_ = dest17__data_i;
              end
            default:
                _36_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _47_ = dest27__data_i;
              end
            default:
                _47_ = _36_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _58_ = w7__data_i;
              end
            default:
                _58_ = _47_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$9 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _69_ = \reg ;
              end
            default:
                _69_ = _58_;
          endcase
        end
      default:
          _20_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _74_ = 4'h0;
        end
      default:
          _74_ = _20_;
    endcase
  end
  always @* begin
      \r7__data_o$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = _30_;
    (* src = "libresoc.v:183569.5-183569.29" *)
    casez (\initial )
      /* src = "libresoc.v:183569.9-183569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r7__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _30_ = _63_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _41_ = 1'h1;
              end
            default:
                _41_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _52_ = 1'h1;
              end
            default:
                _52_ = _41_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _63_ = 1'h1;
              end
            default:
                _63_ = _52_;
          endcase
        end
      default:
          _30_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$10  <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _73_;
    (* src = "libresoc.v:183599.5-183599.29" *)
    casez (\initial )
      /* src = "libresoc.v:183599.9-183599.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r27__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = _68_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _35_ = dest17__data_i;
              end
            default:
                _35_ = 4'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _46_ = dest27__data_i;
              end
            default:
                _46_ = _35_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _57_ = w7__data_i;
              end
            default:
                _57_ = _46_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *)
          casez (\$12 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _68_ = \reg ;
              end
            default:
                _68_ = _57_;
          endcase
        end
      default:
          _18_ = 4'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _73_ = 4'h0;
        end
      default:
          _73_ = _18_;
    endcase
  end
  always @* begin
      \r27__data_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _31_;
    (* src = "libresoc.v:183639.5-183639.29" *)
    casez (\initial )
      /* src = "libresoc.v:183639.9-183639.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" *)
    casez (r27__ren)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _31_ = _64_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest17__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _42_ = 1'h1;
              end
            default:
                _42_ = 1'h0;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (dest27__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _53_ = 1'h1;
              end
            default:
                _53_ = _42_;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" *)
          casez (w7__wen)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _64_ = 1'h1;
              end
            default:
                _64_ = _53_;
          endcase
        end
      default:
          _31_ = 1'h0;
    endcase
  end
  always @* begin
      \wr_detect$13  <= _14_;
  end
  assign \$9  = _78_;
  assign \$12  = _79_;
  assign \$1  = _80_;
  assign \$3  = _81_;
  assign \$6  = _82_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183672.1-183730.10" *)
module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183673.7-183673.20" *)
  reg _00_;
  (* src = "libresoc.v:183718.3-183726.6" *)
  reg [4:0] _01_;
  (* src = "libresoc.v:183716.3-183717.27" *)
  reg [4:0] _02_;
  (* src = "libresoc.v:183718.3-183726.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:183695.13-183695.26" *)
  reg [4:0] _04_;
  (* src = "libresoc.v:183708.17-183708.96" *)
  wire [4:0] _05_;
  (* src = "libresoc.v:183713.17-183713.96" *)
  wire [4:0] _06_;
  (* src = "libresoc.v:183710.18-183710.93" *)
  wire [4:0] _07_;
  (* src = "libresoc.v:183712.17-183712.92" *)
  wire [4:0] _08_;
  (* src = "libresoc.v:183715.17-183715.92" *)
  wire [4:0] _09_;
  (* src = "libresoc.v:183709.18-183709.98" *)
  wire [4:0] _10_;
  (* src = "libresoc.v:183711.18-183711.99" *)
  wire [4:0] _11_;
  (* src = "libresoc.v:183714.17-183714.97" *)
  wire [4:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [4:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [4:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183673.7-183673.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [4:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [4:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [4:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [4:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [4:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:183719.5-183719.29" *)
    casez (\initial )
      /* src = "libresoc.v:183719.9-183719.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 5'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183734.1-183792.10" *)
module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183735.7-183735.20" *)
  reg _00_;
  (* src = "libresoc.v:183780.3-183788.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:183778.3-183779.27" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:183780.3-183788.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:183757.13-183757.25" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:183770.17-183770.96" *)
  wire [3:0] _05_;
  (* src = "libresoc.v:183775.17-183775.96" *)
  wire [3:0] _06_;
  (* src = "libresoc.v:183772.18-183772.93" *)
  wire [3:0] _07_;
  (* src = "libresoc.v:183774.17-183774.92" *)
  wire [3:0] _08_;
  (* src = "libresoc.v:183777.17-183777.92" *)
  wire [3:0] _09_;
  (* src = "libresoc.v:183771.18-183771.98" *)
  wire [3:0] _10_;
  (* src = "libresoc.v:183773.18-183773.99" *)
  wire [3:0] _11_;
  (* src = "libresoc.v:183776.17-183776.97" *)
  wire [3:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [3:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [3:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183735.7-183735.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [3:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [3:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [3:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [3:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [3:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:183781.5-183781.29" *)
    casez (\initial )
      /* src = "libresoc.v:183781.9-183781.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 4'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183796.1-183854.10" *)
module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183797.7-183797.20" *)
  reg _00_;
  (* src = "libresoc.v:183842.3-183850.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:183840.3-183841.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:183842.3-183850.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:183819.13-183819.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:183832.17-183832.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:183837.17-183837.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:183834.18-183834.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:183836.17-183836.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:183839.17-183839.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:183833.18-183833.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:183835.18-183835.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:183838.17-183838.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183797.7-183797.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:183843.5-183843.29" *)
    casez (\initial )
      /* src = "libresoc.v:183843.9-183843.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183858.1-183916.10" *)
module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183859.7-183859.20" *)
  reg _00_;
  (* src = "libresoc.v:183904.3-183912.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:183902.3-183903.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:183904.3-183912.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:183881.13-183881.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:183894.17-183894.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:183899.17-183899.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:183896.18-183896.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:183898.17-183898.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:183901.17-183901.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:183895.18-183895.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:183897.18-183897.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:183900.17-183900.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183859.7-183859.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:183905.5-183905.29" *)
    casez (\initial )
      /* src = "libresoc.v:183905.9-183905.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183920.1-183978.10" *)
module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183921.7-183921.20" *)
  reg _00_;
  (* src = "libresoc.v:183966.3-183974.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:183964.3-183965.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:183966.3-183974.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:183943.13-183943.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:183956.17-183956.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:183961.17-183961.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:183958.18-183958.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:183960.17-183960.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:183963.17-183963.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:183957.18-183957.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:183959.18-183959.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:183962.17-183962.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183921.7-183921.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:183967.5-183967.29" *)
    casez (\initial )
      /* src = "libresoc.v:183967.9-183967.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:183982.1-184040.10" *)
module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:183983.7-183983.20" *)
  reg _00_;
  (* src = "libresoc.v:184028.3-184036.6" *)
  reg [4:0] _01_;
  (* src = "libresoc.v:184026.3-184027.27" *)
  reg [4:0] _02_;
  (* src = "libresoc.v:184028.3-184036.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:184005.13-184005.26" *)
  reg [4:0] _04_;
  (* src = "libresoc.v:184018.17-184018.96" *)
  wire [4:0] _05_;
  (* src = "libresoc.v:184023.17-184023.96" *)
  wire [4:0] _06_;
  (* src = "libresoc.v:184020.18-184020.93" *)
  wire [4:0] _07_;
  (* src = "libresoc.v:184022.17-184022.92" *)
  wire [4:0] _08_;
  (* src = "libresoc.v:184025.17-184025.92" *)
  wire [4:0] _09_;
  (* src = "libresoc.v:184019.18-184019.98" *)
  wire [4:0] _10_;
  (* src = "libresoc.v:184021.18-184021.99" *)
  wire [4:0] _11_;
  (* src = "libresoc.v:184024.17-184024.97" *)
  wire [4:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [4:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [4:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:183983.7-183983.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [4:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [4:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [4:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [4:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [4:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184029.5-184029.29" *)
    casez (\initial )
      /* src = "libresoc.v:184029.9-184029.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 5'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184044.1-184102.10" *)
module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184045.7-184045.20" *)
  reg _00_;
  (* src = "libresoc.v:184090.3-184098.6" *)
  reg [1:0] _01_;
  (* src = "libresoc.v:184088.3-184089.27" *)
  reg [1:0] _02_;
  (* src = "libresoc.v:184090.3-184098.6" *)
  reg [1:0] _03_;
  (* src = "libresoc.v:184067.13-184067.25" *)
  reg [1:0] _04_;
  (* src = "libresoc.v:184080.17-184080.96" *)
  wire [1:0] _05_;
  (* src = "libresoc.v:184085.17-184085.96" *)
  wire [1:0] _06_;
  (* src = "libresoc.v:184082.18-184082.93" *)
  wire [1:0] _07_;
  (* src = "libresoc.v:184084.17-184084.92" *)
  wire [1:0] _08_;
  (* src = "libresoc.v:184087.17-184087.92" *)
  wire [1:0] _09_;
  (* src = "libresoc.v:184081.18-184081.98" *)
  wire [1:0] _10_;
  (* src = "libresoc.v:184083.18-184083.99" *)
  wire [1:0] _11_;
  (* src = "libresoc.v:184086.17-184086.97" *)
  wire [1:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [1:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [1:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [1:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [1:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [1:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [1:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [1:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [1:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184045.7-184045.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [1:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [1:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [1:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [1:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [1:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [1:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [1:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184091.5-184091.29" *)
    casez (\initial )
      /* src = "libresoc.v:184091.9-184091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 2'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184106.1-184164.10" *)
module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184107.7-184107.20" *)
  reg _00_;
  (* src = "libresoc.v:184152.3-184160.6" *)
  reg [5:0] _01_;
  (* src = "libresoc.v:184150.3-184151.27" *)
  reg [5:0] _02_;
  (* src = "libresoc.v:184152.3-184160.6" *)
  reg [5:0] _03_;
  (* src = "libresoc.v:184129.13-184129.26" *)
  reg [5:0] _04_;
  (* src = "libresoc.v:184142.17-184142.96" *)
  wire [5:0] _05_;
  (* src = "libresoc.v:184147.17-184147.96" *)
  wire [5:0] _06_;
  (* src = "libresoc.v:184144.18-184144.93" *)
  wire [5:0] _07_;
  (* src = "libresoc.v:184146.17-184146.92" *)
  wire [5:0] _08_;
  (* src = "libresoc.v:184149.17-184149.92" *)
  wire [5:0] _09_;
  (* src = "libresoc.v:184143.18-184143.98" *)
  wire [5:0] _10_;
  (* src = "libresoc.v:184145.18-184145.99" *)
  wire [5:0] _11_;
  (* src = "libresoc.v:184148.17-184148.97" *)
  wire [5:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [5:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [5:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184107.7-184107.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [5:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [5:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [5:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [5:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [5:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184153.5-184153.29" *)
    casez (\initial )
      /* src = "libresoc.v:184153.9-184153.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 6'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.req_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184168.1-184226.10" *)
module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184169.7-184169.20" *)
  reg _00_;
  (* src = "libresoc.v:184214.3-184222.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:184212.3-184213.27" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:184214.3-184222.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:184191.13-184191.25" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:184204.17-184204.96" *)
  wire [3:0] _05_;
  (* src = "libresoc.v:184209.17-184209.96" *)
  wire [3:0] _06_;
  (* src = "libresoc.v:184206.18-184206.93" *)
  wire [3:0] _07_;
  (* src = "libresoc.v:184208.17-184208.92" *)
  wire [3:0] _08_;
  (* src = "libresoc.v:184211.17-184211.92" *)
  wire [3:0] _09_;
  (* src = "libresoc.v:184205.18-184205.98" *)
  wire [3:0] _10_;
  (* src = "libresoc.v:184207.18-184207.99" *)
  wire [3:0] _11_;
  (* src = "libresoc.v:184210.17-184210.97" *)
  wire [3:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [3:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [3:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184169.7-184169.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [3:0] q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [3:0] qlq_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [3:0] qn_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [3:0] r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [3:0] s_req;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_req;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_req;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_req;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_req;
  assign _11_ = q_req | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_req;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184215.5-184215.29" *)
    casez (\initial )
      /* src = "libresoc.v:184215.9-184215.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 4'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_req = \$15 ;
  assign qn_req = \$13 ;
  assign q_req = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.reset_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184230.1-184279.10" *)
module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184231.7-184231.20" *)
  reg _00_;
  (* src = "libresoc.v:184267.3-184275.6" *)
  reg _01_;
  (* src = "libresoc.v:184265.3-184266.27" *)
  reg _02_;
  (* src = "libresoc.v:184267.3-184275.6" *)
  reg _03_;
  (* src = "libresoc.v:184247.7-184247.19" *)
  reg _04_;
  (* src = "libresoc.v:184262.17-184262.96" *)
  wire _05_;
  (* src = "libresoc.v:184261.17-184261.94" *)
  wire _06_;
  (* src = "libresoc.v:184264.17-184264.94" *)
  wire _07_;
  (* src = "libresoc.v:184260.17-184260.100" *)
  wire _08_;
  (* src = "libresoc.v:184263.17-184263.99" *)
  wire _09_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184231.7-184231.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_reset;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_reset;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_reset;
  assign _08_ = q_reset | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _09_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_reset;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184268.5-184268.29" *)
    casez (\initial )
      /* src = "libresoc.v:184268.9-184268.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _08_;
  assign \$1  = _06_;
  assign \$3  = _05_;
  assign \$5  = _09_;
  assign \$7  = _07_;
  assign qlq_reset = \$9 ;
  assign qn_reset = \$7 ;
  assign q_reset = q_int;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.l0.reset_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184283.1-184332.10" *)
module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184284.7-184284.20" *)
  reg _00_;
  (* src = "libresoc.v:184320.3-184328.6" *)
  reg _01_;
  (* src = "libresoc.v:184318.3-184319.27" *)
  reg _02_;
  (* src = "libresoc.v:184320.3-184328.6" *)
  reg _03_;
  (* src = "libresoc.v:184300.7-184300.19" *)
  reg _04_;
  (* src = "libresoc.v:184315.17-184315.96" *)
  wire _05_;
  (* src = "libresoc.v:184314.17-184314.94" *)
  wire _06_;
  (* src = "libresoc.v:184317.17-184317.94" *)
  wire _07_;
  (* src = "libresoc.v:184313.17-184313.100" *)
  wire _08_;
  (* src = "libresoc.v:184316.17-184316.99" *)
  wire _09_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184284.7-184284.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_reset;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_reset;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_reset;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_reset;
  assign _08_ = q_reset | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _09_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_reset;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184321.5-184321.29" *)
    casez (\initial )
      /* src = "libresoc.v:184321.9-184321.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _08_;
  assign \$1  = _06_;
  assign \$3  = _05_;
  assign \$5  = _09_;
  assign \$7  = _07_;
  assign qlq_reset = \$9 ;
  assign qn_reset = \$7 ;
  assign q_reset = q_int;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184336.1-184923.10" *)
module right_mask(mask, shift);
  reg \initial  = 0;
  (* src = "libresoc.v:184337.7-184337.20" *)
  reg _000_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg [63:0] _001_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _002_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _003_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _004_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _005_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _006_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _007_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _008_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _009_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _010_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _011_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _012_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _013_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _014_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _015_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _016_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _017_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _018_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _019_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _020_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _021_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _022_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _023_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _024_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _025_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _026_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _027_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _028_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _029_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _030_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _031_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _032_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _033_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _034_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _035_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _036_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _037_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _038_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _039_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _040_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _041_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _042_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _043_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _044_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _045_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _046_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _047_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _048_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _049_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _050_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _051_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _052_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _053_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _054_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _055_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _056_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _057_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _058_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _059_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _060_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _061_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _062_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _063_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _064_;
  (* src = "libresoc.v:184535.3-184922.6" *)
  reg _065_;
  (* src = "libresoc.v:184471.17-184471.96" *)
  wire _066_;
  (* src = "libresoc.v:184472.18-184472.98" *)
  wire _067_;
  (* src = "libresoc.v:184473.19-184473.99" *)
  wire _068_;
  (* src = "libresoc.v:184474.19-184474.99" *)
  wire _069_;
  (* src = "libresoc.v:184475.19-184475.99" *)
  wire _070_;
  (* src = "libresoc.v:184476.19-184476.99" *)
  wire _071_;
  (* src = "libresoc.v:184477.19-184477.99" *)
  wire _072_;
  (* src = "libresoc.v:184478.19-184478.99" *)
  wire _073_;
  (* src = "libresoc.v:184479.19-184479.99" *)
  wire _074_;
  (* src = "libresoc.v:184480.19-184480.99" *)
  wire _075_;
  (* src = "libresoc.v:184481.19-184481.99" *)
  wire _076_;
  (* src = "libresoc.v:184482.18-184482.97" *)
  wire _077_;
  (* src = "libresoc.v:184483.19-184483.99" *)
  wire _078_;
  (* src = "libresoc.v:184484.19-184484.99" *)
  wire _079_;
  (* src = "libresoc.v:184485.19-184485.99" *)
  wire _080_;
  (* src = "libresoc.v:184486.19-184486.99" *)
  wire _081_;
  (* src = "libresoc.v:184487.19-184487.99" *)
  wire _082_;
  (* src = "libresoc.v:184488.18-184488.97" *)
  wire _083_;
  (* src = "libresoc.v:184489.18-184489.97" *)
  wire _084_;
  (* src = "libresoc.v:184490.18-184490.97" *)
  wire _085_;
  (* src = "libresoc.v:184491.17-184491.96" *)
  wire _086_;
  (* src = "libresoc.v:184492.18-184492.97" *)
  wire _087_;
  (* src = "libresoc.v:184493.18-184493.97" *)
  wire _088_;
  (* src = "libresoc.v:184494.18-184494.97" *)
  wire _089_;
  (* src = "libresoc.v:184495.18-184495.97" *)
  wire _090_;
  (* src = "libresoc.v:184496.18-184496.97" *)
  wire _091_;
  (* src = "libresoc.v:184497.18-184497.97" *)
  wire _092_;
  (* src = "libresoc.v:184498.18-184498.97" *)
  wire _093_;
  (* src = "libresoc.v:184499.18-184499.98" *)
  wire _094_;
  (* src = "libresoc.v:184500.18-184500.98" *)
  wire _095_;
  (* src = "libresoc.v:184501.18-184501.98" *)
  wire _096_;
  (* src = "libresoc.v:184502.17-184502.96" *)
  wire _097_;
  (* src = "libresoc.v:184503.18-184503.98" *)
  wire _098_;
  (* src = "libresoc.v:184504.18-184504.98" *)
  wire _099_;
  (* src = "libresoc.v:184505.18-184505.98" *)
  wire _100_;
  (* src = "libresoc.v:184506.18-184506.98" *)
  wire _101_;
  (* src = "libresoc.v:184507.18-184507.98" *)
  wire _102_;
  (* src = "libresoc.v:184508.18-184508.98" *)
  wire _103_;
  (* src = "libresoc.v:184509.18-184509.98" *)
  wire _104_;
  (* src = "libresoc.v:184510.18-184510.98" *)
  wire _105_;
  (* src = "libresoc.v:184511.18-184511.98" *)
  wire _106_;
  (* src = "libresoc.v:184512.18-184512.98" *)
  wire _107_;
  (* src = "libresoc.v:184513.17-184513.96" *)
  wire _108_;
  (* src = "libresoc.v:184514.18-184514.98" *)
  wire _109_;
  (* src = "libresoc.v:184515.18-184515.98" *)
  wire _110_;
  (* src = "libresoc.v:184516.18-184516.98" *)
  wire _111_;
  (* src = "libresoc.v:184517.18-184517.98" *)
  wire _112_;
  (* src = "libresoc.v:184518.18-184518.98" *)
  wire _113_;
  (* src = "libresoc.v:184519.18-184519.98" *)
  wire _114_;
  (* src = "libresoc.v:184520.18-184520.98" *)
  wire _115_;
  (* src = "libresoc.v:184521.18-184521.98" *)
  wire _116_;
  (* src = "libresoc.v:184522.18-184522.98" *)
  wire _117_;
  (* src = "libresoc.v:184523.18-184523.98" *)
  wire _118_;
  (* src = "libresoc.v:184524.17-184524.96" *)
  wire _119_;
  (* src = "libresoc.v:184525.18-184525.98" *)
  wire _120_;
  (* src = "libresoc.v:184526.18-184526.98" *)
  wire _121_;
  (* src = "libresoc.v:184527.18-184527.98" *)
  wire _122_;
  (* src = "libresoc.v:184528.18-184528.98" *)
  wire _123_;
  (* src = "libresoc.v:184529.18-184529.98" *)
  wire _124_;
  (* src = "libresoc.v:184530.18-184530.98" *)
  wire _125_;
  (* src = "libresoc.v:184531.18-184531.98" *)
  wire _126_;
  (* src = "libresoc.v:184532.18-184532.98" *)
  wire _127_;
  (* src = "libresoc.v:184533.18-184533.98" *)
  wire _128_;
  (* src = "libresoc.v:184534.18-184534.98" *)
  wire _129_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$125 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$61 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$63 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$67 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$69 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
  wire \$99 ;
  (* src = "libresoc.v:184337.7-184337.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *)
  output [63:0] mask;
  reg [63:0] mask;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *)
  input [6:0] shift;
  assign _066_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h4;
  assign _067_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h31;
  assign _068_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h32;
  assign _069_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h33;
  assign _070_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h34;
  assign _071_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h35;
  assign _072_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h36;
  assign _073_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h37;
  assign _074_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h38;
  assign _075_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h39;
  assign _076_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3a;
  assign _077_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h5;
  assign _078_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3b;
  assign _079_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3c;
  assign _080_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3d;
  assign _081_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3e;
  assign _082_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h3f;
  assign _083_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h6;
  assign _084_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 3'h7;
  assign _085_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h8;
  assign _086_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h0;
  assign _087_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'h9;
  assign _088_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'ha;
  assign _089_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hb;
  assign _090_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hc;
  assign _091_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hd;
  assign _092_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'he;
  assign _093_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 4'hf;
  assign _094_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h10;
  assign _095_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h11;
  assign _096_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h12;
  assign _097_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 1'h1;
  assign _098_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h13;
  assign _099_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h14;
  assign _100_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h15;
  assign _101_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h16;
  assign _102_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h17;
  assign _103_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h18;
  assign _104_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h19;
  assign _105_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1a;
  assign _106_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1b;
  assign _107_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1c;
  assign _108_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h2;
  assign _109_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1d;
  assign _110_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1e;
  assign _111_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 5'h1f;
  assign _112_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h20;
  assign _113_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h21;
  assign _114_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h22;
  assign _115_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h23;
  assign _116_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h24;
  assign _117_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h25;
  assign _118_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h26;
  assign _119_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 2'h3;
  assign _120_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h27;
  assign _121_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h28;
  assign _122_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h29;
  assign _123_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2a;
  assign _124_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2b;
  assign _125_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2c;
  assign _126_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2d;
  assign _127_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2e;
  assign _128_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h2f;
  assign _129_ = shift > (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *) 6'h30;
  always @* begin
    if (\initial ) begin end
    _000_ = 1'h0;
  end
  always @* begin
      \initial  <= _000_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _001_[0] = _012_;
    _001_[1] = _023_;
    _001_[2] = _034_;
    _001_[3] = _045_;
    _001_[4] = _056_;
    _001_[5] = _062_;
    _001_[6] = _063_;
    _001_[7] = _064_;
    _001_[8] = _065_;
    _001_[9] = _002_;
    _001_[10] = _003_;
    _001_[11] = _004_;
    _001_[12] = _005_;
    _001_[13] = _006_;
    _001_[14] = _007_;
    _001_[15] = _008_;
    _001_[16] = _009_;
    _001_[17] = _010_;
    _001_[18] = _011_;
    _001_[19] = _013_;
    _001_[20] = _014_;
    _001_[21] = _015_;
    _001_[22] = _016_;
    _001_[23] = _017_;
    _001_[24] = _018_;
    _001_[25] = _019_;
    _001_[26] = _020_;
    _001_[27] = _021_;
    _001_[28] = _022_;
    _001_[29] = _024_;
    _001_[30] = _025_;
    _001_[31] = _026_;
    _001_[32] = _027_;
    _001_[33] = _028_;
    _001_[34] = _029_;
    _001_[35] = _030_;
    _001_[36] = _031_;
    _001_[37] = _032_;
    _001_[38] = _033_;
    _001_[39] = _035_;
    _001_[40] = _036_;
    _001_[41] = _037_;
    _001_[42] = _038_;
    _001_[43] = _039_;
    _001_[44] = _040_;
    _001_[45] = _041_;
    _001_[46] = _042_;
    _001_[47] = _043_;
    _001_[48] = _044_;
    _001_[49] = _046_;
    _001_[50] = _047_;
    _001_[51] = _048_;
    _001_[52] = _049_;
    _001_[53] = _050_;
    _001_[54] = _051_;
    _001_[55] = _052_;
    _001_[56] = _053_;
    _001_[57] = _054_;
    _001_[58] = _055_;
    _001_[59] = _057_;
    _001_[60] = _058_;
    _001_[61] = _059_;
    _001_[62] = _060_;
    _001_[63] = _061_;
    (* src = "libresoc.v:184536.5-184536.29" *)
    casez (\initial )
      /* src = "libresoc.v:184536.9-184536.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$1 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _012_ = 1'h1;
        end
      default:
          _012_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$3 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _023_ = 1'h1;
        end
      default:
          _023_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$5 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _034_ = 1'h1;
        end
      default:
          _034_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$7 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _045_ = 1'h1;
        end
      default:
          _045_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$9 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _056_ = 1'h1;
        end
      default:
          _056_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$11 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _062_ = 1'h1;
        end
      default:
          _062_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _063_ = 1'h1;
        end
      default:
          _063_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$15 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _064_ = 1'h1;
        end
      default:
          _064_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$17 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _065_ = 1'h1;
        end
      default:
          _065_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$19 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _002_ = 1'h1;
        end
      default:
          _002_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$21 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _003_ = 1'h1;
        end
      default:
          _003_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$23 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _004_ = 1'h1;
        end
      default:
          _004_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$25 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _005_ = 1'h1;
        end
      default:
          _005_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$27 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _006_ = 1'h1;
        end
      default:
          _006_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$29 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _007_ = 1'h1;
        end
      default:
          _007_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$31 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _008_ = 1'h1;
        end
      default:
          _008_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$33 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _009_ = 1'h1;
        end
      default:
          _009_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$35 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _010_ = 1'h1;
        end
      default:
          _010_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$37 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _011_ = 1'h1;
        end
      default:
          _011_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$39 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _013_ = 1'h1;
        end
      default:
          _013_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$41 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _014_ = 1'h1;
        end
      default:
          _014_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$43 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _015_ = 1'h1;
        end
      default:
          _015_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$45 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _016_ = 1'h1;
        end
      default:
          _016_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$47 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _017_ = 1'h1;
        end
      default:
          _017_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$49 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _018_ = 1'h1;
        end
      default:
          _018_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$51 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _019_ = 1'h1;
        end
      default:
          _019_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$53 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _020_ = 1'h1;
        end
      default:
          _020_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _021_ = 1'h1;
        end
      default:
          _021_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$57 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _022_ = 1'h1;
        end
      default:
          _022_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$59 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _024_ = 1'h1;
        end
      default:
          _024_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$61 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _025_ = 1'h1;
        end
      default:
          _025_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$63 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _026_ = 1'h1;
        end
      default:
          _026_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$65 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _027_ = 1'h1;
        end
      default:
          _027_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$67 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _028_ = 1'h1;
        end
      default:
          _028_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$69 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _029_ = 1'h1;
        end
      default:
          _029_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$71 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _030_ = 1'h1;
        end
      default:
          _030_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$73 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _031_ = 1'h1;
        end
      default:
          _031_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$75 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _032_ = 1'h1;
        end
      default:
          _032_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$77 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _033_ = 1'h1;
        end
      default:
          _033_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$79 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _035_ = 1'h1;
        end
      default:
          _035_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$81 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _036_ = 1'h1;
        end
      default:
          _036_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$83 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _037_ = 1'h1;
        end
      default:
          _037_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$85 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _038_ = 1'h1;
        end
      default:
          _038_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$87 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _039_ = 1'h1;
        end
      default:
          _039_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$89 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _040_ = 1'h1;
        end
      default:
          _040_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$91 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _041_ = 1'h1;
        end
      default:
          _041_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$93 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _042_ = 1'h1;
        end
      default:
          _042_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$95 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _043_ = 1'h1;
        end
      default:
          _043_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$97 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _044_ = 1'h1;
        end
      default:
          _044_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$99 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _046_ = 1'h1;
        end
      default:
          _046_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$101 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _047_ = 1'h1;
        end
      default:
          _047_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$103 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _048_ = 1'h1;
        end
      default:
          _048_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$105 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _049_ = 1'h1;
        end
      default:
          _049_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$107 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _050_ = 1'h1;
        end
      default:
          _050_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$109 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _051_ = 1'h1;
        end
      default:
          _051_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$111 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _052_ = 1'h1;
        end
      default:
          _052_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _053_ = 1'h1;
        end
      default:
          _053_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _054_ = 1'h1;
        end
      default:
          _054_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$117 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _055_ = 1'h1;
        end
      default:
          _055_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$119 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _057_ = 1'h1;
        end
      default:
          _057_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$121 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _058_ = 1'h1;
        end
      default:
          _058_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$123 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _059_ = 1'h1;
        end
      default:
          _059_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$125 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _060_ = 1'h1;
        end
      default:
          _060_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" *)
    casez (\$127 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _061_ = 1'h1;
        end
      default:
          _061_ = 1'h0;
    endcase
  end
  always @* begin
      mask <= _001_;
  end
  assign \$9  = _066_;
  assign \$99  = _067_;
  assign \$101  = _068_;
  assign \$103  = _069_;
  assign \$105  = _070_;
  assign \$107  = _071_;
  assign \$109  = _072_;
  assign \$111  = _073_;
  assign \$113  = _074_;
  assign \$115  = _075_;
  assign \$117  = _076_;
  assign \$11  = _077_;
  assign \$119  = _078_;
  assign \$121  = _079_;
  assign \$123  = _080_;
  assign \$125  = _081_;
  assign \$127  = _082_;
  assign \$13  = _083_;
  assign \$15  = _084_;
  assign \$17  = _085_;
  assign \$1  = _086_;
  assign \$19  = _087_;
  assign \$21  = _088_;
  assign \$23  = _089_;
  assign \$25  = _090_;
  assign \$27  = _091_;
  assign \$29  = _092_;
  assign \$31  = _093_;
  assign \$33  = _094_;
  assign \$35  = _095_;
  assign \$37  = _096_;
  assign \$3  = _097_;
  assign \$39  = _098_;
  assign \$41  = _099_;
  assign \$43  = _100_;
  assign \$45  = _101_;
  assign \$47  = _102_;
  assign \$49  = _103_;
  assign \$51  = _104_;
  assign \$53  = _105_;
  assign \$55  = _106_;
  assign \$57  = _107_;
  assign \$5  = _108_;
  assign \$59  = _109_;
  assign \$61  = _110_;
  assign \$63  = _111_;
  assign \$65  = _112_;
  assign \$67  = _113_;
  assign \$69  = _114_;
  assign \$71  = _115_;
  assign \$73  = _116_;
  assign \$75  = _117_;
  assign \$77  = _118_;
  assign \$7  = _119_;
  assign \$79  = _120_;
  assign \$81  = _121_;
  assign \$83  = _122_;
  assign \$85  = _123_;
  assign \$87  = _124_;
  assign \$89  = _125_;
  assign \$91  = _126_;
  assign \$93  = _127_;
  assign \$95  = _128_;
  assign \$97  = _129_;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184927.1-184985.10" *)
module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184928.7-184928.20" *)
  reg _00_;
  (* src = "libresoc.v:184973.3-184981.6" *)
  reg _01_;
  (* src = "libresoc.v:184971.3-184972.27" *)
  reg _02_;
  (* src = "libresoc.v:184973.3-184981.6" *)
  reg _03_;
  (* src = "libresoc.v:184950.7-184950.19" *)
  reg _04_;
  (* src = "libresoc.v:184963.17-184963.96" *)
  wire _05_;
  (* src = "libresoc.v:184968.17-184968.96" *)
  wire _06_;
  (* src = "libresoc.v:184965.18-184965.94" *)
  wire _07_;
  (* src = "libresoc.v:184967.17-184967.93" *)
  wire _08_;
  (* src = "libresoc.v:184970.17-184970.93" *)
  wire _09_;
  (* src = "libresoc.v:184964.18-184964.99" *)
  wire _10_;
  (* src = "libresoc.v:184966.18-184966.100" *)
  wire _11_;
  (* src = "libresoc.v:184969.17-184969.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184928.7-184928.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:184974.5-184974.29" *)
    casez (\initial )
      /* src = "libresoc.v:184974.9-184974.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:184989.1-185047.10" *)
module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:184990.7-184990.20" *)
  reg _00_;
  (* src = "libresoc.v:185035.3-185043.6" *)
  reg _01_;
  (* src = "libresoc.v:185033.3-185034.27" *)
  reg _02_;
  (* src = "libresoc.v:185035.3-185043.6" *)
  reg _03_;
  (* src = "libresoc.v:185012.7-185012.19" *)
  reg _04_;
  (* src = "libresoc.v:185025.17-185025.96" *)
  wire _05_;
  (* src = "libresoc.v:185030.17-185030.96" *)
  wire _06_;
  (* src = "libresoc.v:185027.18-185027.94" *)
  wire _07_;
  (* src = "libresoc.v:185029.17-185029.93" *)
  wire _08_;
  (* src = "libresoc.v:185032.17-185032.93" *)
  wire _09_;
  (* src = "libresoc.v:185026.18-185026.99" *)
  wire _10_;
  (* src = "libresoc.v:185028.18-185028.100" *)
  wire _11_;
  (* src = "libresoc.v:185031.17-185031.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:184990.7-184990.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185036.5-185036.29" *)
    casez (\initial )
      /* src = "libresoc.v:185036.9-185036.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185051.1-185109.10" *)
module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185052.7-185052.20" *)
  reg _00_;
  (* src = "libresoc.v:185097.3-185105.6" *)
  reg _01_;
  (* src = "libresoc.v:185095.3-185096.27" *)
  reg _02_;
  (* src = "libresoc.v:185097.3-185105.6" *)
  reg _03_;
  (* src = "libresoc.v:185074.7-185074.19" *)
  reg _04_;
  (* src = "libresoc.v:185087.17-185087.96" *)
  wire _05_;
  (* src = "libresoc.v:185092.17-185092.96" *)
  wire _06_;
  (* src = "libresoc.v:185089.18-185089.94" *)
  wire _07_;
  (* src = "libresoc.v:185091.17-185091.93" *)
  wire _08_;
  (* src = "libresoc.v:185094.17-185094.93" *)
  wire _09_;
  (* src = "libresoc.v:185088.18-185088.99" *)
  wire _10_;
  (* src = "libresoc.v:185090.18-185090.100" *)
  wire _11_;
  (* src = "libresoc.v:185093.17-185093.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185052.7-185052.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185098.5-185098.29" *)
    casez (\initial )
      /* src = "libresoc.v:185098.9-185098.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185113.1-185171.10" *)
module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185114.7-185114.20" *)
  reg _00_;
  (* src = "libresoc.v:185159.3-185167.6" *)
  reg _01_;
  (* src = "libresoc.v:185157.3-185158.27" *)
  reg _02_;
  (* src = "libresoc.v:185159.3-185167.6" *)
  reg _03_;
  (* src = "libresoc.v:185136.7-185136.19" *)
  reg _04_;
  (* src = "libresoc.v:185149.17-185149.96" *)
  wire _05_;
  (* src = "libresoc.v:185154.17-185154.96" *)
  wire _06_;
  (* src = "libresoc.v:185151.18-185151.94" *)
  wire _07_;
  (* src = "libresoc.v:185153.17-185153.93" *)
  wire _08_;
  (* src = "libresoc.v:185156.17-185156.93" *)
  wire _09_;
  (* src = "libresoc.v:185150.18-185150.99" *)
  wire _10_;
  (* src = "libresoc.v:185152.18-185152.100" *)
  wire _11_;
  (* src = "libresoc.v:185155.17-185155.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185114.7-185114.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185160.5-185160.29" *)
    casez (\initial )
      /* src = "libresoc.v:185160.9-185160.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185175.1-185233.10" *)
module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185176.7-185176.20" *)
  reg _00_;
  (* src = "libresoc.v:185221.3-185229.6" *)
  reg _01_;
  (* src = "libresoc.v:185219.3-185220.27" *)
  reg _02_;
  (* src = "libresoc.v:185221.3-185229.6" *)
  reg _03_;
  (* src = "libresoc.v:185198.7-185198.19" *)
  reg _04_;
  (* src = "libresoc.v:185211.17-185211.96" *)
  wire _05_;
  (* src = "libresoc.v:185216.17-185216.96" *)
  wire _06_;
  (* src = "libresoc.v:185213.18-185213.94" *)
  wire _07_;
  (* src = "libresoc.v:185215.17-185215.93" *)
  wire _08_;
  (* src = "libresoc.v:185218.17-185218.93" *)
  wire _09_;
  (* src = "libresoc.v:185212.18-185212.99" *)
  wire _10_;
  (* src = "libresoc.v:185214.18-185214.100" *)
  wire _11_;
  (* src = "libresoc.v:185217.17-185217.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185176.7-185176.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185222.5-185222.29" *)
    casez (\initial )
      /* src = "libresoc.v:185222.9-185222.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185237.1-185295.10" *)
module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185238.7-185238.20" *)
  reg _00_;
  (* src = "libresoc.v:185283.3-185291.6" *)
  reg _01_;
  (* src = "libresoc.v:185281.3-185282.27" *)
  reg _02_;
  (* src = "libresoc.v:185283.3-185291.6" *)
  reg _03_;
  (* src = "libresoc.v:185260.7-185260.19" *)
  reg _04_;
  (* src = "libresoc.v:185273.17-185273.96" *)
  wire _05_;
  (* src = "libresoc.v:185278.17-185278.96" *)
  wire _06_;
  (* src = "libresoc.v:185275.18-185275.94" *)
  wire _07_;
  (* src = "libresoc.v:185277.17-185277.93" *)
  wire _08_;
  (* src = "libresoc.v:185280.17-185280.93" *)
  wire _09_;
  (* src = "libresoc.v:185274.18-185274.99" *)
  wire _10_;
  (* src = "libresoc.v:185276.18-185276.100" *)
  wire _11_;
  (* src = "libresoc.v:185279.17-185279.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185238.7-185238.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185284.5-185284.29" *)
    casez (\initial )
      /* src = "libresoc.v:185284.9-185284.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185299.1-185357.10" *)
module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185300.7-185300.20" *)
  reg _00_;
  (* src = "libresoc.v:185345.3-185353.6" *)
  reg _01_;
  (* src = "libresoc.v:185343.3-185344.27" *)
  reg _02_;
  (* src = "libresoc.v:185345.3-185353.6" *)
  reg _03_;
  (* src = "libresoc.v:185322.7-185322.19" *)
  reg _04_;
  (* src = "libresoc.v:185335.17-185335.96" *)
  wire _05_;
  (* src = "libresoc.v:185340.17-185340.96" *)
  wire _06_;
  (* src = "libresoc.v:185337.18-185337.94" *)
  wire _07_;
  (* src = "libresoc.v:185339.17-185339.93" *)
  wire _08_;
  (* src = "libresoc.v:185342.17-185342.93" *)
  wire _09_;
  (* src = "libresoc.v:185336.18-185336.99" *)
  wire _10_;
  (* src = "libresoc.v:185338.18-185338.100" *)
  wire _11_;
  (* src = "libresoc.v:185341.17-185341.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185300.7-185300.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185346.5-185346.29" *)
    casez (\initial )
      /* src = "libresoc.v:185346.9-185346.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185361.1-185419.10" *)
module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185362.7-185362.20" *)
  reg _00_;
  (* src = "libresoc.v:185407.3-185415.6" *)
  reg _01_;
  (* src = "libresoc.v:185405.3-185406.27" *)
  reg _02_;
  (* src = "libresoc.v:185407.3-185415.6" *)
  reg _03_;
  (* src = "libresoc.v:185384.7-185384.19" *)
  reg _04_;
  (* src = "libresoc.v:185397.17-185397.96" *)
  wire _05_;
  (* src = "libresoc.v:185402.17-185402.96" *)
  wire _06_;
  (* src = "libresoc.v:185399.18-185399.94" *)
  wire _07_;
  (* src = "libresoc.v:185401.17-185401.93" *)
  wire _08_;
  (* src = "libresoc.v:185404.17-185404.93" *)
  wire _09_;
  (* src = "libresoc.v:185398.18-185398.99" *)
  wire _10_;
  (* src = "libresoc.v:185400.18-185400.100" *)
  wire _11_;
  (* src = "libresoc.v:185403.17-185403.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185362.7-185362.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185408.5-185408.29" *)
    casez (\initial )
      /* src = "libresoc.v:185408.9-185408.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.rok_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185423.1-185481.10" *)
module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185424.7-185424.20" *)
  reg _00_;
  (* src = "libresoc.v:185469.3-185477.6" *)
  reg _01_;
  (* src = "libresoc.v:185467.3-185468.27" *)
  reg _02_;
  (* src = "libresoc.v:185469.3-185477.6" *)
  reg _03_;
  (* src = "libresoc.v:185446.7-185446.19" *)
  reg _04_;
  (* src = "libresoc.v:185459.17-185459.96" *)
  wire _05_;
  (* src = "libresoc.v:185464.17-185464.96" *)
  wire _06_;
  (* src = "libresoc.v:185461.18-185461.94" *)
  wire _07_;
  (* src = "libresoc.v:185463.17-185463.93" *)
  wire _08_;
  (* src = "libresoc.v:185466.17-185466.93" *)
  wire _09_;
  (* src = "libresoc.v:185460.18-185460.99" *)
  wire _10_;
  (* src = "libresoc.v:185462.18-185462.100" *)
  wire _11_;
  (* src = "libresoc.v:185465.17-185465.98" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185424.7-185424.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rdok;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rdok;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rdok;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rdok;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rdok;
  assign _11_ = q_rdok | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rdok;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185470.5-185470.29" *)
    casez (\initial )
      /* src = "libresoc.v:185470.9-185470.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rdok = \$15 ;
  assign qn_rdok = \$13 ;
  assign q_rdok = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185485.1-185845.10" *)
module rotator(mb, mb_extra, rs, ra, shift, is_32bit, arith, right_shift, clear_left, clear_right, sign_ext_rs, result_o, carry_out_o, me);
  reg \initial  = 0;
  (* src = "libresoc.v:185754.3-185772.6" *)
  reg _00_;
  (* src = "libresoc.v:185686.3-185700.6" *)
  reg [31:0] _01_;
  (* src = "libresoc.v:185486.7-185486.20" *)
  reg _02_;
  (* src = "libresoc.v:185785.3-185818.6" *)
  reg [6:0] _03_;
  (* src = "libresoc.v:185819.3-185833.6" *)
  reg [6:0] _04_;
  (* src = "libresoc.v:185711.3-185722.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:185723.3-185734.6" *)
  reg [1:0] _06_;
  (* src = "libresoc.v:185735.3-185753.6" *)
  reg [63:0] _07_;
  (* src = "libresoc.v:185701.3-185710.6" *)
  reg [6:0] _08_;
  (* src = "libresoc.v:185773.3-185784.6" *)
  reg [5:0] _09_;
  (* src = "libresoc.v:185754.3-185772.6" *)
  reg _10_;
  (* src = "libresoc.v:185686.3-185700.6" *)
  reg [31:0] _11_;
  (* src = "libresoc.v:185785.3-185818.6" *)
  reg [6:0] _12_;
  (* src = "libresoc.v:185819.3-185833.6" *)
  reg [6:0] _13_;
  (* src = "libresoc.v:185711.3-185722.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:185723.3-185734.6" *)
  reg [1:0] _15_;
  (* src = "libresoc.v:185735.3-185753.6" *)
  reg [63:0] _16_;
  (* src = "libresoc.v:185701.3-185710.6" *)
  reg [6:0] _17_;
  (* src = "libresoc.v:185773.3-185784.6" *)
  reg [5:0] _18_;
  (* src = "libresoc.v:185785.3-185818.6" *)
  reg [1:0] _19_;
  (* src = "libresoc.v:185785.3-185818.6" *)
  reg [1:0] _20_;
  (* src = "libresoc.v:185637.18-185637.118" *)
  wire _21_;
  (* src = "libresoc.v:185639.18-185639.114" *)
  wire _22_;
  (* src = "libresoc.v:185648.18-185648.113" *)
  wire _23_;
  (* src = "libresoc.v:185650.18-185650.114" *)
  wire _24_;
  (* src = "libresoc.v:185652.18-185652.114" *)
  wire _25_;
  (* src = "libresoc.v:185653.18-185653.103" *)
  wire [63:0] _26_;
  (* src = "libresoc.v:185654.18-185654.106" *)
  wire [63:0] _27_;
  (* src = "libresoc.v:185656.18-185656.103" *)
  wire [63:0] _28_;
  (* src = "libresoc.v:185658.18-185658.105" *)
  wire [63:0] _29_;
  (* src = "libresoc.v:185661.18-185661.106" *)
  wire [63:0] _30_;
  (* src = "libresoc.v:185664.18-185664.105" *)
  wire [63:0] _31_;
  (* src = "libresoc.v:185666.17-185666.109" *)
  wire _32_;
  (* src = "libresoc.v:185667.18-185667.104" *)
  wire [63:0] _33_;
  (* src = "libresoc.v:185671.18-185671.105" *)
  wire [63:0] _34_;
  (* src = "libresoc.v:185635.17-185635.98" *)
  wire [6:0] _35_;
  (* src = "libresoc.v:185651.18-185651.122" *)
  wire _36_;
  (* src = "libresoc.v:185641.18-185641.111" *)
  wire _37_;
  (* src = "libresoc.v:185643.18-185643.111" *)
  wire _38_;
  (* src = "libresoc.v:185644.17-185644.117" *)
  wire [6:0] _39_;
  (* src = "libresoc.v:185636.18-185636.103" *)
  wire _40_;
  (* src = "libresoc.v:185638.18-185638.108" *)
  wire _41_;
  (* src = "libresoc.v:185640.18-185640.105" *)
  wire [5:0] _42_;
  (* src = "libresoc.v:185646.18-185646.112" *)
  wire [63:0] _43_;
  (* src = "libresoc.v:185647.18-185647.109" *)
  wire _44_;
  (* src = "libresoc.v:185655.17-185655.105" *)
  wire _45_;
  (* src = "libresoc.v:185657.18-185657.102" *)
  wire [63:0] _46_;
  (* src = "libresoc.v:185663.18-185663.102" *)
  wire [63:0] _47_;
  (* src = "libresoc.v:185668.18-185668.100" *)
  wire [63:0] _48_;
  (* src = "libresoc.v:185670.18-185670.100" *)
  wire [63:0] _49_;
  (* src = "libresoc.v:185649.18-185649.115" *)
  wire _50_;
  (* src = "libresoc.v:185659.18-185659.108" *)
  wire [63:0] _51_;
  (* src = "libresoc.v:185660.18-185660.103" *)
  wire [63:0] _52_;
  (* src = "libresoc.v:185662.18-185662.103" *)
  wire [63:0] _53_;
  (* src = "libresoc.v:185665.18-185665.108" *)
  wire [63:0] _54_;
  (* src = "libresoc.v:185669.18-185669.106" *)
  wire [63:0] _55_;
  (* src = "libresoc.v:185635.17-185635.98" *)
  wire [6:0] _56_;
  (* src = "libresoc.v:185672.18-185672.102" *)
  wire _57_;
  (* src = "libresoc.v:185642.18-185642.109" *)
  wire [7:0] _58_;
  (* src = "libresoc.v:185645.18-185645.110" *)
  wire [7:0] _59_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *)
  wire [6:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *)
  wire [6:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" *)
  wire [5:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *)
  wire [7:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *)
  wire [7:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *)
  wire [7:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *)
  wire [7:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" *)
  wire [63:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *)
  wire [63:0] \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *)
  wire [63:0] \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" *)
  wire [63:0] \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *)
  wire [63:0] \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *)
  wire [63:0] \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *)
  wire [63:0] \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *)
  wire [63:0] \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *)
  wire [6:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" *)
  input arith;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" *)
  output carry_out_o;
  reg carry_out_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" *)
  input clear_left;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" *)
  input clear_right;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" *)
  reg [31:0] hi32;
  (* src = "libresoc.v:185486.7-185486.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" *)
  input is_32bit;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *)
  wire [63:0] left_mask_mask;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *)
  wire [6:0] left_mask_shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *)
  input [4:0] mb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" *)
  reg [6:0] \mb$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" *)
  input mb_extra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" *)
  input [4:0] me;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" *)
  reg [6:0] \me$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" *)
  wire [63:0] ml;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" *)
  reg [63:0] mr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" *)
  reg [1:0] output_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" *)
  wire [63:0] repl32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" *)
  output [63:0] result_o;
  reg [63:0] result_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" *)
  wire [63:0] right_mask_mask;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" *)
  reg [6:0] right_mask_shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" *)
  input right_shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" *)
  wire [63:0] rot;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" *)
  reg [5:0] rot_count;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" *)
  wire [63:0] rotl_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" *)
  wire [5:0] rotl_b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" *)
  wire [63:0] rotl_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" *)
  input [63:0] rs;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" *)
  wire [6:0] sh;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" *)
  input [6:0] shift;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" *)
  wire [5:0] shift_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" *)
  input sign_ext_rs;
  assign _21_ = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *) is_32bit;
  assign _22_ = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) \$16 ;
  assign _23_ = clear_left & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) \$34 ;
  assign _24_ = arith & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" *) repl32[63];
  assign _25_ = clear_right & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) \$42 ;
  assign _26_ = mr & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) ml;
  assign _27_ = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$46 ;
  assign _28_ = mr & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) ml;
  assign _29_ = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$50 ;
  assign _30_ = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$58 ;
  assign _31_ = ra & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$62 ;
  assign _32_ = shift[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) \$4 ;
  assign _33_ = rot & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" *) mr;
  assign _34_ = rs & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) \$77 ;
  assign _35_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) mb;
  assign _36_ = \mb$8 [5:0] > (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" *) \me$13 [5:0];
  assign _37_ = \mb$8  <= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) 7'h40;
  assign _38_ = \mb$8  <= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *) 7'h40;
  assign _39_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" *) $signed({ shift_signed[5], shift_signed });
  assign _40_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" *) sh[5];
  assign _41_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" *) clear_left;
  assign _42_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" *) sh[5:0];
  assign _43_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" *) left_mask_mask;
  assign _44_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) clear_right;
  assign _45_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" *) is_32bit;
  assign _46_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$51 ;
  assign _47_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$63 ;
  assign _48_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) mr;
  assign _49_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) ml;
  assign _50_ = \$36  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *) right_shift;
  assign _51_ = \$48  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" *) \$54 ;
  assign _52_ = mr | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) ml;
  assign _53_ = mr | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) ml;
  assign _54_ = \$60  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" *) \$66 ;
  assign _55_ = rot | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" *) \$72 ;
  assign _56_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" *) _35_;
  assign _57_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" *) \$79 ;
  assign _58_ = 7'h40 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" *) \mb$8 ;
  assign _59_ = 6'h3f - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" *) \me$13 ;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:185673.13-185676.4" *)
  left_mask left_mask (
    .mask(left_mask_mask),
    .shift(left_mask_shift)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:185677.14-185680.4" *)
  right_mask right_mask (
    .mask(right_mask_mask),
    .shift(right_mask_shift)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:185681.8-185685.4" *)
  rotl rotl (
    .a(rotl_a),
    .b(rotl_b),
    .o(rotl_o)
  );
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _11_;
    (* src = "libresoc.v:185687.5-185687.29" *)
    casez (\initial )
      /* src = "libresoc.v:185687.9-185687.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" *)
    casez ({ sign_ext_rs, is_32bit })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _11_ = rs[31:0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _11_ = { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] };
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _11_ = rs[63:32];
        end
    endcase
  end
  always @* begin
      hi32 <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _17_;
    (* src = "libresoc.v:185702.5-185702.29" *)
    casez (\initial )
      /* src = "libresoc.v:185702.9-185702.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *)
    casez (\$22 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = \$24 [6:0];
        end
      default:
          _17_ = 7'h00;
    endcase
  end
  always @* begin
      right_mask_shift <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _14_;
    (* src = "libresoc.v:185712.5-185712.29" *)
    casez (\initial )
      /* src = "libresoc.v:185712.9-185712.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" *)
    casez (\$27 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = right_mask_mask;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _14_ = 64'h0000000000000000;
        end
    endcase
  end
  always @* begin
      mr <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:185724.5-185724.29" *)
    casez (\initial )
      /* src = "libresoc.v:185724.9-185724.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" *)
    casez (\$38 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = { 1'h1, \$40  };
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _15_ = { 1'h0, \$44  };
        end
    endcase
  end
  always @* begin
      output_mode <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _16_;
    (* src = "libresoc.v:185736.5-185736.29" *)
    casez (\initial )
      /* src = "libresoc.v:185736.9-185736.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *)
    casez (output_mode)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _16_ = \$56 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _16_ = \$68 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _16_ = \$70 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _16_ = \$74 ;
        end
      default:
          _16_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      result_o <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _10_;
    (* src = "libresoc.v:185755.5-185755.29" *)
    casez (\initial )
      /* src = "libresoc.v:185755.9-185755.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" *)
    casez (output_mode)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _10_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
          _10_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
          _10_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _10_ = \$76 ;
        end
      default:
          _10_ = 1'h0;
    endcase
  end
  always @* begin
      carry_out_o <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _18_;
    (* src = "libresoc.v:185774.5-185774.29" *)
    casez (\initial )
      /* src = "libresoc.v:185774.9-185774.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" *)
    casez (right_shift)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = \$1 [5:0];
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _18_ = shift[5:0];
        end
    endcase
  end
  always @* begin
      rot_count <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _12_;
    (* src = "libresoc.v:185786.5-185786.29" *)
    casez (\initial )
      /* src = "libresoc.v:185786.9-185786.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" *)
    casez ({ right_shift, clear_left })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _12_[4:0] = \$9 [4:0];
          _12_[6:5] = _19_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" *)
          casez (is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _19_ = 2'h1;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _19_ = { 1'h0, mb_extra };
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _12_[4:0] = sh[4:0];
          _12_[6:5] = _20_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" *)
          casez (is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _20_ = { sh[5], \$11  };
              end
            default:
                _20_ = sh[6:5];
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _12_ = { 1'h0, is_32bit, 5'h00 };
        end
    endcase
  end
  always @* begin
      \mb$8  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:185820.5-185820.29" *)
    casez (\initial )
      /* src = "libresoc.v:185820.9-185820.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" *)
    casez ({ \$18 , \$14  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _13_ = { 2'h1, me };
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'b1?:
        begin
          _13_ = { 1'h0, mb_extra, mb };
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _13_ = { sh[6], \$20  };
        end
    endcase
  end
  always @* begin
      \me$13  <= _04_;
  end
  assign \$9  = _56_;
  assign \$11  = _40_;
  assign \$14  = _21_;
  assign \$16  = _41_;
  assign \$18  = _22_;
  assign \$20  = _42_;
  assign \$22  = _37_;
  assign \$25  = _58_;
  assign \$27  = _38_;
  assign \$2  = _39_;
  assign \$30  = _59_;
  assign \$32  = _43_;
  assign \$34  = _44_;
  assign \$36  = _23_;
  assign \$38  = _50_;
  assign \$40  = _24_;
  assign \$42  = _36_;
  assign \$44  = _25_;
  assign \$46  = _26_;
  assign \$48  = _27_;
  assign \$4  = _45_;
  assign \$51  = _28_;
  assign \$50  = _46_;
  assign \$54  = _29_;
  assign \$56  = _51_;
  assign \$58  = _52_;
  assign \$60  = _30_;
  assign \$63  = _53_;
  assign \$62  = _47_;
  assign \$66  = _31_;
  assign \$68  = _54_;
  assign \$6  = _32_;
  assign \$70  = _33_;
  assign \$72  = _48_;
  assign \$74  = _55_;
  assign \$77  = _49_;
  assign \$79  = _34_;
  assign \$76  = _57_;
  assign \$1  = \$2 ;
  assign \$24  = \$25 ;
  assign \$29  = \$30 ;
  assign ml = \$32 ;
  assign left_mask_shift = \$30 [6:0];
  assign sh = { \$6 , shift[5:0] };
  assign rot = rotl_o;
  assign rotl_b = rot_count;
  assign rotl_a = repl32;
  assign shift_signed = shift[5:0];
  assign repl32 = { hi32, rs[31:0] };
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185849.1-185863.10" *)
module rotl(b, o, a);
  (* src = "libresoc.v:185861.17-185861.32" *)
  wire [127:0] _0_;
  (* src = "libresoc.v:185860.17-185860.100" *)
  wire [7:0] _1_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" *)
  wire [63:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" *)
  wire [7:0] \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" *)
  input [63:0] a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" *)
  input [5:0] b;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" *)
  output [63:0] o;
  assign _0_ = { a, a } >> (* src = "libresoc.v:185861.17-185861.32" *) \$2 ;
  assign _1_ = 7'h40 - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" *) b;
  assign \$2  = _1_;
  assign \$1  = _0_[63:0];
  assign o = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185867.1-185925.10" *)
module rst_l(coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185868.7-185868.20" *)
  reg _00_;
  (* src = "libresoc.v:185913.3-185921.6" *)
  reg _01_;
  (* src = "libresoc.v:185911.3-185912.27" *)
  reg _02_;
  (* src = "libresoc.v:185913.3-185921.6" *)
  reg _03_;
  (* src = "libresoc.v:185890.7-185890.19" *)
  reg _04_;
  (* src = "libresoc.v:185903.17-185903.96" *)
  wire _05_;
  (* src = "libresoc.v:185908.17-185908.96" *)
  wire _06_;
  (* src = "libresoc.v:185905.18-185905.93" *)
  wire _07_;
  (* src = "libresoc.v:185907.17-185907.92" *)
  wire _08_;
  (* src = "libresoc.v:185910.17-185910.92" *)
  wire _09_;
  (* src = "libresoc.v:185904.18-185904.98" *)
  wire _10_;
  (* src = "libresoc.v:185906.18-185906.99" *)
  wire _11_;
  (* src = "libresoc.v:185909.17-185909.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185868.7-185868.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185914.5-185914.29" *)
    casez (\initial )
      /* src = "libresoc.v:185914.9-185914.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185929.1-185987.10" *)
module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185930.7-185930.20" *)
  reg _00_;
  (* src = "libresoc.v:185975.3-185983.6" *)
  reg _01_;
  (* src = "libresoc.v:185973.3-185974.27" *)
  reg _02_;
  (* src = "libresoc.v:185975.3-185983.6" *)
  reg _03_;
  (* src = "libresoc.v:185952.7-185952.19" *)
  reg _04_;
  (* src = "libresoc.v:185965.17-185965.96" *)
  wire _05_;
  (* src = "libresoc.v:185970.17-185970.96" *)
  wire _06_;
  (* src = "libresoc.v:185967.18-185967.93" *)
  wire _07_;
  (* src = "libresoc.v:185969.17-185969.92" *)
  wire _08_;
  (* src = "libresoc.v:185972.17-185972.92" *)
  wire _09_;
  (* src = "libresoc.v:185966.18-185966.98" *)
  wire _10_;
  (* src = "libresoc.v:185968.18-185968.99" *)
  wire _11_;
  (* src = "libresoc.v:185971.17-185971.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185930.7-185930.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:185976.5-185976.29" *)
    casez (\initial )
      /* src = "libresoc.v:185976.9-185976.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:185991.1-186049.10" *)
module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:185992.7-185992.20" *)
  reg _00_;
  (* src = "libresoc.v:186037.3-186045.6" *)
  reg _01_;
  (* src = "libresoc.v:186035.3-186036.27" *)
  reg _02_;
  (* src = "libresoc.v:186037.3-186045.6" *)
  reg _03_;
  (* src = "libresoc.v:186014.7-186014.19" *)
  reg _04_;
  (* src = "libresoc.v:186027.17-186027.96" *)
  wire _05_;
  (* src = "libresoc.v:186032.17-186032.96" *)
  wire _06_;
  (* src = "libresoc.v:186029.18-186029.93" *)
  wire _07_;
  (* src = "libresoc.v:186031.17-186031.92" *)
  wire _08_;
  (* src = "libresoc.v:186034.17-186034.92" *)
  wire _09_;
  (* src = "libresoc.v:186028.18-186028.98" *)
  wire _10_;
  (* src = "libresoc.v:186030.18-186030.99" *)
  wire _11_;
  (* src = "libresoc.v:186033.17-186033.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:185992.7-185992.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186038.5-186038.29" *)
    casez (\initial )
      /* src = "libresoc.v:186038.9-186038.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186053.1-186111.10" *)
module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186054.7-186054.20" *)
  reg _00_;
  (* src = "libresoc.v:186099.3-186107.6" *)
  reg _01_;
  (* src = "libresoc.v:186097.3-186098.27" *)
  reg _02_;
  (* src = "libresoc.v:186099.3-186107.6" *)
  reg _03_;
  (* src = "libresoc.v:186076.7-186076.19" *)
  reg _04_;
  (* src = "libresoc.v:186089.17-186089.96" *)
  wire _05_;
  (* src = "libresoc.v:186094.17-186094.96" *)
  wire _06_;
  (* src = "libresoc.v:186091.18-186091.93" *)
  wire _07_;
  (* src = "libresoc.v:186093.17-186093.92" *)
  wire _08_;
  (* src = "libresoc.v:186096.17-186096.92" *)
  wire _09_;
  (* src = "libresoc.v:186090.18-186090.98" *)
  wire _10_;
  (* src = "libresoc.v:186092.18-186092.99" *)
  wire _11_;
  (* src = "libresoc.v:186095.17-186095.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186054.7-186054.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186100.5-186100.29" *)
    casez (\initial )
      /* src = "libresoc.v:186100.9-186100.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186115.1-186173.10" *)
module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186116.7-186116.20" *)
  reg _00_;
  (* src = "libresoc.v:186161.3-186169.6" *)
  reg _01_;
  (* src = "libresoc.v:186159.3-186160.27" *)
  reg _02_;
  (* src = "libresoc.v:186161.3-186169.6" *)
  reg _03_;
  (* src = "libresoc.v:186138.7-186138.19" *)
  reg _04_;
  (* src = "libresoc.v:186151.17-186151.96" *)
  wire _05_;
  (* src = "libresoc.v:186156.17-186156.96" *)
  wire _06_;
  (* src = "libresoc.v:186153.18-186153.93" *)
  wire _07_;
  (* src = "libresoc.v:186155.17-186155.92" *)
  wire _08_;
  (* src = "libresoc.v:186158.17-186158.92" *)
  wire _09_;
  (* src = "libresoc.v:186152.18-186152.98" *)
  wire _10_;
  (* src = "libresoc.v:186154.18-186154.99" *)
  wire _11_;
  (* src = "libresoc.v:186157.17-186157.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186116.7-186116.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186162.5-186162.29" *)
    casez (\initial )
      /* src = "libresoc.v:186162.9-186162.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186177.1-186235.10" *)
module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186178.7-186178.20" *)
  reg _00_;
  (* src = "libresoc.v:186223.3-186231.6" *)
  reg _01_;
  (* src = "libresoc.v:186221.3-186222.27" *)
  reg _02_;
  (* src = "libresoc.v:186223.3-186231.6" *)
  reg _03_;
  (* src = "libresoc.v:186200.7-186200.19" *)
  reg _04_;
  (* src = "libresoc.v:186213.17-186213.96" *)
  wire _05_;
  (* src = "libresoc.v:186218.17-186218.96" *)
  wire _06_;
  (* src = "libresoc.v:186215.18-186215.93" *)
  wire _07_;
  (* src = "libresoc.v:186217.17-186217.92" *)
  wire _08_;
  (* src = "libresoc.v:186220.17-186220.92" *)
  wire _09_;
  (* src = "libresoc.v:186214.18-186214.98" *)
  wire _10_;
  (* src = "libresoc.v:186216.18-186216.99" *)
  wire _11_;
  (* src = "libresoc.v:186219.17-186219.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186178.7-186178.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186224.5-186224.29" *)
    casez (\initial )
      /* src = "libresoc.v:186224.9-186224.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186239.1-186297.10" *)
module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186240.7-186240.20" *)
  reg _00_;
  (* src = "libresoc.v:186285.3-186293.6" *)
  reg _01_;
  (* src = "libresoc.v:186283.3-186284.27" *)
  reg _02_;
  (* src = "libresoc.v:186285.3-186293.6" *)
  reg _03_;
  (* src = "libresoc.v:186262.7-186262.19" *)
  reg _04_;
  (* src = "libresoc.v:186275.17-186275.96" *)
  wire _05_;
  (* src = "libresoc.v:186280.17-186280.96" *)
  wire _06_;
  (* src = "libresoc.v:186277.18-186277.93" *)
  wire _07_;
  (* src = "libresoc.v:186279.17-186279.92" *)
  wire _08_;
  (* src = "libresoc.v:186282.17-186282.92" *)
  wire _09_;
  (* src = "libresoc.v:186276.18-186276.98" *)
  wire _10_;
  (* src = "libresoc.v:186278.18-186278.99" *)
  wire _11_;
  (* src = "libresoc.v:186281.17-186281.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186240.7-186240.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186286.5-186286.29" *)
    casez (\initial )
      /* src = "libresoc.v:186286.9-186286.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186301.1-186359.10" *)
module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186302.7-186302.20" *)
  reg _00_;
  (* src = "libresoc.v:186347.3-186355.6" *)
  reg _01_;
  (* src = "libresoc.v:186345.3-186346.27" *)
  reg _02_;
  (* src = "libresoc.v:186347.3-186355.6" *)
  reg _03_;
  (* src = "libresoc.v:186324.7-186324.19" *)
  reg _04_;
  (* src = "libresoc.v:186337.17-186337.96" *)
  wire _05_;
  (* src = "libresoc.v:186342.17-186342.96" *)
  wire _06_;
  (* src = "libresoc.v:186339.18-186339.93" *)
  wire _07_;
  (* src = "libresoc.v:186341.17-186341.92" *)
  wire _08_;
  (* src = "libresoc.v:186344.17-186344.92" *)
  wire _09_;
  (* src = "libresoc.v:186338.18-186338.98" *)
  wire _10_;
  (* src = "libresoc.v:186340.18-186340.99" *)
  wire _11_;
  (* src = "libresoc.v:186343.17-186343.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186302.7-186302.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186348.5-186348.29" *)
    casez (\initial )
      /* src = "libresoc.v:186348.9-186348.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186363.1-186421.10" *)
module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186364.7-186364.20" *)
  reg _00_;
  (* src = "libresoc.v:186409.3-186417.6" *)
  reg _01_;
  (* src = "libresoc.v:186407.3-186408.27" *)
  reg _02_;
  (* src = "libresoc.v:186409.3-186417.6" *)
  reg _03_;
  (* src = "libresoc.v:186386.7-186386.19" *)
  reg _04_;
  (* src = "libresoc.v:186399.17-186399.96" *)
  wire _05_;
  (* src = "libresoc.v:186404.17-186404.96" *)
  wire _06_;
  (* src = "libresoc.v:186401.18-186401.93" *)
  wire _07_;
  (* src = "libresoc.v:186403.17-186403.92" *)
  wire _08_;
  (* src = "libresoc.v:186406.17-186406.92" *)
  wire _09_;
  (* src = "libresoc.v:186400.18-186400.98" *)
  wire _10_;
  (* src = "libresoc.v:186402.18-186402.99" *)
  wire _11_;
  (* src = "libresoc.v:186405.17-186405.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186364.7-186364.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186410.5-186410.29" *)
    casez (\initial )
      /* src = "libresoc.v:186410.9-186410.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.rst_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186425.1-186483.10" *)
module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:186426.7-186426.20" *)
  reg _00_;
  (* src = "libresoc.v:186471.3-186479.6" *)
  reg _01_;
  (* src = "libresoc.v:186469.3-186470.27" *)
  reg _02_;
  (* src = "libresoc.v:186471.3-186479.6" *)
  reg _03_;
  (* src = "libresoc.v:186448.7-186448.19" *)
  reg _04_;
  (* src = "libresoc.v:186461.17-186461.96" *)
  wire _05_;
  (* src = "libresoc.v:186466.17-186466.96" *)
  wire _06_;
  (* src = "libresoc.v:186463.18-186463.93" *)
  wire _07_;
  (* src = "libresoc.v:186465.17-186465.92" *)
  wire _08_;
  (* src = "libresoc.v:186468.17-186468.92" *)
  wire _09_;
  (* src = "libresoc.v:186462.18-186462.98" *)
  wire _10_;
  (* src = "libresoc.v:186464.18-186464.99" *)
  wire _11_;
  (* src = "libresoc.v:186467.17-186467.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:186426.7-186426.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire q_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_rst;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_rst;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_rst;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_rst;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_rst;
  assign _11_ = q_rst | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_rst;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:186472.5-186472.29" *)
    casez (\initial )
      /* src = "libresoc.v:186472.9-186472.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_rst = \$15 ;
  assign qn_rst = \$13 ;
  assign q_rst = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186487.1-186896.10" *)
module setup_stage(logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, ra, rb, xer_so, \muxid$1 , \logical_op__insn_type$2 , \logical_op__fn_unit$3 , \logical_op__imm_data__data$4 , \logical_op__imm_data__ok$5 , \logical_op__rc__rc$6 , \logical_op__rc__ok$7 , \logical_op__oe__oe$8 , \logical_op__oe__ok$9 , \logical_op__invert_in$10 , \logical_op__zero_a$11 , \logical_op__input_carry$12 , \logical_op__invert_out$13 , \logical_op__write_cr0$14 , \logical_op__output_carry$15 , \logical_op__is_32bit$16 , \logical_op__is_signed$17 , \logical_op__data_len$18 , \logical_op__insn$19 , \xer_so$20 , divisor_neg, dividend_neg, dive_abs_ov32, dive_abs_ov64, div_by_zero, dividend, divisor_radicand, operation, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:186854.3-186879.6" *)
  reg [127:0] _00_;
  (* src = "libresoc.v:186488.7-186488.20" *)
  reg _01_;
  (* src = "libresoc.v:186854.3-186879.6" *)
  reg [127:0] _02_;
  (* src = "libresoc.v:186854.3-186879.6" *)
  reg [127:0] _03_;
  (* src = "libresoc.v:186833.18-186833.122" *)
  wire _04_;
  (* src = "libresoc.v:186835.18-186835.122" *)
  wire _05_;
  (* src = "libresoc.v:186844.18-186844.105" *)
  wire _06_;
  (* src = "libresoc.v:186847.18-186847.105" *)
  wire _07_;
  (* src = "libresoc.v:186843.18-186843.123" *)
  wire _08_;
  (* src = "libresoc.v:186846.18-186846.123" *)
  wire _09_;
  (* src = "libresoc.v:186849.18-186849.117" *)
  wire _10_;
  (* src = "libresoc.v:186836.18-186836.97" *)
  wire [64:0] _11_;
  (* src = "libresoc.v:186837.18-186837.91" *)
  wire [64:0] _12_;
  (* src = "libresoc.v:186839.18-186839.97" *)
  wire [64:0] _13_;
  (* src = "libresoc.v:186840.18-186840.91" *)
  wire [64:0] _14_;
  (* src = "libresoc.v:186852.18-186852.99" *)
  wire [127:0] _15_;
  (* src = "libresoc.v:186842.18-186842.112" *)
  wire _16_;
  (* src = "libresoc.v:186845.18-186845.124" *)
  wire _17_;
  (* src = "libresoc.v:186836.18-186836.97" *)
  wire [64:0] _18_;
  (* src = "libresoc.v:186839.18-186839.97" *)
  wire [64:0] _19_;
  (* src = "libresoc.v:186837.18-186837.91" *)
  wire [64:0] _20_;
  (* src = "libresoc.v:186840.18-186840.91" *)
  wire [64:0] _21_;
  (* src = "libresoc.v:186852.18-186852.99" *)
  wire [127:0] _22_;
  (* src = "libresoc.v:186851.18-186851.117" *)
  wire [94:0] _23_;
  (* src = "libresoc.v:186853.18-186853.111" *)
  wire [190:0] _24_;
  (* src = "libresoc.v:186832.18-186832.131" *)
  wire _25_;
  (* src = "libresoc.v:186834.18-186834.131" *)
  wire _26_;
  (* src = "libresoc.v:186838.18-186838.119" *)
  wire [64:0] _27_;
  (* src = "libresoc.v:186841.18-186841.120" *)
  wire [64:0] _28_;
  (* src = "libresoc.v:186848.18-186848.130" *)
  wire [31:0] _29_;
  (* src = "libresoc.v:186850.18-186850.131" *)
  wire [31:0] _30_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
  wire [64:0] \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
  wire [64:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [64:0] \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *)
  wire [64:0] \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
  wire [64:0] \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
  wire [64:0] \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [64:0] \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *)
  wire [64:0] \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *)
  wire \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
  wire [31:0] \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *)
  wire [31:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *)
  wire [127:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *)
  wire [94:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *)
  wire [190:0] \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *)
  wire [190:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" *)
  wire [63:0] abs_dend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" *)
  wire [63:0] abs_dor;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *)
  output div_by_zero;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" *)
  output dive_abs_ov32;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" *)
  output dive_abs_ov64;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" *)
  output [127:0] dividend;
  reg [127:0] dividend;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" *)
  output dividend_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" *)
  output divisor_neg;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" *)
  output [63:0] divisor_radicand;
  (* src = "libresoc.v:186488.7-186488.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [3:0] logical_op__data_len;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [3:0] \logical_op__data_len$18 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] logical_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \logical_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] logical_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [63:0] \logical_op__imm_data__data$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__imm_data__ok$5 ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] logical_op__input_carry;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [1:0] \logical_op__input_carry$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] logical_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \logical_op__insn$19 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] logical_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \logical_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_in$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__invert_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__invert_out$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_32bit$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__is_signed$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__oe$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__oe__ok$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__output_carry$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__ok$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__rc__rc$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__write_cr0$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input logical_op__zero_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \logical_op__zero_a$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" *)
  output [1:0] operation;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  output \xer_so$20 ;
  assign _04_ = \$21  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) logical_op__is_signed;
  assign _05_ = \$25  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) logical_op__is_signed;
  assign _06_ = \$43  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) \$45 ;
  assign _07_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) \$51 ;
  assign _08_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" *) 7'h1e;
  assign _09_ = logical_op__insn_type == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" *) 7'h1e;
  assign _10_ = divisor_radicand == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" *) 1'h0;
  assign _11_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) rb;
  assign _12_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) rb;
  assign _13_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) ra;
  assign _14_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) ra;
  assign _15_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) \$62 ;
  assign _16_ = abs_dend >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" *) abs_dor;
  assign _17_ = abs_dend[31:0] >= (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" *) abs_dor[31:0];
  assign _18_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) _11_;
  assign _19_ = - (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) _13_;
  assign _20_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _12_;
  assign _21_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *) _14_;
  assign _22_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) _15_;
  assign _23_ = abs_dend[31:0] <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" *) 6'h20;
  assign _24_ = abs_dend <<< (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" *) 7'h40;
  assign _25_ = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" *) ra[31] : ra[63];
  assign _26_ = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" *) rb[31] : rb[63];
  assign _27_ = divisor_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" *) \$30  : \$32 ;
  assign _28_ = dividend_neg ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" *) \$37  : \$39 ;
  assign _29_ = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dor[63:32];
  assign _30_ = logical_op__is_32bit ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" *) 32'd0 : abs_dend[63:32];
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _02_;
    (* src = "libresoc.v:186855.5-186855.29" *)
    casez (\initial )
      /* src = "libresoc.v:186855.9-186855.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" *)
    casez (logical_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h1d, 7'h2f:
        begin
          _02_[127:64] = 64'h0000000000000000;
          _02_[31:0] = abs_dend[31:0];
          _02_[63:32] = \$59 ;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h1e:
        begin
          _02_ = _03_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" *)
          casez (logical_op__is_32bit)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _03_ = \$61 ;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _03_ = \$65 [127:0];
              end
          endcase
        end
      default:
          _02_ = 128'h00000000000000000000000000000000;
    endcase
  end
  always @* begin
      dividend <= _00_;
  end
  assign \$21  = _25_;
  assign \$23  = _04_;
  assign \$25  = _26_;
  assign \$27  = _05_;
  assign \$30  = _18_;
  assign \$32  = _20_;
  assign \$34  = _27_;
  assign \$37  = _19_;
  assign \$39  = _21_;
  assign \$41  = _28_;
  assign \$43  = _16_;
  assign \$45  = _08_;
  assign \$47  = _06_;
  assign \$49  = _17_;
  assign \$51  = _09_;
  assign \$53  = _07_;
  assign \$55  = _29_;
  assign \$57  = _10_;
  assign \$59  = _30_;
  assign \$62  = _23_;
  assign \$61  = _22_;
  assign \$66  = _24_;
  assign \$29  = \$34 ;
  assign \$36  = \$41 ;
  assign \$65  = \$66 ;
  assign { \logical_op__insn$19 , \logical_op__data_len$18 , \logical_op__is_signed$17 , \logical_op__is_32bit$16 , \logical_op__output_carry$15 , \logical_op__write_cr0$14 , \logical_op__invert_out$13 , \logical_op__input_carry$12 , \logical_op__zero_a$11 , \logical_op__invert_in$10 , \logical_op__oe__ok$9 , \logical_op__oe__oe$8 , \logical_op__rc__ok$7 , \logical_op__rc__rc$6 , \logical_op__imm_data__ok$5 , \logical_op__imm_data__data$4 , \logical_op__fn_unit$3 , \logical_op__insn_type$2  } = { logical_op__insn, logical_op__data_len, logical_op__is_signed, logical_op__is_32bit, logical_op__output_carry, logical_op__write_cr0, logical_op__invert_out, logical_op__input_carry, logical_op__zero_a, logical_op__invert_in, logical_op__oe__ok, logical_op__oe__oe, logical_op__rc__ok, logical_op__rc__rc, logical_op__imm_data__ok, logical_op__imm_data__data, logical_op__fn_unit, logical_op__insn_type };
  assign \muxid$1  = muxid;
  assign \xer_so$20  = xer_so;
  assign div_by_zero = \$57 ;
  assign divisor_radicand[63:32] = \$55 ;
  assign divisor_radicand[31:0] = abs_dor[31:0];
  assign dive_abs_ov32 = \$53 ;
  assign dive_abs_ov64 = \$47 ;
  assign abs_dend = \$41 [63:0];
  assign abs_dor = \$34 [63:0];
  assign divisor_neg = \$27 ;
  assign dividend_neg = \$23 ;
  assign operation = 2'h1;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:186900.1-188107.10" *)
module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src3_i, src1_i, src4_i, src5_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, cr_a_ok, dest2_o, xer_ca_ok, dest3_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:187678.3-187679.25" *)
  reg _000_;
  (* src = "libresoc.v:187676.3-187677.46" *)
  reg _001_;
  (* src = "libresoc.v:188027.3-188035.6" *)
  reg _002_;
  (* src = "libresoc.v:187594.3-187595.39" *)
  reg _003_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:187622.3-187623.75" *)
  reg [13:0] _005_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:187624.3-187625.89" *)
  reg [63:0] _007_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _008_;
  (* src = "libresoc.v:187626.3-187627.85" *)
  reg _009_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [1:0] _010_;
  (* src = "libresoc.v:187640.3-187641.83" *)
  reg [1:0] _011_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _012_;
  (* src = "libresoc.v:187644.3-187645.77" *)
  reg _013_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [31:0] _014_;
  (* src = "libresoc.v:187652.3-187653.69" *)
  reg [31:0] _015_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [6:0] _016_;
  (* src = "libresoc.v:187620.3-187621.79" *)
  reg [6:0] _017_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _018_;
  (* src = "libresoc.v:187638.3-187639.79" *)
  reg _019_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _020_;
  (* src = "libresoc.v:187648.3-187649.77" *)
  reg _021_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _022_;
  (* src = "libresoc.v:187650.3-187651.79" *)
  reg _023_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _024_;
  (* src = "libresoc.v:187632.3-187633.73" *)
  reg _025_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _026_;
  (* src = "libresoc.v:187634.3-187635.73" *)
  reg _027_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _028_;
  (* src = "libresoc.v:187642.3-187643.85" *)
  reg _029_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _030_;
  (* src = "libresoc.v:187646.3-187647.79" *)
  reg _031_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _032_;
  (* src = "libresoc.v:187630.3-187631.73" *)
  reg _033_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _034_;
  (* src = "libresoc.v:187628.3-187629.73" *)
  reg _035_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _036_;
  (* src = "libresoc.v:187636.3-187637.79" *)
  reg _037_;
  (* src = "libresoc.v:188018.3-188026.6" *)
  reg _038_;
  (* src = "libresoc.v:187596.3-187597.43" *)
  reg _039_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg [63:0] _040_;
  (* src = "libresoc.v:187616.3-187617.37" *)
  reg [63:0] _041_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg _042_;
  (* src = "libresoc.v:187618.3-187619.43" *)
  reg _043_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg [3:0] _044_;
  (* src = "libresoc.v:187612.3-187613.43" *)
  reg [3:0] _045_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg _046_;
  (* src = "libresoc.v:187614.3-187615.49" *)
  reg _047_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg [1:0] _048_;
  (* src = "libresoc.v:187608.3-187609.47" *)
  reg [1:0] _049_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg _050_;
  (* src = "libresoc.v:187610.3-187611.53" *)
  reg _051_;
  (* src = "libresoc.v:188036.3-188045.6" *)
  reg [63:0] _052_;
  (* src = "libresoc.v:188046.3-188055.6" *)
  reg [3:0] _053_;
  (* src = "libresoc.v:188056.3-188065.6" *)
  reg [1:0] _054_;
  (* src = "libresoc.v:186901.7-186901.20" *)
  reg _055_;
  (* src = "libresoc.v:187819.3-187827.6" *)
  reg _056_;
  (* src = "libresoc.v:187662.3-187663.39" *)
  reg _057_;
  (* src = "libresoc.v:187810.3-187818.6" *)
  reg _058_;
  (* src = "libresoc.v:187664.3-187665.39" *)
  reg _059_;
  (* src = "libresoc.v:188066.3-188074.6" *)
  reg [2:0] _060_;
  (* src = "libresoc.v:187674.3-187675.37" *)
  reg [2:0] _061_;
  (* src = "libresoc.v:187764.3-187773.6" *)
  reg _062_;
  (* src = "libresoc.v:187855.3-187863.6" *)
  reg [2:0] _063_;
  (* src = "libresoc.v:187654.3-187655.39" *)
  reg [2:0] _064_;
  (* src = "libresoc.v:187846.3-187854.6" *)
  reg [2:0] _065_;
  (* src = "libresoc.v:187656.3-187657.39" *)
  reg [2:0] _066_;
  (* src = "libresoc.v:187783.3-187791.6" *)
  reg _067_;
  (* src = "libresoc.v:187670.3-187671.41" *)
  reg _068_;
  (* src = "libresoc.v:187774.3-187782.6" *)
  reg _069_;
  (* src = "libresoc.v:187672.3-187673.41" *)
  reg _070_;
  (* src = "libresoc.v:187801.3-187809.6" *)
  reg _071_;
  (* src = "libresoc.v:187666.3-187667.39" *)
  reg _072_;
  (* src = "libresoc.v:187792.3-187800.6" *)
  reg _073_;
  (* src = "libresoc.v:187668.3-187669.39" *)
  reg _074_;
  (* src = "libresoc.v:187837.3-187845.6" *)
  reg [4:0] _075_;
  (* src = "libresoc.v:187658.3-187659.39" *)
  reg [4:0] _076_;
  (* src = "libresoc.v:187828.3-187836.6" *)
  reg [4:0] _077_;
  (* src = "libresoc.v:187660.3-187661.39" *)
  reg [4:0] _078_;
  (* src = "libresoc.v:187968.3-187977.6" *)
  reg [63:0] _079_;
  (* src = "libresoc.v:187606.3-187607.29" *)
  reg [63:0] _080_;
  (* src = "libresoc.v:187978.3-187987.6" *)
  reg [63:0] _081_;
  (* src = "libresoc.v:187604.3-187605.29" *)
  reg [63:0] _082_;
  (* src = "libresoc.v:187988.3-187997.6" *)
  reg [63:0] _083_;
  (* src = "libresoc.v:187602.3-187603.29" *)
  reg [63:0] _084_;
  (* src = "libresoc.v:187998.3-188007.6" *)
  reg _085_;
  (* src = "libresoc.v:187600.3-187601.29" *)
  reg _086_;
  (* src = "libresoc.v:188008.3-188017.6" *)
  reg [1:0] _087_;
  (* src = "libresoc.v:187598.3-187599.29" *)
  reg [1:0] _088_;
  (* src = "libresoc.v:187023.7-187023.24" *)
  reg _089_;
  (* src = "libresoc.v:187033.7-187033.26" *)
  reg _090_;
  (* src = "libresoc.v:188027.3-188035.6" *)
  reg _091_;
  (* src = "libresoc.v:187041.7-187041.25" *)
  reg _092_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [13:0] _093_;
  (* src = "libresoc.v:187084.14-187084.54" *)
  reg [13:0] _094_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [63:0] _095_;
  (* src = "libresoc.v:187088.14-187088.73" *)
  reg [63:0] _096_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _097_;
  (* src = "libresoc.v:187092.7-187092.48" *)
  reg _098_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [1:0] _099_;
  (* src = "libresoc.v:187100.13-187100.53" *)
  reg [1:0] _100_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _101_;
  (* src = "libresoc.v:187104.7-187104.44" *)
  reg _102_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [31:0] _103_;
  (* src = "libresoc.v:187108.14-187108.48" *)
  reg [31:0] _104_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [6:0] _105_;
  (* src = "libresoc.v:187187.13-187187.52" *)
  reg [6:0] _106_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _107_;
  (* src = "libresoc.v:187191.7-187191.45" *)
  reg _108_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _109_;
  (* src = "libresoc.v:187195.7-187195.44" *)
  reg _110_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _111_;
  (* src = "libresoc.v:187199.7-187199.45" *)
  reg _112_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _113_;
  (* src = "libresoc.v:187203.7-187203.42" *)
  reg _114_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _115_;
  (* src = "libresoc.v:187207.7-187207.42" *)
  reg _116_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _117_;
  (* src = "libresoc.v:187211.7-187211.48" *)
  reg _118_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _119_;
  (* src = "libresoc.v:187215.7-187215.45" *)
  reg _120_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _121_;
  (* src = "libresoc.v:187219.7-187219.42" *)
  reg _122_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _123_;
  (* src = "libresoc.v:187223.7-187223.42" *)
  reg _124_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _125_;
  (* src = "libresoc.v:187227.7-187227.45" *)
  reg _126_;
  (* src = "libresoc.v:188018.3-188026.6" *)
  reg _127_;
  (* src = "libresoc.v:187239.7-187239.27" *)
  reg _128_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg [63:0] _129_;
  (* src = "libresoc.v:187273.14-187273.47" *)
  reg [63:0] _130_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg _131_;
  (* src = "libresoc.v:187277.7-187277.27" *)
  reg _132_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg [3:0] _133_;
  (* src = "libresoc.v:187281.13-187281.33" *)
  reg [3:0] _134_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg _135_;
  (* src = "libresoc.v:187285.7-187285.30" *)
  reg _136_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg [1:0] _137_;
  (* src = "libresoc.v:187289.13-187289.35" *)
  reg [1:0] _138_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg _139_;
  (* src = "libresoc.v:187293.7-187293.32" *)
  reg _140_;
  (* src = "libresoc.v:188036.3-188045.6" *)
  reg [63:0] _141_;
  (* src = "libresoc.v:188046.3-188055.6" *)
  reg [3:0] _142_;
  (* src = "libresoc.v:188056.3-188065.6" *)
  reg [1:0] _143_;
  (* src = "libresoc.v:187819.3-187827.6" *)
  reg _144_;
  (* src = "libresoc.v:187310.7-187310.25" *)
  reg _145_;
  (* src = "libresoc.v:187810.3-187818.6" *)
  reg _146_;
  (* src = "libresoc.v:187314.7-187314.25" *)
  reg _147_;
  (* src = "libresoc.v:188066.3-188074.6" *)
  reg [2:0] _148_;
  (* src = "libresoc.v:187446.13-187446.30" *)
  reg [2:0] _149_;
  (* src = "libresoc.v:187764.3-187773.6" *)
  reg _150_;
  (* src = "libresoc.v:187855.3-187863.6" *)
  reg [2:0] _151_;
  (* src = "libresoc.v:187454.13-187454.31" *)
  reg [2:0] _152_;
  (* src = "libresoc.v:187846.3-187854.6" *)
  reg [2:0] _153_;
  (* src = "libresoc.v:187458.13-187458.31" *)
  reg [2:0] _154_;
  (* src = "libresoc.v:187783.3-187791.6" *)
  reg _155_;
  (* src = "libresoc.v:187470.7-187470.26" *)
  reg _156_;
  (* src = "libresoc.v:187774.3-187782.6" *)
  reg _157_;
  (* src = "libresoc.v:187474.7-187474.26" *)
  reg _158_;
  (* src = "libresoc.v:187801.3-187809.6" *)
  reg _159_;
  (* src = "libresoc.v:187478.7-187478.25" *)
  reg _160_;
  (* src = "libresoc.v:187792.3-187800.6" *)
  reg _161_;
  (* src = "libresoc.v:187482.7-187482.25" *)
  reg _162_;
  (* src = "libresoc.v:187837.3-187845.6" *)
  reg [4:0] _163_;
  (* src = "libresoc.v:187500.13-187500.32" *)
  reg [4:0] _164_;
  (* src = "libresoc.v:187828.3-187836.6" *)
  reg [4:0] _165_;
  (* src = "libresoc.v:187504.13-187504.32" *)
  reg [4:0] _166_;
  (* src = "libresoc.v:187968.3-187977.6" *)
  reg [63:0] _167_;
  (* src = "libresoc.v:187510.14-187510.43" *)
  reg [63:0] _168_;
  (* src = "libresoc.v:187978.3-187987.6" *)
  reg [63:0] _169_;
  (* src = "libresoc.v:187514.14-187514.43" *)
  reg [63:0] _170_;
  (* src = "libresoc.v:187988.3-187997.6" *)
  reg [63:0] _171_;
  (* src = "libresoc.v:187518.14-187518.43" *)
  reg [63:0] _172_;
  (* src = "libresoc.v:187998.3-188007.6" *)
  reg _173_;
  (* src = "libresoc.v:187522.7-187522.20" *)
  reg _174_;
  (* src = "libresoc.v:188008.3-188017.6" *)
  reg [1:0] _175_;
  (* src = "libresoc.v:187526.13-187526.26" *)
  reg [1:0] _176_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg [63:0] _177_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _178_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _179_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _180_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _181_;
  (* src = "libresoc.v:187864.3-187901.6" *)
  reg _182_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg [63:0] _183_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg _184_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg [3:0] _185_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg _186_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg [1:0] _187_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg _188_;
  (* src = "libresoc.v:187902.3-187923.6" *)
  reg _189_;
  (* src = "libresoc.v:187924.3-187945.6" *)
  reg _190_;
  (* src = "libresoc.v:187946.3-187967.6" *)
  reg _191_;
  (* src = "libresoc.v:187536.19-187536.114" *)
  wire [4:0] _192_;
  (* src = "libresoc.v:187537.19-187537.125" *)
  wire _193_;
  (* src = "libresoc.v:187538.19-187538.125" *)
  wire _194_;
  (* src = "libresoc.v:187539.19-187539.125" *)
  wire _195_;
  (* src = "libresoc.v:187540.18-187540.110" *)
  wire _196_;
  (* src = "libresoc.v:187541.19-187541.141" *)
  wire [2:0] _197_;
  (* src = "libresoc.v:187542.19-187542.121" *)
  wire [2:0] _198_;
  (* src = "libresoc.v:187543.19-187543.127" *)
  wire _199_;
  (* src = "libresoc.v:187544.19-187544.127" *)
  wire _200_;
  (* src = "libresoc.v:187545.19-187545.127" *)
  wire _201_;
  (* src = "libresoc.v:187547.18-187547.98" *)
  wire _202_;
  (* src = "libresoc.v:187549.18-187549.100" *)
  wire _203_;
  (* src = "libresoc.v:187550.18-187550.149" *)
  wire [2:0] _204_;
  (* src = "libresoc.v:187552.18-187552.119" *)
  wire [2:0] _205_;
  (* src = "libresoc.v:187555.17-187555.123" *)
  wire _206_;
  (* src = "libresoc.v:187556.18-187556.116" *)
  wire _207_;
  (* src = "libresoc.v:187561.18-187561.113" *)
  wire _208_;
  (* src = "libresoc.v:187562.18-187562.125" *)
  wire [2:0] _209_;
  (* src = "libresoc.v:187564.18-187564.112" *)
  wire _210_;
  (* src = "libresoc.v:187566.18-187566.132" *)
  wire _211_;
  (* src = "libresoc.v:187567.18-187567.132" *)
  wire _212_;
  (* src = "libresoc.v:187568.18-187568.117" *)
  wire _213_;
  (* src = "libresoc.v:187574.18-187574.136" *)
  wire _214_;
  (* src = "libresoc.v:187575.18-187575.124" *)
  wire [2:0] _215_;
  (* src = "libresoc.v:187577.18-187577.116" *)
  wire _216_;
  (* src = "libresoc.v:187578.18-187578.119" *)
  wire _217_;
  (* src = "libresoc.v:187579.18-187579.121" *)
  wire _218_;
  (* src = "libresoc.v:187589.18-187589.140" *)
  wire _219_;
  (* src = "libresoc.v:187590.18-187590.138" *)
  wire _220_;
  (* src = "libresoc.v:187591.18-187591.171" *)
  wire [4:0] _221_;
  (* src = "libresoc.v:187593.18-187593.129" *)
  wire [4:0] _222_;
  (* src = "libresoc.v:187563.18-187563.113" *)
  wire _223_;
  (* src = "libresoc.v:187565.18-187565.119" *)
  wire _224_;
  (* src = "libresoc.v:187535.19-187535.115" *)
  wire [4:0] _225_;
  (* src = "libresoc.v:187546.18-187546.97" *)
  wire _226_;
  (* src = "libresoc.v:187548.18-187548.99" *)
  wire _227_;
  (* src = "libresoc.v:187551.18-187551.113" *)
  wire [2:0] _228_;
  (* src = "libresoc.v:187554.18-187554.106" *)
  wire _229_;
  (* src = "libresoc.v:187560.18-187560.126" *)
  wire _230_;
  (* src = "libresoc.v:187571.17-187571.113" *)
  wire [4:0] _231_;
  (* src = "libresoc.v:187592.18-187592.136" *)
  wire _232_;
  (* src = "libresoc.v:187559.18-187559.112" *)
  wire _233_;
  (* src = "libresoc.v:187569.18-187569.122" *)
  wire _234_;
  (* src = "libresoc.v:187570.18-187570.124" *)
  wire _235_;
  (* src = "libresoc.v:187572.18-187572.155" *)
  wire [2:0] _236_;
  (* src = "libresoc.v:187573.18-187573.181" *)
  wire [4:0] _237_;
  (* src = "libresoc.v:187576.18-187576.120" *)
  wire [2:0] _238_;
  (* src = "libresoc.v:187582.17-187582.117" *)
  wire [4:0] _239_;
  (* src = "libresoc.v:187588.17-187588.104" *)
  wire _240_;
  (* src = "libresoc.v:187553.18-187553.106" *)
  wire _241_;
  (* src = "libresoc.v:187557.18-187557.113" *)
  wire _242_;
  (* src = "libresoc.v:187558.18-187558.112" *)
  wire _243_;
  (* src = "libresoc.v:187580.18-187580.165" *)
  wire _244_;
  (* src = "libresoc.v:187581.18-187581.182" *)
  wire [63:0] _245_;
  (* src = "libresoc.v:187583.18-187583.118" *)
  wire [63:0] _246_;
  (* src = "libresoc.v:187584.18-187584.115" *)
  wire [63:0] _247_;
  (* src = "libresoc.v:187585.18-187585.118" *)
  wire [63:0] _248_;
  (* src = "libresoc.v:187586.18-187586.118" *)
  wire _249_;
  (* src = "libresoc.v:187587.18-187587.118" *)
  wire [1:0] _250_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [4:0] \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [4:0] \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [2:0] \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [2:0] \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [2:0] \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [2:0] \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [4:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [2:0] \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [4:0] \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [2:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [2:0] \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [4:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *)
  wire [63:0] \$78 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$80 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$82 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$84 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$86 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [1:0] \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [4:0] \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *)
  wire \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [4:0] \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [2:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [3:0] alu_shift_rot0_cr_a;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_shift_rot0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_shift_rot0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_shift_rot0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_shift_rot0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_shift_rot0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_shift_rot0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_shift_rot0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_shift_rot0_rc;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_shift_rot0_sr_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_shift_rot0_sr_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_shift_rot0_sr_op__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_shift_rot0_sr_op__imm_data__data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__imm_data__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__imm_data__ok$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] alu_shift_rot0_sr_op__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [1:0] \alu_shift_rot0_sr_op__input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__input_cr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_shift_rot0_sr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_shift_rot0_sr_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_shift_rot0_sr_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_shift_rot0_sr_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__invert_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__is_signed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__oe__oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__oe__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__output_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__output_cr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__rc__ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__rc__rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_shift_rot0_sr_op__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_shift_rot0_sr_op__write_cr0$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_shift_rot0_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \alu_shift_rot0_xer_ca$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire alu_shift_rot0_xer_so;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [4:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [2:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [2:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [2:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] data_r1__cr_a;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [3:0] \data_r1__cr_a$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__cr_a_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__cr_a_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r2__xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r2__xer_ca$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [3:0] dest2_o;
  reg [3:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest3_o;
  reg [1:0] dest3_o;
  (* src = "libresoc.v:186901.7-186901.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_shift_rot0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_shift_rot0__imm_data__data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__imm_data__ok;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [1:0] oper_i_alu_shift_rot0__input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__input_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_shift_rot0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_shift_rot0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__invert_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__is_signed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__oe__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__oe__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__output_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__output_cr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__rc__ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__rc__rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_shift_rot0__write_cr0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [2:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [2:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [2:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [2:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [4:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [2:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src4_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src5_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [4:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" *)
  wire [63:0] src_or_imm;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r3$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] src_r4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] \src_r4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" *)
  wire src_sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  assign _192_ = \$98  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$100 ;
  assign _193_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _194_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _195_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _196_ = \$2  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$4 ;
  assign _197_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$104 , \$106 , \$108  };
  assign _198_ = \$110  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _199_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _200_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _201_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _202_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$12 ;
  assign _203_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ;
  assign _204_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o };
  assign _205_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _206_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _207_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$22 ;
  assign _208_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$38 ;
  assign _209_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _210_ = \$40  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$44 ;
  assign _211_ = \$48  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_shift_rot0_n_ready_i;
  assign _212_ = \$50  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_shift_rot0_n_valid_o;
  assign _213_ = \$52  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _214_ = alu_shift_rot0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _215_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _216_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _217_ = cr_a_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _218_ = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _219_ = alu_shift_rot0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _220_ = alu_shift_rot0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _221_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _222_ = \$94  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { 3'h7, \$96 , 1'h1 };
  assign _223_ = \$42  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _224_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _225_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _226_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _227_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _228_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _229_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _230_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_shift_rot0_n_ready_i;
  assign _231_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _232_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" *) alu_shift_rot0_sr_op__imm_data__ok;
  assign _233_ = \$32  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$34 ;
  assign _234_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _235_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _236_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _237_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _238_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _239_ = \$5  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _240_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$7 ;
  assign _241_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ;
  assign _242_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _243_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _244_ = alu_shift_rot0_sr_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" *) opc_l_q_opc : src_l_q_src[1];
  assign _245_ = alu_shift_rot0_sr_op__imm_data__ok ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" *) alu_shift_rot0_sr_op__imm_data__data : src2_i;
  assign _246_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _247_ = src_sel ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src_or_imm : src_r1;
  assign _248_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  assign _249_ = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3;
  assign _250_ = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187680.15-187686.4" *)
  \alu_l$125  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187687.18-187722.4" *)
  alu_shift_rot0 alu_shift_rot0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .cr_a(alu_shift_rot0_cr_a),
    .cr_a_ok(cr_a_ok),
    .n_ready_i(alu_shift_rot0_n_ready_i),
    .n_valid_o(alu_shift_rot0_n_valid_o),
    .o(alu_shift_rot0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_shift_rot0_p_ready_o),
    .p_valid_i(alu_shift_rot0_p_valid_i),
    .ra(alu_shift_rot0_ra),
    .rb(alu_shift_rot0_rb),
    .rc(alu_shift_rot0_rc),
    .sr_op__fn_unit(alu_shift_rot0_sr_op__fn_unit),
    .sr_op__imm_data__data(alu_shift_rot0_sr_op__imm_data__data),
    .sr_op__imm_data__ok(alu_shift_rot0_sr_op__imm_data__ok),
    .sr_op__input_carry(alu_shift_rot0_sr_op__input_carry),
    .sr_op__input_cr(alu_shift_rot0_sr_op__input_cr),
    .sr_op__insn(alu_shift_rot0_sr_op__insn),
    .sr_op__insn_type(alu_shift_rot0_sr_op__insn_type),
    .sr_op__invert_in(alu_shift_rot0_sr_op__invert_in),
    .sr_op__is_32bit(alu_shift_rot0_sr_op__is_32bit),
    .sr_op__is_signed(alu_shift_rot0_sr_op__is_signed),
    .sr_op__oe__oe(alu_shift_rot0_sr_op__oe__oe),
    .sr_op__oe__ok(alu_shift_rot0_sr_op__oe__ok),
    .sr_op__output_carry(alu_shift_rot0_sr_op__output_carry),
    .sr_op__output_cr(alu_shift_rot0_sr_op__output_cr),
    .sr_op__rc__ok(alu_shift_rot0_sr_op__rc__ok),
    .sr_op__rc__rc(alu_shift_rot0_sr_op__rc__rc),
    .sr_op__write_cr0(alu_shift_rot0_sr_op__write_cr0),
    .xer_ca(alu_shift_rot0_xer_ca),
    .\xer_ca$1 (\alu_shift_rot0_xer_ca$1 ),
    .xer_ca_ok(xer_ca_ok),
    .xer_so(alu_shift_rot0_xer_so)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187723.16-187729.4" *)
  \alui_l$124  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187730.15-187736.4" *)
  \opc_l$120  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187737.15-187743.4" *)
  \req_l$121  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187744.15-187750.4" *)
  \rok_l$123  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187751.15-187756.4" *)
  \rst_l$122  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:187757.15-187763.4" *)
  \src_l$119  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _055_ = 1'h0;
  end
  always @* begin
      \initial  <= _055_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _089_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__fn_unit <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__imm_data__data <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__imm_data__ok <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__input_carry <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__input_cr <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__insn <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__insn_type <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__invert_in <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__is_32bit <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__is_signed <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__oe__oe <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__oe__ok <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__output_carry <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__output_cr <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__rc__ok <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__rc__rc <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _126_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_shift_rot0_sr_op__write_cr0 <= _126_;
  end
  always @* begin
    if (\initial ) begin end
    _128_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _128_;
  end
  always @* begin
    if (\initial ) begin end
    _130_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _130_;
  end
  always @* begin
    if (\initial ) begin end
    _132_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _132_;
  end
  always @* begin
    if (\initial ) begin end
    _134_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a <= _134_;
  end
  always @* begin
    if (\initial ) begin end
    _136_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__cr_a_ok <= _136_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ca <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__xer_ca_ok <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _145_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _145_;
  end
  always @* begin
    if (\initial ) begin end
    _147_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _147_;
  end
  always @* begin
    if (\initial ) begin end
    _149_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _149_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 3'h7;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _160_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _160_;
  end
  always @* begin
    if (\initial ) begin end
    _162_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _162_;
  end
  always @* begin
    if (\initial ) begin end
    _164_ = 5'h1f;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _164_;
  end
  always @* begin
    if (\initial ) begin end
    _166_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _166_;
  end
  always @* begin
    if (\initial ) begin end
    _168_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _168_;
  end
  always @* begin
    if (\initial ) begin end
    _170_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _170_;
  end
  always @* begin
    if (\initial ) begin end
    _172_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _172_;
  end
  always @* begin
    if (\initial ) begin end
    _174_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r3 <= _174_;
  end
  always @* begin
    if (\initial ) begin end
    _176_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src_r4 <= _176_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = \src_r4$next ;
  end
  always @(posedge coresync_clk) begin
      src_r4 <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = \src_r3$next ;
  end
  always @(posedge coresync_clk) begin
      src_r3 <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \data_r2__xer_ca$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ca <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \data_r2__xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__xer_ca_ok <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \data_r1__cr_a$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \data_r1__cr_a_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__cr_a_ok <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \alu_shift_rot0_sr_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__insn_type <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_shift_rot0_sr_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__fn_unit <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_shift_rot0_sr_op__imm_data__data$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__imm_data__data <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_shift_rot0_sr_op__imm_data__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__imm_data__ok <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \alu_shift_rot0_sr_op__rc__rc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__rc__rc <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \alu_shift_rot0_sr_op__rc__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__rc__ok <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \alu_shift_rot0_sr_op__oe__oe$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__oe__oe <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \alu_shift_rot0_sr_op__oe__ok$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__oe__ok <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \alu_shift_rot0_sr_op__write_cr0$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__write_cr0 <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_shift_rot0_sr_op__invert_in$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__invert_in <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_shift_rot0_sr_op__input_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__input_carry <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \alu_shift_rot0_sr_op__output_carry$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__output_carry <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_shift_rot0_sr_op__input_cr$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__input_cr <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \alu_shift_rot0_sr_op__output_cr$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__output_cr <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alu_shift_rot0_sr_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__is_32bit <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \alu_shift_rot0_sr_op__is_signed$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__is_signed <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \alu_shift_rot0_sr_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_shift_rot0_sr_op__insn <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = alu_shift_rot0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$10 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _150_;
    (* src = "libresoc.v:187765.5-187765.29" *)
    casez (\initial )
      /* src = "libresoc.v:187765.9-187765.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$54 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _150_ = 1'h1;
        end
      default:
          _150_ = \$46 ;
    endcase
  end
  always @* begin
      req_done <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _157_;
    (* src = "libresoc.v:187775.5-187775.29" *)
    casez (\initial )
      /* src = "libresoc.v:187775.9-187775.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = 1'h0;
        end
      default:
          _157_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = _155_;
    (* src = "libresoc.v:187784.5-187784.29" *)
    casez (\initial )
      /* src = "libresoc.v:187784.9-187784.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _155_ = 1'h1;
        end
      default:
          _155_ = \$64 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = _161_;
    (* src = "libresoc.v:187793.5-187793.29" *)
    casez (\initial )
      /* src = "libresoc.v:187793.9-187793.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _161_ = 1'h0;
        end
      default:
          _161_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = _159_;
    (* src = "libresoc.v:187802.5-187802.29" *)
    casez (\initial )
      /* src = "libresoc.v:187802.9-187802.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _159_ = 1'h1;
        end
      default:
          _159_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _146_;
    (* src = "libresoc.v:187811.5-187811.29" *)
    casez (\initial )
      /* src = "libresoc.v:187811.9-187811.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _146_ = 1'h0;
        end
      default:
          _146_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _144_;
    (* src = "libresoc.v:187820.5-187820.29" *)
    casez (\initial )
      /* src = "libresoc.v:187820.9-187820.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _144_ = 1'h1;
        end
      default:
          _144_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = _165_;
    (* src = "libresoc.v:187829.5-187829.29" *)
    casez (\initial )
      /* src = "libresoc.v:187829.9-187829.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _165_ = 5'h00;
        end
      default:
          _165_ = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = _163_;
    (* src = "libresoc.v:187838.5-187838.29" *)
    casez (\initial )
      /* src = "libresoc.v:187838.9-187838.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _163_ = 5'h1f;
        end
      default:
          _163_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _153_;
    (* src = "libresoc.v:187847.5-187847.29" *)
    casez (\initial )
      /* src = "libresoc.v:187847.9-187847.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = 3'h0;
        end
      default:
          _153_ = \$66 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = _151_;
    (* src = "libresoc.v:187856.5-187856.29" *)
    casez (\initial )
      /* src = "libresoc.v:187856.9-187856.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = 3'h7;
        end
      default:
          _151_ = \$68 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _093_;
    _010_ = _099_;
    _012_ = _101_;
    _014_ = _103_;
    _016_ = _105_;
    _018_ = _107_;
    _020_ = _109_;
    _022_ = _111_;
    _028_ = _117_;
    _030_ = _119_;
    _036_ = _125_;
    _006_ = _177_;
    _008_ = _178_;
    _024_ = _179_;
    _026_ = _180_;
    _032_ = _181_;
    _034_ = _182_;
    (* src = "libresoc.v:187865.5-187865.29" *)
    casez (\initial )
      /* src = "libresoc.v:187865.9-187865.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _103_, _111_, _109_, _119_, _101_, _117_, _099_, _107_, _125_, _115_, _113_, _121_, _123_, _097_, _095_, _093_, _105_ } = { oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__insn_type };
        end
      default:
        begin
          _093_ = alu_shift_rot0_sr_op__fn_unit;
          _095_ = alu_shift_rot0_sr_op__imm_data__data;
          _097_ = alu_shift_rot0_sr_op__imm_data__ok;
          _099_ = alu_shift_rot0_sr_op__input_carry;
          _101_ = alu_shift_rot0_sr_op__input_cr;
          _103_ = alu_shift_rot0_sr_op__insn;
          _105_ = alu_shift_rot0_sr_op__insn_type;
          _107_ = alu_shift_rot0_sr_op__invert_in;
          _109_ = alu_shift_rot0_sr_op__is_32bit;
          _111_ = alu_shift_rot0_sr_op__is_signed;
          _113_ = alu_shift_rot0_sr_op__oe__oe;
          _115_ = alu_shift_rot0_sr_op__oe__ok;
          _117_ = alu_shift_rot0_sr_op__output_carry;
          _119_ = alu_shift_rot0_sr_op__output_cr;
          _121_ = alu_shift_rot0_sr_op__rc__ok;
          _123_ = alu_shift_rot0_sr_op__rc__rc;
          _125_ = alu_shift_rot0_sr_op__write_cr0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _177_ = 64'h0000000000000000;
          _178_ = 1'h0;
          _182_ = 1'h0;
          _181_ = 1'h0;
          _179_ = 1'h0;
          _180_ = 1'h0;
        end
      default:
        begin
          _177_ = _095_;
          _178_ = _097_;
          _179_ = _113_;
          _180_ = _115_;
          _181_ = _121_;
          _182_ = _123_;
        end
    endcase
  end
  always @* begin
      \alu_shift_rot0_sr_op__fn_unit$next  <= _004_;
      \alu_shift_rot0_sr_op__imm_data__data$next  <= _006_;
      \alu_shift_rot0_sr_op__imm_data__ok$next  <= _008_;
      \alu_shift_rot0_sr_op__input_carry$next  <= _010_;
      \alu_shift_rot0_sr_op__input_cr$next  <= _012_;
      \alu_shift_rot0_sr_op__insn$next  <= _014_;
      \alu_shift_rot0_sr_op__insn_type$next  <= _016_;
      \alu_shift_rot0_sr_op__invert_in$next  <= _018_;
      \alu_shift_rot0_sr_op__is_32bit$next  <= _020_;
      \alu_shift_rot0_sr_op__is_signed$next  <= _022_;
      \alu_shift_rot0_sr_op__oe__oe$next  <= _024_;
      \alu_shift_rot0_sr_op__oe__ok$next  <= _026_;
      \alu_shift_rot0_sr_op__output_carry$next  <= _028_;
      \alu_shift_rot0_sr_op__output_cr$next  <= _030_;
      \alu_shift_rot0_sr_op__rc__ok$next  <= _032_;
      \alu_shift_rot0_sr_op__rc__rc$next  <= _034_;
      \alu_shift_rot0_sr_op__write_cr0$next  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _183_;
    _042_ = _189_;
    (* src = "libresoc.v:187903.5-187903.29" *)
    casez (\initial )
      /* src = "libresoc.v:187903.9-187903.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _131_, _129_ } = { o_ok, alu_shift_rot0_o };
        end
      default:
        begin
          _129_ = data_r0__o;
          _131_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _184_, _183_ } = 65'h00000000000000000;
        end
      default:
        begin
          _183_ = _129_;
          _184_ = _131_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _189_ = 1'h0;
        end
      default:
          _189_ = _184_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _040_;
      \data_r0__o_ok$next  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _185_;
    _046_ = _190_;
    (* src = "libresoc.v:187925.5-187925.29" *)
    casez (\initial )
      /* src = "libresoc.v:187925.9-187925.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _135_, _133_ } = { cr_a_ok, alu_shift_rot0_cr_a };
        end
      default:
        begin
          _133_ = data_r1__cr_a;
          _135_ = data_r1__cr_a_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _186_, _185_ } = 5'h00;
        end
      default:
        begin
          _185_ = _133_;
          _186_ = _135_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _190_ = 1'h0;
        end
      default:
          _190_ = _186_;
    endcase
  end
  always @* begin
      \data_r1__cr_a$next  <= _044_;
      \data_r1__cr_a_ok$next  <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = _187_;
    _050_ = _191_;
    (* src = "libresoc.v:187947.5-187947.29" *)
    casez (\initial )
      /* src = "libresoc.v:187947.9-187947.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _139_, _137_ } = { xer_ca_ok, alu_shift_rot0_xer_ca };
        end
      default:
        begin
          _137_ = data_r2__xer_ca;
          _139_ = data_r2__xer_ca_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _188_, _187_ } = 3'h0;
        end
      default:
        begin
          _187_ = _137_;
          _188_ = _139_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _191_ = 1'h0;
        end
      default:
          _191_ = _188_;
    endcase
  end
  always @* begin
      \data_r2__xer_ca$next  <= _048_;
      \data_r2__xer_ca_ok$next  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = _167_;
    (* src = "libresoc.v:187969.5-187969.29" *)
    casez (\initial )
      /* src = "libresoc.v:187969.9-187969.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _167_ = src1_i;
        end
      default:
          _167_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = _169_;
    (* src = "libresoc.v:187979.5-187979.29" *)
    casez (\initial )
      /* src = "libresoc.v:187979.9-187979.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_sel)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _169_ = src_or_imm;
        end
      default:
          _169_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = _171_;
    (* src = "libresoc.v:187989.5-187989.29" *)
    casez (\initial )
      /* src = "libresoc.v:187989.9-187989.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = src3_i;
        end
      default:
          _171_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = _173_;
    (* src = "libresoc.v:187999.5-187999.29" *)
    casez (\initial )
      /* src = "libresoc.v:187999.9-187999.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[3])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = src4_i;
        end
      default:
          _173_ = src_r3;
    endcase
  end
  always @* begin
      \src_r3$next  <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = _175_;
    (* src = "libresoc.v:188009.5-188009.29" *)
    casez (\initial )
      /* src = "libresoc.v:188009.9-188009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[4])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = src5_i;
        end
      default:
          _175_ = src_r4;
    endcase
  end
  always @* begin
      \src_r4$next  <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _127_;
    (* src = "libresoc.v:188019.5-188019.29" *)
    casez (\initial )
      /* src = "libresoc.v:188019.9-188019.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = 1'h1;
        end
      default:
          _127_ = \$90 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _091_;
    (* src = "libresoc.v:188028.5-188028.29" *)
    casez (\initial )
      /* src = "libresoc.v:188028.9-188028.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _091_ = 1'h1;
        end
      default:
          _091_ = \$92 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = _141_;
    (* src = "libresoc.v:188037.5-188037.29" *)
    casez (\initial )
      /* src = "libresoc.v:188037.9-188037.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$114 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = data_r0__o;
        end
      default:
          _141_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = _142_;
    (* src = "libresoc.v:188047.5-188047.29" *)
    casez (\initial )
      /* src = "libresoc.v:188047.9-188047.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$116 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _142_ = data_r1__cr_a;
        end
      default:
          _142_ = 4'h0;
    endcase
  end
  always @* begin
      dest2_o <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _143_;
    (* src = "libresoc.v:188057.5-188057.29" *)
    casez (\initial )
      /* src = "libresoc.v:188057.9-188057.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$118 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = data_r2__xer_ca;
        end
      default:
          _143_ = 2'h0;
    endcase
  end
  always @* begin
      dest3_o <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _148_;
    (* src = "libresoc.v:188067.5-188067.29" *)
    casez (\initial )
      /* src = "libresoc.v:188067.9-188067.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _148_ = 3'h0;
        end
      default:
          _148_ = \$20 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _060_;
  end
  assign \$100  = _225_;
  assign \$102  = _192_;
  assign \$104  = _193_;
  assign \$106  = _194_;
  assign \$108  = _195_;
  assign \$10  = _196_;
  assign \$110  = _197_;
  assign \$112  = _198_;
  assign \$114  = _199_;
  assign \$116  = _200_;
  assign \$118  = _201_;
  assign \$12  = _226_;
  assign \$14  = _202_;
  assign \$16  = _227_;
  assign \$18  = _203_;
  assign \$20  = _204_;
  assign \$24  = _228_;
  assign \$26  = _205_;
  assign \$23  = _241_;
  assign \$22  = _229_;
  assign \$2  = _206_;
  assign \$30  = _207_;
  assign \$32  = _242_;
  assign \$34  = _243_;
  assign \$36  = _233_;
  assign \$38  = _230_;
  assign \$40  = _208_;
  assign \$42  = _209_;
  assign \$44  = _223_;
  assign \$46  = _210_;
  assign \$48  = _224_;
  assign \$50  = _211_;
  assign \$52  = _212_;
  assign \$54  = _213_;
  assign \$56  = _234_;
  assign \$58  = _235_;
  assign \$5  = _231_;
  assign \$60  = _236_;
  assign \$62  = _237_;
  assign \$64  = _214_;
  assign \$66  = _215_;
  assign \$68  = _238_;
  assign \$70  = _216_;
  assign \$72  = _217_;
  assign \$74  = _218_;
  assign \$76  = _244_;
  assign \$78  = _245_;
  assign \$7  = _239_;
  assign \$80  = _246_;
  assign \$82  = _247_;
  assign \$84  = _248_;
  assign \$86  = _249_;
  assign \$88  = _250_;
  assign \$4  = _240_;
  assign \$90  = _219_;
  assign \$92  = _220_;
  assign \$94  = _221_;
  assign \$96  = _232_;
  assign \$98  = _222_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$112 ;
  assign cu_rd__rel_o = \$102 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_shift_rot0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_shift_rot0_p_valid_i = alui_l_q_alui;
  assign \alu_shift_rot0_xer_ca$1  = \$88 ;
  assign alu_shift_rot0_xer_so = \$86 ;
  assign alu_shift_rot0_rc = \$84 ;
  assign alu_shift_rot0_rb = \$82 ;
  assign alu_shift_rot0_ra = \$80 ;
  assign src_or_imm = \$78 ;
  assign src_sel = \$76 ;
  assign cu_wrmask_o = { \$74 , \$72 , \$70  };
  assign reset_r = \$62 ;
  assign reset_w = \$60 ;
  assign rst_r = \$58 ;
  assign reset = \$56 ;
  assign wr_any = \$36 ;
  assign cu_done_o = \$30 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$18 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_shift_rot0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$14 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$10 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.spr" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:188111.1-188189.10" *)
module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:188112.7-188112.20" *)
  reg _05_;
  (* src = "libresoc.v:188166.3-188174.6" *)
  reg _06_;
  (* src = "libresoc.v:188164.3-188165.35" *)
  reg _07_;
  (* src = "libresoc.v:188175.3-188184.6" *)
  reg [63:0] _08_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [3:0] _09_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [63:0] _10_;
  (* src = "libresoc.v:188159.3-188162.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:188166.3-188174.6" *)
  reg _12_;
  (* src = "libresoc.v:188128.7-188128.23" *)
  reg _13_;
  (* src = "libresoc.v:188175.3-188184.6" *)
  reg [63:0] _14_;
  (* src = "libresoc.v:188163.26-188163.32" *)
  wire [63:0] _15_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [3:0] _16_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:0.0-0.0" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:188158.13-188158.16" *)
  reg [3:0] _0_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:188112.7-188112.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [3:0] memory_r_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" *)
  wire [63:0] memory_r_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [3:0] memory_w_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire [63:0] memory_w_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" *)
  wire memory_w_en;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" *)
  reg \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] spr1__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [3:0] \spr1__addr$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] spr1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] spr1__data_o;
  reg [63:0] spr1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input spr1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input spr1__wen;
  (* src = "libresoc.v:188144.14-188144.20" *)
  reg [63:0] memory [10:0];
  initial begin
    memory[0] = 64'h0000000000000000;
    memory[1] = 64'h0000000000000000;
    memory[2] = 64'h0000000000000000;
    memory[3] = 64'h0000000000000000;
    memory[4] = 64'h0000000000000000;
    memory[5] = 64'h0000000000000000;
    memory[6] = 64'h0000000000000000;
    memory[7] = 64'h0000000000000000;
    memory[8] = 64'h0000000000000000;
    memory[9] = 64'h0000000000000000;
    memory[10] = 64'h0000000000000000;
  end
  assign _15_ = memory[_0_];
  always @* begin
    if (\initial ) begin end
  end
  always @* begin
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _05_ = 1'h0;
  end
  always @* begin
      \initial  <= _05_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _13_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = memory_r_addr;
    _01_ = _09_;
    _02_ = _10_;
    _03_ = _11_;
    (* src = "libresoc.v:188161.5-188161.61" *)
    casez (memory_w_en)
      /* src = "libresoc.v:188161.9-188161.20" */
      1'h1:
        begin
          _09_ = memory_w_addr;
          _10_ = memory_w_data;
          _11_ = 64'hffffffffffffffff;
        end
      default:
        begin
          _09_ = 4'hx;
          _10_ = 64'hxxxxxxxxxxxxxxxx;
          _11_ = 64'h0000000000000000;
        end
    endcase
  end
  always @(posedge coresync_clk) begin
      _0_ <= _04_;
      _16_ <= _01_;
      _17_ <= _02_;
      _18_ <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _12_;
    (* src = "libresoc.v:188167.5-188167.29" *)
    casez (\initial )
      /* src = "libresoc.v:188167.9-188167.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 1'h0;
        end
      default:
          _12_ = spr1__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _14_;
    (* src = "libresoc.v:188176.5-188176.29" *)
    casez (\initial )
      /* src = "libresoc.v:188176.9-188176.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" *)
    casez (ren_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = memory_r_data;
        end
      default:
          _14_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      spr1__data_o <= _08_;
  end
  assign memory_r_data = _15_;
  assign memory_w_data = spr1__data_i;
  assign memory_w_en = spr1__wen;
  assign memory_w_addr = \spr1__addr$1 ;
  assign memory_r_addr = spr1__addr;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:188193.1-189446.10" *)
module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src1_i, src4_i, src6_i, src5_i, src3_i, src2_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, xer_ca_ok, dest6_o, xer_ov_ok, dest5_o, xer_so_ok, dest4_o, fast1_ok, dest3_o, spr1_ok, dest2_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:188943.3-188944.25" *)
  reg _000_;
  (* src = "libresoc.v:188941.3-188942.40" *)
  reg _001_;
  (* src = "libresoc.v:189337.3-189345.6" *)
  reg _002_;
  (* src = "libresoc.v:188871.3-188872.39" *)
  reg _003_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [13:0] _004_;
  (* src = "libresoc.v:188913.3-188914.65" *)
  reg [13:0] _005_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [31:0] _006_;
  (* src = "libresoc.v:188915.3-188916.59" *)
  reg [31:0] _007_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [6:0] _008_;
  (* src = "libresoc.v:188911.3-188912.69" *)
  reg [6:0] _009_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg _010_;
  (* src = "libresoc.v:188917.3-188918.67" *)
  reg _011_;
  (* src = "libresoc.v:189328.3-189336.6" *)
  reg _012_;
  (* src = "libresoc.v:188873.3-188874.43" *)
  reg _013_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg [63:0] _014_;
  (* src = "libresoc.v:188907.3-188908.37" *)
  reg [63:0] _015_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg _016_;
  (* src = "libresoc.v:188909.3-188910.43" *)
  reg _017_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg [63:0] _018_;
  (* src = "libresoc.v:188903.3-188904.43" *)
  reg [63:0] _019_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg _020_;
  (* src = "libresoc.v:188905.3-188906.49" *)
  reg _021_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg [63:0] _022_;
  (* src = "libresoc.v:188899.3-188900.45" *)
  reg [63:0] _023_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg _024_;
  (* src = "libresoc.v:188901.3-188902.51" *)
  reg _025_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _026_;
  (* src = "libresoc.v:188895.3-188896.47" *)
  reg _027_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _028_;
  (* src = "libresoc.v:188897.3-188898.53" *)
  reg _029_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg [1:0] _030_;
  (* src = "libresoc.v:188891.3-188892.47" *)
  reg [1:0] _031_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg _032_;
  (* src = "libresoc.v:188893.3-188894.53" *)
  reg _033_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg [1:0] _034_;
  (* src = "libresoc.v:188887.3-188888.47" *)
  reg [1:0] _035_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg _036_;
  (* src = "libresoc.v:188889.3-188890.53" *)
  reg _037_;
  (* src = "libresoc.v:189346.3-189355.6" *)
  reg [63:0] _038_;
  (* src = "libresoc.v:189356.3-189365.6" *)
  reg [63:0] _039_;
  (* src = "libresoc.v:189366.3-189375.6" *)
  reg [63:0] _040_;
  (* src = "libresoc.v:189376.3-189385.6" *)
  reg _041_;
  (* src = "libresoc.v:189386.3-189395.6" *)
  reg [1:0] _042_;
  (* src = "libresoc.v:189396.3-189405.6" *)
  reg [1:0] _043_;
  (* src = "libresoc.v:188194.7-188194.20" *)
  reg _044_;
  (* src = "libresoc.v:189078.3-189086.6" *)
  reg _045_;
  (* src = "libresoc.v:188927.3-188928.39" *)
  reg _046_;
  (* src = "libresoc.v:189069.3-189077.6" *)
  reg _047_;
  (* src = "libresoc.v:188929.3-188930.39" *)
  reg _048_;
  (* src = "libresoc.v:189406.3-189414.6" *)
  reg [5:0] _049_;
  (* src = "libresoc.v:188939.3-188940.37" *)
  reg [5:0] _050_;
  (* src = "libresoc.v:189023.3-189032.6" *)
  reg _051_;
  (* src = "libresoc.v:189114.3-189122.6" *)
  reg [5:0] _052_;
  (* src = "libresoc.v:188919.3-188920.39" *)
  reg [5:0] _053_;
  (* src = "libresoc.v:189105.3-189113.6" *)
  reg [5:0] _054_;
  (* src = "libresoc.v:188921.3-188922.39" *)
  reg [5:0] _055_;
  (* src = "libresoc.v:189042.3-189050.6" *)
  reg _056_;
  (* src = "libresoc.v:188935.3-188936.41" *)
  reg _057_;
  (* src = "libresoc.v:189033.3-189041.6" *)
  reg _058_;
  (* src = "libresoc.v:188937.3-188938.41" *)
  reg _059_;
  (* src = "libresoc.v:189060.3-189068.6" *)
  reg _060_;
  (* src = "libresoc.v:188931.3-188932.39" *)
  reg _061_;
  (* src = "libresoc.v:189051.3-189059.6" *)
  reg _062_;
  (* src = "libresoc.v:188933.3-188934.39" *)
  reg _063_;
  (* src = "libresoc.v:189096.3-189104.6" *)
  reg [5:0] _064_;
  (* src = "libresoc.v:188923.3-188924.39" *)
  reg [5:0] _065_;
  (* src = "libresoc.v:189087.3-189095.6" *)
  reg [5:0] _066_;
  (* src = "libresoc.v:188925.3-188926.39" *)
  reg [5:0] _067_;
  (* src = "libresoc.v:189268.3-189277.6" *)
  reg [63:0] _068_;
  (* src = "libresoc.v:188885.3-188886.29" *)
  reg [63:0] _069_;
  (* src = "libresoc.v:189278.3-189287.6" *)
  reg [63:0] _070_;
  (* src = "libresoc.v:188883.3-188884.29" *)
  reg [63:0] _071_;
  (* src = "libresoc.v:189288.3-189297.6" *)
  reg [63:0] _072_;
  (* src = "libresoc.v:188881.3-188882.29" *)
  reg [63:0] _073_;
  (* src = "libresoc.v:189298.3-189307.6" *)
  reg _074_;
  (* src = "libresoc.v:188879.3-188880.29" *)
  reg _075_;
  (* src = "libresoc.v:189308.3-189317.6" *)
  reg [1:0] _076_;
  (* src = "libresoc.v:188877.3-188878.29" *)
  reg [1:0] _077_;
  (* src = "libresoc.v:189318.3-189327.6" *)
  reg [1:0] _078_;
  (* src = "libresoc.v:188875.3-188876.29" *)
  reg [1:0] _079_;
  (* src = "libresoc.v:188330.7-188330.24" *)
  reg _080_;
  (* src = "libresoc.v:188340.7-188340.26" *)
  reg _081_;
  (* src = "libresoc.v:189337.3-189345.6" *)
  reg _082_;
  (* src = "libresoc.v:188348.7-188348.25" *)
  reg _083_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [13:0] _084_;
  (* src = "libresoc.v:188393.14-188393.49" *)
  reg [13:0] _085_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [31:0] _086_;
  (* src = "libresoc.v:188397.14-188397.43" *)
  reg [31:0] _087_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg [6:0] _088_;
  (* src = "libresoc.v:188476.13-188476.47" *)
  reg [6:0] _089_;
  (* src = "libresoc.v:189123.3-189135.6" *)
  reg _090_;
  (* src = "libresoc.v:188480.7-188480.39" *)
  reg _091_;
  (* src = "libresoc.v:189328.3-189336.6" *)
  reg _092_;
  (* src = "libresoc.v:188498.7-188498.27" *)
  reg _093_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg [63:0] _094_;
  (* src = "libresoc.v:188530.14-188530.47" *)
  reg [63:0] _095_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg _096_;
  (* src = "libresoc.v:188534.7-188534.27" *)
  reg _097_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:188538.14-188538.50" *)
  reg [63:0] _099_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg _100_;
  (* src = "libresoc.v:188542.7-188542.30" *)
  reg _101_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg [63:0] _102_;
  (* src = "libresoc.v:188546.14-188546.51" *)
  reg [63:0] _103_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg _104_;
  (* src = "libresoc.v:188550.7-188550.31" *)
  reg _105_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _106_;
  (* src = "libresoc.v:188554.7-188554.29" *)
  reg _107_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _108_;
  (* src = "libresoc.v:188558.7-188558.32" *)
  reg _109_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg [1:0] _110_;
  (* src = "libresoc.v:188562.13-188562.35" *)
  reg [1:0] _111_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg _112_;
  (* src = "libresoc.v:188566.7-188566.32" *)
  reg _113_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg [1:0] _114_;
  (* src = "libresoc.v:188570.13-188570.35" *)
  reg [1:0] _115_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg _116_;
  (* src = "libresoc.v:188574.7-188574.32" *)
  reg _117_;
  (* src = "libresoc.v:189346.3-189355.6" *)
  reg [63:0] _118_;
  (* src = "libresoc.v:189356.3-189365.6" *)
  reg [63:0] _119_;
  (* src = "libresoc.v:189366.3-189375.6" *)
  reg [63:0] _120_;
  (* src = "libresoc.v:189376.3-189385.6" *)
  reg _121_;
  (* src = "libresoc.v:189386.3-189395.6" *)
  reg [1:0] _122_;
  (* src = "libresoc.v:189396.3-189405.6" *)
  reg [1:0] _123_;
  (* src = "libresoc.v:189078.3-189086.6" *)
  reg _124_;
  (* src = "libresoc.v:188602.7-188602.25" *)
  reg _125_;
  (* src = "libresoc.v:189069.3-189077.6" *)
  reg _126_;
  (* src = "libresoc.v:188606.7-188606.25" *)
  reg _127_;
  (* src = "libresoc.v:189406.3-189414.6" *)
  reg [5:0] _128_;
  (* src = "libresoc.v:188708.13-188708.31" *)
  reg [5:0] _129_;
  (* src = "libresoc.v:189023.3-189032.6" *)
  reg _130_;
  (* src = "libresoc.v:189114.3-189122.6" *)
  reg [5:0] _131_;
  (* src = "libresoc.v:188716.13-188716.32" *)
  reg [5:0] _132_;
  (* src = "libresoc.v:189105.3-189113.6" *)
  reg [5:0] _133_;
  (* src = "libresoc.v:188720.13-188720.32" *)
  reg [5:0] _134_;
  (* src = "libresoc.v:189042.3-189050.6" *)
  reg _135_;
  (* src = "libresoc.v:188732.7-188732.26" *)
  reg _136_;
  (* src = "libresoc.v:189033.3-189041.6" *)
  reg _137_;
  (* src = "libresoc.v:188736.7-188736.26" *)
  reg _138_;
  (* src = "libresoc.v:189060.3-189068.6" *)
  reg _139_;
  (* src = "libresoc.v:188740.7-188740.25" *)
  reg _140_;
  (* src = "libresoc.v:189051.3-189059.6" *)
  reg _141_;
  (* src = "libresoc.v:188744.7-188744.25" *)
  reg _142_;
  (* src = "libresoc.v:189096.3-189104.6" *)
  reg [5:0] _143_;
  (* src = "libresoc.v:188766.13-188766.32" *)
  reg [5:0] _144_;
  (* src = "libresoc.v:189087.3-189095.6" *)
  reg [5:0] _145_;
  (* src = "libresoc.v:188770.13-188770.32" *)
  reg [5:0] _146_;
  (* src = "libresoc.v:189268.3-189277.6" *)
  reg [63:0] _147_;
  (* src = "libresoc.v:188774.14-188774.43" *)
  reg [63:0] _148_;
  (* src = "libresoc.v:189278.3-189287.6" *)
  reg [63:0] _149_;
  (* src = "libresoc.v:188778.14-188778.43" *)
  reg [63:0] _150_;
  (* src = "libresoc.v:189288.3-189297.6" *)
  reg [63:0] _151_;
  (* src = "libresoc.v:188782.14-188782.43" *)
  reg [63:0] _152_;
  (* src = "libresoc.v:189298.3-189307.6" *)
  reg _153_;
  (* src = "libresoc.v:188786.7-188786.20" *)
  reg _154_;
  (* src = "libresoc.v:189308.3-189317.6" *)
  reg [1:0] _155_;
  (* src = "libresoc.v:188790.13-188790.26" *)
  reg [1:0] _156_;
  (* src = "libresoc.v:189318.3-189327.6" *)
  reg [1:0] _157_;
  (* src = "libresoc.v:188794.13-188794.26" *)
  reg [1:0] _158_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg [63:0] _159_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg _160_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg [63:0] _161_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg _162_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg [63:0] _163_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg _164_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _165_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _166_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg [1:0] _167_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg _168_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg [1:0] _169_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg _170_;
  (* src = "libresoc.v:189136.3-189157.6" *)
  reg _171_;
  (* src = "libresoc.v:189158.3-189179.6" *)
  reg _172_;
  (* src = "libresoc.v:189180.3-189201.6" *)
  reg _173_;
  (* src = "libresoc.v:189202.3-189223.6" *)
  reg _174_;
  (* src = "libresoc.v:189224.3-189245.6" *)
  reg _175_;
  (* src = "libresoc.v:189246.3-189267.6" *)
  reg _176_;
  (* src = "libresoc.v:188806.19-188806.133" *)
  wire _177_;
  (* src = "libresoc.v:188807.19-188807.183" *)
  wire [5:0] _178_;
  (* src = "libresoc.v:188808.19-188808.115" *)
  wire [5:0] _179_;
  (* src = "libresoc.v:188810.19-188810.115" *)
  wire [5:0] _180_;
  (* src = "libresoc.v:188811.19-188811.125" *)
  wire _181_;
  (* src = "libresoc.v:188812.19-188812.125" *)
  wire _182_;
  (* src = "libresoc.v:188813.19-188813.125" *)
  wire _183_;
  (* src = "libresoc.v:188814.19-188814.125" *)
  wire _184_;
  (* src = "libresoc.v:188815.19-188815.125" *)
  wire _185_;
  (* src = "libresoc.v:188817.19-188817.125" *)
  wire _186_;
  (* src = "libresoc.v:188818.19-188818.165" *)
  wire [5:0] _187_;
  (* src = "libresoc.v:188819.19-188819.121" *)
  wire [5:0] _188_;
  (* src = "libresoc.v:188820.19-188820.127" *)
  wire _189_;
  (* src = "libresoc.v:188821.19-188821.127" *)
  wire _190_;
  (* src = "libresoc.v:188823.19-188823.127" *)
  wire _191_;
  (* src = "libresoc.v:188824.19-188824.127" *)
  wire _192_;
  (* src = "libresoc.v:188825.19-188825.127" *)
  wire _193_;
  (* src = "libresoc.v:188826.19-188826.127" *)
  wire _194_;
  (* src = "libresoc.v:188827.18-188827.110" *)
  wire _195_;
  (* src = "libresoc.v:188829.18-188829.98" *)
  wire _196_;
  (* src = "libresoc.v:188831.18-188831.100" *)
  wire _197_;
  (* src = "libresoc.v:188832.18-188832.182" *)
  wire [5:0] _198_;
  (* src = "libresoc.v:188834.18-188834.119" *)
  wire [5:0] _199_;
  (* src = "libresoc.v:188837.18-188837.116" *)
  wire _200_;
  (* src = "libresoc.v:188842.18-188842.113" *)
  wire _201_;
  (* src = "libresoc.v:188843.18-188843.125" *)
  wire [5:0] _202_;
  (* src = "libresoc.v:188845.18-188845.112" *)
  wire _203_;
  (* src = "libresoc.v:188847.18-188847.126" *)
  wire _204_;
  (* src = "libresoc.v:188848.18-188848.126" *)
  wire _205_;
  (* src = "libresoc.v:188849.18-188849.117" *)
  wire _206_;
  (* src = "libresoc.v:188854.18-188854.130" *)
  wire _207_;
  (* src = "libresoc.v:188855.17-188855.123" *)
  wire _208_;
  (* src = "libresoc.v:188856.18-188856.124" *)
  wire [5:0] _209_;
  (* src = "libresoc.v:188858.18-188858.116" *)
  wire _210_;
  (* src = "libresoc.v:188859.18-188859.119" *)
  wire _211_;
  (* src = "libresoc.v:188860.18-188860.120" *)
  wire _212_;
  (* src = "libresoc.v:188861.18-188861.121" *)
  wire _213_;
  (* src = "libresoc.v:188862.18-188862.121" *)
  wire _214_;
  (* src = "libresoc.v:188863.18-188863.121" *)
  wire _215_;
  (* src = "libresoc.v:188870.18-188870.134" *)
  wire _216_;
  (* src = "libresoc.v:188844.18-188844.113" *)
  wire _217_;
  (* src = "libresoc.v:188846.18-188846.119" *)
  wire _218_;
  (* src = "libresoc.v:188805.17-188805.113" *)
  wire [5:0] _219_;
  (* src = "libresoc.v:188809.19-188809.115" *)
  wire [5:0] _220_;
  (* src = "libresoc.v:188828.18-188828.97" *)
  wire _221_;
  (* src = "libresoc.v:188830.18-188830.99" *)
  wire _222_;
  (* src = "libresoc.v:188833.18-188833.113" *)
  wire [5:0] _223_;
  (* src = "libresoc.v:188836.18-188836.106" *)
  wire _224_;
  (* src = "libresoc.v:188841.18-188841.120" *)
  wire _225_;
  (* src = "libresoc.v:188816.18-188816.118" *)
  wire [5:0] _226_;
  (* src = "libresoc.v:188840.18-188840.112" *)
  wire _227_;
  (* src = "libresoc.v:188850.18-188850.122" *)
  wire _228_;
  (* src = "libresoc.v:188851.18-188851.124" *)
  wire _229_;
  (* src = "libresoc.v:188852.18-188852.194" *)
  wire [5:0] _230_;
  (* src = "libresoc.v:188853.18-188853.194" *)
  wire [5:0] _231_;
  (* src = "libresoc.v:188857.18-188857.120" *)
  wire [5:0] _232_;
  (* src = "libresoc.v:188822.17-188822.105" *)
  wire _233_;
  (* src = "libresoc.v:188835.18-188835.106" *)
  wire _234_;
  (* src = "libresoc.v:188838.18-188838.113" *)
  wire _235_;
  (* src = "libresoc.v:188839.18-188839.112" *)
  wire _236_;
  (* src = "libresoc.v:188864.18-188864.118" *)
  wire [63:0] _237_;
  (* src = "libresoc.v:188865.18-188865.118" *)
  wire [63:0] _238_;
  (* src = "libresoc.v:188866.18-188866.118" *)
  wire [63:0] _239_;
  (* src = "libresoc.v:188867.18-188867.118" *)
  wire _240_;
  (* src = "libresoc.v:188868.18-188868.118" *)
  wire [1:0] _241_;
  (* src = "libresoc.v:188869.18-188869.118" *)
  wire [1:0] _242_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$104 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$106 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [5:0] \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [5:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$110 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$114 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$116 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [5:0] \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [5:0] \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$18 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [5:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$26 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [5:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [5:0] \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [5:0] \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [5:0] \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [5:0] \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [5:0] \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [5:0] \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$84 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$86 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [5:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$90 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire \$92 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [1:0] \$94 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [1:0] \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [5:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_spr0_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_spr0_fast1$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_spr0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_spr0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_spr0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_spr0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_spr0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_spr0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_spr0_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_spr0_spr1$1 ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_spr0_spr_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_spr0_spr_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_spr0_spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_spr0_spr_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_spr0_spr_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_spr0_spr_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_spr0_spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_spr0_spr_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_spr0_xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \alu_spr0_xer_ca$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [1:0] alu_spr0_xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [1:0] \alu_spr0_xer_ov$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire alu_spr0_xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire \alu_spr0_xer_so$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [5:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [5:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [5:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [5:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r1__spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r1__spr1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__spr1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r2__fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r2__fast1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__xer_so_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__xer_so_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r4__xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r4__xer_ov$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r4__xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r4__xer_ov_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] data_r5__xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [1:0] \data_r5__xer_ca$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r5__xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r5__xer_ca_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest2_o;
  reg [63:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest3_o;
  reg [63:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output dest4_o;
  reg dest4_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest5_o;
  reg [1:0] dest5_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [1:0] dest6_o;
  reg [1:0] dest6_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "libresoc.v:188194.7-188194.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_spr0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_spr0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_spr0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_spr0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [5:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [5:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [5:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [5:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [5:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input src4_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src5_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [1:0] src6_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [5:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [5:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [5:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg src_r3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg \src_r3$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] src_r4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] \src_r4$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] src_r5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [1:0] \src_r5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  assign _177_ = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _178_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _179_ = \$102  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 6'h3f;
  assign _180_ = \$104  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$106 ;
  assign _181_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _182_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _183_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _184_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _185_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _186_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _187_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$110 , \$112 , \$114 , \$116 , \$118 , \$120  };
  assign _188_ = \$122  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _189_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _190_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _191_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _192_ = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _193_ = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _194_ = cu_wr__go_i[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _195_ = \$6  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ;
  assign _196_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$16 ;
  assign _197_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$20 ;
  assign _198_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _199_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$28 ;
  assign _200_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$26 ;
  assign _201_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$42 ;
  assign _202_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _203_ = \$44  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$48 ;
  assign _204_ = \$52  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_spr0_n_ready_i;
  assign _205_ = \$54  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_spr0_n_valid_o;
  assign _206_ = \$56  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _207_ = alu_spr0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _208_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _209_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _210_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _211_ = spr1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _212_ = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _213_ = xer_so_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _214_ = xer_ov_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _215_ = xer_ca_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _216_ = alu_spr0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _217_ = \$46  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _218_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _219_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _220_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _221_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _222_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _223_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _224_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ;
  assign _225_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_spr0_n_ready_i;
  assign _226_ = \$9  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _227_ = \$36  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$38 ;
  assign _228_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _229_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _230_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _231_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _232_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _233_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$11 ;
  assign _234_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$30 ;
  assign _235_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _236_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _237_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _238_ = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1;
  assign _239_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  assign _240_ = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3;
  assign _241_ = src_l_q_src[4] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src5_i : src_r4;
  assign _242_ = src_l_q_src[5] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src6_i : src_r5;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:188945.14-188951.4" *)
  \alu_l$73  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:188952.12-188981.4" *)
  alu_spr0 alu_spr0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .fast1(alu_spr0_fast1),
    .\fast1$2 (\alu_spr0_fast1$2 ),
    .fast1_ok(fast1_ok),
    .n_ready_i(alu_spr0_n_ready_i),
    .n_valid_o(alu_spr0_n_valid_o),
    .o(alu_spr0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_spr0_p_ready_o),
    .p_valid_i(alu_spr0_p_valid_i),
    .ra(alu_spr0_ra),
    .spr1(alu_spr0_spr1),
    .\spr1$1 (\alu_spr0_spr1$1 ),
    .spr1_ok(spr1_ok),
    .spr_op__fn_unit(alu_spr0_spr_op__fn_unit),
    .spr_op__insn(alu_spr0_spr_op__insn),
    .spr_op__insn_type(alu_spr0_spr_op__insn_type),
    .spr_op__is_32bit(alu_spr0_spr_op__is_32bit),
    .xer_ca(alu_spr0_xer_ca),
    .\xer_ca$5 (\alu_spr0_xer_ca$5 ),
    .xer_ca_ok(xer_ca_ok),
    .xer_ov(alu_spr0_xer_ov),
    .\xer_ov$4 (\alu_spr0_xer_ov$4 ),
    .xer_ov_ok(xer_ov_ok),
    .xer_so(alu_spr0_xer_so),
    .\xer_so$3 (\alu_spr0_xer_so$3 ),
    .xer_so_ok(xer_so_ok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:188982.15-188988.4" *)
  \alui_l$72  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:188989.14-188995.4" *)
  \opc_l$68  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:188996.14-189002.4" *)
  \req_l$69  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:189003.14-189009.4" *)
  \rok_l$71  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:189010.14-189015.4" *)
  \rst_l$70  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:189016.14-189022.4" *)
  \src_l$67  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _044_ = 1'h0;
  end
  always @* begin
      \initial  <= _044_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _080_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_spr0_spr_op__fn_unit <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_spr0_spr_op__insn <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_spr0_spr_op__insn_type <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_spr0_spr_op__is_32bit <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r1__spr1 <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__spr1_ok <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r2__fast1 <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__fast1_ok <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__xer_so_ok <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r4__xer_ov <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r4__xer_ov_ok <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      data_r5__xer_ca <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r5__xer_ca_ok <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _132_ = 6'h3f;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _132_;
  end
  always @* begin
    if (\initial ) begin end
    _134_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _134_;
  end
  always @* begin
    if (\initial ) begin end
    _136_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _136_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 6'h3f;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      src_r3 <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src_r4 <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      src_r5 <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \src_r5$next ;
  end
  always @(posedge coresync_clk) begin
      src_r5 <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = \src_r4$next ;
  end
  always @(posedge coresync_clk) begin
      src_r4 <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = \src_r3$next ;
  end
  always @(posedge coresync_clk) begin
      src_r3 <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \data_r5__xer_ca$next ;
  end
  always @(posedge coresync_clk) begin
      data_r5__xer_ca <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \data_r5__xer_ca_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r5__xer_ca_ok <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \data_r4__xer_ov$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__xer_ov <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \data_r4__xer_ov_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__xer_ov_ok <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \data_r3__xer_so$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \data_r3__xer_so_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__xer_so_ok <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \data_r2__fast1$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__fast1 <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \data_r2__fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__fast1_ok <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \data_r1__spr1$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__spr1 <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \data_r1__spr1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__spr1_ok <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_spr0_spr_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_spr0_spr_op__insn_type <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_spr0_spr_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_spr0_spr_op__fn_unit <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_spr0_spr_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_spr0_spr_op__insn <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_spr0_spr_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_spr0_spr_op__is_32bit <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = alu_spr0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$14 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = _130_;
    (* src = "libresoc.v:189024.5-189024.29" *)
    casez (\initial )
      /* src = "libresoc.v:189024.9-189024.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$58 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h1;
        end
      default:
          _130_ = \$50 ;
    endcase
  end
  always @* begin
      req_done <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = _137_;
    (* src = "libresoc.v:189034.5-189034.29" *)
    casez (\initial )
      /* src = "libresoc.v:189034.9-189034.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _137_ = 1'h0;
        end
      default:
          _137_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _135_;
    (* src = "libresoc.v:189043.5-189043.29" *)
    casez (\initial )
      /* src = "libresoc.v:189043.9-189043.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _135_ = 1'h1;
        end
      default:
          _135_ = \$68 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = _141_;
    (* src = "libresoc.v:189052.5-189052.29" *)
    casez (\initial )
      /* src = "libresoc.v:189052.9-189052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 1'h0;
        end
      default:
          _141_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = _139_;
    (* src = "libresoc.v:189061.5-189061.29" *)
    casez (\initial )
      /* src = "libresoc.v:189061.9-189061.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _139_ = 1'h1;
        end
      default:
          _139_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _126_;
    (* src = "libresoc.v:189070.5-189070.29" *)
    casez (\initial )
      /* src = "libresoc.v:189070.9-189070.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = 1'h0;
        end
      default:
          _126_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = _124_;
    (* src = "libresoc.v:189079.5-189079.29" *)
    casez (\initial )
      /* src = "libresoc.v:189079.9-189079.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _124_ = 1'h1;
        end
      default:
          _124_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = _145_;
    (* src = "libresoc.v:189088.5-189088.29" *)
    casez (\initial )
      /* src = "libresoc.v:189088.9-189088.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 6'h00;
        end
      default:
          _145_ = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = _143_;
    (* src = "libresoc.v:189097.5-189097.29" *)
    casez (\initial )
      /* src = "libresoc.v:189097.9-189097.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 6'h3f;
        end
      default:
          _143_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _133_;
    (* src = "libresoc.v:189106.5-189106.29" *)
    casez (\initial )
      /* src = "libresoc.v:189106.9-189106.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _133_ = 6'h00;
        end
      default:
          _133_ = \$70 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = _131_;
    (* src = "libresoc.v:189115.5-189115.29" *)
    casez (\initial )
      /* src = "libresoc.v:189115.9-189115.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _131_ = 6'h3f;
        end
      default:
          _131_ = \$72 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _084_;
    _006_ = _086_;
    _008_ = _088_;
    _010_ = _090_;
    (* src = "libresoc.v:189124.5-189124.29" *)
    casez (\initial )
      /* src = "libresoc.v:189124.9-189124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _090_, _086_, _084_, _088_ } = { oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__insn, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn_type };
        end
      default:
        begin
          _084_ = alu_spr0_spr_op__fn_unit;
          _086_ = alu_spr0_spr_op__insn;
          _088_ = alu_spr0_spr_op__insn_type;
          _090_ = alu_spr0_spr_op__is_32bit;
        end
    endcase
  end
  always @* begin
      \alu_spr0_spr_op__fn_unit$next  <= _004_;
      \alu_spr0_spr_op__insn$next  <= _006_;
      \alu_spr0_spr_op__insn_type$next  <= _008_;
      \alu_spr0_spr_op__is_32bit$next  <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _159_;
    _016_ = _171_;
    (* src = "libresoc.v:189137.5-189137.29" *)
    casez (\initial )
      /* src = "libresoc.v:189137.9-189137.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _096_, _094_ } = { o_ok, alu_spr0_o };
        end
      default:
        begin
          _094_ = data_r0__o;
          _096_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _160_, _159_ } = 65'h00000000000000000;
        end
      default:
        begin
          _159_ = _094_;
          _160_ = _096_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 1'h0;
        end
      default:
          _171_ = _160_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _014_;
      \data_r0__o_ok$next  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _161_;
    _020_ = _172_;
    (* src = "libresoc.v:189159.5-189159.29" *)
    casez (\initial )
      /* src = "libresoc.v:189159.9-189159.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _100_, _098_ } = { spr1_ok, alu_spr0_spr1 };
        end
      default:
        begin
          _098_ = data_r1__spr1;
          _100_ = data_r1__spr1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _162_, _161_ } = 65'h00000000000000000;
        end
      default:
        begin
          _161_ = _098_;
          _162_ = _100_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _172_ = 1'h0;
        end
      default:
          _172_ = _162_;
    endcase
  end
  always @* begin
      \data_r1__spr1$next  <= _018_;
      \data_r1__spr1_ok$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _163_;
    _024_ = _173_;
    (* src = "libresoc.v:189181.5-189181.29" *)
    casez (\initial )
      /* src = "libresoc.v:189181.9-189181.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _104_, _102_ } = { fast1_ok, alu_spr0_fast1 };
        end
      default:
        begin
          _102_ = data_r2__fast1;
          _104_ = data_r2__fast1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _164_, _163_ } = 65'h00000000000000000;
        end
      default:
        begin
          _163_ = _102_;
          _164_ = _104_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 1'h0;
        end
      default:
          _173_ = _164_;
    endcase
  end
  always @* begin
      \data_r2__fast1$next  <= _022_;
      \data_r2__fast1_ok$next  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _165_;
    _028_ = _174_;
    (* src = "libresoc.v:189203.5-189203.29" *)
    casez (\initial )
      /* src = "libresoc.v:189203.9-189203.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _108_, _106_ } = { xer_so_ok, alu_spr0_xer_so };
        end
      default:
        begin
          _106_ = data_r3__xer_so;
          _108_ = data_r3__xer_so_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _166_, _165_ } = 2'h0;
        end
      default:
        begin
          _165_ = _106_;
          _166_ = _108_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _174_ = 1'h0;
        end
      default:
          _174_ = _166_;
    endcase
  end
  always @* begin
      \data_r3__xer_so$next  <= _026_;
      \data_r3__xer_so_ok$next  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _167_;
    _032_ = _175_;
    (* src = "libresoc.v:189225.5-189225.29" *)
    casez (\initial )
      /* src = "libresoc.v:189225.9-189225.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _112_, _110_ } = { xer_ov_ok, alu_spr0_xer_ov };
        end
      default:
        begin
          _110_ = data_r4__xer_ov;
          _112_ = data_r4__xer_ov_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _168_, _167_ } = 3'h0;
        end
      default:
        begin
          _167_ = _110_;
          _168_ = _112_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 1'h0;
        end
      default:
          _175_ = _168_;
    endcase
  end
  always @* begin
      \data_r4__xer_ov$next  <= _030_;
      \data_r4__xer_ov_ok$next  <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = _169_;
    _036_ = _176_;
    (* src = "libresoc.v:189247.5-189247.29" *)
    casez (\initial )
      /* src = "libresoc.v:189247.9-189247.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _116_, _114_ } = { xer_ca_ok, alu_spr0_xer_ca };
        end
      default:
        begin
          _114_ = data_r5__xer_ca;
          _116_ = data_r5__xer_ca_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _170_, _169_ } = 3'h0;
        end
      default:
        begin
          _169_ = _114_;
          _170_ = _116_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _176_ = 1'h0;
        end
      default:
          _176_ = _170_;
    endcase
  end
  always @* begin
      \data_r5__xer_ca$next  <= _034_;
      \data_r5__xer_ca_ok$next  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = _147_;
    (* src = "libresoc.v:189269.5-189269.29" *)
    casez (\initial )
      /* src = "libresoc.v:189269.9-189269.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = src1_i;
        end
      default:
          _147_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = _149_;
    (* src = "libresoc.v:189279.5-189279.29" *)
    casez (\initial )
      /* src = "libresoc.v:189279.9-189279.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[1])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _149_ = src2_i;
        end
      default:
          _149_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = _151_;
    (* src = "libresoc.v:189289.5-189289.29" *)
    casez (\initial )
      /* src = "libresoc.v:189289.9-189289.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = src3_i;
        end
      default:
          _151_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = _153_;
    (* src = "libresoc.v:189299.5-189299.29" *)
    casez (\initial )
      /* src = "libresoc.v:189299.9-189299.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[3])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = src4_i;
        end
      default:
          _153_ = src_r3;
    endcase
  end
  always @* begin
      \src_r3$next  <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = _155_;
    (* src = "libresoc.v:189309.5-189309.29" *)
    casez (\initial )
      /* src = "libresoc.v:189309.9-189309.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[4])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _155_ = src5_i;
        end
      default:
          _155_ = src_r4;
    endcase
  end
  always @* begin
      \src_r4$next  <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = _157_;
    (* src = "libresoc.v:189319.5-189319.29" *)
    casez (\initial )
      /* src = "libresoc.v:189319.9-189319.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[5])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = src6_i;
        end
      default:
          _157_ = src_r5;
    endcase
  end
  always @* begin
      \src_r5$next  <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _092_;
    (* src = "libresoc.v:189329.5-189329.29" *)
    casez (\initial )
      /* src = "libresoc.v:189329.9-189329.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _092_ = 1'h1;
        end
      default:
          _092_ = \$98 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _082_;
    (* src = "libresoc.v:189338.5-189338.29" *)
    casez (\initial )
      /* src = "libresoc.v:189338.9-189338.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _082_ = 1'h1;
        end
      default:
          _082_ = \$100 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _118_;
    (* src = "libresoc.v:189347.5-189347.29" *)
    casez (\initial )
      /* src = "libresoc.v:189347.9-189347.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$126 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _118_ = data_r0__o;
        end
      default:
          _118_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = _119_;
    (* src = "libresoc.v:189357.5-189357.29" *)
    casez (\initial )
      /* src = "libresoc.v:189357.9-189357.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$128 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _119_ = data_r1__spr1;
        end
      default:
          _119_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest2_o <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _120_;
    (* src = "libresoc.v:189367.5-189367.29" *)
    casez (\initial )
      /* src = "libresoc.v:189367.9-189367.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$130 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _120_ = data_r2__fast1;
        end
      default:
          _120_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest3_o <= _040_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _121_;
    (* src = "libresoc.v:189377.5-189377.29" *)
    casez (\initial )
      /* src = "libresoc.v:189377.9-189377.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$132 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _121_ = data_r3__xer_so;
        end
      default:
          _121_ = 1'h0;
    endcase
  end
  always @* begin
      dest4_o <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = _122_;
    (* src = "libresoc.v:189387.5-189387.29" *)
    casez (\initial )
      /* src = "libresoc.v:189387.9-189387.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$134 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _122_ = data_r4__xer_ov;
        end
      default:
          _122_ = 2'h0;
    endcase
  end
  always @* begin
      dest5_o <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _123_;
    (* src = "libresoc.v:189397.5-189397.29" *)
    casez (\initial )
      /* src = "libresoc.v:189397.9-189397.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$136 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _123_ = data_r5__xer_ca;
        end
      default:
          _123_ = 2'h0;
    endcase
  end
  always @* begin
      dest6_o <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = _128_;
    (* src = "libresoc.v:189407.5-189407.29" *)
    casez (\initial )
      /* src = "libresoc.v:189407.9-189407.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = 6'h00;
        end
      default:
          _128_ = \$24 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _049_;
  end
  assign \$9  = _219_;
  assign \$100  = _177_;
  assign \$102  = _178_;
  assign \$104  = _179_;
  assign \$106  = _220_;
  assign \$108  = _180_;
  assign \$110  = _181_;
  assign \$112  = _182_;
  assign \$114  = _183_;
  assign \$116  = _184_;
  assign \$118  = _185_;
  assign \$11  = _226_;
  assign \$120  = _186_;
  assign \$122  = _187_;
  assign \$124  = _188_;
  assign \$126  = _189_;
  assign \$128  = _190_;
  assign \$8  = _233_;
  assign \$130  = _191_;
  assign \$132  = _192_;
  assign \$134  = _193_;
  assign \$136  = _194_;
  assign \$14  = _195_;
  assign \$16  = _221_;
  assign \$18  = _196_;
  assign \$20  = _222_;
  assign \$22  = _197_;
  assign \$24  = _198_;
  assign \$28  = _223_;
  assign \$30  = _199_;
  assign \$27  = _234_;
  assign \$26  = _224_;
  assign \$34  = _200_;
  assign \$36  = _235_;
  assign \$38  = _236_;
  assign \$40  = _227_;
  assign \$42  = _225_;
  assign \$44  = _201_;
  assign \$46  = _202_;
  assign \$48  = _217_;
  assign \$50  = _203_;
  assign \$52  = _218_;
  assign \$54  = _204_;
  assign \$56  = _205_;
  assign \$58  = _206_;
  assign \$60  = _228_;
  assign \$62  = _229_;
  assign \$64  = _230_;
  assign \$66  = _231_;
  assign \$68  = _207_;
  assign \$6  = _208_;
  assign \$70  = _209_;
  assign \$72  = _232_;
  assign \$74  = _210_;
  assign \$76  = _211_;
  assign \$78  = _212_;
  assign \$80  = _213_;
  assign \$82  = _214_;
  assign \$84  = _215_;
  assign \$86  = _237_;
  assign \$88  = _238_;
  assign \$90  = _239_;
  assign \$92  = _240_;
  assign \$94  = _241_;
  assign \$96  = _242_;
  assign \$98  = _216_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$124 ;
  assign cu_rd__rel_o = \$108 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_spr0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_spr0_p_valid_i = alui_l_q_alui;
  assign \alu_spr0_xer_ca$5  = \$96 ;
  assign \alu_spr0_xer_ov$4  = \$94 ;
  assign \alu_spr0_xer_so$3  = \$92 ;
  assign \alu_spr0_fast1$2  = \$90 ;
  assign \alu_spr0_spr1$1  = \$88 ;
  assign alu_spr0_ra = \$86 ;
  assign cu_wrmask_o = { \$84 , \$82 , \$80 , \$78 , \$76 , \$74  };
  assign reset_r = \$66 ;
  assign reset_w = \$64 ;
  assign rst_r = \$62 ;
  assign reset = \$60 ;
  assign wr_any = \$40 ;
  assign cu_done_o = \$34 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$22 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_spr0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$18 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$14 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:189450.1-189974.10" *)
module spr_main(spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, ra, spr1, fast1, xer_so, xer_ov, xer_ca, \muxid$1 , \spr_op__insn_type$2 , \spr_op__fn_unit$3 , \spr_op__insn$4 , \spr_op__is_32bit$5 , o, o_ok, \spr1$6 , spr1_ok, \fast1$7 , fast1_ok, \xer_so$8 , xer_so_ok, \xer_ov$9 , xer_ov_ok, \xer_ca$10 , xer_ca_ok, muxid);
  reg \initial  = 0;
  (* src = "libresoc.v:189723.3-189738.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:189804.3-189819.6" *)
  reg _01_;
  (* src = "libresoc.v:189451.7-189451.20" *)
  reg _02_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg [63:0] _03_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg _04_;
  (* src = "libresoc.v:189952.3-189970.6" *)
  reg [63:0] _05_;
  (* src = "libresoc.v:189739.3-189757.6" *)
  reg _06_;
  (* src = "libresoc.v:189907.3-189930.6" *)
  reg [1:0] _07_;
  (* src = "libresoc.v:189931.3-189951.6" *)
  reg _08_;
  (* src = "libresoc.v:189862.3-189885.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:189886.3-189906.6" *)
  reg _10_;
  (* src = "libresoc.v:189820.3-189840.6" *)
  reg _11_;
  (* src = "libresoc.v:189841.3-189861.6" *)
  reg _12_;
  (* src = "libresoc.v:189723.3-189738.6" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:189804.3-189819.6" *)
  reg _14_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg [63:0] _15_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg _16_;
  (* src = "libresoc.v:189952.3-189970.6" *)
  reg [63:0] _17_;
  (* src = "libresoc.v:189739.3-189757.6" *)
  reg _18_;
  (* src = "libresoc.v:189907.3-189930.6" *)
  reg [1:0] _19_;
  (* src = "libresoc.v:189931.3-189951.6" *)
  reg _20_;
  (* src = "libresoc.v:189862.3-189885.6" *)
  reg [1:0] _21_;
  (* src = "libresoc.v:189886.3-189906.6" *)
  reg _22_;
  (* src = "libresoc.v:189820.3-189840.6" *)
  reg _23_;
  (* src = "libresoc.v:189841.3-189861.6" *)
  reg _24_;
  (* src = "libresoc.v:189723.3-189738.6" *)
  reg [63:0] _25_;
  (* src = "libresoc.v:189804.3-189819.6" *)
  reg _26_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg [63:0] _27_;
  (* src = "libresoc.v:189952.3-189970.6" *)
  reg [63:0] _28_;
  (* src = "libresoc.v:189739.3-189757.6" *)
  reg _29_;
  (* src = "libresoc.v:189907.3-189930.6" *)
  reg [1:0] _30_;
  (* src = "libresoc.v:189931.3-189951.6" *)
  reg _31_;
  (* src = "libresoc.v:189862.3-189885.6" *)
  reg [1:0] _32_;
  (* src = "libresoc.v:189886.3-189906.6" *)
  reg _33_;
  (* src = "libresoc.v:189820.3-189840.6" *)
  reg _34_;
  (* src = "libresoc.v:189841.3-189861.6" *)
  reg _35_;
  (* src = "libresoc.v:189758.3-189803.6" *)
  reg [45:0] _36_;
  (* src = "libresoc.v:189907.3-189930.6" *)
  reg [1:0] _37_;
  (* src = "libresoc.v:189931.3-189951.6" *)
  reg _38_;
  (* src = "libresoc.v:189862.3-189885.6" *)
  reg [1:0] _39_;
  (* src = "libresoc.v:189886.3-189906.6" *)
  reg _40_;
  (* src = "libresoc.v:189820.3-189840.6" *)
  reg _41_;
  (* src = "libresoc.v:189841.3-189861.6" *)
  reg _42_;
  (* src = "libresoc.v:189716.18-189716.106" *)
  wire _43_;
  (* src = "libresoc.v:189717.18-189717.106" *)
  wire _44_;
  (* src = "libresoc.v:189718.18-189718.106" *)
  wire _45_;
  (* src = "libresoc.v:189719.18-189719.106" *)
  wire _46_;
  (* src = "libresoc.v:189720.18-189720.106" *)
  wire _47_;
  (* src = "libresoc.v:189721.18-189721.106" *)
  wire _48_;
  (* src = "libresoc.v:189722.18-189722.106" *)
  wire _49_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \fast1$7 ;
  reg [63:0] \fast1$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  reg fast1_ok;
  (* src = "libresoc.v:189451.7-189451.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  input [1:0] muxid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" *)
  output [1:0] \muxid$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] o;
  reg [63:0] o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  reg o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:50" *)
  wire [9:0] spr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [63:0] spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [63:0] \spr1$6 ;
  reg [63:0] \spr1$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr1_ok;
  reg spr1_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] spr_op__fn_unit;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [13:0] \spr_op__fn_unit$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] spr_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [31:0] \spr_op__insn$4 ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] spr_op__insn_type;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output [6:0] \spr_op__insn_type$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input spr_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  output \spr_op__is_32bit$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ca;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ca$10 ;
  reg [1:0] \xer_ca$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ca_ok;
  reg xer_ca_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input [1:0] xer_ov;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [1:0] \xer_ov$9 ;
  reg [1:0] \xer_ov$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_ov_ok;
  reg xer_ov_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  input xer_so;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output \xer_so$8 ;
  reg \xer_so$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output xer_so_ok;
  reg xer_so_ok;
  assign _43_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _44_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _45_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _46_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _47_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _48_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *) 10'h001;
  assign _49_ = spr == (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *) 10'h001;
  always @* begin
    if (\initial ) begin end
    _02_ = 1'h0;
  end
  always @* begin
      \initial  <= _02_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _13_;
    (* src = "libresoc.v:189724.5-189724.29" *)
    casez (\initial )
      /* src = "libresoc.v:189724.9-189724.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _13_ = _25_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _25_ = ra;
              end
            default:
                _25_ = 64'h0000000000000000;
          endcase
        end
      default:
          _13_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \fast1$7  <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _18_;
    (* src = "libresoc.v:189740.5-189740.29" *)
    casez (\initial )
      /* src = "libresoc.v:189740.9-189740.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _18_ = _29_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
                _29_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _29_ = 1'h1;
              end
          endcase
        end
      default:
          _18_ = 1'h0;
    endcase
  end
  always @* begin
      spr1_ok <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _16_;
    _03_ = _15_;
    (* src = "libresoc.v:189759.5-189759.29" *)
    casez (\initial )
      /* src = "libresoc.v:189759.9-189759.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _16_ = 1'h0;
          _15_ = 64'h0000000000000000;
        end
      /* src = "libresoc.v:0.0-0.0" */
      7'h2e:
        begin
          _16_ = 1'h1;
          _15_ = _27_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:85" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016, 10'h10c:
              begin
                _27_[17:0] = fast1[17:0];
                _27_[63:18] = _36_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:90" *)
                casez (\$23 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _36_[45:14] = 32'd0;
                      _36_[10:2] = 9'h000;
                      _36_[13] = xer_so;
                      _36_[12] = xer_ov[0];
                      _36_[1] = xer_ov[1];
                      _36_[11] = xer_ca[0];
                      _36_[0] = xer_ca[1];
                    end
                  default:
                      _36_ = fast1[63:18];
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            10'h10d:
              begin
                _27_[63:32] = 32'd0;
                _27_[31:0] = fast1[63:32];
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _27_ = spr1;
              end
          endcase
        end
      default:
        begin
          _16_ = 1'h0;
          _15_ = 64'h0000000000000000;
        end
    endcase
  end
  always @* begin
      o_ok <= _04_;
      o <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _14_;
    (* src = "libresoc.v:189805.5-189805.29" *)
    casez (\initial )
      /* src = "libresoc.v:189805.9-189805.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _14_ = _26_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _26_ = 1'h1;
              end
            default:
                _26_ = 1'h0;
          endcase
        end
      default:
          _14_ = 1'h0;
    endcase
  end
  always @* begin
      fast1_ok <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _23_;
    (* src = "libresoc.v:189821.5-189821.29" *)
    casez (\initial )
      /* src = "libresoc.v:189821.9-189821.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _23_ = _34_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _34_ = _41_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$11 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _41_ = ra[31];
                    end
                  default:
                      _41_ = 1'h0;
                endcase
              end
            default:
                _34_ = 1'h0;
          endcase
        end
      default:
          _23_ = 1'h0;
    endcase
  end
  always @* begin
      \xer_so$8  <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _12_ = _24_;
    (* src = "libresoc.v:189842.5-189842.29" *)
    casez (\initial )
      /* src = "libresoc.v:189842.9-189842.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _24_ = _35_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _35_ = _42_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$13 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _42_ = 1'h1;
                    end
                  default:
                      _42_ = 1'h0;
                endcase
              end
            default:
                _35_ = 1'h0;
          endcase
        end
      default:
          _24_ = 1'h0;
    endcase
  end
  always @* begin
      xer_so_ok <= _12_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _21_;
    (* src = "libresoc.v:189863.5-189863.29" *)
    casez (\initial )
      /* src = "libresoc.v:189863.9-189863.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _21_ = _32_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _32_ = _39_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$15 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _39_[0] = ra[30];
                      _39_[1] = ra[19];
                    end
                  default:
                      _39_ = 2'h0;
                endcase
              end
            default:
                _32_ = 2'h0;
          endcase
        end
      default:
          _21_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ov$9  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _22_;
    (* src = "libresoc.v:189887.5-189887.29" *)
    casez (\initial )
      /* src = "libresoc.v:189887.9-189887.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _22_ = _33_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _33_ = _40_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$17 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _40_ = 1'h1;
                    end
                  default:
                      _40_ = 1'h0;
                endcase
              end
            default:
                _33_ = 1'h0;
          endcase
        end
      default:
          _22_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ov_ok <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _19_;
    (* src = "libresoc.v:189908.5-189908.29" *)
    casez (\initial )
      /* src = "libresoc.v:189908.9-189908.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _19_ = _30_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _30_ = _37_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$19 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _37_[0] = ra[29];
                      _37_[1] = ra[18];
                    end
                  default:
                      _37_ = 2'h0;
                endcase
              end
            default:
                _30_ = 2'h0;
          endcase
        end
      default:
          _19_ = 2'h0;
    endcase
  end
  always @* begin
      \xer_ca$10  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = _20_;
    (* src = "libresoc.v:189932.5-189932.29" *)
    casez (\initial )
      /* src = "libresoc.v:189932.9-189932.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _20_ = _31_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
              begin
                _31_ = _38_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:64" *)
                casez (\$21 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _38_ = 1'h1;
                    end
                  default:
                      _38_ = 1'h0;
                endcase
              end
            default:
                _31_ = 1'h0;
          endcase
        end
      default:
          _20_ = 1'h0;
    endcase
  end
  always @* begin
      xer_ca_ok <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = _17_;
    (* src = "libresoc.v:189953.5-189953.29" *)
    casez (\initial )
      /* src = "libresoc.v:189953.9-189953.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:54" *)
    casez (spr_op__insn_type)
      /* src = "libresoc.v:0.0-0.0" */
      7'h31:
        begin
          _17_ = _28_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:57" *)
          casez (spr)
            /* src = "libresoc.v:0.0-0.0" */
            10'h009, 10'h008, 10'h32f, 10'h01a, 10'h01b, 10'h001, 10'h016:
                _28_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _28_ = ra;
              end
          endcase
        end
      default:
          _17_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \spr1$6  <= _05_;
  end
  assign \$11  = _43_;
  assign \$13  = _44_;
  assign \$15  = _45_;
  assign \$17  = _46_;
  assign \$19  = _47_;
  assign \$21  = _48_;
  assign \$23  = _49_;
  assign { \spr_op__is_32bit$5 , \spr_op__insn$4 , \spr_op__fn_unit$3 , \spr_op__insn_type$2  } = { spr_op__is_32bit, spr_op__insn, spr_op__fn_unit, spr_op__insn_type };
  assign \muxid$1  = muxid;
  assign spr = { spr_op__insn[15:11], spr_op__insn[20:16] };
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_a.sprmap" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:189978.1-191444.10" *)
module sprmap(spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i);
  reg \initial  = 0;
  (* src = "libresoc.v:190108.3-190429.6" *)
  reg [2:0] _0_;
  (* src = "libresoc.v:190430.3-190751.6" *)
  reg _1_;
  (* src = "libresoc.v:189979.7-189979.20" *)
  reg _2_;
  (* src = "libresoc.v:190752.3-191097.6" *)
  reg [9:0] _3_;
  (* src = "libresoc.v:191098.3-191443.6" *)
  reg _4_;
  (* src = "libresoc.v:190108.3-190429.6" *)
  reg [2:0] _5_;
  (* src = "libresoc.v:190430.3-190751.6" *)
  reg _6_;
  (* src = "libresoc.v:190752.3-191097.6" *)
  reg [9:0] _7_;
  (* src = "libresoc.v:191098.3-191443.6" *)
  reg _8_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_o;
  reg [2:0] fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_o_ok;
  reg fast_o_ok;
  (* src = "libresoc.v:189979.7-189979.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *)
  input [9:0] spr_i;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spr_o;
  reg [9:0] spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr_o_ok;
  reg spr_o_ok;
  always @* begin
    if (\initial ) begin end
    _2_ = 1'h0;
  end
  always @* begin
      \initial  <= _2_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _5_;
    (* src = "libresoc.v:190109.5-190109.29" *)
    casez (\initial )
      /* src = "libresoc.v:190109.9-190109.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
        begin
          _5_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
        begin
          _5_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
        begin
          _5_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
        begin
          _5_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
        begin
          _5_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
        begin
          _5_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
        begin
          _5_ = 3'h7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
        begin
          _5_ = 3'h2;
        end
      default:
          _5_ = 3'h0;
    endcase
  end
  always @* begin
      fast_o <= _0_;
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _6_;
    (* src = "libresoc.v:190431.5-190431.29" *)
    casez (\initial )
      /* src = "libresoc.v:190431.9-190431.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
        begin
          _6_ = 1'h1;
        end
      default:
          _6_ = 1'h0;
    endcase
  end
  always @* begin
      fast_o_ok <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _3_ = _7_;
    (* src = "libresoc.v:190753.5-190753.29" *)
    casez (\initial )
      /* src = "libresoc.v:190753.9-190753.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
        begin
          _7_ = 10'h001;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
        begin
          _7_ = 10'h004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
        begin
          _7_ = 10'h005;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _7_ = 10'h006;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
        begin
          _7_ = 10'h007;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
        begin
          _7_ = 10'h00b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
        begin
          _7_ = 10'h00c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
        begin
          _7_ = 10'h00d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
        begin
          _7_ = 10'h00e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
        begin
          _7_ = 10'h00f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _7_ = 10'h010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
        begin
          _7_ = 10'h011;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
        begin
          _7_ = 10'h012;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
        begin
          _7_ = 10'h013;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
        begin
          _7_ = 10'h014;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
        begin
          _7_ = 10'h015;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
        begin
          _7_ = 10'h016;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
        begin
          _7_ = 10'h017;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
        begin
          _7_ = 10'h018;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
        begin
          _7_ = 10'h019;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
        begin
          _7_ = 10'h01a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
        begin
          _7_ = 10'h01b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
        begin
          _7_ = 10'h01c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
        begin
          _7_ = 10'h01d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
        begin
          _7_ = 10'h01e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
        begin
          _7_ = 10'h01f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
        begin
          _7_ = 10'h020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
        begin
          _7_ = 10'h021;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
        begin
          _7_ = 10'h023;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
        begin
          _7_ = 10'h024;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
        begin
          _7_ = 10'h025;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _7_ = 10'h026;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
        begin
          _7_ = 10'h027;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
        begin
          _7_ = 10'h028;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
        begin
          _7_ = 10'h029;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
        begin
          _7_ = 10'h02a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
        begin
          _7_ = 10'h02b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
        begin
          _7_ = 10'h02c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
        begin
          _7_ = 10'h02d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
        begin
          _7_ = 10'h02e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
        begin
          _7_ = 10'h02f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
        begin
          _7_ = 10'h030;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
        begin
          _7_ = 10'h031;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
        begin
          _7_ = 10'h032;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
        begin
          _7_ = 10'h033;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
        begin
          _7_ = 10'h034;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
        begin
          _7_ = 10'h035;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
        begin
          _7_ = 10'h036;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
        begin
          _7_ = 10'h037;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
        begin
          _7_ = 10'h038;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
        begin
          _7_ = 10'h039;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
        begin
          _7_ = 10'h03a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
        begin
          _7_ = 10'h03b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
        begin
          _7_ = 10'h03c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
        begin
          _7_ = 10'h03d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
        begin
          _7_ = 10'h03e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
        begin
          _7_ = 10'h03f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
        begin
          _7_ = 10'h040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
        begin
          _7_ = 10'h041;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
        begin
          _7_ = 10'h042;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
        begin
          _7_ = 10'h043;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
        begin
          _7_ = 10'h044;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
        begin
          _7_ = 10'h045;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
        begin
          _7_ = 10'h046;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
        begin
          _7_ = 10'h047;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
        begin
          _7_ = 10'h048;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
        begin
          _7_ = 10'h049;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
        begin
          _7_ = 10'h04a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
        begin
          _7_ = 10'h04b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
        begin
          _7_ = 10'h04c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
        begin
          _7_ = 10'h04d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
        begin
          _7_ = 10'h04e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
        begin
          _7_ = 10'h04f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
        begin
          _7_ = 10'h050;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
        begin
          _7_ = 10'h051;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
        begin
          _7_ = 10'h052;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
        begin
          _7_ = 10'h053;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
        begin
          _7_ = 10'h054;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
        begin
          _7_ = 10'h055;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
        begin
          _7_ = 10'h056;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
        begin
          _7_ = 10'h057;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
        begin
          _7_ = 10'h058;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
        begin
          _7_ = 10'h059;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
        begin
          _7_ = 10'h05a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
        begin
          _7_ = 10'h05b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
        begin
          _7_ = 10'h05c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
        begin
          _7_ = 10'h05d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
        begin
          _7_ = 10'h05e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
        begin
          _7_ = 10'h05f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
        begin
          _7_ = 10'h060;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
        begin
          _7_ = 10'h061;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
        begin
          _7_ = 10'h062;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
        begin
          _7_ = 10'h063;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
        begin
          _7_ = 10'h064;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
        begin
          _7_ = 10'h065;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
        begin
          _7_ = 10'h066;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
        begin
          _7_ = 10'h067;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h330:
        begin
          _7_ = 10'h069;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h337:
        begin
          _7_ = 10'h06a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h350:
        begin
          _7_ = 10'h06b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h351:
        begin
          _7_ = 10'h06c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h357:
        begin
          _7_ = 10'h06d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h380:
        begin
          _7_ = 10'h06e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h382:
        begin
          _7_ = 10'h06f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h3ff:
        begin
          _7_ = 10'h070;
        end
      default:
          _7_ = 10'h000;
    endcase
  end
  always @* begin
      spr_o <= _3_;
  end
  always @* begin
    if (\initial ) begin end
    _4_ = _8_;
    (* src = "libresoc.v:191099.5-191099.29" *)
    casez (\initial )
      /* src = "libresoc.v:191099.9-191099.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h330:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h337:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h350:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h351:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h357:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h380:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h382:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h3ff:
        begin
          _8_ = 1'h1;
        end
      default:
          _8_ = 1'h0;
    endcase
  end
  always @* begin
      spr_o_ok <= _4_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.dec2.dec_o.sprmap" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:191448.1-192914.10" *)
module \sprmap$174 (spr_o, spr_o_ok, fast_o, fast_o_ok, spr_i);
  reg \initial  = 0;
  (* src = "libresoc.v:191578.3-191899.6" *)
  reg [2:0] _0_;
  (* src = "libresoc.v:191900.3-192221.6" *)
  reg _1_;
  (* src = "libresoc.v:191449.7-191449.20" *)
  reg _2_;
  (* src = "libresoc.v:192222.3-192567.6" *)
  reg [9:0] _3_;
  (* src = "libresoc.v:192568.3-192913.6" *)
  reg _4_;
  (* src = "libresoc.v:191578.3-191899.6" *)
  reg [2:0] _5_;
  (* src = "libresoc.v:191900.3-192221.6" *)
  reg _6_;
  (* src = "libresoc.v:192222.3-192567.6" *)
  reg [9:0] _7_;
  (* src = "libresoc.v:192568.3-192913.6" *)
  reg _8_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [2:0] fast_o;
  reg [2:0] fast_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast_o_ok;
  reg fast_o_ok;
  (* src = "libresoc.v:191449.7-191449.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76" *)
  input [9:0] spr_i;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output [9:0] spr_o;
  reg [9:0] spr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output spr_o_ok;
  reg spr_o_ok;
  always @* begin
    if (\initial ) begin end
    _2_ = 1'h0;
  end
  always @* begin
      \initial  <= _2_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _0_ = _5_;
    (* src = "libresoc.v:191579.5-191579.29" *)
    casez (\initial )
      /* src = "libresoc.v:191579.9-191579.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
        begin
          _5_ = 3'h5;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
        begin
          _5_ = 3'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
        begin
          _5_ = 3'h0;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
        begin
          _5_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
        begin
          _5_ = 3'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
        begin
          _5_ = 3'h4;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
        begin
          _5_ = 3'h7;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
          _5_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
        begin
          _5_ = 3'h2;
        end
      default:
          _5_ = 3'h0;
    endcase
  end
  always @* begin
      fast_o <= _0_;
  end
  always @* begin
    if (\initial ) begin end
    _1_ = _6_;
    (* src = "libresoc.v:191901.5-191901.29" *)
    casez (\initial )
      /* src = "libresoc.v:191901.9-191901.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
        begin
          _6_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
          _6_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
        begin
          _6_ = 1'h1;
        end
      default:
          _6_ = 1'h0;
    endcase
  end
  always @* begin
      fast_o_ok <= _1_;
  end
  always @* begin
    if (\initial ) begin end
    _3_ = _7_;
    (* src = "libresoc.v:192223.5-192223.29" *)
    casez (\initial )
      /* src = "libresoc.v:192223.9-192223.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
        begin
          _7_ = 10'h001;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
        begin
          _7_ = 10'h004;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
        begin
          _7_ = 10'h005;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _7_ = 10'h006;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
        begin
          _7_ = 10'h007;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
        begin
          _7_ = 10'h00b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
        begin
          _7_ = 10'h00c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
        begin
          _7_ = 10'h00d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
        begin
          _7_ = 10'h00e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
        begin
          _7_ = 10'h00f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _7_ = 10'h010;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
        begin
          _7_ = 10'h011;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
        begin
          _7_ = 10'h012;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
        begin
          _7_ = 10'h013;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
        begin
          _7_ = 10'h014;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
        begin
          _7_ = 10'h015;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
        begin
          _7_ = 10'h016;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
        begin
          _7_ = 10'h017;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
        begin
          _7_ = 10'h018;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
        begin
          _7_ = 10'h019;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
        begin
          _7_ = 10'h01a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
        begin
          _7_ = 10'h01b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
        begin
          _7_ = 10'h01c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
        begin
          _7_ = 10'h01d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
        begin
          _7_ = 10'h01e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
        begin
          _7_ = 10'h01f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
        begin
          _7_ = 10'h020;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
        begin
          _7_ = 10'h021;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
        begin
          _7_ = 10'h023;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
        begin
          _7_ = 10'h024;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
        begin
          _7_ = 10'h025;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _7_ = 10'h026;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
        begin
          _7_ = 10'h027;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
        begin
          _7_ = 10'h028;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
        begin
          _7_ = 10'h029;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
        begin
          _7_ = 10'h02a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
        begin
          _7_ = 10'h02b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
        begin
          _7_ = 10'h02c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
        begin
          _7_ = 10'h02d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
        begin
          _7_ = 10'h02e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
        begin
          _7_ = 10'h02f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
        begin
          _7_ = 10'h030;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
        begin
          _7_ = 10'h031;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
        begin
          _7_ = 10'h032;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
        begin
          _7_ = 10'h033;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
        begin
          _7_ = 10'h034;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
        begin
          _7_ = 10'h035;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
        begin
          _7_ = 10'h036;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
        begin
          _7_ = 10'h037;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
        begin
          _7_ = 10'h038;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
        begin
          _7_ = 10'h039;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
        begin
          _7_ = 10'h03a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
        begin
          _7_ = 10'h03b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
        begin
          _7_ = 10'h03c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
        begin
          _7_ = 10'h03d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
        begin
          _7_ = 10'h03e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
        begin
          _7_ = 10'h03f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
        begin
          _7_ = 10'h040;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
        begin
          _7_ = 10'h041;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
        begin
          _7_ = 10'h042;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
        begin
          _7_ = 10'h043;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
        begin
          _7_ = 10'h044;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
        begin
          _7_ = 10'h045;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
        begin
          _7_ = 10'h046;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
        begin
          _7_ = 10'h047;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
        begin
          _7_ = 10'h048;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
        begin
          _7_ = 10'h049;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
        begin
          _7_ = 10'h04a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
        begin
          _7_ = 10'h04b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
        begin
          _7_ = 10'h04c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
        begin
          _7_ = 10'h04d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
        begin
          _7_ = 10'h04e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
        begin
          _7_ = 10'h04f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
        begin
          _7_ = 10'h050;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
        begin
          _7_ = 10'h051;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
        begin
          _7_ = 10'h052;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
        begin
          _7_ = 10'h053;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
        begin
          _7_ = 10'h054;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
        begin
          _7_ = 10'h055;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
        begin
          _7_ = 10'h056;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
        begin
          _7_ = 10'h057;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
        begin
          _7_ = 10'h058;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
        begin
          _7_ = 10'h059;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
        begin
          _7_ = 10'h05a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
        begin
          _7_ = 10'h05b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
        begin
          _7_ = 10'h05c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
        begin
          _7_ = 10'h05d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
        begin
          _7_ = 10'h05e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
        begin
          _7_ = 10'h05f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
        begin
          _7_ = 10'h060;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
        begin
          _7_ = 10'h061;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
        begin
          _7_ = 10'h062;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
        begin
          _7_ = 10'h063;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
        begin
          _7_ = 10'h064;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
        begin
          _7_ = 10'h065;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
        begin
          _7_ = 10'h066;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
        begin
          _7_ = 10'h067;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
          _7_ = 10'h000;
      /* src = "libresoc.v:0.0-0.0" */
      10'h330:
        begin
          _7_ = 10'h069;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h337:
        begin
          _7_ = 10'h06a;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h350:
        begin
          _7_ = 10'h06b;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h351:
        begin
          _7_ = 10'h06c;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h357:
        begin
          _7_ = 10'h06d;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h380:
        begin
          _7_ = 10'h06e;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h382:
        begin
          _7_ = 10'h06f;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h3ff:
        begin
          _7_ = 10'h070;
        end
      default:
          _7_ = 10'h000;
    endcase
  end
  always @* begin
      spr_o <= _3_;
  end
  always @* begin
    if (\initial ) begin end
    _4_ = _8_;
    (* src = "libresoc.v:192569.5-192569.29" *)
    casez (\initial )
      /* src = "libresoc.v:192569.9-192569.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" *)
    casez (spr_i)
      /* src = "libresoc.v:0.0-0.0" */
      10'h001:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h003:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h008:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h009:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h00d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h011:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h012:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h013:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h016:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01a:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01b:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h01c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h01d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h030:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h03d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h080:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h081:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h082:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h083:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h088:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h090:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h098:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h099:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h09f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0b4:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0ba:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bb:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0bc:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h0be:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h100:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h103:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h10c:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h10d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h110:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h111:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h112:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h113:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h11f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h130:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h131:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h132:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h133:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h134:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h135:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h136:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h139:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13a:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h13f:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h150:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h151:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h152:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h153:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h15d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1be:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h1d0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2c0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d0:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h2d1:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h300:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h301:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h302:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h303:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h304:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h305:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h306:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h307:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h308:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h30e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h310:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h311:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h312:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h313:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h314:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h315:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h316:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h317:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h318:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31c:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31d:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h31e:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h320:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h321:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h322:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h323:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h324:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h325:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h326:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h328:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h329:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32a:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32b:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h32f:
          _8_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      10'h330:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h337:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h350:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h351:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h357:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h380:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h382:
        begin
          _8_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      10'h3ff:
        begin
          _8_ = 1'h1;
        end
      default:
          _8_ = 1'h0;
    endcase
  end
  always @* begin
      spr_o_ok <= _4_;
  end
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.alu0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:192918.1-192976.10" *)
module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:192919.7-192919.20" *)
  reg _00_;
  (* src = "libresoc.v:192964.3-192972.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:192962.3-192963.27" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:192964.3-192972.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:192941.13-192941.25" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:192954.17-192954.96" *)
  wire [3:0] _05_;
  (* src = "libresoc.v:192959.17-192959.96" *)
  wire [3:0] _06_;
  (* src = "libresoc.v:192956.18-192956.93" *)
  wire [3:0] _07_;
  (* src = "libresoc.v:192958.17-192958.92" *)
  wire [3:0] _08_;
  (* src = "libresoc.v:192961.17-192961.92" *)
  wire [3:0] _09_;
  (* src = "libresoc.v:192955.18-192955.98" *)
  wire [3:0] _10_;
  (* src = "libresoc.v:192957.18-192957.99" *)
  wire [3:0] _11_;
  (* src = "libresoc.v:192960.17-192960.97" *)
  wire [3:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [3:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [3:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:192919.7-192919.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [3:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [3:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [3:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [3:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [3:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:192965.5-192965.29" *)
    casez (\initial )
      /* src = "libresoc.v:192965.9-192965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 4'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.cr0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:192980.1-193038.10" *)
module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:192981.7-192981.20" *)
  reg _00_;
  (* src = "libresoc.v:193026.3-193034.6" *)
  reg [5:0] _01_;
  (* src = "libresoc.v:193024.3-193025.27" *)
  reg [5:0] _02_;
  (* src = "libresoc.v:193026.3-193034.6" *)
  reg [5:0] _03_;
  (* src = "libresoc.v:193003.13-193003.26" *)
  reg [5:0] _04_;
  (* src = "libresoc.v:193016.17-193016.96" *)
  wire [5:0] _05_;
  (* src = "libresoc.v:193021.17-193021.96" *)
  wire [5:0] _06_;
  (* src = "libresoc.v:193018.18-193018.93" *)
  wire [5:0] _07_;
  (* src = "libresoc.v:193020.17-193020.92" *)
  wire [5:0] _08_;
  (* src = "libresoc.v:193023.17-193023.92" *)
  wire [5:0] _09_;
  (* src = "libresoc.v:193017.18-193017.98" *)
  wire [5:0] _10_;
  (* src = "libresoc.v:193019.18-193019.99" *)
  wire [5:0] _11_;
  (* src = "libresoc.v:193022.17-193022.97" *)
  wire [5:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [5:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [5:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:192981.7-192981.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [5:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [5:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [5:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [5:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [5:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193027.5-193027.29" *)
    casez (\initial )
      /* src = "libresoc.v:193027.9-193027.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 6'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.mul0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193042.1-193100.10" *)
module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193043.7-193043.20" *)
  reg _00_;
  (* src = "libresoc.v:193088.3-193096.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:193086.3-193087.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:193088.3-193096.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193065.13-193065.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193078.17-193078.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:193083.17-193083.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:193080.18-193080.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:193082.17-193082.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:193085.17-193085.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:193079.18-193079.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:193081.18-193081.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:193084.17-193084.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193043.7-193043.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193089.5-193089.29" *)
    casez (\initial )
      /* src = "libresoc.v:193089.9-193089.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.shiftrot0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193104.1-193162.10" *)
module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193105.7-193105.20" *)
  reg _00_;
  (* src = "libresoc.v:193150.3-193158.6" *)
  reg [4:0] _01_;
  (* src = "libresoc.v:193148.3-193149.27" *)
  reg [4:0] _02_;
  (* src = "libresoc.v:193150.3-193158.6" *)
  reg [4:0] _03_;
  (* src = "libresoc.v:193127.13-193127.26" *)
  reg [4:0] _04_;
  (* src = "libresoc.v:193140.17-193140.96" *)
  wire [4:0] _05_;
  (* src = "libresoc.v:193145.17-193145.96" *)
  wire [4:0] _06_;
  (* src = "libresoc.v:193142.18-193142.93" *)
  wire [4:0] _07_;
  (* src = "libresoc.v:193144.17-193144.92" *)
  wire [4:0] _08_;
  (* src = "libresoc.v:193147.17-193147.92" *)
  wire [4:0] _09_;
  (* src = "libresoc.v:193141.18-193141.98" *)
  wire [4:0] _10_;
  (* src = "libresoc.v:193143.18-193143.99" *)
  wire [4:0] _11_;
  (* src = "libresoc.v:193146.17-193146.97" *)
  wire [4:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [4:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [4:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [4:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [4:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193105.7-193105.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [4:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [4:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [4:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [4:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [4:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [4:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193151.5-193151.29" *)
    casez (\initial )
      /* src = "libresoc.v:193151.9-193151.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 5'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193166.1-193224.10" *)
module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193167.7-193167.20" *)
  reg _00_;
  (* src = "libresoc.v:193212.3-193220.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:193210.3-193211.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:193212.3-193220.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193189.13-193189.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193202.17-193202.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:193207.17-193207.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:193204.18-193204.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:193206.17-193206.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:193209.17-193209.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:193203.18-193203.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:193205.18-193205.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:193208.17-193208.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193167.7-193167.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193213.5-193213.29" *)
    casez (\initial )
      /* src = "libresoc.v:193213.9-193213.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.branch0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193228.1-193286.10" *)
module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193229.7-193229.20" *)
  reg _00_;
  (* src = "libresoc.v:193274.3-193282.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:193272.3-193273.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:193274.3-193282.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193251.13-193251.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193264.17-193264.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:193269.17-193269.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:193266.18-193266.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:193268.17-193268.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:193271.17-193271.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:193265.18-193265.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:193267.18-193267.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:193270.17-193270.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193229.7-193229.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193275.5-193275.29" *)
    casez (\initial )
      /* src = "libresoc.v:193275.9-193275.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193290.1-193348.10" *)
module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193291.7-193291.20" *)
  reg _00_;
  (* src = "libresoc.v:193336.3-193344.6" *)
  reg [3:0] _01_;
  (* src = "libresoc.v:193334.3-193335.27" *)
  reg [3:0] _02_;
  (* src = "libresoc.v:193336.3-193344.6" *)
  reg [3:0] _03_;
  (* src = "libresoc.v:193313.13-193313.25" *)
  reg [3:0] _04_;
  (* src = "libresoc.v:193326.17-193326.96" *)
  wire [3:0] _05_;
  (* src = "libresoc.v:193331.17-193331.96" *)
  wire [3:0] _06_;
  (* src = "libresoc.v:193328.18-193328.93" *)
  wire [3:0] _07_;
  (* src = "libresoc.v:193330.17-193330.92" *)
  wire [3:0] _08_;
  (* src = "libresoc.v:193333.17-193333.92" *)
  wire [3:0] _09_;
  (* src = "libresoc.v:193327.18-193327.98" *)
  wire [3:0] _10_;
  (* src = "libresoc.v:193329.18-193329.99" *)
  wire [3:0] _11_;
  (* src = "libresoc.v:193332.17-193332.97" *)
  wire [3:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [3:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [3:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [3:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [3:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193291.7-193291.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [3:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [3:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [3:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [3:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [3:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [3:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193337.5-193337.29" *)
    casez (\initial )
      /* src = "libresoc.v:193337.9-193337.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 4'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.logical0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193352.1-193410.10" *)
module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193353.7-193353.20" *)
  reg _00_;
  (* src = "libresoc.v:193398.3-193406.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:193396.3-193397.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:193398.3-193406.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193375.13-193375.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193388.17-193388.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:193393.17-193393.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:193390.18-193390.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:193392.17-193392.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:193395.17-193395.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:193389.18-193389.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:193391.18-193391.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:193394.17-193394.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193353.7-193353.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193399.5-193399.29" *)
    casez (\initial )
      /* src = "libresoc.v:193399.9-193399.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.spr0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193414.1-193472.10" *)
module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193415.7-193415.20" *)
  reg _00_;
  (* src = "libresoc.v:193460.3-193468.6" *)
  reg [5:0] _01_;
  (* src = "libresoc.v:193458.3-193459.27" *)
  reg [5:0] _02_;
  (* src = "libresoc.v:193460.3-193468.6" *)
  reg [5:0] _03_;
  (* src = "libresoc.v:193437.13-193437.26" *)
  reg [5:0] _04_;
  (* src = "libresoc.v:193450.17-193450.96" *)
  wire [5:0] _05_;
  (* src = "libresoc.v:193455.17-193455.96" *)
  wire [5:0] _06_;
  (* src = "libresoc.v:193452.18-193452.93" *)
  wire [5:0] _07_;
  (* src = "libresoc.v:193454.17-193454.92" *)
  wire [5:0] _08_;
  (* src = "libresoc.v:193457.17-193457.92" *)
  wire [5:0] _09_;
  (* src = "libresoc.v:193451.18-193451.98" *)
  wire [5:0] _10_;
  (* src = "libresoc.v:193453.18-193453.99" *)
  wire [5:0] _11_;
  (* src = "libresoc.v:193456.17-193456.97" *)
  wire [5:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [5:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [5:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [5:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [5:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193415.7-193415.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [5:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [5:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [5:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [5:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [5:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [5:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 6'h00;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193461.5-193461.29" *)
    casez (\initial )
      /* src = "libresoc.v:193461.9-193461.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 6'h00;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.div0.src_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193476.1-193534.10" *)
module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193477.7-193477.20" *)
  reg _00_;
  (* src = "libresoc.v:193522.3-193530.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:193520.3-193521.27" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:193522.3-193530.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193499.13-193499.25" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193512.17-193512.96" *)
  wire [2:0] _05_;
  (* src = "libresoc.v:193517.17-193517.96" *)
  wire [2:0] _06_;
  (* src = "libresoc.v:193514.18-193514.93" *)
  wire [2:0] _07_;
  (* src = "libresoc.v:193516.17-193516.92" *)
  wire [2:0] _08_;
  (* src = "libresoc.v:193519.17-193519.92" *)
  wire [2:0] _09_;
  (* src = "libresoc.v:193513.18-193513.98" *)
  wire [2:0] _10_;
  (* src = "libresoc.v:193515.18-193515.99" *)
  wire [2:0] _11_;
  (* src = "libresoc.v:193518.17-193518.97" *)
  wire [2:0] _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire [2:0] \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire [2:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire [2:0] \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire [2:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193477.7-193477.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg [2:0] \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output [2:0] q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire [2:0] qlq_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire [2:0] qn_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input [2:0] r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input [2:0] s_src;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_src;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_src;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_src;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_src;
  assign _11_ = q_src | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_src;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193523.5-193523.29" *)
    casez (\initial )
      /* src = "libresoc.v:193523.9-193523.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 3'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_src = \$15 ;
  assign qn_src = \$13 ;
  assign q_src = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.st_active" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193538.1-193596.10" *)
module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193539.7-193539.20" *)
  reg _00_;
  (* src = "libresoc.v:193584.3-193592.6" *)
  reg _01_;
  (* src = "libresoc.v:193582.3-193583.27" *)
  reg _02_;
  (* src = "libresoc.v:193584.3-193592.6" *)
  reg _03_;
  (* src = "libresoc.v:193561.7-193561.19" *)
  reg _04_;
  (* src = "libresoc.v:193574.17-193574.96" *)
  wire _05_;
  (* src = "libresoc.v:193579.17-193579.96" *)
  wire _06_;
  (* src = "libresoc.v:193576.18-193576.99" *)
  wire _07_;
  (* src = "libresoc.v:193578.17-193578.98" *)
  wire _08_;
  (* src = "libresoc.v:193581.17-193581.98" *)
  wire _09_;
  (* src = "libresoc.v:193575.18-193575.104" *)
  wire _10_;
  (* src = "libresoc.v:193577.18-193577.105" *)
  wire _11_;
  (* src = "libresoc.v:193580.17-193580.103" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193539.7-193539.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_st_active;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_st_active;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_st_active;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_st_active;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_st_active;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_st_active;
  assign _11_ = q_st_active | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_st_active;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193585.5-193585.29" *)
    casez (\initial )
      /* src = "libresoc.v:193585.9-193585.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_st_active = \$15 ;
  assign qn_st_active = \$13 ;
  assign q_st_active = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.st_done" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193600.1-193658.10" *)
module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193601.7-193601.20" *)
  reg _00_;
  (* src = "libresoc.v:193646.3-193654.6" *)
  reg _01_;
  (* src = "libresoc.v:193644.3-193645.27" *)
  reg _02_;
  (* src = "libresoc.v:193646.3-193654.6" *)
  reg _03_;
  (* src = "libresoc.v:193623.7-193623.19" *)
  reg _04_;
  (* src = "libresoc.v:193636.17-193636.96" *)
  wire _05_;
  (* src = "libresoc.v:193641.17-193641.96" *)
  wire _06_;
  (* src = "libresoc.v:193638.18-193638.97" *)
  wire _07_;
  (* src = "libresoc.v:193640.17-193640.96" *)
  wire _08_;
  (* src = "libresoc.v:193643.17-193643.96" *)
  wire _09_;
  (* src = "libresoc.v:193637.18-193637.102" *)
  wire _10_;
  (* src = "libresoc.v:193639.18-193639.103" *)
  wire _11_;
  (* src = "libresoc.v:193642.17-193642.101" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193601.7-193601.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_st_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_st_done;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_st_done;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_st_done;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_st_done;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_st_done;
  assign _11_ = q_st_done | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_st_done;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:193647.5-193647.29" *)
    casez (\initial )
      /* src = "libresoc.v:193647.9-193647.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_st_done = \$15 ;
  assign qn_st_done = \$13 ;
  assign q_st_done = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.state" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193662.1-193958.10" *)
module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data_i, msr__ren, msr__data_o, \wen$1 , \data_i$2 , state_nia_wen, \data_i$3 , \data_i$4 , \wen$5 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193910.3-193919.6" *)
  reg [63:0] _00_;
  (* src = "libresoc.v:193663.7-193663.20" *)
  reg _01_;
  (* src = "libresoc.v:193929.3-193938.6" *)
  reg [63:0] _02_;
  (* src = "libresoc.v:193920.3-193928.6" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:193824.3-193825.43" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:193791.13-193791.34" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:193882.3-193890.6" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:193822.3-193823.43" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:193795.13-193795.34" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:193901.3-193909.6" *)
  reg [2:0] _09_;
  (* src = "libresoc.v:193826.3-193827.35" *)
  reg [2:0] _10_;
  (* src = "libresoc.v:193891.3-193900.6" *)
  reg [63:0] _11_;
  (* src = "libresoc.v:193910.3-193919.6" *)
  reg [63:0] _12_;
  (* src = "libresoc.v:193929.3-193938.6" *)
  reg [63:0] _13_;
  (* src = "libresoc.v:193920.3-193928.6" *)
  reg [2:0] _14_;
  (* src = "libresoc.v:193882.3-193890.6" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:193901.3-193909.6" *)
  reg [2:0] _16_;
  (* src = "libresoc.v:193789.13-193789.29" *)
  reg [2:0] _17_;
  (* src = "libresoc.v:193891.3-193900.6" *)
  reg [63:0] _18_;
  (* src = "libresoc.v:193813.18-193813.109" *)
  wire [63:0] _19_;
  (* src = "libresoc.v:193815.18-193815.124" *)
  wire [63:0] _20_;
  (* src = "libresoc.v:193816.18-193816.110" *)
  wire [63:0] _21_;
  (* src = "libresoc.v:193818.18-193818.122" *)
  wire [63:0] _22_;
  (* src = "libresoc.v:193819.18-193819.109" *)
  wire [63:0] _23_;
  (* src = "libresoc.v:193821.17-193821.123" *)
  wire [63:0] _24_;
  (* src = "libresoc.v:193814.18-193814.100" *)
  wire _25_;
  (* src = "libresoc.v:193817.18-193817.100" *)
  wire _26_;
  (* src = "libresoc.v:193820.17-193820.95" *)
  wire _27_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$10 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$22 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [63:0] \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$6 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [63:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] cia__data_o;
  reg [63:0] cia__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] cia__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] \data_i$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] \data_i$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [63:0] \data_i$4 ;
  (* src = "libresoc.v:193663.7-193663.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] msr__data_o;
  reg [63:0] msr__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] msr__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_cia0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_cia0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_d_wr10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_d_wr10__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_msr0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_msr0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_msr0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_msr0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_nia0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_nia0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_sv0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_0_sv0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_sv0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_sv0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_cia1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_cia1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_d_wr11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_d_wr11__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_msr1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_msr1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_msr1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_msr1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_nia1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_nia1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_sv1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_1_sv1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_sv1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_sv1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_cia2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_cia2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_d_wr12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_d_wr12__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_msr2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_msr2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_msr2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_msr2__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_nia2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_nia2__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_sv2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] reg_2_sv2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_sv2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_sv2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$12$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$19$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] state_nia_wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [63:0] sv__data_o;
  reg [63:0] sv__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] sv__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \wen$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \wen$5 ;
  assign _19_ = reg_0_cia0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$8 ;
  assign _20_ = reg_1_msr1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_msr2__data_o;
  assign _21_ = reg_0_msr0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$15 ;
  assign _22_ = reg_1_sv1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_sv2__data_o;
  assign _23_ = reg_0_sv0__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$22 ;
  assign _24_ = reg_1_cia1__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_cia2__data_o;
  assign _25_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$12 ;
  assign _26_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$19 ;
  assign _27_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:193828.15-193845.4" *)
  \reg_0$135  reg_0 (
    .cia0__data_o(reg_0_cia0__data_o),
    .cia0__ren(reg_0_cia0__ren),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .d_wr10__data_i(reg_0_d_wr10__data_i),
    .d_wr10__wen(reg_0_d_wr10__wen),
    .msr0__data_i(reg_0_msr0__data_i),
    .msr0__data_o(reg_0_msr0__data_o),
    .msr0__ren(reg_0_msr0__ren),
    .msr0__wen(reg_0_msr0__wen),
    .nia0__data_i(reg_0_nia0__data_i),
    .nia0__wen(reg_0_nia0__wen),
    .sv0__data_i(reg_0_sv0__data_i),
    .sv0__data_o(reg_0_sv0__data_o),
    .sv0__ren(reg_0_sv0__ren),
    .sv0__wen(reg_0_sv0__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:193846.15-193863.4" *)
  \reg_1$136  reg_1 (
    .cia1__data_o(reg_1_cia1__data_o),
    .cia1__ren(reg_1_cia1__ren),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .d_wr11__data_i(reg_1_d_wr11__data_i),
    .d_wr11__wen(reg_1_d_wr11__wen),
    .msr1__data_i(reg_1_msr1__data_i),
    .msr1__data_o(reg_1_msr1__data_o),
    .msr1__ren(reg_1_msr1__ren),
    .msr1__wen(reg_1_msr1__wen),
    .nia1__data_i(reg_1_nia1__data_i),
    .nia1__wen(reg_1_nia1__wen),
    .sv1__data_i(reg_1_sv1__data_i),
    .sv1__data_o(reg_1_sv1__data_o),
    .sv1__ren(reg_1_sv1__ren),
    .sv1__wen(reg_1_sv1__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:193864.15-193881.4" *)
  \reg_2$137  reg_2 (
    .cia2__data_o(reg_2_cia2__data_o),
    .cia2__ren(reg_2_cia2__ren),
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .d_wr12__data_i(reg_2_d_wr12__data_i),
    .d_wr12__wen(reg_2_d_wr12__wen),
    .msr2__data_i(reg_2_msr2__data_i),
    .msr2__data_o(reg_2_msr2__data_o),
    .msr2__ren(reg_2_msr2__ren),
    .msr2__wen(reg_2_msr2__wen),
    .nia2__data_i(reg_2_nia2__data_i),
    .nia2__wen(reg_2_nia2__wen),
    .sv2__data_i(reg_2_sv2__data_i),
    .sv2__data_o(reg_2_sv2__data_o),
    .sv2__ren(reg_2_sv2__ren),
    .sv2__wen(reg_2_sv2__wen)
  );
  always @* begin
    if (\initial ) begin end
    _01_ = 1'h0;
  end
  always @* begin
      \initial  <= _01_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _17_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _17_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$12  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$19  <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = \ren_delay$19$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$19  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = \ren_delay$12$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$12  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _15_;
    (* src = "libresoc.v:193883.5-193883.29" *)
    casez (\initial )
      /* src = "libresoc.v:193883.9-193883.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _15_ = 3'h0;
        end
      default:
          _15_ = sv__ren;
    endcase
  end
  always @* begin
      \ren_delay$19$next  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _18_;
    (* src = "libresoc.v:193892.5-193892.29" *)
    casez (\initial )
      /* src = "libresoc.v:193892.9-193892.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$20 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = \$24 ;
        end
      default:
          _18_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      sv__data_o <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _16_;
    (* src = "libresoc.v:193902.5-193902.29" *)
    casez (\initial )
      /* src = "libresoc.v:193902.9-193902.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = 3'h0;
        end
      default:
          _16_ = cia__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _12_;
    (* src = "libresoc.v:193911.5-193911.29" *)
    casez (\initial )
      /* src = "libresoc.v:193911.9-193911.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$6 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = \$10 ;
        end
      default:
          _12_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      cia__data_o <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = _14_;
    (* src = "libresoc.v:193921.5-193921.29" *)
    casez (\initial )
      /* src = "libresoc.v:193921.9-193921.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = 3'h0;
        end
      default:
          _14_ = msr__ren;
    endcase
  end
  always @* begin
      \ren_delay$12$next  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = _13_;
    (* src = "libresoc.v:193930.5-193930.29" *)
    casez (\initial )
      /* src = "libresoc.v:193930.9-193930.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$13 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = \$17 ;
        end
      default:
          _13_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      msr__data_o <= _02_;
  end
  assign \$10  = _19_;
  assign \$13  = _25_;
  assign \$15  = _20_;
  assign \$17  = _21_;
  assign \$20  = _26_;
  assign \$22  = _22_;
  assign \$24  = _23_;
  assign \$6  = _27_;
  assign \$8  = _24_;
  assign reg_2_d_wr12__data_i = data_i;
  assign reg_1_d_wr11__data_i = data_i;
  assign reg_0_d_wr10__data_i = data_i;
  assign { reg_2_d_wr12__wen, reg_1_d_wr11__wen, reg_0_d_wr10__wen } = wen;
  assign reg_2_sv2__data_i = \data_i$2 ;
  assign reg_1_sv1__data_i = \data_i$2 ;
  assign reg_0_sv0__data_i = \data_i$2 ;
  assign { reg_2_sv2__wen, reg_1_sv1__wen, reg_0_sv0__wen } = \wen$1 ;
  assign reg_2_msr2__data_i = \data_i$4 ;
  assign reg_1_msr1__data_i = \data_i$4 ;
  assign reg_0_msr0__data_i = \data_i$4 ;
  assign { reg_2_msr2__wen, reg_1_msr1__wen, reg_0_msr0__wen } = \wen$5 ;
  assign reg_2_nia2__data_i = \data_i$3 ;
  assign reg_1_nia1__data_i = \data_i$3 ;
  assign reg_0_nia0__data_i = \data_i$3 ;
  assign { reg_2_nia2__wen, reg_1_nia1__wen, reg_0_nia0__wen } = state_nia_wen;
  assign { reg_2_sv2__ren, reg_1_sv1__ren, reg_0_sv0__ren } = sv__ren;
  assign { reg_2_msr2__ren, reg_1_msr1__ren, reg_0_msr0__ren } = msr__ren;
  assign { reg_2_cia2__ren, reg_1_cia1__ren, reg_0_cia0__ren } = cia__ren;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.sto_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:193962.1-194020.10" *)
module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:193963.7-193963.20" *)
  reg _00_;
  (* src = "libresoc.v:194008.3-194016.6" *)
  reg _01_;
  (* src = "libresoc.v:194006.3-194007.27" *)
  reg _02_;
  (* src = "libresoc.v:194008.3-194016.6" *)
  reg _03_;
  (* src = "libresoc.v:193985.7-193985.19" *)
  reg _04_;
  (* src = "libresoc.v:193998.17-193998.96" *)
  wire _05_;
  (* src = "libresoc.v:194003.17-194003.96" *)
  wire _06_;
  (* src = "libresoc.v:194000.18-194000.93" *)
  wire _07_;
  (* src = "libresoc.v:194002.17-194002.92" *)
  wire _08_;
  (* src = "libresoc.v:194005.17-194005.92" *)
  wire _09_;
  (* src = "libresoc.v:193999.18-193999.98" *)
  wire _10_;
  (* src = "libresoc.v:194001.18-194001.99" *)
  wire _11_;
  (* src = "libresoc.v:194004.17-194004.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:193963.7-193963.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_sto;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_sto;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_sto;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_sto;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_sto;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_sto;
  assign _11_ = q_sto | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_sto;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:194009.5-194009.29" *)
    casez (\initial )
      /* src = "libresoc.v:194009.9-194009.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_sto = \$15 ;
  assign qn_sto = \$13 ;
  assign q_sto = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer" *)
(* top =  1  *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:194025.1-194987.10" *)
module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, pc_i);
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tck;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tdi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  output TAP_bus__tdo;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
  output busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *)
  input core_bigendian_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [44:0] dbus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [1:0] dbus__bte;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [2:0] dbus__cti;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [63:0] dbus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [63:0] dbus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [7:0] dbus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [44:0] ibus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [1:0] ibus__bte;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [2:0] ibus__cti;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [63:0] ibus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [63:0] ibus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [7:0] ibus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output icp_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [27:0] icp_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output [31:0] icp_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [31:0] icp_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [3:0] icp_wb__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output ics_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [27:0] ics_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output [31:0] ics_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [31:0] ics_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [3:0] ics_wb__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
  input [15:0] int_level_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input jtag_wb__ack;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [29:0] jtag_wb__adr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input [31:0] jtag_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [31:0] jtag_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input jtag_wb__err;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [3:0] jtag_wb__sel;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__stb;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *)
  input memerr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_clk__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_clk__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_miso__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_miso__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_mosi__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_mosi__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_scl__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_scl__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] pc_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input pc_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *)
  output [63:0] pc_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cas_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cas_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cke__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cke__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_clock__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_clock__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ras_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ras_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_we_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_we_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  wire ti_coresync_clk;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:194672.6-194985.4" *)
  ti ti (
    .TAP_bus__tck(TAP_bus__tck),
    .TAP_bus__tdi(TAP_bus__tdi),
    .TAP_bus__tdo(TAP_bus__tdo),
    .TAP_bus__tms(TAP_bus__tms),
    .busy_o(busy_o),
    .clk(clk),
    .core_bigendian_i(core_bigendian_i),
    .coresync_clk(ti_coresync_clk),
    .dbus__ack(dbus__ack),
    .dbus__adr(dbus__adr),
    .dbus__cyc(dbus__cyc),
    .dbus__dat_r(dbus__dat_r),
    .dbus__dat_w(dbus__dat_w),
    .dbus__err(dbus__err),
    .dbus__sel(dbus__sel),
    .dbus__stb(dbus__stb),
    .dbus__we(dbus__we),
    .eint_0__core__i(eint_0__core__i),
    .eint_0__pad__i(eint_0__pad__i),
    .eint_1__core__i(eint_1__core__i),
    .eint_1__pad__i(eint_1__pad__i),
    .eint_2__core__i(eint_2__core__i),
    .eint_2__pad__i(eint_2__pad__i),
    .gpio_e10__core__i(gpio_e10__core__i),
    .gpio_e10__core__o(gpio_e10__core__o),
    .gpio_e10__core__oe(gpio_e10__core__oe),
    .gpio_e10__pad__i(gpio_e10__pad__i),
    .gpio_e10__pad__o(gpio_e10__pad__o),
    .gpio_e10__pad__oe(gpio_e10__pad__oe),
    .gpio_e11__core__i(gpio_e11__core__i),
    .gpio_e11__core__o(gpio_e11__core__o),
    .gpio_e11__core__oe(gpio_e11__core__oe),
    .gpio_e11__pad__i(gpio_e11__pad__i),
    .gpio_e11__pad__o(gpio_e11__pad__o),
    .gpio_e11__pad__oe(gpio_e11__pad__oe),
    .gpio_e12__core__i(gpio_e12__core__i),
    .gpio_e12__core__o(gpio_e12__core__o),
    .gpio_e12__core__oe(gpio_e12__core__oe),
    .gpio_e12__pad__i(gpio_e12__pad__i),
    .gpio_e12__pad__o(gpio_e12__pad__o),
    .gpio_e12__pad__oe(gpio_e12__pad__oe),
    .gpio_e13__core__i(gpio_e13__core__i),
    .gpio_e13__core__o(gpio_e13__core__o),
    .gpio_e13__core__oe(gpio_e13__core__oe),
    .gpio_e13__pad__i(gpio_e13__pad__i),
    .gpio_e13__pad__o(gpio_e13__pad__o),
    .gpio_e13__pad__oe(gpio_e13__pad__oe),
    .gpio_e14__core__i(gpio_e14__core__i),
    .gpio_e14__core__o(gpio_e14__core__o),
    .gpio_e14__core__oe(gpio_e14__core__oe),
    .gpio_e14__pad__i(gpio_e14__pad__i),
    .gpio_e14__pad__o(gpio_e14__pad__o),
    .gpio_e14__pad__oe(gpio_e14__pad__oe),
    .gpio_e15__core__i(gpio_e15__core__i),
    .gpio_e15__core__o(gpio_e15__core__o),
    .gpio_e15__core__oe(gpio_e15__core__oe),
    .gpio_e15__pad__i(gpio_e15__pad__i),
    .gpio_e15__pad__o(gpio_e15__pad__o),
    .gpio_e15__pad__oe(gpio_e15__pad__oe),
    .gpio_e8__core__i(gpio_e8__core__i),
    .gpio_e8__core__o(gpio_e8__core__o),
    .gpio_e8__core__oe(gpio_e8__core__oe),
    .gpio_e8__pad__i(gpio_e8__pad__i),
    .gpio_e8__pad__o(gpio_e8__pad__o),
    .gpio_e8__pad__oe(gpio_e8__pad__oe),
    .gpio_e9__core__i(gpio_e9__core__i),
    .gpio_e9__core__o(gpio_e9__core__o),
    .gpio_e9__core__oe(gpio_e9__core__oe),
    .gpio_e9__pad__i(gpio_e9__pad__i),
    .gpio_e9__pad__o(gpio_e9__pad__o),
    .gpio_e9__pad__oe(gpio_e9__pad__oe),
    .gpio_s0__core__i(gpio_s0__core__i),
    .gpio_s0__core__o(gpio_s0__core__o),
    .gpio_s0__core__oe(gpio_s0__core__oe),
    .gpio_s0__pad__i(gpio_s0__pad__i),
    .gpio_s0__pad__o(gpio_s0__pad__o),
    .gpio_s0__pad__oe(gpio_s0__pad__oe),
    .gpio_s1__core__i(gpio_s1__core__i),
    .gpio_s1__core__o(gpio_s1__core__o),
    .gpio_s1__core__oe(gpio_s1__core__oe),
    .gpio_s1__pad__i(gpio_s1__pad__i),
    .gpio_s1__pad__o(gpio_s1__pad__o),
    .gpio_s1__pad__oe(gpio_s1__pad__oe),
    .gpio_s2__core__i(gpio_s2__core__i),
    .gpio_s2__core__o(gpio_s2__core__o),
    .gpio_s2__core__oe(gpio_s2__core__oe),
    .gpio_s2__pad__i(gpio_s2__pad__i),
    .gpio_s2__pad__o(gpio_s2__pad__o),
    .gpio_s2__pad__oe(gpio_s2__pad__oe),
    .gpio_s3__core__i(gpio_s3__core__i),
    .gpio_s3__core__o(gpio_s3__core__o),
    .gpio_s3__core__oe(gpio_s3__core__oe),
    .gpio_s3__pad__i(gpio_s3__pad__i),
    .gpio_s3__pad__o(gpio_s3__pad__o),
    .gpio_s3__pad__oe(gpio_s3__pad__oe),
    .gpio_s4__core__i(gpio_s4__core__i),
    .gpio_s4__core__o(gpio_s4__core__o),
    .gpio_s4__core__oe(gpio_s4__core__oe),
    .gpio_s4__pad__i(gpio_s4__pad__i),
    .gpio_s4__pad__o(gpio_s4__pad__o),
    .gpio_s4__pad__oe(gpio_s4__pad__oe),
    .gpio_s5__core__i(gpio_s5__core__i),
    .gpio_s5__core__o(gpio_s5__core__o),
    .gpio_s5__core__oe(gpio_s5__core__oe),
    .gpio_s5__pad__i(gpio_s5__pad__i),
    .gpio_s5__pad__o(gpio_s5__pad__o),
    .gpio_s5__pad__oe(gpio_s5__pad__oe),
    .gpio_s6__core__i(gpio_s6__core__i),
    .gpio_s6__core__o(gpio_s6__core__o),
    .gpio_s6__core__oe(gpio_s6__core__oe),
    .gpio_s6__pad__i(gpio_s6__pad__i),
    .gpio_s6__pad__o(gpio_s6__pad__o),
    .gpio_s6__pad__oe(gpio_s6__pad__oe),
    .gpio_s7__core__i(gpio_s7__core__i),
    .gpio_s7__core__o(gpio_s7__core__o),
    .gpio_s7__core__oe(gpio_s7__core__oe),
    .gpio_s7__pad__i(gpio_s7__pad__i),
    .gpio_s7__pad__o(gpio_s7__pad__o),
    .gpio_s7__pad__oe(gpio_s7__pad__oe),
    .ibus__ack(ibus__ack),
    .ibus__adr(ibus__adr),
    .ibus__cyc(ibus__cyc),
    .ibus__dat_r(ibus__dat_r),
    .ibus__err(ibus__err),
    .ibus__sel(ibus__sel),
    .ibus__stb(ibus__stb),
    .icp_wb__ack(icp_wb__ack),
    .icp_wb__adr(icp_wb__adr),
    .icp_wb__cyc(icp_wb__cyc),
    .icp_wb__dat_r(icp_wb__dat_r),
    .icp_wb__dat_w(icp_wb__dat_w),
    .icp_wb__sel(icp_wb__sel),
    .icp_wb__stb(icp_wb__stb),
    .icp_wb__we(icp_wb__we),
    .ics_wb__ack(ics_wb__ack),
    .ics_wb__adr(ics_wb__adr),
    .ics_wb__cyc(ics_wb__cyc),
    .ics_wb__dat_r(ics_wb__dat_r),
    .ics_wb__dat_w(ics_wb__dat_w),
    .ics_wb__stb(ics_wb__stb),
    .ics_wb__we(ics_wb__we),
    .int_level_i(int_level_i),
    .jtag_wb__ack(jtag_wb__ack),
    .jtag_wb__adr(jtag_wb__adr),
    .jtag_wb__cyc(jtag_wb__cyc),
    .jtag_wb__dat_r(jtag_wb__dat_r),
    .jtag_wb__dat_w(jtag_wb__dat_w),
    .jtag_wb__sel(jtag_wb__sel),
    .jtag_wb__stb(jtag_wb__stb),
    .jtag_wb__we(jtag_wb__we),
    .mspi0_clk__core__o(mspi0_clk__core__o),
    .mspi0_clk__pad__o(mspi0_clk__pad__o),
    .mspi0_cs_n__core__o(mspi0_cs_n__core__o),
    .mspi0_cs_n__pad__o(mspi0_cs_n__pad__o),
    .mspi0_miso__core__i(mspi0_miso__core__i),
    .mspi0_miso__pad__i(mspi0_miso__pad__i),
    .mspi0_mosi__core__o(mspi0_mosi__core__o),
    .mspi0_mosi__pad__o(mspi0_mosi__pad__o),
    .mtwi_scl__core__o(mtwi_scl__core__o),
    .mtwi_scl__pad__o(mtwi_scl__pad__o),
    .mtwi_sda__core__i(mtwi_sda__core__i),
    .mtwi_sda__core__o(mtwi_sda__core__o),
    .mtwi_sda__core__oe(mtwi_sda__core__oe),
    .mtwi_sda__pad__i(mtwi_sda__pad__i),
    .mtwi_sda__pad__o(mtwi_sda__pad__o),
    .mtwi_sda__pad__oe(mtwi_sda__pad__oe),
    .pc_i(pc_i),
    .pc_i_ok(pc_i_ok),
    .pc_o(pc_o),
    .rst(rst),
    .sdr_a_0__core__o(sdr_a_0__core__o),
    .sdr_a_0__pad__o(sdr_a_0__pad__o),
    .sdr_a_10__core__o(sdr_a_10__core__o),
    .sdr_a_10__pad__o(sdr_a_10__pad__o),
    .sdr_a_11__core__o(sdr_a_11__core__o),
    .sdr_a_11__pad__o(sdr_a_11__pad__o),
    .sdr_a_12__core__o(sdr_a_12__core__o),
    .sdr_a_12__pad__o(sdr_a_12__pad__o),
    .sdr_a_1__core__o(sdr_a_1__core__o),
    .sdr_a_1__pad__o(sdr_a_1__pad__o),
    .sdr_a_2__core__o(sdr_a_2__core__o),
    .sdr_a_2__pad__o(sdr_a_2__pad__o),
    .sdr_a_3__core__o(sdr_a_3__core__o),
    .sdr_a_3__pad__o(sdr_a_3__pad__o),
    .sdr_a_4__core__o(sdr_a_4__core__o),
    .sdr_a_4__pad__o(sdr_a_4__pad__o),
    .sdr_a_5__core__o(sdr_a_5__core__o),
    .sdr_a_5__pad__o(sdr_a_5__pad__o),
    .sdr_a_6__core__o(sdr_a_6__core__o),
    .sdr_a_6__pad__o(sdr_a_6__pad__o),
    .sdr_a_7__core__o(sdr_a_7__core__o),
    .sdr_a_7__pad__o(sdr_a_7__pad__o),
    .sdr_a_8__core__o(sdr_a_8__core__o),
    .sdr_a_8__pad__o(sdr_a_8__pad__o),
    .sdr_a_9__core__o(sdr_a_9__core__o),
    .sdr_a_9__pad__o(sdr_a_9__pad__o),
    .sdr_ba_0__core__o(sdr_ba_0__core__o),
    .sdr_ba_0__pad__o(sdr_ba_0__pad__o),
    .sdr_ba_1__core__o(sdr_ba_1__core__o),
    .sdr_ba_1__pad__o(sdr_ba_1__pad__o),
    .sdr_cas_n__core__o(sdr_cas_n__core__o),
    .sdr_cas_n__pad__o(sdr_cas_n__pad__o),
    .sdr_cke__core__o(sdr_cke__core__o),
    .sdr_cke__pad__o(sdr_cke__pad__o),
    .sdr_clock__core__o(sdr_clock__core__o),
    .sdr_clock__pad__o(sdr_clock__pad__o),
    .sdr_cs_n__core__o(sdr_cs_n__core__o),
    .sdr_cs_n__pad__o(sdr_cs_n__pad__o),
    .sdr_dm_0__core__o(sdr_dm_0__core__o),
    .sdr_dm_0__pad__o(sdr_dm_0__pad__o),
    .sdr_dm_1__core__o(sdr_dm_1__core__o),
    .sdr_dm_1__pad__o(sdr_dm_1__pad__o),
    .sdr_dq_0__core__i(sdr_dq_0__core__i),
    .sdr_dq_0__core__o(sdr_dq_0__core__o),
    .sdr_dq_0__core__oe(sdr_dq_0__core__oe),
    .sdr_dq_0__pad__i(sdr_dq_0__pad__i),
    .sdr_dq_0__pad__o(sdr_dq_0__pad__o),
    .sdr_dq_0__pad__oe(sdr_dq_0__pad__oe),
    .sdr_dq_10__core__i(sdr_dq_10__core__i),
    .sdr_dq_10__core__o(sdr_dq_10__core__o),
    .sdr_dq_10__core__oe(sdr_dq_10__core__oe),
    .sdr_dq_10__pad__i(sdr_dq_10__pad__i),
    .sdr_dq_10__pad__o(sdr_dq_10__pad__o),
    .sdr_dq_10__pad__oe(sdr_dq_10__pad__oe),
    .sdr_dq_11__core__i(sdr_dq_11__core__i),
    .sdr_dq_11__core__o(sdr_dq_11__core__o),
    .sdr_dq_11__core__oe(sdr_dq_11__core__oe),
    .sdr_dq_11__pad__i(sdr_dq_11__pad__i),
    .sdr_dq_11__pad__o(sdr_dq_11__pad__o),
    .sdr_dq_11__pad__oe(sdr_dq_11__pad__oe),
    .sdr_dq_12__core__i(sdr_dq_12__core__i),
    .sdr_dq_12__core__o(sdr_dq_12__core__o),
    .sdr_dq_12__core__oe(sdr_dq_12__core__oe),
    .sdr_dq_12__pad__i(sdr_dq_12__pad__i),
    .sdr_dq_12__pad__o(sdr_dq_12__pad__o),
    .sdr_dq_12__pad__oe(sdr_dq_12__pad__oe),
    .sdr_dq_13__core__i(sdr_dq_13__core__i),
    .sdr_dq_13__core__o(sdr_dq_13__core__o),
    .sdr_dq_13__core__oe(sdr_dq_13__core__oe),
    .sdr_dq_13__pad__i(sdr_dq_13__pad__i),
    .sdr_dq_13__pad__o(sdr_dq_13__pad__o),
    .sdr_dq_13__pad__oe(sdr_dq_13__pad__oe),
    .sdr_dq_14__core__i(sdr_dq_14__core__i),
    .sdr_dq_14__core__o(sdr_dq_14__core__o),
    .sdr_dq_14__core__oe(sdr_dq_14__core__oe),
    .sdr_dq_14__pad__i(sdr_dq_14__pad__i),
    .sdr_dq_14__pad__o(sdr_dq_14__pad__o),
    .sdr_dq_14__pad__oe(sdr_dq_14__pad__oe),
    .sdr_dq_15__core__i(sdr_dq_15__core__i),
    .sdr_dq_15__core__o(sdr_dq_15__core__o),
    .sdr_dq_15__core__oe(sdr_dq_15__core__oe),
    .sdr_dq_15__pad__i(sdr_dq_15__pad__i),
    .sdr_dq_15__pad__o(sdr_dq_15__pad__o),
    .sdr_dq_15__pad__oe(sdr_dq_15__pad__oe),
    .sdr_dq_1__core__i(sdr_dq_1__core__i),
    .sdr_dq_1__core__o(sdr_dq_1__core__o),
    .sdr_dq_1__core__oe(sdr_dq_1__core__oe),
    .sdr_dq_1__pad__i(sdr_dq_1__pad__i),
    .sdr_dq_1__pad__o(sdr_dq_1__pad__o),
    .sdr_dq_1__pad__oe(sdr_dq_1__pad__oe),
    .sdr_dq_2__core__i(sdr_dq_2__core__i),
    .sdr_dq_2__core__o(sdr_dq_2__core__o),
    .sdr_dq_2__core__oe(sdr_dq_2__core__oe),
    .sdr_dq_2__pad__i(sdr_dq_2__pad__i),
    .sdr_dq_2__pad__o(sdr_dq_2__pad__o),
    .sdr_dq_2__pad__oe(sdr_dq_2__pad__oe),
    .sdr_dq_3__core__i(sdr_dq_3__core__i),
    .sdr_dq_3__core__o(sdr_dq_3__core__o),
    .sdr_dq_3__core__oe(sdr_dq_3__core__oe),
    .sdr_dq_3__pad__i(sdr_dq_3__pad__i),
    .sdr_dq_3__pad__o(sdr_dq_3__pad__o),
    .sdr_dq_3__pad__oe(sdr_dq_3__pad__oe),
    .sdr_dq_4__core__i(sdr_dq_4__core__i),
    .sdr_dq_4__core__o(sdr_dq_4__core__o),
    .sdr_dq_4__core__oe(sdr_dq_4__core__oe),
    .sdr_dq_4__pad__i(sdr_dq_4__pad__i),
    .sdr_dq_4__pad__o(sdr_dq_4__pad__o),
    .sdr_dq_4__pad__oe(sdr_dq_4__pad__oe),
    .sdr_dq_5__core__i(sdr_dq_5__core__i),
    .sdr_dq_5__core__o(sdr_dq_5__core__o),
    .sdr_dq_5__core__oe(sdr_dq_5__core__oe),
    .sdr_dq_5__pad__i(sdr_dq_5__pad__i),
    .sdr_dq_5__pad__o(sdr_dq_5__pad__o),
    .sdr_dq_5__pad__oe(sdr_dq_5__pad__oe),
    .sdr_dq_6__core__i(sdr_dq_6__core__i),
    .sdr_dq_6__core__o(sdr_dq_6__core__o),
    .sdr_dq_6__core__oe(sdr_dq_6__core__oe),
    .sdr_dq_6__pad__i(sdr_dq_6__pad__i),
    .sdr_dq_6__pad__o(sdr_dq_6__pad__o),
    .sdr_dq_6__pad__oe(sdr_dq_6__pad__oe),
    .sdr_dq_7__core__i(sdr_dq_7__core__i),
    .sdr_dq_7__core__o(sdr_dq_7__core__o),
    .sdr_dq_7__core__oe(sdr_dq_7__core__oe),
    .sdr_dq_7__pad__i(sdr_dq_7__pad__i),
    .sdr_dq_7__pad__o(sdr_dq_7__pad__o),
    .sdr_dq_7__pad__oe(sdr_dq_7__pad__oe),
    .sdr_dq_8__core__i(sdr_dq_8__core__i),
    .sdr_dq_8__core__o(sdr_dq_8__core__o),
    .sdr_dq_8__core__oe(sdr_dq_8__core__oe),
    .sdr_dq_8__pad__i(sdr_dq_8__pad__i),
    .sdr_dq_8__pad__o(sdr_dq_8__pad__o),
    .sdr_dq_8__pad__oe(sdr_dq_8__pad__oe),
    .sdr_dq_9__core__i(sdr_dq_9__core__i),
    .sdr_dq_9__core__o(sdr_dq_9__core__o),
    .sdr_dq_9__core__oe(sdr_dq_9__core__oe),
    .sdr_dq_9__pad__i(sdr_dq_9__pad__i),
    .sdr_dq_9__pad__o(sdr_dq_9__pad__o),
    .sdr_dq_9__pad__oe(sdr_dq_9__pad__oe),
    .sdr_ras_n__core__o(sdr_ras_n__core__o),
    .sdr_ras_n__pad__o(sdr_ras_n__pad__o),
    .sdr_we_n__core__o(sdr_we_n__core__o),
    .sdr_we_n__pad__o(sdr_we_n__pad__o)
  );
  assign ti_coresync_clk = clk;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:194991.1-200214.10" *)
module ti(clk, rst, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, ibus__cyc, ibus__ack, ibus__err, ibus__stb, ibus__sel, ibus__dat_r, ibus__adr, mspi0_clk__core__o, mspi0_cs_n__core__o, mspi0_mosi__core__o, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dq_0__pad__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_1__pad__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_2__pad__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_3__pad__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_4__pad__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_5__pad__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_6__pad__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_7__pad__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_a_0__core__o, sdr_a_1__core__o, sdr_a_2__core__o, sdr_a_3__core__o, sdr_a_4__core__o, sdr_a_5__core__o, sdr_a_6__core__o, sdr_a_7__core__o, sdr_a_8__core__o, sdr_a_9__core__o, sdr_ba_0__core__o, sdr_ba_1__core__o, sdr_clock__core__o, sdr_cke__core__o, sdr_ras_n__core__o, sdr_cas_n__core__o, sdr_we_n__core__o, sdr_cs_n__core__o, sdr_a_10__core__o, sdr_a_11__core__o, sdr_a_12__core__o, sdr_dm_1__core__o, sdr_dq_8__pad__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_9__pad__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_10__pad__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_11__pad__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_12__pad__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_13__pad__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_14__pad__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_15__pad__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, gpio_e8__pad__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e9__pad__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e10__pad__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e11__pad__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e12__pad__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e13__pad__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e14__pad__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e15__pad__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_s0__pad__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s1__pad__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s2__pad__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s3__pad__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s4__pad__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s5__pad__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s6__pad__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s7__pad__i, gpio_s7__core__o, gpio_s7__core__oe, mtwi_sda__pad__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_scl__core__o, eint_0__pad__i, eint_1__pad__i, eint_2__pad__i, TAP_bus__tdi, mspi0_clk__pad__o, mspi0_cs_n__pad__o, mspi0_mosi__pad__o, mspi0_miso__core__i, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__pad__o, sdr_a_1__pad__o, sdr_a_2__pad__o, sdr_a_3__pad__o, sdr_a_4__pad__o, sdr_a_5__pad__o, sdr_a_6__pad__o, sdr_a_7__pad__o, sdr_a_8__pad__o, sdr_a_9__pad__o, sdr_ba_0__pad__o, sdr_ba_1__pad__o, sdr_clock__pad__o, sdr_cke__pad__o, sdr_ras_n__pad__o, sdr_cas_n__pad__o, sdr_we_n__pad__o, sdr_cs_n__pad__o, sdr_a_10__pad__o, sdr_a_11__pad__o, sdr_a_12__pad__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__pad__o, eint_0__core__i, eint_1__core__i, eint_2__core__i, TAP_bus__tdo, jtag_wb__adr, jtag_wb__sel, jtag_wb__stb, jtag_wb__cyc, jtag_wb__we, jtag_wb__dat_w, jtag_wb__ack, jtag_wb__dat_r, TAP_bus__tck, TAP_bus__tms, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _000_;
  (* src = "libresoc.v:197234.3-197235.41" *)
  reg [7:0] _001_;
  (* src = "libresoc.v:198051.3-198086.6" *)
  reg _002_;
  (* src = "libresoc.v:197346.3-197347.57" *)
  reg _003_;
  (* src = "libresoc.v:195280.7-195280.35" *)
  reg _004_;
  (* src = "libresoc.v:198810.3-198827.6" *)
  reg [2:0] _005_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [63:0] _006_;
  (* src = "libresoc.v:197310.3-197311.53" *)
  reg [63:0] _007_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _008_;
  (* src = "libresoc.v:197354.3-197355.57" *)
  reg [7:0] _009_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _010_;
  (* src = "libresoc.v:197356.3-197357.63" *)
  reg _011_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _012_;
  (* src = "libresoc.v:197358.3-197359.57" *)
  reg [7:0] _013_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _014_;
  (* src = "libresoc.v:197336.3-197337.75" *)
  reg _015_;
  (* src = "libresoc.v:195306.7-195306.44" *)
  reg _016_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _017_;
  (* src = "libresoc.v:197338.3-197339.75" *)
  reg _018_;
  (* src = "libresoc.v:195310.7-195310.44" *)
  reg _019_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _020_;
  (* src = "libresoc.v:197340.3-197341.75" *)
  reg _021_;
  (* src = "libresoc.v:195314.7-195314.44" *)
  reg _022_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _023_;
  (* src = "libresoc.v:197342.3-197343.75" *)
  reg _024_;
  (* src = "libresoc.v:195318.7-195318.44" *)
  reg _025_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _026_;
  (* src = "libresoc.v:197344.3-197345.75" *)
  reg _027_;
  (* src = "libresoc.v:195322.7-195322.44" *)
  reg _028_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _029_;
  (* src = "libresoc.v:197348.3-197349.75" *)
  reg _030_;
  (* src = "libresoc.v:195326.7-195326.44" *)
  reg _031_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _032_;
  (* src = "libresoc.v:197350.3-197351.75" *)
  reg _033_;
  (* src = "libresoc.v:195330.7-195330.44" *)
  reg _034_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _035_;
  (* src = "libresoc.v:197334.3-197335.71" *)
  reg _036_;
  (* src = "libresoc.v:195304.7-195304.42" *)
  reg _037_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [13:0] _038_;
  (* src = "libresoc.v:197316.3-197317.61" *)
  reg [13:0] _039_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [1:0] _040_;
  (* src = "libresoc.v:197330.3-197331.69" *)
  reg [1:0] _041_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [31:0] _042_;
  (* src = "libresoc.v:197312.3-197313.55" *)
  reg [31:0] _043_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _044_;
  (* src = "libresoc.v:197314.3-197315.65" *)
  reg [6:0] _045_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _046_;
  (* src = "libresoc.v:197362.3-197363.63" *)
  reg _047_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [63:0] _048_;
  (* src = "libresoc.v:197308.3-197309.53" *)
  reg [63:0] _049_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _050_;
  (* src = "libresoc.v:197326.3-197327.51" *)
  reg _051_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _052_;
  (* src = "libresoc.v:197328.3-197329.57" *)
  reg _053_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _054_;
  (* src = "libresoc.v:197320.3-197321.51" *)
  reg _055_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _056_;
  (* src = "libresoc.v:197322.3-197323.57" *)
  reg _057_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [12:0] _058_;
  (* src = "libresoc.v:197352.3-197353.63" *)
  reg [12:0] _059_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _060_;
  (* src = "libresoc.v:197332.3-197333.63" *)
  reg [7:0] _061_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _062_;
  (* src = "libresoc.v:197290.3-197291.49" *)
  reg [6:0] _063_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _064_;
  (* src = "libresoc.v:197292.3-197293.55" *)
  reg _065_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _066_;
  (* src = "libresoc.v:197298.3-197299.55" *)
  reg [6:0] _067_;
  (* src = "libresoc.v:195488.13-195488.41" *)
  reg [6:0] _068_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _069_;
  (* src = "libresoc.v:197294.3-197295.49" *)
  reg [6:0] _070_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _071_;
  (* src = "libresoc.v:197300.3-197301.61" *)
  reg _072_;
  (* src = "libresoc.v:195496.7-195496.37" *)
  reg _073_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _074_;
  (* src = "libresoc.v:197296.3-197297.55" *)
  reg _075_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _076_;
  (* src = "libresoc.v:197304.3-197305.49" *)
  reg [6:0] _077_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _078_;
  (* src = "libresoc.v:197360.3-197361.53" *)
  reg _079_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _080_;
  (* src = "libresoc.v:197226.3-197227.51" *)
  reg [6:0] _081_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _082_;
  (* src = "libresoc.v:197242.3-197243.41" *)
  reg [6:0] _083_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _084_;
  (* src = "libresoc.v:197272.3-197273.47" *)
  reg [2:0] _085_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _086_;
  (* src = "libresoc.v:197274.3-197275.53" *)
  reg _087_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _088_;
  (* src = "libresoc.v:197276.3-197277.47" *)
  reg [2:0] _089_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _090_;
  (* src = "libresoc.v:197278.3-197279.53" *)
  reg _091_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _092_;
  (* src = "libresoc.v:197282.3-197283.49" *)
  reg [2:0] _093_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _094_;
  (* src = "libresoc.v:197286.3-197287.49" *)
  reg [2:0] _095_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _096_;
  (* src = "libresoc.v:197318.3-197319.41" *)
  reg _097_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _098_;
  (* src = "libresoc.v:197232.3-197233.47" *)
  reg [6:0] _099_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _100_;
  (* src = "libresoc.v:197390.3-197391.41" *)
  reg [63:0] _101_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _102_;
  (* src = "libresoc.v:197246.3-197247.45" *)
  reg [6:0] _103_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _104_;
  (* src = "libresoc.v:197248.3-197249.51" *)
  reg _105_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _106_;
  (* src = "libresoc.v:197250.3-197251.45" *)
  reg [6:0] _107_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _108_;
  (* src = "libresoc.v:197252.3-197253.51" *)
  reg _109_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _110_;
  (* src = "libresoc.v:197254.3-197255.45" *)
  reg [6:0] _111_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _112_;
  (* src = "libresoc.v:197256.3-197257.51" *)
  reg _113_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _114_;
  (* src = "libresoc.v:197238.3-197239.45" *)
  reg [6:0] _115_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [9:0] _116_;
  (* src = "libresoc.v:197264.3-197265.45" *)
  reg [9:0] _117_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _118_;
  (* src = "libresoc.v:197266.3-197267.51" *)
  reg _119_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [9:0] _120_;
  (* src = "libresoc.v:197260.3-197261.45" *)
  reg [9:0] _121_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _122_;
  (* src = "libresoc.v:197228.3-197229.51" *)
  reg [6:0] _123_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _124_;
  (* src = "libresoc.v:197224.3-197225.47" *)
  reg [1:0] _125_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _126_;
  (* src = "libresoc.v:197222.3-197223.49" *)
  reg [1:0] _127_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _128_;
  (* src = "libresoc.v:197230.3-197231.41" *)
  reg [6:0] _129_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _130_;
  (* src = "libresoc.v:197268.3-197269.49" *)
  reg [2:0] _131_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _132_;
  (* src = "libresoc.v:197306.3-197307.45" *)
  reg _133_;
  (* src = "libresoc.v:198261.3-198270.6" *)
  reg [63:0] _134_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _135_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _136_;
  (* src = "libresoc.v:197220.3-197221.33" *)
  reg [63:0] _137_;
  (* src = "libresoc.v:198378.3-198387.6" *)
  reg [4:0] _138_;
  (* src = "libresoc.v:198388.3-198397.6" *)
  reg _139_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _140_;
  (* src = "libresoc.v:197244.3-197245.37" *)
  reg _141_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg _142_;
  (* src = "libresoc.v:197218.3-197219.35" *)
  reg _143_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _144_;
  (* src = "libresoc.v:197284.3-197285.45" *)
  reg _145_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _146_;
  (* src = "libresoc.v:197288.3-197289.45" *)
  reg _147_;
  (* src = "libresoc.v:198427.3-198436.6" *)
  reg [7:0] _148_;
  (* src = "libresoc.v:198466.3-198475.6" *)
  reg [2:0] _149_;
  (* src = "libresoc.v:198586.3-198608.6" *)
  reg [2:0] _150_;
  (* src = "libresoc.v:198505.3-198523.6" *)
  reg [2:0] _151_;
  (* src = "libresoc.v:198632.3-198654.6" *)
  reg [63:0] _152_;
  (* src = "libresoc.v:198524.3-198542.6" *)
  reg _153_;
  (* src = "libresoc.v:198609.3-198631.6" *)
  reg _154_;
  (* src = "libresoc.v:198307.3-198322.6" *)
  reg _155_;
  (* src = "libresoc.v:198282.3-198306.6" *)
  reg _156_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _157_;
  (* src = "libresoc.v:197206.3-197207.33" *)
  reg [63:0] _158_;
  (* src = "libresoc.v:199060.3-199075.6" *)
  reg [2:0] _159_;
  (* src = "libresoc.v:198015.3-198050.6" *)
  reg [31:0] _160_;
  (* src = "libresoc.v:197368.3-197369.47" *)
  reg [31:0] _161_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _162_;
  (* src = "libresoc.v:197240.3-197241.41" *)
  reg _163_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _164_;
  (* src = "libresoc.v:197262.3-197263.41" *)
  reg _165_;
  (* src = "libresoc.v:199576.3-199630.6" *)
  reg _166_;
  (* src = "libresoc.v:198866.3-198883.6" *)
  reg [2:0] _167_;
  (* src = "libresoc.v:198087.3-198122.6" *)
  reg _168_;
  (* src = "libresoc.v:197324.3-197325.41" *)
  reg _169_;
  (* src = "libresoc.v:198251.3-198260.6" *)
  reg [2:0] _170_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _171_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _172_;
  (* src = "libresoc.v:197270.3-197271.41" *)
  reg _173_;
  (* src = "libresoc.v:197384.3-197385.43" *)
  reg _174_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _175_;
  (* src = "libresoc.v:197402.3-197403.47" *)
  reg [6:0] _176_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _177_;
  (* src = "libresoc.v:197408.3-197409.43" *)
  reg [6:0] _178_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _179_;
  (* src = "libresoc.v:197404.3-197405.47" *)
  reg [6:0] _180_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _181_;
  (* src = "libresoc.v:197400.3-197401.43" *)
  reg [1:0] _182_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _183_;
  (* src = "libresoc.v:197398.3-197399.45" *)
  reg [1:0] _184_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _185_;
  (* src = "libresoc.v:197406.3-197407.37" *)
  reg [6:0] _186_;
  (* src = "libresoc.v:198437.3-198445.6" *)
  reg _187_;
  (* src = "libresoc.v:197258.3-197259.37" *)
  reg _188_;
  (* src = "libresoc.v:198398.3-198406.6" *)
  reg _189_;
  (* src = "libresoc.v:197280.3-197281.39" *)
  reg _190_;
  (* src = "libresoc.v:198476.3-198484.6" *)
  reg _191_;
  (* src = "libresoc.v:197236.3-197237.39" *)
  reg _192_;
  (* src = "libresoc.v:199631.3-199685.6" *)
  reg _193_;
  (* src = "libresoc.v:198456.3-198465.6" *)
  reg _194_;
  (* src = "libresoc.v:198446.3-198455.6" *)
  reg [63:0] _195_;
  (* src = "libresoc.v:198417.3-198426.6" *)
  reg _196_;
  (* src = "libresoc.v:198407.3-198416.6" *)
  reg [63:0] _197_;
  (* src = "libresoc.v:198495.3-198504.6" *)
  reg _198_;
  (* src = "libresoc.v:198485.3-198494.6" *)
  reg [63:0] _199_;
  (* src = "libresoc.v:197941.3-197949.6" *)
  reg [3:0] _200_;
  (* src = "libresoc.v:197216.3-197217.45" *)
  reg [3:0] _201_;
  (* src = "libresoc.v:198778.3-198786.6" *)
  reg [63:0] _202_;
  (* src = "libresoc.v:197210.3-197211.39" *)
  reg [63:0] _203_;
  (* src = "libresoc.v:197950.3-197958.6" *)
  reg _204_;
  (* src = "libresoc.v:197214.3-197215.43" *)
  reg _205_;
  (* src = "libresoc.v:198754.3-198762.6" *)
  reg _206_;
  (* src = "libresoc.v:197212.3-197213.41" *)
  reg _207_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _208_;
  (* src = "libresoc.v:197396.3-197397.41" *)
  reg [63:0] _209_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg _210_;
  (* src = "libresoc.v:197388.3-197389.43" *)
  reg _211_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _212_;
  (* src = "libresoc.v:197394.3-197395.41" *)
  reg [63:0] _213_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _214_;
  (* src = "libresoc.v:197392.3-197393.39" *)
  reg [63:0] _215_;
  (* src = "libresoc.v:199307.3-199341.6" *)
  reg [31:0] _216_;
  (* src = "libresoc.v:197372.3-197373.53" *)
  reg [31:0] _217_;
  (* src = "libresoc.v:200174.3-200183.6" *)
  reg [1:0] _218_;
  (* src = "libresoc.v:197386.3-197387.27" *)
  reg [1:0] _219_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _220_;
  (* src = "libresoc.v:197302.3-197303.45" *)
  reg _221_;
  (* src = "libresoc.v:198271.3-198281.6" *)
  reg _222_;
  (* src = "libresoc.v:198123.3-198157.6" *)
  reg _223_;
  (* src = "libresoc.v:198158.3-198201.6" *)
  reg _224_;
  (* src = "libresoc.v:198358.3-198377.6" *)
  reg _225_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _226_;
  (* src = "libresoc.v:197374.3-197375.47" *)
  reg [1:0] _227_;
  (* src = "libresoc.v:199949.3-199963.6" *)
  reg _228_;
  (* src = "libresoc.v:199342.3-199364.6" *)
  reg _229_;
  (* src = "libresoc.v:199119.3-199129.6" *)
  reg _230_;
  (* src = "libresoc.v:199452.3-199467.6" *)
  reg _231_;
  (* src = "libresoc.v:198543.3-198570.6" *)
  reg [1:0] _232_;
  (* src = "libresoc.v:197204.3-197205.35" *)
  reg [1:0] _233_;
  (* src = "libresoc.v:199130.3-199145.6" *)
  reg [47:0] _234_;
  (* src = "libresoc.v:199155.3-199188.6" *)
  reg _235_;
  (* src = "libresoc.v:199189.3-199222.6" *)
  reg _236_;
  (* src = "libresoc.v:194992.7-194992.20" *)
  reg _237_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _238_;
  (* src = "libresoc.v:198202.3-198250.6" *)
  reg _239_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _240_;
  (* src = "libresoc.v:197370.3-197371.47" *)
  reg [2:0] _241_;
  (* src = "libresoc.v:199110.3-199118.6" *)
  reg _242_;
  (* src = "libresoc.v:197208.3-197209.49" *)
  reg _243_;
  (* src = "libresoc.v:199146.3-199154.6" *)
  reg [63:0] _244_;
  (* src = "libresoc.v:197410.3-197411.47" *)
  reg [63:0] _245_;
  (* src = "libresoc.v:199223.3-199252.6" *)
  reg _246_;
  (* src = "libresoc.v:197376.3-197377.33" *)
  reg _247_;
  (* src = "libresoc.v:198571.3-198585.6" *)
  reg [63:0] _248_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _249_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _250_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _251_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _252_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _253_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _254_;
  (* src = "libresoc.v:198655.3-198677.6" *)
  reg [63:0] _255_;
  (* src = "libresoc.v:199076.3-199109.6" *)
  reg [63:0] _256_;
  (* src = "libresoc.v:197378.3-197379.23" *)
  reg [63:0] _257_;
  (* src = "libresoc.v:198787.3-198809.6" *)
  reg [63:0] _258_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _259_;
  (* src = "libresoc.v:197366.3-197367.37" *)
  reg _260_;
  (* src = "libresoc.v:198763.3-198777.6" *)
  reg _261_;
  (* src = "libresoc.v:197382.3-197383.39" *)
  reg _262_;
  (* src = "libresoc.v:200010.3-200028.6" *)
  reg _263_;
  (* src = "libresoc.v:200029.3-200051.6" *)
  reg _264_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _265_;
  (* src = "libresoc.v:197364.3-197365.37" *)
  reg _266_;
  (* src = "libresoc.v:198843.3-198865.6" *)
  reg [63:0] _267_;
  (* src = "libresoc.v:198828.3-198842.6" *)
  reg _268_;
  (* src = "libresoc.v:197380.3-197381.49" *)
  reg _269_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _270_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _271_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _272_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _273_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _274_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _275_;
  (* src = "libresoc.v:195274.13-195274.33" *)
  reg [7:0] _276_;
  (* src = "libresoc.v:198051.3-198086.6" *)
  reg _277_;
  (* src = "libresoc.v:198810.3-198827.6" *)
  reg [2:0] _278_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [63:0] _279_;
  (* src = "libresoc.v:195288.14-195288.55" *)
  reg [63:0] _280_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _281_;
  (* src = "libresoc.v:195292.13-195292.41" *)
  reg [7:0] _282_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _283_;
  (* src = "libresoc.v:195296.7-195296.37" *)
  reg _284_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _285_;
  (* src = "libresoc.v:195300.13-195300.41" *)
  reg [7:0] _286_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _287_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _288_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _289_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _290_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _291_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _292_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _293_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _294_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [13:0] _295_;
  (* src = "libresoc.v:195351.14-195351.47" *)
  reg [13:0] _296_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [1:0] _297_;
  (* src = "libresoc.v:195359.13-195359.46" *)
  reg [1:0] _298_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [31:0] _299_;
  (* src = "libresoc.v:195363.14-195363.41" *)
  reg [31:0] _300_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _301_;
  (* src = "libresoc.v:195442.13-195442.45" *)
  reg [6:0] _302_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _303_;
  (* src = "libresoc.v:195446.7-195446.37" *)
  reg _304_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [63:0] _305_;
  (* src = "libresoc.v:195450.14-195450.55" *)
  reg [63:0] _306_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _307_;
  (* src = "libresoc.v:195454.7-195454.31" *)
  reg _308_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _309_;
  (* src = "libresoc.v:195458.7-195458.34" *)
  reg _310_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _311_;
  (* src = "libresoc.v:195462.7-195462.31" *)
  reg _312_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _313_;
  (* src = "libresoc.v:195466.7-195466.34" *)
  reg _314_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [12:0] _315_;
  (* src = "libresoc.v:195470.14-195470.48" *)
  reg [12:0] _316_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [7:0] _317_;
  (* src = "libresoc.v:195474.13-195474.44" *)
  reg [7:0] _318_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _319_;
  (* src = "libresoc.v:195478.13-195478.37" *)
  reg [6:0] _320_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _321_;
  (* src = "libresoc.v:195482.7-195482.33" *)
  reg _322_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _323_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _324_;
  (* src = "libresoc.v:195486.13-195486.37" *)
  reg [6:0] _325_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _326_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _327_;
  (* src = "libresoc.v:195494.7-195494.33" *)
  reg _328_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _329_;
  (* src = "libresoc.v:195502.13-195502.37" *)
  reg [6:0] _330_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _331_;
  (* src = "libresoc.v:195506.7-195506.32" *)
  reg _332_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _333_;
  (* src = "libresoc.v:195510.13-195510.38" *)
  reg [6:0] _334_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _335_;
  (* src = "libresoc.v:195514.13-195514.33" *)
  reg [6:0] _336_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _337_;
  (* src = "libresoc.v:195518.13-195518.35" *)
  reg [2:0] _338_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _339_;
  (* src = "libresoc.v:195522.7-195522.32" *)
  reg _340_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _341_;
  (* src = "libresoc.v:195526.13-195526.35" *)
  reg [2:0] _342_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _343_;
  (* src = "libresoc.v:195530.7-195530.32" *)
  reg _344_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _345_;
  (* src = "libresoc.v:195534.13-195534.36" *)
  reg [2:0] _346_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _347_;
  (* src = "libresoc.v:195538.13-195538.36" *)
  reg [2:0] _348_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _349_;
  (* src = "libresoc.v:195542.7-195542.26" *)
  reg _350_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _351_;
  (* src = "libresoc.v:195546.13-195546.36" *)
  reg [6:0] _352_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _353_;
  (* src = "libresoc.v:195550.14-195550.49" *)
  reg [63:0] _354_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _355_;
  (* src = "libresoc.v:195554.13-195554.35" *)
  reg [6:0] _356_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _357_;
  (* src = "libresoc.v:195558.7-195558.31" *)
  reg _358_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _359_;
  (* src = "libresoc.v:195562.13-195562.35" *)
  reg [6:0] _360_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _361_;
  (* src = "libresoc.v:195566.7-195566.31" *)
  reg _362_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _363_;
  (* src = "libresoc.v:195570.13-195570.35" *)
  reg [6:0] _364_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _365_;
  (* src = "libresoc.v:195574.7-195574.31" *)
  reg _366_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [6:0] _367_;
  (* src = "libresoc.v:195578.13-195578.35" *)
  reg [6:0] _368_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [9:0] _369_;
  (* src = "libresoc.v:195594.13-195594.37" *)
  reg [9:0] _370_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _371_;
  (* src = "libresoc.v:195598.7-195598.31" *)
  reg _372_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [9:0] _373_;
  (* src = "libresoc.v:195614.13-195614.37" *)
  reg [9:0] _374_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _375_;
  (* src = "libresoc.v:195618.13-195618.38" *)
  reg [6:0] _376_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _377_;
  (* src = "libresoc.v:195622.13-195622.35" *)
  reg [1:0] _378_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _379_;
  (* src = "libresoc.v:195626.13-195626.36" *)
  reg [1:0] _380_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _381_;
  (* src = "libresoc.v:195632.13-195632.33" *)
  reg [6:0] _382_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg [2:0] _383_;
  (* src = "libresoc.v:195636.13-195636.36" *)
  reg [2:0] _384_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _385_;
  (* src = "libresoc.v:195644.7-195644.28" *)
  reg _386_;
  (* src = "libresoc.v:198261.3-198270.6" *)
  reg [63:0] _387_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _388_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _389_;
  (* src = "libresoc.v:195660.14-195660.45" *)
  reg [63:0] _390_;
  (* src = "libresoc.v:198378.3-198387.6" *)
  reg [4:0] _391_;
  (* src = "libresoc.v:198388.3-198397.6" *)
  reg _392_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _393_;
  (* src = "libresoc.v:195670.7-195670.24" *)
  reg _394_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg _395_;
  (* src = "libresoc.v:195674.7-195674.23" *)
  reg _396_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _397_;
  (* src = "libresoc.v:195678.7-195678.28" *)
  reg _398_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _399_;
  (* src = "libresoc.v:195682.7-195682.28" *)
  reg _400_;
  (* src = "libresoc.v:198427.3-198436.6" *)
  reg [7:0] _401_;
  (* src = "libresoc.v:198466.3-198475.6" *)
  reg [2:0] _402_;
  (* src = "libresoc.v:198586.3-198608.6" *)
  reg [2:0] _403_;
  (* src = "libresoc.v:198505.3-198523.6" *)
  reg [2:0] _404_;
  (* src = "libresoc.v:198632.3-198654.6" *)
  reg [63:0] _405_;
  (* src = "libresoc.v:198524.3-198542.6" *)
  reg _406_;
  (* src = "libresoc.v:198609.3-198631.6" *)
  reg _407_;
  (* src = "libresoc.v:198307.3-198322.6" *)
  reg _408_;
  (* src = "libresoc.v:198282.3-198306.6" *)
  reg _409_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _410_;
  (* src = "libresoc.v:195710.14-195710.45" *)
  reg [63:0] _411_;
  (* src = "libresoc.v:199060.3-199075.6" *)
  reg [2:0] _412_;
  (* src = "libresoc.v:198015.3-198050.6" *)
  reg [31:0] _413_;
  (* src = "libresoc.v:195718.14-195718.37" *)
  reg [31:0] _414_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _415_;
  (* src = "libresoc.v:195722.7-195722.26" *)
  reg _416_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _417_;
  (* src = "libresoc.v:195726.7-195726.26" *)
  reg _418_;
  (* src = "libresoc.v:199576.3-199630.6" *)
  reg _419_;
  (* src = "libresoc.v:198866.3-198883.6" *)
  reg [2:0] _420_;
  (* src = "libresoc.v:198087.3-198122.6" *)
  reg _421_;
  (* src = "libresoc.v:195738.7-195738.26" *)
  reg _422_;
  (* src = "libresoc.v:198251.3-198260.6" *)
  reg [2:0] _423_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _424_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _425_;
  (* src = "libresoc.v:195748.7-195748.26" *)
  reg _426_;
  (* src = "libresoc.v:195754.7-195754.30" *)
  reg _427_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _428_;
  (* src = "libresoc.v:195760.13-195760.36" *)
  reg [6:0] _429_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _430_;
  (* src = "libresoc.v:195764.13-195764.34" *)
  reg [6:0] _431_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _432_;
  (* src = "libresoc.v:195768.13-195768.36" *)
  reg [6:0] _433_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _434_;
  (* src = "libresoc.v:195772.13-195772.33" *)
  reg [1:0] _435_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _436_;
  (* src = "libresoc.v:195776.13-195776.34" *)
  reg [1:0] _437_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _438_;
  (* src = "libresoc.v:195780.13-195780.31" *)
  reg [6:0] _439_;
  (* src = "libresoc.v:198437.3-198445.6" *)
  reg _440_;
  (* src = "libresoc.v:195784.7-195784.24" *)
  reg _441_;
  (* src = "libresoc.v:198398.3-198406.6" *)
  reg _442_;
  (* src = "libresoc.v:195788.7-195788.25" *)
  reg _443_;
  (* src = "libresoc.v:198476.3-198484.6" *)
  reg _444_;
  (* src = "libresoc.v:195792.7-195792.25" *)
  reg _445_;
  (* src = "libresoc.v:199631.3-199685.6" *)
  reg _446_;
  (* src = "libresoc.v:198456.3-198465.6" *)
  reg _447_;
  (* src = "libresoc.v:198446.3-198455.6" *)
  reg [63:0] _448_;
  (* src = "libresoc.v:198417.3-198426.6" *)
  reg _449_;
  (* src = "libresoc.v:198407.3-198416.6" *)
  reg [63:0] _450_;
  (* src = "libresoc.v:198495.3-198504.6" *)
  reg _451_;
  (* src = "libresoc.v:198485.3-198494.6" *)
  reg [63:0] _452_;
  (* src = "libresoc.v:197941.3-197949.6" *)
  reg [3:0] _453_;
  (* src = "libresoc.v:195840.13-195840.34" *)
  reg [3:0] _454_;
  (* src = "libresoc.v:198778.3-198786.6" *)
  reg [63:0] _455_;
  (* src = "libresoc.v:195844.14-195844.48" *)
  reg [63:0] _456_;
  (* src = "libresoc.v:197950.3-197958.6" *)
  reg _457_;
  (* src = "libresoc.v:195850.7-195850.27" *)
  reg _458_;
  (* src = "libresoc.v:198754.3-198762.6" *)
  reg _459_;
  (* src = "libresoc.v:195854.7-195854.26" *)
  reg _460_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _461_;
  (* src = "libresoc.v:195908.14-195908.49" *)
  reg [63:0] _462_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg _463_;
  (* src = "libresoc.v:195912.7-195912.27" *)
  reg _464_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _465_;
  (* src = "libresoc.v:195916.14-195916.49" *)
  reg [63:0] _466_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _467_;
  (* src = "libresoc.v:195920.14-195920.48" *)
  reg [63:0] _468_;
  (* src = "libresoc.v:199307.3-199341.6" *)
  reg [31:0] _469_;
  (* src = "libresoc.v:196072.14-196072.40" *)
  reg [31:0] _470_;
  (* src = "libresoc.v:200174.3-200183.6" *)
  reg [1:0] _471_;
  (* src = "libresoc.v:196342.13-196342.25" *)
  reg [1:0] _472_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _473_;
  (* src = "libresoc.v:196358.7-196358.28" *)
  reg _474_;
  (* src = "libresoc.v:198271.3-198281.6" *)
  reg _475_;
  (* src = "libresoc.v:198123.3-198157.6" *)
  reg _476_;
  (* src = "libresoc.v:198158.3-198201.6" *)
  reg _477_;
  (* src = "libresoc.v:198358.3-198377.6" *)
  reg _478_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _479_;
  (* src = "libresoc.v:196370.13-196370.35" *)
  reg [1:0] _480_;
  (* src = "libresoc.v:199949.3-199963.6" *)
  reg _481_;
  (* src = "libresoc.v:199342.3-199364.6" *)
  reg _482_;
  (* src = "libresoc.v:199119.3-199129.6" *)
  reg _483_;
  (* src = "libresoc.v:199452.3-199467.6" *)
  reg _484_;
  (* src = "libresoc.v:198543.3-198570.6" *)
  reg [1:0] _485_;
  (* src = "libresoc.v:196382.13-196382.29" *)
  reg [1:0] _486_;
  (* src = "libresoc.v:199130.3-199145.6" *)
  reg [47:0] _487_;
  (* src = "libresoc.v:199155.3-199188.6" *)
  reg _488_;
  (* src = "libresoc.v:199189.3-199222.6" *)
  reg _489_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _490_;
  (* src = "libresoc.v:198202.3-198250.6" *)
  reg _491_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _492_;
  (* src = "libresoc.v:196642.13-196642.35" *)
  reg [2:0] _493_;
  (* src = "libresoc.v:199110.3-199118.6" *)
  reg _494_;
  (* src = "libresoc.v:196646.7-196646.30" *)
  reg _495_;
  (* src = "libresoc.v:199146.3-199154.6" *)
  reg [63:0] _496_;
  (* src = "libresoc.v:196654.14-196654.52" *)
  reg [63:0] _497_;
  (* src = "libresoc.v:199223.3-199252.6" *)
  reg _498_;
  (* src = "libresoc.v:196694.7-196694.22" *)
  reg _499_;
  (* src = "libresoc.v:198571.3-198585.6" *)
  reg [63:0] _500_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _501_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _502_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _503_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _504_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _505_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _506_;
  (* src = "libresoc.v:198655.3-198677.6" *)
  reg [63:0] _507_;
  (* src = "libresoc.v:199076.3-199109.6" *)
  reg [63:0] _508_;
  (* src = "libresoc.v:196734.14-196734.40" *)
  reg [63:0] _509_;
  (* src = "libresoc.v:198787.3-198809.6" *)
  reg [63:0] _510_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _511_;
  (* src = "libresoc.v:196740.7-196740.24" *)
  reg _512_;
  (* src = "libresoc.v:198763.3-198777.6" *)
  reg _513_;
  (* src = "libresoc.v:196750.7-196750.25" *)
  reg _514_;
  (* src = "libresoc.v:200010.3-200028.6" *)
  reg _515_;
  (* src = "libresoc.v:200029.3-200051.6" *)
  reg _516_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _517_;
  (* src = "libresoc.v:197050.7-197050.24" *)
  reg _518_;
  (* src = "libresoc.v:198843.3-198865.6" *)
  reg [63:0] _519_;
  (* src = "libresoc.v:198828.3-198842.6" *)
  reg _520_;
  (* src = "libresoc.v:197060.7-197060.30" *)
  reg _521_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _522_;
  (* src = "libresoc.v:198051.3-198086.6" *)
  reg _523_;
  (* src = "libresoc.v:198810.3-198827.6" *)
  reg [2:0] _524_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _525_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _526_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _527_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _528_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _529_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _530_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _531_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _532_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _533_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _534_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _535_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _536_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _537_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _538_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _539_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _540_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _541_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _542_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _543_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _544_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _545_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _546_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _547_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _548_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _549_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _550_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [1:0] _551_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [6:0] _552_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _553_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _554_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _555_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _556_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg _557_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _558_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _559_;
  (* src = "libresoc.v:198307.3-198322.6" *)
  reg _560_;
  (* src = "libresoc.v:198282.3-198306.6" *)
  reg _561_;
  (* src = "libresoc.v:197959.3-198014.6" *)
  reg [63:0] _562_;
  (* src = "libresoc.v:199060.3-199075.6" *)
  reg [2:0] _563_;
  (* src = "libresoc.v:198015.3-198050.6" *)
  reg [31:0] _564_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _565_;
  (* src = "libresoc.v:200052.3-200173.6" *)
  reg _566_;
  (* src = "libresoc.v:199576.3-199630.6" *)
  reg _567_;
  (* src = "libresoc.v:198866.3-198883.6" *)
  reg [2:0] _568_;
  (* src = "libresoc.v:198087.3-198122.6" *)
  reg _569_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _570_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _571_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _572_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _573_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _574_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _575_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _576_;
  (* src = "libresoc.v:199631.3-199685.6" *)
  reg _577_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _578_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg _579_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _580_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _581_;
  (* src = "libresoc.v:199307.3-199341.6" *)
  reg [31:0] _582_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _583_;
  (* src = "libresoc.v:198158.3-198201.6" *)
  reg _584_;
  (* src = "libresoc.v:198358.3-198377.6" *)
  reg _585_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _586_;
  (* src = "libresoc.v:199452.3-199467.6" *)
  reg _587_;
  (* src = "libresoc.v:198543.3-198570.6" *)
  reg [1:0] _588_;
  (* src = "libresoc.v:199130.3-199145.6" *)
  reg [47:0] _589_;
  (* src = "libresoc.v:199155.3-199188.6" *)
  reg _590_;
  (* src = "libresoc.v:199189.3-199222.6" *)
  reg _591_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _592_;
  (* src = "libresoc.v:198202.3-198250.6" *)
  reg _593_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _594_;
  (* src = "libresoc.v:199223.3-199252.6" *)
  reg _595_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _596_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _597_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _598_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _599_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _600_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _601_;
  (* src = "libresoc.v:199076.3-199109.6" *)
  reg [63:0] _602_;
  (* src = "libresoc.v:198787.3-198809.6" *)
  reg [63:0] _603_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _604_;
  (* src = "libresoc.v:198763.3-198777.6" *)
  reg _605_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _606_;
  (* src = "libresoc.v:198843.3-198865.6" *)
  reg [63:0] _607_;
  (* src = "libresoc.v:198828.3-198842.6" *)
  reg _608_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _609_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _610_;
  (* src = "libresoc.v:198282.3-198306.6" *)
  reg _611_;
  (* src = "libresoc.v:199576.3-199630.6" *)
  reg _612_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _613_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _614_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _615_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _616_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _617_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _618_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _619_;
  (* src = "libresoc.v:199631.3-199685.6" *)
  reg _620_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _621_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _622_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _623_;
  (* src = "libresoc.v:199307.3-199341.6" *)
  reg [31:0] _624_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _625_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _626_;
  (* src = "libresoc.v:199155.3-199188.6" *)
  reg _627_;
  (* src = "libresoc.v:199189.3-199222.6" *)
  reg _628_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _629_;
  (* src = "libresoc.v:198202.3-198250.6" *)
  reg _630_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _631_;
  (* src = "libresoc.v:199223.3-199252.6" *)
  reg _632_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _633_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _634_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _635_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _636_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _637_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _638_;
  (* src = "libresoc.v:199076.3-199109.6" *)
  reg [63:0] _639_;
  (* src = "libresoc.v:198787.3-198809.6" *)
  reg [63:0] _640_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _641_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _642_;
  (* src = "libresoc.v:198843.3-198865.6" *)
  reg [63:0] _643_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _644_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _645_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _646_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _647_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _648_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _649_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _650_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _651_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _652_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _653_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [63:0] _654_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _655_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _656_;
  (* src = "libresoc.v:199155.3-199188.6" *)
  reg _657_;
  (* src = "libresoc.v:199189.3-199222.6" *)
  reg _658_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _659_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _660_;
  (* src = "libresoc.v:199223.3-199252.6" *)
  reg _661_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _662_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _663_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _664_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _665_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _666_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _667_;
  (* src = "libresoc.v:199076.3-199109.6" *)
  reg [63:0] _668_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _669_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _670_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _671_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _672_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _673_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _674_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _675_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _676_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _677_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [1:0] _678_;
  (* src = "libresoc.v:198678.3-198753.6" *)
  reg [6:0] _679_;
  (* src = "libresoc.v:198323.3-198357.6" *)
  reg _680_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _681_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _682_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _683_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _684_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _685_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _686_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _687_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [1:0] _688_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _689_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _690_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _691_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _692_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _693_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _694_;
  (* src = "libresoc.v:199253.3-199306.6" *)
  reg [1:0] _695_;
  (* src = "libresoc.v:199964.3-200009.6" *)
  reg _696_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _697_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _698_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _699_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _700_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _701_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _702_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _703_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _704_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _705_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _706_;
  (* src = "libresoc.v:199365.3-199451.6" *)
  reg [6:0] _707_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _708_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _709_;
  (* src = "libresoc.v:199777.3-199857.6" *)
  reg _710_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _711_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _712_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _713_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _714_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _715_;
  (* src = "libresoc.v:198972.3-199059.6" *)
  reg [63:0] _716_;
  (* src = "libresoc.v:198884.3-198971.6" *)
  reg [2:0] _717_;
  (* src = "libresoc.v:199468.3-199575.6" *)
  reg [2:0] _718_;
  (* src = "libresoc.v:199686.3-199776.6" *)
  reg _719_;
  (* src = "libresoc.v:199858.3-199948.6" *)
  reg _720_;
  (* src = "libresoc.v:197078.19-197078.108" *)
  wire [64:0] _721_;
  (* src = "libresoc.v:197082.19-197082.108" *)
  wire [64:0] _722_;
  (* src = "libresoc.v:197094.19-197094.112" *)
  wire [7:0] _723_;
  (* src = "libresoc.v:197095.19-197095.112" *)
  wire [7:0] _724_;
  (* src = "libresoc.v:197167.19-197167.116" *)
  wire [64:0] _725_;
  (* src = "libresoc.v:197087.19-197087.104" *)
  wire _726_;
  (* src = "libresoc.v:197090.19-197090.104" *)
  wire _727_;
  (* src = "libresoc.v:197098.19-197098.104" *)
  wire _728_;
  (* src = "libresoc.v:197101.19-197101.104" *)
  wire _729_;
  (* src = "libresoc.v:197103.19-197103.111" *)
  wire _730_;
  (* src = "libresoc.v:197107.19-197107.104" *)
  wire _731_;
  (* src = "libresoc.v:197113.19-197113.104" *)
  wire _732_;
  (* src = "libresoc.v:197116.19-197116.104" *)
  wire _733_;
  (* src = "libresoc.v:197119.19-197119.104" *)
  wire _734_;
  (* src = "libresoc.v:197122.19-197122.104" *)
  wire _735_;
  (* src = "libresoc.v:197125.19-197125.104" *)
  wire _736_;
  (* src = "libresoc.v:197128.19-197128.104" *)
  wire _737_;
  (* src = "libresoc.v:197129.19-197129.115" *)
  wire [2:0] _738_;
  (* src = "libresoc.v:197133.19-197133.104" *)
  wire _739_;
  (* src = "libresoc.v:197136.19-197136.104" *)
  wire _740_;
  (* src = "libresoc.v:197142.19-197142.104" *)
  wire _741_;
  (* src = "libresoc.v:197146.19-197146.104" *)
  wire _742_;
  (* src = "libresoc.v:197147.19-197147.115" *)
  wire [2:0] _743_;
  (* src = "libresoc.v:197150.19-197150.111" *)
  wire _744_;
  (* src = "libresoc.v:197154.19-197154.104" *)
  wire _745_;
  (* src = "libresoc.v:197158.19-197158.104" *)
  wire _746_;
  (* src = "libresoc.v:197173.18-197173.109" *)
  wire _747_;
  (* src = "libresoc.v:197185.18-197185.101" *)
  wire _748_;
  (* src = "libresoc.v:197187.18-197187.109" *)
  wire _749_;
  (* src = "libresoc.v:197190.18-197190.101" *)
  wire _750_;
  (* src = "libresoc.v:197196.18-197196.101" *)
  wire _751_;
  (* src = "libresoc.v:197198.18-197198.109" *)
  wire _752_;
  (* src = "libresoc.v:197201.18-197201.101" *)
  wire _753_;
  (* src = "libresoc.v:197102.19-197102.108" *)
  wire _754_;
  (* src = "libresoc.v:197149.19-197149.108" *)
  wire _755_;
  (* src = "libresoc.v:197159.19-197159.116" *)
  wire _756_;
  (* src = "libresoc.v:197186.18-197186.107" *)
  wire _757_;
  (* src = "libresoc.v:197197.18-197197.107" *)
  wire _758_;
  (* src = "libresoc.v:197164.19-197164.114" *)
  wire [63:0] _759_;
  (* src = "libresoc.v:197165.19-197165.113" *)
  wire [63:0] _760_;
  (* src = "libresoc.v:197181.18-197181.109" *)
  wire [63:0] _761_;
  (* src = "libresoc.v:197080.19-197080.111" *)
  wire [6:0] _762_;
  (* src = "libresoc.v:197083.19-197083.106" *)
  wire [6:0] _763_;
  (* src = "libresoc.v:197156.18-197156.102" *)
  wire _764_;
  (* src = "libresoc.v:197161.19-197161.123" *)
  wire _765_;
  (* src = "libresoc.v:197171.18-197171.102" *)
  wire _766_;
  (* src = "libresoc.v:197079.19-197079.100" *)
  wire _767_;
  (* src = "libresoc.v:197085.19-197085.107" *)
  wire _768_;
  (* src = "libresoc.v:197086.19-197086.109" *)
  wire _769_;
  (* src = "libresoc.v:197088.19-197088.107" *)
  wire _770_;
  (* src = "libresoc.v:197089.19-197089.109" *)
  wire _771_;
  (* src = "libresoc.v:197096.19-197096.107" *)
  wire _772_;
  (* src = "libresoc.v:197097.19-197097.109" *)
  wire _773_;
  (* src = "libresoc.v:197099.19-197099.107" *)
  wire _774_;
  (* src = "libresoc.v:197100.19-197100.109" *)
  wire _775_;
  (* src = "libresoc.v:197104.19-197104.105" *)
  wire _776_;
  (* src = "libresoc.v:197105.19-197105.107" *)
  wire _777_;
  (* src = "libresoc.v:197106.19-197106.109" *)
  wire _778_;
  (* src = "libresoc.v:197111.19-197111.107" *)
  wire _779_;
  (* src = "libresoc.v:197112.19-197112.109" *)
  wire _780_;
  (* src = "libresoc.v:197114.19-197114.107" *)
  wire _781_;
  (* src = "libresoc.v:197115.19-197115.109" *)
  wire _782_;
  (* src = "libresoc.v:197117.19-197117.107" *)
  wire _783_;
  (* src = "libresoc.v:197118.19-197118.109" *)
  wire _784_;
  (* src = "libresoc.v:197120.19-197120.107" *)
  wire _785_;
  (* src = "libresoc.v:197121.19-197121.109" *)
  wire _786_;
  (* src = "libresoc.v:197123.19-197123.107" *)
  wire _787_;
  (* src = "libresoc.v:197124.19-197124.109" *)
  wire _788_;
  (* src = "libresoc.v:197126.19-197126.107" *)
  wire _789_;
  (* src = "libresoc.v:197127.19-197127.109" *)
  wire _790_;
  (* src = "libresoc.v:197131.19-197131.107" *)
  wire _791_;
  (* src = "libresoc.v:197132.19-197132.109" *)
  wire _792_;
  (* src = "libresoc.v:197134.19-197134.107" *)
  wire _793_;
  (* src = "libresoc.v:197135.19-197135.109" *)
  wire _794_;
  (* src = "libresoc.v:197140.19-197140.107" *)
  wire _795_;
  (* src = "libresoc.v:197141.19-197141.109" *)
  wire _796_;
  (* src = "libresoc.v:197143.19-197143.107" *)
  wire _797_;
  (* src = "libresoc.v:197144.19-197144.109" *)
  wire _798_;
  (* src = "libresoc.v:197145.18-197145.99" *)
  wire _799_;
  (* src = "libresoc.v:197151.19-197151.107" *)
  wire _800_;
  (* src = "libresoc.v:197152.19-197152.107" *)
  wire _801_;
  (* src = "libresoc.v:197153.19-197153.109" *)
  wire _802_;
  (* src = "libresoc.v:197155.19-197155.107" *)
  wire _803_;
  (* src = "libresoc.v:197157.19-197157.109" *)
  wire _804_;
  (* src = "libresoc.v:197162.19-197162.107" *)
  wire _805_;
  (* src = "libresoc.v:197163.19-197163.107" *)
  wire _806_;
  (* src = "libresoc.v:197172.18-197172.103" *)
  wire _807_;
  (* src = "libresoc.v:197174.18-197174.107" *)
  wire _808_;
  (* src = "libresoc.v:197175.18-197175.97" *)
  wire _809_;
  (* src = "libresoc.v:197176.18-197176.107" *)
  wire _810_;
  (* src = "libresoc.v:197177.18-197177.107" *)
  wire _811_;
  (* src = "libresoc.v:197178.18-197178.107" *)
  wire _812_;
  (* src = "libresoc.v:197179.18-197179.102" *)
  wire _813_;
  (* src = "libresoc.v:197180.18-197180.107" *)
  wire _814_;
  (* src = "libresoc.v:197182.18-197182.107" *)
  wire _815_;
  (* src = "libresoc.v:197183.18-197183.106" *)
  wire _816_;
  (* src = "libresoc.v:197184.18-197184.108" *)
  wire _817_;
  (* src = "libresoc.v:197188.18-197188.106" *)
  wire _818_;
  (* src = "libresoc.v:197189.18-197189.108" *)
  wire _819_;
  (* src = "libresoc.v:197194.18-197194.106" *)
  wire _820_;
  (* src = "libresoc.v:197195.18-197195.108" *)
  wire _821_;
  (* src = "libresoc.v:197199.18-197199.106" *)
  wire _822_;
  (* src = "libresoc.v:197200.18-197200.108" *)
  wire _823_;
  (* src = "libresoc.v:197077.19-197077.105" *)
  wire _824_;
  (* src = "libresoc.v:197091.19-197091.113" *)
  wire _825_;
  (* src = "libresoc.v:197093.19-197093.106" *)
  wire _826_;
  (* src = "libresoc.v:197108.19-197108.113" *)
  wire _827_;
  (* src = "libresoc.v:197110.19-197110.106" *)
  wire _828_;
  (* src = "libresoc.v:197137.19-197137.113" *)
  wire _829_;
  (* src = "libresoc.v:197139.19-197139.106" *)
  wire _830_;
  (* src = "libresoc.v:197169.18-197169.110" *)
  wire _831_;
  (* src = "libresoc.v:197170.18-197170.100" *)
  wire _832_;
  (* src = "libresoc.v:197191.18-197191.112" *)
  wire _833_;
  (* src = "libresoc.v:197193.18-197193.104" *)
  wire _834_;
  (* src = "libresoc.v:197202.18-197202.112" *)
  wire _835_;
  (* src = "libresoc.v:197160.19-197160.211" *)
  wire [63:0] _836_;
  (* src = "libresoc.v:197164.19-197164.114" *)
  wire [63:0] _837_;
  (* src = "libresoc.v:197165.19-197165.113" *)
  wire [63:0] _838_;
  (* src = "libresoc.v:197181.18-197181.109" *)
  wire [63:0] _839_;
  (* src = "libresoc.v:197130.19-197130.93" *)
  wire _840_;
  (* src = "libresoc.v:197148.19-197148.93" *)
  wire _841_;
  (* src = "libresoc.v:197081.19-197081.42" *)
  wire [63:0] _842_;
  (* src = "libresoc.v:197084.19-197084.42" *)
  wire [63:0] _843_;
  (* src = "libresoc.v:197166.19-197166.116" *)
  wire [64:0] _844_;
  (* src = "libresoc.v:197168.18-197168.101" *)
  wire [2:0] _845_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$100 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *)
  wire [64:0] \$102 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *)
  wire [64:0] \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *)
  wire [31:0] \$107 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *)
  wire [6:0] \$108 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:56" *)
  wire [31:0] \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
  wire [64:0] \$112 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *)
  wire [64:0] \$113 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *)
  wire [6:0] \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$118 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$120 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$122 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$124 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$126 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$128 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
  wire \$130 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$132 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$134 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *)
  wire [7:0] \$136 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *)
  wire [7:0] \$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *)
  wire [7:0] \$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *)
  wire [7:0] \$140 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$142 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$144 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$146 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$148 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$150 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$152 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$154 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$156 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *)
  wire \$158 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$160 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$162 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$164 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
  wire \$166 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$168 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$170 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$172 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$174 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$176 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$178 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$180 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$182 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$184 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$186 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$188 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$190 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$192 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$194 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$196 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$198 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$200 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$202 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$204 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$206 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$208 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
  wire [2:0] \$209 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$212 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$214 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$216 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$218 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$220 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$222 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
  wire \$224 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$226 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$228 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$230 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$232 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$234 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$236 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$238 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$240 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$242 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
  wire [2:0] \$243 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$246 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$248 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
  wire \$250 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$252 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$254 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$256 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$258 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$260 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$262 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:688" *)
  wire \$264 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] \$266 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
  wire \$268 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *)
  wire [2:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
  wire \$270 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
  wire \$272 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] \$274 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] \$276 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
  wire [64:0] \$278 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *)
  wire [64:0] \$279 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *)
  wire [2:0] \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *)
  wire [64:0] \$281 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *)
  wire [64:0] \$282 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
  wire \$30 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *)
  wire \$34 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$38 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
  wire \$42 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$46 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *)
  wire \$50 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] \$54 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$58 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$62 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$66 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$70 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$72 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
  wire \$74 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$76 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$78 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$80 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$82 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
  wire \$84 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$86 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
  wire \$88 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$90 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$92 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
  wire \$94 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
  wire \$96 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *)
  wire \$98 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tck;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tdi;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  output TAP_bus__tdo;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *)
  input TAP_bus__tms;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *)
  output busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
  reg [7:0] core_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
  reg [7:0] \core_asmcode$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:238" *)
  input core_bigendian_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *)
  reg \core_bigendian_i$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102" *)
  reg \core_bigendian_i$10$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] core_cia__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_cia__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  reg [63:0] core_core_core_cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  reg [63:0] \core_core_core_cia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [7:0] core_core_core_cr_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [7:0] \core_core_core_cr_rd$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_core_cr_rd_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_core_cr_rd_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [7:0] core_core_core_cr_wr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [7:0] \core_core_core_cr_wr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$4$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$5$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$6$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$7$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$8$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$9$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  reg \core_core_core_exc_$signal$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  reg [13:0] core_core_core_fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  reg [13:0] \core_core_core_fn_unit$next ;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  reg [1:0] core_core_core_input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  reg [1:0] \core_core_core_input_carry$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  reg [31:0] core_core_core_insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  reg [31:0] \core_core_core_insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  reg [6:0] core_core_core_insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  reg [6:0] \core_core_core_insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  reg core_core_core_is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  reg \core_core_core_is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  reg [63:0] core_core_core_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  reg [63:0] \core_core_core_msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_core_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_core_oe$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_core_oe_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_core_oe_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_core_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_core_rc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_core_rc_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_core_rc_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  reg [12:0] core_core_core_trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  reg [12:0] \core_core_core_trapaddr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  reg [7:0] core_core_core_traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  reg [7:0] \core_core_core_traptype$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_cr_in1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_cr_in1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_cr_in1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_cr_in1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_cr_in2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_cr_in2$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_cr_in2$1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_cr_in2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_cr_in2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_cr_in2_ok$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_cr_in2_ok$2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_cr_in2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_cr_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_cr_wr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_cr_wr_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  reg [6:0] core_core_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  reg [6:0] \core_core_dststep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_ea$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] core_core_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] \core_core_fast1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] core_core_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] \core_core_fast2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_fast2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] core_core_fasto1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] \core_core_fasto1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] core_core_fasto2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [2:0] \core_core_fasto2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *)
  reg core_core_lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *)
  reg \core_core_lk$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  reg [6:0] core_core_maxvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  reg [6:0] \core_core_maxvl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  reg [63:0] core_core_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  reg [63:0] \core_core_pc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_reg1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_reg1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_reg1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_reg1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_reg2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_reg2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_reg2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_reg2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_reg3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_reg3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_reg3_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_reg3_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] core_core_rego;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [6:0] \core_core_rego$next ;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [9:0] core_core_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [9:0] \core_core_spr1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_core_spr1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_core_spr1_ok$next ;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [9:0] core_core_spro;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg [9:0] \core_core_spro$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  reg [6:0] core_core_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  reg [6:0] \core_core_srcstep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  reg [1:0] core_core_subvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  reg [1:0] \core_core_subvl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  reg [1:0] core_core_svstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  reg [1:0] \core_core_svstep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *)
  wire core_core_terminate_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  reg [6:0] core_core_vl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  reg [6:0] \core_core_vl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  reg [2:0] core_core_xer_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  reg [2:0] \core_core_xer_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107" *)
  wire core_corebusy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  wire core_coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_cr_out_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_cr_out_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire core_cu_ad__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire core_cu_ad__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire core_cu_st__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  wire core_cu_st__rel_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] core_data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] \core_data_i$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *)
  reg [63:0] core_dec;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *)
  reg [63:0] \core_dec$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [4:0] core_dmi__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] core_dmi__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg core_dmi__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_ea_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_ea_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *)
  reg core_eint;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *)
  reg \core_eint$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_fasto1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_fasto1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_fasto2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_fasto2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [31:0] core_full_rd2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [7:0] core_full_rd2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [5:0] core_full_rd__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_full_rd__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_issue__addr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] \core_issue__addr$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [63:0] core_issue__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] core_issue__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg core_issue__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg core_issue__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106" *)
  reg core_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105" *)
  reg core_ivalid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  reg [63:0] core_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  reg [63:0] \core_msr$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] core_msr__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_msr__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *)
  reg [31:0] core_raw_insn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101" *)
  reg [31:0] \core_raw_insn_i$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_rego_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_rego_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg core_spro_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  reg \core_spro_ok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] core_state_nia_wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:110" *)
  reg core_stopped_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [63:0] core_sv__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_sv__ren;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *)
  reg core_sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:97" *)
  reg \core_sv_a_nz$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:96" *)
  wire core_wb_dcache_en;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] core_wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  reg [2:0] \core_wen$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
  reg core_xer_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
  reg \core_xer_out$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg cu_st__rel_o_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \cu_st__rel_o_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire cu_st__rel_o_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  reg [6:0] cur_cur_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  reg [6:0] \cur_cur_dststep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  reg [6:0] cur_cur_maxvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  reg [6:0] \cur_cur_maxvl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  reg [6:0] cur_cur_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  reg [6:0] \cur_cur_srcstep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  reg [1:0] cur_cur_subvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  reg [1:0] \cur_cur_subvl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  reg [1:0] cur_cur_svstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  reg [1:0] \cur_cur_svstep$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  reg [6:0] cur_cur_vl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  reg [6:0] \cur_cur_vl$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1022" *)
  reg d_cr_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1022" *)
  reg \d_cr_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1012" *)
  reg d_reg_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1012" *)
  reg \d_reg_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
  reg d_xer_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *)
  reg \d_xer_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  wire [6:0] dbg_core_dbg_core_dbg_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  wire [6:0] dbg_core_dbg_core_dbg_maxvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  wire [6:0] dbg_core_dbg_core_dbg_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  wire [1:0] dbg_core_dbg_core_dbg_subvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  wire [1:0] dbg_core_dbg_core_dbg_svstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  wire [6:0] dbg_core_dbg_core_dbg_vl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  wire [63:0] dbg_core_dbg_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  wire [63:0] dbg_core_dbg_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:99" *)
  wire dbg_core_rst_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98" *)
  wire dbg_core_stop_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:104" *)
  reg dbg_core_stopped_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  reg dbg_d_cr_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  reg [63:0] dbg_d_cr_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  wire dbg_d_cr_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  reg dbg_d_gpr_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79" *)
  wire [6:0] dbg_d_gpr_addr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  reg [63:0] dbg_d_gpr_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  wire dbg_d_gpr_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:78" *)
  reg dbg_d_xer_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80" *)
  reg [63:0] dbg_d_xer_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:77" *)
  wire dbg_d_xer_req;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:63" *)
  wire dbg_dmi_ack_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *)
  reg [3:0] dbg_dmi_addr_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" *)
  reg [3:0] \dbg_dmi_addr_i$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *)
  reg [63:0] dbg_dmi_din;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" *)
  reg [63:0] \dbg_dmi_din$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" *)
  wire [63:0] dbg_dmi_dout;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *)
  reg dbg_dmi_req_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" *)
  reg \dbg_dmi_req_i$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *)
  reg dbg_dmi_we_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" *)
  reg \dbg_dmi_we_i$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:103" *)
  wire dbg_terminate_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [44:0] dbus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input [63:0] dbus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [63:0] dbus__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  input dbus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output [7:0] dbus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *)
  output dbus__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:101" *)
  wire [7:0] dec2_asmcode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" *)
  wire dec2_bigendian;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44" *)
  wire [63:0] dec2_cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_cr_in1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_cr_in1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_cr_in2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] \dec2_cr_in2$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_cr_in2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire \dec2_cr_in2_ok$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_cr_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_cr_out_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] dec2_cr_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_cr_rd_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [7:0] dec2_cr_wr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_cr_wr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *)
  reg [63:0] dec2_cur_dec;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:19" *)
  reg [63:0] \dec2_cur_dec$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *)
  reg dec2_cur_eint;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:18" *)
  reg \dec2_cur_eint$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  reg [63:0] dec2_cur_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:17" *)
  reg [63:0] \dec2_cur_msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  reg [63:0] dec2_cur_pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:16" *)
  reg [63:0] \dec2_cur_pc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_ea;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_ea_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" *)
  wire \dec2_exc_$signal$22 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec2_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec2_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec2_fasto1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_fasto1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [2:0] dec2_fasto2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_fasto2_ok;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49" *)
  wire [13:0] dec2_fn_unit;
  (* enum_base_type = "CryIn" *)
  (* enum_value_00 = "ZERO" *)
  (* enum_value_01 = "ONE" *)
  (* enum_value_10 = "CA" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" *)
  wire [1:0] dec2_input_carry;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" *)
  wire [31:0] dec2_insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" *)
  wire [6:0] dec2_insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59" *)
  wire dec2_is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50" *)
  wire dec2_lk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:43" *)
  wire [63:0] dec2_msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_oe_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  reg [31:0] dec2_raw_opcode_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" *)
  reg [31:0] \dec2_raw_opcode_in$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_rc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_rc_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_reg1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_reg1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_reg2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_reg2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_reg3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_reg3_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [6:0] dec2_rego;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_rego_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] dec2_spr1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_spr1_ok;
  (* enum_base_type = "SPR" *)
  (* enum_value_0000000001 = "XER" *)
  (* enum_value_0000000011 = "DSCR" *)
  (* enum_value_0000001000 = "LR" *)
  (* enum_value_0000001001 = "CTR" *)
  (* enum_value_0000001101 = "AMR" *)
  (* enum_value_0000010001 = "DSCR_priv" *)
  (* enum_value_0000010010 = "DSISR" *)
  (* enum_value_0000010011 = "DAR" *)
  (* enum_value_0000010110 = "DEC" *)
  (* enum_value_0000011010 = "SRR0" *)
  (* enum_value_0000011011 = "SRR1" *)
  (* enum_value_0000011100 = "CFAR" *)
  (* enum_value_0000011101 = "AMR_priv" *)
  (* enum_value_0000110000 = "PIDR" *)
  (* enum_value_0000111101 = "IAMR" *)
  (* enum_value_0010000000 = "TFHAR" *)
  (* enum_value_0010000001 = "TFIAR" *)
  (* enum_value_0010000010 = "TEXASR" *)
  (* enum_value_0010000011 = "TEXASRU" *)
  (* enum_value_0010001000 = "CTRL" *)
  (* enum_value_0010010000 = "TIDR" *)
  (* enum_value_0010011000 = "CTRL_priv" *)
  (* enum_value_0010011001 = "FSCR" *)
  (* enum_value_0010011101 = "UAMOR" *)
  (* enum_value_0010011110 = "GSR" *)
  (* enum_value_0010011111 = "PSPB" *)
  (* enum_value_0010110000 = "DPDES" *)
  (* enum_value_0010110100 = "DAWR0" *)
  (* enum_value_0010111010 = "RPR" *)
  (* enum_value_0010111011 = "CIABR" *)
  (* enum_value_0010111100 = "DAWRX0" *)
  (* enum_value_0010111110 = "HFSCR" *)
  (* enum_value_0100000000 = "VRSAVE" *)
  (* enum_value_0100000011 = "SPRG3" *)
  (* enum_value_0100001100 = "TB" *)
  (* enum_value_0100001101 = "TBU" *)
  (* enum_value_0100010000 = "SPRG0_priv" *)
  (* enum_value_0100010001 = "SPRG1_priv" *)
  (* enum_value_0100010010 = "SPRG2_priv" *)
  (* enum_value_0100010011 = "SPRG3_priv" *)
  (* enum_value_0100011011 = "CIR" *)
  (* enum_value_0100011100 = "TBL" *)
  (* enum_value_0100011101 = "TBU_hypv" *)
  (* enum_value_0100011110 = "TBU40" *)
  (* enum_value_0100011111 = "PVR" *)
  (* enum_value_0100110000 = "HSPRG0" *)
  (* enum_value_0100110001 = "HSPRG1" *)
  (* enum_value_0100110010 = "HDSISR" *)
  (* enum_value_0100110011 = "HDAR" *)
  (* enum_value_0100110100 = "SPURR" *)
  (* enum_value_0100110101 = "PURR" *)
  (* enum_value_0100110110 = "HDEC" *)
  (* enum_value_0100111001 = "HRMOR" *)
  (* enum_value_0100111010 = "HSRR0" *)
  (* enum_value_0100111011 = "HSRR1" *)
  (* enum_value_0100111110 = "LPCR" *)
  (* enum_value_0100111111 = "LPIDR" *)
  (* enum_value_0101010000 = "HMER" *)
  (* enum_value_0101010001 = "HMEER" *)
  (* enum_value_0101010010 = "PCR" *)
  (* enum_value_0101010011 = "HEIR" *)
  (* enum_value_0101011101 = "AMOR" *)
  (* enum_value_0110111110 = "TIR" *)
  (* enum_value_0111010000 = "PTCR" *)
  (* enum_value_1011000000 = "SVSTATE" *)
  (* enum_value_1011010000 = "PRTBL" *)
  (* enum_value_1011010001 = "SVSRR0" *)
  (* enum_value_1100000000 = "SIER" *)
  (* enum_value_1100000001 = "MMCR2" *)
  (* enum_value_1100000010 = "MMCRA" *)
  (* enum_value_1100000011 = "PMC1" *)
  (* enum_value_1100000100 = "PMC2" *)
  (* enum_value_1100000101 = "PMC3" *)
  (* enum_value_1100000110 = "PMC4" *)
  (* enum_value_1100000111 = "PMC5" *)
  (* enum_value_1100001000 = "PMC6" *)
  (* enum_value_1100001011 = "MMCR0" *)
  (* enum_value_1100001100 = "SIAR" *)
  (* enum_value_1100001101 = "SDAR" *)
  (* enum_value_1100001110 = "MMCR1" *)
  (* enum_value_1100010000 = "SIER_priv" *)
  (* enum_value_1100010001 = "MMCR2_priv" *)
  (* enum_value_1100010010 = "MMCRA_priv" *)
  (* enum_value_1100010011 = "PMC1_priv" *)
  (* enum_value_1100010100 = "PMC2_priv" *)
  (* enum_value_1100010101 = "PMC3_priv" *)
  (* enum_value_1100010110 = "PMC4_priv" *)
  (* enum_value_1100010111 = "PMC5_priv" *)
  (* enum_value_1100011000 = "PMC6_priv" *)
  (* enum_value_1100011011 = "MMCR0_priv" *)
  (* enum_value_1100011100 = "SIAR_priv" *)
  (* enum_value_1100011101 = "SDAR_priv" *)
  (* enum_value_1100011110 = "MMCR1_priv" *)
  (* enum_value_1100100000 = "BESCRS" *)
  (* enum_value_1100100001 = "BESCRSU" *)
  (* enum_value_1100100010 = "BESCRR" *)
  (* enum_value_1100100011 = "BESCRRU" *)
  (* enum_value_1100100100 = "EBBHR" *)
  (* enum_value_1100100101 = "EBBRR" *)
  (* enum_value_1100100110 = "BESCR" *)
  (* enum_value_1100101000 = "reserved808" *)
  (* enum_value_1100101001 = "reserved809" *)
  (* enum_value_1100101010 = "reserved810" *)
  (* enum_value_1100101011 = "reserved811" *)
  (* enum_value_1100101111 = "TAR" *)
  (* enum_value_1100110000 = "ASDR" *)
  (* enum_value_1100110111 = "PSSCR" *)
  (* enum_value_1101010000 = "IC" *)
  (* enum_value_1101010001 = "VTB" *)
  (* enum_value_1101010111 = "PSSCR_hypv" *)
  (* enum_value_1110000000 = "PPR" *)
  (* enum_value_1110000010 = "PPR32" *)
  (* enum_value_1111111111 = "PIR" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [9:0] dec2_spro;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire dec2_spro_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:714" *)
  wire dec2_sv_a_nz;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" *)
  wire [12:0] dec2_trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54" *)
  wire [7:0] dec2_traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:111" *)
  wire [2:0] dec2_xer_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:112" *)
  wire dec2_xer_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" *)
  reg [1:0] delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:848" *)
  reg [1:0] \delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output eint_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input eint_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
  reg exec_fsm_state;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
  reg \exec_fsm_state$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" *)
  reg exec_insn_ready_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:945" *)
  reg exec_insn_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:950" *)
  reg exec_pc_ready_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" *)
  reg exec_pc_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
  reg [1:0] fetch_fsm_state;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
  reg [1:0] \fetch_fsm_state$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:934" *)
  reg fetch_insn_ready_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:933" *)
  reg fetch_insn_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *)
  reg fetch_pc_ready_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:929" *)
  reg fetch_pc_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
  reg [1:0] fsm_state;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
  reg [1:0] \fsm_state$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_e9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_e9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input gpio_s7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output gpio_s7__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [44:0] ibus__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input [63:0] ibus__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  input ibus__err;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output [7:0] ibus__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" *)
  output ibus__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output icp_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [27:0] icp_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output [31:0] icp_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [31:0] icp_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [3:0] icp_wb__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output ics_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [27:0] ics_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output [31:0] ics_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [31:0] ics_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" *)
  reg [47:0] imem_a_pc_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *)
  reg imem_a_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" *)
  wire imem_f_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" *)
  wire [63:0] imem_f_instr_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" *)
  reg imem_f_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" *)
  wire imem_wb_icache_en;
  (* src = "libresoc.v:194992.7-194992.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:268" *)
  reg insn_done;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
  input [15:0] int_level_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:686" *)
  reg is_last;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:923" *)
  wire is_svp64_mode;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
  reg [2:0] issue_fsm_state;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
  reg [2:0] \issue_fsm_state$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg jtag_dmi0__ack_o;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg \jtag_dmi0__ack_o$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  wire [3:0] jtag_dmi0__addr_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  wire [63:0] jtag_dmi0__din;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg [63:0] jtag_dmi0__dout;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  reg [63:0] \jtag_dmi0__dout$next ;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  wire jtag_dmi0__req_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *)
  wire jtag_dmi0__we_i;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input jtag_wb__ack;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [29:0] jtag_wb__adr;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  input [31:0] jtag_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [31:0] jtag_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output [3:0] jtag_wb__sel;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__stb;
  (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" *)
  output jtag_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_clk__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_clk__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_miso__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_miso__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mspi0_mosi__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mspi0_mosi__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *)
  reg msr_read;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:290" *)
  reg \msr_read$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_scl__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_scl__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input mtwi_sda__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output mtwi_sda__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1065" *)
  reg [63:0] new_dec;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" *)
  reg [6:0] new_svstate_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:31" *)
  reg [6:0] new_svstate_maxvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:29" *)
  reg [6:0] new_svstate_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:27" *)
  reg [1:0] new_svstate_subvl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:26" *)
  reg [1:0] new_svstate_svstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" *)
  reg [6:0] new_svstate_vl;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1082" *)
  reg [63:0] new_tb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:535" *)
  wire [6:0] next_dststep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:534" *)
  wire [6:0] next_srcstep;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" *)
  reg [63:0] nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:910" *)
  reg [63:0] \nia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *)
  reg [63:0] pc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889" *)
  reg pc_changed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:889" *)
  reg \pc_changed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input [63:0] pc_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  input pc_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:235" *)
  output [63:0] pc_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
  reg pc_ok_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
  reg \pc_ok_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:842" *)
  wire por_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *)
  wire pred_insn_ready_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *)
  reg pred_insn_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *)
  reg pred_mask_ready_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:941" *)
  wire pred_mask_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_a_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_a_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ba_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ba_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cas_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cas_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cke__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cke__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_clock__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_clock__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_cs_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_cs_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dm_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dm_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_0__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_0__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_10__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_10__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_11__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_11__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_12__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_12__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_13__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_13__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_14__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_14__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_15__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_15__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_1__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_1__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_2__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_2__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_3__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_3__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_4__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_4__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_5__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_5__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_6__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_6__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_7__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_7__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_8__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_8__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__core__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__core__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_dq_9__pad__i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_dq_9__pad__oe;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_ras_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_ras_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  input sdr_we_n__core__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *)
  output sdr_we_n__pad__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:890" *)
  reg sv_changed;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:890" *)
  reg \sv_changed$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" *)
  reg [63:0] svstate;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [31:0] svstate_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire svstate_i_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
  reg svstate_ok_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *)
  reg \svstate_ok_delay$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847" *)
  wire ti_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" *)
  reg update_svstate;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
  wire xics_icp_core_irq_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  wire [7:0] xics_icp_ics_i_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  wire [3:0] xics_icp_ics_i_src;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  wire [7:0] xics_ics_icp_o_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  wire [3:0] xics_ics_icp_o_src;
  assign _721_ = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:353" *) 3'h4;
  assign _722_ = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" *) 3'h4;
  assign _723_ = cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:536" *) 1'h1;
  assign _724_ = cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:537" *) 1'h1;
  assign _725_ = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1083" *) 1'h1;
  assign _726_ = \$118  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$120 ;
  assign _727_ = \$124  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$126 ;
  assign _728_ = \$142  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$144 ;
  assign _729_ = \$148  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$150 ;
  assign _730_ = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$154 ;
  assign _731_ = \$160  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$162 ;
  assign _732_ = \$172  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$174 ;
  assign _733_ = \$178  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$180 ;
  assign _734_ = \$184  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$186 ;
  assign _735_ = \$190  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$192 ;
  assign _736_ = \$196  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$198 ;
  assign _737_ = \$202  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$204 ;
  assign _738_ = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *) 1'h1;
  assign _739_ = \$212  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$214 ;
  assign _740_ = \$218  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$220 ;
  assign _741_ = \$230  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$232 ;
  assign _742_ = \$236  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$238 ;
  assign _743_ = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *) 3'h4;
  assign _744_ = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$246 ;
  assign _745_ = \$252  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$254 ;
  assign _746_ = \$258  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$260 ;
  assign _747_ = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$36 ;
  assign _748_ = \$58  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$60 ;
  assign _749_ = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$64 ;
  assign _750_ = \$68  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$70 ;
  assign _751_ = \$80  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) \$82 ;
  assign _752_ = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) \$86 ;
  assign _753_ = \$90  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) \$92 ;
  assign _754_ = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0;
  assign _755_ = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0;
  assign _756_ = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:688" *) cur_cur_vl;
  assign _757_ = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0;
  assign _758_ = cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *) 1'h0;
  assign _759_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o;
  assign _760_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o;
  assign _761_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) svstate_i;
  assign _762_ = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) 6'h20;
  assign _763_ = \$112 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" *) 6'h20;
  assign _764_ = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *) 1'h0;
  assign _765_ = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) 7'h01;
  assign _766_ = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) \$32 ;
  assign _767_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read;
  assign _768_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _769_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _770_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _771_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _772_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _773_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _774_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _775_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _776_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *) is_svp64_mode;
  assign _777_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _778_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _779_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _780_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _781_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _782_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _783_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _784_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _785_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _786_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _787_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _788_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _789_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _790_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _791_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _792_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _793_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _794_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _795_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _796_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _797_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _798_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _799_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *) msr_read;
  assign _800_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o;
  assign _801_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _802_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _803_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _804_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _805_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o;
  assign _806_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) core_corebusy_o;
  assign _807_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly;
  assign _808_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _809_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) pc_i_ok;
  assign _810_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _811_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _812_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _813_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) svstate_i_ok;
  assign _814_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _815_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) core_coresync_rst;
  assign _816_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _817_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _818_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _819_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _820_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) dbg_core_stop_o;
  assign _821_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *) core_coresync_rst;
  assign _822_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) dbg_core_stop_o;
  assign _823_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *) core_coresync_rst;
  assign _824_ = \$98  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last;
  assign _825_ = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed;
  assign _826_ = \$132  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last;
  assign _827_ = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed;
  assign _828_ = \$168  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last;
  assign _829_ = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed;
  assign _830_ = \$226  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last;
  assign _831_ = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) dbg_core_rst_o;
  assign _832_ = \$30  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) rst;
  assign _833_ = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed;
  assign _834_ = \$76  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:699" *) is_last;
  assign _835_ = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *) sv_changed;
  assign _836_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) { 32'h00000000, new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
  assign _837_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) _759_;
  assign _838_ = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) _760_;
  assign _839_ = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *) _761_;
  assign _840_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$209 ;
  assign _841_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$243 ;
  assign _842_ = imem_f_instr_o >> (* src = "libresoc.v:197081.19-197081.42" *) \$108 ;
  assign _843_ = imem_f_instr_o >> (* src = "libresoc.v:197084.19-197084.42" *) \$115 ;
  assign _844_ = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1067" *) 1'h1;
  assign _845_ = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:850" *) 1'h1;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197412.8-197510.4" *)
  core core (
    .bigendian_i(\core_bigendian_i$10 ),
    .cia__data_o(core_cia__data_o),
    .cia__ren(core_cia__ren),
    .core_core_cia(core_core_core_cia),
    .core_core_cr_rd(core_core_core_cr_rd),
    .core_core_cr_rd_ok(core_core_core_cr_rd_ok),
    .core_core_cr_wr(core_core_core_cr_wr),
    .\core_core_exc_$signal (\core_core_core_exc_$signal ),
    .\core_core_exc_$signal$3 (\core_core_core_exc_$signal$3 ),
    .\core_core_exc_$signal$4 (\core_core_core_exc_$signal$4 ),
    .\core_core_exc_$signal$5 (\core_core_core_exc_$signal$5 ),
    .\core_core_exc_$signal$6 (\core_core_core_exc_$signal$6 ),
    .\core_core_exc_$signal$7 (\core_core_core_exc_$signal$7 ),
    .\core_core_exc_$signal$8 (\core_core_core_exc_$signal$8 ),
    .\core_core_exc_$signal$9 (\core_core_core_exc_$signal$9 ),
    .core_core_fn_unit(core_core_core_fn_unit),
    .core_core_input_carry(core_core_core_input_carry),
    .core_core_insn(core_core_core_insn),
    .core_core_insn_type(core_core_core_insn_type),
    .core_core_is_32bit(core_core_core_is_32bit),
    .core_core_msr(core_core_core_msr),
    .core_core_oe(core_core_core_oe),
    .core_core_oe_ok(core_core_core_oe_ok),
    .core_core_rc(core_core_core_rc),
    .core_core_rc_ok(core_core_core_rc_ok),
    .core_core_trapaddr(core_core_core_trapaddr),
    .core_core_traptype(core_core_core_traptype),
    .core_cr_in1(core_core_cr_in1),
    .core_cr_in1_ok(core_core_cr_in1_ok),
    .core_cr_in2(core_core_cr_in2),
    .\core_cr_in2$1 (\core_core_cr_in2$1 ),
    .core_cr_in2_ok(core_core_cr_in2_ok),
    .\core_cr_in2_ok$2 (\core_core_cr_in2_ok$2 ),
    .core_cr_out(core_core_cr_out),
    .core_ea(core_core_ea),
    .core_fast1(core_core_fast1),
    .core_fast1_ok(core_core_fast1_ok),
    .core_fast2(core_core_fast2),
    .core_fast2_ok(core_core_fast2_ok),
    .core_fasto1(core_core_fasto1),
    .core_fasto2(core_core_fasto2),
    .core_pc(core_core_pc),
    .core_reg1(core_core_reg1),
    .core_reg1_ok(core_core_reg1_ok),
    .core_reg2(core_core_reg2),
    .core_reg2_ok(core_core_reg2_ok),
    .core_reg3(core_core_reg3),
    .core_reg3_ok(core_core_reg3_ok),
    .core_rego(core_core_rego),
    .core_spr1(core_core_spr1),
    .core_spr1_ok(core_core_spr1_ok),
    .core_spro(core_core_spro),
    .core_terminate_o(core_core_terminate_o),
    .core_xer_in(core_core_xer_in),
    .corebusy_o(core_corebusy_o),
    .coresync_clk(coresync_clk),
    .coresync_rst(core_coresync_rst),
    .cu_ad__go_i(core_cu_ad__go_i),
    .cu_ad__rel_o(core_cu_ad__rel_o),
    .cu_st__go_i(core_cu_st__go_i),
    .cu_st__rel_o(core_cu_st__rel_o),
    .data_i(core_data_i),
    .\data_i$11 (\core_data_i$12 ),
    .dbus__ack(dbus__ack),
    .dbus__adr(dbus__adr),
    .dbus__cyc(dbus__cyc),
    .dbus__dat_r(dbus__dat_r),
    .dbus__dat_w(dbus__dat_w),
    .dbus__err(dbus__err),
    .dbus__sel(dbus__sel),
    .dbus__stb(dbus__stb),
    .dbus__we(dbus__we),
    .dmi__addr(core_dmi__addr),
    .dmi__data_o(core_dmi__data_o),
    .dmi__ren(core_dmi__ren),
    .full_rd2__data_o(core_full_rd2__data_o),
    .full_rd2__ren(core_full_rd2__ren),
    .full_rd__data_o(core_full_rd__data_o),
    .full_rd__ren(core_full_rd__ren),
    .issue__addr(core_issue__addr),
    .\issue__addr$12 (\core_issue__addr$13 ),
    .issue__data_i(core_issue__data_i),
    .issue__data_o(core_issue__data_o),
    .issue__ren(core_issue__ren),
    .issue__wen(core_issue__wen),
    .issue_i(core_issue_i),
    .ivalid_i(core_ivalid_i),
    .msr__data_o(core_msr__data_o),
    .msr__ren(core_msr__ren),
    .raw_insn_i(core_raw_insn_i),
    .state_nia_wen(core_state_nia_wen),
    .sv__data_o(core_sv__data_o),
    .sv__ren(core_sv__ren),
    .sv_a_nz(core_sv_a_nz),
    .wb_dcache_en(core_wb_dcache_en),
    .wen(core_wen),
    .\wen$10 (\core_wen$11 )
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197511.7-197542.4" *)
  dbg dbg (
    .clk(clk),
    .core_dbg_core_dbg_dststep(dbg_core_dbg_core_dbg_dststep),
    .core_dbg_core_dbg_maxvl(dbg_core_dbg_core_dbg_maxvl),
    .core_dbg_core_dbg_srcstep(dbg_core_dbg_core_dbg_srcstep),
    .core_dbg_core_dbg_subvl(dbg_core_dbg_core_dbg_subvl),
    .core_dbg_core_dbg_svstep(dbg_core_dbg_core_dbg_svstep),
    .core_dbg_core_dbg_vl(dbg_core_dbg_core_dbg_vl),
    .core_dbg_msr(dbg_core_dbg_msr),
    .core_dbg_pc(dbg_core_dbg_pc),
    .core_rst_o(dbg_core_rst_o),
    .core_stop_o(dbg_core_stop_o),
    .core_stopped_i(dbg_core_stopped_i),
    .d_cr_ack(dbg_d_cr_ack),
    .d_cr_data(dbg_d_cr_data),
    .d_cr_req(dbg_d_cr_req),
    .d_gpr_ack(dbg_d_gpr_ack),
    .d_gpr_addr(dbg_d_gpr_addr),
    .d_gpr_data(dbg_d_gpr_data),
    .d_gpr_req(dbg_d_gpr_req),
    .d_xer_ack(dbg_d_xer_ack),
    .d_xer_data(dbg_d_xer_data),
    .d_xer_req(dbg_d_xer_req),
    .dmi_ack_o(dbg_dmi_ack_o),
    .dmi_addr_i(dbg_dmi_addr_i),
    .dmi_din(dbg_dmi_din),
    .dmi_dout(dbg_dmi_dout),
    .dmi_req_i(dbg_dmi_req_i),
    .dmi_we_i(dbg_dmi_we_i),
    .rst(rst),
    .terminate_i(dbg_terminate_i)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197543.8-197610.4" *)
  dec2 dec2 (
    .asmcode(dec2_asmcode),
    .bigendian(dec2_bigendian),
    .cia(dec2_cia),
    .cr_in1(dec2_cr_in1),
    .cr_in1_ok(dec2_cr_in1_ok),
    .cr_in2(dec2_cr_in2),
    .\cr_in2$1 (\dec2_cr_in2$14 ),
    .cr_in2_ok(dec2_cr_in2_ok),
    .\cr_in2_ok$2 (\dec2_cr_in2_ok$15 ),
    .cr_out(dec2_cr_out),
    .cr_out_ok(dec2_cr_out_ok),
    .cr_rd(dec2_cr_rd),
    .cr_rd_ok(dec2_cr_rd_ok),
    .cr_wr(dec2_cr_wr),
    .cr_wr_ok(dec2_cr_wr_ok),
    .cur_dec(dec2_cur_dec),
    .cur_eint(dec2_cur_eint),
    .cur_msr(dec2_cur_msr),
    .cur_pc(dec2_cur_pc),
    .ea(dec2_ea),
    .ea_ok(dec2_ea_ok),
    .\exc_$signal (\dec2_exc_$signal ),
    .\exc_$signal$3 (\dec2_exc_$signal$16 ),
    .\exc_$signal$4 (\dec2_exc_$signal$17 ),
    .\exc_$signal$5 (\dec2_exc_$signal$18 ),
    .\exc_$signal$6 (\dec2_exc_$signal$19 ),
    .\exc_$signal$7 (\dec2_exc_$signal$20 ),
    .\exc_$signal$8 (\dec2_exc_$signal$21 ),
    .\exc_$signal$9 (\dec2_exc_$signal$22 ),
    .fast1(dec2_fast1),
    .fast1_ok(dec2_fast1_ok),
    .fast2(dec2_fast2),
    .fast2_ok(dec2_fast2_ok),
    .fasto1(dec2_fasto1),
    .fasto1_ok(dec2_fasto1_ok),
    .fasto2(dec2_fasto2),
    .fasto2_ok(dec2_fasto2_ok),
    .fn_unit(dec2_fn_unit),
    .input_carry(dec2_input_carry),
    .insn(dec2_insn),
    .insn_type(dec2_insn_type),
    .is_32bit(dec2_is_32bit),
    .lk(dec2_lk),
    .msr(dec2_msr),
    .oe(dec2_oe),
    .oe_ok(dec2_oe_ok),
    .raw_opcode_in(dec2_raw_opcode_in),
    .rc(dec2_rc),
    .rc_ok(dec2_rc_ok),
    .reg1(dec2_reg1),
    .reg1_ok(dec2_reg1_ok),
    .reg2(dec2_reg2),
    .reg2_ok(dec2_reg2_ok),
    .reg3(dec2_reg3),
    .reg3_ok(dec2_reg3_ok),
    .rego(dec2_rego),
    .rego_ok(dec2_rego_ok),
    .spr1(dec2_spr1),
    .spr1_ok(dec2_spr1_ok),
    .spro(dec2_spro),
    .spro_ok(dec2_spro_ok),
    .sv_a_nz(dec2_sv_a_nz),
    .trapaddr(dec2_trapaddr),
    .traptype(dec2_traptype),
    .xer_in(dec2_xer_in),
    .xer_out(dec2_xer_out)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197611.8-197627.4" *)
  imem imem (
    .a_pc_i(imem_a_pc_i),
    .a_valid_i(imem_a_valid_i),
    .clk(clk),
    .f_busy_o(imem_f_busy_o),
    .f_instr_o(imem_f_instr_o),
    .f_valid_i(imem_f_valid_i),
    .ibus__ack(ibus__ack),
    .ibus__adr(ibus__adr),
    .ibus__cyc(ibus__cyc),
    .ibus__dat_r(ibus__dat_r),
    .ibus__err(ibus__err),
    .ibus__sel(ibus__sel),
    .ibus__stb(ibus__stb),
    .rst(rst),
    .wb_icache_en(imem_wb_icache_en)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197628.8-197911.4" *)
  jtag jtag (
    .TAP_bus__tck(TAP_bus__tck),
    .TAP_bus__tdi(TAP_bus__tdi),
    .TAP_bus__tdo(TAP_bus__tdo),
    .TAP_bus__tms(TAP_bus__tms),
    .clk(clk),
    .dmi0__ack_o(jtag_dmi0__ack_o),
    .dmi0__addr_i(jtag_dmi0__addr_i),
    .dmi0__din(jtag_dmi0__din),
    .dmi0__dout(jtag_dmi0__dout),
    .dmi0__req_i(jtag_dmi0__req_i),
    .dmi0__we_i(jtag_dmi0__we_i),
    .eint_0__core__i(eint_0__core__i),
    .eint_0__pad__i(eint_0__pad__i),
    .eint_1__core__i(eint_1__core__i),
    .eint_1__pad__i(eint_1__pad__i),
    .eint_2__core__i(eint_2__core__i),
    .eint_2__pad__i(eint_2__pad__i),
    .gpio_e10__core__i(gpio_e10__core__i),
    .gpio_e10__core__o(gpio_e10__core__o),
    .gpio_e10__core__oe(gpio_e10__core__oe),
    .gpio_e10__pad__i(gpio_e10__pad__i),
    .gpio_e10__pad__o(gpio_e10__pad__o),
    .gpio_e10__pad__oe(gpio_e10__pad__oe),
    .gpio_e11__core__i(gpio_e11__core__i),
    .gpio_e11__core__o(gpio_e11__core__o),
    .gpio_e11__core__oe(gpio_e11__core__oe),
    .gpio_e11__pad__i(gpio_e11__pad__i),
    .gpio_e11__pad__o(gpio_e11__pad__o),
    .gpio_e11__pad__oe(gpio_e11__pad__oe),
    .gpio_e12__core__i(gpio_e12__core__i),
    .gpio_e12__core__o(gpio_e12__core__o),
    .gpio_e12__core__oe(gpio_e12__core__oe),
    .gpio_e12__pad__i(gpio_e12__pad__i),
    .gpio_e12__pad__o(gpio_e12__pad__o),
    .gpio_e12__pad__oe(gpio_e12__pad__oe),
    .gpio_e13__core__i(gpio_e13__core__i),
    .gpio_e13__core__o(gpio_e13__core__o),
    .gpio_e13__core__oe(gpio_e13__core__oe),
    .gpio_e13__pad__i(gpio_e13__pad__i),
    .gpio_e13__pad__o(gpio_e13__pad__o),
    .gpio_e13__pad__oe(gpio_e13__pad__oe),
    .gpio_e14__core__i(gpio_e14__core__i),
    .gpio_e14__core__o(gpio_e14__core__o),
    .gpio_e14__core__oe(gpio_e14__core__oe),
    .gpio_e14__pad__i(gpio_e14__pad__i),
    .gpio_e14__pad__o(gpio_e14__pad__o),
    .gpio_e14__pad__oe(gpio_e14__pad__oe),
    .gpio_e15__core__i(gpio_e15__core__i),
    .gpio_e15__core__o(gpio_e15__core__o),
    .gpio_e15__core__oe(gpio_e15__core__oe),
    .gpio_e15__pad__i(gpio_e15__pad__i),
    .gpio_e15__pad__o(gpio_e15__pad__o),
    .gpio_e15__pad__oe(gpio_e15__pad__oe),
    .gpio_e8__core__i(gpio_e8__core__i),
    .gpio_e8__core__o(gpio_e8__core__o),
    .gpio_e8__core__oe(gpio_e8__core__oe),
    .gpio_e8__pad__i(gpio_e8__pad__i),
    .gpio_e8__pad__o(gpio_e8__pad__o),
    .gpio_e8__pad__oe(gpio_e8__pad__oe),
    .gpio_e9__core__i(gpio_e9__core__i),
    .gpio_e9__core__o(gpio_e9__core__o),
    .gpio_e9__core__oe(gpio_e9__core__oe),
    .gpio_e9__pad__i(gpio_e9__pad__i),
    .gpio_e9__pad__o(gpio_e9__pad__o),
    .gpio_e9__pad__oe(gpio_e9__pad__oe),
    .gpio_s0__core__i(gpio_s0__core__i),
    .gpio_s0__core__o(gpio_s0__core__o),
    .gpio_s0__core__oe(gpio_s0__core__oe),
    .gpio_s0__pad__i(gpio_s0__pad__i),
    .gpio_s0__pad__o(gpio_s0__pad__o),
    .gpio_s0__pad__oe(gpio_s0__pad__oe),
    .gpio_s1__core__i(gpio_s1__core__i),
    .gpio_s1__core__o(gpio_s1__core__o),
    .gpio_s1__core__oe(gpio_s1__core__oe),
    .gpio_s1__pad__i(gpio_s1__pad__i),
    .gpio_s1__pad__o(gpio_s1__pad__o),
    .gpio_s1__pad__oe(gpio_s1__pad__oe),
    .gpio_s2__core__i(gpio_s2__core__i),
    .gpio_s2__core__o(gpio_s2__core__o),
    .gpio_s2__core__oe(gpio_s2__core__oe),
    .gpio_s2__pad__i(gpio_s2__pad__i),
    .gpio_s2__pad__o(gpio_s2__pad__o),
    .gpio_s2__pad__oe(gpio_s2__pad__oe),
    .gpio_s3__core__i(gpio_s3__core__i),
    .gpio_s3__core__o(gpio_s3__core__o),
    .gpio_s3__core__oe(gpio_s3__core__oe),
    .gpio_s3__pad__i(gpio_s3__pad__i),
    .gpio_s3__pad__o(gpio_s3__pad__o),
    .gpio_s3__pad__oe(gpio_s3__pad__oe),
    .gpio_s4__core__i(gpio_s4__core__i),
    .gpio_s4__core__o(gpio_s4__core__o),
    .gpio_s4__core__oe(gpio_s4__core__oe),
    .gpio_s4__pad__i(gpio_s4__pad__i),
    .gpio_s4__pad__o(gpio_s4__pad__o),
    .gpio_s4__pad__oe(gpio_s4__pad__oe),
    .gpio_s5__core__i(gpio_s5__core__i),
    .gpio_s5__core__o(gpio_s5__core__o),
    .gpio_s5__core__oe(gpio_s5__core__oe),
    .gpio_s5__pad__i(gpio_s5__pad__i),
    .gpio_s5__pad__o(gpio_s5__pad__o),
    .gpio_s5__pad__oe(gpio_s5__pad__oe),
    .gpio_s6__core__i(gpio_s6__core__i),
    .gpio_s6__core__o(gpio_s6__core__o),
    .gpio_s6__core__oe(gpio_s6__core__oe),
    .gpio_s6__pad__i(gpio_s6__pad__i),
    .gpio_s6__pad__o(gpio_s6__pad__o),
    .gpio_s6__pad__oe(gpio_s6__pad__oe),
    .gpio_s7__core__i(gpio_s7__core__i),
    .gpio_s7__core__o(gpio_s7__core__o),
    .gpio_s7__core__oe(gpio_s7__core__oe),
    .gpio_s7__pad__i(gpio_s7__pad__i),
    .gpio_s7__pad__o(gpio_s7__pad__o),
    .gpio_s7__pad__oe(gpio_s7__pad__oe),
    .jtag_wb__ack(jtag_wb__ack),
    .jtag_wb__adr(jtag_wb__adr),
    .jtag_wb__cyc(jtag_wb__cyc),
    .jtag_wb__dat_r(jtag_wb__dat_r),
    .jtag_wb__dat_w(jtag_wb__dat_w),
    .jtag_wb__sel(jtag_wb__sel),
    .jtag_wb__stb(jtag_wb__stb),
    .jtag_wb__we(jtag_wb__we),
    .mspi0_clk__core__o(mspi0_clk__core__o),
    .mspi0_clk__pad__o(mspi0_clk__pad__o),
    .mspi0_cs_n__core__o(mspi0_cs_n__core__o),
    .mspi0_cs_n__pad__o(mspi0_cs_n__pad__o),
    .mspi0_miso__core__i(mspi0_miso__core__i),
    .mspi0_miso__pad__i(mspi0_miso__pad__i),
    .mspi0_mosi__core__o(mspi0_mosi__core__o),
    .mspi0_mosi__pad__o(mspi0_mosi__pad__o),
    .mtwi_scl__core__o(mtwi_scl__core__o),
    .mtwi_scl__pad__o(mtwi_scl__pad__o),
    .mtwi_sda__core__i(mtwi_sda__core__i),
    .mtwi_sda__core__o(mtwi_sda__core__o),
    .mtwi_sda__core__oe(mtwi_sda__core__oe),
    .mtwi_sda__pad__i(mtwi_sda__pad__i),
    .mtwi_sda__pad__o(mtwi_sda__pad__o),
    .mtwi_sda__pad__oe(mtwi_sda__pad__oe),
    .rst(rst),
    .sdr_a_0__core__o(sdr_a_0__core__o),
    .sdr_a_0__pad__o(sdr_a_0__pad__o),
    .sdr_a_10__core__o(sdr_a_10__core__o),
    .sdr_a_10__pad__o(sdr_a_10__pad__o),
    .sdr_a_11__core__o(sdr_a_11__core__o),
    .sdr_a_11__pad__o(sdr_a_11__pad__o),
    .sdr_a_12__core__o(sdr_a_12__core__o),
    .sdr_a_12__pad__o(sdr_a_12__pad__o),
    .sdr_a_1__core__o(sdr_a_1__core__o),
    .sdr_a_1__pad__o(sdr_a_1__pad__o),
    .sdr_a_2__core__o(sdr_a_2__core__o),
    .sdr_a_2__pad__o(sdr_a_2__pad__o),
    .sdr_a_3__core__o(sdr_a_3__core__o),
    .sdr_a_3__pad__o(sdr_a_3__pad__o),
    .sdr_a_4__core__o(sdr_a_4__core__o),
    .sdr_a_4__pad__o(sdr_a_4__pad__o),
    .sdr_a_5__core__o(sdr_a_5__core__o),
    .sdr_a_5__pad__o(sdr_a_5__pad__o),
    .sdr_a_6__core__o(sdr_a_6__core__o),
    .sdr_a_6__pad__o(sdr_a_6__pad__o),
    .sdr_a_7__core__o(sdr_a_7__core__o),
    .sdr_a_7__pad__o(sdr_a_7__pad__o),
    .sdr_a_8__core__o(sdr_a_8__core__o),
    .sdr_a_8__pad__o(sdr_a_8__pad__o),
    .sdr_a_9__core__o(sdr_a_9__core__o),
    .sdr_a_9__pad__o(sdr_a_9__pad__o),
    .sdr_ba_0__core__o(sdr_ba_0__core__o),
    .sdr_ba_0__pad__o(sdr_ba_0__pad__o),
    .sdr_ba_1__core__o(sdr_ba_1__core__o),
    .sdr_ba_1__pad__o(sdr_ba_1__pad__o),
    .sdr_cas_n__core__o(sdr_cas_n__core__o),
    .sdr_cas_n__pad__o(sdr_cas_n__pad__o),
    .sdr_cke__core__o(sdr_cke__core__o),
    .sdr_cke__pad__o(sdr_cke__pad__o),
    .sdr_clock__core__o(sdr_clock__core__o),
    .sdr_clock__pad__o(sdr_clock__pad__o),
    .sdr_cs_n__core__o(sdr_cs_n__core__o),
    .sdr_cs_n__pad__o(sdr_cs_n__pad__o),
    .sdr_dm_0__core__o(sdr_dm_0__core__o),
    .sdr_dm_0__pad__o(sdr_dm_0__pad__o),
    .sdr_dm_1__core__o(sdr_dm_1__core__o),
    .sdr_dm_1__pad__o(sdr_dm_1__pad__o),
    .sdr_dq_0__core__i(sdr_dq_0__core__i),
    .sdr_dq_0__core__o(sdr_dq_0__core__o),
    .sdr_dq_0__core__oe(sdr_dq_0__core__oe),
    .sdr_dq_0__pad__i(sdr_dq_0__pad__i),
    .sdr_dq_0__pad__o(sdr_dq_0__pad__o),
    .sdr_dq_0__pad__oe(sdr_dq_0__pad__oe),
    .sdr_dq_10__core__i(sdr_dq_10__core__i),
    .sdr_dq_10__core__o(sdr_dq_10__core__o),
    .sdr_dq_10__core__oe(sdr_dq_10__core__oe),
    .sdr_dq_10__pad__i(sdr_dq_10__pad__i),
    .sdr_dq_10__pad__o(sdr_dq_10__pad__o),
    .sdr_dq_10__pad__oe(sdr_dq_10__pad__oe),
    .sdr_dq_11__core__i(sdr_dq_11__core__i),
    .sdr_dq_11__core__o(sdr_dq_11__core__o),
    .sdr_dq_11__core__oe(sdr_dq_11__core__oe),
    .sdr_dq_11__pad__i(sdr_dq_11__pad__i),
    .sdr_dq_11__pad__o(sdr_dq_11__pad__o),
    .sdr_dq_11__pad__oe(sdr_dq_11__pad__oe),
    .sdr_dq_12__core__i(sdr_dq_12__core__i),
    .sdr_dq_12__core__o(sdr_dq_12__core__o),
    .sdr_dq_12__core__oe(sdr_dq_12__core__oe),
    .sdr_dq_12__pad__i(sdr_dq_12__pad__i),
    .sdr_dq_12__pad__o(sdr_dq_12__pad__o),
    .sdr_dq_12__pad__oe(sdr_dq_12__pad__oe),
    .sdr_dq_13__core__i(sdr_dq_13__core__i),
    .sdr_dq_13__core__o(sdr_dq_13__core__o),
    .sdr_dq_13__core__oe(sdr_dq_13__core__oe),
    .sdr_dq_13__pad__i(sdr_dq_13__pad__i),
    .sdr_dq_13__pad__o(sdr_dq_13__pad__o),
    .sdr_dq_13__pad__oe(sdr_dq_13__pad__oe),
    .sdr_dq_14__core__i(sdr_dq_14__core__i),
    .sdr_dq_14__core__o(sdr_dq_14__core__o),
    .sdr_dq_14__core__oe(sdr_dq_14__core__oe),
    .sdr_dq_14__pad__i(sdr_dq_14__pad__i),
    .sdr_dq_14__pad__o(sdr_dq_14__pad__o),
    .sdr_dq_14__pad__oe(sdr_dq_14__pad__oe),
    .sdr_dq_15__core__i(sdr_dq_15__core__i),
    .sdr_dq_15__core__o(sdr_dq_15__core__o),
    .sdr_dq_15__core__oe(sdr_dq_15__core__oe),
    .sdr_dq_15__pad__i(sdr_dq_15__pad__i),
    .sdr_dq_15__pad__o(sdr_dq_15__pad__o),
    .sdr_dq_15__pad__oe(sdr_dq_15__pad__oe),
    .sdr_dq_1__core__i(sdr_dq_1__core__i),
    .sdr_dq_1__core__o(sdr_dq_1__core__o),
    .sdr_dq_1__core__oe(sdr_dq_1__core__oe),
    .sdr_dq_1__pad__i(sdr_dq_1__pad__i),
    .sdr_dq_1__pad__o(sdr_dq_1__pad__o),
    .sdr_dq_1__pad__oe(sdr_dq_1__pad__oe),
    .sdr_dq_2__core__i(sdr_dq_2__core__i),
    .sdr_dq_2__core__o(sdr_dq_2__core__o),
    .sdr_dq_2__core__oe(sdr_dq_2__core__oe),
    .sdr_dq_2__pad__i(sdr_dq_2__pad__i),
    .sdr_dq_2__pad__o(sdr_dq_2__pad__o),
    .sdr_dq_2__pad__oe(sdr_dq_2__pad__oe),
    .sdr_dq_3__core__i(sdr_dq_3__core__i),
    .sdr_dq_3__core__o(sdr_dq_3__core__o),
    .sdr_dq_3__core__oe(sdr_dq_3__core__oe),
    .sdr_dq_3__pad__i(sdr_dq_3__pad__i),
    .sdr_dq_3__pad__o(sdr_dq_3__pad__o),
    .sdr_dq_3__pad__oe(sdr_dq_3__pad__oe),
    .sdr_dq_4__core__i(sdr_dq_4__core__i),
    .sdr_dq_4__core__o(sdr_dq_4__core__o),
    .sdr_dq_4__core__oe(sdr_dq_4__core__oe),
    .sdr_dq_4__pad__i(sdr_dq_4__pad__i),
    .sdr_dq_4__pad__o(sdr_dq_4__pad__o),
    .sdr_dq_4__pad__oe(sdr_dq_4__pad__oe),
    .sdr_dq_5__core__i(sdr_dq_5__core__i),
    .sdr_dq_5__core__o(sdr_dq_5__core__o),
    .sdr_dq_5__core__oe(sdr_dq_5__core__oe),
    .sdr_dq_5__pad__i(sdr_dq_5__pad__i),
    .sdr_dq_5__pad__o(sdr_dq_5__pad__o),
    .sdr_dq_5__pad__oe(sdr_dq_5__pad__oe),
    .sdr_dq_6__core__i(sdr_dq_6__core__i),
    .sdr_dq_6__core__o(sdr_dq_6__core__o),
    .sdr_dq_6__core__oe(sdr_dq_6__core__oe),
    .sdr_dq_6__pad__i(sdr_dq_6__pad__i),
    .sdr_dq_6__pad__o(sdr_dq_6__pad__o),
    .sdr_dq_6__pad__oe(sdr_dq_6__pad__oe),
    .sdr_dq_7__core__i(sdr_dq_7__core__i),
    .sdr_dq_7__core__o(sdr_dq_7__core__o),
    .sdr_dq_7__core__oe(sdr_dq_7__core__oe),
    .sdr_dq_7__pad__i(sdr_dq_7__pad__i),
    .sdr_dq_7__pad__o(sdr_dq_7__pad__o),
    .sdr_dq_7__pad__oe(sdr_dq_7__pad__oe),
    .sdr_dq_8__core__i(sdr_dq_8__core__i),
    .sdr_dq_8__core__o(sdr_dq_8__core__o),
    .sdr_dq_8__core__oe(sdr_dq_8__core__oe),
    .sdr_dq_8__pad__i(sdr_dq_8__pad__i),
    .sdr_dq_8__pad__o(sdr_dq_8__pad__o),
    .sdr_dq_8__pad__oe(sdr_dq_8__pad__oe),
    .sdr_dq_9__core__i(sdr_dq_9__core__i),
    .sdr_dq_9__core__o(sdr_dq_9__core__o),
    .sdr_dq_9__core__oe(sdr_dq_9__core__oe),
    .sdr_dq_9__pad__i(sdr_dq_9__pad__i),
    .sdr_dq_9__pad__o(sdr_dq_9__pad__o),
    .sdr_dq_9__pad__oe(sdr_dq_9__pad__oe),
    .sdr_ras_n__core__o(sdr_ras_n__core__o),
    .sdr_ras_n__pad__o(sdr_ras_n__pad__o),
    .sdr_we_n__core__o(sdr_we_n__core__o),
    .sdr_we_n__pad__o(sdr_we_n__pad__o),
    .wb_dcache_en(core_wb_dcache_en),
    .wb_icache_en(imem_wb_icache_en)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197912.12-197926.4" *)
  xics_icp xics_icp (
    .clk(clk),
    .core_irq_o(xics_icp_core_irq_o),
    .icp_wb__ack(icp_wb__ack),
    .icp_wb__adr(icp_wb__adr),
    .icp_wb__cyc(icp_wb__cyc),
    .icp_wb__dat_r(icp_wb__dat_r),
    .icp_wb__dat_w(icp_wb__dat_w),
    .icp_wb__sel(icp_wb__sel),
    .icp_wb__stb(icp_wb__stb),
    .icp_wb__we(icp_wb__we),
    .ics_i_pri(xics_icp_ics_i_pri),
    .ics_i_src(xics_icp_ics_i_src),
    .rst(rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:197927.12-197940.4" *)
  xics_ics xics_ics (
    .clk(clk),
    .icp_o_pri(xics_ics_icp_o_pri),
    .icp_o_src(xics_ics_icp_o_src),
    .ics_wb__ack(ics_wb__ack),
    .ics_wb__adr(ics_wb__adr),
    .ics_wb__cyc(ics_wb__cyc),
    .ics_wb__dat_r(ics_wb__dat_r),
    .ics_wb__dat_w(ics_wb__dat_w),
    .ics_wb__stb(ics_wb__stb),
    .ics_wb__we(ics_wb__we),
    .int_level_i(int_level_i),
    .rst(rst)
  );
  always @* begin
    if (\initial ) begin end
    _237_ = 1'h0;
  end
  always @* begin
      \initial  <= _237_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _276_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      core_asmcode <= _276_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_bigendian_i$10  <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _280_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      core_core_core_cia <= _280_;
  end
  always @* begin
    if (\initial ) begin end
    _282_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      core_core_core_cr_rd <= _282_;
  end
  always @* begin
    if (\initial ) begin end
    _284_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_cr_rd_ok <= _284_;
  end
  always @* begin
    if (\initial ) begin end
    _286_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      core_core_core_cr_wr <= _286_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal  <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$3  <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$4  <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$5  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$6  <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$7  <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$8  <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_core_exc_$signal$9  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _296_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      core_core_core_fn_unit <= _296_;
  end
  always @* begin
    if (\initial ) begin end
    _298_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_input_carry <= _298_;
  end
  always @* begin
    if (\initial ) begin end
    _300_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      core_core_core_insn <= _300_;
  end
  always @* begin
    if (\initial ) begin end
    _302_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_core_insn_type <= _302_;
  end
  always @* begin
    if (\initial ) begin end
    _304_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_is_32bit <= _304_;
  end
  always @* begin
    if (\initial ) begin end
    _306_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      core_core_core_msr <= _306_;
  end
  always @* begin
    if (\initial ) begin end
    _308_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_oe <= _308_;
  end
  always @* begin
    if (\initial ) begin end
    _310_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_oe_ok <= _310_;
  end
  always @* begin
    if (\initial ) begin end
    _312_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_rc <= _312_;
  end
  always @* begin
    if (\initial ) begin end
    _314_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_core_rc_ok <= _314_;
  end
  always @* begin
    if (\initial ) begin end
    _316_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      core_core_core_trapaddr <= _316_;
  end
  always @* begin
    if (\initial ) begin end
    _318_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      core_core_core_traptype <= _318_;
  end
  always @* begin
    if (\initial ) begin end
    _320_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_cr_in1 <= _320_;
  end
  always @* begin
    if (\initial ) begin end
    _322_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_cr_in1_ok <= _322_;
  end
  always @* begin
    if (\initial ) begin end
    _325_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_cr_in2 <= _325_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      \core_core_cr_in2$1  <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _328_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_cr_in2_ok <= _328_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      \core_core_cr_in2_ok$2  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _330_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_cr_out <= _330_;
  end
  always @* begin
    if (\initial ) begin end
    _332_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_cr_wr_ok <= _332_;
  end
  always @* begin
    if (\initial ) begin end
    _334_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_dststep <= _334_;
  end
  always @* begin
    if (\initial ) begin end
    _336_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_ea <= _336_;
  end
  always @* begin
    if (\initial ) begin end
    _338_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fast1 <= _338_;
  end
  always @* begin
    if (\initial ) begin end
    _340_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fast1_ok <= _340_;
  end
  always @* begin
    if (\initial ) begin end
    _342_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fast2 <= _342_;
  end
  always @* begin
    if (\initial ) begin end
    _344_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fast2_ok <= _344_;
  end
  always @* begin
    if (\initial ) begin end
    _346_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fasto1 <= _346_;
  end
  always @* begin
    if (\initial ) begin end
    _348_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      core_core_fasto2 <= _348_;
  end
  always @* begin
    if (\initial ) begin end
    _350_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_lk <= _350_;
  end
  always @* begin
    if (\initial ) begin end
    _352_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_maxvl <= _352_;
  end
  always @* begin
    if (\initial ) begin end
    _354_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      core_core_pc <= _354_;
  end
  always @* begin
    if (\initial ) begin end
    _356_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_reg1 <= _356_;
  end
  always @* begin
    if (\initial ) begin end
    _358_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_reg1_ok <= _358_;
  end
  always @* begin
    if (\initial ) begin end
    _360_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_reg2 <= _360_;
  end
  always @* begin
    if (\initial ) begin end
    _362_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_reg2_ok <= _362_;
  end
  always @* begin
    if (\initial ) begin end
    _364_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_reg3 <= _364_;
  end
  always @* begin
    if (\initial ) begin end
    _366_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_reg3_ok <= _366_;
  end
  always @* begin
    if (\initial ) begin end
    _368_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_rego <= _368_;
  end
  always @* begin
    if (\initial ) begin end
    _370_ = 10'h000;
  end
  always @* begin
  end
  initial begin
      core_core_spr1 <= _370_;
  end
  always @* begin
    if (\initial ) begin end
    _372_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_core_spr1_ok <= _372_;
  end
  always @* begin
    if (\initial ) begin end
    _374_ = 10'h000;
  end
  always @* begin
  end
  initial begin
      core_core_spro <= _374_;
  end
  always @* begin
    if (\initial ) begin end
    _376_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_srcstep <= _376_;
  end
  always @* begin
    if (\initial ) begin end
    _378_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      core_core_subvl <= _378_;
  end
  always @* begin
    if (\initial ) begin end
    _380_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      core_core_svstep <= _380_;
  end
  always @* begin
    if (\initial ) begin end
    _382_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      core_core_vl <= _382_;
  end
  always @* begin
    if (\initial ) begin end
    _384_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      core_core_xer_in <= _384_;
  end
  always @* begin
    if (\initial ) begin end
    _386_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_cr_out_ok <= _386_;
  end
  always @* begin
    if (\initial ) begin end
    _390_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      core_dec <= _390_;
  end
  always @* begin
    if (\initial ) begin end
    _394_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_ea_ok <= _394_;
  end
  always @* begin
    if (\initial ) begin end
    _396_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_eint <= _396_;
  end
  always @* begin
    if (\initial ) begin end
    _398_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_fasto1_ok <= _398_;
  end
  always @* begin
    if (\initial ) begin end
    _400_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_fasto2_ok <= _400_;
  end
  always @* begin
    if (\initial ) begin end
    _411_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      core_msr <= _411_;
  end
  always @* begin
    if (\initial ) begin end
    _414_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      core_raw_insn_i <= _414_;
  end
  always @* begin
    if (\initial ) begin end
    _416_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_rego_ok <= _416_;
  end
  always @* begin
    if (\initial ) begin end
    _418_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_spro_ok <= _418_;
  end
  always @* begin
    if (\initial ) begin end
    _422_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_sv_a_nz <= _422_;
  end
  always @* begin
    if (\initial ) begin end
    _426_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_xer_out <= _426_;
  end
  always @* begin
    if (\initial ) begin end
    _427_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      cu_st__rel_o_dly <= _427_;
  end
  always @* begin
    if (\initial ) begin end
    _429_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      cur_cur_dststep <= _429_;
  end
  always @* begin
    if (\initial ) begin end
    _431_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      cur_cur_maxvl <= _431_;
  end
  always @* begin
    if (\initial ) begin end
    _433_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      cur_cur_srcstep <= _433_;
  end
  always @* begin
    if (\initial ) begin end
    _435_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      cur_cur_subvl <= _435_;
  end
  always @* begin
    if (\initial ) begin end
    _437_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      cur_cur_svstep <= _437_;
  end
  always @* begin
    if (\initial ) begin end
    _439_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      cur_cur_vl <= _439_;
  end
  always @* begin
    if (\initial ) begin end
    _441_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      d_cr_delay <= _441_;
  end
  always @* begin
    if (\initial ) begin end
    _443_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      d_reg_delay <= _443_;
  end
  always @* begin
    if (\initial ) begin end
    _445_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      d_xer_delay <= _445_;
  end
  always @* begin
    if (\initial ) begin end
    _454_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      dbg_dmi_addr_i <= _454_;
  end
  always @* begin
    if (\initial ) begin end
    _456_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dbg_dmi_din <= _456_;
  end
  always @* begin
    if (\initial ) begin end
    _458_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dbg_dmi_req_i <= _458_;
  end
  always @* begin
    if (\initial ) begin end
    _460_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dbg_dmi_we_i <= _460_;
  end
  always @* begin
    if (\initial ) begin end
    _462_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dec2_cur_dec <= _462_;
  end
  always @* begin
    if (\initial ) begin end
    _464_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      dec2_cur_eint <= _464_;
  end
  always @* begin
    if (\initial ) begin end
    _466_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dec2_cur_msr <= _466_;
  end
  always @* begin
    if (\initial ) begin end
    _468_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      dec2_cur_pc <= _468_;
  end
  always @* begin
    if (\initial ) begin end
    _470_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      dec2_raw_opcode_in <= _470_;
  end
  always @* begin
    if (\initial ) begin end
    _472_ = 2'h3;
  end
  always @* begin
  end
  initial begin
      delay <= _472_;
  end
  always @* begin
    if (\initial ) begin end
    _474_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      exec_fsm_state <= _474_;
  end
  always @* begin
    if (\initial ) begin end
    _480_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      fetch_fsm_state <= _480_;
  end
  always @* begin
    if (\initial ) begin end
    _486_ = 2'h0;
  end
  always @* begin
  end
  initial begin
      fsm_state <= _486_;
  end
  always @* begin
    if (\initial ) begin end
    _493_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      issue_fsm_state <= _493_;
  end
  always @* begin
    if (\initial ) begin end
    _495_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      jtag_dmi0__ack_o <= _495_;
  end
  always @* begin
    if (\initial ) begin end
    _497_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      jtag_dmi0__dout <= _497_;
  end
  always @* begin
    if (\initial ) begin end
    _499_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      msr_read <= _499_;
  end
  always @* begin
    if (\initial ) begin end
    _509_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      nia <= _509_;
  end
  always @* begin
    if (\initial ) begin end
    _512_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      pc_changed <= _512_;
  end
  always @* begin
    if (\initial ) begin end
    _514_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      pc_ok_delay <= _514_;
  end
  always @* begin
    if (\initial ) begin end
    _518_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      sv_changed <= _518_;
  end
  always @* begin
    if (\initial ) begin end
    _521_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      svstate_ok_delay <= _521_;
  end
  always @* begin
    if (\initial ) begin end
    _233_ = \fsm_state$next ;
  end
  always @(posedge clk) begin
      fsm_state <= _233_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = \core_msr$next ;
  end
  always @(posedge clk) begin
      core_msr <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _243_ = \jtag_dmi0__ack_o$next ;
  end
  always @(posedge clk) begin
      jtag_dmi0__ack_o <= _243_;
  end
  always @* begin
    if (\initial ) begin end
    _203_ = \dbg_dmi_din$next ;
  end
  always @(posedge clk) begin
      dbg_dmi_din <= _203_;
  end
  always @* begin
    if (\initial ) begin end
    _207_ = \dbg_dmi_we_i$next ;
  end
  always @(posedge clk) begin
      dbg_dmi_we_i <= _207_;
  end
  always @* begin
    if (\initial ) begin end
    _205_ = \dbg_dmi_req_i$next ;
  end
  always @(posedge clk) begin
      dbg_dmi_req_i <= _205_;
  end
  always @* begin
    if (\initial ) begin end
    _201_ = \dbg_dmi_addr_i$next ;
  end
  always @(posedge clk) begin
      dbg_dmi_addr_i <= _201_;
  end
  always @* begin
    if (\initial ) begin end
    _143_ = \core_eint$next ;
  end
  always @(posedge clk) begin
      core_eint <= _143_;
  end
  always @* begin
    if (\initial ) begin end
    _137_ = \core_dec$next ;
  end
  always @(posedge clk) begin
      core_dec <= _137_;
  end
  always @* begin
    if (\initial ) begin end
    _127_ = \core_core_svstep$next ;
  end
  always @(posedge clk) begin
      core_core_svstep <= _127_;
  end
  always @* begin
    if (\initial ) begin end
    _125_ = \core_core_subvl$next ;
  end
  always @(posedge clk) begin
      core_core_subvl <= _125_;
  end
  always @* begin
    if (\initial ) begin end
    _081_ = \core_core_dststep$next ;
  end
  always @(posedge clk) begin
      core_core_dststep <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _123_ = \core_core_srcstep$next ;
  end
  always @(posedge clk) begin
      core_core_srcstep <= _123_;
  end
  always @* begin
    if (\initial ) begin end
    _129_ = \core_core_vl$next ;
  end
  always @(posedge clk) begin
      core_core_vl <= _129_;
  end
  always @* begin
    if (\initial ) begin end
    _099_ = \core_core_maxvl$next ;
  end
  always @(posedge clk) begin
      core_core_maxvl <= _099_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = \core_asmcode$next ;
  end
  always @(posedge clk) begin
      core_asmcode <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _192_ = \d_xer_delay$next ;
  end
  always @(posedge clk) begin
      d_xer_delay <= _192_;
  end
  always @* begin
    if (\initial ) begin end
    _115_ = \core_core_rego$next ;
  end
  always @(posedge clk) begin
      core_core_rego <= _115_;
  end
  always @* begin
    if (\initial ) begin end
    _163_ = \core_rego_ok$next ;
  end
  always @(posedge clk) begin
      core_rego_ok <= _163_;
  end
  always @* begin
    if (\initial ) begin end
    _083_ = \core_core_ea$next ;
  end
  always @(posedge clk) begin
      core_core_ea <= _083_;
  end
  always @* begin
    if (\initial ) begin end
    _141_ = \core_ea_ok$next ;
  end
  always @(posedge clk) begin
      core_ea_ok <= _141_;
  end
  always @* begin
    if (\initial ) begin end
    _103_ = \core_core_reg1$next ;
  end
  always @(posedge clk) begin
      core_core_reg1 <= _103_;
  end
  always @* begin
    if (\initial ) begin end
    _105_ = \core_core_reg1_ok$next ;
  end
  always @(posedge clk) begin
      core_core_reg1_ok <= _105_;
  end
  always @* begin
    if (\initial ) begin end
    _107_ = \core_core_reg2$next ;
  end
  always @(posedge clk) begin
      core_core_reg2 <= _107_;
  end
  always @* begin
    if (\initial ) begin end
    _109_ = \core_core_reg2_ok$next ;
  end
  always @(posedge clk) begin
      core_core_reg2_ok <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _111_ = \core_core_reg3$next ;
  end
  always @(posedge clk) begin
      core_core_reg3 <= _111_;
  end
  always @* begin
    if (\initial ) begin end
    _113_ = \core_core_reg3_ok$next ;
  end
  always @(posedge clk) begin
      core_core_reg3_ok <= _113_;
  end
  always @* begin
    if (\initial ) begin end
    _188_ = \d_cr_delay$next ;
  end
  always @(posedge clk) begin
      d_cr_delay <= _188_;
  end
  always @* begin
    if (\initial ) begin end
    _121_ = \core_core_spro$next ;
  end
  always @(posedge clk) begin
      core_core_spro <= _121_;
  end
  always @* begin
    if (\initial ) begin end
    _165_ = \core_spro_ok$next ;
  end
  always @(posedge clk) begin
      core_spro_ok <= _165_;
  end
  always @* begin
    if (\initial ) begin end
    _117_ = \core_core_spr1$next ;
  end
  always @(posedge clk) begin
      core_core_spr1 <= _117_;
  end
  always @* begin
    if (\initial ) begin end
    _119_ = \core_core_spr1_ok$next ;
  end
  always @(posedge clk) begin
      core_core_spr1_ok <= _119_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = \core_core_xer_in$next ;
  end
  always @(posedge clk) begin
      core_core_xer_in <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _173_ = \core_xer_out$next ;
  end
  always @(posedge clk) begin
      core_xer_out <= _173_;
  end
  always @* begin
    if (\initial ) begin end
    _085_ = \core_core_fast1$next ;
  end
  always @(posedge clk) begin
      core_core_fast1 <= _085_;
  end
  always @* begin
    if (\initial ) begin end
    _087_ = \core_core_fast1_ok$next ;
  end
  always @(posedge clk) begin
      core_core_fast1_ok <= _087_;
  end
  always @* begin
    if (\initial ) begin end
    _089_ = \core_core_fast2$next ;
  end
  always @(posedge clk) begin
      core_core_fast2 <= _089_;
  end
  always @* begin
    if (\initial ) begin end
    _091_ = \core_core_fast2_ok$next ;
  end
  always @(posedge clk) begin
      core_core_fast2_ok <= _091_;
  end
  always @* begin
    if (\initial ) begin end
    _190_ = \d_reg_delay$next ;
  end
  always @(posedge clk) begin
      d_reg_delay <= _190_;
  end
  always @* begin
    if (\initial ) begin end
    _093_ = \core_core_fasto1$next ;
  end
  always @(posedge clk) begin
      core_core_fasto1 <= _093_;
  end
  always @* begin
    if (\initial ) begin end
    _145_ = \core_fasto1_ok$next ;
  end
  always @(posedge clk) begin
      core_fasto1_ok <= _145_;
  end
  always @* begin
    if (\initial ) begin end
    _095_ = \core_core_fasto2$next ;
  end
  always @(posedge clk) begin
      core_core_fasto2 <= _095_;
  end
  always @* begin
    if (\initial ) begin end
    _147_ = \core_fasto2_ok$next ;
  end
  always @(posedge clk) begin
      core_fasto2_ok <= _147_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = \core_core_cr_in1$next ;
  end
  always @(posedge clk) begin
      core_core_cr_in1 <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = \core_core_cr_in1_ok$next ;
  end
  always @(posedge clk) begin
      core_core_cr_in1_ok <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \core_core_cr_in2$next ;
  end
  always @(posedge clk) begin
      core_core_cr_in2 <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = \core_core_cr_in2_ok$next ;
  end
  always @(posedge clk) begin
      core_core_cr_in2_ok <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = \core_core_cr_in2$1$next ;
  end
  always @(posedge clk) begin
      \core_core_cr_in2$1  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \core_core_cr_in2_ok$2$next ;
  end
  always @(posedge clk) begin
      \core_core_cr_in2_ok$2  <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _221_ = \exec_fsm_state$next ;
  end
  always @(posedge clk) begin
      exec_fsm_state <= _221_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = \core_core_cr_out$next ;
  end
  always @(posedge clk) begin
      core_core_cr_out <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = \core_cr_out_ok$next ;
  end
  always @(posedge clk) begin
      core_cr_out_ok <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _049_ = \core_core_core_msr$next ;
  end
  always @(posedge clk) begin
      core_core_core_msr <= _049_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \core_core_core_cia$next ;
  end
  always @(posedge clk) begin
      core_core_core_cia <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \core_core_core_insn$next ;
  end
  always @(posedge clk) begin
      core_core_core_insn <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = \core_core_core_insn_type$next ;
  end
  always @(posedge clk) begin
      core_core_core_insn_type <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \core_core_core_fn_unit$next ;
  end
  always @(posedge clk) begin
      core_core_core_fn_unit <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _097_ = \core_core_lk$next ;
  end
  always @(posedge clk) begin
      core_core_lk <= _097_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \core_core_core_rc$next ;
  end
  always @(posedge clk) begin
      core_core_core_rc <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = \core_core_core_rc_ok$next ;
  end
  always @(posedge clk) begin
      core_core_core_rc_ok <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _169_ = \core_sv_a_nz$next ;
  end
  always @(posedge clk) begin
      core_sv_a_nz <= _169_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \core_core_core_oe$next ;
  end
  always @(posedge clk) begin
      core_core_core_oe <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \core_core_core_oe_ok$next ;
  end
  always @(posedge clk) begin
      core_core_core_oe_ok <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \core_core_core_input_carry$next ;
  end
  always @(posedge clk) begin
      core_core_core_input_carry <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = \core_core_core_traptype$next ;
  end
  always @(posedge clk) begin
      core_core_core_traptype <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = \core_core_core_exc_$signal$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal  <= _036_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \core_core_core_exc_$signal$3$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$3  <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = \core_core_core_exc_$signal$4$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$4  <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \core_core_core_exc_$signal$5$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$5  <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = \core_core_core_exc_$signal$6$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$6  <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \core_core_core_exc_$signal$7$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$7  <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \core_bigendian_i$10$next ;
  end
  always @(posedge clk) begin
      \core_bigendian_i$10  <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = \core_core_core_exc_$signal$8$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$8  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \core_core_core_exc_$signal$9$next ;
  end
  always @(posedge clk) begin
      \core_core_core_exc_$signal$9  <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = \core_core_core_trapaddr$next ;
  end
  always @(posedge clk) begin
      core_core_core_trapaddr <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \core_core_core_cr_rd$next ;
  end
  always @(posedge clk) begin
      core_core_core_cr_rd <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \core_core_core_cr_rd_ok$next ;
  end
  always @(posedge clk) begin
      core_core_core_cr_rd_ok <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \core_core_core_cr_wr$next ;
  end
  always @(posedge clk) begin
      core_core_core_cr_wr <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = \core_core_cr_wr_ok$next ;
  end
  always @(posedge clk) begin
      core_core_cr_wr_ok <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = \core_core_core_is_32bit$next ;
  end
  always @(posedge clk) begin
      core_core_core_is_32bit <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _266_ = \sv_changed$next ;
  end
  always @(posedge clk) begin
      sv_changed <= _266_;
  end
  always @* begin
    if (\initial ) begin end
    _260_ = \pc_changed$next ;
  end
  always @(posedge clk) begin
      pc_changed <= _260_;
  end
  always @* begin
    if (\initial ) begin end
    _161_ = \core_raw_insn_i$next ;
  end
  always @(posedge clk) begin
      core_raw_insn_i <= _161_;
  end
  always @* begin
    if (\initial ) begin end
    _241_ = \issue_fsm_state$next ;
  end
  always @(posedge clk) begin
      issue_fsm_state <= _241_;
  end
  always @* begin
    if (\initial ) begin end
    _217_ = \dec2_raw_opcode_in$next ;
  end
  always @(posedge clk) begin
      dec2_raw_opcode_in <= _217_;
  end
  always @* begin
    if (\initial ) begin end
    _227_ = \fetch_fsm_state$next ;
  end
  always @(posedge clk) begin
      fetch_fsm_state <= _227_;
  end
  always @* begin
    if (\initial ) begin end
    _247_ = \msr_read$next ;
  end
  always @(posedge clk) begin
      msr_read <= _247_;
  end
  always @* begin
    if (\initial ) begin end
    _257_ = \nia$next ;
  end
  always @(posedge clk) begin
      nia <= _257_;
  end
  always @* begin
    if (\initial ) begin end
    _269_ = \svstate_ok_delay$next ;
  end
  always @(posedge clk) begin
      svstate_ok_delay <= _269_;
  end
  always @* begin
    if (\initial ) begin end
    _262_ = \pc_ok_delay$next ;
  end
  always @(posedge clk) begin
      pc_ok_delay <= _262_;
  end
  always @* begin
    if (\initial ) begin end
    _174_ = core_cu_st__rel_o;
  end
  always @(posedge clk) begin
      cu_st__rel_o_dly <= _174_;
  end
  always @* begin
    if (\initial ) begin end
    _219_ = \delay$next ;
  end
  always @(posedge por_clk) begin
      delay <= _219_;
  end
  always @* begin
    if (\initial ) begin end
    _211_ = \dec2_cur_eint$next ;
  end
  always @(posedge clk) begin
      dec2_cur_eint <= _211_;
  end
  always @* begin
    if (\initial ) begin end
    _101_ = \core_core_pc$next ;
  end
  always @(posedge clk) begin
      core_core_pc <= _101_;
  end
  always @* begin
    if (\initial ) begin end
    _215_ = \dec2_cur_pc$next ;
  end
  always @(posedge clk) begin
      dec2_cur_pc <= _215_;
  end
  always @* begin
    if (\initial ) begin end
    _213_ = \dec2_cur_msr$next ;
  end
  always @(posedge clk) begin
      dec2_cur_msr <= _213_;
  end
  always @* begin
    if (\initial ) begin end
    _209_ = \dec2_cur_dec$next ;
  end
  always @(posedge clk) begin
      dec2_cur_dec <= _209_;
  end
  always @* begin
    if (\initial ) begin end
    _184_ = \cur_cur_svstep$next ;
  end
  always @(posedge clk) begin
      cur_cur_svstep <= _184_;
  end
  always @* begin
    if (\initial ) begin end
    _182_ = \cur_cur_subvl$next ;
  end
  always @(posedge clk) begin
      cur_cur_subvl <= _182_;
  end
  always @* begin
    if (\initial ) begin end
    _176_ = \cur_cur_dststep$next ;
  end
  always @(posedge clk) begin
      cur_cur_dststep <= _176_;
  end
  always @* begin
    if (\initial ) begin end
    _180_ = \cur_cur_srcstep$next ;
  end
  always @(posedge clk) begin
      cur_cur_srcstep <= _180_;
  end
  always @* begin
    if (\initial ) begin end
    _186_ = \cur_cur_vl$next ;
  end
  always @(posedge clk) begin
      cur_cur_vl <= _186_;
  end
  always @* begin
    if (\initial ) begin end
    _178_ = \cur_cur_maxvl$next ;
  end
  always @(posedge clk) begin
      cur_cur_maxvl <= _178_;
  end
  always @* begin
    if (\initial ) begin end
    _245_ = \jtag_dmi0__dout$next ;
  end
  always @(posedge clk) begin
      jtag_dmi0__dout <= _245_;
  end
  always @* begin
    if (\initial ) begin end
    _200_ = _453_;
    (* src = "libresoc.v:197942.5-197942.29" *)
    casez (\initial )
      /* src = "libresoc.v:197942.9-197942.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _453_ = 4'h0;
        end
      default:
          _453_ = jtag_dmi0__addr_i;
    endcase
  end
  always @* begin
      \dbg_dmi_addr_i$next  <= _200_;
  end
  always @* begin
    if (\initial ) begin end
    _204_ = _457_;
    (* src = "libresoc.v:197951.5-197951.29" *)
    casez (\initial )
      /* src = "libresoc.v:197951.9-197951.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _457_ = 1'h0;
        end
      default:
          _457_ = jtag_dmi0__req_i;
    endcase
  end
  always @* begin
      \dbg_dmi_req_i$next  <= _204_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = _540_;
    _098_ = _543_;
    _100_ = _544_;
    _122_ = _549_;
    _124_ = _550_;
    _126_ = _551_;
    _128_ = _552_;
    _136_ = _555_;
    _142_ = _557_;
    _157_ = _562_;
    (* src = "libresoc.v:197960.5-197960.29" *)
    casez (\initial )
      /* src = "libresoc.v:197960.9-197960.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          { _351_, _381_, _375_, _333_, _377_, _379_, _389_, _395_, _410_, _353_ } = { cur_cur_maxvl, cur_cur_vl, cur_cur_srcstep, cur_cur_dststep, cur_cur_subvl, cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc };
        end
      default:
        begin
          _333_ = core_core_dststep;
          _351_ = core_core_maxvl;
          _353_ = core_core_pc;
          _375_ = core_core_srcstep;
          _377_ = core_core_subvl;
          _379_ = core_core_svstep;
          _381_ = core_core_vl;
          _389_ = core_dec;
          _395_ = core_eint;
          _410_ = core_msr;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _544_ = 64'h0000000000000000;
          _562_ = 64'h0000000000000000;
          _557_ = 1'h0;
          _555_ = 64'h0000000000000000;
          _551_ = 2'h0;
          _550_ = 2'h0;
          _540_ = 7'h00;
          _549_ = 7'h00;
          _552_ = 7'h00;
          _543_ = 7'h00;
        end
      default:
        begin
          _540_ = _333_;
          _543_ = _351_;
          _544_ = _353_;
          _549_ = _375_;
          _550_ = _377_;
          _551_ = _379_;
          _552_ = _381_;
          _555_ = _389_;
          _557_ = _395_;
          _562_ = _410_;
        end
    endcase
  end
  always @* begin
      \core_core_dststep$next  <= _080_;
      \core_core_maxvl$next  <= _098_;
      \core_core_pc$next  <= _100_;
      \core_core_srcstep$next  <= _122_;
      \core_core_subvl$next  <= _124_;
      \core_core_svstep$next  <= _126_;
      \core_core_vl$next  <= _128_;
      \core_dec$next  <= _136_;
      \core_eint$next  <= _142_;
      \core_msr$next  <= _157_;
  end
  always @* begin
    if (\initial ) begin end
    _160_ = _564_;
    (* src = "libresoc.v:198016.5-198016.29" *)
    casez (\initial )
      /* src = "libresoc.v:198016.9-198016.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _413_ = core_raw_insn_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _413_ = core_raw_insn_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _413_ = core_raw_insn_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _413_ = core_raw_insn_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _413_ = core_raw_insn_i;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _413_ = dec2_raw_opcode_in;
        end
      default:
          _413_ = core_raw_insn_i;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _564_ = 32'd0;
        end
      default:
          _564_ = _413_;
    endcase
  end
  always @* begin
      \core_raw_insn_i$next  <= _160_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _523_;
    (* src = "libresoc.v:198052.5-198052.29" *)
    casez (\initial )
      /* src = "libresoc.v:198052.9-198052.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _277_ = \core_bigendian_i$10 ;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _277_ = \core_bigendian_i$10 ;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _277_ = \core_bigendian_i$10 ;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _277_ = \core_bigendian_i$10 ;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _277_ = \core_bigendian_i$10 ;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _277_ = core_bigendian_i;
        end
      default:
          _277_ = \core_bigendian_i$10 ;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _523_ = 1'h0;
        end
      default:
          _523_ = _277_;
    endcase
  end
  always @* begin
      \core_bigendian_i$10$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _168_ = _569_;
    (* src = "libresoc.v:198088.5-198088.29" *)
    casez (\initial )
      /* src = "libresoc.v:198088.9-198088.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _421_ = core_sv_a_nz;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _421_ = core_sv_a_nz;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _421_ = core_sv_a_nz;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _421_ = core_sv_a_nz;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _421_ = core_sv_a_nz;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _421_ = dec2_sv_a_nz;
        end
      default:
          _421_ = core_sv_a_nz;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _569_ = 1'h0;
        end
      default:
          _569_ = _421_;
    endcase
  end
  always @* begin
      \core_sv_a_nz$next  <= _168_;
  end
  always @* begin
    if (\initial ) begin end
    _223_ = _476_;
    (* src = "libresoc.v:198124.5-198124.29" *)
    casez (\initial )
      /* src = "libresoc.v:198124.9-198124.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _476_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _476_ = 1'h1;
        end
      default:
          _476_ = 1'h0;
    endcase
  end
  always @* begin
      exec_insn_valid_i <= _223_;
  end
  always @* begin
    if (\initial ) begin end
    _224_ = _477_;
    (* src = "libresoc.v:198159.5-198159.29" *)
    casez (\initial )
      /* src = "libresoc.v:198159.9-198159.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _477_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _477_ = _584_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$256 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _584_ = 1'h1;
              end
            default:
                _584_ = 1'h0;
          endcase
        end
      default:
          _477_ = 1'h0;
    endcase
  end
  always @* begin
      exec_pc_ready_i <= _224_;
  end
  always @* begin
    if (\initial ) begin end
    _239_ = _491_;
    (* src = "libresoc.v:198203.5-198203.29" *)
    casez (\initial )
      /* src = "libresoc.v:198203.9-198203.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _491_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _491_ = _593_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$262 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _593_ = _630_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _630_ = \$264 ;
                    end
                  default:
                      _630_ = 1'h0;
                endcase
              end
            default:
                _593_ = 1'h0;
          endcase
        end
      default:
          _491_ = 1'h0;
    endcase
  end
  always @* begin
      is_last <= _239_;
  end
  always @* begin
    if (\initial ) begin end
    _170_ = _423_;
    (* src = "libresoc.v:198252.5-198252.29" *)
    casez (\initial )
      /* src = "libresoc.v:198252.9-198252.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
    casez (update_svstate)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _423_ = 3'h4;
        end
      default:
          _423_ = 3'h0;
    endcase
  end
  always @* begin
      \core_wen$11  <= _170_;
  end
  always @* begin
    if (\initial ) begin end
    _134_ = _387_;
    (* src = "libresoc.v:198262.5-198262.29" *)
    casez (\initial )
      /* src = "libresoc.v:198262.9-198262.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
    casez (update_svstate)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _387_ = \$266 ;
        end
      default:
          _387_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      \core_data_i$12  <= _134_;
  end
  always @* begin
    if (\initial ) begin end
    _222_ = _475_;
    (* src = "libresoc.v:198272.5-198272.29" *)
    casez (\initial )
      /* src = "libresoc.v:198272.9-198272.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _475_ = 1'h1;
        end
      default:
          _475_ = 1'h0;
    endcase
  end
  always @* begin
      exec_insn_ready_o <= _222_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = _409_;
    (* src = "libresoc.v:198283.5-198283.29" *)
    casez (\initial )
      /* src = "libresoc.v:198283.9-198283.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _409_ = _561_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
          casez (exec_insn_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _561_ = 1'h1;
              end
            default:
                _561_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _409_ = _611_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *)
          casez (\$268 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _611_ = 1'h1;
              end
            default:
                _611_ = 1'h0;
          endcase
        end
      default:
          _409_ = 1'h0;
    endcase
  end
  always @* begin
      core_ivalid_i <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _155_ = _408_;
    (* src = "libresoc.v:198308.5-198308.29" *)
    casez (\initial )
      /* src = "libresoc.v:198308.9-198308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _408_ = _560_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
          casez (exec_insn_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _560_ = 1'h1;
              end
            default:
                _560_ = 1'h0;
          endcase
        end
      default:
          _408_ = 1'h0;
    endcase
  end
  always @* begin
      core_issue_i <= _155_;
  end
  always @* begin
    if (\initial ) begin end
    _220_ = _680_;
    (* src = "libresoc.v:198324.5-198324.29" *)
    casez (\initial )
      /* src = "libresoc.v:198324.9-198324.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _473_ = _583_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
          casez (exec_insn_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _583_ = 1'h1;
              end
            default:
                _583_ = exec_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _473_ = _625_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
          casez (\$270 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _625_ = _655_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" *)
                casez (exec_pc_ready_i)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _655_ = 1'h0;
                    end
                  default:
                      _655_ = exec_fsm_state;
                endcase
              end
            default:
                _625_ = exec_fsm_state;
          endcase
        end
      default:
          _473_ = exec_fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _680_ = 1'h0;
        end
      default:
          _680_ = _473_;
    endcase
  end
  always @* begin
      \exec_fsm_state$next  <= _220_;
  end
  always @* begin
    if (\initial ) begin end
    _225_ = _478_;
    (* src = "libresoc.v:198359.5-198359.29" *)
    casez (\initial )
      /* src = "libresoc.v:198359.9-198359.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
          _478_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _478_ = _585_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
          casez (\$272 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _585_ = 1'h1;
              end
            default:
                _585_ = 1'h0;
          endcase
        end
      default:
          _478_ = 1'h0;
    endcase
  end
  always @* begin
      exec_pc_valid_o <= _225_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = _391_;
    (* src = "libresoc.v:198379.5-198379.29" *)
    casez (\initial )
      /* src = "libresoc.v:198379.9-198379.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" *)
    casez (dbg_d_gpr_req)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _391_ = dbg_d_gpr_addr[4:0];
        end
      default:
          _391_ = 5'h00;
    endcase
  end
  always @* begin
      core_dmi__addr <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _139_ = _392_;
    (* src = "libresoc.v:198389.5-198389.29" *)
    casez (\initial )
      /* src = "libresoc.v:198389.9-198389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1004" *)
    casez (dbg_d_gpr_req)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _392_ = 1'h1;
        end
      default:
          _392_ = 1'h0;
    endcase
  end
  always @* begin
      core_dmi__ren <= _139_;
  end
  always @* begin
    if (\initial ) begin end
    _189_ = _442_;
    (* src = "libresoc.v:198399.5-198399.29" *)
    casez (\initial )
      /* src = "libresoc.v:198399.9-198399.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _442_ = 1'h0;
        end
      default:
          _442_ = dbg_d_gpr_req;
    endcase
  end
  always @* begin
      \d_reg_delay$next  <= _189_;
  end
  always @* begin
    if (\initial ) begin end
    _197_ = _450_;
    (* src = "libresoc.v:198408.5-198408.29" *)
    casez (\initial )
      /* src = "libresoc.v:198408.9-198408.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" *)
    casez (d_reg_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _450_ = core_dmi__data_o;
        end
      default:
          _450_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dbg_d_gpr_data <= _197_;
  end
  always @* begin
    if (\initial ) begin end
    _196_ = _449_;
    (* src = "libresoc.v:198418.5-198418.29" *)
    casez (\initial )
      /* src = "libresoc.v:198418.9-198418.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1014" *)
    casez (d_reg_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _449_ = 1'h1;
        end
      default:
          _449_ = 1'h0;
    endcase
  end
  always @* begin
      dbg_d_gpr_ack <= _196_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = _401_;
    (* src = "libresoc.v:198428.5-198428.29" *)
    casez (\initial )
      /* src = "libresoc.v:198428.9-198428.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *)
    casez (dbg_d_cr_req)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _401_ = 8'hff;
        end
      default:
          _401_ = 8'h00;
    endcase
  end
  always @* begin
      core_full_rd2__ren <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _187_ = _440_;
    (* src = "libresoc.v:198438.5-198438.29" *)
    casez (\initial )
      /* src = "libresoc.v:198438.9-198438.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _440_ = 1'h0;
        end
      default:
          _440_ = dbg_d_cr_req;
    endcase
  end
  always @* begin
      \d_cr_delay$next  <= _187_;
  end
  always @* begin
    if (\initial ) begin end
    _195_ = _448_;
    (* src = "libresoc.v:198447.5-198447.29" *)
    casez (\initial )
      /* src = "libresoc.v:198447.9-198447.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
    casez (d_cr_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _448_ = \$274 ;
        end
      default:
          _448_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dbg_d_cr_data <= _195_;
  end
  always @* begin
    if (\initial ) begin end
    _194_ = _447_;
    (* src = "libresoc.v:198457.5-198457.29" *)
    casez (\initial )
      /* src = "libresoc.v:198457.9-198457.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *)
    casez (d_cr_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _447_ = 1'h1;
        end
      default:
          _447_ = 1'h0;
    endcase
  end
  always @* begin
      dbg_d_cr_ack <= _194_;
  end
  always @* begin
    if (\initial ) begin end
    _149_ = _402_;
    (* src = "libresoc.v:198467.5-198467.29" *)
    casez (\initial )
      /* src = "libresoc.v:198467.9-198467.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1030" *)
    casez (dbg_d_xer_req)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _402_ = 3'h7;
        end
      default:
          _402_ = 3'h0;
    endcase
  end
  always @* begin
      core_full_rd__ren <= _149_;
  end
  always @* begin
    if (\initial ) begin end
    _191_ = _444_;
    (* src = "libresoc.v:198477.5-198477.29" *)
    casez (\initial )
      /* src = "libresoc.v:198477.9-198477.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _444_ = 1'h0;
        end
      default:
          _444_ = dbg_d_xer_req;
    endcase
  end
  always @* begin
      \d_xer_delay$next  <= _191_;
  end
  always @* begin
    if (\initial ) begin end
    _199_ = _452_;
    (* src = "libresoc.v:198486.5-198486.29" *)
    casez (\initial )
      /* src = "libresoc.v:198486.9-198486.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
    casez (d_xer_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _452_ = \$276 ;
        end
      default:
          _452_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dbg_d_xer_data <= _199_;
  end
  always @* begin
    if (\initial ) begin end
    _198_ = _451_;
    (* src = "libresoc.v:198496.5-198496.29" *)
    casez (\initial )
      /* src = "libresoc.v:198496.9-198496.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1034" *)
    casez (d_xer_delay)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _451_ = 1'h1;
        end
      default:
          _451_ = 1'h0;
    endcase
  end
  always @* begin
      dbg_d_xer_ack <= _198_;
  end
  always @* begin
    if (\initial ) begin end
    _151_ = _404_;
    (* src = "libresoc.v:198506.5-198506.29" *)
    casez (\initial )
      /* src = "libresoc.v:198506.9-198506.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _404_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
          _404_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _404_ = 3'h7;
        end
      default:
          _404_ = 3'h0;
    endcase
  end
  always @* begin
      core_issue__addr <= _151_;
  end
  always @* begin
    if (\initial ) begin end
    _153_ = _406_;
    (* src = "libresoc.v:198525.5-198525.29" *)
    casez (\initial )
      /* src = "libresoc.v:198525.9-198525.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _406_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
          _406_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _406_ = 1'h1;
        end
      default:
          _406_ = 1'h0;
    endcase
  end
  always @* begin
      core_issue__ren <= _153_;
  end
  always @* begin
    if (\initial ) begin end
    _232_ = _588_;
    (* src = "libresoc.v:198544.5-198544.29" *)
    casez (\initial )
      /* src = "libresoc.v:198544.9-198544.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _485_ = 2'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _485_ = 2'h2;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _485_ = 2'h3;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _485_ = 2'h0;
        end
      default:
          _485_ = fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _588_ = 2'h0;
        end
      default:
          _588_ = _485_;
    endcase
  end
  always @* begin
      \fsm_state$next  <= _232_;
  end
  always @* begin
    if (\initial ) begin end
    _248_ = _500_;
    (* src = "libresoc.v:198572.5-198572.29" *)
    casez (\initial )
      /* src = "libresoc.v:198572.9-198572.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _500_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _500_ = \$278 [63:0];
        end
      default:
          _500_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      new_dec <= _248_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = _403_;
    (* src = "libresoc.v:198587.5-198587.29" *)
    casez (\initial )
      /* src = "libresoc.v:198587.9-198587.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _403_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _403_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
          _403_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _403_ = 3'h7;
        end
      default:
          _403_ = 3'h0;
    endcase
  end
  always @* begin
      \core_issue__addr$13  <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = _407_;
    (* src = "libresoc.v:198610.5-198610.29" *)
    casez (\initial )
      /* src = "libresoc.v:198610.9-198610.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _407_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _407_ = 1'h1;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
          _407_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _407_ = 1'h1;
        end
      default:
          _407_ = 1'h0;
    endcase
  end
  always @* begin
      core_issue__wen <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = _405_;
    (* src = "libresoc.v:198633.5-198633.29" *)
    casez (\initial )
      /* src = "libresoc.v:198633.9-198633.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _405_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _405_ = new_dec;
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
          _405_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _405_ = new_tb;
        end
      default:
          _405_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      core_issue__data_i <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _255_ = _507_;
    (* src = "libresoc.v:198656.5-198656.29" *)
    casez (\initial )
      /* src = "libresoc.v:198656.9-198656.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _507_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
          _507_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
          _507_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _507_ = \$281 [63:0];
        end
      default:
          _507_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      new_tb <= _255_;
  end
  always @* begin
    if (\initial ) begin end
    _175_ = _674_;
    _177_ = _675_;
    _179_ = _676_;
    _181_ = _677_;
    _183_ = _678_;
    _185_ = _679_;
    _208_ = _621_;
    _210_ = _579_;
    _212_ = _653_;
    _214_ = _654_;
    (* src = "libresoc.v:198679.5-198679.29" *)
    casez (\initial )
      /* src = "libresoc.v:198679.9-198679.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" *)
    casez (core_coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _430_, _438_, _432_, _428_, _434_, _436_, _461_, _463_, _465_, _467_ } = 225'h000000000000000000000000000000000000000000000000000000000;
        end
      default:
        begin
          _428_ = cur_cur_dststep;
          _430_ = cur_cur_maxvl;
          _432_ = cur_cur_srcstep;
          _434_ = cur_cur_subvl;
          _436_ = cur_cur_svstep;
          _438_ = cur_cur_vl;
          _461_ = dec2_cur_dec;
          _463_ = xics_icp_core_irq_o;
          _465_ = dec2_cur_msr;
          _467_ = dec2_cur_pc;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _580_ = _465_;
          _571_ = _614_;
          _572_ = _615_;
          _573_ = _616_;
          _574_ = _617_;
          _575_ = _618_;
          _576_ = _619_;
          _581_ = _623_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _623_ = pc;
                { _615_, _619_, _616_, _614_, _617_, _618_ } = svstate[31:0];
              end
            default:
              begin
                _614_ = _428_;
                _615_ = _430_;
                _616_ = _432_;
                _617_ = _434_;
                _618_ = _436_;
                _619_ = _438_;
                _623_ = _467_;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _571_ = _428_;
          _572_ = _430_;
          _573_ = _432_;
          _574_ = _434_;
          _575_ = _436_;
          _576_ = _438_;
          _581_ = _467_;
          _580_ = _622_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
          casez (\$23 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _622_ = core_msr__data_o;
              end
            default:
                _622_ = _465_;
          endcase
        end
      default:
        begin
          _571_ = _428_;
          _572_ = _430_;
          _573_ = _432_;
          _574_ = _434_;
          _575_ = _436_;
          _576_ = _438_;
          _580_ = _465_;
          _581_ = _467_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:741" *)
    casez (update_svstate)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _648_, _652_, _649_, _647_, _650_, _651_ } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep };
        end
      default:
        begin
          _647_ = _571_;
          _648_ = _572_;
          _649_ = _573_;
          _650_ = _574_;
          _651_ = _575_;
          _652_ = _576_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1055" *)
    casez (fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _578_ = _461_;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _578_ = new_dec;
        end
      default:
          _578_ = _461_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _579_ = 1'h0;
          _654_ = 64'h0000000000000000;
          _653_ = 64'h0000000000000000;
          _621_ = 64'h0000000000000000;
          _678_ = 2'h0;
          _677_ = 2'h0;
          _674_ = 7'h00;
          _676_ = 7'h00;
          _679_ = 7'h00;
          _675_ = 7'h00;
        end
      default:
        begin
          _674_ = _647_;
          _675_ = _648_;
          _676_ = _649_;
          _677_ = _650_;
          _678_ = _651_;
          _679_ = _652_;
          _621_ = _578_;
          _579_ = _463_;
          _653_ = _580_;
          _654_ = _581_;
        end
    endcase
  end
  always @* begin
      \cur_cur_dststep$next  <= _175_;
      \cur_cur_maxvl$next  <= _177_;
      \cur_cur_srcstep$next  <= _179_;
      \cur_cur_subvl$next  <= _181_;
      \cur_cur_svstep$next  <= _183_;
      \cur_cur_vl$next  <= _185_;
      \dec2_cur_dec$next  <= _208_;
      \dec2_cur_eint$next  <= _210_;
      \dec2_cur_msr$next  <= _212_;
      \dec2_cur_pc$next  <= _214_;
  end
  always @* begin
    if (\initial ) begin end
    _206_ = _459_;
    (* src = "libresoc.v:198755.5-198755.29" *)
    casez (\initial )
      /* src = "libresoc.v:198755.9-198755.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _459_ = 1'h0;
        end
      default:
          _459_ = jtag_dmi0__we_i;
    endcase
  end
  always @* begin
      \dbg_dmi_we_i$next  <= _206_;
  end
  always @* begin
    if (\initial ) begin end
    _261_ = _605_;
    (* src = "libresoc.v:198764.5-198764.29" *)
    casez (\initial )
      /* src = "libresoc.v:198764.9-198764.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$40 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _513_ = \$42 ;
        end
      default:
          _513_ = pc_ok_delay;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _605_ = 1'h0;
        end
      default:
          _605_ = _513_;
    endcase
  end
  always @* begin
      \pc_ok_delay$next  <= _261_;
  end
  always @* begin
    if (\initial ) begin end
    _202_ = _455_;
    (* src = "libresoc.v:198779.5-198779.29" *)
    casez (\initial )
      /* src = "libresoc.v:198779.9-198779.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _455_ = 64'h0000000000000000;
        end
      default:
          _455_ = jtag_dmi0__din;
    endcase
  end
  always @* begin
      \dbg_dmi_din$next  <= _202_;
  end
  always @* begin
    if (\initial ) begin end
    _258_ = _510_;
    (* src = "libresoc.v:198788.5-198788.29" *)
    casez (\initial )
      /* src = "libresoc.v:198788.9-198788.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$44 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _510_ = _640_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
          casez (pc_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _603_ = pc_i;
              end
            default:
                _603_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *)
          casez (pc_ok_delay)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _640_ = core_cia__data_o;
              end
            default:
                _640_ = _603_;
          endcase
        end
      default:
          _510_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      pc <= _258_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _278_;
    (* src = "libresoc.v:198811.5-198811.29" *)
    casez (\initial )
      /* src = "libresoc.v:198811.9-198811.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$46 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _278_ = _524_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
          casez (pc_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _524_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _524_ = 3'h1;
              end
          endcase
        end
      default:
          _278_ = 3'h0;
    endcase
  end
  always @* begin
      core_cia__ren <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _268_ = _608_;
    (* src = "libresoc.v:198829.5-198829.29" *)
    casez (\initial )
      /* src = "libresoc.v:198829.9-198829.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$48 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _520_ = \$50 ;
        end
      default:
          _520_ = svstate_ok_delay;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _608_ = 1'h0;
        end
      default:
          _608_ = _520_;
    endcase
  end
  always @* begin
      \svstate_ok_delay$next  <= _268_;
  end
  always @* begin
    if (\initial ) begin end
    _267_ = _519_;
    (* src = "libresoc.v:198844.5-198844.29" *)
    casez (\initial )
      /* src = "libresoc.v:198844.9-198844.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$52 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _519_ = _643_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
          casez (svstate_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _607_ = \$54 ;
              end
            default:
                _607_ = 64'h0000000000000000;
          endcase
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:74" *)
          casez (svstate_ok_delay)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _643_ = core_sv__data_o;
              end
            default:
                _643_ = _607_;
          endcase
        end
      default:
          _519_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      svstate <= _267_;
  end
  always @* begin
    if (\initial ) begin end
    _167_ = _420_;
    (* src = "libresoc.v:198867.5-198867.29" *)
    casez (\initial )
      /* src = "libresoc.v:198867.9-198867.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *)
    casez (\$56 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _420_ = _568_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *)
          casez (svstate_i_ok)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _568_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _568_ = 3'h4;
              end
          endcase
        end
      default:
          _420_ = 3'h0;
    endcase
  end
  always @* begin
      core_sv__ren <= _167_;
  end
  always @* begin
    if (\initial ) begin end
    _171_ = _424_;
    (* src = "libresoc.v:198885.5-198885.29" *)
    casez (\initial )
      /* src = "libresoc.v:198885.9-198885.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _424_ = _570_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$62 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _570_ = 3'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _570_ = _613_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _613_ = 3'h1;
                    end
                  default:
                      _613_ = 3'h0;
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _424_ = _646_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
          casez (fetch_insn_valid_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _646_ = _673_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
                casez (\$66 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _673_ = 3'h1;
                    end
                  default:
                      _673_ = 3'h0;
                endcase
              end
            default:
                _646_ = 3'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _424_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _424_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _424_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _424_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _424_ = 3'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _424_ = _694_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$72 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _694_ = _704_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _704_ = _712_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
                      casez ({ \$78 , \$74  })
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b?1:
                            _712_ = 3'h0;
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b1?:
                          begin
                            _712_ = 3'h1;
                          end
                        default:
                            _712_ = 3'h0;
                      endcase
                    end
                  default:
                      _704_ = 3'h0;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _694_ = _717_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _717_ = 3'h1;
                    end
                  default:
                      _717_ = 3'h0;
                endcase
              end
          endcase
        end
      default:
          _424_ = 3'h0;
    endcase
  end
  always @* begin
      core_wen <= _171_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = _388_;
    (* src = "libresoc.v:198973.5-198973.29" *)
    casez (\initial )
      /* src = "libresoc.v:198973.9-198973.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _388_ = _554_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$84 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _554_ = 64'h0000000000000000;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _554_ = _610_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _610_ = pc_i;
                    end
                  default:
                      _610_ = 64'h0000000000000000;
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _388_ = _645_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
          casez (fetch_insn_valid_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _645_ = _672_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
                casez (\$88 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _672_ = nia;
                    end
                  default:
                      _672_ = 64'h0000000000000000;
                endcase
              end
            default:
                _645_ = 64'h0000000000000000;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _388_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _388_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _388_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _388_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _388_ = 64'h0000000000000000;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _388_ = _693_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$94 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _693_ = _703_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _703_ = _711_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
                      casez ({ \$100 , \$96  })
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b?1:
                            _711_ = 64'h0000000000000000;
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b1?:
                          begin
                            _711_ = nia;
                          end
                        default:
                            _711_ = 64'h0000000000000000;
                      endcase
                    end
                  default:
                      _703_ = 64'h0000000000000000;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _693_ = _716_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _716_ = pc_i;
                    end
                  default:
                      _716_ = 64'h0000000000000000;
                endcase
              end
          endcase
        end
      default:
          _388_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      core_data_i <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _159_ = _412_;
    (* src = "libresoc.v:199061.5-199061.29" *)
    casez (\initial )
      /* src = "libresoc.v:199061.9-199061.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _412_ = _563_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _563_ = 3'h2;
              end
            default:
                _563_ = 3'h0;
          endcase
        end
      default:
          _412_ = 3'h0;
    endcase
  end
  always @* begin
      core_msr__ren <= _159_;
  end
  always @* begin
    if (\initial ) begin end
    _256_ = _668_;
    (* src = "libresoc.v:199077.5-199077.29" *)
    casez (\initial )
      /* src = "libresoc.v:199077.9-199077.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:911" *)
    casez (core_coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _508_ = 64'h0000000000000000;
        end
      default:
          _508_ = nia;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _602_ = _508_;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _602_ = _639_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _639_ = _508_;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _639_ = \$102 [63:0];
              end
          endcase
        end
      default:
          _602_ = _508_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _668_ = 64'h0000000000000000;
        end
      default:
          _668_ = _602_;
    endcase
  end
  always @* begin
      \nia$next  <= _256_;
  end
  always @* begin
    if (\initial ) begin end
    _242_ = _494_;
    (* src = "libresoc.v:199111.5-199111.29" *)
    casez (\initial )
      /* src = "libresoc.v:199111.9-199111.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _494_ = 1'h0;
        end
      default:
          _494_ = dbg_dmi_ack_o;
    endcase
  end
  always @* begin
      \jtag_dmi0__ack_o$next  <= _242_;
  end
  always @* begin
    if (\initial ) begin end
    _230_ = _483_;
    (* src = "libresoc.v:199120.5-199120.29" *)
    casez (\initial )
      /* src = "libresoc.v:199120.9-199120.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _483_ = 1'h1;
        end
      default:
          _483_ = 1'h0;
    endcase
  end
  always @* begin
      fetch_pc_ready_o <= _230_;
  end
  always @* begin
    if (\initial ) begin end
    _234_ = _487_;
    (* src = "libresoc.v:199131.5-199131.29" *)
    casez (\initial )
      /* src = "libresoc.v:199131.9-199131.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _487_ = _589_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _589_ = pc[47:0];
              end
            default:
                _589_ = 48'h000000000000;
          endcase
        end
      default:
          _487_ = 48'h000000000000;
    endcase
  end
  always @* begin
      imem_a_pc_i <= _234_;
  end
  always @* begin
    if (\initial ) begin end
    _244_ = _496_;
    (* src = "libresoc.v:199147.5-199147.29" *)
    casez (\initial )
      /* src = "libresoc.v:199147.9-199147.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _496_ = 64'h0000000000000000;
        end
      default:
          _496_ = dbg_dmi_dout;
    endcase
  end
  always @* begin
      \jtag_dmi0__dout$next  <= _244_;
  end
  always @* begin
    if (\initial ) begin end
    _235_ = _488_;
    (* src = "libresoc.v:199156.5-199156.29" *)
    casez (\initial )
      /* src = "libresoc.v:199156.9-199156.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _488_ = _590_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _590_ = 1'h1;
              end
            default:
                _590_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _488_ = _627_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _627_ = 1'h1;
              end
            default:
                _627_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _488_ = _657_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _657_ = 1'h1;
              end
            default:
                _657_ = 1'h0;
          endcase
        end
      default:
          _488_ = 1'h0;
    endcase
  end
  always @* begin
      imem_a_valid_i <= _235_;
  end
  always @* begin
    if (\initial ) begin end
    _236_ = _489_;
    (* src = "libresoc.v:199190.5-199190.29" *)
    casez (\initial )
      /* src = "libresoc.v:199190.9-199190.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _489_ = _591_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _591_ = 1'h1;
              end
            default:
                _591_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _489_ = _628_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _628_ = 1'h1;
              end
            default:
                _628_ = 1'h0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _489_ = _658_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _658_ = 1'h1;
              end
            default:
                _658_ = 1'h0;
          endcase
        end
      default:
          _489_ = 1'h0;
    endcase
  end
  always @* begin
      imem_f_valid_i <= _236_;
  end
  always @* begin
    if (\initial ) begin end
    _246_ = _661_;
    (* src = "libresoc.v:199224.5-199224.29" *)
    casez (\initial )
      /* src = "libresoc.v:199224.9-199224.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _498_ = _595_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _595_ = 1'h0;
              end
            default:
                _595_ = msr_read;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _498_ = _632_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" *)
          casez (\$105 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _632_ = 1'h1;
              end
            default:
                _632_ = msr_read;
          endcase
        end
      default:
          _498_ = msr_read;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _661_ = 1'h1;
        end
      default:
          _661_ = _498_;
    endcase
  end
  always @* begin
      \msr_read$next  <= _246_;
  end
  always @* begin
    if (\initial ) begin end
    _226_ = _695_;
    (* src = "libresoc.v:199254.5-199254.29" *)
    casez (\initial )
      /* src = "libresoc.v:199254.9-199254.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
        begin
          _479_ = _586_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" *)
          casez (fetch_pc_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _586_ = 2'h1;
              end
            default:
                _586_ = fetch_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _479_ = _626_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _626_ = fetch_fsm_state;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _626_ = 2'h2;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _479_ = _656_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _656_ = fetch_fsm_state;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _656_ = 2'h2;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _479_ = _681_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:386" *)
          casez (fetch_insn_ready_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _681_ = 2'h0;
              end
            default:
                _681_ = fetch_fsm_state;
          endcase
        end
      default:
          _479_ = fetch_fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _695_ = 2'h0;
        end
      default:
          _695_ = _479_;
    endcase
  end
  always @* begin
      \fetch_fsm_state$next  <= _226_;
  end
  always @* begin
    if (\initial ) begin end
    _216_ = _469_;
    (* src = "libresoc.v:199308.5-199308.29" *)
    casez (\initial )
      /* src = "libresoc.v:199308.9-199308.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _469_ = dec2_raw_opcode_in;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
        begin
          _469_ = _582_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _582_ = dec2_raw_opcode_in;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _582_ = \$107 ;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
        begin
          _469_ = _624_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" *)
          casez (imem_f_busy_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _624_ = dec2_raw_opcode_in;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _624_ = \$111 ;
              end
          endcase
        end
      default:
          _469_ = dec2_raw_opcode_in;
    endcase
  end
  always @* begin
      \dec2_raw_opcode_in$next  <= _216_;
  end
  always @* begin
    if (\initial ) begin end
    _229_ = _482_;
    (* src = "libresoc.v:199343.5-199343.29" *)
    casez (\initial )
      /* src = "libresoc.v:199343.9-199343.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *)
    casez (fetch_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      2'h0:
          _482_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h1:
          _482_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h3:
          _482_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      2'h2:
        begin
          _482_ = 1'h1;
        end
      default:
          _482_ = 1'h0;
    endcase
  end
  always @* begin
      fetch_insn_valid_o <= _229_;
  end
  always @* begin
    if (\initial ) begin end
    _249_ = _501_;
    _250_ = _502_;
    _251_ = _503_;
    _252_ = _504_;
    _253_ = _505_;
    _254_ = _506_;
    (* src = "libresoc.v:199366.5-199366.29" *)
    casez (\initial )
      /* src = "libresoc.v:199366.9-199366.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _501_ = _596_;
          _502_ = _597_;
          _503_ = _598_;
          _504_ = _599_;
          _505_ = _600_;
          _506_ = _601_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$122 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _596_ = cur_cur_dststep;
                _597_ = cur_cur_maxvl;
                _598_ = cur_cur_srcstep;
                _599_ = cur_cur_subvl;
                _600_ = cur_cur_svstep;
                _601_ = cur_cur_vl;
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _596_ = _633_;
                _597_ = _634_;
                _598_ = _635_;
                _599_ = _636_;
                _600_ = _637_;
                _601_ = _638_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _634_, _638_, _635_, _633_, _636_, _637_ } = svstate_i;
                    end
                  default:
                    begin
                      _633_ = cur_cur_dststep;
                      _634_ = cur_cur_maxvl;
                      _635_ = cur_cur_srcstep;
                      _636_ = cur_cur_subvl;
                      _637_ = cur_cur_svstep;
                      _638_ = cur_cur_vl;
                    end
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _501_ = _662_;
          _502_ = _663_;
          _503_ = _664_;
          _504_ = _665_;
          _505_ = _666_;
          _506_ = _667_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$128 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _663_ = cur_cur_maxvl;
                _665_ = cur_cur_subvl;
                _666_ = cur_cur_svstep;
                _667_ = cur_cur_vl;
                _662_ = _684_;
                _664_ = _686_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _684_ = _698_;
                      _686_ = _699_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
                      casez ({ \$134 , \$130  })
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b?1:
                          begin
                            _698_ = cur_cur_dststep;
                            _699_ = cur_cur_srcstep;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b1?:
                          begin
                            _699_ = 7'h00;
                            _698_ = 7'h00;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _699_ = next_srcstep;
                            _698_ = next_dststep;
                          end
                      endcase
                    end
                  default:
                    begin
                      _684_ = cur_cur_dststep;
                      _686_ = cur_cur_srcstep;
                    end
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _662_ = _706_;
                _663_ = _685_;
                _664_ = _707_;
                _665_ = _687_;
                _666_ = _688_;
                _667_ = _689_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      { _685_, _689_, _707_, _706_, _687_, _688_ } = svstate_i;
                    end
                  default:
                    begin
                      _706_ = cur_cur_dststep;
                      _685_ = cur_cur_maxvl;
                      _707_ = cur_cur_srcstep;
                      _687_ = cur_cur_subvl;
                      _688_ = cur_cur_svstep;
                      _689_ = cur_cur_vl;
                    end
                endcase
              end
          endcase
        end
      default:
        begin
          _501_ = cur_cur_dststep;
          _502_ = cur_cur_maxvl;
          _503_ = cur_cur_srcstep;
          _504_ = cur_cur_subvl;
          _505_ = cur_cur_svstep;
          _506_ = cur_cur_vl;
        end
    endcase
  end
  always @* begin
      new_svstate_dststep <= _249_;
      new_svstate_maxvl <= _250_;
      new_svstate_srcstep <= _251_;
      new_svstate_subvl <= _252_;
      new_svstate_svstep <= _253_;
      new_svstate_vl <= _254_;
  end
  always @* begin
    if (\initial ) begin end
    _231_ = _484_;
    (* src = "libresoc.v:199453.5-199453.29" *)
    casez (\initial )
      /* src = "libresoc.v:199453.9-199453.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _484_ = _587_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$146 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _587_ = 1'h1;
              end
            default:
                _587_ = 1'h0;
          endcase
        end
      default:
          _484_ = 1'h0;
    endcase
  end
  always @* begin
      fetch_pc_valid_i <= _231_;
  end
  always @* begin
    if (\initial ) begin end
    _240_ = _274_;
    (* src = "libresoc.v:199469.5-199469.29" *)
    casez (\initial )
      /* src = "libresoc.v:199469.9-199469.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _492_ = _594_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$152 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _594_ = _631_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:549" *)
                casez (fetch_pc_ready_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _631_ = 3'h1;
                    end
                  default:
                      _631_ = issue_fsm_state;
                endcase
              end
            default:
                _594_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _492_ = _660_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
          casez (fetch_insn_valid_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _660_ = _683_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
                casez (\$156 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _683_ = 3'h0;
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  default:
                    begin
                      _683_ = 3'h2;
                    end
                endcase
              end
            default:
                _660_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _492_ = _697_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:589" *)
          casez (pred_insn_ready_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _697_ = 3'h4;
              end
            default:
                _697_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _492_ = _705_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *)
          casez (pred_mask_valid_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _705_ = 3'h5;
              end
            default:
                _705_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _492_ = _713_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:599" *)
          casez (\$158 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _713_ = 3'h2;
              end
            default:
                _713_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          _492_ = 3'h6;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
        begin
          _492_ = _718_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:675" *)
          casez (exec_insn_ready_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _718_ = 3'h7;
              end
            default:
                _718_ = issue_fsm_state;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _492_ = _271_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$164 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _271_ = _272_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _272_ = _273_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
                      casez ({ \$170 , \$166  })
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b?1:
                          begin
                            _273_ = 3'h0;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b1?:
                          begin
                            _273_ = 3'h0;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _273_ = 3'h5;
                          end
                      endcase
                    end
                  default:
                      _272_ = issue_fsm_state;
                endcase
              end
            default:
                _271_ = issue_fsm_state;
          endcase
        end
      default:
          _492_ = issue_fsm_state;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _274_ = 3'h0;
        end
      default:
          _274_ = _492_;
    endcase
  end
  always @* begin
      \issue_fsm_state$next  <= _240_;
  end
  always @* begin
    if (\initial ) begin end
    _166_ = _419_;
    (* src = "libresoc.v:199577.5-199577.29" *)
    casez (\initial )
      /* src = "libresoc.v:199577.9-199577.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _419_ = _567_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$176 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _567_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _567_ = 1'h1;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _419_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _419_ = _612_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$182 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _612_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _612_ = 1'h1;
              end
          endcase
        end
      default:
          _419_ = 1'h0;
    endcase
  end
  always @* begin
      core_stopped_i <= _166_;
  end
  always @* begin
    if (\initial ) begin end
    _193_ = _446_;
    (* src = "libresoc.v:199632.5-199632.29" *)
    casez (\initial )
      /* src = "libresoc.v:199632.9-199632.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _446_ = _577_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$188 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _577_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _577_ = 1'h1;
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _446_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _446_ = _620_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$194 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _620_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _620_ = 1'h1;
              end
          endcase
        end
      default:
          _446_ = 1'h0;
    endcase
  end
  always @* begin
      dbg_core_stopped_i <= _193_;
  end
  always @* begin
    if (\initial ) begin end
    _259_ = _719_;
    (* src = "libresoc.v:199687.5-199687.29" *)
    casez (\initial )
      /* src = "libresoc.v:199687.9-199687.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _511_ = _604_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$200 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _604_ = pc_changed;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _604_ = _641_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:556" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _641_ = 1'h1;
                    end
                  default:
                      _641_ = pc_changed;
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _511_ = pc_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _511_ = _669_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$206 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _669_ = pc_changed;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _669_ = _690_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" *)
                casez (pc_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _690_ = 1'h1;
                    end
                  default:
                      _690_ = pc_changed;
                endcase
              end
          endcase
        end
      default:
          _511_ = pc_changed;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _700_ = _708_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
          casez (exec_insn_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _708_ = 1'h0;
              end
            default:
                _708_ = _511_;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _700_ = _714_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" *)
          casez (\$208 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _714_ = 1'h1;
              end
            default:
                _714_ = _511_;
          endcase
        end
      default:
          _700_ = _511_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _719_ = 1'h0;
        end
      default:
          _719_ = _700_;
    endcase
  end
  always @* begin
      \pc_changed$next  <= _259_;
  end
  always @* begin
    if (\initial ) begin end
    _270_ = _522_;
    (* src = "libresoc.v:199778.5-199778.29" *)
    casez (\initial )
      /* src = "libresoc.v:199778.9-199778.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _522_ = _609_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$216 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _609_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _609_ = _644_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _644_ = 1'h1;
                    end
                  default:
                      _644_ = 1'h0;
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _522_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _522_ = _671_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$222 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _671_ = _692_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" *)
                casez (exec_pc_valid_o)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _692_ = _702_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:693" *)
                      casez ({ \$228 , \$224  })
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b?1:
                            _702_ = 1'h0;
                        /* src = "libresoc.v:0.0-0.0" */
                        2'b1?:
                          begin
                            _702_ = 1'h1;
                          end
                        /* src = "libresoc.v:0.0-0.0" */
                        default:
                          begin
                            _702_ = 1'h1;
                          end
                      endcase
                    end
                  default:
                      _692_ = 1'h0;
                endcase
              end
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _671_ = _710_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _710_ = 1'h1;
                    end
                  default:
                      _710_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _522_ = 1'h0;
    endcase
  end
  always @* begin
      update_svstate <= _270_;
  end
  always @* begin
    if (\initial ) begin end
    _265_ = _720_;
    (* src = "libresoc.v:199859.5-199859.29" *)
    casez (\initial )
      /* src = "libresoc.v:199859.9-199859.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _517_ = _606_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:547" *)
          casez (\$234 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _606_ = sv_changed;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _606_ = _642_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:560" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _642_ = 1'h1;
                    end
                  default:
                      _642_ = sv_changed;
                endcase
              end
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h6:
          _517_ = sv_changed;
      /* src = "libresoc.v:0.0-0.0" */
      3'h7:
        begin
          _517_ = _670_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:681" *)
          casez (\$240 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _670_ = sv_changed;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _670_ = _691_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:735" *)
                casez (svstate_i_ok)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _691_ = 1'h1;
                    end
                  default:
                      _691_ = sv_changed;
                endcase
              end
          endcase
        end
      default:
          _517_ = sv_changed;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
        begin
          _701_ = _709_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *)
          casez (exec_insn_valid_i)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _709_ = 1'h0;
              end
            default:
                _709_ = _517_;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _701_ = _715_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" *)
          casez (\$242 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _715_ = 1'h1;
              end
            default:
                _715_ = _517_;
          endcase
        end
      default:
          _701_ = _517_;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _720_ = 1'h0;
        end
      default:
          _720_ = _701_;
    endcase
  end
  always @* begin
      \sv_changed$next  <= _265_;
  end
  always @* begin
    if (\initial ) begin end
    _228_ = _481_;
    (* src = "libresoc.v:199950.5-199950.29" *)
    casez (\initial )
      /* src = "libresoc.v:199950.9-199950.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _481_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _481_ = 1'h1;
        end
      default:
          _481_ = 1'h0;
    endcase
  end
  always @* begin
      fetch_insn_ready_i <= _228_;
  end
  always @* begin
    if (\initial ) begin end
    _238_ = _659_;
    (* src = "libresoc.v:199965.5-199965.29" *)
    casez (\initial )
      /* src = "libresoc.v:199965.9-199965.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _490_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _490_ = _592_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:568" *)
          casez (fetch_insn_valid_o)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _592_ = _629_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:573" *)
                casez (\$248 )
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _629_ = 1'h1;
                    end
                  default:
                      _629_ = 1'h0;
                endcase
              end
            default:
                _592_ = 1'h0;
          endcase
        end
      default:
          _490_ = 1'h0;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:767" *)
    casez (exec_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      1'h0:
          _659_ = _490_;
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _659_ = _682_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *)
          casez (\$250 )
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _682_ = _696_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" *)
                casez (exec_pc_ready_i)
                  /* src = "libresoc.v:0.0-0.0" */
                  1'h1:
                    begin
                      _696_ = 1'h1;
                    end
                  default:
                      _696_ = _490_;
                endcase
              end
            default:
                _682_ = _490_;
          endcase
        end
      default:
          _659_ = _490_;
    endcase
  end
  always @* begin
      insn_done <= _238_;
  end
  always @* begin
    if (\initial ) begin end
    _263_ = _515_;
    (* src = "libresoc.v:200011.5-200011.29" *)
    casez (\initial )
      /* src = "libresoc.v:200011.9-200011.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _515_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _515_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _515_ = 1'h1;
        end
      default:
          _515_ = 1'h0;
    endcase
  end
  always @* begin
      pred_insn_valid_i <= _263_;
  end
  always @* begin
    if (\initial ) begin end
    _264_ = _516_;
    (* src = "libresoc.v:200030.5-200030.29" *)
    casez (\initial )
      /* src = "libresoc.v:200030.9-200030.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
          _516_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
          _516_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
          _516_ = 1'h0;
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _516_ = 1'h1;
        end
      default:
          _516_ = 1'h0;
    endcase
  end
  always @* begin
      pred_mask_ready_i <= _264_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _275_;
    _006_ = _279_;
    _008_ = _281_;
    _012_ = _285_;
    _038_ = _295_;
    _040_ = _297_;
    _042_ = _299_;
    _044_ = _301_;
    _046_ = _303_;
    _048_ = _305_;
    _050_ = _307_;
    _054_ = _311_;
    _058_ = _315_;
    _060_ = _317_;
    _062_ = _319_;
    _066_ = _323_;
    _069_ = _324_;
    _076_ = _329_;
    _082_ = _335_;
    _084_ = _337_;
    _088_ = _341_;
    _092_ = _345_;
    _094_ = _347_;
    _096_ = _349_;
    _102_ = _355_;
    _106_ = _359_;
    _110_ = _363_;
    _114_ = _367_;
    _116_ = _369_;
    _120_ = _373_;
    _130_ = _383_;
    _172_ = _425_;
    _010_ = _525_;
    _014_ = _526_;
    _017_ = _527_;
    _020_ = _528_;
    _023_ = _529_;
    _026_ = _530_;
    _029_ = _531_;
    _032_ = _532_;
    _035_ = _533_;
    _052_ = _534_;
    _056_ = _535_;
    _064_ = _536_;
    _071_ = _537_;
    _074_ = _538_;
    _078_ = _539_;
    _086_ = _541_;
    _090_ = _542_;
    _104_ = _545_;
    _108_ = _546_;
    _112_ = _547_;
    _118_ = _548_;
    _132_ = _553_;
    _140_ = _556_;
    _144_ = _558_;
    _146_ = _559_;
    _162_ = _565_;
    _164_ = _566_;
    (* src = "libresoc.v:200053.5-200053.29" *)
    casez (\initial )
      /* src = "libresoc.v:200053.9-200053.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" *)
    casez (issue_fsm_state)
      /* src = "libresoc.v:0.0-0.0" */
      3'h0:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h1:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h3:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h4:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h5:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'h2:
        begin
          { _303_, _331_, _285_, _283_, _281_, _315_, _293_, _292_, _291_, _290_, _289_, _288_, _287_, _294_, _317_, _297_, _309_, _307_, _313_, _311_, _349_, _295_, _301_, _299_, _279_, _305_, _385_, _329_, _326_, _323_, _327_, _324_, _321_, _319_, _399_, _347_, _397_, _345_, _343_, _341_, _339_, _337_, _425_, _383_, _371_, _369_, _417_, _373_, _365_, _363_, _361_, _359_, _357_, _355_, _393_, _335_, _415_, _367_, _275_ } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, \dec2_exc_$signal$22 , \dec2_exc_$signal$21 , \dec2_exc_$signal$20 , \dec2_exc_$signal$19 , \dec2_exc_$signal$18 , \dec2_exc_$signal$17 , \dec2_exc_$signal$16 , \dec2_exc_$signal , dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_cia, dec2_msr, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$15 , \dec2_cr_in2$14 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode };
        end
      default:
        begin
          _275_ = core_asmcode;
          _279_ = core_core_core_cia;
          _281_ = core_core_core_cr_rd;
          _283_ = core_core_core_cr_rd_ok;
          _285_ = core_core_core_cr_wr;
          _287_ = \core_core_core_exc_$signal$3 ;
          _288_ = \core_core_core_exc_$signal$4 ;
          _289_ = \core_core_core_exc_$signal$5 ;
          _290_ = \core_core_core_exc_$signal$6 ;
          _291_ = \core_core_core_exc_$signal$7 ;
          _292_ = \core_core_core_exc_$signal$8 ;
          _293_ = \core_core_core_exc_$signal$9 ;
          _294_ = \core_core_core_exc_$signal ;
          _295_ = core_core_core_fn_unit;
          _297_ = core_core_core_input_carry;
          _299_ = core_core_core_insn;
          _301_ = core_core_core_insn_type;
          _303_ = core_core_core_is_32bit;
          _305_ = core_core_core_msr;
          _307_ = core_core_core_oe;
          _309_ = core_core_core_oe_ok;
          _311_ = core_core_core_rc;
          _313_ = core_core_core_rc_ok;
          _315_ = core_core_core_trapaddr;
          _317_ = core_core_core_traptype;
          _319_ = core_core_cr_in1;
          _321_ = core_core_cr_in1_ok;
          _323_ = \core_core_cr_in2$1 ;
          _324_ = core_core_cr_in2;
          _326_ = \core_core_cr_in2_ok$2 ;
          _327_ = core_core_cr_in2_ok;
          _329_ = core_core_cr_out;
          _331_ = core_core_cr_wr_ok;
          _335_ = core_core_ea;
          _337_ = core_core_fast1;
          _339_ = core_core_fast1_ok;
          _341_ = core_core_fast2;
          _343_ = core_core_fast2_ok;
          _345_ = core_core_fasto1;
          _347_ = core_core_fasto2;
          _349_ = core_core_lk;
          _355_ = core_core_reg1;
          _357_ = core_core_reg1_ok;
          _359_ = core_core_reg2;
          _361_ = core_core_reg2_ok;
          _363_ = core_core_reg3;
          _365_ = core_core_reg3_ok;
          _367_ = core_core_rego;
          _369_ = core_core_spr1;
          _371_ = core_core_spr1_ok;
          _373_ = core_core_spro;
          _383_ = core_core_xer_in;
          _385_ = core_cr_out_ok;
          _393_ = core_ea_ok;
          _397_ = core_fasto1_ok;
          _399_ = core_fasto2_ok;
          _415_ = core_rego_ok;
          _417_ = core_spro_ok;
          _425_ = core_xer_out;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _565_ = 1'h0;
          _556_ = 1'h0;
          _545_ = 1'h0;
          _546_ = 1'h0;
          _547_ = 1'h0;
          _566_ = 1'h0;
          _548_ = 1'h0;
          _541_ = 1'h0;
          _542_ = 1'h0;
          _558_ = 1'h0;
          _559_ = 1'h0;
          _536_ = 1'h0;
          _538_ = 1'h0;
          _537_ = 1'h0;
          _553_ = 1'h0;
          _535_ = 1'h0;
          _534_ = 1'h0;
          _533_ = 1'h0;
          _526_ = 1'h0;
          _527_ = 1'h0;
          _528_ = 1'h0;
          _529_ = 1'h0;
          _530_ = 1'h0;
          _531_ = 1'h0;
          _532_ = 1'h0;
          _525_ = 1'h0;
          _539_ = 1'h0;
        end
      default:
        begin
          _525_ = _283_;
          _526_ = _287_;
          _527_ = _288_;
          _528_ = _289_;
          _529_ = _290_;
          _530_ = _291_;
          _531_ = _292_;
          _532_ = _293_;
          _533_ = _294_;
          _534_ = _309_;
          _535_ = _313_;
          _536_ = _321_;
          _537_ = _326_;
          _538_ = _327_;
          _539_ = _331_;
          _541_ = _339_;
          _542_ = _343_;
          _545_ = _357_;
          _546_ = _361_;
          _547_ = _365_;
          _548_ = _371_;
          _553_ = _385_;
          _556_ = _393_;
          _558_ = _397_;
          _559_ = _399_;
          _565_ = _415_;
          _566_ = _417_;
        end
    endcase
  end
  always @* begin
      \core_asmcode$next  <= _000_;
      \core_core_core_cia$next  <= _006_;
      \core_core_core_cr_rd$next  <= _008_;
      \core_core_core_cr_rd_ok$next  <= _010_;
      \core_core_core_cr_wr$next  <= _012_;
      \core_core_core_exc_$signal$3$next  <= _014_;
      \core_core_core_exc_$signal$4$next  <= _017_;
      \core_core_core_exc_$signal$5$next  <= _020_;
      \core_core_core_exc_$signal$6$next  <= _023_;
      \core_core_core_exc_$signal$7$next  <= _026_;
      \core_core_core_exc_$signal$8$next  <= _029_;
      \core_core_core_exc_$signal$9$next  <= _032_;
      \core_core_core_exc_$signal$next  <= _035_;
      \core_core_core_fn_unit$next  <= _038_;
      \core_core_core_input_carry$next  <= _040_;
      \core_core_core_insn$next  <= _042_;
      \core_core_core_insn_type$next  <= _044_;
      \core_core_core_is_32bit$next  <= _046_;
      \core_core_core_msr$next  <= _048_;
      \core_core_core_oe$next  <= _050_;
      \core_core_core_oe_ok$next  <= _052_;
      \core_core_core_rc$next  <= _054_;
      \core_core_core_rc_ok$next  <= _056_;
      \core_core_core_trapaddr$next  <= _058_;
      \core_core_core_traptype$next  <= _060_;
      \core_core_cr_in1$next  <= _062_;
      \core_core_cr_in1_ok$next  <= _064_;
      \core_core_cr_in2$1$next  <= _066_;
      \core_core_cr_in2$next  <= _069_;
      \core_core_cr_in2_ok$2$next  <= _071_;
      \core_core_cr_in2_ok$next  <= _074_;
      \core_core_cr_out$next  <= _076_;
      \core_core_cr_wr_ok$next  <= _078_;
      \core_core_ea$next  <= _082_;
      \core_core_fast1$next  <= _084_;
      \core_core_fast1_ok$next  <= _086_;
      \core_core_fast2$next  <= _088_;
      \core_core_fast2_ok$next  <= _090_;
      \core_core_fasto1$next  <= _092_;
      \core_core_fasto2$next  <= _094_;
      \core_core_lk$next  <= _096_;
      \core_core_reg1$next  <= _102_;
      \core_core_reg1_ok$next  <= _104_;
      \core_core_reg2$next  <= _106_;
      \core_core_reg2_ok$next  <= _108_;
      \core_core_reg3$next  <= _110_;
      \core_core_reg3_ok$next  <= _112_;
      \core_core_rego$next  <= _114_;
      \core_core_spr1$next  <= _116_;
      \core_core_spr1_ok$next  <= _118_;
      \core_core_spro$next  <= _120_;
      \core_core_xer_in$next  <= _130_;
      \core_cr_out_ok$next  <= _132_;
      \core_ea_ok$next  <= _140_;
      \core_fasto1_ok$next  <= _144_;
      \core_fasto2_ok$next  <= _146_;
      \core_rego_ok$next  <= _162_;
      \core_spro_ok$next  <= _164_;
      \core_xer_out$next  <= _172_;
  end
  always @* begin
    if (\initial ) begin end
    _218_ = _471_;
    (* src = "libresoc.v:200175.5-200175.29" *)
    casez (\initial )
      /* src = "libresoc.v:200175.9-200175.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:849" *)
    casez (\$25 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _471_ = \$27 [1:0];
        end
      default:
          _471_ = delay;
    endcase
  end
  always @* begin
      \delay$next  <= _218_;
  end
  assign \$100  = _824_;
  assign \$103  = _721_;
  assign \$105  = _767_;
  assign \$108  = _762_;
  assign \$107  = _842_[31:0];
  assign \$113  = _722_;
  assign \$115  = _763_;
  assign \$111  = _843_[31:0];
  assign \$118  = _768_;
  assign \$120  = _769_;
  assign \$122  = _726_;
  assign \$124  = _770_;
  assign \$126  = _771_;
  assign \$128  = _727_;
  assign \$130  = _825_;
  assign \$132  = 1'h1;
  assign \$134  = _826_;
  assign \$137  = _723_;
  assign \$140  = _724_;
  assign \$142  = _772_;
  assign \$144  = _773_;
  assign \$146  = _728_;
  assign \$148  = _774_;
  assign \$150  = _775_;
  assign \$152  = _729_;
  assign \$154  = _754_;
  assign \$156  = _730_;
  assign \$158  = _776_;
  assign \$160  = _777_;
  assign \$162  = _778_;
  assign \$164  = _731_;
  assign \$166  = _827_;
  assign \$168  = 1'h1;
  assign \$170  = _828_;
  assign \$172  = _779_;
  assign \$174  = _780_;
  assign \$176  = _732_;
  assign \$178  = _781_;
  assign \$180  = _782_;
  assign \$182  = _733_;
  assign \$184  = _783_;
  assign \$186  = _784_;
  assign \$188  = _734_;
  assign \$190  = _785_;
  assign \$192  = _786_;
  assign \$194  = _735_;
  assign \$196  = _787_;
  assign \$198  = _788_;
  assign \$200  = _736_;
  assign \$202  = _789_;
  assign \$204  = _790_;
  assign \$206  = _737_;
  assign \$209  = _738_;
  assign \$208  = _840_;
  assign \$212  = _791_;
  assign \$214  = _792_;
  assign \$216  = _739_;
  assign \$218  = _793_;
  assign \$220  = _794_;
  assign \$222  = _740_;
  assign \$224  = _829_;
  assign \$226  = 1'h1;
  assign \$228  = _830_;
  assign \$230  = _795_;
  assign \$232  = _796_;
  assign \$234  = _741_;
  assign \$236  = _797_;
  assign \$238  = _798_;
  assign \$23  = _799_;
  assign \$240  = _742_;
  assign \$243  = _743_;
  assign \$242  = _841_;
  assign \$246  = _755_;
  assign \$248  = _744_;
  assign \$250  = _800_;
  assign \$252  = _801_;
  assign \$254  = _802_;
  assign \$256  = _745_;
  assign \$258  = _803_;
  assign \$25  = _764_;
  assign \$260  = _804_;
  assign \$262  = _746_;
  assign \$264  = _756_;
  assign \$266  = _836_;
  assign \$268  = _765_;
  assign \$270  = _805_;
  assign \$272  = _806_;
  assign \$274  = _837_;
  assign \$276  = _838_;
  assign \$279  = _844_;
  assign \$282  = _725_;
  assign \$28  = _845_;
  assign \$30  = _831_;
  assign \$32  = _832_;
  assign \$34  = _766_;
  assign \$36  = _807_;
  assign \$38  = _747_;
  assign \$40  = _808_;
  assign \$42  = _809_;
  assign \$44  = _810_;
  assign \$46  = _811_;
  assign \$48  = _812_;
  assign \$50  = _813_;
  assign \$52  = _814_;
  assign \$54  = _839_;
  assign \$56  = _815_;
  assign \$58  = _816_;
  assign \$60  = _817_;
  assign \$62  = _748_;
  assign \$64  = _757_;
  assign \$66  = _749_;
  assign \$68  = _818_;
  assign \$70  = _819_;
  assign \$72  = _750_;
  assign \$74  = _833_;
  assign \$76  = 1'h1;
  assign \$78  = _834_;
  assign \$80  = _820_;
  assign \$82  = _821_;
  assign \$84  = _751_;
  assign \$86  = _758_;
  assign \$88  = _752_;
  assign \$90  = _822_;
  assign \$92  = _823_;
  assign \$94  = _753_;
  assign \$96  = _835_;
  assign \$98  = 1'h1;
  assign \$27  = \$28 ;
  assign \$102  = \$103 ;
  assign \$112  = \$113 ;
  assign \$136  = \$137 ;
  assign \$139  = \$140 ;
  assign \$278  = \$279 ;
  assign \$281  = \$282 ;
  assign dec2_sv_a_nz = 1'h0;
  assign svstate_i_ok = 1'h0;
  assign svstate_i = 32'd0;
  assign is_svp64_mode = 1'h0;
  assign pred_insn_ready_o = 1'h0;
  assign pred_mask_valid_o = 1'h0;
  assign next_dststep = \$140 [6:0];
  assign next_srcstep = \$137 [6:0];
  assign dbg_core_dbg_msr = dec2_cur_msr;
  assign { dbg_core_dbg_core_dbg_maxvl, dbg_core_dbg_core_dbg_vl, dbg_core_dbg_core_dbg_srcstep, dbg_core_dbg_core_dbg_dststep, dbg_core_dbg_core_dbg_subvl, dbg_core_dbg_core_dbg_svstep } = svstate[31:0];
  assign dbg_core_dbg_pc = pc;
  assign dbg_terminate_i = core_core_terminate_o;
  assign pc_o = dec2_cur_pc;
  assign core_cu_st__go_i = cu_st__rel_o_rise;
  assign core_cu_ad__go_i = core_cu_ad__rel_o;
  assign cu_st__rel_o_rise = \$38 ;
  assign \cu_st__rel_o_dly$next  = core_cu_st__rel_o;
  assign dec2_bigendian = core_bigendian_i;
  assign busy_o = core_corebusy_o;
  assign core_coresync_rst = ti_rst;
  assign ti_rst = \$34 ;
  assign por_clk = clk;
  assign { xics_icp_ics_i_pri, xics_icp_ics_i_src } = { xics_ics_icp_o_pri, xics_ics_icp_o_src };
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.trap0" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:200218.1-201409.10" *)
module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, cu_issue_i, cu_busy_o, cu_rdmaskn_i, cu_rd__rel_o, cu_rd__go_i, src2_i, src1_i, src3_i, src4_i, o_ok, cu_wr__rel_o, cu_wr__go_i, dest1_o, fast1_ok, fast2_ok, dest2_o, dest3_o, nia_ok, dest4_o, msr_ok, dest5_o, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:200954.3-200955.25" *)
  reg _000_;
  (* src = "libresoc.v:200952.3-200953.41" *)
  reg _001_;
  (* src = "libresoc.v:201312.3-201320.6" *)
  reg _002_;
  (* src = "libresoc.v:200880.3-200881.39" *)
  reg _003_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [63:0] _004_;
  (* src = "libresoc.v:200920.3-200921.61" *)
  reg [63:0] _005_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [13:0] _006_;
  (* src = "libresoc.v:200914.3-200915.69" *)
  reg [13:0] _007_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [31:0] _008_;
  (* src = "libresoc.v:200916.3-200917.63" *)
  reg [31:0] _009_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [6:0] _010_;
  (* src = "libresoc.v:200912.3-200913.73" *)
  reg [6:0] _011_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg _012_;
  (* src = "libresoc.v:200922.3-200923.71" *)
  reg _013_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [7:0] _014_;
  (* src = "libresoc.v:200928.3-200929.71" *)
  reg [7:0] _015_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [63:0] _016_;
  (* src = "libresoc.v:200918.3-200919.61" *)
  reg [63:0] _017_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [12:0] _018_;
  (* src = "libresoc.v:200926.3-200927.71" *)
  reg [12:0] _019_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [7:0] _020_;
  (* src = "libresoc.v:200924.3-200925.71" *)
  reg [7:0] _021_;
  (* src = "libresoc.v:201303.3-201311.6" *)
  reg _022_;
  (* src = "libresoc.v:200882.3-200883.43" *)
  reg _023_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg [63:0] _024_;
  (* src = "libresoc.v:200908.3-200909.37" *)
  reg [63:0] _025_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg _026_;
  (* src = "libresoc.v:200910.3-200911.43" *)
  reg _027_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg [63:0] _028_;
  (* src = "libresoc.v:200904.3-200905.45" *)
  reg [63:0] _029_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg _030_;
  (* src = "libresoc.v:200906.3-200907.51" *)
  reg _031_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg [63:0] _032_;
  (* src = "libresoc.v:200900.3-200901.45" *)
  reg [63:0] _033_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg _034_;
  (* src = "libresoc.v:200902.3-200903.51" *)
  reg _035_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg [63:0] _036_;
  (* src = "libresoc.v:200896.3-200897.41" *)
  reg [63:0] _037_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg _038_;
  (* src = "libresoc.v:200898.3-200899.47" *)
  reg _039_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg [63:0] _040_;
  (* src = "libresoc.v:200892.3-200893.41" *)
  reg [63:0] _041_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg _042_;
  (* src = "libresoc.v:200894.3-200895.47" *)
  reg _043_;
  (* src = "libresoc.v:201321.3-201330.6" *)
  reg [63:0] _044_;
  (* src = "libresoc.v:201331.3-201340.6" *)
  reg [63:0] _045_;
  (* src = "libresoc.v:201341.3-201350.6" *)
  reg [63:0] _046_;
  (* src = "libresoc.v:201351.3-201360.6" *)
  reg [63:0] _047_;
  (* src = "libresoc.v:201361.3-201370.6" *)
  reg [63:0] _048_;
  (* src = "libresoc.v:200219.7-200219.20" *)
  reg _049_;
  (* src = "libresoc.v:201090.3-201098.6" *)
  reg _050_;
  (* src = "libresoc.v:200938.3-200939.39" *)
  reg _051_;
  (* src = "libresoc.v:201081.3-201089.6" *)
  reg _052_;
  (* src = "libresoc.v:200940.3-200941.39" *)
  reg _053_;
  (* src = "libresoc.v:201371.3-201379.6" *)
  reg [4:0] _054_;
  (* src = "libresoc.v:200950.3-200951.37" *)
  reg [4:0] _055_;
  (* src = "libresoc.v:201035.3-201044.6" *)
  reg _056_;
  (* src = "libresoc.v:201126.3-201134.6" *)
  reg [4:0] _057_;
  (* src = "libresoc.v:200930.3-200931.39" *)
  reg [4:0] _058_;
  (* src = "libresoc.v:201117.3-201125.6" *)
  reg [4:0] _059_;
  (* src = "libresoc.v:200932.3-200933.39" *)
  reg [4:0] _060_;
  (* src = "libresoc.v:201054.3-201062.6" *)
  reg _061_;
  (* src = "libresoc.v:200946.3-200947.41" *)
  reg _062_;
  (* src = "libresoc.v:201045.3-201053.6" *)
  reg _063_;
  (* src = "libresoc.v:200948.3-200949.41" *)
  reg _064_;
  (* src = "libresoc.v:201072.3-201080.6" *)
  reg _065_;
  (* src = "libresoc.v:200942.3-200943.39" *)
  reg _066_;
  (* src = "libresoc.v:201063.3-201071.6" *)
  reg _067_;
  (* src = "libresoc.v:200944.3-200945.39" *)
  reg _068_;
  (* src = "libresoc.v:201108.3-201116.6" *)
  reg [3:0] _069_;
  (* src = "libresoc.v:200934.3-200935.39" *)
  reg [3:0] _070_;
  (* src = "libresoc.v:201099.3-201107.6" *)
  reg [3:0] _071_;
  (* src = "libresoc.v:200936.3-200937.39" *)
  reg [3:0] _072_;
  (* src = "libresoc.v:201263.3-201272.6" *)
  reg [63:0] _073_;
  (* src = "libresoc.v:200890.3-200891.29" *)
  reg [63:0] _074_;
  (* src = "libresoc.v:201273.3-201282.6" *)
  reg [63:0] _075_;
  (* src = "libresoc.v:200888.3-200889.29" *)
  reg [63:0] _076_;
  (* src = "libresoc.v:201283.3-201292.6" *)
  reg [63:0] _077_;
  (* src = "libresoc.v:200886.3-200887.29" *)
  reg [63:0] _078_;
  (* src = "libresoc.v:201293.3-201302.6" *)
  reg [63:0] _079_;
  (* src = "libresoc.v:200884.3-200885.29" *)
  reg [63:0] _080_;
  (* src = "libresoc.v:200345.7-200345.24" *)
  reg _081_;
  (* src = "libresoc.v:200355.7-200355.26" *)
  reg _082_;
  (* src = "libresoc.v:201312.3-201320.6" *)
  reg _083_;
  (* src = "libresoc.v:200363.7-200363.25" *)
  reg _084_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [63:0] _085_;
  (* src = "libresoc.v:200399.14-200399.59" *)
  reg [63:0] _086_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [13:0] _087_;
  (* src = "libresoc.v:200418.14-200418.51" *)
  reg [13:0] _088_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [31:0] _089_;
  (* src = "libresoc.v:200422.14-200422.45" *)
  reg [31:0] _090_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [6:0] _091_;
  (* src = "libresoc.v:200501.13-200501.49" *)
  reg [6:0] _092_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg _093_;
  (* src = "libresoc.v:200505.7-200505.41" *)
  reg _094_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [7:0] _095_;
  (* src = "libresoc.v:200509.13-200509.48" *)
  reg [7:0] _096_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [63:0] _097_;
  (* src = "libresoc.v:200513.14-200513.59" *)
  reg [63:0] _098_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [12:0] _099_;
  (* src = "libresoc.v:200517.14-200517.52" *)
  reg [12:0] _100_;
  (* src = "libresoc.v:201135.3-201152.6" *)
  reg [7:0] _101_;
  (* src = "libresoc.v:200521.13-200521.48" *)
  reg [7:0] _102_;
  (* src = "libresoc.v:201303.3-201311.6" *)
  reg _103_;
  (* src = "libresoc.v:200527.7-200527.27" *)
  reg _104_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg [63:0] _105_;
  (* src = "libresoc.v:200559.14-200559.47" *)
  reg [63:0] _106_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg _107_;
  (* src = "libresoc.v:200563.7-200563.27" *)
  reg _108_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg [63:0] _109_;
  (* src = "libresoc.v:200567.14-200567.51" *)
  reg [63:0] _110_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg _111_;
  (* src = "libresoc.v:200571.7-200571.31" *)
  reg _112_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg [63:0] _113_;
  (* src = "libresoc.v:200575.14-200575.51" *)
  reg [63:0] _114_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg _115_;
  (* src = "libresoc.v:200579.7-200579.31" *)
  reg _116_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg [63:0] _117_;
  (* src = "libresoc.v:200583.14-200583.49" *)
  reg [63:0] _118_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg _119_;
  (* src = "libresoc.v:200587.7-200587.29" *)
  reg _120_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg [63:0] _121_;
  (* src = "libresoc.v:200591.14-200591.49" *)
  reg [63:0] _122_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg _123_;
  (* src = "libresoc.v:200595.7-200595.29" *)
  reg _124_;
  (* src = "libresoc.v:201321.3-201330.6" *)
  reg [63:0] _125_;
  (* src = "libresoc.v:201331.3-201340.6" *)
  reg [63:0] _126_;
  (* src = "libresoc.v:201341.3-201350.6" *)
  reg [63:0] _127_;
  (* src = "libresoc.v:201351.3-201360.6" *)
  reg [63:0] _128_;
  (* src = "libresoc.v:201361.3-201370.6" *)
  reg [63:0] _129_;
  (* src = "libresoc.v:201090.3-201098.6" *)
  reg _130_;
  (* src = "libresoc.v:200626.7-200626.25" *)
  reg _131_;
  (* src = "libresoc.v:201081.3-201089.6" *)
  reg _132_;
  (* src = "libresoc.v:200630.7-200630.25" *)
  reg _133_;
  (* src = "libresoc.v:201371.3-201379.6" *)
  reg [4:0] _134_;
  (* src = "libresoc.v:200742.13-200742.31" *)
  reg [4:0] _135_;
  (* src = "libresoc.v:201035.3-201044.6" *)
  reg _136_;
  (* src = "libresoc.v:201126.3-201134.6" *)
  reg [4:0] _137_;
  (* src = "libresoc.v:200750.13-200750.32" *)
  reg [4:0] _138_;
  (* src = "libresoc.v:201117.3-201125.6" *)
  reg [4:0] _139_;
  (* src = "libresoc.v:200754.13-200754.32" *)
  reg [4:0] _140_;
  (* src = "libresoc.v:201054.3-201062.6" *)
  reg _141_;
  (* src = "libresoc.v:200766.7-200766.26" *)
  reg _142_;
  (* src = "libresoc.v:201045.3-201053.6" *)
  reg _143_;
  (* src = "libresoc.v:200770.7-200770.26" *)
  reg _144_;
  (* src = "libresoc.v:201072.3-201080.6" *)
  reg _145_;
  (* src = "libresoc.v:200774.7-200774.25" *)
  reg _146_;
  (* src = "libresoc.v:201063.3-201071.6" *)
  reg _147_;
  (* src = "libresoc.v:200778.7-200778.25" *)
  reg _148_;
  (* src = "libresoc.v:201108.3-201116.6" *)
  reg [3:0] _149_;
  (* src = "libresoc.v:200794.13-200794.31" *)
  reg [3:0] _150_;
  (* src = "libresoc.v:201099.3-201107.6" *)
  reg [3:0] _151_;
  (* src = "libresoc.v:200798.13-200798.31" *)
  reg [3:0] _152_;
  (* src = "libresoc.v:201263.3-201272.6" *)
  reg [63:0] _153_;
  (* src = "libresoc.v:200802.14-200802.43" *)
  reg [63:0] _154_;
  (* src = "libresoc.v:201273.3-201282.6" *)
  reg [63:0] _155_;
  (* src = "libresoc.v:200806.14-200806.43" *)
  reg [63:0] _156_;
  (* src = "libresoc.v:201283.3-201292.6" *)
  reg [63:0] _157_;
  (* src = "libresoc.v:200810.14-200810.43" *)
  reg [63:0] _158_;
  (* src = "libresoc.v:201293.3-201302.6" *)
  reg [63:0] _159_;
  (* src = "libresoc.v:200814.14-200814.43" *)
  reg [63:0] _160_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg [63:0] _161_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg _162_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg [63:0] _163_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg _164_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg [63:0] _165_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg _166_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg [63:0] _167_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg _168_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg [63:0] _169_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg _170_;
  (* src = "libresoc.v:201153.3-201174.6" *)
  reg _171_;
  (* src = "libresoc.v:201175.3-201196.6" *)
  reg _172_;
  (* src = "libresoc.v:201197.3-201218.6" *)
  reg _173_;
  (* src = "libresoc.v:201219.3-201240.6" *)
  reg _174_;
  (* src = "libresoc.v:201241.3-201262.6" *)
  reg _175_;
  (* src = "libresoc.v:200820.18-200820.112" *)
  wire [3:0] _176_;
  (* src = "libresoc.v:200821.19-200821.125" *)
  wire _177_;
  (* src = "libresoc.v:200822.19-200822.125" *)
  wire _178_;
  (* src = "libresoc.v:200823.19-200823.125" *)
  wire _179_;
  (* src = "libresoc.v:200824.19-200824.125" *)
  wire _180_;
  (* src = "libresoc.v:200825.19-200825.125" *)
  wire _181_;
  (* src = "libresoc.v:200826.19-200826.157" *)
  wire [4:0] _182_;
  (* src = "libresoc.v:200827.19-200827.121" *)
  wire [4:0] _183_;
  (* src = "libresoc.v:200828.19-200828.127" *)
  wire _184_;
  (* src = "libresoc.v:200829.19-200829.127" *)
  wire _185_;
  (* src = "libresoc.v:200830.18-200830.110" *)
  wire _186_;
  (* src = "libresoc.v:200831.19-200831.127" *)
  wire _187_;
  (* src = "libresoc.v:200832.19-200832.127" *)
  wire _188_;
  (* src = "libresoc.v:200833.19-200833.127" *)
  wire _189_;
  (* src = "libresoc.v:200835.18-200835.98" *)
  wire _190_;
  (* src = "libresoc.v:200837.18-200837.100" *)
  wire _191_;
  (* src = "libresoc.v:200838.18-200838.171" *)
  wire [4:0] _192_;
  (* src = "libresoc.v:200840.18-200840.119" *)
  wire [4:0] _193_;
  (* src = "libresoc.v:200843.18-200843.116" *)
  wire _194_;
  (* src = "libresoc.v:200847.17-200847.123" *)
  wire _195_;
  (* src = "libresoc.v:200849.18-200849.113" *)
  wire _196_;
  (* src = "libresoc.v:200850.18-200850.125" *)
  wire [4:0] _197_;
  (* src = "libresoc.v:200852.18-200852.112" *)
  wire _198_;
  (* src = "libresoc.v:200854.18-200854.127" *)
  wire _199_;
  (* src = "libresoc.v:200855.18-200855.127" *)
  wire _200_;
  (* src = "libresoc.v:200856.18-200856.117" *)
  wire _201_;
  (* src = "libresoc.v:200861.18-200861.131" *)
  wire _202_;
  (* src = "libresoc.v:200862.18-200862.124" *)
  wire [4:0] _203_;
  (* src = "libresoc.v:200865.18-200865.116" *)
  wire _204_;
  (* src = "libresoc.v:200866.18-200866.120" *)
  wire _205_;
  (* src = "libresoc.v:200867.18-200867.120" *)
  wire _206_;
  (* src = "libresoc.v:200868.18-200868.118" *)
  wire _207_;
  (* src = "libresoc.v:200869.18-200869.118" *)
  wire _208_;
  (* src = "libresoc.v:200875.18-200875.135" *)
  wire _209_;
  (* src = "libresoc.v:200876.18-200876.133" *)
  wire _210_;
  (* src = "libresoc.v:200877.18-200877.160" *)
  wire [3:0] _211_;
  (* src = "libresoc.v:200878.18-200878.112" *)
  wire [3:0] _212_;
  (* src = "libresoc.v:200851.18-200851.113" *)
  wire _213_;
  (* src = "libresoc.v:200853.18-200853.119" *)
  wire _214_;
  (* src = "libresoc.v:200834.18-200834.97" *)
  wire _215_;
  (* src = "libresoc.v:200836.18-200836.99" *)
  wire _216_;
  (* src = "libresoc.v:200839.18-200839.113" *)
  wire [4:0] _217_;
  (* src = "libresoc.v:200842.18-200842.106" *)
  wire _218_;
  (* src = "libresoc.v:200848.18-200848.121" *)
  wire _219_;
  (* src = "libresoc.v:200863.17-200863.113" *)
  wire [3:0] _220_;
  (* src = "libresoc.v:200879.18-200879.114" *)
  wire [3:0] _221_;
  (* src = "libresoc.v:200846.18-200846.112" *)
  wire _222_;
  (* src = "libresoc.v:200857.18-200857.122" *)
  wire _223_;
  (* src = "libresoc.v:200858.18-200858.124" *)
  wire _224_;
  (* src = "libresoc.v:200859.18-200859.181" *)
  wire [4:0] _225_;
  (* src = "libresoc.v:200860.18-200860.168" *)
  wire [3:0] _226_;
  (* src = "libresoc.v:200864.18-200864.120" *)
  wire [4:0] _227_;
  (* src = "libresoc.v:200874.17-200874.117" *)
  wire [3:0] _228_;
  (* src = "libresoc.v:200819.17-200819.104" *)
  wire _229_;
  (* src = "libresoc.v:200841.18-200841.106" *)
  wire _230_;
  (* src = "libresoc.v:200844.18-200844.113" *)
  wire _231_;
  (* src = "libresoc.v:200845.18-200845.112" *)
  wire _232_;
  (* src = "libresoc.v:200870.18-200870.118" *)
  wire [63:0] _233_;
  (* src = "libresoc.v:200871.18-200871.118" *)
  wire [63:0] _234_;
  (* src = "libresoc.v:200872.18-200872.118" *)
  wire [63:0] _235_;
  (* src = "libresoc.v:200873.18-200873.118" *)
  wire [63:0] _236_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [4:0] \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *)
  wire [4:0] \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *)
  wire [4:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [4:0] \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire [4:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$33 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *)
  wire \$37 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *)
  wire \$41 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire [4:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$45 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *)
  wire \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$49 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$53 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
  wire \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *)
  wire \$57 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *)
  wire \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [3:0] \$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *)
  wire [4:0] \$61 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *)
  wire [3:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *)
  wire \$65 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *)
  wire [4:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *)
  wire [4:0] \$69 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *)
  wire [3:0] \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$81 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$83 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$85 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *)
  wire [63:0] \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *)
  wire [3:0] \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" *)
  wire all_rd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg all_rd_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \all_rd_dly$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" *)
  wire all_rd_pulse;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire all_rd_rise;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" *)
  wire alu_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  reg alu_done_dly;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *)
  wire \alu_done_dly$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *)
  wire alu_done_rise;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alu_l_q_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alu_l_r_alu;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alu_l_r_alu$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alu_l_s_alu;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" *)
  wire alu_pulse;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" *)
  wire [4:0] alu_pulsem;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_trap0_fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_trap0_fast1$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_trap0_fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] \alu_trap0_fast2$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_trap0_msr;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" *)
  wire alu_trap0_n_ready_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:252" *)
  wire alu_trap0_n_valid_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_trap0_nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  wire [63:0] alu_trap0_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" *)
  wire alu_trap0_p_ready_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" *)
  wire alu_trap0_p_valid_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_trap0_ra;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" *)
  wire [63:0] alu_trap0_rb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_trap0_trap_op__cia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_trap0_trap_op__cia$next ;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] alu_trap0_trap_op__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [13:0] \alu_trap0_trap_op__fn_unit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] alu_trap0_trap_op__insn;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [31:0] \alu_trap0_trap_op__insn$next ;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] alu_trap0_trap_op__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [6:0] \alu_trap0_trap_op__insn_type$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg alu_trap0_trap_op__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg \alu_trap0_trap_op__is_32bit$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] alu_trap0_trap_op__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \alu_trap0_trap_op__ldst_exc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] alu_trap0_trap_op__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [63:0] \alu_trap0_trap_op__msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [12:0] alu_trap0_trap_op__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [12:0] \alu_trap0_trap_op__trapaddr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] alu_trap0_trap_op__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  reg [7:0] \alu_trap0_trap_op__traptype$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire alui_l_q_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg alui_l_r_alui;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \alui_l_r_alui$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  wire alui_l_s_alui;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *)
  output cu_busy_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" *)
  wire cu_done_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" *)
  wire cu_go_die_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" *)
  input cu_issue_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [3:0] cu_rd__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [3:0] cu_rd__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" *)
  input [3:0] cu_rdmaskn_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" *)
  wire cu_shadown_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  input [4:0] cu_wr__go_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *)
  output [4:0] cu_wr__rel_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" *)
  wire [4:0] cu_wrmask_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r0__o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r0__o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r0__o_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r0__o_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r1__fast1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r1__fast1$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r1__fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r1__fast1_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r2__fast2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r2__fast2$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r2__fast2_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r2__fast2_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r3__nia;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r3__nia$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r3__nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r3__nia_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] data_r4__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg [63:0] \data_r4__msr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg data_r4__msr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" *)
  reg \data_r4__msr_ok$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest1_o;
  reg [63:0] dest1_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest2_o;
  reg [63:0] dest2_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest3_o;
  reg [63:0] dest3_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest4_o;
  reg [63:0] dest4_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" *)
  output [63:0] dest5_o;
  reg [63:0] dest5_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast1_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output fast2_ok;
  (* src = "libresoc.v:200219.7-200219.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output msr_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output nia_ok;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:19" *)
  output o_ok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire opc_l_q_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg opc_l_r_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \opc_l_r_opc$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg opc_l_s_opc;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \opc_l_s_opc$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_trap0__cia;
  (* enum_base_type = "Function" *)
  (* enum_value_00000000000000 = "NONE" *)
  (* enum_value_00000000000010 = "ALU" *)
  (* enum_value_00000000000100 = "LDST" *)
  (* enum_value_00000000001000 = "SHIFT_ROT" *)
  (* enum_value_00000000010000 = "LOGICAL" *)
  (* enum_value_00000000100000 = "BRANCH" *)
  (* enum_value_00000001000000 = "CR" *)
  (* enum_value_00000010000000 = "TRAP" *)
  (* enum_value_00000100000000 = "MUL" *)
  (* enum_value_00001000000000 = "DIV" *)
  (* enum_value_00010000000000 = "SPR" *)
  (* enum_value_00100000000000 = "MMU" *)
  (* enum_value_01000000000000 = "SV" *)
  (* enum_value_10000000000000 = "VL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [13:0] oper_i_alu_trap0__fn_unit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [31:0] oper_i_alu_trap0__insn;
  (* enum_base_type = "MicrOp" *)
  (* enum_value_0000000 = "OP_ILLEGAL" *)
  (* enum_value_0000001 = "OP_NOP" *)
  (* enum_value_0000010 = "OP_ADD" *)
  (* enum_value_0000011 = "OP_ADDPCIS" *)
  (* enum_value_0000100 = "OP_AND" *)
  (* enum_value_0000101 = "OP_ATTN" *)
  (* enum_value_0000110 = "OP_B" *)
  (* enum_value_0000111 = "OP_BC" *)
  (* enum_value_0001000 = "OP_BCREG" *)
  (* enum_value_0001001 = "OP_BPERM" *)
  (* enum_value_0001010 = "OP_CMP" *)
  (* enum_value_0001011 = "OP_CMPB" *)
  (* enum_value_0001100 = "OP_CMPEQB" *)
  (* enum_value_0001101 = "OP_CMPRB" *)
  (* enum_value_0001110 = "OP_CNTZ" *)
  (* enum_value_0001111 = "OP_CRAND" *)
  (* enum_value_0010000 = "OP_CRANDC" *)
  (* enum_value_0010001 = "OP_CREQV" *)
  (* enum_value_0010010 = "OP_CRNAND" *)
  (* enum_value_0010011 = "OP_CRNOR" *)
  (* enum_value_0010100 = "OP_CROR" *)
  (* enum_value_0010101 = "OP_CRORC" *)
  (* enum_value_0010110 = "OP_CRXOR" *)
  (* enum_value_0010111 = "OP_DARN" *)
  (* enum_value_0011000 = "OP_DCBF" *)
  (* enum_value_0011001 = "OP_DCBST" *)
  (* enum_value_0011010 = "OP_DCBT" *)
  (* enum_value_0011011 = "OP_DCBTST" *)
  (* enum_value_0011100 = "OP_DCBZ" *)
  (* enum_value_0011101 = "OP_DIV" *)
  (* enum_value_0011110 = "OP_DIVE" *)
  (* enum_value_0011111 = "OP_EXTS" *)
  (* enum_value_0100000 = "OP_EXTSWSLI" *)
  (* enum_value_0100001 = "OP_ICBI" *)
  (* enum_value_0100010 = "OP_ICBT" *)
  (* enum_value_0100011 = "OP_ISEL" *)
  (* enum_value_0100100 = "OP_ISYNC" *)
  (* enum_value_0100101 = "OP_LOAD" *)
  (* enum_value_0100110 = "OP_STORE" *)
  (* enum_value_0100111 = "OP_MADDHD" *)
  (* enum_value_0101000 = "OP_MADDHDU" *)
  (* enum_value_0101001 = "OP_MADDLD" *)
  (* enum_value_0101010 = "OP_MCRF" *)
  (* enum_value_0101011 = "OP_MCRXR" *)
  (* enum_value_0101100 = "OP_MCRXRX" *)
  (* enum_value_0101101 = "OP_MFCR" *)
  (* enum_value_0101110 = "OP_MFSPR" *)
  (* enum_value_0101111 = "OP_MOD" *)
  (* enum_value_0110000 = "OP_MTCRF" *)
  (* enum_value_0110001 = "OP_MTSPR" *)
  (* enum_value_0110010 = "OP_MUL_L64" *)
  (* enum_value_0110011 = "OP_MUL_H64" *)
  (* enum_value_0110100 = "OP_MUL_H32" *)
  (* enum_value_0110101 = "OP_OR" *)
  (* enum_value_0110110 = "OP_POPCNT" *)
  (* enum_value_0110111 = "OP_PRTY" *)
  (* enum_value_0111000 = "OP_RLC" *)
  (* enum_value_0111001 = "OP_RLCL" *)
  (* enum_value_0111010 = "OP_RLCR" *)
  (* enum_value_0111011 = "OP_SETB" *)
  (* enum_value_0111100 = "OP_SHL" *)
  (* enum_value_0111101 = "OP_SHR" *)
  (* enum_value_0111110 = "OP_SYNC" *)
  (* enum_value_0111111 = "OP_TRAP" *)
  (* enum_value_1000011 = "OP_XOR" *)
  (* enum_value_1000100 = "OP_SIM_CONFIG" *)
  (* enum_value_1000101 = "OP_CROP" *)
  (* enum_value_1000110 = "OP_RFID" *)
  (* enum_value_1000111 = "OP_MFMSR" *)
  (* enum_value_1001000 = "OP_MTMSRD" *)
  (* enum_value_1001001 = "OP_SC" *)
  (* enum_value_1001010 = "OP_MTMSR" *)
  (* enum_value_1001011 = "OP_TLBIE" *)
  (* enum_value_1001100 = "OP_SETVL" *)
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [6:0] oper_i_alu_trap0__insn_type;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input oper_i_alu_trap0__is_32bit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] oper_i_alu_trap0__ldst_exc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [63:0] oper_i_alu_trap0__msr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [12:0] oper_i_alu_trap0__trapaddr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" *)
  input [7:0] oper_i_alu_trap0__traptype;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [4:0] prev_wr_go;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" *)
  reg [4:0] \prev_wr_go$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" *)
  reg req_done;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [4:0] req_l_q_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] req_l_r_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [4:0] \req_l_r_req$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] req_l_s_req;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [4:0] \req_l_s_req$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" *)
  wire reset;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" *)
  wire [3:0] reset_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" *)
  wire [4:0] reset_w;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire rok_l_q_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rok_l_r_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rok_l_r_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rok_l_s_rdok;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rok_l_s_rdok$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg rst_l_r_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg \rst_l_r_rst$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg rst_l_s_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg \rst_l_s_rst$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" *)
  wire rst_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src1_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src2_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src3_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" *)
  input [63:0] src4_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  wire [3:0] src_l_q_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] src_l_r_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  reg [3:0] \src_l_r_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] src_l_s_src;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  reg [3:0] \src_l_s_src$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r0$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r1$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r2$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] src_r3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *)
  reg [63:0] \src_r3$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" *)
  wire wr_any;
  assign _176_ = \$95  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) \$97 ;
  assign _177_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _178_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _179_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _180_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _181_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" *) cu_shadown_i;
  assign _182_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) { \$101 , \$103 , \$105 , \$107 , \$109  };
  assign _183_ = \$111  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" *) cu_wrmask_o;
  assign _184_ = cu_wr__go_i[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _185_ = cu_wr__go_i[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _186_ = \$3  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$5 ;
  assign _187_ = cu_wr__go_i[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _188_ = cu_wr__go_i[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _189_ = cu_wr__go_i[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *) cu_busy_o;
  assign _190_ = all_rd & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$13 ;
  assign _191_ = alu_done & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$17 ;
  assign _192_ = cu_wr__go_i & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _193_ = cu_wr__rel_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$25 ;
  assign _194_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$23 ;
  assign _195_ = cu_busy_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" *) rok_l_q_rdok;
  assign _196_ = wr_any & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) \$39 ;
  assign _197_ = req_l_q_req & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) cu_wrmask_o;
  assign _198_ = \$41  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) \$45 ;
  assign _199_ = \$49  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_ready_i;
  assign _200_ = \$51  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) alu_trap0_n_valid_o;
  assign _201_ = \$53  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) cu_busy_o;
  assign _202_ = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" *) cu_busy_o;
  assign _203_ = alu_pulsem & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" *) cu_wrmask_o;
  assign _204_ = o_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _205_ = fast1_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _206_ = fast2_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _207_ = nia_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _208_ = msr_ok & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" *) cu_busy_o;
  assign _209_ = alu_trap0_p_ready_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" *) alui_l_q_alui;
  assign _210_ = alu_trap0_n_valid_o & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" *) alu_l_q_alu;
  assign _211_ = src_l_q_src & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) { cu_busy_o, cu_busy_o, cu_busy_o, cu_busy_o };
  assign _212_ = \$93  & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) 4'hf;
  assign _213_ = \$43  == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" *) 1'h0;
  assign _214_ = cu_wrmask_o == (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *) 1'h0;
  assign _215_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) all_rd_dly;
  assign _216_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) alu_done_dly;
  assign _217_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) cu_wrmask_o;
  assign _218_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$24 ;
  assign _219_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" *) alu_trap0_n_ready_i;
  assign _220_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__rel_o;
  assign _221_ = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" *) cu_rdmaskn_i;
  assign _222_ = \$33  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) \$35 ;
  assign _223_ = req_done | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" *) cu_go_die_i;
  assign _224_ = cu_issue_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" *) cu_go_die_i;
  assign _225_ = cu_wr__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _226_ = cu_rd__go_i | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" *) { cu_go_die_i, cu_go_die_i, cu_go_die_i, cu_go_die_i };
  assign _227_ = reset_w | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" *) prev_wr_go;
  assign _228_ = \$6  | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) cu_rd__go_i;
  assign _229_ = & (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" *) \$8 ;
  assign _230_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" *) \$27 ;
  assign _231_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) cu_wr__go_i;
  assign _232_ = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" *) prev_wr_go;
  assign _233_ = src_l_q_src[0] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src1_i : src_r0;
  assign _234_ = src_l_q_src[1] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src2_i : src_r1;
  assign _235_ = src_l_q_src[2] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src3_i : src_r2;
  assign _236_ = src_l_q_src[3] ? (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" *) src4_i : src_r3;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:200956.14-200962.4" *)
  \alu_l$45  alu_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alu(alu_l_q_alu),
    .r_alu(alu_l_r_alu),
    .s_alu(alu_l_s_alu)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:200963.13-200993.4" *)
  alu_trap0 alu_trap0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .fast1(alu_trap0_fast1),
    .\fast1$1 (\alu_trap0_fast1$1 ),
    .fast1_ok(fast1_ok),
    .fast2(alu_trap0_fast2),
    .\fast2$2 (\alu_trap0_fast2$2 ),
    .fast2_ok(fast2_ok),
    .msr(alu_trap0_msr),
    .msr_ok(msr_ok),
    .n_ready_i(alu_trap0_n_ready_i),
    .n_valid_o(alu_trap0_n_valid_o),
    .nia(alu_trap0_nia),
    .nia_ok(nia_ok),
    .o(alu_trap0_o),
    .o_ok(o_ok),
    .p_ready_o(alu_trap0_p_ready_o),
    .p_valid_i(alu_trap0_p_valid_i),
    .ra(alu_trap0_ra),
    .rb(alu_trap0_rb),
    .trap_op__cia(alu_trap0_trap_op__cia),
    .trap_op__fn_unit(alu_trap0_trap_op__fn_unit),
    .trap_op__insn(alu_trap0_trap_op__insn),
    .trap_op__insn_type(alu_trap0_trap_op__insn_type),
    .trap_op__is_32bit(alu_trap0_trap_op__is_32bit),
    .trap_op__ldst_exc(alu_trap0_trap_op__ldst_exc),
    .trap_op__msr(alu_trap0_trap_op__msr),
    .trap_op__trapaddr(alu_trap0_trap_op__trapaddr),
    .trap_op__traptype(alu_trap0_trap_op__traptype)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:200994.15-201000.4" *)
  \alui_l$44  alui_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_alui(alui_l_q_alui),
    .r_alui(alui_l_r_alui),
    .s_alui(alui_l_s_alui)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:201001.14-201007.4" *)
  \opc_l$40  opc_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_opc(opc_l_q_opc),
    .r_opc(opc_l_r_opc),
    .s_opc(opc_l_s_opc)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:201008.14-201014.4" *)
  \req_l$41  req_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_req(req_l_q_req),
    .r_req(req_l_r_req),
    .s_req(req_l_s_req)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:201015.14-201021.4" *)
  \rok_l$43  rok_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_rdok(rok_l_q_rdok),
    .r_rdok(rok_l_r_rdok),
    .s_rdok(rok_l_s_rdok)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:201022.14-201027.4" *)
  \rst_l$42  rst_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .r_rst(rst_l_r_rst),
    .s_rst(rst_l_s_rst)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:201028.14-201034.4" *)
  \src_l$39  src_l (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .q_src(src_l_q_src),
    .r_src(src_l_r_src),
    .s_src(src_l_s_src)
  );
  always @* begin
    if (\initial ) begin end
    _049_ = 1'h0;
  end
  always @* begin
      \initial  <= _049_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _081_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      all_rd_dly <= _081_;
  end
  always @* begin
    if (\initial ) begin end
    _082_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_done_dly <= _082_;
  end
  always @* begin
    if (\initial ) begin end
    _084_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alu_l_r_alu <= _084_;
  end
  always @* begin
    if (\initial ) begin end
    _086_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__cia <= _086_;
  end
  always @* begin
    if (\initial ) begin end
    _088_ = 14'h0000;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__fn_unit <= _088_;
  end
  always @* begin
    if (\initial ) begin end
    _090_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__insn <= _090_;
  end
  always @* begin
    if (\initial ) begin end
    _092_ = 7'h00;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__insn_type <= _092_;
  end
  always @* begin
    if (\initial ) begin end
    _094_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__is_32bit <= _094_;
  end
  always @* begin
    if (\initial ) begin end
    _096_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__ldst_exc <= _096_;
  end
  always @* begin
    if (\initial ) begin end
    _098_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__msr <= _098_;
  end
  always @* begin
    if (\initial ) begin end
    _100_ = 13'h0000;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__trapaddr <= _100_;
  end
  always @* begin
    if (\initial ) begin end
    _102_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      alu_trap0_trap_op__traptype <= _102_;
  end
  always @* begin
    if (\initial ) begin end
    _104_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      alui_l_r_alui <= _104_;
  end
  always @* begin
    if (\initial ) begin end
    _106_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r0__o <= _106_;
  end
  always @* begin
    if (\initial ) begin end
    _108_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r0__o_ok <= _108_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r1__fast1 <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r1__fast1_ok <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r2__fast2 <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r2__fast2_ok <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r3__nia <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r3__nia_ok <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      data_r4__msr <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      data_r4__msr_ok <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _131_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      opc_l_r_opc <= _131_;
  end
  always @* begin
    if (\initial ) begin end
    _133_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      opc_l_s_opc <= _133_;
  end
  always @* begin
    if (\initial ) begin end
    _135_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      prev_wr_go <= _135_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 5'h1f;
  end
  always @* begin
  end
  initial begin
      req_l_r_req <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 5'h00;
  end
  always @* begin
  end
  initial begin
      req_l_s_req <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rok_l_r_rdok <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rok_l_s_rdok <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 1'h1;
  end
  always @* begin
  end
  initial begin
      rst_l_r_rst <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      rst_l_s_rst <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _150_ = 4'hf;
  end
  always @* begin
  end
  initial begin
      src_l_r_src <= _150_;
  end
  always @* begin
    if (\initial ) begin end
    _152_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      src_l_s_src <= _152_;
  end
  always @* begin
    if (\initial ) begin end
    _154_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r0 <= _154_;
  end
  always @* begin
    if (\initial ) begin end
    _156_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r1 <= _156_;
  end
  always @* begin
    if (\initial ) begin end
    _158_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r2 <= _158_;
  end
  always @* begin
    if (\initial ) begin end
    _160_ = 64'h0000000000000000;
  end
  always @* begin
  end
  initial begin
      src_r3 <= _160_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = \alu_l_r_alu$next ;
  end
  always @(posedge coresync_clk) begin
      alu_l_r_alu <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = \alui_l_r_alui$next ;
  end
  always @(posedge coresync_clk) begin
      alui_l_r_alui <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _080_ = \src_r3$next ;
  end
  always @(posedge coresync_clk) begin
      src_r3 <= _080_;
  end
  always @* begin
    if (\initial ) begin end
    _078_ = \src_r2$next ;
  end
  always @(posedge coresync_clk) begin
      src_r2 <= _078_;
  end
  always @* begin
    if (\initial ) begin end
    _076_ = \src_r1$next ;
  end
  always @(posedge coresync_clk) begin
      src_r1 <= _076_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \src_r0$next ;
  end
  always @(posedge coresync_clk) begin
      src_r0 <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = \data_r4__msr$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__msr <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = \data_r4__msr_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r4__msr_ok <= _043_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \data_r3__nia$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__nia <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \data_r3__nia_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r3__nia_ok <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = \data_r2__fast2$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__fast2 <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = \data_r2__fast2_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r2__fast2_ok <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = \data_r1__fast1$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__fast1 <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = \data_r1__fast1_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r1__fast1_ok <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = \data_r0__o$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = \data_r0__o_ok$next ;
  end
  always @(posedge coresync_clk) begin
      data_r0__o_ok <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = \alu_trap0_trap_op__insn_type$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__insn_type <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = \alu_trap0_trap_op__fn_unit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__fn_unit <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = \alu_trap0_trap_op__insn$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__insn <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = \alu_trap0_trap_op__msr$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__msr <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = \alu_trap0_trap_op__cia$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__cia <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = \alu_trap0_trap_op__is_32bit$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__is_32bit <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = \alu_trap0_trap_op__traptype$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__traptype <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = \alu_trap0_trap_op__trapaddr$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__trapaddr <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = \alu_trap0_trap_op__ldst_exc$next ;
  end
  always @(posedge coresync_clk) begin
      alu_trap0_trap_op__ldst_exc <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \req_l_r_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_r_req <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \req_l_s_req$next ;
  end
  always @(posedge coresync_clk) begin
      req_l_s_req <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \src_l_r_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_r_src <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \src_l_s_src$next ;
  end
  always @(posedge coresync_clk) begin
      src_l_s_src <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _051_ = \opc_l_r_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_r_opc <= _051_;
  end
  always @* begin
    if (\initial ) begin end
    _053_ = \opc_l_s_opc$next ;
  end
  always @(posedge coresync_clk) begin
      opc_l_s_opc <= _053_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \rst_l_r_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_r_rst <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \rst_l_s_rst$next ;
  end
  always @(posedge coresync_clk) begin
      rst_l_s_rst <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \rok_l_r_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_r_rdok <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \rok_l_s_rdok$next ;
  end
  always @(posedge coresync_clk) begin
      rok_l_s_rdok <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _055_ = \prev_wr_go$next ;
  end
  always @(posedge coresync_clk) begin
      prev_wr_go <= _055_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = alu_trap0_n_valid_o;
  end
  always @(posedge coresync_clk) begin
      alu_done_dly <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = \$11 ;
  end
  always @(posedge coresync_clk) begin
      all_rd_dly <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = _136_;
    (* src = "libresoc.v:201036.5-201036.29" *)
    casez (\initial )
      /* src = "libresoc.v:201036.9-201036.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" *)
    casez (\$55 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _136_ = 1'h1;
        end
      default:
          _136_ = \$47 ;
    endcase
  end
  always @* begin
      req_done <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _063_ = _143_;
    (* src = "libresoc.v:201046.5-201046.29" *)
    casez (\initial )
      /* src = "libresoc.v:201046.9-201046.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _143_ = 1'h0;
        end
      default:
          _143_ = cu_issue_i;
    endcase
  end
  always @* begin
      \rok_l_s_rdok$next  <= _063_;
  end
  always @* begin
    if (\initial ) begin end
    _061_ = _141_;
    (* src = "libresoc.v:201055.5-201055.29" *)
    casez (\initial )
      /* src = "libresoc.v:201055.9-201055.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _141_ = 1'h1;
        end
      default:
          _141_ = \$65 ;
    endcase
  end
  always @* begin
      \rok_l_r_rdok$next  <= _061_;
  end
  always @* begin
    if (\initial ) begin end
    _067_ = _147_;
    (* src = "libresoc.v:201064.5-201064.29" *)
    casez (\initial )
      /* src = "libresoc.v:201064.9-201064.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _147_ = 1'h0;
        end
      default:
          _147_ = all_rd;
    endcase
  end
  always @* begin
      \rst_l_s_rst$next  <= _067_;
  end
  always @* begin
    if (\initial ) begin end
    _065_ = _145_;
    (* src = "libresoc.v:201073.5-201073.29" *)
    casez (\initial )
      /* src = "libresoc.v:201073.9-201073.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _145_ = 1'h1;
        end
      default:
          _145_ = rst_r;
    endcase
  end
  always @* begin
      \rst_l_r_rst$next  <= _065_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = _132_;
    (* src = "libresoc.v:201082.5-201082.29" *)
    casez (\initial )
      /* src = "libresoc.v:201082.9-201082.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _132_ = 1'h0;
        end
      default:
          _132_ = cu_issue_i;
    endcase
  end
  always @* begin
      \opc_l_s_opc$next  <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = _130_;
    (* src = "libresoc.v:201091.5-201091.29" *)
    casez (\initial )
      /* src = "libresoc.v:201091.9-201091.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _130_ = 1'h1;
        end
      default:
          _130_ = req_done;
    endcase
  end
  always @* begin
      \opc_l_r_opc$next  <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _071_ = _151_;
    (* src = "libresoc.v:201100.5-201100.29" *)
    casez (\initial )
      /* src = "libresoc.v:201100.9-201100.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _151_ = 4'h0;
        end
      default:
          _151_ = { cu_issue_i, cu_issue_i, cu_issue_i, cu_issue_i };
    endcase
  end
  always @* begin
      \src_l_s_src$next  <= _071_;
  end
  always @* begin
    if (\initial ) begin end
    _069_ = _149_;
    (* src = "libresoc.v:201109.5-201109.29" *)
    casez (\initial )
      /* src = "libresoc.v:201109.9-201109.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _149_ = 4'hf;
        end
      default:
          _149_ = reset_r;
    endcase
  end
  always @* begin
      \src_l_r_src$next  <= _069_;
  end
  always @* begin
    if (\initial ) begin end
    _059_ = _139_;
    (* src = "libresoc.v:201118.5-201118.29" *)
    casez (\initial )
      /* src = "libresoc.v:201118.9-201118.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _139_ = 5'h00;
        end
      default:
          _139_ = \$67 ;
    endcase
  end
  always @* begin
      \req_l_s_req$next  <= _059_;
  end
  always @* begin
    if (\initial ) begin end
    _057_ = _137_;
    (* src = "libresoc.v:201127.5-201127.29" *)
    casez (\initial )
      /* src = "libresoc.v:201127.9-201127.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _137_ = 5'h1f;
        end
      default:
          _137_ = \$69 ;
    endcase
  end
  always @* begin
      \req_l_r_req$next  <= _057_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _085_;
    _006_ = _087_;
    _008_ = _089_;
    _010_ = _091_;
    _012_ = _093_;
    _014_ = _095_;
    _016_ = _097_;
    _018_ = _099_;
    _020_ = _101_;
    (* src = "libresoc.v:201136.5-201136.29" *)
    casez (\initial )
      /* src = "libresoc.v:201136.9-201136.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _095_, _099_, _101_, _093_, _085_, _097_, _089_, _087_, _091_ } = { oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__traptype, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__cia, oper_i_alu_trap0__msr, oper_i_alu_trap0__insn, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn_type };
        end
      default:
        begin
          _085_ = alu_trap0_trap_op__cia;
          _087_ = alu_trap0_trap_op__fn_unit;
          _089_ = alu_trap0_trap_op__insn;
          _091_ = alu_trap0_trap_op__insn_type;
          _093_ = alu_trap0_trap_op__is_32bit;
          _095_ = alu_trap0_trap_op__ldst_exc;
          _097_ = alu_trap0_trap_op__msr;
          _099_ = alu_trap0_trap_op__trapaddr;
          _101_ = alu_trap0_trap_op__traptype;
        end
    endcase
  end
  always @* begin
      \alu_trap0_trap_op__cia$next  <= _004_;
      \alu_trap0_trap_op__fn_unit$next  <= _006_;
      \alu_trap0_trap_op__insn$next  <= _008_;
      \alu_trap0_trap_op__insn_type$next  <= _010_;
      \alu_trap0_trap_op__is_32bit$next  <= _012_;
      \alu_trap0_trap_op__ldst_exc$next  <= _014_;
      \alu_trap0_trap_op__msr$next  <= _016_;
      \alu_trap0_trap_op__trapaddr$next  <= _018_;
      \alu_trap0_trap_op__traptype$next  <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _161_;
    _026_ = _171_;
    (* src = "libresoc.v:201154.5-201154.29" *)
    casez (\initial )
      /* src = "libresoc.v:201154.9-201154.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _107_, _105_ } = { o_ok, alu_trap0_o };
        end
      default:
        begin
          _105_ = data_r0__o;
          _107_ = data_r0__o_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _162_, _161_ } = 65'h00000000000000000;
        end
      default:
        begin
          _161_ = _105_;
          _162_ = _107_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _171_ = 1'h0;
        end
      default:
          _171_ = _162_;
    endcase
  end
  always @* begin
      \data_r0__o$next  <= _024_;
      \data_r0__o_ok$next  <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _163_;
    _030_ = _172_;
    (* src = "libresoc.v:201176.5-201176.29" *)
    casez (\initial )
      /* src = "libresoc.v:201176.9-201176.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _111_, _109_ } = { fast1_ok, alu_trap0_fast1 };
        end
      default:
        begin
          _109_ = data_r1__fast1;
          _111_ = data_r1__fast1_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _164_, _163_ } = 65'h00000000000000000;
        end
      default:
        begin
          _163_ = _109_;
          _164_ = _111_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _172_ = 1'h0;
        end
      default:
          _172_ = _164_;
    endcase
  end
  always @* begin
      \data_r1__fast1$next  <= _028_;
      \data_r1__fast1_ok$next  <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _165_;
    _034_ = _173_;
    (* src = "libresoc.v:201198.5-201198.29" *)
    casez (\initial )
      /* src = "libresoc.v:201198.9-201198.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _115_, _113_ } = { fast2_ok, alu_trap0_fast2 };
        end
      default:
        begin
          _113_ = data_r2__fast2;
          _115_ = data_r2__fast2_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _166_, _165_ } = 65'h00000000000000000;
        end
      default:
        begin
          _165_ = _113_;
          _166_ = _115_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _173_ = 1'h0;
        end
      default:
          _173_ = _166_;
    endcase
  end
  always @* begin
      \data_r2__fast2$next  <= _032_;
      \data_r2__fast2_ok$next  <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _167_;
    _038_ = _174_;
    (* src = "libresoc.v:201220.5-201220.29" *)
    casez (\initial )
      /* src = "libresoc.v:201220.9-201220.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _119_, _117_ } = { nia_ok, alu_trap0_nia };
        end
      default:
        begin
          _117_ = data_r3__nia;
          _119_ = data_r3__nia_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _168_, _167_ } = 65'h00000000000000000;
        end
      default:
        begin
          _167_ = _117_;
          _168_ = _119_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _174_ = 1'h0;
        end
      default:
          _174_ = _168_;
    endcase
  end
  always @* begin
      \data_r3__nia$next  <= _036_;
      \data_r3__nia_ok$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _040_ = _169_;
    _042_ = _175_;
    (* src = "libresoc.v:201242.5-201242.29" *)
    casez (\initial )
      /* src = "libresoc.v:201242.9-201242.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" *)
    casez (alu_pulse)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _123_, _121_ } = { msr_ok, alu_trap0_msr };
        end
      default:
        begin
          _121_ = data_r4__msr;
          _123_ = data_r4__msr_ok;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" *)
    casez (cu_issue_i)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          { _170_, _169_ } = 65'h00000000000000000;
        end
      default:
        begin
          _169_ = _121_;
          _170_ = _123_;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _175_ = 1'h0;
        end
      default:
          _175_ = _170_;
    endcase
  end
  always @* begin
      \data_r4__msr$next  <= _040_;
      \data_r4__msr_ok$next  <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _073_ = _153_;
    (* src = "libresoc.v:201264.5-201264.29" *)
    casez (\initial )
      /* src = "libresoc.v:201264.9-201264.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[0])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _153_ = src1_i;
        end
      default:
          _153_ = src_r0;
    endcase
  end
  always @* begin
      \src_r0$next  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _075_ = _155_;
    (* src = "libresoc.v:201274.5-201274.29" *)
    casez (\initial )
      /* src = "libresoc.v:201274.9-201274.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[1])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _155_ = src2_i;
        end
      default:
          _155_ = src_r1;
    endcase
  end
  always @* begin
      \src_r1$next  <= _075_;
  end
  always @* begin
    if (\initial ) begin end
    _077_ = _157_;
    (* src = "libresoc.v:201284.5-201284.29" *)
    casez (\initial )
      /* src = "libresoc.v:201284.9-201284.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[2])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _157_ = src3_i;
        end
      default:
          _157_ = src_r2;
    endcase
  end
  always @* begin
      \src_r2$next  <= _077_;
  end
  always @* begin
    if (\initial ) begin end
    _079_ = _159_;
    (* src = "libresoc.v:201294.5-201294.29" *)
    casez (\initial )
      /* src = "libresoc.v:201294.9-201294.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:48" *)
    casez (src_l_q_src[3])
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _159_ = src4_i;
        end
      default:
          _159_ = src_r3;
    endcase
  end
  always @* begin
      \src_r3$next  <= _079_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _103_;
    (* src = "libresoc.v:201304.5-201304.29" *)
    casez (\initial )
      /* src = "libresoc.v:201304.9-201304.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = 1'h1;
        end
      default:
          _103_ = \$89 ;
    endcase
  end
  always @* begin
      \alui_l_r_alui$next  <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _083_;
    (* src = "libresoc.v:201313.5-201313.29" *)
    casez (\initial )
      /* src = "libresoc.v:201313.9-201313.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _083_ = 1'h1;
        end
      default:
          _083_ = \$91 ;
    endcase
  end
  always @* begin
      \alu_l_r_alu$next  <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = _125_;
    (* src = "libresoc.v:201322.5-201322.29" *)
    casez (\initial )
      /* src = "libresoc.v:201322.9-201322.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$115 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _125_ = data_r0__o;
        end
      default:
          _125_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest1_o <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _045_ = _126_;
    (* src = "libresoc.v:201332.5-201332.29" *)
    casez (\initial )
      /* src = "libresoc.v:201332.9-201332.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$117 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _126_ = data_r1__fast1;
        end
      default:
          _126_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest2_o <= _045_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = _127_;
    (* src = "libresoc.v:201342.5-201342.29" *)
    casez (\initial )
      /* src = "libresoc.v:201342.9-201342.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$119 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _127_ = data_r2__fast2;
        end
      default:
          _127_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest3_o <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _047_ = _128_;
    (* src = "libresoc.v:201352.5-201352.29" *)
    casez (\initial )
      /* src = "libresoc.v:201352.9-201352.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$121 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _128_ = data_r3__nia;
        end
      default:
          _128_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest4_o <= _047_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = _129_;
    (* src = "libresoc.v:201362.5-201362.29" *)
    casez (\initial )
      /* src = "libresoc.v:201362.9-201362.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" *)
    casez (\$123 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _129_ = data_r4__msr;
        end
      default:
          _129_ = 64'h0000000000000000;
    endcase
  end
  always @* begin
      dest5_o <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = _134_;
    (* src = "libresoc.v:201372.5-201372.29" *)
    casez (\initial )
      /* src = "libresoc.v:201372.9-201372.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _134_ = 5'h00;
        end
      default:
          _134_ = \$21 ;
    endcase
  end
  always @* begin
      \prev_wr_go$next  <= _054_;
  end
  assign \$5  = _229_;
  assign \$99  = _176_;
  assign \$101  = _177_;
  assign \$103  = _178_;
  assign \$105  = _179_;
  assign \$107  = _180_;
  assign \$109  = _181_;
  assign \$111  = _182_;
  assign \$113  = _183_;
  assign \$115  = _184_;
  assign \$117  = _185_;
  assign \$11  = _186_;
  assign \$119  = _187_;
  assign \$121  = _188_;
  assign \$123  = _189_;
  assign \$13  = _215_;
  assign \$15  = _190_;
  assign \$17  = _216_;
  assign \$19  = _191_;
  assign \$21  = _192_;
  assign \$25  = _217_;
  assign \$27  = _193_;
  assign \$24  = _230_;
  assign \$23  = _218_;
  assign \$31  = _194_;
  assign \$33  = _231_;
  assign \$35  = _232_;
  assign \$37  = _222_;
  assign \$3  = _195_;
  assign \$39  = _219_;
  assign \$41  = _196_;
  assign \$43  = _197_;
  assign \$45  = _213_;
  assign \$47  = _198_;
  assign \$49  = _214_;
  assign \$51  = _199_;
  assign \$53  = _200_;
  assign \$55  = _201_;
  assign \$57  = _223_;
  assign \$59  = _224_;
  assign \$61  = _225_;
  assign \$63  = _226_;
  assign \$65  = _202_;
  assign \$67  = _203_;
  assign \$6  = _220_;
  assign \$69  = _227_;
  assign \$71  = _204_;
  assign \$73  = _205_;
  assign \$75  = _206_;
  assign \$77  = _207_;
  assign \$79  = _208_;
  assign \$81  = _233_;
  assign \$83  = _234_;
  assign \$85  = _235_;
  assign \$87  = _236_;
  assign \$8  = _228_;
  assign \$89  = _209_;
  assign \$91  = _210_;
  assign \$93  = _211_;
  assign \$95  = _212_;
  assign \$97  = _221_;
  assign cu_go_die_i = 1'h0;
  assign cu_shadown_i = 1'h1;
  assign cu_wr__rel_o = \$113 ;
  assign cu_rd__rel_o = \$99 ;
  assign cu_busy_o = opc_l_q_opc;
  assign alu_l_s_alu = all_rd_pulse;
  assign alu_trap0_n_ready_i = alu_l_q_alu;
  assign alui_l_s_alui = all_rd_pulse;
  assign alu_trap0_p_valid_i = alui_l_q_alui;
  assign \alu_trap0_fast2$2  = \$87 ;
  assign \alu_trap0_fast1$1  = \$85 ;
  assign alu_trap0_rb = \$83 ;
  assign alu_trap0_ra = \$81 ;
  assign cu_wrmask_o = { \$79 , \$77 , \$75 , \$73 , \$71  };
  assign reset_r = \$63 ;
  assign reset_w = \$61 ;
  assign rst_r = \$59 ;
  assign reset = \$57 ;
  assign wr_any = \$37 ;
  assign cu_done_o = \$31 ;
  assign alu_pulsem = { alu_pulse, alu_pulse, alu_pulse, alu_pulse, alu_pulse };
  assign alu_pulse = alu_done_rise;
  assign alu_done_rise = \$19 ;
  assign \alu_done_dly$next  = alu_done;
  assign alu_done = alu_trap0_n_valid_o;
  assign all_rd_pulse = all_rd_rise;
  assign all_rd_rise = \$15 ;
  assign \all_rd_dly$next  = all_rd;
  assign all_rd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.upd_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201413.1-201471.10" *)
module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:201414.7-201414.20" *)
  reg _00_;
  (* src = "libresoc.v:201459.3-201467.6" *)
  reg _01_;
  (* src = "libresoc.v:201457.3-201458.27" *)
  reg _02_;
  (* src = "libresoc.v:201459.3-201467.6" *)
  reg _03_;
  (* src = "libresoc.v:201436.7-201436.19" *)
  reg _04_;
  (* src = "libresoc.v:201449.17-201449.96" *)
  wire _05_;
  (* src = "libresoc.v:201454.17-201454.96" *)
  wire _06_;
  (* src = "libresoc.v:201451.18-201451.93" *)
  wire _07_;
  (* src = "libresoc.v:201453.17-201453.92" *)
  wire _08_;
  (* src = "libresoc.v:201456.17-201456.92" *)
  wire _09_;
  (* src = "libresoc.v:201450.18-201450.98" *)
  wire _10_;
  (* src = "libresoc.v:201452.18-201452.99" *)
  wire _11_;
  (* src = "libresoc.v:201455.17-201455.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:201414.7-201414.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_upd;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_upd;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_upd;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_upd;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_upd;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_upd;
  assign _11_ = q_upd | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_upd;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:201460.5-201460.29" *)
    casez (\initial )
      /* src = "libresoc.v:201460.9-201460.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_upd = \$15 ;
  assign qn_upd = \$13 ;
  assign q_upd = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.l0.pimem.valid_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201475.1-201533.10" *)
module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:201476.7-201476.20" *)
  reg _00_;
  (* src = "libresoc.v:201521.3-201529.6" *)
  reg _01_;
  (* src = "libresoc.v:201519.3-201520.27" *)
  reg _02_;
  (* src = "libresoc.v:201521.3-201529.6" *)
  reg _03_;
  (* src = "libresoc.v:201498.7-201498.19" *)
  reg _04_;
  (* src = "libresoc.v:201511.17-201511.96" *)
  wire _05_;
  (* src = "libresoc.v:201516.17-201516.96" *)
  wire _06_;
  (* src = "libresoc.v:201513.18-201513.95" *)
  wire _07_;
  (* src = "libresoc.v:201515.17-201515.94" *)
  wire _08_;
  (* src = "libresoc.v:201518.17-201518.94" *)
  wire _09_;
  (* src = "libresoc.v:201512.18-201512.100" *)
  wire _10_;
  (* src = "libresoc.v:201514.18-201514.101" *)
  wire _11_;
  (* src = "libresoc.v:201517.17-201517.99" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:201476.7-201476.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_valid;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_valid;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_valid;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_valid;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_valid;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_valid;
  assign _11_ = q_valid | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_valid;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:201522.5-201522.29" *)
    casez (\initial )
      /* src = "libresoc.v:201522.9-201522.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_valid = \$15 ;
  assign qn_valid = \$13 ;
  assign q_valid = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.fus.ldst0.wri_l" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201537.1-201595.10" *)
module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:201538.7-201538.20" *)
  reg _00_;
  (* src = "libresoc.v:201583.3-201591.6" *)
  reg _01_;
  (* src = "libresoc.v:201581.3-201582.27" *)
  reg _02_;
  (* src = "libresoc.v:201583.3-201591.6" *)
  reg _03_;
  (* src = "libresoc.v:201560.7-201560.19" *)
  reg _04_;
  (* src = "libresoc.v:201573.17-201573.96" *)
  wire _05_;
  (* src = "libresoc.v:201578.17-201578.96" *)
  wire _06_;
  (* src = "libresoc.v:201575.18-201575.93" *)
  wire _07_;
  (* src = "libresoc.v:201577.17-201577.92" *)
  wire _08_;
  (* src = "libresoc.v:201580.17-201580.92" *)
  wire _09_;
  (* src = "libresoc.v:201574.18-201574.98" *)
  wire _10_;
  (* src = "libresoc.v:201576.18-201576.99" *)
  wire _11_;
  (* src = "libresoc.v:201579.17-201579.97" *)
  wire _12_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *)
  wire \$13 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *)
  wire \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "libresoc.v:201538.7-201538.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg q_int;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *)
  reg \q_int$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *)
  output q_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:69" *)
  wire qlq_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" *)
  wire qn_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" *)
  input r_wri;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *)
  input s_wri;
  assign _05_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) \$7 ;
  assign _06_ = q_int & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) \$1 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" *) q_wri;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) r_wri;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) r_wri;
  assign _10_ = \$9  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) s_wri;
  assign _11_ = q_wri | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) q_int;
  assign _12_ = \$3  | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" *) s_wri;
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _04_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      q_int <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \q_int$next ;
  end
  always @(posedge coresync_clk) begin
      q_int <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _03_;
    (* src = "libresoc.v:201584.5-201584.29" *)
    casez (\initial )
      /* src = "libresoc.v:201584.9-201584.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _03_ = 1'h0;
        end
      default:
          _03_ = \$5 ;
    endcase
  end
  always @* begin
      \q_int$next  <= _01_;
  end
  assign \$9  = _05_;
  assign \$11  = _10_;
  assign \$13  = _07_;
  assign \$15  = _11_;
  assign \$1  = _08_;
  assign \$3  = _06_;
  assign \$5  = _12_;
  assign \$7  = _09_;
  assign qlq_wri = \$15 ;
  assign qn_wri = \$13 ;
  assign q_wri = \$11 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_CR_cr_a" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201599.1-201665.10" *)
module wrpick_CR_cr_a(o, en_o, i);
  (* src = "libresoc.v:201644.17-201644.91" *)
  wire _00_;
  (* src = "libresoc.v:201646.18-201646.93" *)
  wire _01_;
  (* src = "libresoc.v:201648.18-201648.93" *)
  wire _02_;
  (* src = "libresoc.v:201649.17-201649.89" *)
  wire [5:0] _03_;
  (* src = "libresoc.v:201651.18-201651.93" *)
  wire _04_;
  (* src = "libresoc.v:201654.17-201654.91" *)
  wire _05_;
  (* src = "libresoc.v:201645.18-201645.106" *)
  wire _06_;
  (* src = "libresoc.v:201647.18-201647.106" *)
  wire _07_;
  (* src = "libresoc.v:201650.18-201650.106" *)
  wire _08_;
  (* src = "libresoc.v:201652.18-201652.90" *)
  wire _09_;
  (* src = "libresoc.v:201653.17-201653.103" *)
  wire _10_;
  (* src = "libresoc.v:201655.17-201655.105" *)
  wire _11_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [5:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [5:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [5:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [5:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _10_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _06_;
  assign \$11  = _01_;
  assign \$16  = _07_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _08_;
  assign \$19  = _04_;
  assign \$23  = _09_;
  assign \$4  = _10_;
  assign \$3  = _05_;
  assign \$8  = _11_;
  assign en_o = \$23 ;
  assign o = { t5, t4, t3, t2, t1, t0 };
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_CR_full_cr" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201669.1-201690.10" *)
module wrpick_CR_full_cr(o, en_o, i);
  (* src = "libresoc.v:201684.17-201684.89" *)
  wire _0_;
  (* src = "libresoc.v:201685.17-201685.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_FAST_fast1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201694.1-201751.10" *)
module wrpick_FAST_fast1(o, en_o, i);
  (* src = "libresoc.v:201733.17-201733.91" *)
  wire _00_;
  (* src = "libresoc.v:201735.18-201735.93" *)
  wire _01_;
  (* src = "libresoc.v:201737.18-201737.93" *)
  wire _02_;
  (* src = "libresoc.v:201738.17-201738.89" *)
  wire [4:0] _03_;
  (* src = "libresoc.v:201741.17-201741.91" *)
  wire _04_;
  (* src = "libresoc.v:201734.18-201734.106" *)
  wire _05_;
  (* src = "libresoc.v:201736.18-201736.106" *)
  wire _06_;
  (* src = "libresoc.v:201739.18-201739.90" *)
  wire _07_;
  (* src = "libresoc.v:201740.17-201740.103" *)
  wire _08_;
  (* src = "libresoc.v:201742.17-201742.105" *)
  wire _09_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [4:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [4:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [4:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [4:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _08_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _09_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _05_;
  assign \$11  = _01_;
  assign \$16  = _06_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$19  = _07_;
  assign \$4  = _08_;
  assign \$3  = _04_;
  assign \$8  = _09_;
  assign en_o = \$19 ;
  assign o = { t4, t3, t2, t1, t0 };
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_INT_o" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201755.1-201857.10" *)
module wrpick_INT_o(o, en_o, i);
  (* src = "libresoc.v:201824.17-201824.91" *)
  wire _00_;
  (* src = "libresoc.v:201826.18-201826.93" *)
  wire _01_;
  (* src = "libresoc.v:201828.18-201828.93" *)
  wire _02_;
  (* src = "libresoc.v:201829.17-201829.89" *)
  wire [9:0] _03_;
  (* src = "libresoc.v:201831.18-201831.93" *)
  wire _04_;
  (* src = "libresoc.v:201833.18-201833.93" *)
  wire _05_;
  (* src = "libresoc.v:201835.18-201835.93" *)
  wire _06_;
  (* src = "libresoc.v:201837.18-201837.93" *)
  wire _07_;
  (* src = "libresoc.v:201839.18-201839.93" *)
  wire _08_;
  (* src = "libresoc.v:201842.17-201842.91" *)
  wire _09_;
  (* src = "libresoc.v:201825.18-201825.106" *)
  wire _10_;
  (* src = "libresoc.v:201827.18-201827.106" *)
  wire _11_;
  (* src = "libresoc.v:201830.18-201830.106" *)
  wire _12_;
  (* src = "libresoc.v:201832.18-201832.106" *)
  wire _13_;
  (* src = "libresoc.v:201834.18-201834.106" *)
  wire _14_;
  (* src = "libresoc.v:201836.18-201836.106" *)
  wire _15_;
  (* src = "libresoc.v:201838.18-201838.106" *)
  wire _16_;
  (* src = "libresoc.v:201840.18-201840.90" *)
  wire _17_;
  (* src = "libresoc.v:201841.17-201841.103" *)
  wire _18_;
  (* src = "libresoc.v:201843.17-201843.105" *)
  wire _19_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [9:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$35 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$39 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [9:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [9:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [9:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t4;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t5;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t6;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t7;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t8;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t9;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$16 ;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _04_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$20 ;
  assign _05_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$24 ;
  assign _06_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$28 ;
  assign _07_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$32 ;
  assign _08_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$36 ;
  assign _09_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _10_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _11_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[3:0], ni[4] };
  assign _12_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[4:0], ni[5] };
  assign _13_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[5:0], ni[6] };
  assign _14_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[6:0], ni[7] };
  assign _15_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[7:0], ni[8] };
  assign _16_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[8:0], ni[9] };
  assign _17_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _18_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _19_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _10_;
  assign \$11  = _01_;
  assign \$16  = _11_;
  assign \$15  = _02_;
  assign \$1  = _03_;
  assign \$20  = _12_;
  assign \$19  = _04_;
  assign \$24  = _13_;
  assign \$23  = _05_;
  assign \$28  = _14_;
  assign \$27  = _06_;
  assign \$32  = _15_;
  assign \$31  = _07_;
  assign \$36  = _16_;
  assign \$35  = _08_;
  assign \$39  = _17_;
  assign \$4  = _18_;
  assign \$3  = _09_;
  assign \$8  = _19_;
  assign en_o = \$39 ;
  assign o = { t9, t8, t7, t6, t5, t4, t3, t2, t1, t0 };
  assign t9 = \$35 ;
  assign t8 = \$31 ;
  assign t7 = \$27 ;
  assign t6 = \$23 ;
  assign t5 = \$19 ;
  assign t4 = \$15 ;
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_SPR_spr1" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201861.1-201882.10" *)
module wrpick_SPR_spr1(o, en_o, i);
  (* src = "libresoc.v:201876.17-201876.89" *)
  wire _0_;
  (* src = "libresoc.v:201877.17-201877.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_STATE_msr" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201886.1-201907.10" *)
module wrpick_STATE_msr(o, en_o, i);
  (* src = "libresoc.v:201901.17-201901.89" *)
  wire _0_;
  (* src = "libresoc.v:201902.17-201902.89" *)
  wire _1_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$3  = _1_;
  assign en_o = \$3 ;
  assign o = t0;
  assign t0 = i;
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_STATE_nia" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201911.1-201941.10" *)
module wrpick_STATE_nia(o, en_o, i);
  (* src = "libresoc.v:201932.17-201932.89" *)
  wire [1:0] _0_;
  (* src = "libresoc.v:201934.17-201934.91" *)
  wire _1_;
  (* src = "libresoc.v:201933.17-201933.103" *)
  wire _2_;
  (* src = "libresoc.v:201935.17-201935.89" *)
  wire _3_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [1:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [1:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [1:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [1:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  assign _0_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _1_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _2_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _3_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign \$1  = _0_;
  assign \$4  = _2_;
  assign \$3  = _1_;
  assign \$7  = _3_;
  assign en_o = \$7 ;
  assign o = { t1, t0 };
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_XER_xer_ca" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201945.1-201984.10" *)
module wrpick_XER_xer_ca(o, en_o, i);
  (* src = "libresoc.v:201972.17-201972.91" *)
  wire _00_;
  (* src = "libresoc.v:201974.17-201974.89" *)
  wire [2:0] _01_;
  (* src = "libresoc.v:201976.17-201976.91" *)
  wire _02_;
  (* src = "libresoc.v:201973.18-201973.90" *)
  wire _03_;
  (* src = "libresoc.v:201975.17-201975.103" *)
  wire _04_;
  (* src = "libresoc.v:201977.17-201977.105" *)
  wire _05_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [2:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [2:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [2:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [2:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _03_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _04_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$11  = _03_;
  assign \$1  = _01_;
  assign \$4  = _04_;
  assign \$3  = _02_;
  assign \$8  = _05_;
  assign en_o = \$11 ;
  assign o = { t2, t1, t0 };
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_XER_xer_ov" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:201988.1-202036.10" *)
module wrpick_XER_xer_ov(o, en_o, i);
  (* src = "libresoc.v:202021.17-202021.91" *)
  wire _00_;
  (* src = "libresoc.v:202023.18-202023.93" *)
  wire _01_;
  (* src = "libresoc.v:202025.17-202025.89" *)
  wire [3:0] _02_;
  (* src = "libresoc.v:202027.17-202027.91" *)
  wire _03_;
  (* src = "libresoc.v:202022.18-202022.106" *)
  wire _04_;
  (* src = "libresoc.v:202024.18-202024.90" *)
  wire _05_;
  (* src = "libresoc.v:202026.17-202026.103" *)
  wire _06_;
  (* src = "libresoc.v:202028.17-202028.105" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [3:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [3:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [3:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _04_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _04_;
  assign \$11  = _01_;
  assign \$15  = _05_;
  assign \$1  = _02_;
  assign \$4  = _06_;
  assign \$3  = _03_;
  assign \$8  = _07_;
  assign en_o = \$15 ;
  assign o = { t3, t2, t1, t0 };
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.wrpick_XER_xer_so" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:202040.1-202088.10" *)
module wrpick_XER_xer_so(o, en_o, i);
  (* src = "libresoc.v:202073.17-202073.91" *)
  wire _00_;
  (* src = "libresoc.v:202075.18-202075.93" *)
  wire _01_;
  (* src = "libresoc.v:202077.17-202077.89" *)
  wire [3:0] _02_;
  (* src = "libresoc.v:202079.17-202079.91" *)
  wire _03_;
  (* src = "libresoc.v:202074.18-202074.106" *)
  wire _04_;
  (* src = "libresoc.v:202076.18-202076.90" *)
  wire _05_;
  (* src = "libresoc.v:202078.17-202078.103" *)
  wire _06_;
  (* src = "libresoc.v:202080.17-202080.105" *)
  wire _07_;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *)
  wire [3:0] \$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$11 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$4 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:47" *)
  output en_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45" *)
  input [3:0] i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:54" *)
  wire [3:0] ni;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:46" *)
  output [3:0] o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t0;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t1;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t2;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" *)
  wire t3;
  assign _00_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$8 ;
  assign _01_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$12 ;
  assign _02_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" *) i;
  assign _03_ = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) \$4 ;
  assign _04_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[2:0], ni[3] };
  assign _05_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" *) o;
  assign _06_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[0], ni[1] };
  assign _07_ = | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" *) { i[1:0], ni[2] };
  assign \$7  = _00_;
  assign \$12  = _04_;
  assign \$11  = _01_;
  assign \$15  = _05_;
  assign \$1  = _02_;
  assign \$4  = _06_;
  assign \$3  = _03_;
  assign \$8  = _07_;
  assign en_o = \$15 ;
  assign o = { t3, t2, t1, t0 };
  assign t3 = \$11 ;
  assign t2 = \$7 ;
  assign t1 = \$3 ;
  assign t0 = i[0];
  assign ni = \$1 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.core.xer" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:202092.1-202412.10" *)
module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, src2__data_o, src2__ren, src3__data_o, src3__ren, data_i, wen, \data_i$1 , \wen$2 , \data_i$3 , \wen$4 , coresync_clk);
  reg \initial  = 0;
  (* src = "libresoc.v:202093.7-202093.20" *)
  reg _00_;
  (* src = "libresoc.v:202372.3-202380.6" *)
  reg [2:0] _01_;
  (* src = "libresoc.v:202270.3-202271.43" *)
  reg [2:0] _02_;
  (* src = "libresoc.v:202229.13-202229.34" *)
  reg [2:0] _03_;
  (* src = "libresoc.v:202334.3-202342.6" *)
  reg [2:0] _04_;
  (* src = "libresoc.v:202268.3-202269.43" *)
  reg [2:0] _05_;
  (* src = "libresoc.v:202233.13-202233.34" *)
  reg [2:0] _06_;
  (* src = "libresoc.v:202353.3-202361.6" *)
  reg [2:0] _07_;
  (* src = "libresoc.v:202272.3-202273.35" *)
  reg [2:0] _08_;
  (* src = "libresoc.v:202362.3-202371.6" *)
  reg [1:0] _09_;
  (* src = "libresoc.v:202381.3-202390.6" *)
  reg [1:0] _10_;
  (* src = "libresoc.v:202343.3-202352.6" *)
  reg [1:0] _11_;
  (* src = "libresoc.v:202372.3-202380.6" *)
  reg [2:0] _12_;
  (* src = "libresoc.v:202334.3-202342.6" *)
  reg [2:0] _13_;
  (* src = "libresoc.v:202353.3-202361.6" *)
  reg [2:0] _14_;
  (* src = "libresoc.v:202227.13-202227.29" *)
  reg [2:0] _15_;
  (* src = "libresoc.v:202362.3-202371.6" *)
  reg [1:0] _16_;
  (* src = "libresoc.v:202381.3-202390.6" *)
  reg [1:0] _17_;
  (* src = "libresoc.v:202343.3-202352.6" *)
  reg [1:0] _18_;
  (* src = "libresoc.v:202259.17-202259.109" *)
  wire [1:0] _19_;
  (* src = "libresoc.v:202261.18-202261.126" *)
  wire [1:0] _20_;
  (* src = "libresoc.v:202262.18-202262.111" *)
  wire [1:0] _21_;
  (* src = "libresoc.v:202264.18-202264.126" *)
  wire [1:0] _22_;
  (* src = "libresoc.v:202265.18-202265.111" *)
  wire [1:0] _23_;
  (* src = "libresoc.v:202267.17-202267.125" *)
  wire [1:0] _24_;
  (* src = "libresoc.v:202260.18-202260.100" *)
  wire _25_;
  (* src = "libresoc.v:202263.18-202263.100" *)
  wire _26_;
  (* src = "libresoc.v:202266.17-202266.95" *)
  wire _27_;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$14 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$16 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$21 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *)
  wire [1:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *)
  wire [1:0] \$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:844" *)
  input coresync_rst;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] \data_i$1 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [1:0] \data_i$3 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [5:0] full_rd__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] full_rd__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [5:0] full_wr__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [2:0] full_wr__wen;
  (* src = "libresoc.v:202093.7-202093.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_dest10__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_dest10__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_dest20__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_dest20__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_dest30__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_dest30__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_r0__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_r0__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_src10__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src10__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_src20__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src20__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_src30__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_src30__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_0_w0__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_0_w0__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_dest11__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_dest11__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_dest21__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_dest21__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_dest31__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_dest31__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_r1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_r1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_src11__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src11__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_src21__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src21__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_src31__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_src31__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_1_w1__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_1_w1__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_dest12__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_dest12__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_dest22__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_dest22__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_dest32__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_dest32__wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_r2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_r2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_src12__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src12__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_src22__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src22__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_src32__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_src32__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire [1:0] reg_2_w2__data_i;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  wire reg_2_w2__wen;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] ren_delay;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$11$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$18 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$18$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" *)
  reg [2:0] \ren_delay$next ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src1__data_o;
  reg [1:0] src1__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] src1__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src2__data_o;
  reg [1:0] src2__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] src2__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  output [1:0] src3__data_o;
  reg [1:0] src3__data_o;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] src3__ren;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] wen;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \wen$2 ;
  (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *)
  input [2:0] \wen$4 ;
  assign _19_ = reg_0_src10__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$7 ;
  assign _20_ = reg_1_src21__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src22__data_o;
  assign _21_ = reg_0_src20__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$14 ;
  assign _22_ = reg_1_src31__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src32__data_o;
  assign _23_ = reg_0_src30__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) \$21 ;
  assign _24_ = reg_1_src11__data_o | (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) reg_2_src12__data_o;
  assign _25_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$11 ;
  assign _26_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \ren_delay$18 ;
  assign _27_ = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) ren_delay;
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:202274.15-202293.4" *)
  \reg_0$132  reg_0 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest10__data_i(reg_0_dest10__data_i),
    .dest10__wen(reg_0_dest10__wen),
    .dest20__data_i(reg_0_dest20__data_i),
    .dest20__wen(reg_0_dest20__wen),
    .dest30__data_i(reg_0_dest30__data_i),
    .dest30__wen(reg_0_dest30__wen),
    .r0__data_o(reg_0_r0__data_o),
    .r0__ren(reg_0_r0__ren),
    .src10__data_o(reg_0_src10__data_o),
    .src10__ren(reg_0_src10__ren),
    .src20__data_o(reg_0_src20__data_o),
    .src20__ren(reg_0_src20__ren),
    .src30__data_o(reg_0_src30__data_o),
    .src30__ren(reg_0_src30__ren),
    .w0__data_i(reg_0_w0__data_i),
    .w0__wen(reg_0_w0__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:202294.15-202313.4" *)
  \reg_1$133  reg_1 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest11__data_i(reg_1_dest11__data_i),
    .dest11__wen(reg_1_dest11__wen),
    .dest21__data_i(reg_1_dest21__data_i),
    .dest21__wen(reg_1_dest21__wen),
    .dest31__data_i(reg_1_dest31__data_i),
    .dest31__wen(reg_1_dest31__wen),
    .r1__data_o(reg_1_r1__data_o),
    .r1__ren(reg_1_r1__ren),
    .src11__data_o(reg_1_src11__data_o),
    .src11__ren(reg_1_src11__ren),
    .src21__data_o(reg_1_src21__data_o),
    .src21__ren(reg_1_src21__ren),
    .src31__data_o(reg_1_src31__data_o),
    .src31__ren(reg_1_src31__ren),
    .w1__data_i(reg_1_w1__data_i),
    .w1__wen(reg_1_w1__wen)
  );
  (* module_not_derived = 32'd1 *)
  (* src = "libresoc.v:202314.15-202333.4" *)
  \reg_2$134  reg_2 (
    .coresync_clk(coresync_clk),
    .coresync_rst(coresync_rst),
    .dest12__data_i(reg_2_dest12__data_i),
    .dest12__wen(reg_2_dest12__wen),
    .dest22__data_i(reg_2_dest22__data_i),
    .dest22__wen(reg_2_dest22__wen),
    .dest32__data_i(reg_2_dest32__data_i),
    .dest32__wen(reg_2_dest32__wen),
    .r2__data_o(reg_2_r2__data_o),
    .r2__ren(reg_2_r2__ren),
    .src12__data_o(reg_2_src12__data_o),
    .src12__ren(reg_2_src12__ren),
    .src22__data_o(reg_2_src22__data_o),
    .src22__ren(reg_2_src22__ren),
    .src32__data_o(reg_2_src32__data_o),
    .src32__ren(reg_2_src32__ren),
    .w2__data_i(reg_2_w2__data_i),
    .w2__wen(reg_2_w2__wen)
  );
  always @* begin
    if (\initial ) begin end
    _00_ = 1'h0;
  end
  always @* begin
      \initial  <= _00_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _15_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      ren_delay <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _03_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$11  <= _03_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = 3'h0;
  end
  always @* begin
  end
  initial begin
      \ren_delay$18  <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = \ren_delay$18$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$18  <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \ren_delay$11$next ;
  end
  always @(posedge coresync_clk) begin
      \ren_delay$11  <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _08_ = \ren_delay$next ;
  end
  always @(posedge coresync_clk) begin
      ren_delay <= _08_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _13_;
    (* src = "libresoc.v:202335.5-202335.29" *)
    casez (\initial )
      /* src = "libresoc.v:202335.9-202335.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _13_ = 3'h0;
        end
      default:
          _13_ = src3__ren;
    endcase
  end
  always @* begin
      \ren_delay$18$next  <= _04_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _18_;
    (* src = "libresoc.v:202344.5-202344.29" *)
    casez (\initial )
      /* src = "libresoc.v:202344.9-202344.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$19 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _18_ = \$23 ;
        end
      default:
          _18_ = 2'h0;
    endcase
  end
  always @* begin
      src3__data_o <= _11_;
  end
  always @* begin
    if (\initial ) begin end
    _07_ = _14_;
    (* src = "libresoc.v:202354.5-202354.29" *)
    casez (\initial )
      /* src = "libresoc.v:202354.9-202354.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _14_ = 3'h0;
        end
      default:
          _14_ = src1__ren;
    endcase
  end
  always @* begin
      \ren_delay$next  <= _07_;
  end
  always @* begin
    if (\initial ) begin end
    _09_ = _16_;
    (* src = "libresoc.v:202363.5-202363.29" *)
    casez (\initial )
      /* src = "libresoc.v:202363.9-202363.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$5 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _16_ = \$9 ;
        end
      default:
          _16_ = 2'h0;
    endcase
  end
  always @* begin
      src1__data_o <= _09_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _12_;
    (* src = "libresoc.v:202373.5-202373.29" *)
    casez (\initial )
      /* src = "libresoc.v:202373.9-202373.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (coresync_rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _12_ = 3'h0;
        end
      default:
          _12_ = src2__ren;
    endcase
  end
  always @* begin
      \ren_delay$11$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = _17_;
    (* src = "libresoc.v:202382.5-202382.29" *)
    casez (\initial )
      /* src = "libresoc.v:202382.9-202382.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" *)
    casez (\$12 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _17_ = \$16 ;
        end
      default:
          _17_ = 2'h0;
    endcase
  end
  always @* begin
      src2__data_o <= _10_;
  end
  assign \$9  = _19_;
  assign \$12  = _25_;
  assign \$14  = _20_;
  assign \$16  = _21_;
  assign \$19  = _26_;
  assign \$21  = _22_;
  assign \$23  = _23_;
  assign \$5  = _27_;
  assign \$7  = _24_;
  assign full_wr__data_i = 6'h00;
  assign full_wr__wen = 3'h0;
  assign { reg_2_w2__wen, reg_1_w1__wen, reg_0_w0__wen } = 3'h0;
  assign { reg_2_w2__data_i, reg_1_w1__data_i, reg_0_w0__data_i } = 6'h00;
  assign { reg_2_r2__ren, reg_1_r1__ren, reg_0_r0__ren } = full_rd__ren;
  assign full_rd__data_o = { reg_2_r2__data_o, reg_1_r1__data_o, reg_0_r0__data_o };
  assign reg_2_dest32__data_i = \data_i$1 ;
  assign reg_1_dest31__data_i = \data_i$1 ;
  assign reg_0_dest30__data_i = \data_i$1 ;
  assign { reg_2_dest32__wen, reg_1_dest31__wen, reg_0_dest30__wen } = \wen$2 ;
  assign reg_2_dest22__data_i = data_i;
  assign reg_1_dest21__data_i = data_i;
  assign reg_0_dest20__data_i = data_i;
  assign { reg_2_dest22__wen, reg_1_dest21__wen, reg_0_dest20__wen } = wen;
  assign reg_2_dest12__data_i = \data_i$3 ;
  assign reg_1_dest11__data_i = \data_i$3 ;
  assign reg_0_dest10__data_i = \data_i$3 ;
  assign { reg_2_dest12__wen, reg_1_dest11__wen, reg_0_dest10__wen } = \wen$4 ;
  assign { reg_2_src32__ren, reg_1_src31__ren, reg_0_src30__ren } = src3__ren;
  assign { reg_2_src22__ren, reg_1_src21__ren, reg_0_src20__ren } = src2__ren;
  assign { reg_2_src12__ren, reg_1_src11__ren, reg_0_src10__ren } = src1__ren;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.xics_icp" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:202416.1-202733.10" *)
module xics_icp(ics_i_src, ics_i_pri, core_irq_o, rst, icp_wb__ack, icp_wb__cyc, icp_wb__dat_r, icp_wb__dat_w, icp_wb__stb, icp_wb__we, icp_wb__adr, icp_wb__sel, clk);
  reg \initial  = 0;
  (* src = "libresoc.v:202597.3-202625.6" *)
  reg [31:0] _00_;
  (* src = "libresoc.v:202648.3-202656.6" *)
  reg _01_;
  (* src = "libresoc.v:202536.3-202537.37" *)
  reg _02_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _03_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [7:0] _04_;
  (* src = "libresoc.v:202540.3-202541.25" *)
  reg [7:0] _05_;
  (* src = "libresoc.v:202657.3-202666.6" *)
  reg [31:0] _06_;
  (* src = "libresoc.v:202417.7-202417.20" *)
  reg _07_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg _08_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg _09_;
  (* src = "libresoc.v:202544.3-202545.23" *)
  reg _10_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _11_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [7:0] _12_;
  (* src = "libresoc.v:202542.3-202543.25" *)
  reg [7:0] _13_;
  (* src = "libresoc.v:202636.3-202647.6" *)
  reg [7:0] _14_;
  (* src = "libresoc.v:202626.3-202635.6" *)
  reg [7:0] _15_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg _16_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg _17_;
  (* src = "libresoc.v:202548.3-202549.29" *)
  reg _18_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [31:0] _19_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [31:0] _20_;
  (* src = "libresoc.v:202546.3-202547.37" *)
  reg [31:0] _21_;
  (* src = "libresoc.v:202566.3-202596.6" *)
  reg _22_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [23:0] _23_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [23:0] _24_;
  (* src = "libresoc.v:202538.3-202539.25" *)
  reg [23:0] _25_;
  (* src = "libresoc.v:202597.3-202625.6" *)
  reg [31:0] _26_;
  (* src = "libresoc.v:202648.3-202656.6" *)
  reg _27_;
  (* src = "libresoc.v:202446.7-202446.24" *)
  reg _28_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _29_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [7:0] _30_;
  (* src = "libresoc.v:202450.13-202450.25" *)
  reg [7:0] _31_;
  (* src = "libresoc.v:202657.3-202666.6" *)
  reg [31:0] _32_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg _33_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg _34_;
  (* src = "libresoc.v:202479.7-202479.17" *)
  reg _35_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _36_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [7:0] _37_;
  (* src = "libresoc.v:202487.13-202487.25" *)
  reg [7:0] _38_;
  (* src = "libresoc.v:202636.3-202647.6" *)
  reg [7:0] _39_;
  (* src = "libresoc.v:202626.3-202635.6" *)
  reg [7:0] _40_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg _41_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg _42_;
  (* src = "libresoc.v:202501.7-202501.20" *)
  reg _43_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [31:0] _44_;
  (* src = "libresoc.v:202509.14-202509.32" *)
  reg [31:0] _45_;
  (* src = "libresoc.v:202566.3-202596.6" *)
  reg _46_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [23:0] _47_;
  (* src = "libresoc.v:202550.3-202565.6" *)
  reg [23:0] _48_;
  (* src = "libresoc.v:202519.14-202519.31" *)
  reg [23:0] _49_;
  (* src = "libresoc.v:202597.3-202625.6" *)
  reg [31:0] _50_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _51_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _52_;
  (* src = "libresoc.v:202566.3-202596.6" *)
  reg _53_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [23:0] _54_;
  (* src = "libresoc.v:202597.3-202625.6" *)
  reg [31:0] _55_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _56_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _57_;
  (* src = "libresoc.v:202566.3-202596.6" *)
  reg _58_;
  (* src = "libresoc.v:202667.3-202729.6" *)
  reg [7:0] _59_;
  (* src = "libresoc.v:202566.3-202596.6" *)
  reg _60_;
  (* src = "libresoc.v:202526.18-202526.116" *)
  wire _61_;
  (* src = "libresoc.v:202530.18-202530.116" *)
  wire _62_;
  (* src = "libresoc.v:202532.18-202532.116" *)
  wire _63_;
  (* src = "libresoc.v:202535.17-202535.109" *)
  wire _64_;
  (* src = "libresoc.v:202531.18-202531.110" *)
  wire _65_;
  (* src = "libresoc.v:202528.18-202528.114" *)
  wire _66_;
  (* src = "libresoc.v:202529.18-202529.109" *)
  wire _67_;
  (* src = "libresoc.v:202534.18-202534.114" *)
  wire _68_;
  (* src = "libresoc.v:202527.18-202527.109" *)
  wire _69_;
  (* src = "libresoc.v:202533.18-202533.109" *)
  wire _70_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
  wire \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *)
  wire \$17 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *)
  wire \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *)
  wire \$21 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
  wire \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *)
  wire \$25 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
  wire \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *)
  wire \$29 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *)
  wire \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" *)
  wire \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" *)
  wire [31:0] be_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *)
  reg [31:0] be_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
  output core_irq_o;
  reg core_irq_o;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *)
  reg \core_irq_o$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
  reg [7:0] cppr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
  reg [7:0] \cppr$10 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
  wire [7:0] \cppr$2 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" *)
  reg [7:0] \cppr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output icp_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [27:0] icp_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  output [31:0] icp_wb__dat_r;
  reg [31:0] icp_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [31:0] icp_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input [3:0] icp_wb__sel;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" *)
  input icp_wb__we;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  input [7:0] ics_i_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  input [3:0] ics_i_src;
  (* src = "libresoc.v:202417.7-202417.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *)
  reg irq;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *)
  reg \irq$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *)
  wire \irq$4 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" *)
  reg \irq$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *)
  reg [7:0] mfrr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *)
  reg [7:0] \mfrr$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *)
  wire [7:0] \mfrr$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" *)
  reg [7:0] \mfrr$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" *)
  reg [7:0] min_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *)
  reg [7:0] pending_priority;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
  reg wb_ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
  reg \wb_ack$14 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
  wire \wb_ack$6 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *)
  reg \wb_ack$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *)
  reg [31:0] wb_rd_data;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *)
  reg [31:0] \wb_rd_data$13 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *)
  wire [31:0] \wb_rd_data$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" *)
  reg [31:0] \wb_rd_data$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" *)
  reg xirr_accept_rd;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *)
  reg [23:0] xisr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *)
  wire [23:0] \xisr$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *)
  reg [23:0] \xisr$9 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" *)
  reg [23:0] \xisr$next ;
  assign _61_ = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb;
  assign _62_ = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb;
  assign _63_ = icp_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *) icp_wb__stb;
  assign _64_ = wb_ack & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" *) icp_wb__cyc;
  assign _65_ = icp_wb__sel == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *) 4'hf;
  assign _66_ = mfrr < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) pending_priority;
  assign _67_ = min_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *) \cppr$10 ;
  assign _68_ = mfrr < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *) pending_priority;
  assign _69_ = ics_i_pri != (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) 8'hff;
  assign _70_ = ics_i_pri != (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *) 8'hff;
  always @* begin
    if (\initial ) begin end
    _07_ = 1'h0;
  end
  always @* begin
      \initial  <= _07_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _28_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      core_irq_o <= _28_;
  end
  always @* begin
    if (\initial ) begin end
    _31_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      cppr <= _31_;
  end
  always @* begin
    if (\initial ) begin end
    _35_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      irq <= _35_;
  end
  always @* begin
    if (\initial ) begin end
    _38_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      mfrr <= _38_;
  end
  always @* begin
    if (\initial ) begin end
    _43_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      wb_ack <= _43_;
  end
  always @* begin
    if (\initial ) begin end
    _45_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      wb_rd_data <= _45_;
  end
  always @* begin
    if (\initial ) begin end
    _49_ = 24'h000000;
  end
  always @* begin
  end
  initial begin
      xisr <= _49_;
  end
  always @* begin
    if (\initial ) begin end
    _02_ = \core_irq_o$next ;
  end
  always @(posedge clk) begin
      core_irq_o <= _02_;
  end
  always @* begin
    if (\initial ) begin end
    _25_ = \xisr$next ;
  end
  always @(posedge clk) begin
      xisr <= _25_;
  end
  always @* begin
    if (\initial ) begin end
    _05_ = \cppr$next ;
  end
  always @(posedge clk) begin
      cppr <= _05_;
  end
  always @* begin
    if (\initial ) begin end
    _13_ = \mfrr$next ;
  end
  always @(posedge clk) begin
      mfrr <= _13_;
  end
  always @* begin
    if (\initial ) begin end
    _10_ = \irq$next ;
  end
  always @(posedge clk) begin
      irq <= _10_;
  end
  always @* begin
    if (\initial ) begin end
    _21_ = \wb_rd_data$next ;
  end
  always @(posedge clk) begin
      wb_rd_data <= _21_;
  end
  always @* begin
    if (\initial ) begin end
    _18_ = \wb_ack$next ;
  end
  always @(posedge clk) begin
      wb_ack <= _18_;
  end
  always @* begin
    if (\initial ) begin end
    _04_ = _30_;
    _09_ = _34_;
    _12_ = _37_;
    _17_ = _42_;
    _20_ = _44_;
    _24_ = _48_;
    (* src = "libresoc.v:202551.5-202551.29" *)
    casez (\initial )
      /* src = "libresoc.v:202551.9-202551.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _48_ = 24'h000000;
          _30_ = 8'h00;
          _37_ = 8'hff;
          _34_ = 1'h0;
          _44_ = 32'd0;
          _42_ = 1'h0;
        end
      default:
        begin
          _30_ = \cppr$2 ;
          _34_ = \irq$4 ;
          _37_ = \mfrr$3 ;
          _42_ = \wb_ack$6 ;
          _44_ = \wb_rd_data$5 ;
          _48_ = \xisr$1 ;
        end
    endcase
  end
  always @* begin
      \cppr$next  <= _04_;
      \irq$next  <= _09_;
      \mfrr$next  <= _12_;
      \wb_ack$next  <= _17_;
      \wb_rd_data$next  <= _20_;
      \xisr$next  <= _24_;
  end
  always @* begin
    if (\initial ) begin end
    _22_ = _46_;
    (* src = "libresoc.v:202567.5-202567.29" *)
    casez (\initial )
      /* src = "libresoc.v:202567.9-202567.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
    casez (\$23 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _46_ = _53_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *)
          casez (icp_wb__we)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _53_ = 1'h0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _53_ = _58_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" *)
                casez (icp_wb__adr[5:0])
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h00:
                      _58_ = 1'h0;
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h01:
                    begin
                      _58_ = _60_;
                      (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" *)
                      casez (\$25 )
                        /* src = "libresoc.v:0.0-0.0" */
                        1'h1:
                          begin
                            _60_ = 1'h1;
                          end
                        default:
                            _60_ = 1'h0;
                      endcase
                    end
                  default:
                      _58_ = 1'h0;
                endcase
              end
          endcase
        end
      default:
          _46_ = 1'h0;
    endcase
  end
  always @* begin
      xirr_accept_rd <= _22_;
  end
  always @* begin
    if (\initial ) begin end
    _00_ = _26_;
    (* src = "libresoc.v:202598.5-202598.29" *)
    casez (\initial )
      /* src = "libresoc.v:202598.9-202598.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
    casez (\$27 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _26_ = _50_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *)
          casez (icp_wb__we)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
                _50_ = 32'd0;
            /* src = "libresoc.v:0.0-0.0" */
            default:
              begin
                _50_ = _55_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" *)
                casez (icp_wb__adr[5:0])
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h00:
                    begin
                      _55_ = { cppr, xisr };
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h01:
                    begin
                      _55_ = { cppr, xisr };
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h03:
                    begin
                      _55_[23:0] = 24'h000000;
                      _55_[31:24] = mfrr;
                    end
                  default:
                      _55_ = 32'd0;
                endcase
              end
          endcase
        end
      default:
          _26_ = 32'd0;
    endcase
  end
  always @* begin
      be_out <= _00_;
  end
  always @* begin
    if (\initial ) begin end
    _15_ = _40_;
    (* src = "libresoc.v:202627.5-202627.29" *)
    casez (\initial )
      /* src = "libresoc.v:202627.9-202627.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *)
    casez (\$29 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _40_ = ics_i_pri;
        end
      default:
          _40_ = 8'hff;
    endcase
  end
  always @* begin
      pending_priority <= _15_;
  end
  always @* begin
    if (\initial ) begin end
    _14_ = _39_;
    (* src = "libresoc.v:202637.5-202637.29" *)
    casez (\initial )
      /* src = "libresoc.v:202637.9-202637.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *)
    casez (\$31 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _39_ = mfrr;
        end
      /* src = "libresoc.v:0.0-0.0" */
      default:
        begin
          _39_ = pending_priority;
        end
    endcase
  end
  always @* begin
      min_pri <= _14_;
  end
  always @* begin
    if (\initial ) begin end
    _01_ = _27_;
    (* src = "libresoc.v:202649.5-202649.29" *)
    casez (\initial )
      /* src = "libresoc.v:202649.9-202649.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _27_ = 1'h0;
        end
      default:
          _27_ = irq;
    endcase
  end
  always @* begin
      \core_irq_o$next  <= _01_;
  end
  always @* begin
    if (\initial ) begin end
    _06_ = _32_;
    (* src = "libresoc.v:202658.5-202658.29" *)
    casez (\initial )
      /* src = "libresoc.v:202658.9-202658.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" *)
    casez (icp_wb__ack)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _32_ = wb_rd_data;
        end
      default:
          _32_ = 32'd0;
    endcase
  end
  always @* begin
      icp_wb__dat_r <= _06_;
  end
  always @* begin
    if (\initial ) begin end
    _11_ = _36_;
    _16_ = _41_;
    _23_ = _54_;
    _03_ = _59_;
    _19_ = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] };
    _08_ = _33_;
    (* src = "libresoc.v:202668.5-202668.29" *)
    casez (\initial )
      /* src = "libresoc.v:202668.9-202668.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" *)
    casez (\$15 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _41_ = 1'h1;
          _29_ = _51_;
          _36_ = _52_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" *)
          casez (icp_wb__we)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _51_ = _56_;
                _52_ = _57_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" *)
                casez (icp_wb__adr[5:0])
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h00:
                    begin
                      _57_ = mfrr;
                      _56_ = be_in[31:24];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h01:
                    begin
                      _57_ = mfrr;
                      _56_ = be_in[31:24];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  6'h03:
                    begin
                      _56_ = cppr;
                      _57_ = be_in[31:24];
                    end
                  default:
                    begin
                      _56_ = cppr;
                      _57_ = mfrr;
                    end
                endcase
              end
            default:
              begin
                _51_ = cppr;
                _52_ = mfrr;
              end
          endcase
        end
      default:
        begin
          _29_ = cppr;
          _36_ = mfrr;
          _41_ = 1'h0;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" *)
    casez (\$17 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _47_ = { 20'h00001, ics_i_src };
        end
      default:
          _47_ = 24'h000000;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" *)
    casez (\$19 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _54_ = 24'h000002;
        end
      default:
          _54_ = _47_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" *)
    casez (xirr_accept_rd)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _59_ = min_pri;
        end
      default:
          _59_ = _29_;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" *)
    casez ({ irq, \$21  })
      /* src = "libresoc.v:0.0-0.0" */
      2'b?1:
        begin
          _33_ = 1'h1;
        end
      default:
          _33_ = 1'h0;
    endcase
  end
  always @* begin
      \cppr$10  <= _03_;
      \irq$12  <= _08_;
      \mfrr$11  <= _11_;
      \wb_ack$14  <= _16_;
      \wb_rd_data$13  <= _19_;
      \xisr$9  <= _23_;
  end
  assign \$15  = _61_;
  assign \$17  = _69_;
  assign \$19  = _66_;
  assign \$21  = _67_;
  assign \$23  = _62_;
  assign \$25  = _65_;
  assign \$27  = _63_;
  assign \$29  = _70_;
  assign \$31  = _68_;
  assign \$7  = _64_;
  assign { \wb_ack$6 , \wb_rd_data$5 , \irq$4 , \mfrr$3 , \cppr$2 , \xisr$1  } = { \wb_ack$14 , \wb_rd_data$13 , \irq$12 , \mfrr$11 , \cppr$10 , \xisr$9  };
  assign be_in = { icp_wb__dat_w[7:0], icp_wb__dat_w[15:8], icp_wb__dat_w[23:16], icp_wb__dat_w[31:24] };
  assign icp_wb__ack = \$7 ;
endmodule

(* generator = "nMigen" *)
(* \nmigen.hierarchy  = "test_issuer.ti.xics_ics" *)
(* cells_not_processed =  1  *)
(* src = "libresoc.v:202737.1-203786.10" *)
module xics_ics(icp_o_src, icp_o_pri, rst, ics_wb__adr, int_level_i, ics_wb__cyc, ics_wb__stb, ics_wb__dat_r, ics_wb__ack, ics_wb__dat_w, ics_wb__we, clk);
  reg \initial  = 0;
  (* src = "libresoc.v:203667.3-203716.6" *)
  reg [31:0] _000_;
  (* src = "libresoc.v:203378.3-203387.6" *)
  reg [3:0] _001_;
  (* src = "libresoc.v:203587.3-203596.6" *)
  reg [3:0] _002_;
  (* src = "libresoc.v:203607.3-203616.6" *)
  reg [3:0] _003_;
  (* src = "libresoc.v:203627.3-203636.6" *)
  reg [3:0] _004_;
  (* src = "libresoc.v:203647.3-203656.6" *)
  reg [3:0] _005_;
  (* src = "libresoc.v:203717.3-203726.6" *)
  reg [3:0] _006_;
  (* src = "libresoc.v:203737.3-203746.6" *)
  reg [3:0] _007_;
  (* src = "libresoc.v:203398.3-203407.6" *)
  reg [3:0] _008_;
  (* src = "libresoc.v:203418.3-203427.6" *)
  reg [3:0] _009_;
  (* src = "libresoc.v:203438.3-203447.6" *)
  reg [3:0] _010_;
  (* src = "libresoc.v:203467.3-203476.6" *)
  reg [3:0] _011_;
  (* src = "libresoc.v:203487.3-203496.6" *)
  reg [3:0] _012_;
  (* src = "libresoc.v:203507.3-203516.6" *)
  reg [3:0] _013_;
  (* src = "libresoc.v:203527.3-203536.6" *)
  reg [3:0] _014_;
  (* src = "libresoc.v:203547.3-203556.6" *)
  reg [3:0] _015_;
  (* src = "libresoc.v:203567.3-203576.6" *)
  reg [3:0] _016_;
  (* src = "libresoc.v:203368.3-203377.6" *)
  reg [7:0] _017_;
  (* src = "libresoc.v:203577.3-203586.6" *)
  reg [7:0] _018_;
  (* src = "libresoc.v:203597.3-203606.6" *)
  reg [7:0] _019_;
  (* src = "libresoc.v:203617.3-203626.6" *)
  reg [7:0] _020_;
  (* src = "libresoc.v:203637.3-203646.6" *)
  reg [7:0] _021_;
  (* src = "libresoc.v:203657.3-203666.6" *)
  reg [7:0] _022_;
  (* src = "libresoc.v:203727.3-203736.6" *)
  reg [7:0] _023_;
  (* src = "libresoc.v:203388.3-203397.6" *)
  reg [7:0] _024_;
  (* src = "libresoc.v:203408.3-203417.6" *)
  reg [7:0] _025_;
  (* src = "libresoc.v:203428.3-203437.6" *)
  reg [7:0] _026_;
  (* src = "libresoc.v:203448.3-203457.6" *)
  reg [7:0] _027_;
  (* src = "libresoc.v:203477.3-203486.6" *)
  reg [7:0] _028_;
  (* src = "libresoc.v:203497.3-203506.6" *)
  reg [7:0] _029_;
  (* src = "libresoc.v:203517.3-203526.6" *)
  reg [7:0] _030_;
  (* src = "libresoc.v:203537.3-203546.6" *)
  reg [7:0] _031_;
  (* src = "libresoc.v:203557.3-203566.6" *)
  reg [7:0] _032_;
  (* src = "libresoc.v:203747.3-203756.6" *)
  reg _033_;
  (* src = "libresoc.v:203242.3-203243.25" *)
  reg [7:0] _034_;
  (* src = "libresoc.v:203240.3-203241.28" *)
  reg [3:0] _035_;
  (* src = "libresoc.v:203766.3-203774.6" *)
  reg _036_;
  (* src = "libresoc.v:203276.3-203277.39" *)
  reg _037_;
  (* src = "libresoc.v:203757.3-203765.6" *)
  reg [31:0] _038_;
  (* src = "libresoc.v:203278.3-203279.43" *)
  reg [31:0] _039_;
  (* src = "libresoc.v:202738.7-202738.20" *)
  reg _040_;
  (* src = "libresoc.v:203458.3-203466.6" *)
  reg [15:0] _041_;
  (* src = "libresoc.v:203280.3-203281.39" *)
  reg [15:0] _042_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _043_;
  (* src = "libresoc.v:203244.3-203245.35" *)
  reg [7:0] _044_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _045_;
  (* src = "libresoc.v:203264.3-203265.37" *)
  reg [7:0] _046_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _047_;
  (* src = "libresoc.v:203266.3-203267.37" *)
  reg [7:0] _048_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _049_;
  (* src = "libresoc.v:203268.3-203269.37" *)
  reg [7:0] _050_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _051_;
  (* src = "libresoc.v:203270.3-203271.37" *)
  reg [7:0] _052_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _053_;
  (* src = "libresoc.v:203272.3-203273.37" *)
  reg [7:0] _054_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _055_;
  (* src = "libresoc.v:203274.3-203275.37" *)
  reg [7:0] _056_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _057_;
  (* src = "libresoc.v:203246.3-203247.35" *)
  reg [7:0] _058_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _059_;
  (* src = "libresoc.v:203248.3-203249.35" *)
  reg [7:0] _060_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _061_;
  (* src = "libresoc.v:203250.3-203251.35" *)
  reg [7:0] _062_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _063_;
  (* src = "libresoc.v:203252.3-203253.35" *)
  reg [7:0] _064_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _065_;
  (* src = "libresoc.v:203254.3-203255.35" *)
  reg [7:0] _066_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _067_;
  (* src = "libresoc.v:203256.3-203257.35" *)
  reg [7:0] _068_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _069_;
  (* src = "libresoc.v:203258.3-203259.35" *)
  reg [7:0] _070_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _071_;
  (* src = "libresoc.v:203260.3-203261.35" *)
  reg [7:0] _072_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _073_;
  (* src = "libresoc.v:203262.3-203263.35" *)
  reg [7:0] _074_;
  (* src = "libresoc.v:203667.3-203716.6" *)
  reg [31:0] _075_;
  (* src = "libresoc.v:203378.3-203387.6" *)
  reg [3:0] _076_;
  (* src = "libresoc.v:203587.3-203596.6" *)
  reg [3:0] _077_;
  (* src = "libresoc.v:203607.3-203616.6" *)
  reg [3:0] _078_;
  (* src = "libresoc.v:203627.3-203636.6" *)
  reg [3:0] _079_;
  (* src = "libresoc.v:203647.3-203656.6" *)
  reg [3:0] _080_;
  (* src = "libresoc.v:203717.3-203726.6" *)
  reg [3:0] _081_;
  (* src = "libresoc.v:203737.3-203746.6" *)
  reg [3:0] _082_;
  (* src = "libresoc.v:203398.3-203407.6" *)
  reg [3:0] _083_;
  (* src = "libresoc.v:203418.3-203427.6" *)
  reg [3:0] _084_;
  (* src = "libresoc.v:203438.3-203447.6" *)
  reg [3:0] _085_;
  (* src = "libresoc.v:203467.3-203476.6" *)
  reg [3:0] _086_;
  (* src = "libresoc.v:203487.3-203496.6" *)
  reg [3:0] _087_;
  (* src = "libresoc.v:203507.3-203516.6" *)
  reg [3:0] _088_;
  (* src = "libresoc.v:203527.3-203536.6" *)
  reg [3:0] _089_;
  (* src = "libresoc.v:203547.3-203556.6" *)
  reg [3:0] _090_;
  (* src = "libresoc.v:203567.3-203576.6" *)
  reg [3:0] _091_;
  (* src = "libresoc.v:203368.3-203377.6" *)
  reg [7:0] _092_;
  (* src = "libresoc.v:203577.3-203586.6" *)
  reg [7:0] _093_;
  (* src = "libresoc.v:203597.3-203606.6" *)
  reg [7:0] _094_;
  (* src = "libresoc.v:203617.3-203626.6" *)
  reg [7:0] _095_;
  (* src = "libresoc.v:203637.3-203646.6" *)
  reg [7:0] _096_;
  (* src = "libresoc.v:203657.3-203666.6" *)
  reg [7:0] _097_;
  (* src = "libresoc.v:203727.3-203736.6" *)
  reg [7:0] _098_;
  (* src = "libresoc.v:203388.3-203397.6" *)
  reg [7:0] _099_;
  (* src = "libresoc.v:203408.3-203417.6" *)
  reg [7:0] _100_;
  (* src = "libresoc.v:203428.3-203437.6" *)
  reg [7:0] _101_;
  (* src = "libresoc.v:203448.3-203457.6" *)
  reg [7:0] _102_;
  (* src = "libresoc.v:203477.3-203486.6" *)
  reg [7:0] _103_;
  (* src = "libresoc.v:203497.3-203506.6" *)
  reg [7:0] _104_;
  (* src = "libresoc.v:203517.3-203526.6" *)
  reg [7:0] _105_;
  (* src = "libresoc.v:203537.3-203546.6" *)
  reg [7:0] _106_;
  (* src = "libresoc.v:203557.3-203566.6" *)
  reg [7:0] _107_;
  (* src = "libresoc.v:203747.3-203756.6" *)
  reg _108_;
  (* src = "libresoc.v:203019.13-203019.30" *)
  reg [7:0] _109_;
  (* src = "libresoc.v:203024.13-203024.29" *)
  reg [3:0] _110_;
  (* src = "libresoc.v:203766.3-203774.6" *)
  reg _111_;
  (* src = "libresoc.v:203033.7-203033.25" *)
  reg _112_;
  (* src = "libresoc.v:203757.3-203765.6" *)
  reg [31:0] _113_;
  (* src = "libresoc.v:203042.14-203042.35" *)
  reg [31:0] _114_;
  (* src = "libresoc.v:203458.3-203466.6" *)
  reg [15:0] _115_;
  (* src = "libresoc.v:203054.14-203054.36" *)
  reg [15:0] _116_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _117_;
  (* src = "libresoc.v:203074.13-203074.30" *)
  reg [7:0] _118_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _119_;
  (* src = "libresoc.v:203078.13-203078.31" *)
  reg [7:0] _120_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _121_;
  (* src = "libresoc.v:203082.13-203082.31" *)
  reg [7:0] _122_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _123_;
  (* src = "libresoc.v:203086.13-203086.31" *)
  reg [7:0] _124_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _125_;
  (* src = "libresoc.v:203090.13-203090.31" *)
  reg [7:0] _126_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _127_;
  (* src = "libresoc.v:203094.13-203094.31" *)
  reg [7:0] _128_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _129_;
  (* src = "libresoc.v:203098.13-203098.31" *)
  reg [7:0] _130_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _131_;
  (* src = "libresoc.v:203102.13-203102.30" *)
  reg [7:0] _132_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _133_;
  (* src = "libresoc.v:203106.13-203106.30" *)
  reg [7:0] _134_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _135_;
  (* src = "libresoc.v:203110.13-203110.30" *)
  reg [7:0] _136_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _137_;
  (* src = "libresoc.v:203114.13-203114.30" *)
  reg [7:0] _138_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _139_;
  (* src = "libresoc.v:203118.13-203118.30" *)
  reg [7:0] _140_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _141_;
  (* src = "libresoc.v:203122.13-203122.30" *)
  reg [7:0] _142_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _143_;
  (* src = "libresoc.v:203126.13-203126.30" *)
  reg [7:0] _144_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _145_;
  (* src = "libresoc.v:203130.13-203130.30" *)
  reg [7:0] _146_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _147_;
  (* src = "libresoc.v:203134.13-203134.30" *)
  reg [7:0] _148_;
  (* src = "libresoc.v:203667.3-203716.6" *)
  reg [31:0] _149_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _150_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _151_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _152_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _153_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _154_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _155_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _156_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _157_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _158_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _159_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _160_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _161_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _162_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _163_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _164_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _165_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _166_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _167_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _168_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _169_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _170_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _171_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _172_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _173_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _174_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _175_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _176_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _177_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _178_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _179_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _180_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _181_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _182_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _183_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _184_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _185_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _186_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _187_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _188_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _189_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _190_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _191_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _192_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _193_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _194_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _195_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _196_;
  (* src = "libresoc.v:203282.3-203367.6" *)
  reg [7:0] _197_;
  (* src = "libresoc.v:203139.19-203139.113" *)
  wire _198_;
  (* src = "libresoc.v:203141.19-203141.114" *)
  wire _199_;
  (* src = "libresoc.v:203143.19-203143.114" *)
  wire _200_;
  (* src = "libresoc.v:203145.19-203145.114" *)
  wire _201_;
  (* src = "libresoc.v:203147.19-203147.114" *)
  wire _202_;
  (* src = "libresoc.v:203149.19-203149.114" *)
  wire _203_;
  (* src = "libresoc.v:203151.19-203151.114" *)
  wire _204_;
  (* src = "libresoc.v:203154.19-203154.114" *)
  wire _205_;
  (* src = "libresoc.v:203156.19-203156.114" *)
  wire _206_;
  (* src = "libresoc.v:203158.19-203158.114" *)
  wire _207_;
  (* src = "libresoc.v:203161.19-203161.114" *)
  wire _208_;
  (* src = "libresoc.v:203163.19-203163.114" *)
  wire _209_;
  (* src = "libresoc.v:203165.19-203165.114" *)
  wire _210_;
  (* src = "libresoc.v:203167.19-203167.114" *)
  wire _211_;
  (* src = "libresoc.v:203169.19-203169.115" *)
  wire _212_;
  (* src = "libresoc.v:203171.19-203171.115" *)
  wire _213_;
  (* src = "libresoc.v:203173.19-203173.115" *)
  wire _214_;
  (* src = "libresoc.v:203176.19-203176.115" *)
  wire _215_;
  (* src = "libresoc.v:203178.19-203178.115" *)
  wire _216_;
  (* src = "libresoc.v:203180.19-203180.115" *)
  wire _217_;
  (* src = "libresoc.v:203183.19-203183.115" *)
  wire _218_;
  (* src = "libresoc.v:203185.19-203185.115" *)
  wire _219_;
  (* src = "libresoc.v:203187.19-203187.115" *)
  wire _220_;
  (* src = "libresoc.v:203189.19-203189.115" *)
  wire _221_;
  (* src = "libresoc.v:203191.19-203191.115" *)
  wire _222_;
  (* src = "libresoc.v:203194.19-203194.115" *)
  wire _223_;
  (* src = "libresoc.v:203218.17-203218.115" *)
  wire _224_;
  (* src = "libresoc.v:203226.18-203226.112" *)
  wire _225_;
  (* src = "libresoc.v:203228.18-203228.112" *)
  wire _226_;
  (* src = "libresoc.v:203230.18-203230.112" *)
  wire _227_;
  (* src = "libresoc.v:203232.18-203232.112" *)
  wire _228_;
  (* src = "libresoc.v:203235.18-203235.112" *)
  wire _229_;
  (* src = "libresoc.v:203237.18-203237.112" *)
  wire _230_;
  (* src = "libresoc.v:203239.18-203239.112" *)
  wire _231_;
  (* src = "libresoc.v:203153.18-203153.109" *)
  wire _232_;
  (* src = "libresoc.v:203175.18-203175.109" *)
  wire _233_;
  (* src = "libresoc.v:203192.17-203192.114" *)
  wire _234_;
  (* src = "libresoc.v:203195.19-203195.110" *)
  wire _235_;
  (* src = "libresoc.v:203197.18-203197.109" *)
  wire _236_;
  (* src = "libresoc.v:203199.18-203199.109" *)
  wire _237_;
  (* src = "libresoc.v:203201.18-203201.109" *)
  wire _238_;
  (* src = "libresoc.v:203203.18-203203.109" *)
  wire _239_;
  (* src = "libresoc.v:203205.18-203205.109" *)
  wire _240_;
  (* src = "libresoc.v:203207.17-203207.114" *)
  wire _241_;
  (* src = "libresoc.v:203208.18-203208.109" *)
  wire _242_;
  (* src = "libresoc.v:203210.18-203210.109" *)
  wire _243_;
  (* src = "libresoc.v:203212.18-203212.110" *)
  wire _244_;
  (* src = "libresoc.v:203214.18-203214.110" *)
  wire _245_;
  (* src = "libresoc.v:203216.18-203216.110" *)
  wire _246_;
  (* src = "libresoc.v:203219.18-203219.110" *)
  wire _247_;
  (* src = "libresoc.v:203221.18-203221.110" *)
  wire _248_;
  (* src = "libresoc.v:203223.18-203223.110" *)
  wire _249_;
  (* src = "libresoc.v:203234.17-203234.108" *)
  wire _250_;
  (* src = "libresoc.v:203138.18-203138.111" *)
  wire _251_;
  (* src = "libresoc.v:203140.19-203140.112" *)
  wire _252_;
  (* src = "libresoc.v:203142.19-203142.112" *)
  wire _253_;
  (* src = "libresoc.v:203144.19-203144.112" *)
  wire _254_;
  (* src = "libresoc.v:203146.19-203146.112" *)
  wire _255_;
  (* src = "libresoc.v:203148.19-203148.112" *)
  wire _256_;
  (* src = "libresoc.v:203150.19-203150.112" *)
  wire _257_;
  (* src = "libresoc.v:203152.19-203152.112" *)
  wire _258_;
  (* src = "libresoc.v:203155.19-203155.112" *)
  wire _259_;
  (* src = "libresoc.v:203157.19-203157.112" *)
  wire _260_;
  (* src = "libresoc.v:203160.19-203160.112" *)
  wire _261_;
  (* src = "libresoc.v:203162.19-203162.112" *)
  wire _262_;
  (* src = "libresoc.v:203164.19-203164.112" *)
  wire _263_;
  (* src = "libresoc.v:203166.19-203166.112" *)
  wire _264_;
  (* src = "libresoc.v:203168.19-203168.113" *)
  wire _265_;
  (* src = "libresoc.v:203170.19-203170.113" *)
  wire _266_;
  (* src = "libresoc.v:203172.19-203172.114" *)
  wire _267_;
  (* src = "libresoc.v:203174.19-203174.114" *)
  wire _268_;
  (* src = "libresoc.v:203177.19-203177.114" *)
  wire _269_;
  (* src = "libresoc.v:203179.19-203179.114" *)
  wire _270_;
  (* src = "libresoc.v:203182.19-203182.114" *)
  wire _271_;
  (* src = "libresoc.v:203184.19-203184.114" *)
  wire _272_;
  (* src = "libresoc.v:203186.19-203186.114" *)
  wire _273_;
  (* src = "libresoc.v:203188.19-203188.114" *)
  wire _274_;
  (* src = "libresoc.v:203190.19-203190.114" *)
  wire _275_;
  (* src = "libresoc.v:203193.19-203193.114" *)
  wire _276_;
  (* src = "libresoc.v:203227.18-203227.110" *)
  wire _277_;
  (* src = "libresoc.v:203229.18-203229.110" *)
  wire _278_;
  (* src = "libresoc.v:203231.18-203231.111" *)
  wire _279_;
  (* src = "libresoc.v:203233.18-203233.111" *)
  wire _280_;
  (* src = "libresoc.v:203236.18-203236.111" *)
  wire _281_;
  (* src = "libresoc.v:203238.18-203238.111" *)
  wire _282_;
  (* src = "libresoc.v:203225.18-203225.40" *)
  wire [15:0] _283_;
  (* src = "libresoc.v:203137.17-203137.114" *)
  wire [7:0] _284_;
  (* src = "libresoc.v:203159.18-203159.116" *)
  wire [7:0] _285_;
  (* src = "libresoc.v:203181.18-203181.116" *)
  wire [7:0] _286_;
  (* src = "libresoc.v:203196.19-203196.118" *)
  wire [7:0] _287_;
  (* src = "libresoc.v:203198.18-203198.116" *)
  wire [7:0] _288_;
  (* src = "libresoc.v:203200.18-203200.116" *)
  wire [7:0] _289_;
  (* src = "libresoc.v:203202.18-203202.116" *)
  wire [7:0] _290_;
  (* src = "libresoc.v:203204.18-203204.116" *)
  wire [7:0] _291_;
  (* src = "libresoc.v:203206.18-203206.116" *)
  wire [7:0] _292_;
  (* src = "libresoc.v:203209.18-203209.116" *)
  wire [7:0] _293_;
  (* src = "libresoc.v:203211.18-203211.116" *)
  wire [7:0] _294_;
  (* src = "libresoc.v:203213.18-203213.117" *)
  wire [7:0] _295_;
  (* src = "libresoc.v:203215.18-203215.117" *)
  wire [7:0] _296_;
  (* src = "libresoc.v:203217.18-203217.117" *)
  wire [7:0] _297_;
  (* src = "libresoc.v:203220.18-203220.117" *)
  wire [7:0] _298_;
  (* src = "libresoc.v:203222.18-203222.117" *)
  wire [7:0] _299_;
  (* src = "libresoc.v:203224.18-203224.117" *)
  wire [7:0] _300_;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" *)
  wire \$1 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$101 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$103 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$105 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$107 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$109 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$11 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$111 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$113 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$115 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$117 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$119 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$12 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$121 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$123 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$125 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$127 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$129 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$131 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$133 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$135 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$137 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$139 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$141 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$143 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$145 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$147 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$149 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$15 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$151 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$153 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$155 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$157 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$159 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$16 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$161 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$163 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$165 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$167 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$169 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$171 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$173 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$175 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$177 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$179 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$181 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$183 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$185 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$187 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$189 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$19 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$191 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$193 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$195 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$197 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$199 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$20 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$201 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$203 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$204 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$23 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$24 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$27 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$28 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" *)
  wire \$3 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$31 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$32 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$35 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$36 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$39 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$40 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$43 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$44 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$47 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$48 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" *)
  wire \$5 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$51 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$52 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$55 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$56 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$59 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$60 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$63 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$64 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$67 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$68 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire [7:0] \$7 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:315" *)
  wire \$71 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *)
  wire \$73 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$75 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$77 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$79 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
  wire \$8 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$81 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$83 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$85 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$87 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$89 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$91 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$93 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$95 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
  wire \$97 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *)
  wire \$99 ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:337" *)
  wire [31:0] be_in;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *)
  reg [31:0] be_out;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input clk;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *)
  reg [3:0] cur_idx9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri0;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri1;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri10;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri11;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri12;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri13;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri14;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri15;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri2;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri3;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri4;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri5;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri6;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri7;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri8;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:366" *)
  reg [7:0] cur_pri9;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:314" *)
  reg ibit;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  output [7:0] icp_o_pri;
  reg [7:0] icp_o_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  wire [7:0] \icp_o_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  output [3:0] icp_o_src;
  reg [3:0] icp_o_src;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  wire [3:0] \icp_o_src$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" *)
  wire [7:0] icp_r_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *)
  wire [3:0] icp_r_src;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output ics_wb__ack;
  reg ics_wb__ack;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  reg \ics_wb__ack$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [27:0] ics_wb__adr;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__cyc;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  output [31:0] ics_wb__dat_r;
  reg [31:0] ics_wb__dat_r;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  reg [31:0] \ics_wb__dat_r$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input [31:0] ics_wb__dat_w;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__stb;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" *)
  input ics_wb__we;
  (* src = "libresoc.v:202738.7-202738.15" *)
  reg \initial ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *)
  input [15:0] int_level_i;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" *)
  reg [15:0] int_level_l;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:263" *)
  reg [15:0] \int_level_l$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:358" *)
  wire [3:0] max_idx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:359" *)
  wire [7:0] max_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:261" *)
  wire [3:0] reg_idx;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:287" *)
  wire reg_is_config;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:288" *)
  wire reg_is_debug;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *)
  wire reg_is_xive;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:843" *)
  input rst;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *)
  wire wb_valid;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive0_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive0_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive10_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive10_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive11_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive11_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive12_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive12_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive13_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive13_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive14_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive14_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive15_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive15_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive1_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive1_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive2_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive2_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive3_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive3_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive4_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive4_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive5_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive5_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive6_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive6_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive7_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive7_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive8_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive8_pri$next ;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] xive9_pri;
  (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" *)
  reg [7:0] \xive9_pri$next ;
  assign _198_ = int_level_l[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$99 ;
  assign _199_ = int_level_l[3] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$103 ;
  assign _200_ = int_level_l[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$107 ;
  assign _201_ = int_level_l[4] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$111 ;
  assign _202_ = int_level_l[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$115 ;
  assign _203_ = int_level_l[5] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$119 ;
  assign _204_ = int_level_l[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$123 ;
  assign _205_ = int_level_l[6] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$127 ;
  assign _206_ = int_level_l[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$131 ;
  assign _207_ = int_level_l[7] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$135 ;
  assign _208_ = int_level_l[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$139 ;
  assign _209_ = int_level_l[8] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$143 ;
  assign _210_ = int_level_l[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$147 ;
  assign _211_ = int_level_l[9] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$151 ;
  assign _212_ = int_level_l[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$155 ;
  assign _213_ = int_level_l[10] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$159 ;
  assign _214_ = int_level_l[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$163 ;
  assign _215_ = int_level_l[11] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$167 ;
  assign _216_ = int_level_l[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$171 ;
  assign _217_ = int_level_l[12] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$175 ;
  assign _218_ = int_level_l[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$179 ;
  assign _219_ = int_level_l[13] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$183 ;
  assign _220_ = int_level_l[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$187 ;
  assign _221_ = int_level_l[14] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$191 ;
  assign _222_ = int_level_l[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$195 ;
  assign _223_ = int_level_l[15] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$199 ;
  assign _224_ = ics_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" *) ics_wb__stb;
  assign _225_ = wb_valid & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *) ics_wb__we;
  assign _226_ = int_level_l[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$75 ;
  assign _227_ = int_level_l[0] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$79 ;
  assign _228_ = int_level_l[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$83 ;
  assign _229_ = int_level_l[1] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$87 ;
  assign _230_ = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$91 ;
  assign _231_ = int_level_l[2] & (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *) \$95 ;
  assign _232_ = xive1_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _233_ = xive2_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _234_ = ics_wb__adr[9:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" *) 1'h0;
  assign _235_ = cur_pri15 == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _236_ = xive3_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _237_ = xive4_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _238_ = xive5_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _239_ = xive6_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _240_ = xive7_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _241_ = ics_wb__adr[9:0] == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" *) 3'h4;
  assign _242_ = xive8_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _243_ = xive9_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _244_ = xive10_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _245_ = xive11_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _246_ = xive12_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _247_ = xive13_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _248_ = xive14_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _249_ = xive15_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _250_ = xive0_pri == (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff;
  assign _251_ = xive3_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri2;
  assign _252_ = xive3_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri2;
  assign _253_ = xive4_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri3;
  assign _254_ = xive4_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri3;
  assign _255_ = xive5_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri4;
  assign _256_ = xive5_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri4;
  assign _257_ = xive6_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri5;
  assign _258_ = xive6_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri5;
  assign _259_ = xive7_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri6;
  assign _260_ = xive7_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri6;
  assign _261_ = xive8_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri7;
  assign _262_ = xive8_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri7;
  assign _263_ = xive9_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri8;
  assign _264_ = xive9_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri8;
  assign _265_ = xive10_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri9;
  assign _266_ = xive10_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri9;
  assign _267_ = xive11_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri10;
  assign _268_ = xive11_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri10;
  assign _269_ = xive12_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri11;
  assign _270_ = xive12_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri11;
  assign _271_ = xive13_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri12;
  assign _272_ = xive13_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri12;
  assign _273_ = xive14_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri13;
  assign _274_ = xive14_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri13;
  assign _275_ = xive15_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri14;
  assign _276_ = xive15_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri14;
  assign _277_ = xive0_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) max_pri;
  assign _278_ = xive0_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) max_pri;
  assign _279_ = xive1_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri0;
  assign _280_ = xive1_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri0;
  assign _281_ = xive2_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri1;
  assign _282_ = xive2_pri < (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" *) cur_pri1;
  assign _283_ = int_level_l >> (* src = "libresoc.v:203225.18-203225.40" *) reg_idx;
  assign _284_ = \$8  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive0_pri;
  assign _285_ = \$12  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive1_pri;
  assign _286_ = \$16  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive2_pri;
  assign _287_ = \$204  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : cur_pri15;
  assign _288_ = \$20  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive3_pri;
  assign _289_ = \$24  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive4_pri;
  assign _290_ = \$28  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive5_pri;
  assign _291_ = \$32  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive6_pri;
  assign _292_ = \$36  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive7_pri;
  assign _293_ = \$40  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive8_pri;
  assign _294_ = \$44  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive9_pri;
  assign _295_ = \$48  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive10_pri;
  assign _296_ = \$52  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive11_pri;
  assign _297_ = \$56  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive12_pri;
  assign _298_ = \$60  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive13_pri;
  assign _299_ = \$64  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive14_pri;
  assign _300_ = \$68  ? (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *) 8'hff : xive15_pri;
  always @* begin
    if (\initial ) begin end
    _040_ = 1'h0;
  end
  always @* begin
      \initial  <= _040_;
  end
  initial begin
  end
  always @* begin
    if (\initial ) begin end
    _109_ = 8'h00;
  end
  always @* begin
  end
  initial begin
      icp_o_pri <= _109_;
  end
  always @* begin
    if (\initial ) begin end
    _110_ = 4'h0;
  end
  always @* begin
  end
  initial begin
      icp_o_src <= _110_;
  end
  always @* begin
    if (\initial ) begin end
    _112_ = 1'h0;
  end
  always @* begin
  end
  initial begin
      ics_wb__ack <= _112_;
  end
  always @* begin
    if (\initial ) begin end
    _114_ = 32'd0;
  end
  always @* begin
  end
  initial begin
      ics_wb__dat_r <= _114_;
  end
  always @* begin
    if (\initial ) begin end
    _116_ = 16'h0000;
  end
  always @* begin
  end
  initial begin
      int_level_l <= _116_;
  end
  always @* begin
    if (\initial ) begin end
    _118_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive0_pri <= _118_;
  end
  always @* begin
    if (\initial ) begin end
    _120_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive10_pri <= _120_;
  end
  always @* begin
    if (\initial ) begin end
    _122_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive11_pri <= _122_;
  end
  always @* begin
    if (\initial ) begin end
    _124_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive12_pri <= _124_;
  end
  always @* begin
    if (\initial ) begin end
    _126_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive13_pri <= _126_;
  end
  always @* begin
    if (\initial ) begin end
    _128_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive14_pri <= _128_;
  end
  always @* begin
    if (\initial ) begin end
    _130_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive15_pri <= _130_;
  end
  always @* begin
    if (\initial ) begin end
    _132_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive1_pri <= _132_;
  end
  always @* begin
    if (\initial ) begin end
    _134_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive2_pri <= _134_;
  end
  always @* begin
    if (\initial ) begin end
    _136_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive3_pri <= _136_;
  end
  always @* begin
    if (\initial ) begin end
    _138_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive4_pri <= _138_;
  end
  always @* begin
    if (\initial ) begin end
    _140_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive5_pri <= _140_;
  end
  always @* begin
    if (\initial ) begin end
    _142_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive6_pri <= _142_;
  end
  always @* begin
    if (\initial ) begin end
    _144_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive7_pri <= _144_;
  end
  always @* begin
    if (\initial ) begin end
    _146_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive8_pri <= _146_;
  end
  always @* begin
    if (\initial ) begin end
    _148_ = 8'hff;
  end
  always @* begin
  end
  initial begin
      xive9_pri <= _148_;
  end
  always @* begin
    if (\initial ) begin end
    _035_ = cur_idx15;
  end
  always @(posedge clk) begin
      icp_o_src <= _035_;
  end
  always @* begin
    if (\initial ) begin end
    _034_ = \$203 ;
  end
  always @(posedge clk) begin
      icp_o_pri <= _034_;
  end
  always @* begin
    if (\initial ) begin end
    _044_ = \xive0_pri$next ;
  end
  always @(posedge clk) begin
      xive0_pri <= _044_;
  end
  always @* begin
    if (\initial ) begin end
    _058_ = \xive1_pri$next ;
  end
  always @(posedge clk) begin
      xive1_pri <= _058_;
  end
  always @* begin
    if (\initial ) begin end
    _060_ = \xive2_pri$next ;
  end
  always @(posedge clk) begin
      xive2_pri <= _060_;
  end
  always @* begin
    if (\initial ) begin end
    _062_ = \xive3_pri$next ;
  end
  always @(posedge clk) begin
      xive3_pri <= _062_;
  end
  always @* begin
    if (\initial ) begin end
    _064_ = \xive4_pri$next ;
  end
  always @(posedge clk) begin
      xive4_pri <= _064_;
  end
  always @* begin
    if (\initial ) begin end
    _066_ = \xive5_pri$next ;
  end
  always @(posedge clk) begin
      xive5_pri <= _066_;
  end
  always @* begin
    if (\initial ) begin end
    _068_ = \xive6_pri$next ;
  end
  always @(posedge clk) begin
      xive6_pri <= _068_;
  end
  always @* begin
    if (\initial ) begin end
    _070_ = \xive7_pri$next ;
  end
  always @(posedge clk) begin
      xive7_pri <= _070_;
  end
  always @* begin
    if (\initial ) begin end
    _072_ = \xive8_pri$next ;
  end
  always @(posedge clk) begin
      xive8_pri <= _072_;
  end
  always @* begin
    if (\initial ) begin end
    _074_ = \xive9_pri$next ;
  end
  always @(posedge clk) begin
      xive9_pri <= _074_;
  end
  always @* begin
    if (\initial ) begin end
    _046_ = \xive10_pri$next ;
  end
  always @(posedge clk) begin
      xive10_pri <= _046_;
  end
  always @* begin
    if (\initial ) begin end
    _048_ = \xive11_pri$next ;
  end
  always @(posedge clk) begin
      xive11_pri <= _048_;
  end
  always @* begin
    if (\initial ) begin end
    _050_ = \xive12_pri$next ;
  end
  always @(posedge clk) begin
      xive12_pri <= _050_;
  end
  always @* begin
    if (\initial ) begin end
    _052_ = \xive13_pri$next ;
  end
  always @(posedge clk) begin
      xive13_pri <= _052_;
  end
  always @* begin
    if (\initial ) begin end
    _054_ = \xive14_pri$next ;
  end
  always @(posedge clk) begin
      xive14_pri <= _054_;
  end
  always @* begin
    if (\initial ) begin end
    _056_ = \xive15_pri$next ;
  end
  always @(posedge clk) begin
      xive15_pri <= _056_;
  end
  always @* begin
    if (\initial ) begin end
    _037_ = \ics_wb__ack$next ;
  end
  always @(posedge clk) begin
      ics_wb__ack <= _037_;
  end
  always @* begin
    if (\initial ) begin end
    _039_ = \ics_wb__dat_r$next ;
  end
  always @(posedge clk) begin
      ics_wb__dat_r <= _039_;
  end
  always @* begin
    if (\initial ) begin end
    _042_ = \int_level_l$next ;
  end
  always @(posedge clk) begin
      int_level_l <= _042_;
  end
  always @* begin
    if (\initial ) begin end
    _043_ = _182_;
    _045_ = _183_;
    _047_ = _184_;
    _049_ = _185_;
    _051_ = _186_;
    _053_ = _187_;
    _055_ = _188_;
    _057_ = _189_;
    _059_ = _190_;
    _061_ = _191_;
    _063_ = _192_;
    _065_ = _193_;
    _067_ = _194_;
    _069_ = _195_;
    _071_ = _196_;
    _073_ = _197_;
    (* src = "libresoc.v:203283.5-203283.29" *)
    casez (\initial )
      /* src = "libresoc.v:203283.9-203283.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" *)
    casez (\$73 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _117_ = _150_;
          _119_ = _151_;
          _121_ = _152_;
          _123_ = _153_;
          _125_ = _154_;
          _127_ = _155_;
          _129_ = _156_;
          _131_ = _157_;
          _133_ = _158_;
          _135_ = _159_;
          _137_ = _160_;
          _139_ = _161_;
          _141_ = _162_;
          _143_ = _163_;
          _145_ = _164_;
          _147_ = _165_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" *)
          casez (reg_is_xive)
            /* src = "libresoc.v:0.0-0.0" */
            1'h1:
              begin
                _150_ = _166_;
                _151_ = _167_;
                _152_ = _168_;
                _153_ = _169_;
                _154_ = _170_;
                _155_ = _171_;
                _156_ = _172_;
                _157_ = _173_;
                _158_ = _174_;
                _159_ = _175_;
                _160_ = _176_;
                _161_ = _177_;
                _162_ = _178_;
                _163_ = _179_;
                _164_ = _180_;
                _165_ = _181_;
                (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" *)
                casez (reg_idx)
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h0:
                    begin
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _166_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h1:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _173_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h2:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _174_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h3:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _175_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h4:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _176_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h5:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _177_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h6:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _178_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h7:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _179_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h8:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _181_ = xive9_pri;
                      _180_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h9:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'ha:
                    begin
                      _166_ = xive0_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _167_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'hb:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _168_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'hc:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _169_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'hd:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _170_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'he:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _171_ = be_in[7:0];
                    end
                  /* src = "libresoc.v:0.0-0.0" */
                  4'h?:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                      _172_ = be_in[7:0];
                    end
                  default:
                    begin
                      _166_ = xive0_pri;
                      _167_ = xive10_pri;
                      _168_ = xive11_pri;
                      _169_ = xive12_pri;
                      _170_ = xive13_pri;
                      _171_ = xive14_pri;
                      _172_ = xive15_pri;
                      _173_ = xive1_pri;
                      _174_ = xive2_pri;
                      _175_ = xive3_pri;
                      _176_ = xive4_pri;
                      _177_ = xive5_pri;
                      _178_ = xive6_pri;
                      _179_ = xive7_pri;
                      _180_ = xive8_pri;
                      _181_ = xive9_pri;
                    end
                endcase
              end
            default:
              begin
                _150_ = xive0_pri;
                _151_ = xive10_pri;
                _152_ = xive11_pri;
                _153_ = xive12_pri;
                _154_ = xive13_pri;
                _155_ = xive14_pri;
                _156_ = xive15_pri;
                _157_ = xive1_pri;
                _158_ = xive2_pri;
                _159_ = xive3_pri;
                _160_ = xive4_pri;
                _161_ = xive5_pri;
                _162_ = xive6_pri;
                _163_ = xive7_pri;
                _164_ = xive8_pri;
                _165_ = xive9_pri;
              end
          endcase
        end
      default:
        begin
          _117_ = xive0_pri;
          _119_ = xive10_pri;
          _121_ = xive11_pri;
          _123_ = xive12_pri;
          _125_ = xive13_pri;
          _127_ = xive14_pri;
          _129_ = xive15_pri;
          _131_ = xive1_pri;
          _133_ = xive2_pri;
          _135_ = xive3_pri;
          _137_ = xive4_pri;
          _139_ = xive5_pri;
          _141_ = xive6_pri;
          _143_ = xive7_pri;
          _145_ = xive8_pri;
          _147_ = xive9_pri;
        end
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _182_ = 8'hff;
          _189_ = 8'hff;
          _190_ = 8'hff;
          _191_ = 8'hff;
          _192_ = 8'hff;
          _193_ = 8'hff;
          _194_ = 8'hff;
          _195_ = 8'hff;
          _196_ = 8'hff;
          _197_ = 8'hff;
          _183_ = 8'hff;
          _184_ = 8'hff;
          _185_ = 8'hff;
          _186_ = 8'hff;
          _187_ = 8'hff;
          _188_ = 8'hff;
        end
      default:
        begin
          _182_ = _117_;
          _183_ = _119_;
          _184_ = _121_;
          _185_ = _123_;
          _186_ = _125_;
          _187_ = _127_;
          _188_ = _129_;
          _189_ = _131_;
          _190_ = _133_;
          _191_ = _135_;
          _192_ = _137_;
          _193_ = _139_;
          _194_ = _141_;
          _195_ = _143_;
          _196_ = _145_;
          _197_ = _147_;
        end
    endcase
  end
  always @* begin
      \xive0_pri$next  <= _043_;
      \xive10_pri$next  <= _045_;
      \xive11_pri$next  <= _047_;
      \xive12_pri$next  <= _049_;
      \xive13_pri$next  <= _051_;
      \xive14_pri$next  <= _053_;
      \xive15_pri$next  <= _055_;
      \xive1_pri$next  <= _057_;
      \xive2_pri$next  <= _059_;
      \xive3_pri$next  <= _061_;
      \xive4_pri$next  <= _063_;
      \xive5_pri$next  <= _065_;
      \xive6_pri$next  <= _067_;
      \xive7_pri$next  <= _069_;
      \xive8_pri$next  <= _071_;
      \xive9_pri$next  <= _073_;
  end
  always @* begin
    if (\initial ) begin end
    _017_ = _092_;
    (* src = "libresoc.v:203369.5-203369.29" *)
    casez (\initial )
      /* src = "libresoc.v:203369.9-203369.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$77 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _092_ = xive0_pri;
        end
      default:
          _092_ = max_pri;
    endcase
  end
  always @* begin
      cur_pri0 <= _017_;
  end
  always @* begin
    if (\initial ) begin end
    _001_ = _076_;
    (* src = "libresoc.v:203379.5-203379.29" *)
    casez (\initial )
      /* src = "libresoc.v:203379.9-203379.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$81 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _076_ = 4'h0;
        end
      default:
          _076_ = max_idx;
    endcase
  end
  always @* begin
      cur_idx0 <= _001_;
  end
  always @* begin
    if (\initial ) begin end
    _024_ = _099_;
    (* src = "libresoc.v:203389.5-203389.29" *)
    casez (\initial )
      /* src = "libresoc.v:203389.9-203389.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$85 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _099_ = xive1_pri;
        end
      default:
          _099_ = cur_pri0;
    endcase
  end
  always @* begin
      cur_pri1 <= _024_;
  end
  always @* begin
    if (\initial ) begin end
    _008_ = _083_;
    (* src = "libresoc.v:203399.5-203399.29" *)
    casez (\initial )
      /* src = "libresoc.v:203399.9-203399.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$89 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _083_ = 4'h1;
        end
      default:
          _083_ = cur_idx0;
    endcase
  end
  always @* begin
      cur_idx1 <= _008_;
  end
  always @* begin
    if (\initial ) begin end
    _025_ = _100_;
    (* src = "libresoc.v:203409.5-203409.29" *)
    casez (\initial )
      /* src = "libresoc.v:203409.9-203409.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$93 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _100_ = xive2_pri;
        end
      default:
          _100_ = cur_pri1;
    endcase
  end
  always @* begin
      cur_pri2 <= _025_;
  end
  always @* begin
    if (\initial ) begin end
    _009_ = _084_;
    (* src = "libresoc.v:203419.5-203419.29" *)
    casez (\initial )
      /* src = "libresoc.v:203419.9-203419.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$97 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _084_ = 4'h2;
        end
      default:
          _084_ = cur_idx1;
    endcase
  end
  always @* begin
      cur_idx2 <= _009_;
  end
  always @* begin
    if (\initial ) begin end
    _026_ = _101_;
    (* src = "libresoc.v:203429.5-203429.29" *)
    casez (\initial )
      /* src = "libresoc.v:203429.9-203429.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$101 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _101_ = xive3_pri;
        end
      default:
          _101_ = cur_pri2;
    endcase
  end
  always @* begin
      cur_pri3 <= _026_;
  end
  always @* begin
    if (\initial ) begin end
    _010_ = _085_;
    (* src = "libresoc.v:203439.5-203439.29" *)
    casez (\initial )
      /* src = "libresoc.v:203439.9-203439.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$105 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _085_ = 4'h3;
        end
      default:
          _085_ = cur_idx2;
    endcase
  end
  always @* begin
      cur_idx3 <= _010_;
  end
  always @* begin
    if (\initial ) begin end
    _027_ = _102_;
    (* src = "libresoc.v:203449.5-203449.29" *)
    casez (\initial )
      /* src = "libresoc.v:203449.9-203449.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$109 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _102_ = xive4_pri;
        end
      default:
          _102_ = cur_pri3;
    endcase
  end
  always @* begin
      cur_pri4 <= _027_;
  end
  always @* begin
    if (\initial ) begin end
    _041_ = _115_;
    (* src = "libresoc.v:203459.5-203459.29" *)
    casez (\initial )
      /* src = "libresoc.v:203459.9-203459.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _115_ = 16'h0000;
        end
      default:
          _115_ = int_level_i;
    endcase
  end
  always @* begin
      \int_level_l$next  <= _041_;
  end
  always @* begin
    if (\initial ) begin end
    _011_ = _086_;
    (* src = "libresoc.v:203468.5-203468.29" *)
    casez (\initial )
      /* src = "libresoc.v:203468.9-203468.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$113 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _086_ = 4'h4;
        end
      default:
          _086_ = cur_idx3;
    endcase
  end
  always @* begin
      cur_idx4 <= _011_;
  end
  always @* begin
    if (\initial ) begin end
    _028_ = _103_;
    (* src = "libresoc.v:203478.5-203478.29" *)
    casez (\initial )
      /* src = "libresoc.v:203478.9-203478.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$117 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _103_ = xive5_pri;
        end
      default:
          _103_ = cur_pri4;
    endcase
  end
  always @* begin
      cur_pri5 <= _028_;
  end
  always @* begin
    if (\initial ) begin end
    _012_ = _087_;
    (* src = "libresoc.v:203488.5-203488.29" *)
    casez (\initial )
      /* src = "libresoc.v:203488.9-203488.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$121 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _087_ = 4'h5;
        end
      default:
          _087_ = cur_idx4;
    endcase
  end
  always @* begin
      cur_idx5 <= _012_;
  end
  always @* begin
    if (\initial ) begin end
    _029_ = _104_;
    (* src = "libresoc.v:203498.5-203498.29" *)
    casez (\initial )
      /* src = "libresoc.v:203498.9-203498.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$125 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _104_ = xive6_pri;
        end
      default:
          _104_ = cur_pri5;
    endcase
  end
  always @* begin
      cur_pri6 <= _029_;
  end
  always @* begin
    if (\initial ) begin end
    _013_ = _088_;
    (* src = "libresoc.v:203508.5-203508.29" *)
    casez (\initial )
      /* src = "libresoc.v:203508.9-203508.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$129 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _088_ = 4'h6;
        end
      default:
          _088_ = cur_idx5;
    endcase
  end
  always @* begin
      cur_idx6 <= _013_;
  end
  always @* begin
    if (\initial ) begin end
    _030_ = _105_;
    (* src = "libresoc.v:203518.5-203518.29" *)
    casez (\initial )
      /* src = "libresoc.v:203518.9-203518.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$133 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _105_ = xive7_pri;
        end
      default:
          _105_ = cur_pri6;
    endcase
  end
  always @* begin
      cur_pri7 <= _030_;
  end
  always @* begin
    if (\initial ) begin end
    _014_ = _089_;
    (* src = "libresoc.v:203528.5-203528.29" *)
    casez (\initial )
      /* src = "libresoc.v:203528.9-203528.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$137 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _089_ = 4'h7;
        end
      default:
          _089_ = cur_idx6;
    endcase
  end
  always @* begin
      cur_idx7 <= _014_;
  end
  always @* begin
    if (\initial ) begin end
    _031_ = _106_;
    (* src = "libresoc.v:203538.5-203538.29" *)
    casez (\initial )
      /* src = "libresoc.v:203538.9-203538.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$141 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _106_ = xive8_pri;
        end
      default:
          _106_ = cur_pri7;
    endcase
  end
  always @* begin
      cur_pri8 <= _031_;
  end
  always @* begin
    if (\initial ) begin end
    _015_ = _090_;
    (* src = "libresoc.v:203548.5-203548.29" *)
    casez (\initial )
      /* src = "libresoc.v:203548.9-203548.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$145 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _090_ = 4'h8;
        end
      default:
          _090_ = cur_idx7;
    endcase
  end
  always @* begin
      cur_idx8 <= _015_;
  end
  always @* begin
    if (\initial ) begin end
    _032_ = _107_;
    (* src = "libresoc.v:203558.5-203558.29" *)
    casez (\initial )
      /* src = "libresoc.v:203558.9-203558.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$149 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _107_ = xive9_pri;
        end
      default:
          _107_ = cur_pri8;
    endcase
  end
  always @* begin
      cur_pri9 <= _032_;
  end
  always @* begin
    if (\initial ) begin end
    _016_ = _091_;
    (* src = "libresoc.v:203568.5-203568.29" *)
    casez (\initial )
      /* src = "libresoc.v:203568.9-203568.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$153 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _091_ = 4'h9;
        end
      default:
          _091_ = cur_idx8;
    endcase
  end
  always @* begin
      cur_idx9 <= _016_;
  end
  always @* begin
    if (\initial ) begin end
    _018_ = _093_;
    (* src = "libresoc.v:203578.5-203578.29" *)
    casez (\initial )
      /* src = "libresoc.v:203578.9-203578.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$157 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _093_ = xive10_pri;
        end
      default:
          _093_ = cur_pri9;
    endcase
  end
  always @* begin
      cur_pri10 <= _018_;
  end
  always @* begin
    if (\initial ) begin end
    _002_ = _077_;
    (* src = "libresoc.v:203588.5-203588.29" *)
    casez (\initial )
      /* src = "libresoc.v:203588.9-203588.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$161 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _077_ = 4'ha;
        end
      default:
          _077_ = cur_idx9;
    endcase
  end
  always @* begin
      cur_idx10 <= _002_;
  end
  always @* begin
    if (\initial ) begin end
    _019_ = _094_;
    (* src = "libresoc.v:203598.5-203598.29" *)
    casez (\initial )
      /* src = "libresoc.v:203598.9-203598.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$165 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _094_ = xive11_pri;
        end
      default:
          _094_ = cur_pri10;
    endcase
  end
  always @* begin
      cur_pri11 <= _019_;
  end
  always @* begin
    if (\initial ) begin end
    _003_ = _078_;
    (* src = "libresoc.v:203608.5-203608.29" *)
    casez (\initial )
      /* src = "libresoc.v:203608.9-203608.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$169 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _078_ = 4'hb;
        end
      default:
          _078_ = cur_idx10;
    endcase
  end
  always @* begin
      cur_idx11 <= _003_;
  end
  always @* begin
    if (\initial ) begin end
    _020_ = _095_;
    (* src = "libresoc.v:203618.5-203618.29" *)
    casez (\initial )
      /* src = "libresoc.v:203618.9-203618.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$173 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _095_ = xive12_pri;
        end
      default:
          _095_ = cur_pri11;
    endcase
  end
  always @* begin
      cur_pri12 <= _020_;
  end
  always @* begin
    if (\initial ) begin end
    _004_ = _079_;
    (* src = "libresoc.v:203628.5-203628.29" *)
    casez (\initial )
      /* src = "libresoc.v:203628.9-203628.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$177 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _079_ = 4'hc;
        end
      default:
          _079_ = cur_idx11;
    endcase
  end
  always @* begin
      cur_idx12 <= _004_;
  end
  always @* begin
    if (\initial ) begin end
    _021_ = _096_;
    (* src = "libresoc.v:203638.5-203638.29" *)
    casez (\initial )
      /* src = "libresoc.v:203638.9-203638.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$181 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _096_ = xive13_pri;
        end
      default:
          _096_ = cur_pri12;
    endcase
  end
  always @* begin
      cur_pri13 <= _021_;
  end
  always @* begin
    if (\initial ) begin end
    _005_ = _080_;
    (* src = "libresoc.v:203648.5-203648.29" *)
    casez (\initial )
      /* src = "libresoc.v:203648.9-203648.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$185 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _080_ = 4'hd;
        end
      default:
          _080_ = cur_idx12;
    endcase
  end
  always @* begin
      cur_idx13 <= _005_;
  end
  always @* begin
    if (\initial ) begin end
    _022_ = _097_;
    (* src = "libresoc.v:203658.5-203658.29" *)
    casez (\initial )
      /* src = "libresoc.v:203658.9-203658.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$189 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _097_ = xive14_pri;
        end
      default:
          _097_ = cur_pri13;
    endcase
  end
  always @* begin
      cur_pri14 <= _022_;
  end
  always @* begin
    if (\initial ) begin end
    _000_ = _075_;
    (* src = "libresoc.v:203668.5-203668.29" *)
    casez (\initial )
      /* src = "libresoc.v:203668.9-203668.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" *)
    casez ({ reg_is_debug, reg_is_config, reg_is_xive })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _075_ = _149_;
          (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" *)
          casez (reg_idx)
            /* src = "libresoc.v:0.0-0.0" */
            4'h0:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$7  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h1:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$11  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h2:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$15  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h3:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$19  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h4:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$23  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h5:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$27  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h6:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$31  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h7:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$35  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h8:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$39  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h9:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$43  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'ha:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$47  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'hb:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$51  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'hc:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$55  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'hd:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$59  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'he:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$63  };
              end
            /* src = "libresoc.v:0.0-0.0" */
            4'h?:
              begin
                _149_ = { ibit, 1'h0, ibit, 21'h000000, \$67  };
              end
            default:
                _149_ = 32'd0;
          endcase
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b?1?:
        begin
          _075_ = 32'd134217744;
        end
      /* src = "libresoc.v:0.0-0.0" */
      3'b1??:
        begin
          _075_ = { icp_r_src, 20'h00000, icp_r_pri };
        end
      default:
          _075_ = 32'd0;
    endcase
  end
  always @* begin
      be_out <= _000_;
  end
  always @* begin
    if (\initial ) begin end
    _006_ = _081_;
    (* src = "libresoc.v:203718.5-203718.29" *)
    casez (\initial )
      /* src = "libresoc.v:203718.9-203718.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$193 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _081_ = 4'he;
        end
      default:
          _081_ = cur_idx13;
    endcase
  end
  always @* begin
      cur_idx14 <= _006_;
  end
  always @* begin
    if (\initial ) begin end
    _023_ = _098_;
    (* src = "libresoc.v:203728.5-203728.29" *)
    casez (\initial )
      /* src = "libresoc.v:203728.9-203728.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$197 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _098_ = xive15_pri;
        end
      default:
          _098_ = cur_pri14;
    endcase
  end
  always @* begin
      cur_pri15 <= _023_;
  end
  always @* begin
    if (\initial ) begin end
    _007_ = _082_;
    (* src = "libresoc.v:203738.5-203738.29" *)
    casez (\initial )
      /* src = "libresoc.v:203738.9-203738.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" *)
    casez (\$201 )
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _082_ = 4'hf;
        end
      default:
          _082_ = cur_idx14;
    endcase
  end
  always @* begin
      cur_idx15 <= _007_;
  end
  always @* begin
    if (\initial ) begin end
    _033_ = _108_;
    (* src = "libresoc.v:203748.5-203748.29" *)
    casez (\initial )
      /* src = "libresoc.v:203748.9-203748.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" *)
    casez ({ reg_is_debug, reg_is_config, reg_is_xive })
      /* src = "libresoc.v:0.0-0.0" */
      3'b??1:
        begin
          _108_ = \$71 ;
        end
      default:
          _108_ = 1'h0;
    endcase
  end
  always @* begin
      ibit <= _033_;
  end
  always @* begin
    if (\initial ) begin end
    _038_ = _113_;
    (* src = "libresoc.v:203758.5-203758.29" *)
    casez (\initial )
      /* src = "libresoc.v:203758.9-203758.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _113_ = 32'd0;
        end
      default:
          _113_ = { be_out[7:0], be_out[15:8], be_out[23:16], be_out[31:24] };
    endcase
  end
  always @* begin
      \ics_wb__dat_r$next  <= _038_;
  end
  always @* begin
    if (\initial ) begin end
    _036_ = _111_;
    (* src = "libresoc.v:203767.5-203767.29" *)
    casez (\initial )
      /* src = "libresoc.v:203767.9-203767.17" */
      1'h1:
          /* empty */;
      default:
          /* empty */;
    endcase
    (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" *)
    casez (rst)
      /* src = "libresoc.v:0.0-0.0" */
      1'h1:
        begin
          _111_ = 1'h0;
        end
      default:
          _111_ = wb_valid;
    endcase
  end
  always @* begin
      \ics_wb__ack$next  <= _036_;
  end
  assign \$7  = _284_;
  assign \$99  = _251_;
  assign \$101  = _198_;
  assign \$103  = _252_;
  assign \$105  = _199_;
  assign \$107  = _253_;
  assign \$109  = _200_;
  assign \$111  = _254_;
  assign \$113  = _201_;
  assign \$115  = _255_;
  assign \$117  = _202_;
  assign \$119  = _256_;
  assign \$121  = _203_;
  assign \$123  = _257_;
  assign \$125  = _204_;
  assign \$127  = _258_;
  assign \$12  = _232_;
  assign \$129  = _205_;
  assign \$131  = _259_;
  assign \$133  = _206_;
  assign \$135  = _260_;
  assign \$137  = _207_;
  assign \$11  = _285_;
  assign \$139  = _261_;
  assign \$141  = _208_;
  assign \$143  = _262_;
  assign \$145  = _209_;
  assign \$147  = _263_;
  assign \$149  = _210_;
  assign \$151  = _264_;
  assign \$153  = _211_;
  assign \$155  = _265_;
  assign \$157  = _212_;
  assign \$159  = _266_;
  assign \$161  = _213_;
  assign \$163  = _267_;
  assign \$165  = _214_;
  assign \$167  = _268_;
  assign \$16  = _233_;
  assign \$169  = _215_;
  assign \$171  = _269_;
  assign \$173  = _216_;
  assign \$175  = _270_;
  assign \$177  = _217_;
  assign \$15  = _286_;
  assign \$179  = _271_;
  assign \$181  = _218_;
  assign \$183  = _272_;
  assign \$185  = _219_;
  assign \$187  = _273_;
  assign \$189  = _220_;
  assign \$191  = _274_;
  assign \$193  = _221_;
  assign \$195  = _275_;
  assign \$197  = _222_;
  assign \$1  = _234_;
  assign \$199  = _276_;
  assign \$201  = _223_;
  assign \$204  = _235_;
  assign \$203  = _287_;
  assign \$20  = _236_;
  assign \$19  = _288_;
  assign \$24  = _237_;
  assign \$23  = _289_;
  assign \$28  = _238_;
  assign \$27  = _290_;
  assign \$32  = _239_;
  assign \$31  = _291_;
  assign \$36  = _240_;
  assign \$35  = _292_;
  assign \$3  = _241_;
  assign \$40  = _242_;
  assign \$39  = _293_;
  assign \$44  = _243_;
  assign \$43  = _294_;
  assign \$48  = _244_;
  assign \$47  = _295_;
  assign \$52  = _245_;
  assign \$51  = _296_;
  assign \$56  = _246_;
  assign \$55  = _297_;
  assign \$5  = _224_;
  assign \$60  = _247_;
  assign \$59  = _298_;
  assign \$64  = _248_;
  assign \$63  = _299_;
  assign \$68  = _249_;
  assign \$67  = _300_;
  assign \$71  = _283_[0];
  assign \$73  = _225_;
  assign \$75  = _277_;
  assign \$77  = _226_;
  assign \$79  = _278_;
  assign \$81  = _227_;
  assign \$83  = _279_;
  assign \$85  = _228_;
  assign \$87  = _280_;
  assign \$8  = _250_;
  assign \$89  = _229_;
  assign \$91  = _281_;
  assign \$93  = _230_;
  assign \$95  = _282_;
  assign \$97  = _231_;
  assign icp_r_pri = \$203 ;
  assign icp_r_src = cur_idx15;
  assign max_idx = 4'h0;
  assign max_pri = 8'hff;
  assign { \icp_o_pri$next , \icp_o_src$next  } = { icp_r_pri, icp_r_src };
  assign be_in = { ics_wb__dat_w[7:0], ics_wb__dat_w[15:8], ics_wb__dat_w[23:16], ics_wb__dat_w[31:24] };
  assign wb_valid = \$5 ;
  assign reg_idx = ics_wb__adr[3:0];
  assign reg_is_debug = \$3 ;
  assign reg_is_config = \$1 ;
  assign reg_is_xive = ics_wb__adr[9];
endmodule
